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-rw-r--r--arch/arm/Kconfig11
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/mach-ixp23xx/Kconfig25
-rw-r--r--arch/arm/mach-ixp23xx/Makefile11
-rw-r--r--arch/arm/mach-ixp23xx/Makefile.boot2
-rw-r--r--arch/arm/mach-ixp23xx/core.c431
-rw-r--r--arch/arm/mach-ixp23xx/espresso.c69
-rw-r--r--arch/arm/mach-ixp23xx/ixdp2351.c325
-rw-r--r--arch/arm/mach-ixp23xx/pci.c275
-rw-r--r--arch/arm/mach-ixp23xx/roadrunner.c164
-rw-r--r--include/asm-arm/arch-ixp23xx/debug-macro.S23
-rw-r--r--include/asm-arm/arch-ixp23xx/dma.h3
-rw-r--r--include/asm-arm/arch-ixp23xx/entry-macro.S31
-rw-r--r--include/asm-arm/arch-ixp23xx/hardware.h37
-rw-r--r--include/asm-arm/arch-ixp23xx/io.h54
-rw-r--r--include/asm-arm/arch-ixp23xx/irqs.h223
-rw-r--r--include/asm-arm/arch-ixp23xx/ixdp2351.h89
-rw-r--r--include/asm-arm/arch-ixp23xx/ixp23xx.h306
-rw-r--r--include/asm-arm/arch-ixp23xx/memory.h46
-rw-r--r--include/asm-arm/arch-ixp23xx/platform.h31
-rw-r--r--include/asm-arm/arch-ixp23xx/system.h33
-rw-r--r--include/asm-arm/arch-ixp23xx/time.h3
-rw-r--r--include/asm-arm/arch-ixp23xx/timex.h7
-rw-r--r--include/asm-arm/arch-ixp23xx/uncompress.h45
-rw-r--r--include/asm-arm/arch-ixp23xx/vmalloc.h10
25 files changed, 2254 insertions, 1 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0dd24ebdf6ac..427c72140110 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -148,6 +148,12 @@ config ARCH_IXP2000
148 help 148 help
149 Support for Intel's IXP2400/2800 (XScale) family of processors. 149 Support for Intel's IXP2400/2800 (XScale) family of processors.
150 150
151config ARCH_IXP23XX
152 bool "IXP23XX-based"
153 select PCI
154 help
155 Support for Intel's IXP23xx (XScale) family of processors.
156
151config ARCH_L7200 157config ARCH_L7200
152 bool "LinkUp-L7200" 158 bool "LinkUp-L7200"
153 select FIQ 159 select FIQ
@@ -269,6 +275,8 @@ source "arch/arm/mach-ixp4xx/Kconfig"
269 275
270source "arch/arm/mach-ixp2000/Kconfig" 276source "arch/arm/mach-ixp2000/Kconfig"
271 277
278source "arch/arm/mach-ixp23xx/Kconfig"
279
272source "arch/arm/mach-pxa/Kconfig" 280source "arch/arm/mach-pxa/Kconfig"
273 281
274source "arch/arm/mach-sa1100/Kconfig" 282source "arch/arm/mach-sa1100/Kconfig"
@@ -787,7 +795,8 @@ source "drivers/acorn/block/Kconfig"
787 795
788if PCMCIA || ARCH_CLPS7500 || ARCH_IOP3XX || ARCH_IXP4XX \ 796if PCMCIA || ARCH_CLPS7500 || ARCH_IOP3XX || ARCH_IXP4XX \
789 || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \ 797 || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \
790 || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE 798 || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE \
799 || ARCH_IXP23XX
791source "drivers/ide/Kconfig" 800source "drivers/ide/Kconfig"
792endif 801endif
793 802
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0f571d3d2fa4..ce3e804ea0f3 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -98,6 +98,7 @@ endif
98 machine-$(CONFIG_ARCH_IOP3XX) := iop3xx 98 machine-$(CONFIG_ARCH_IOP3XX) := iop3xx
99 machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx 99 machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
100 machine-$(CONFIG_ARCH_IXP2000) := ixp2000 100 machine-$(CONFIG_ARCH_IXP2000) := ixp2000
101 machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
101 machine-$(CONFIG_ARCH_OMAP1) := omap1 102 machine-$(CONFIG_ARCH_OMAP1) := omap1
102 machine-$(CONFIG_ARCH_OMAP2) := omap2 103 machine-$(CONFIG_ARCH_OMAP2) := omap2
103 incdir-$(CONFIG_ARCH_OMAP) := omap 104 incdir-$(CONFIG_ARCH_OMAP) := omap
diff --git a/arch/arm/mach-ixp23xx/Kconfig b/arch/arm/mach-ixp23xx/Kconfig
new file mode 100644
index 000000000000..982670ec3866
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/Kconfig
@@ -0,0 +1,25 @@
1if ARCH_IXP23XX
2
3config ARCH_SUPPORTS_BIG_ENDIAN
4 bool
5 default y
6
7menu "Intel IXP23xx Implementation Options"
8
9comment "IXP23xx Platforms"
10
11config MACH_ESPRESSO
12 bool "Support IP Fabrics Double Espresso platform"
13 help
14
15config MACH_IXDP2351
16 bool "Support Intel IXDP2351 platform"
17 help
18
19config MACH_ROADRUNNER
20 bool "Support ADI RoadRunner platform"
21 help
22
23endmenu
24
25endif
diff --git a/arch/arm/mach-ixp23xx/Makefile b/arch/arm/mach-ixp23xx/Makefile
new file mode 100644
index 000000000000..288b371b6d03
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for the linux kernel.
3#
4obj-y := core.o pci.o
5obj-m :=
6obj-n :=
7obj- :=
8
9obj-$(CONFIG_MACH_ESPRESSO) += espresso.o
10obj-$(CONFIG_MACH_IXDP2351) += ixdp2351.o
11obj-$(CONFIG_MACH_ROADRUNNER) += roadrunner.o
diff --git a/arch/arm/mach-ixp23xx/Makefile.boot b/arch/arm/mach-ixp23xx/Makefile.boot
new file mode 100644
index 000000000000..d5561ad15bad
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/Makefile.boot
@@ -0,0 +1,2 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
new file mode 100644
index 000000000000..092ee12ced42
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -0,0 +1,431 @@
1/*
2 * arch/arm/mach-ixp23xx/core.c
3 *
4 * Core routines for IXP23xx chips
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * Based on 2.4 code Copyright 2004 (c) Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/config.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/spinlock.h>
21#include <linux/sched.h>
22#include <linux/interrupt.h>
23#include <linux/serial.h>
24#include <linux/tty.h>
25#include <linux/bitops.h>
26#include <linux/serial.h>
27#include <linux/serial_8250.h>
28#include <linux/serial_core.h>
29#include <linux/device.h>
30#include <linux/mm.h>
31#include <linux/time.h>
32#include <linux/timex.h>
33
34#include <asm/types.h>
35#include <asm/setup.h>
36#include <asm/memory.h>
37#include <asm/hardware.h>
38#include <asm/mach-types.h>
39#include <asm/irq.h>
40#include <asm/system.h>
41#include <asm/tlbflush.h>
42#include <asm/pgtable.h>
43
44#include <asm/mach/map.h>
45#include <asm/mach/time.h>
46#include <asm/mach/irq.h>
47#include <asm/mach/arch.h>
48
49
50/*************************************************************************
51 * Chip specific mappings shared by all IXP23xx systems
52 *************************************************************************/
53static struct map_desc ixp23xx_io_desc[] __initdata = {
54 { /* XSI-CPP CSRs */
55 .virtual = IXP23XX_XSI2CPP_CSR_VIRT,
56 .pfn = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS),
57 .length = IXP23XX_XSI2CPP_CSR_SIZE,
58 .type = MT_DEVICE,
59 }, { /* Expansion Bus Config */
60 .virtual = IXP23XX_EXP_CFG_VIRT,
61 .pfn = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS),
62 .length = IXP23XX_EXP_CFG_SIZE,
63 .type = MT_DEVICE,
64 }, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */
65 .virtual = IXP23XX_PERIPHERAL_VIRT,
66 .pfn = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS),
67 .length = IXP23XX_PERIPHERAL_SIZE,
68 .type = MT_DEVICE,
69 }, { /* CAP CSRs */
70 .virtual = IXP23XX_CAP_CSR_VIRT,
71 .pfn = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS),
72 .length = IXP23XX_CAP_CSR_SIZE,
73 .type = MT_DEVICE,
74 }, { /* MSF CSRs */
75 .virtual = IXP23XX_MSF_CSR_VIRT,
76 .pfn = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
77 .length = IXP23XX_MSF_CSR_SIZE,
78 .type = MT_DEVICE,
79 }, { /* PCI I/O Space */
80 .virtual = IXP23XX_PCI_IO_VIRT,
81 .pfn = __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
82 .length = IXP23XX_PCI_IO_SIZE,
83 .type = MT_DEVICE,
84 }, { /* PCI Config Space */
85 .virtual = IXP23XX_PCI_CFG_VIRT,
86 .pfn = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
87 .length = IXP23XX_PCI_CFG_SIZE,
88 .type = MT_DEVICE,
89 }, { /* PCI local CFG CSRs */
90 .virtual = IXP23XX_PCI_CREG_VIRT,
91 .pfn = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS),
92 .length = IXP23XX_PCI_CREG_SIZE,
93 .type = MT_DEVICE,
94 }, { /* PCI MEM Space */
95 .virtual = IXP23XX_PCI_MEM_VIRT,
96 .pfn = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS),
97 .length = IXP23XX_PCI_MEM_SIZE,
98 .type = MT_DEVICE,
99 }
100};
101
102void __init ixp23xx_map_io(void)
103{
104 iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
105}
106
107
108/***************************************************************************
109 * IXP23xx Interrupt Handling
110 ***************************************************************************/
111enum ixp23xx_irq_type {
112 IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE
113};
114
115static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
116
117static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
118{
119 int line = irq - IRQ_IXP23XX_GPIO6 + 6;
120 u32 int_style;
121 enum ixp23xx_irq_type irq_type;
122 volatile u32 *int_reg;
123
124 /*
125 * Only GPIOs 6-15 are wired to interrupts on IXP23xx
126 */
127 if (line < 6 || line > 15)
128 return -EINVAL;
129
130 switch (type) {
131 case IRQT_BOTHEDGE:
132 int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
133 irq_type = IXP23XX_IRQ_EDGE;
134 break;
135 case IRQT_RISING:
136 int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
137 irq_type = IXP23XX_IRQ_EDGE;
138 break;
139 case IRQT_FALLING:
140 int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
141 irq_type = IXP23XX_IRQ_EDGE;
142 break;
143 case IRQT_HIGH:
144 int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
145 irq_type = IXP23XX_IRQ_LEVEL;
146 break;
147 case IRQT_LOW:
148 int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
149 irq_type = IXP23XX_IRQ_LEVEL;
150 break;
151 default:
152 return -EINVAL;
153 }
154
155 ixp23xx_config_irq(irq, irq_type);
156
157 if (line >= 8) { /* pins 8-15 */
158 line -= 8;
159 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R;
160 } else { /* pins 0-7 */
161 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R;
162 }
163
164 /*
165 * Clear pending interrupts
166 */
167 *IXP23XX_GPIO_GPISR = (1 << line);
168
169 /* Clear the style for the appropriate pin */
170 *int_reg &= ~(IXP23XX_GPIO_STYLE_MASK <<
171 (line * IXP23XX_GPIO_STYLE_SIZE));
172
173 /* Set the new style */
174 *int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE));
175
176 return 0;
177}
178
179static void ixp23xx_irq_mask(unsigned int irq)
180{
181 volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
182
183 *intr_reg &= ~(1 << (irq % 32));
184}
185
186static void ixp23xx_irq_ack(unsigned int irq)
187{
188 int line = irq - IRQ_IXP23XX_GPIO6 + 6;
189
190 if ((line < 6) || (line > 15))
191 return;
192
193 *IXP23XX_GPIO_GPISR = (1 << line);
194}
195
196/*
197 * Level triggered interrupts on GPIO lines can only be cleared when the
198 * interrupt condition disappears.
199 */
200static void ixp23xx_irq_level_unmask(unsigned int irq)
201{
202 volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
203
204 ixp23xx_irq_ack(irq);
205
206 *intr_reg |= (1 << (irq % 32));
207}
208
209static void ixp23xx_irq_edge_unmask(unsigned int irq)
210{
211 volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
212
213 *intr_reg |= (1 << (irq % 32));
214}
215
216static struct irqchip ixp23xx_irq_level_chip = {
217 .ack = ixp23xx_irq_mask,
218 .mask = ixp23xx_irq_mask,
219 .unmask = ixp23xx_irq_level_unmask,
220 .set_type = ixp23xx_irq_set_type
221};
222
223static struct irqchip ixp23xx_irq_edge_chip = {
224 .ack = ixp23xx_irq_ack,
225 .mask = ixp23xx_irq_mask,
226 .unmask = ixp23xx_irq_edge_unmask,
227 .set_type = ixp23xx_irq_set_type
228};
229
230static void ixp23xx_pci_irq_mask(unsigned int irq)
231{
232 *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
233}
234
235static void ixp23xx_pci_irq_unmask(unsigned int irq)
236{
237 *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
238}
239
240/*
241 * TODO: Should this just be done at ASM level?
242 */
243static void pci_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
244{
245 u32 pci_interrupt;
246 unsigned int irqno;
247 struct irqdesc *int_desc;
248
249 pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
250
251 desc->chip->ack(irq);
252
253 /* See which PCI_INTA, or PCI_INTB interrupted */
254 if (pci_interrupt & (1 << 26)) {
255 irqno = IRQ_IXP23XX_INTB;
256 } else if (pci_interrupt & (1 << 27)) {
257 irqno = IRQ_IXP23XX_INTA;
258 } else {
259 BUG();
260 }
261
262 int_desc = irq_desc + irqno;
263 int_desc->handle(irqno, int_desc, regs);
264
265 desc->chip->unmask(irq);
266}
267
268static struct irqchip ixp23xx_pci_irq_chip = {
269 .ack = ixp23xx_pci_irq_mask,
270 .mask = ixp23xx_pci_irq_mask,
271 .unmask = ixp23xx_pci_irq_unmask
272};
273
274static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
275{
276 switch (type) {
277 case IXP23XX_IRQ_LEVEL:
278 set_irq_chip(irq, &ixp23xx_irq_level_chip);
279 set_irq_handler(irq, do_level_IRQ);
280 break;
281 case IXP23XX_IRQ_EDGE:
282 set_irq_chip(irq, &ixp23xx_irq_edge_chip);
283 set_irq_handler(irq, do_edge_IRQ);
284 break;
285 }
286 set_irq_flags(irq, IRQF_VALID);
287}
288
289void __init ixp23xx_init_irq(void)
290{
291 int irq;
292
293 /* Route everything to IRQ */
294 *IXP23XX_INTR_SEL1 = 0x0;
295 *IXP23XX_INTR_SEL2 = 0x0;
296 *IXP23XX_INTR_SEL3 = 0x0;
297 *IXP23XX_INTR_SEL4 = 0x0;
298
299 /* Mask all sources */
300 *IXP23XX_INTR_EN1 = 0x0;
301 *IXP23XX_INTR_EN2 = 0x0;
302 *IXP23XX_INTR_EN3 = 0x0;
303 *IXP23XX_INTR_EN4 = 0x0;
304
305 /*
306 * Configure all IRQs for level-sensitive operation
307 */
308 for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
309 ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
310 }
311
312 for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
313 set_irq_chip(irq, &ixp23xx_pci_irq_chip);
314 set_irq_handler(irq, do_level_IRQ);
315 set_irq_flags(irq, IRQF_VALID);
316 }
317
318 set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
319}
320
321
322/*************************************************************************
323 * Timer-tick functions for IXP23xx
324 *************************************************************************/
325#define CLOCK_TICKS_PER_USEC CLOCK_TICK_RATE / (USEC_PER_SEC)
326
327static unsigned long next_jiffy_time;
328
329static unsigned long
330ixp23xx_gettimeoffset(void)
331{
332 unsigned long elapsed;
333
334 elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH);
335
336 return elapsed / CLOCK_TICKS_PER_USEC;
337}
338
339static irqreturn_t
340ixp23xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
341{
342 /* Clear Pending Interrupt by writing '1' to it */
343 *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
344 while ((*IXP23XX_TIMER_CONT - next_jiffy_time) > LATCH) {
345 timer_tick(regs);
346 next_jiffy_time += LATCH;
347 }
348
349 return IRQ_HANDLED;
350}
351
352static struct irqaction ixp23xx_timer_irq = {
353 .name = "IXP23xx Timer Tick",
354 .handler = ixp23xx_timer_interrupt,
355 .flags = SA_INTERRUPT | SA_TIMER,
356};
357
358void __init ixp23xx_init_timer(void)
359{
360 /* Clear Pending Interrupt by writing '1' to it */
361 *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
362
363 /* Setup the Timer counter value */
364 *IXP23XX_TIMER1_RELOAD =
365 (LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE;
366
367 *IXP23XX_TIMER_CONT = 0;
368 next_jiffy_time = LATCH;
369
370 /* Connect the interrupt handler and enable the interrupt */
371 setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq);
372}
373
374struct sys_timer ixp23xx_timer = {
375 .init = ixp23xx_init_timer,
376 .offset = ixp23xx_gettimeoffset,
377};
378
379
380/*************************************************************************
381 * IXP23xx Platform Initializaion
382 *************************************************************************/
383static struct resource ixp23xx_uart_resources[] = {
384 {
385 .start = IXP23XX_UART1_PHYS,
386 .end = IXP23XX_UART1_PHYS + 0x0fff,
387 .flags = IORESOURCE_MEM
388 }, {
389 .start = IXP23XX_UART2_PHYS,
390 .end = IXP23XX_UART2_PHYS + 0x0fff,
391 .flags = IORESOURCE_MEM
392 }
393};
394
395static struct plat_serial8250_port ixp23xx_uart_data[] = {
396 {
397 .mapbase = IXP23XX_UART1_PHYS,
398 .membase = (char *)(IXP23XX_UART1_VIRT + 3),
399 .irq = IRQ_IXP23XX_UART1,
400 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
401 .iotype = UPIO_MEM,
402 .regshift = 2,
403 .uartclk = IXP23XX_UART_XTAL,
404 }, {
405 .mapbase = IXP23XX_UART2_PHYS,
406 .membase = (char *)(IXP23XX_UART2_VIRT + 3),
407 .irq = IRQ_IXP23XX_UART2,
408 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
409 .iotype = UPIO_MEM,
410 .regshift = 2,
411 .uartclk = IXP23XX_UART_XTAL,
412 },
413 { },
414};
415
416static struct platform_device ixp23xx_uart = {
417 .name = "serial8250",
418 .id = 0,
419 .dev.platform_data = ixp23xx_uart_data,
420 .num_resources = 2,
421 .resource = ixp23xx_uart_resources,
422};
423
424static struct platform_device *ixp23xx_devices[] __initdata = {
425 &ixp23xx_uart,
426};
427
428void __init ixp23xx_sys_init(void)
429{
430 platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
431}
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
new file mode 100644
index 000000000000..2327c9790416
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/espresso.c
@@ -0,0 +1,69 @@
1/*
2 * arch/arm/mach-ixp23xx/espresso.c
3 *
4 * Double Espresso-specific routines
5 *
6 * Author: Lennert Buytenhek <buytenh@wantstofly.org>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/config.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/spinlock.h>
17#include <linux/sched.h>
18#include <linux/interrupt.h>
19#include <linux/serial.h>
20#include <linux/tty.h>
21#include <linux/bitops.h>
22#include <linux/ioport.h>
23#include <linux/serial.h>
24#include <linux/serial_8250.h>
25#include <linux/serial_core.h>
26#include <linux/device.h>
27#include <linux/mm.h>
28#include <linux/pci.h>
29#include <linux/mtd/physmap.h>
30
31#include <asm/types.h>
32#include <asm/setup.h>
33#include <asm/memory.h>
34#include <asm/hardware.h>
35#include <asm/mach-types.h>
36#include <asm/irq.h>
37#include <asm/system.h>
38#include <asm/tlbflush.h>
39#include <asm/pgtable.h>
40
41#include <asm/mach/map.h>
42#include <asm/mach/irq.h>
43#include <asm/mach/arch.h>
44#include <asm/mach/irq.h>
45#include <asm/mach/pci.h>
46
47static void __init espresso_init(void)
48{
49 physmap_configure(0x90000000, 0x02000000, 2, NULL);
50
51 /*
52 * Mark flash as writeable.
53 */
54 IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
55 IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
56
57 ixp23xx_sys_init();
58}
59
60MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso")
61 /* Maintainer: Lennert Buytenhek */
62 .phys_io = IXP23XX_PERIPHERAL_PHYS,
63 .io_pg_offst = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
64 .map_io = ixp23xx_map_io,
65 .init_irq = ixp23xx_init_irq,
66 .timer = &ixp23xx_timer,
67 .boot_params = 0x00000100,
68 .init_machine = espresso_init,
69MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
new file mode 100644
index 000000000000..00146c35daac
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -0,0 +1,325 @@
1/*
2 * arch/arm/mach-ixp23xx/ixdp2351.c
3 *
4 * IXDP2351 board-specific routines
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * Based on 2.4 code Copyright 2004 (c) Intel Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/config.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/spinlock.h>
21#include <linux/sched.h>
22#include <linux/interrupt.h>
23#include <linux/serial.h>
24#include <linux/tty.h>
25#include <linux/bitops.h>
26#include <linux/ioport.h>
27#include <linux/serial.h>
28#include <linux/serial_8250.h>
29#include <linux/serial_core.h>
30#include <linux/device.h>
31#include <linux/mm.h>
32#include <linux/pci.h>
33#include <linux/mtd/physmap.h>
34
35#include <asm/types.h>
36#include <asm/setup.h>
37#include <asm/memory.h>
38#include <asm/hardware.h>
39#include <asm/mach-types.h>
40#include <asm/irq.h>
41#include <asm/system.h>
42#include <asm/tlbflush.h>
43#include <asm/pgtable.h>
44
45#include <asm/mach/map.h>
46#include <asm/mach/irq.h>
47#include <asm/mach/arch.h>
48#include <asm/mach/irq.h>
49#include <asm/mach/pci.h>
50
51/*
52 * IXDP2351 Interrupt Handling
53 */
54static void ixdp2351_inta_mask(unsigned int irq)
55{
56 *IXDP2351_CPLD_INTA_MASK_SET_REG = IXDP2351_INTA_IRQ_MASK(irq);
57}
58
59static void ixdp2351_inta_unmask(unsigned int irq)
60{
61 *IXDP2351_CPLD_INTA_MASK_CLR_REG = IXDP2351_INTA_IRQ_MASK(irq);
62}
63
64static void ixdp2351_inta_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
65{
66 u16 ex_interrupt =
67 *IXDP2351_CPLD_INTA_STAT_REG & IXDP2351_INTA_IRQ_VALID;
68 int i;
69
70 desc->chip->mask(irq);
71
72 for (i = 0; i < IXDP2351_INTA_IRQ_NUM; i++) {
73 if (ex_interrupt & (1 << i)) {
74 struct irqdesc *cpld_desc;
75 int cpld_irq =
76 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + i);
77 cpld_desc = irq_desc + cpld_irq;
78 cpld_desc->handle(cpld_irq, cpld_desc, regs);
79 }
80 }
81
82 desc->chip->unmask(irq);
83}
84
85static struct irqchip ixdp2351_inta_chip = {
86 .ack = ixdp2351_inta_mask,
87 .mask = ixdp2351_inta_mask,
88 .unmask = ixdp2351_inta_unmask
89};
90
91static void ixdp2351_intb_mask(unsigned int irq)
92{
93 *IXDP2351_CPLD_INTB_MASK_SET_REG = IXDP2351_INTB_IRQ_MASK(irq);
94}
95
96static void ixdp2351_intb_unmask(unsigned int irq)
97{
98 *IXDP2351_CPLD_INTB_MASK_CLR_REG = IXDP2351_INTB_IRQ_MASK(irq);
99}
100
101static void ixdp2351_intb_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
102{
103 u16 ex_interrupt =
104 *IXDP2351_CPLD_INTB_STAT_REG & IXDP2351_INTB_IRQ_VALID;
105 int i;
106
107 desc->chip->ack(irq);
108
109 for (i = 0; i < IXDP2351_INTB_IRQ_NUM; i++) {
110 if (ex_interrupt & (1 << i)) {
111 struct irqdesc *cpld_desc;
112 int cpld_irq =
113 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + i);
114 cpld_desc = irq_desc + cpld_irq;
115 cpld_desc->handle(cpld_irq, cpld_desc, regs);
116 }
117 }
118
119 desc->chip->unmask(irq);
120}
121
122static struct irqchip ixdp2351_intb_chip = {
123 .ack = ixdp2351_intb_mask,
124 .mask = ixdp2351_intb_mask,
125 .unmask = ixdp2351_intb_unmask
126};
127
128void ixdp2351_init_irq(void)
129{
130 int irq;
131
132 /* Mask all interrupts from CPLD, disable simulation */
133 *IXDP2351_CPLD_INTA_MASK_SET_REG = (u16) -1;
134 *IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1;
135 *IXDP2351_CPLD_INTA_SIM_REG = 0;
136 *IXDP2351_CPLD_INTB_SIM_REG = 0;
137
138 ixp23xx_init_irq();
139
140 for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE);
141 irq <
142 IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM);
143 irq++) {
144 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
145 set_irq_flags(irq, IRQF_VALID);
146 set_irq_handler(irq, do_level_IRQ);
147 set_irq_chip(irq, &ixdp2351_inta_chip);
148 }
149 }
150
151 for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE);
152 irq <
153 IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM);
154 irq++) {
155 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
156 set_irq_flags(irq, IRQF_VALID);
157 set_irq_handler(irq, do_level_IRQ);
158 set_irq_chip(irq, &ixdp2351_intb_chip);
159 }
160 }
161
162 set_irq_chained_handler(IRQ_IXP23XX_INTA, &ixdp2351_inta_handler);
163 set_irq_chained_handler(IRQ_IXP23XX_INTB, &ixdp2351_intb_handler);
164}
165
166/*
167 * IXDP2351 PCI
168 */
169
170/*
171 * This board does not do normal PCI IRQ routing, or any
172 * sort of swizzling, so we just need to check where on the
173 * bus the device is and figure out what CPLD pin it is
174 * being routed to.
175 */
176#define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
177
178static int __init ixdp2351_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
179{
180 u8 bus = dev->bus->number;
181 u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
182 struct pci_bus *tmp_bus = dev->bus;
183
184 /* Primary bus, no interrupts here */
185 if (!bus)
186 return -1;
187
188 /* Lookup first leaf in bus tree */
189 while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL))
190 tmp_bus = tmp_bus->parent;
191
192 /* Select between known bridges */
193 switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
194 /* Device is located after first bridge */
195 case 0x0008:
196 if (tmp_bus == dev->bus) {
197 /* Device is located directy after first bridge */
198 switch (devpin) {
199 /* Onboard 82546 */
200 case DEVPIN(1, 1): /* Onboard 82546 ch 0 */
201 return IRQ_IXDP2351_INTA_82546;
202 case DEVPIN(1, 2): /* Onboard 82546 ch 1 */
203 return IRQ_IXDP2351_INTB_82546;
204 /* PMC SLOT */
205 case DEVPIN(0, 1): /* PMCP INTA# */
206 case DEVPIN(2, 4): /* PMCS INTD# */
207 return IRQ_IXDP2351_SPCI_PMC_INTA;
208 case DEVPIN(0, 2): /* PMCP INTB# */
209 case DEVPIN(2, 1): /* PMCS INTA# */
210 return IRQ_IXDP2351_SPCI_PMC_INTB;
211 case DEVPIN(0, 3): /* PMCP INTC# */
212 case DEVPIN(2, 2): /* PMCS INTB# */
213 return IRQ_IXDP2351_SPCI_PMC_INTC;
214 case DEVPIN(0, 4): /* PMCP INTD# */
215 case DEVPIN(2, 3): /* PMCS INTC# */
216 return IRQ_IXDP2351_SPCI_PMC_INTD;
217 }
218 } else {
219 /* Device is located indirectly after first bridge */
220 /* Not supported now */
221 return -1;
222 }
223 break;
224 case 0x0010:
225 if (tmp_bus == dev->bus) {
226 /* Device is located directy after second bridge */
227 /* Secondary bus of second bridge */
228 switch (devpin) {
229 case DEVPIN(0, 1): /* DB#0 */
230 case DEVPIN(0, 2):
231 case DEVPIN(0, 3):
232 case DEVPIN(0, 4):
233 return IRQ_IXDP2351_SPCI_DB_0;
234 case DEVPIN(1, 1): /* DB#1 */
235 case DEVPIN(1, 2):
236 case DEVPIN(1, 3):
237 case DEVPIN(1, 4):
238 return IRQ_IXDP2351_SPCI_DB_1;
239 case DEVPIN(2, 1): /* FIC1 */
240 case DEVPIN(2, 2):
241 case DEVPIN(2, 3):
242 case DEVPIN(2, 4):
243 case DEVPIN(3, 1): /* FIC2 */
244 case DEVPIN(3, 2):
245 case DEVPIN(3, 3):
246 case DEVPIN(3, 4):
247 return IRQ_IXDP2351_SPCI_FIC;
248 }
249 } else {
250 /* Device is located indirectly after second bridge */
251 /* Not supported now */
252 return -1;
253 }
254 break;
255 }
256
257 return -1;
258}
259
260struct hw_pci ixdp2351_pci __initdata = {
261 .nr_controllers = 1,
262 .preinit = ixp23xx_pci_preinit,
263 .setup = ixp23xx_pci_setup,
264 .scan = ixp23xx_pci_scan_bus,
265 .map_irq = ixdp2351_map_irq,
266};
267
268int __init ixdp2351_pci_init(void)
269{
270 if (machine_is_ixdp2351())
271 pci_common_init(&ixdp2351_pci);
272
273 return 0;
274}
275
276subsys_initcall(ixdp2351_pci_init);
277
278/*
279 * IXDP2351 Static Mapped I/O
280 */
281static struct map_desc ixdp2351_io_desc[] __initdata = {
282 {
283 .virtual = IXDP2351_NP_VIRT_BASE,
284 .pfn = __phys_to_pfn((u64)IXDP2351_NP_PHYS_BASE),
285 .length = IXDP2351_NP_PHYS_SIZE,
286 .type = MT_DEVICE
287 }, {
288 .virtual = IXDP2351_BB_BASE_VIRT,
289 .pfn = __phys_to_pfn((u64)IXDP2351_BB_BASE_PHYS),
290 .length = IXDP2351_BB_SIZE,
291 .type = MT_DEVICE
292 }
293};
294
295static void __init ixdp2351_map_io(void)
296{
297 ixp23xx_map_io();
298 iotable_init(ixdp2351_io_desc, ARRAY_SIZE(ixdp2351_io_desc));
299}
300
301static void __init ixdp2351_init(void)
302{
303 physmap_configure(0x90000000, 0x04000000, 1, NULL);
304
305 /*
306 * Mark flash as writeable
307 */
308 IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
309 IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
310 IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
311 IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
312
313 ixp23xx_sys_init();
314}
315
316MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
317 /* Maintainer: MontaVista Software, Inc. */
318 .phys_io = IXP23XX_PERIPHERAL_PHYS,
319 .io_pg_offst = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
320 .map_io = ixdp2351_map_io,
321 .init_irq = ixdp2351_init_irq,
322 .timer = &ixp23xx_timer,
323 .boot_params = 0x00000100,
324 .init_machine = ixdp2351_init,
325MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
new file mode 100644
index 000000000000..5330ad78c1bb
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -0,0 +1,275 @@
1/*
2 * arch/arm/mach-ixp23xx/pci.c
3 *
4 * PCI routines for IXP23XX based systems
5 *
6 * Copyright (c) 2005 MontaVista Software, Inc.
7 *
8 * based on original code:
9 *
10 * Author: Naeem Afzal <naeem.m.afzal@intel.com>
11 * Copyright 2002-2005 Intel Corp.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19#include <linux/config.h>
20#include <linux/sched.h>
21#include <linux/kernel.h>
22#include <linux/pci.h>
23#include <linux/interrupt.h>
24#include <linux/mm.h>
25#include <linux/init.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
28#include <linux/delay.h>
29
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/sizes.h>
33#include <asm/system.h>
34#include <asm/mach/pci.h>
35#include <asm/mach-types.h>
36#include <asm/hardware.h>
37
38extern int (*external_fault) (unsigned long, struct pt_regs *);
39
40static int pci_master_aborts = 0;
41
42#ifdef DEBUG
43#define DBG(x...) printk(x)
44#else
45#define DBG(x...)
46#endif
47
48int clear_master_aborts(void);
49
50static u32
51*ixp23xx_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where)
52{
53 u32 *paddress;
54
55 /*
56 * Must be dword aligned
57 */
58 where &= ~3;
59
60 /*
61 * For top bus, generate type 0, else type 1
62 */
63 if (!bus_nr) {
64 if (PCI_SLOT(devfn) >= 8)
65 return 0;
66
67 paddress = (u32 *) (IXP23XX_PCI_CFG0_VIRT
68 | (1 << (PCI_SLOT(devfn) + 16))
69 | (PCI_FUNC(devfn) << 8) | where);
70 } else {
71 paddress = (u32 *) (IXP23XX_PCI_CFG1_VIRT
72 | (bus_nr << 16)
73 | (PCI_SLOT(devfn) << 11)
74 | (PCI_FUNC(devfn) << 8) | where);
75 }
76
77 return paddress;
78}
79
80/*
81 * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes.
82 * 0 and 3 are not valid indexes...
83 */
84static u32 bytemask[] = {
85 /*0*/ 0,
86 /*1*/ 0xff,
87 /*2*/ 0xffff,
88 /*3*/ 0,
89 /*4*/ 0xffffffff,
90};
91
92static int ixp23xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
93 int where, int size, u32 *value)
94{
95 u32 n;
96 u32 *addr;
97
98 n = where % 4;
99
100 DBG("In config_read(%d) %d from dev %d:%d:%d\n", size, where,
101 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
102
103 addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
104 if (!addr)
105 return PCIBIOS_DEVICE_NOT_FOUND;
106
107 pci_master_aborts = 0;
108 *value = (*addr >> (8*n)) & bytemask[size];
109 if (pci_master_aborts) {
110 pci_master_aborts = 0;
111 *value = 0xffffffff;
112 return PCIBIOS_DEVICE_NOT_FOUND;
113 }
114
115 return PCIBIOS_SUCCESSFUL;
116}
117
118/*
119 * We don't do error checking on the address for writes.
120 * It's assumed that the user checked for the device existing first
121 * by doing a read first.
122 */
123static int ixp23xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
124 int where, int size, u32 value)
125{
126 u32 mask;
127 u32 *addr;
128 u32 temp;
129
130 mask = ~(bytemask[size] << ((where % 0x4) * 8));
131 addr = ixp23xx_pci_config_addr(bus->number, devfn, where);
132 if (!addr)
133 return PCIBIOS_DEVICE_NOT_FOUND;
134 temp = (u32) (value) << ((where % 0x4) * 8);
135 *addr = (*addr & mask) | temp;
136
137 clear_master_aborts();
138
139 return PCIBIOS_SUCCESSFUL;
140}
141
142struct pci_ops ixp23xx_pci_ops = {
143 .read = ixp23xx_pci_read_config,
144 .write = ixp23xx_pci_write_config,
145};
146
147struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
148{
149 return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata);
150}
151
152int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
153{
154 volatile unsigned long temp;
155 unsigned long flags;
156
157 pci_master_aborts = 1;
158
159 local_irq_save(flags);
160 temp = *IXP23XX_PCI_CONTROL;
161
162 /*
163 * master abort and cmd tgt err
164 */
165 if (temp & ((1 << 8) | (1 << 5)))
166 *IXP23XX_PCI_CONTROL = temp;
167
168 temp = *IXP23XX_PCI_CMDSTAT;
169
170 if (temp & (1 << 29))
171 *IXP23XX_PCI_CMDSTAT = temp;
172 local_irq_restore(flags);
173
174 /*
175 * If it was an imprecise abort, then we need to correct the
176 * return address to be _after_ the instruction.
177 */
178 if (fsr & (1 << 10))
179 regs->ARM_pc += 4;
180
181 return 0;
182}
183
184int clear_master_aborts(void)
185{
186 volatile u32 temp;
187
188 temp = *IXP23XX_PCI_CONTROL;
189
190 /*
191 * master abort and cmd tgt err
192 */
193 if (temp & ((1 << 8) | (1 << 5)))
194 *IXP23XX_PCI_CONTROL = temp;
195
196 temp = *IXP23XX_PCI_CMDSTAT;
197
198 if (temp & (1 << 29))
199 *IXP23XX_PCI_CMDSTAT = temp;
200
201 return 0;
202}
203
204void __init ixp23xx_pci_preinit(void)
205{
206#ifdef __ARMEB__
207 *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */
208#endif
209 /*
210 * ADDR_31 needs to be clear for PCI memory access to CPP memory
211 */
212 *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_ADDR_31;
213 *IXP23XX_CPP2XSI_CURR_XFER_REG3 |= IXP23XX_CPP2XSI_PSH_OFF;
214
215 /*
216 * Select correct memory for PCI inbound transactions
217 */
218 if (ixp23xx_cpp_boot()) {
219 *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1);
220 } else {
221 *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1);
222 }
223
224 hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS,
225 "PCI config cycle to non-existent device");
226
227 *IXP23XX_PCI_ADDR_EXT = 0x0000e000;
228}
229
230/*
231 * Prevent PCI layer from seeing the inbound host-bridge resources
232 */
233static void __devinit pci_fixup_ixp23xx(struct pci_dev *dev)
234{
235 int i;
236
237 dev->class &= 0xff;
238 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
239 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
240 dev->resource[i].start = 0;
241 dev->resource[i].end = 0;
242 dev->resource[i].flags = 0;
243 }
244}
245DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9002, pci_fixup_ixp23xx);
246
247/*
248 * IXP2300 systems often have large resource requirements, so we just
249 * use our own resource space.
250 */
251static struct resource ixp23xx_pci_mem_space = {
252 .start = IXP23XX_PCI_MEM_START,
253 .end = IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE - 1,
254 .flags = IORESOURCE_MEM,
255 .name = "PCI Mem Space"
256};
257
258static struct resource ixp23xx_pci_io_space = {
259 .start = 0x00000100,
260 .end = 0x01ffffff,
261 .flags = IORESOURCE_IO,
262 .name = "PCI I/O Space"
263};
264
265int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
266{
267 if (nr >= 1)
268 return 0;
269
270 sys->resource[0] = &ixp23xx_pci_io_space;
271 sys->resource[1] = &ixp23xx_pci_mem_space;
272 sys->resource[2] = NULL;
273
274 return 1;
275}
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
new file mode 100644
index 000000000000..43c14e740794
--- /dev/null
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -0,0 +1,164 @@
1/*
2 * arch/arm/mach-ixp23xx/roadrunner.c
3 *
4 * RoadRunner board-specific routines
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * Based on 2.4 code Copyright 2005 (c) ADI Engineering Corporation
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/config.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/spinlock.h>
21#include <linux/sched.h>
22#include <linux/interrupt.h>
23#include <linux/serial.h>
24#include <linux/tty.h>
25#include <linux/bitops.h>
26#include <linux/ioport.h>
27#include <linux/serial.h>
28#include <linux/serial_8250.h>
29#include <linux/serial_core.h>
30#include <linux/device.h>
31#include <linux/mm.h>
32#include <linux/pci.h>
33#include <linux/mtd/physmap.h>
34
35#include <asm/types.h>
36#include <asm/setup.h>
37#include <asm/memory.h>
38#include <asm/hardware.h>
39#include <asm/mach-types.h>
40#include <asm/irq.h>
41#include <asm/system.h>
42#include <asm/tlbflush.h>
43#include <asm/pgtable.h>
44
45#include <asm/mach/map.h>
46#include <asm/mach/irq.h>
47#include <asm/mach/arch.h>
48#include <asm/mach/irq.h>
49#include <asm/mach/pci.h>
50
51/*
52 * Interrupt mapping
53 */
54#define INTA IRQ_ROADRUNNER_PCI_INTA
55#define INTB IRQ_ROADRUNNER_PCI_INTB
56#define INTC IRQ_ROADRUNNER_PCI_INTC
57#define INTD IRQ_ROADRUNNER_PCI_INTD
58
59#define INTC_PIN IXP23XX_GPIO_PIN_11
60#define INTD_PIN IXP23XX_GPIO_PIN_12
61
62static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
63{
64 static int pci_card_slot_irq[] = {INTB, INTC, INTD, INTA};
65 static int pmc_card_slot_irq[] = {INTA, INTB, INTC, INTD};
66 static int usb_irq[] = {INTB, INTC, INTD, -1};
67 static int mini_pci_1_irq[] = {INTB, INTC, -1, -1};
68 static int mini_pci_2_irq[] = {INTC, INTD, -1, -1};
69
70 switch(dev->bus->number) {
71 case 0:
72 switch(dev->devfn) {
73 case 0x0: // PCI-PCI bridge
74 break;
75 case 0x8: // PCI Card Slot
76 return pci_card_slot_irq[pin - 1];
77 case 0x10: // PMC Slot
78 return pmc_card_slot_irq[pin - 1];
79 case 0x18: // PMC Slot Secondary Agent
80 break;
81 case 0x20: // IXP Processor
82 break;
83 default:
84 return NO_IRQ;
85 }
86 break;
87
88 case 1:
89 switch(dev->devfn) {
90 case 0x0: // IDE Controller
91 return (pin == 1) ? INTC : -1;
92 case 0x8: // USB fun 0
93 case 0x9: // USB fun 1
94 case 0xa: // USB fun 2
95 return usb_irq[pin - 1];
96 case 0x10: // Mini PCI 1
97 return mini_pci_1_irq[pin-1];
98 case 0x18: // Mini PCI 2
99 return mini_pci_2_irq[pin-1];
100 case 0x20: // MEM slot
101 return (pin == 1) ? INTA : -1;
102 default:
103 return NO_IRQ;
104 }
105 break;
106
107 default:
108 return NO_IRQ;
109 }
110
111 return NO_IRQ;
112}
113
114static void roadrunner_pci_preinit(void)
115{
116 set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQT_LOW);
117 set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQT_LOW);
118
119 ixp23xx_pci_preinit();
120}
121
122static struct hw_pci roadrunner_pci __initdata = {
123 .nr_controllers = 1,
124 .preinit = roadrunner_pci_preinit,
125 .setup = ixp23xx_pci_setup,
126 .scan = ixp23xx_pci_scan_bus,
127 .map_irq = roadrunner_map_irq,
128};
129
130static int __init roadrunner_pci_init(void)
131{
132 if (machine_is_roadrunner())
133 pci_common_init(&roadrunner_pci);
134
135 return 0;
136};
137
138subsys_initcall(roadrunner_pci_init);
139
140static void __init roadrunner_init(void)
141{
142 physmap_configure(0x90000000, 0x04000000, 2, NULL);
143
144 /*
145 * Mark flash as writeable
146 */
147 IXP23XX_EXP_CS0[0] |= IXP23XX_FLASH_WRITABLE;
148 IXP23XX_EXP_CS0[1] |= IXP23XX_FLASH_WRITABLE;
149 IXP23XX_EXP_CS0[2] |= IXP23XX_FLASH_WRITABLE;
150 IXP23XX_EXP_CS0[3] |= IXP23XX_FLASH_WRITABLE;
151
152 ixp23xx_sys_init();
153}
154
155MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform")
156 /* Maintainer: Deepak Saxena */
157 .phys_io = IXP23XX_PERIPHERAL_PHYS,
158 .io_pg_offst = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
159 .map_io = ixp23xx_map_io,
160 .init_irq = ixp23xx_init_irq,
161 .timer = &ixp23xx_timer,
162 .boot_params = 0x00000100,
163 .init_machine = roadrunner_init,
164MACHINE_END
diff --git a/include/asm-arm/arch-ixp23xx/debug-macro.S b/include/asm-arm/arch-ixp23xx/debug-macro.S
new file mode 100644
index 000000000000..eb99fd69fd24
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/debug-macro.S
@@ -0,0 +1,23 @@
1/*
2 * include/asm-arm/arch-ixp23xx/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * Copyright (C) 1994-1999 Russell King
7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <asm/arch/ixp23xx.h>
14
15 .macro addruart,rx
16 mrc p15, 0, \rx, c1, c0
17 tst \rx, #1 @ mmu enabled?
18 ldreq \rx, =IXP23XX_PERIPHERAL_PHYS @ physical
19 ldrne \rx, =IXP23XX_PERIPHERAL_VIRT @ virtual
20 .endm
21
22#define UART_SHIFT 2
23#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-ixp23xx/dma.h b/include/asm-arm/arch-ixp23xx/dma.h
new file mode 100644
index 000000000000..2f4335e3b836
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/dma.h
@@ -0,0 +1,3 @@
1/*
2 * include/asm-arm/arch-ixp23xx/dma.h
3 */
diff --git a/include/asm-arm/arch-ixp23xx/entry-macro.S b/include/asm-arm/arch-ixp23xx/entry-macro.S
new file mode 100644
index 000000000000..0ef4e6016ac4
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/entry-macro.S
@@ -0,0 +1,31 @@
1/*
2 * include/asm-arm/arch-ixp23xx/entry-macro.S
3 */
4
5 .macro disable_fiq
6 .endm
7
8 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
9 ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
10 ldr \irqnr, [\irqnr] @ get interrupt number
11 cmp \irqnr, #0x0 @ suprious interrupt ?
12 movne \irqnr, \irqnr, lsr #2 @ skip unwanted low order bits
13 subne \irqnr, \irqnr, #1 @ convert to 0 based
14
15#if 0
16 cmp \irqnr, #IRQ_IXP23XX_PCI_INT_RPH
17 bne 1001f
18 mov \irqnr, #IRQ_IXP23XX_INTA
19
20 ldr \irqnr, =0xf5000030
21
22 mov \tmp, #(1<<26)
23 tst \irqnr, \tmp
24 movne \irqnr, #IRQ_IXP23XX_INTB
25
26 mov \tmp, #(1<<27)
27 tst \irqnr, \tmp
28 movne \irqnr, #IRQ_IXP23XX_INTA
291001:
30#endif
31 .endm
diff --git a/include/asm-arm/arch-ixp23xx/hardware.h b/include/asm-arm/arch-ixp23xx/hardware.h
new file mode 100644
index 000000000000..c0010d21a684
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/hardware.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-arm/arch-ixp23xx/hardware.h
3 *
4 * Copyright (C) 2002-2004 Intel Corporation.
5 * Copyricht (C) 2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Hardware definitions for IXP23XX based systems
12 */
13
14#ifndef __ASM_ARCH_HARDWARE_H
15#define __ASM_ARCH_HARDWARE_H
16
17/* PCI IO info */
18#define PCIO_BASE IXP23XX_PCI_IO_VIRT
19#define PCIBIOS_MIN_IO 0x00000000
20#define PCIBIOS_MIN_MEM 0xe0000000
21
22#include "ixp23xx.h"
23
24#define pcibios_assign_all_busses() 0
25
26/*
27 * Platform helper functions
28 */
29#include "platform.h"
30
31/*
32 * Platform-specific headers
33 */
34#include "ixdp2351.h"
35
36
37#endif
diff --git a/include/asm-arm/arch-ixp23xx/io.h b/include/asm-arm/arch-ixp23xx/io.h
new file mode 100644
index 000000000000..18415a81ac74
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/io.h
@@ -0,0 +1,54 @@
1/*
2 * include/asm-arm/arch-ixp23xx/io.h
3 *
4 * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2003-2005 Intel Corp.
8 * Copyright (C) 2005 MontaVista Software, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_IO_H
16#define __ASM_ARCH_IO_H
17
18#define IO_SPACE_LIMIT 0xffffffff
19
20#define __io(p) ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
21#define __mem_pci(a) (a)
22
23#include <linux/kernel.h> /* For BUG */
24
25static inline void __iomem *
26ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned long flags)
27{
28 if (addr >= IXP23XX_PCI_MEM_START &&
29 addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) {
30 if (addr + size > IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE)
31 return NULL;
32
33 return (void __iomem *)
34 ((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT);
35 }
36
37 return __ioremap(addr, size, flags);
38}
39
40static inline void
41ixp23xx_iounmap(void __iomem *addr)
42{
43 if ((((u32)addr) >= IXP23XX_PCI_MEM_VIRT) &&
44 (((u32)addr) < IXP23XX_PCI_MEM_VIRT + IXP23XX_PCI_MEM_SIZE))
45 return;
46
47 __iounmap(addr);
48}
49
50#define __arch_ioremap(a,s,f) ixp23xx_ioremap(a,s,f)
51#define __arch_iounmap(a) ixp23xx_iounmap(a)
52
53
54#endif
diff --git a/include/asm-arm/arch-ixp23xx/irqs.h b/include/asm-arm/arch-ixp23xx/irqs.h
new file mode 100644
index 000000000000..e69639585721
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/irqs.h
@@ -0,0 +1,223 @@
1/*
2 * include/asm-arm/arch-ixp23xx/irqs.h
3 *
4 * IRQ definitions for IXP23XX based systems
5 *
6 * Author: Naeem Afzal <naeem.m.afzal@intel.com>
7 *
8 * Copyright (C) 2003-2004 Intel Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_IRQS_H
16#define __ASM_ARCH_IRQS_H
17
18#define NR_IXP23XX_IRQS IRQ_IXP23XX_INTB+1
19#define IRQ_IXP23XX_EXTIRQS NR_IXP23XX_IRQS
20
21
22#define IRQ_IXP23XX_DBG0 0 /* Debug/Execution/MBox */
23#define IRQ_IXP23XX_DBG1 1 /* Debug/Execution/MBox */
24#define IRQ_IXP23XX_NPE_TRG 2 /* npe_trigger */
25#define IRQ_IXP23XX_TIMER1 3 /* Timer[0] */
26#define IRQ_IXP23XX_TIMER2 4 /* Timer[1] */
27#define IRQ_IXP23XX_TIMESTAMP 5 /* Timer[2], Time-stamp */
28#define IRQ_IXP23XX_WDOG 6 /* Time[3], Watchdog Timer */
29#define IRQ_IXP23XX_PCI_DBELL 7 /* PCI Doorbell */
30#define IRQ_IXP23XX_PCI_DMA1 8 /* PCI DMA Channel 1 */
31#define IRQ_IXP23XX_PCI_DMA2 9 /* PCI DMA Channel 2 */
32#define IRQ_IXP23XX_PCI_DMA3 10 /* PCI DMA Channel 3 */
33#define IRQ_IXP23XX_PCI_INT_RPH 11 /* pcxg_pci_int_rph */
34#define IRQ_IXP23XX_CPP_PMU 12 /* xpxg_pm_int_rpl */
35#define IRQ_IXP23XX_SWINT0 13 /* S/W Interrupt0 */
36#define IRQ_IXP23XX_SWINT1 14 /* S/W Interrupt1 */
37#define IRQ_IXP23XX_UART2 15 /* UART1 Interrupt */
38#define IRQ_IXP23XX_UART1 16 /* UART0 Interrupt */
39#define IRQ_IXP23XX_XSI_PMU_ROLLOVER 17 /* AHB Performance M. Unit counter rollover */
40#define IRQ_IXP23XX_XSI_AHB_PM0 18 /* intr_pm_o */
41#define IRQ_IXP23XX_XSI_AHB_ECE0 19 /* intr_ece_o */
42#define IRQ_IXP23XX_XSI_AHB_GASKET 20 /* gas_intr_o */
43#define IRQ_IXP23XX_XSI_CPP 21 /* xsi2cpp_int */
44#define IRQ_IXP23XX_CPP_XSI 22 /* cpp2xsi_int */
45#define IRQ_IXP23XX_ME_ATTN0 23 /* ME_ATTN */
46#define IRQ_IXP23XX_ME_ATTN1 24 /* ME_ATTN */
47#define IRQ_IXP23XX_ME_ATTN2 25 /* ME_ATTN */
48#define IRQ_IXP23XX_ME_ATTN3 26 /* ME_ATTN */
49#define IRQ_IXP23XX_PCI_ERR_RPH 27 /* PCXG_PCI_ERR_RPH */
50#define IRQ_IXP23XX_D0XG_ECC_CORR 28 /* D0XG_DRAM_ECC_CORR */
51#define IRQ_IXP23XX_D0XG_ECC_UNCORR 29 /* D0XG_DRAM_ECC_UNCORR */
52#define IRQ_IXP23XX_SRAM_ERR1 30 /* SRAM1_ERR */
53#define IRQ_IXP23XX_SRAM_ERR0 31 /* SRAM0_ERR */
54#define IRQ_IXP23XX_MEDIA_ERR 32 /* MEDIA_ERR */
55#define IRQ_IXP23XX_STH_DRAM_ECC_MAJ 33 /* STH_DRAM0_ECC_MAJ */
56#define IRQ_IXP23XX_GPIO6 34 /* GPIO0 interrupts */
57#define IRQ_IXP23XX_GPIO7 35 /* GPIO1 interrupts */
58#define IRQ_IXP23XX_GPIO8 36 /* GPIO2 interrupts */
59#define IRQ_IXP23XX_GPIO9 37 /* GPIO3 interrupts */
60#define IRQ_IXP23XX_GPIO10 38 /* GPIO4 interrupts */
61#define IRQ_IXP23XX_GPIO11 39 /* GPIO5 interrupts */
62#define IRQ_IXP23XX_GPIO12 40 /* GPIO6 interrupts */
63#define IRQ_IXP23XX_GPIO13 41 /* GPIO7 interrupts */
64#define IRQ_IXP23XX_GPIO14 42 /* GPIO8 interrupts */
65#define IRQ_IXP23XX_GPIO15 43 /* GPIO9 interrupts */
66#define IRQ_IXP23XX_SHAC_RING0 44 /* SHAC Ring Full */
67#define IRQ_IXP23XX_SHAC_RING1 45 /* SHAC Ring Full */
68#define IRQ_IXP23XX_SHAC_RING2 46 /* SHAC Ring Full */
69#define IRQ_IXP23XX_SHAC_RING3 47 /* SHAC Ring Full */
70#define IRQ_IXP23XX_SHAC_RING4 48 /* SHAC Ring Full */
71#define IRQ_IXP23XX_SHAC_RING5 49 /* SHAC Ring Full */
72#define IRQ_IXP23XX_SHAC_RING6 50 /* SHAC RING Full */
73#define IRQ_IXP23XX_SHAC_RING7 51 /* SHAC Ring Full */
74#define IRQ_IXP23XX_SHAC_RING8 52 /* SHAC Ring Full */
75#define IRQ_IXP23XX_SHAC_RING9 53 /* SHAC Ring Full */
76#define IRQ_IXP23XX_SHAC_RING10 54 /* SHAC Ring Full */
77#define IRQ_IXP23XX_SHAC_RING11 55 /* SHAC Ring Full */
78#define IRQ_IXP23XX_ME_THREAD_A0_ME0 56 /* ME_THREAD_A */
79#define IRQ_IXP23XX_ME_THREAD_A1_ME0 57 /* ME_THREAD_A */
80#define IRQ_IXP23XX_ME_THREAD_A2_ME0 58 /* ME_THREAD_A */
81#define IRQ_IXP23XX_ME_THREAD_A3_ME0 59 /* ME_THREAD_A */
82#define IRQ_IXP23XX_ME_THREAD_A4_ME0 60 /* ME_THREAD_A */
83#define IRQ_IXP23XX_ME_THREAD_A5_ME0 61 /* ME_THREAD_A */
84#define IRQ_IXP23XX_ME_THREAD_A6_ME0 62 /* ME_THREAD_A */
85#define IRQ_IXP23XX_ME_THREAD_A7_ME0 63 /* ME_THREAD_A */
86#define IRQ_IXP23XX_ME_THREAD_A8_ME1 64 /* ME_THREAD_A */
87#define IRQ_IXP23XX_ME_THREAD_A9_ME1 65 /* ME_THREAD_A */
88#define IRQ_IXP23XX_ME_THREAD_A10_ME1 66 /* ME_THREAD_A */
89#define IRQ_IXP23XX_ME_THREAD_A11_ME1 67 /* ME_THREAD_A */
90#define IRQ_IXP23XX_ME_THREAD_A12_ME1 68 /* ME_THREAD_A */
91#define IRQ_IXP23XX_ME_THREAD_A13_ME1 69 /* ME_THREAD_A */
92#define IRQ_IXP23XX_ME_THREAD_A14_ME1 70 /* ME_THREAD_A */
93#define IRQ_IXP23XX_ME_THREAD_A15_ME1 71 /* ME_THREAD_A */
94#define IRQ_IXP23XX_ME_THREAD_A16_ME2 72 /* ME_THREAD_A */
95#define IRQ_IXP23XX_ME_THREAD_A17_ME2 73 /* ME_THREAD_A */
96#define IRQ_IXP23XX_ME_THREAD_A18_ME2 74 /* ME_THREAD_A */
97#define IRQ_IXP23XX_ME_THREAD_A19_ME2 75 /* ME_THREAD_A */
98#define IRQ_IXP23XX_ME_THREAD_A20_ME2 76 /* ME_THREAD_A */
99#define IRQ_IXP23XX_ME_THREAD_A21_ME2 77 /* ME_THREAD_A */
100#define IRQ_IXP23XX_ME_THREAD_A22_ME2 78 /* ME_THREAD_A */
101#define IRQ_IXP23XX_ME_THREAD_A23_ME2 79 /* ME_THREAD_A */
102#define IRQ_IXP23XX_ME_THREAD_A24_ME3 80 /* ME_THREAD_A */
103#define IRQ_IXP23XX_ME_THREAD_A25_ME3 81 /* ME_THREAD_A */
104#define IRQ_IXP23XX_ME_THREAD_A26_ME3 82 /* ME_THREAD_A */
105#define IRQ_IXP23XX_ME_THREAD_A27_ME3 83 /* ME_THREAD_A */
106#define IRQ_IXP23XX_ME_THREAD_A28_ME3 84 /* ME_THREAD_A */
107#define IRQ_IXP23XX_ME_THREAD_A29_ME3 85 /* ME_THREAD_A */
108#define IRQ_IXP23XX_ME_THREAD_A30_ME3 86 /* ME_THREAD_A */
109#define IRQ_IXP23XX_ME_THREAD_A31_ME3 87 /* ME_THREAD_A */
110#define IRQ_IXP23XX_ME_THREAD_B0_ME0 88 /* ME_THREAD_B */
111#define IRQ_IXP23XX_ME_THREAD_B1_ME0 89 /* ME_THREAD_B */
112#define IRQ_IXP23XX_ME_THREAD_B2_ME0 90 /* ME_THREAD_B */
113#define IRQ_IXP23XX_ME_THREAD_B3_ME0 91 /* ME_THREAD_B */
114#define IRQ_IXP23XX_ME_THREAD_B4_ME0 92 /* ME_THREAD_B */
115#define IRQ_IXP23XX_ME_THREAD_B5_ME0 93 /* ME_THREAD_B */
116#define IRQ_IXP23XX_ME_THREAD_B6_ME0 94 /* ME_THREAD_B */
117#define IRQ_IXP23XX_ME_THREAD_B7_ME0 95 /* ME_THREAD_B */
118#define IRQ_IXP23XX_ME_THREAD_B8_ME1 96 /* ME_THREAD_B */
119#define IRQ_IXP23XX_ME_THREAD_B9_ME1 97 /* ME_THREAD_B */
120#define IRQ_IXP23XX_ME_THREAD_B10_ME1 98 /* ME_THREAD_B */
121#define IRQ_IXP23XX_ME_THREAD_B11_ME1 99 /* ME_THREAD_B */
122#define IRQ_IXP23XX_ME_THREAD_B12_ME1 100 /* ME_THREAD_B */
123#define IRQ_IXP23XX_ME_THREAD_B13_ME1 101 /* ME_THREAD_B */
124#define IRQ_IXP23XX_ME_THREAD_B14_ME1 102 /* ME_THREAD_B */
125#define IRQ_IXP23XX_ME_THREAD_B15_ME1 103 /* ME_THREAD_B */
126#define IRQ_IXP23XX_ME_THREAD_B16_ME2 104 /* ME_THREAD_B */
127#define IRQ_IXP23XX_ME_THREAD_B17_ME2 105 /* ME_THREAD_B */
128#define IRQ_IXP23XX_ME_THREAD_B18_ME2 106 /* ME_THREAD_B */
129#define IRQ_IXP23XX_ME_THREAD_B19_ME2 107 /* ME_THREAD_B */
130#define IRQ_IXP23XX_ME_THREAD_B20_ME2 108 /* ME_THREAD_B */
131#define IRQ_IXP23XX_ME_THREAD_B21_ME2 109 /* ME_THREAD_B */
132#define IRQ_IXP23XX_ME_THREAD_B22_ME2 110 /* ME_THREAD_B */
133#define IRQ_IXP23XX_ME_THREAD_B23_ME2 111 /* ME_THREAD_B */
134#define IRQ_IXP23XX_ME_THREAD_B24_ME3 112 /* ME_THREAD_B */
135#define IRQ_IXP23XX_ME_THREAD_B25_ME3 113 /* ME_THREAD_B */
136#define IRQ_IXP23XX_ME_THREAD_B26_ME3 114 /* ME_THREAD_B */
137#define IRQ_IXP23XX_ME_THREAD_B27_ME3 115 /* ME_THREAD_B */
138#define IRQ_IXP23XX_ME_THREAD_B28_ME3 116 /* ME_THREAD_B */
139#define IRQ_IXP23XX_ME_THREAD_B29_ME3 117 /* ME_THREAD_B */
140#define IRQ_IXP23XX_ME_THREAD_B30_ME3 118 /* ME_THREAD_B */
141#define IRQ_IXP23XX_ME_THREAD_B31_ME3 119 /* ME_THREAD_B */
142
143#define NUM_IXP23XX_RAW_IRQS 120
144
145#define IRQ_IXP23XX_INTA 120 /* Indirect pcxg_pci_int_rph */
146#define IRQ_IXP23XX_INTB 121 /* Indirect pcxg_pci_int_rph */
147
148#define NR_IXP23XX_IRQ (IRQ_IXP23XX_INTB + 1)
149
150/*
151 * We default to 32 per-board IRQs. Increase this number if you need
152 * more, but keep it realistic.
153 */
154#define NR_IXP23XX_MACH_IRQS 32
155
156#define NR_IRQS NR_IXP23XX_IRQS + NR_IXP23XX_MACH_IRQS
157
158#define IXP23XX_MACH_IRQ(irq) (NR_IXP23XX_IRQ + (irq))
159
160
161/*
162 * IXDP2351-specific interrupts
163 */
164
165/*
166 * External PCI interrupts signaled through INTB
167 *
168 */
169#define IXDP2351_INTB_IRQ_BASE 0
170#define IRQ_IXDP2351_INTA_82546 IXP23XX_MACH_IRQ(0)
171#define IRQ_IXDP2351_INTB_82546 IXP23XX_MACH_IRQ(1)
172#define IRQ_IXDP2351_SPCI_DB_0 IXP23XX_MACH_IRQ(2)
173#define IRQ_IXDP2351_SPCI_DB_1 IXP23XX_MACH_IRQ(3)
174#define IRQ_IXDP2351_SPCI_PMC_INTA IXP23XX_MACH_IRQ(4)
175#define IRQ_IXDP2351_SPCI_PMC_INTB IXP23XX_MACH_IRQ(5)
176#define IRQ_IXDP2351_SPCI_PMC_INTC IXP23XX_MACH_IRQ(6)
177#define IRQ_IXDP2351_SPCI_PMC_INTD IXP23XX_MACH_IRQ(7)
178#define IRQ_IXDP2351_SPCI_FIC IXP23XX_MACH_IRQ(8)
179
180#define IXDP2351_INTB_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(0))
181#define IXDP2351_INTB_IRQ_MASK(irq) (1 << IXDP2351_INTB_IRQ_BIT(irq))
182#define IXDP2351_INTB_IRQ_VALID 0x01FF
183#define IXDP2351_INTB_IRQ_NUM 16
184
185/*
186 * Other external interrupts signaled through INTA
187 */
188#define IXDP2351_INTA_IRQ_BASE 16
189#define IRQ_IXDP2351_IPMI_FROM IXP23XX_MACH_IRQ(16)
190#define IRQ_IXDP2351_125US IXP23XX_MACH_IRQ(17)
191#define IRQ_IXDP2351_DB_0_ADD IXP23XX_MACH_IRQ(18)
192#define IRQ_IXDP2351_DB_1_ADD IXP23XX_MACH_IRQ(19)
193#define IRQ_IXDP2351_DEBUG1 IXP23XX_MACH_IRQ(20)
194#define IRQ_IXDP2351_ADD_UART IXP23XX_MACH_IRQ(21)
195#define IRQ_IXDP2351_FIC_ADD IXP23XX_MACH_IRQ(24)
196#define IRQ_IXDP2351_CS8900 IXP23XX_MACH_IRQ(25)
197#define IRQ_IXDP2351_BBSRAM IXP23XX_MACH_IRQ(26)
198#define IRQ_IXDP2351_CONFIG_MEDIA IXP23XX_MACH_IRQ(27)
199#define IRQ_IXDP2351_CLOCK_REF IXP23XX_MACH_IRQ(28)
200#define IRQ_IXDP2351_A10_NP IXP23XX_MACH_IRQ(29)
201#define IRQ_IXDP2351_A11_NP IXP23XX_MACH_IRQ(30)
202#define IRQ_IXDP2351_DEBUG_NP IXP23XX_MACH_IRQ(31)
203
204#define IXDP2351_INTA_IRQ_BIT(irq) (irq - IXP23XX_MACH_IRQ(16))
205#define IXDP2351_INTA_IRQ_MASK(irq) (1 << IXDP2351_INTA_IRQ_BIT(irq))
206#define IXDP2351_INTA_IRQ_VALID 0xFF3F
207#define IXDP2351_INTA_IRQ_NUM 16
208
209
210/*
211 * ADI RoadRunner IRQs
212 */
213#define IRQ_ROADRUNNER_PCI_INTA IRQ_IXP23XX_INTA
214#define IRQ_ROADRUNNER_PCI_INTB IRQ_IXP23XX_INTB
215#define IRQ_ROADRUNNER_PCI_INTC IRQ_IXP23XX_GPIO11
216#define IRQ_ROADRUNNER_PCI_INTD IRQ_IXP23XX_GPIO12
217
218/*
219 * Put new board definitions here
220 */
221
222
223#endif
diff --git a/include/asm-arm/arch-ixp23xx/ixdp2351.h b/include/asm-arm/arch-ixp23xx/ixdp2351.h
new file mode 100644
index 000000000000..4a24f8f15655
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/ixdp2351.h
@@ -0,0 +1,89 @@
1/*
2 * include/asm-arm/arch-ixp23xx/ixdp2351.h
3 *
4 * Register and other defines for IXDP2351
5 *
6 * Copyright (c) 2002-2004 Intel Corp.
7 * Copytight (c) 2005 MontaVista Software, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#ifndef __ASM_ARCH_IXDP2351_H
16#define __ASM_ARCH_IXDP2351_H
17
18/*
19 * NP module memory map
20 */
21#define IXDP2351_NP_PHYS_BASE (IXP23XX_EXP_BUS_CS4_BASE)
22#define IXDP2351_NP_PHYS_SIZE 0x00100000
23#define IXDP2351_NP_VIRT_BASE 0xeff00000
24
25#define IXDP2351_VIRT_CS8900_BASE (IXDP2351_NP_VIRT_BASE)
26#define IXDP2351_VIRT_CS8900_END (IXDP2351_VIRT_CS8900_BASE + 16)
27
28#define IXDP2351_VIRT_NP_CPLD_BASE (IXP23XX_EXP_BUS_CS4_BASE_VIRT + 0x00010000)
29
30#define IXDP2351_NP_CPLD_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_NP_CPLD_BASE + reg))
31
32#define IXDP2351_NP_CPLD_RESET1_REG IXDP2351_NP_CPLD_REG(0x00)
33#define IXDP2351_NP_CPLD_LED_REG IXDP2351_NP_CPLD_REG(0x02)
34#define IXDP2351_NP_CPLD_VERSION_REG IXDP2351_NP_CPLD_REG(0x04)
35
36/*
37 * Base board module memory map
38 */
39
40#define IXDP2351_BB_BASE_PHYS (IXP23XX_EXP_BUS_CS5_BASE)
41#define IXDP2351_BB_SIZE 0x01000000
42#define IXDP2351_BB_BASE_VIRT (0xee000000)
43
44#define IXDP2351_BB_AREA_BASE(offset) (IXDP2351_BB_BASE_VIRT + offset)
45
46#define IXDP2351_VIRT_NVRAM_BASE IXDP2351_BB_AREA_BASE(0x0)
47#define IXDP2351_NVRAM_SIZE (0x20000)
48
49#define IXDP2351_VIRT_MB_IXF1104_BASE IXDP3251_BB_AREA_BASE(0x00020000)
50#define IXDP2351_VIRT_ADD_UART_BASE IXDP2351_BB_AREA_BASE(0x000240C0)
51#define IXDP2351_VIRT_FIC_BASE IXDP2351_BB_AREA_BASE(0x00200000)
52#define IXDP2351_VIRT_DB0_BASE IXDP2351_BB_AREA_BASE(0x00400000)
53#define IXDP2351_VIRT_DB1_BASE IXDP2351_BB_AREA_BASE(0x00600000)
54#define IXDP2351_VIRT_CPLD_BASE IXDP2351_BB_AREA_BASE(0x00024000)
55
56/*
57 * On board CPLD registers
58 */
59#define IXDP2351_CPLD_BB_REG(reg) ((volatile u16 *)(IXDP2351_VIRT_CPLD_BASE + reg))
60
61#define IXDP2351_CPLD_RESET0_REG IXDP2351_CPLD_BB_REG(0x00)
62#define IXDP2351_CPLD_RESET1_REG IXDP2351_CPLD_BB_REG(0x04)
63
64#define IXDP2351_CPLD_RESET1_MAGIC 0x55AA
65#define IXDP2351_CPLD_RESET1_ENABLE 0x8000
66
67#define IXDP2351_CPLD_FPGA_CONFIG_REG IXDP2351_CPLD_BB_REG(0x08)
68#define IXDP2351_CPLD_INTB_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x10)
69#define IXDP2351_CPLD_INTA_MASK_SET_REG IXDP2351_CPLD_BB_REG(0x14)
70#define IXDP2351_CPLD_INTB_STAT_REG IXDP2351_CPLD_BB_REG(0x18)
71#define IXDP2351_CPLD_INTA_STAT_REG IXDP2351_CPLD_BB_REG(0x1C)
72#define IXDP2351_CPLD_INTB_RAW_REG IXDP2351_CPLD_BB_REG(0x20) /* read */
73#define IXDP2351_CPLD_INTA_RAW_REG IXDP2351_CPLD_BB_REG(0x24) /* read */
74#define IXDP2351_CPLD_INTB_MASK_CLR_REG IXDP2351_CPLD_INTB_RAW_REG /* write */
75#define IXDP2351_CPLD_INTA_MASK_CLR_REG IXDP2351_CPLD_INTA_RAW_REG /* write */
76#define IXDP2351_CPLD_INTB_SIM_REG IXDP2351_CPLD_BB_REG(0x28)
77#define IXDP2351_CPLD_INTA_SIM_REG IXDP2351_CPLD_BB_REG(0x2C)
78 /* Interrupt bits are defined in irqs.h */
79#define IXDP2351_CPLD_BB_GBE0_REG IXDP2351_CPLD_BB_REG(0x30)
80#define IXDP2351_CPLD_BB_GBE1_REG IXDP2351_CPLD_BB_REG(0x34)
81
82/* #define IXDP2351_CPLD_BB_MISC_REG IXDP2351_CPLD_REG(0x1C) */
83/* #define IXDP2351_CPLD_BB_MISC_REV_MASK 0xFF */
84/* #define IXDP2351_CPLD_BB_GDXCS0_REG IXDP2351_CPLD_REG(0x24) */
85/* #define IXDP2351_CPLD_BB_GDXCS1_REG IXDP2351_CPLD_REG(0x28) */
86/* #define IXDP2351_CPLD_BB_CLOCK_REG IXDP2351_CPLD_REG(0x04) */
87
88
89#endif
diff --git a/include/asm-arm/arch-ixp23xx/ixp23xx.h b/include/asm-arm/arch-ixp23xx/ixp23xx.h
new file mode 100644
index 000000000000..e49e1ca61b1a
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/ixp23xx.h
@@ -0,0 +1,306 @@
1/*
2 * include/asm-arm/arch-ixp23xx/ixp23xx.h
3 *
4 * Register definitions for IXP23XX
5 *
6 * Copyright (C) 2003-2005 Intel Corporation.
7 * Copyright (C) 2005 MontaVista Software, Inc.
8 *
9 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARCH_IXP23XX_H
17#define __ASM_ARCH_IXP23XX_H
18
19/*
20 * IXP2300 linux memory map:
21 *
22 * virt phys size
23 * fffd0000 a0000000 64K XSI2CPP_CSR
24 * fffc0000 c4000000 4K EXP_CFG
25 * fff00000 c8000000 64K PERIPHERAL
26 * fe000000 1c0000000 16M CAP_CSR
27 * fd000000 1c8000000 16M MSF_CSR
28 * fb000000 16M ---
29 * fa000000 1d8000000 32M PCI_IO
30 * f8000000 1da000000 32M PCI_CFG
31 * f6000000 1de000000 32M PCI_CREG
32 * f4000000 32M ---
33 * f0000000 1e0000000 64M PCI_MEM
34 * e[c-f]000000 per-platform mappings
35 */
36
37
38/****************************************************************************
39 * Static mappings.
40 ****************************************************************************/
41#define IXP23XX_XSI2CPP_CSR_PHYS 0xa0000000
42#define IXP23XX_XSI2CPP_CSR_VIRT 0xfffd0000
43#define IXP23XX_XSI2CPP_CSR_SIZE 0x00010000
44
45#define IXP23XX_EXP_CFG_PHYS 0xc4000000
46#define IXP23XX_EXP_CFG_VIRT 0xfffc0000
47#define IXP23XX_EXP_CFG_SIZE 0x00001000
48
49#define IXP23XX_PERIPHERAL_PHYS 0xc8000000
50#define IXP23XX_PERIPHERAL_VIRT 0xfff00000
51#define IXP23XX_PERIPHERAL_SIZE 0x00010000
52
53#define IXP23XX_CAP_CSR_PHYS 0x1c0000000ULL
54#define IXP23XX_CAP_CSR_VIRT 0xfe000000
55#define IXP23XX_CAP_CSR_SIZE 0x01000000
56
57#define IXP23XX_MSF_CSR_PHYS 0x1c8000000ULL
58#define IXP23XX_MSF_CSR_VIRT 0xfd000000
59#define IXP23XX_MSF_CSR_SIZE 0x01000000
60
61#define IXP23XX_PCI_IO_PHYS 0x1d8000000ULL
62#define IXP23XX_PCI_IO_VIRT 0xfa000000
63#define IXP23XX_PCI_IO_SIZE 0x02000000
64
65#define IXP23XX_PCI_CFG_PHYS 0x1da000000ULL
66#define IXP23XX_PCI_CFG_VIRT 0xf8000000
67#define IXP23XX_PCI_CFG_SIZE 0x02000000
68#define IXP23XX_PCI_CFG0_VIRT IXP23XX_PCI_CFG_VIRT
69#define IXP23XX_PCI_CFG1_VIRT (IXP23XX_PCI_CFG_VIRT + 0x01000000)
70
71#define IXP23XX_PCI_CREG_PHYS 0x1de000000ULL
72#define IXP23XX_PCI_CREG_VIRT 0xf6000000
73#define IXP23XX_PCI_CREG_SIZE 0x02000000
74#define IXP23XX_PCI_CSR_VIRT (IXP23XX_PCI_CREG_VIRT + 0x01000000)
75
76#define IXP23XX_PCI_MEM_START 0xe0000000
77#define IXP23XX_PCI_MEM_PHYS 0x1e0000000ULL
78#define IXP23XX_PCI_MEM_VIRT 0xf0000000
79#define IXP23XX_PCI_MEM_SIZE 0x04000000
80
81
82/****************************************************************************
83 * XSI2CPP CSRs.
84 ****************************************************************************/
85#define IXP23XX_XSI2CPP_REG(x) ((volatile unsigned long *)(IXP23XX_XSI2CPP_CSR_VIRT + (x)))
86#define IXP23XX_CPP2XSI_CURR_XFER_REG3 IXP23XX_XSI2CPP_REG(0xf8)
87#define IXP23XX_CPP2XSI_ADDR_31 (1 << 19)
88#define IXP23XX_CPP2XSI_PSH_OFF (1 << 20)
89#define IXP23XX_CPP2XSI_COH_OFF (1 << 21)
90
91
92/****************************************************************************
93 * Expansion Bus Config.
94 ****************************************************************************/
95#define IXP23XX_EXP_CFG_REG(x) ((volatile unsigned long *)(IXP23XX_EXP_CFG_VIRT + (x)))
96#define IXP23XX_EXP_CS0 IXP23XX_EXP_CFG_REG(0x00)
97#define IXP23XX_EXP_CS1 IXP23XX_EXP_CFG_REG(0x04)
98#define IXP23XX_EXP_CS2 IXP23XX_EXP_CFG_REG(0x08)
99#define IXP23XX_EXP_CS3 IXP23XX_EXP_CFG_REG(0x0c)
100#define IXP23XX_EXP_CS4 IXP23XX_EXP_CFG_REG(0x10)
101#define IXP23XX_EXP_CS5 IXP23XX_EXP_CFG_REG(0x14)
102#define IXP23XX_EXP_CS6 IXP23XX_EXP_CFG_REG(0x18)
103#define IXP23XX_EXP_CS7 IXP23XX_EXP_CFG_REG(0x1c)
104#define IXP23XX_FLASH_WRITABLE (0x2)
105#define IXP23XX_FLASH_BUS8 (0x1)
106
107#define IXP23XX_EXP_CFG0 IXP23XX_EXP_CFG_REG(0x20)
108#define IXP23XX_EXP_CFG1 IXP23XX_EXP_CFG_REG(0x24)
109#define IXP23XX_EXP_CFG0_MEM_MAP (1 << 31)
110#define IXP23XX_EXP_CFG0_XSCALE_SPEED_SEL (3 << 22)
111#define IXP23XX_EXP_CFG0_XSCALE_SPEED_EN (1 << 21)
112#define IXP23XX_EXP_CFG0_CPP_SPEED_SEL (3 << 19)
113#define IXP23XX_EXP_CFG0_CPP_SPEED_EN (1 << 18)
114#define IXP23XX_EXP_CFG0_PCI_SWIN (3 << 16)
115#define IXP23XX_EXP_CFG0_PCI_DWIN (3 << 14)
116#define IXP23XX_EXP_CFG0_PCI33_MODE (1 << 13)
117#define IXP23XX_EXP_CFG0_QDR_SPEED_SEL (1 << 12)
118#define IXP23XX_EXP_CFG0_CPP_DIV_SEL (1 << 5)
119#define IXP23XX_EXP_CFG0_XSI_NOT_PRES (1 << 4)
120#define IXP23XX_EXP_CFG0_PROM_BOOT (1 << 3)
121#define IXP23XX_EXP_CFG0_PCI_ARB (1 << 2)
122#define IXP23XX_EXP_CFG0_PCI_HOST (1 << 1)
123#define IXP23XX_EXP_CFG0_FLASH_WIDTH (1 << 0)
124
125#define IXP23XX_EXP_UNIT_FUSE IXP23XX_EXP_CFG_REG(0x28)
126#define IXP23XX_EXP_MSF_MUX IXP23XX_EXP_CFG_REG(0x30)
127
128#define IXP23XX_EXP_BUS_PHYS 0x90000000
129#define IXP23XX_EXP_BUS_WINDOW_SIZE 0x01000000
130
131#define IXP23XX_EXP_BUS_CS0_BASE (IXP23XX_EXP_BUS_PHYS + 0x00000000)
132#define IXP23XX_EXP_BUS_CS1_BASE (IXP23XX_EXP_BUS_PHYS + 0x01000000)
133#define IXP23XX_EXP_BUS_CS2_BASE (IXP23XX_EXP_BUS_PHYS + 0x02000000)
134#define IXP23XX_EXP_BUS_CS3_BASE (IXP23XX_EXP_BUS_PHYS + 0x03000000)
135#define IXP23XX_EXP_BUS_CS4_BASE (IXP23XX_EXP_BUS_PHYS + 0x04000000)
136#define IXP23XX_EXP_BUS_CS5_BASE (IXP23XX_EXP_BUS_PHYS + 0x05000000)
137#define IXP23XX_EXP_BUS_CS6_BASE (IXP23XX_EXP_BUS_PHYS + 0x06000000)
138#define IXP23XX_EXP_BUS_CS7_BASE (IXP23XX_EXP_BUS_PHYS + 0x07000000)
139
140
141/****************************************************************************
142 * Peripherals.
143 ****************************************************************************/
144#define IXP23XX_UART1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x0000)
145#define IXP23XX_UART2_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x1000)
146#define IXP23XX_PMU_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x2000)
147#define IXP23XX_INTC_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x3000)
148#define IXP23XX_GPIO_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x4000)
149#define IXP23XX_TIMER_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x5000)
150#define IXP23XX_NPE0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x6000)
151#define IXP23XX_DSR_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x7000)
152#define IXP23XX_NPE1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x8000)
153#define IXP23XX_ETH0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0x9000)
154#define IXP23XX_ETH1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xA000)
155#define IXP23XX_GIG0_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xB000)
156#define IXP23XX_GIG1_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xC000)
157#define IXP23XX_DDRS_VIRT (IXP23XX_PERIPHERAL_VIRT + 0xD000)
158
159#define IXP23XX_UART1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x0000)
160#define IXP23XX_UART2_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x1000)
161#define IXP23XX_PMU_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x2000)
162#define IXP23XX_INTC_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x3000)
163#define IXP23XX_GPIO_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x4000)
164#define IXP23XX_TIMER_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x5000)
165#define IXP23XX_NPE0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x6000)
166#define IXP23XX_DSR_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x7000)
167#define IXP23XX_NPE1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x8000)
168#define IXP23XX_ETH0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0x9000)
169#define IXP23XX_ETH1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xA000)
170#define IXP23XX_GIG0_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xB000)
171#define IXP23XX_GIG1_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xC000)
172#define IXP23XX_DDRS_PHYS (IXP23XX_PERIPHERAL_PHYS + 0xD000)
173
174
175/****************************************************************************
176 * Interrupt controller.
177 ****************************************************************************/
178#define IXP23XX_INTC_REG(x) ((volatile unsigned long *)(IXP23XX_INTC_VIRT + (x)))
179#define IXP23XX_INTR_ST1 IXP23XX_INTC_REG(0x00)
180#define IXP23XX_INTR_ST2 IXP23XX_INTC_REG(0x04)
181#define IXP23XX_INTR_ST3 IXP23XX_INTC_REG(0x08)
182#define IXP23XX_INTR_ST4 IXP23XX_INTC_REG(0x0c)
183#define IXP23XX_INTR_EN1 IXP23XX_INTC_REG(0x10)
184#define IXP23XX_INTR_EN2 IXP23XX_INTC_REG(0x14)
185#define IXP23XX_INTR_EN3 IXP23XX_INTC_REG(0x18)
186#define IXP23XX_INTR_EN4 IXP23XX_INTC_REG(0x1c)
187#define IXP23XX_INTR_SEL1 IXP23XX_INTC_REG(0x20)
188#define IXP23XX_INTR_SEL2 IXP23XX_INTC_REG(0x24)
189#define IXP23XX_INTR_SEL3 IXP23XX_INTC_REG(0x28)
190#define IXP23XX_INTR_SEL4 IXP23XX_INTC_REG(0x2c)
191#define IXP23XX_INTR_IRQ_ST1 IXP23XX_INTC_REG(0x30)
192#define IXP23XX_INTR_IRQ_ST2 IXP23XX_INTC_REG(0x34)
193#define IXP23XX_INTR_IRQ_ST3 IXP23XX_INTC_REG(0x38)
194#define IXP23XX_INTR_IRQ_ST4 IXP23XX_INTC_REG(0x3c)
195#define IXP23XX_INTR_IRQ_ENC_ST_OFFSET 0x54
196
197
198/****************************************************************************
199 * GPIO.
200 ****************************************************************************/
201#define IXP23XX_GPIO_REG(x) ((volatile unsigned long *)(IXP23XX_GPIO_VIRT + (x)))
202#define IXP23XX_GPIO_GPOUTR IXP23XX_GPIO_REG(0x00)
203#define IXP23XX_GPIO_GPOER IXP23XX_GPIO_REG(0x04)
204#define IXP23XX_GPIO_GPINR IXP23XX_GPIO_REG(0x08)
205#define IXP23XX_GPIO_GPISR IXP23XX_GPIO_REG(0x0c)
206#define IXP23XX_GPIO_GPIT1R IXP23XX_GPIO_REG(0x10)
207#define IXP23XX_GPIO_GPIT2R IXP23XX_GPIO_REG(0x14)
208#define IXP23XX_GPIO_GPCLKR IXP23XX_GPIO_REG(0x18)
209#define IXP23XX_GPIO_GPDBSELR IXP23XX_GPIO_REG(0x1c)
210
211#define IXP23XX_GPIO_STYLE_MASK 0x7
212#define IXP23XX_GPIO_STYLE_ACTIVE_HIGH 0x0
213#define IXP23XX_GPIO_STYLE_ACTIVE_LOW 0x1
214#define IXP23XX_GPIO_STYLE_RISING_EDGE 0x2
215#define IXP23XX_GPIO_STYLE_FALLING_EDGE 0x3
216#define IXP23XX_GPIO_STYLE_TRANSITIONAL 0x4
217
218#define IXP23XX_GPIO_STYLE_SIZE 3
219
220
221/****************************************************************************
222 * Timer.
223 ****************************************************************************/
224#define IXP23XX_TIMER_REG(x) ((volatile unsigned long *)(IXP23XX_TIMER_VIRT + (x)))
225#define IXP23XX_TIMER_CONT IXP23XX_TIMER_REG(0x00)
226#define IXP23XX_TIMER1_TIMESTAMP IXP23XX_TIMER_REG(0x04)
227#define IXP23XX_TIMER1_RELOAD IXP23XX_TIMER_REG(0x08)
228#define IXP23XX_TIMER2_TIMESTAMP IXP23XX_TIMER_REG(0x0c)
229#define IXP23XX_TIMER2_RELOAD IXP23XX_TIMER_REG(0x10)
230#define IXP23XX_TIMER_WDOG IXP23XX_TIMER_REG(0x14)
231#define IXP23XX_TIMER_WDOG_EN IXP23XX_TIMER_REG(0x18)
232#define IXP23XX_TIMER_WDOG_KEY IXP23XX_TIMER_REG(0x1c)
233#define IXP23XX_TIMER_WDOG_KEY_MAGIC 0x482e
234#define IXP23XX_TIMER_STATUS IXP23XX_TIMER_REG(0x20)
235#define IXP23XX_TIMER_SOFT_RESET IXP23XX_TIMER_REG(0x24)
236#define IXP23XX_TIMER_SOFT_RESET_EN IXP23XX_TIMER_REG(0x28)
237
238#define IXP23XX_TIMER_ENABLE (1 << 0)
239#define IXP23XX_TIMER_ONE_SHOT (1 << 1)
240/* Low order bits of reload value ignored */
241#define IXP23XX_TIMER_RELOAD_MASK (0x3)
242#define IXP23XX_TIMER_DISABLED (0x0)
243#define IXP23XX_TIMER1_INT_PEND (1 << 0)
244#define IXP23XX_TIMER2_INT_PEND (1 << 1)
245#define IXP23XX_TIMER_STATUS_TS_PEND (1 << 2)
246#define IXP23XX_TIMER_STATUS_WDOG_PEND (1 << 3)
247#define IXP23XX_TIMER_STATUS_WARM_RESET (1 << 4)
248
249
250/****************************************************************************
251 * CAP CSRs.
252 ****************************************************************************/
253#define IXP23XX_GLOBAL_REG(x) ((volatile unsigned long *)(IXP23XX_CAP_CSR_VIRT + 0x4a00 + (x)))
254#define IXP23XX_PROD_IDG IXP23XX_GLOBAL_REG(0x00)
255#define IXP23XX_MISC_CONTROL IXP23XX_GLOBAL_REG(0x04)
256#define IXP23XX_MSF_CLK_CNTRL IXP23XX_GLOBAL_REG(0x08)
257#define IXP23XX_RESET0 IXP23XX_GLOBAL_REG(0x0c)
258#define IXP23XX_RESET1 IXP23XX_GLOBAL_REG(0x10)
259#define IXP23XX_STRAP_OPTIONS IXP23XX_GLOBAL_REG(0x18)
260
261#define IXP23XX_ENABLE_WATCHDOG (1 << 24)
262#define IXP23XX_SHPC_INIT_COMP (1 << 21)
263#define IXP23XX_RST_ALL (1 << 16)
264#define IXP23XX_RESET_PCI (1 << 2)
265#define IXP23XX_PCI_UNIT_RESET (1 << 1)
266#define IXP23XX_XSCALE_RESET (1 << 0)
267
268
269/****************************************************************************
270 * PCI CSRs.
271 ****************************************************************************/
272#define IXP23XX_PCI_CREG(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + (x)))
273#define IXP23XX_PCI_CMDSTAT IXP23XX_PCI_CREG(0x04)
274#define IXP23XX_PCI_SRAM_BAR IXP23XX_PCI_CREG(0x14)
275#define IXP23XX_PCI_SDRAM_BAR IXP23XX_PCI_CREG(0x18)
276
277
278#define IXP23XX_PCI_CSR(x) ((volatile unsigned long *)(IXP23XX_PCI_CREG_VIRT + 0x01000000 + (x)))
279#define IXP23XX_PCI_OUT_INT_STATUS IXP23XX_PCI_CSR(0x0030)
280#define IXP23XX_PCI_OUT_INT_MASK IXP23XX_PCI_CSR(0x0034)
281#define IXP23XX_PCI_SRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x00fc)
282#define IXP23XX_PCI_DRAM_BASE_ADDR_MASK IXP23XX_PCI_CSR(0x0100)
283#define IXP23XX_PCI_CONTROL IXP23XX_PCI_CSR(0x013c)
284#define IXP23XX_PCI_ADDR_EXT IXP23XX_PCI_CSR(0x0140)
285#define IXP23XX_PCI_ME_PUSH_STATUS IXP23XX_PCI_CSR(0x0148)
286#define IXP23XX_PCI_ME_PUSH_EN IXP23XX_PCI_CSR(0x014c)
287#define IXP23XX_PCI_ERR_STATUS IXP23XX_PCI_CSR(0x0150)
288#define IXP23XX_PCI_ERROR_STATUS IXP23XX_PCI_CSR(0x0150)
289#define IXP23XX_PCI_ERR_ENABLE IXP23XX_PCI_CSR(0x0154)
290#define IXP23XX_PCI_XSCALE_INT_STATUS IXP23XX_PCI_CSR(0x0158)
291#define IXP23XX_PCI_XSCALE_INT_ENABLE IXP23XX_PCI_CSR(0x015c)
292#define IXP23XX_PCI_CPP_ADDR_BITS IXP23XX_PCI_CSR(0x0160)
293
294
295#ifndef __ASSEMBLY__
296/*
297 * Is system memory on the XSI or CPP bus?
298 */
299static inline unsigned ixp23xx_cpp_boot(void)
300{
301 return (*IXP23XX_EXP_CFG0 & IXP23XX_EXP_CFG0_XSI_NOT_PRES);
302}
303#endif
304
305
306#endif
diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h
new file mode 100644
index 000000000000..bebcf0aa0d72
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/memory.h
@@ -0,0 +1,46 @@
1/*
2 * include/asm-arm/arch-ixp23xx/memory.h
3 *
4 * Copyright (c) 2003-2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef __ASM_ARCH_MEMORY_H
13#define __ASM_ARCH_MEMORY_H
14
15#include <asm/hardware.h>
16
17/*
18 * Physical DRAM offset.
19 */
20#define PHYS_OFFSET (0x00000000)
21
22
23/*
24 * Virtual view <-> DMA view memory address translations
25 * virt_to_bus: Used to translate the virtual address to an
26 * address suitable to be passed to set_dma_addr
27 * bus_to_virt: Used to convert an address for DMA operations
28 * to an address that the kernel can use.
29 */
30#ifndef __ASSEMBLY__
31
32#define __virt_to_bus(v) \
33 ({ unsigned int ret; \
34 ret = ((__virt_to_phys(v) - 0x00000000) + \
35 (*((volatile int *)IXP23XX_PCI_SDRAM_BAR) & 0xfffffff0)); \
36 ret; })
37
38#define __bus_to_virt(b) \
39 ({ unsigned int data; \
40 data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \
41 __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); })
42
43#endif
44
45
46#endif
diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h
new file mode 100644
index 000000000000..f85b4685a491
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/platform.h
@@ -0,0 +1,31 @@
1/*
2 * include/asm-arm/arch-ixp23xx/platform.h
3 *
4 * Various bits of code used by platform-level code.
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASSEMBLY__
16
17struct pci_sys_data;
18
19void ixp23xx_map_io(void);
20void ixp23xx_init_irq(void);
21void ixp23xx_sys_init(void);
22int ixp23xx_pci_setup(int, struct pci_sys_data *);
23void ixp23xx_pci_preinit(void);
24struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*);
25
26extern struct sys_timer ixp23xx_timer;
27
28#define IXP23XX_UART_XTAL 14745600
29
30
31#endif
diff --git a/include/asm-arm/arch-ixp23xx/system.h b/include/asm-arm/arch-ixp23xx/system.h
new file mode 100644
index 000000000000..925e6b0c338b
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/system.h
@@ -0,0 +1,33 @@
1/*
2 * include/asm-arm/arch-ixp23xx/system.h
3 *
4 * Copyright (C) 2003 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <asm/hardware.h>
12#include <asm/mach-types.h>
13
14static inline void arch_idle(void)
15{
16#if 0
17 if (!hlt_counter)
18 cpu_do_idle();
19#endif
20}
21
22static inline void arch_reset(char mode)
23{
24 /* First try machine specific support */
25 if (machine_is_ixdp2351()) {
26 *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC;
27 (void) *IXDP2351_CPLD_RESET1_REG;
28 *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE;
29 }
30
31 /* Use on-chip reset capability */
32 *IXP23XX_RESET0 |= IXP23XX_RST_ALL;
33}
diff --git a/include/asm-arm/arch-ixp23xx/time.h b/include/asm-arm/arch-ixp23xx/time.h
new file mode 100644
index 000000000000..f6828fdd2883
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/time.h
@@ -0,0 +1,3 @@
1/*
2 * include/asm-arm/arch-ixp23xx/time.h
3 */
diff --git a/include/asm-arm/arch-ixp23xx/timex.h b/include/asm-arm/arch-ixp23xx/timex.h
new file mode 100644
index 000000000000..516f72fe6082
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/timex.h
@@ -0,0 +1,7 @@
1/*
2 * include/asm-arm/arch-ixp23xx/timex.h
3 *
4 * XScale architecture timex specifications
5 */
6
7#define CLOCK_TICK_RATE 75000000
diff --git a/include/asm-arm/arch-ixp23xx/uncompress.h b/include/asm-arm/arch-ixp23xx/uncompress.h
new file mode 100644
index 000000000000..62623fa9b2f7
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/uncompress.h
@@ -0,0 +1,45 @@
1/*
2 * include/asm-arm/arch-ixp23xx/uncompress.h
3 *
4 * Copyright (C) 2002-2004 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_UNCOMPRESS_H
12#define __ASM_ARCH_UNCOMPRESS_H
13
14#include <asm/hardware.h>
15#include <linux/serial_reg.h>
16
17#define UART_BASE ((volatile u32 *)IXP23XX_UART1_PHYS)
18
19static __inline__ void putc(char c)
20{
21 int j;
22
23 for (j = 0; j < 0x1000; j++) {
24 if (UART_BASE[UART_LSR] & UART_LSR_THRE)
25 break;
26 }
27
28 UART_BASE[UART_TX] = c;
29}
30
31static void putstr(const char *s)
32{
33 while (*s) {
34 putc(*s);
35 if (*s == '\n')
36 putc('\r');
37 s++;
38 }
39}
40
41#define arch_decomp_setup()
42#define arch_decomp_wdog()
43
44
45#endif
diff --git a/include/asm-arm/arch-ixp23xx/vmalloc.h b/include/asm-arm/arch-ixp23xx/vmalloc.h
new file mode 100644
index 000000000000..9f2566658541
--- /dev/null
+++ b/include/asm-arm/arch-ixp23xx/vmalloc.h
@@ -0,0 +1,10 @@
1/*
2 * include/asm-arm/arch-ixp23xx/vmalloc.h
3 *
4 * Copyright (c) 2005 MontaVista Software, Inc.
5 *
6 * NPU mappings end at 0xf0000000 and we allocate 64MB for board
7 * specific static I/O.
8 */
9
10#define VMALLOC_END (0xec000000)
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 03:34:07 -0400