diff options
-rw-r--r-- | arch/blackfin/kernel/cplbinit.c | 42 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf527/mem_map.h | 1 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf533/mem_map.h | 2 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf537/mem_map.h | 1 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/mem_map.h | 11 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf561/bf561.h | 19 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf561/mem_map.h | 5 |
7 files changed, 45 insertions, 36 deletions
diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplbinit.c index 959b510c5ffb..6320bc45fbba 100644 --- a/arch/blackfin/kernel/cplbinit.c +++ b/arch/blackfin/kernel/cplbinit.c | |||
@@ -64,7 +64,7 @@ static struct cplb_desc cplb_data[] = { | |||
64 | #else | 64 | #else |
65 | .valid = 0, | 65 | .valid = 0, |
66 | #endif | 66 | #endif |
67 | .name = "ZERO Pointer Saveguard", | 67 | .name = "Zero Pointer Guard Page", |
68 | }, | 68 | }, |
69 | { | 69 | { |
70 | .start = L1_CODE_START, | 70 | .start = L1_CODE_START, |
@@ -95,20 +95,20 @@ static struct cplb_desc cplb_data[] = { | |||
95 | .end = 0, /* dynamic */ | 95 | .end = 0, /* dynamic */ |
96 | .psize = 0, | 96 | .psize = 0, |
97 | .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, | 97 | .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB, |
98 | .i_conf = SDRAM_IGENERIC, | 98 | .i_conf = SDRAM_IGENERIC, |
99 | .d_conf = SDRAM_DGENERIC, | 99 | .d_conf = SDRAM_DGENERIC, |
100 | .valid = 1, | 100 | .valid = 1, |
101 | .name = "SDRAM Kernel", | 101 | .name = "Kernel Memory", |
102 | }, | 102 | }, |
103 | { | 103 | { |
104 | .start = 0, /* dynamic */ | 104 | .start = 0, /* dynamic */ |
105 | .end = 0, /* dynamic */ | 105 | .end = 0, /* dynamic */ |
106 | .psize = 0, | 106 | .psize = 0, |
107 | .attr = INITIAL_T | SWITCH_T | D_CPLB, | 107 | .attr = INITIAL_T | SWITCH_T | D_CPLB, |
108 | .i_conf = SDRAM_IGENERIC, | 108 | .i_conf = SDRAM_IGENERIC, |
109 | .d_conf = SDRAM_DNON_CHBL, | 109 | .d_conf = SDRAM_DNON_CHBL, |
110 | .valid = 1, | 110 | .valid = 1, |
111 | .name = "SDRAM RAM MTD", | 111 | .name = "uClinux MTD Memory", |
112 | }, | 112 | }, |
113 | { | 113 | { |
114 | .start = 0, /* dynamic */ | 114 | .start = 0, /* dynamic */ |
@@ -117,7 +117,7 @@ static struct cplb_desc cplb_data[] = { | |||
117 | .attr = INITIAL_T | SWITCH_T | D_CPLB, | 117 | .attr = INITIAL_T | SWITCH_T | D_CPLB, |
118 | .d_conf = SDRAM_DNON_CHBL, | 118 | .d_conf = SDRAM_DNON_CHBL, |
119 | .valid = 1, | 119 | .valid = 1, |
120 | .name = "SDRAM Uncached DMA ZONE", | 120 | .name = "Uncached DMA Zone", |
121 | }, | 121 | }, |
122 | { | 122 | { |
123 | .start = 0, /* dynamic */ | 123 | .start = 0, /* dynamic */ |
@@ -127,7 +127,7 @@ static struct cplb_desc cplb_data[] = { | |||
127 | .i_conf = 0, /* dynamic */ | 127 | .i_conf = 0, /* dynamic */ |
128 | .d_conf = 0, /* dynamic */ | 128 | .d_conf = 0, /* dynamic */ |
129 | .valid = 1, | 129 | .valid = 1, |
130 | .name = "SDRAM Reserved Memory", | 130 | .name = "Reserved Memory", |
131 | }, | 131 | }, |
132 | { | 132 | { |
133 | .start = ASYNC_BANK0_BASE, | 133 | .start = ASYNC_BANK0_BASE, |
@@ -136,14 +136,14 @@ static struct cplb_desc cplb_data[] = { | |||
136 | .attr = SWITCH_T | D_CPLB, | 136 | .attr = SWITCH_T | D_CPLB, |
137 | .d_conf = SDRAM_EBIU, | 137 | .d_conf = SDRAM_EBIU, |
138 | .valid = 1, | 138 | .valid = 1, |
139 | .name = "ASYNC Memory", | 139 | .name = "Asynchronous Memory Banks", |
140 | }, | 140 | }, |
141 | { | 141 | { |
142 | #if defined(CONFIG_BF561) | 142 | #ifdef L2_START |
143 | .start = L2_SRAM, | 143 | .start = L2_START, |
144 | .end = L2_SRAM_END, | 144 | .end = L2_START + L2_LENGTH, |
145 | .psize = SIZE_1M, | 145 | .psize = SIZE_1M, |
146 | .attr = SWITCH_T | D_CPLB, | 146 | .attr = SWITCH_T | I_CPLB | D_CPLB, |
147 | .i_conf = L2_MEMORY, | 147 | .i_conf = L2_MEMORY, |
148 | .d_conf = L2_MEMORY, | 148 | .d_conf = L2_MEMORY, |
149 | .valid = 1, | 149 | .valid = 1, |
@@ -151,7 +151,17 @@ static struct cplb_desc cplb_data[] = { | |||
151 | .valid = 0, | 151 | .valid = 0, |
152 | #endif | 152 | #endif |
153 | .name = "L2 Memory", | 153 | .name = "L2 Memory", |
154 | } | 154 | }, |
155 | { | ||
156 | .start = BOOT_ROM_START, | ||
157 | .end = BOOT_ROM_START + BOOT_ROM_LENGTH, | ||
158 | .psize = SIZE_1M, | ||
159 | .attr = SWITCH_T | I_CPLB | D_CPLB, | ||
160 | .i_conf = SDRAM_IGENERIC, | ||
161 | .d_conf = SDRAM_DGENERIC, | ||
162 | .valid = 1, | ||
163 | .name = "On-Chip BootROM", | ||
164 | }, | ||
155 | }; | 165 | }; |
156 | 166 | ||
157 | static u16 __init lock_kernel_check(u32 start, u32 end) | 167 | static u16 __init lock_kernel_check(u32 start, u32 end) |
@@ -343,7 +353,7 @@ void __init generate_cpl_tables(void) | |||
343 | else | 353 | else |
344 | cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL; | 354 | cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL; |
345 | 355 | ||
346 | for (i = ZERO_P; i <= L2_MEM; i++) { | 356 | for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) { |
347 | if (!cplb_data[i].valid) | 357 | if (!cplb_data[i].valid) |
348 | continue; | 358 | continue; |
349 | 359 | ||
diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h index bb046984231e..193082deaa4e 100644 --- a/include/asm-blackfin/mach-bf527/mem_map.h +++ b/include/asm-blackfin/mach-bf527/mem_map.h | |||
@@ -47,6 +47,7 @@ | |||
47 | /* Boot ROM Memory */ | 47 | /* Boot ROM Memory */ |
48 | 48 | ||
49 | #define BOOT_ROM_START 0xEF000000 | 49 | #define BOOT_ROM_START 0xEF000000 |
50 | #define BOOT_ROM_LENGTH 0x8000 | ||
50 | 51 | ||
51 | /* Level 1 Memory */ | 52 | /* Level 1 Memory */ |
52 | 53 | ||
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h index 8daf6d4bf093..bd30b6f3be00 100644 --- a/include/asm-blackfin/mach-bf533/mem_map.h +++ b/include/asm-blackfin/mach-bf533/mem_map.h | |||
@@ -1,4 +1,3 @@ | |||
1 | |||
2 | /* | 1 | /* |
3 | * File: include/asm-blackfin/mach-bf533/mem_map.h | 2 | * File: include/asm-blackfin/mach-bf533/mem_map.h |
4 | * Based on: | 3 | * Based on: |
@@ -48,6 +47,7 @@ | |||
48 | /* Boot ROM Memory */ | 47 | /* Boot ROM Memory */ |
49 | 48 | ||
50 | #define BOOT_ROM_START 0xEF000000 | 49 | #define BOOT_ROM_START 0xEF000000 |
50 | #define BOOT_ROM_LENGTH 0x400 | ||
51 | 51 | ||
52 | /* Level 1 Memory */ | 52 | /* Level 1 Memory */ |
53 | 53 | ||
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h index f5facdad4442..5c6726d6f3b1 100644 --- a/include/asm-blackfin/mach-bf537/mem_map.h +++ b/include/asm-blackfin/mach-bf537/mem_map.h | |||
@@ -47,6 +47,7 @@ | |||
47 | /* Boot ROM Memory */ | 47 | /* Boot ROM Memory */ |
48 | 48 | ||
49 | #define BOOT_ROM_START 0xEF000000 | 49 | #define BOOT_ROM_START 0xEF000000 |
50 | #define BOOT_ROM_LENGTH 0x800 | ||
50 | 51 | ||
51 | /* Level 1 Memory */ | 52 | /* Level 1 Memory */ |
52 | 53 | ||
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h index bacec3455898..00752f774986 100644 --- a/include/asm-blackfin/mach-bf548/mem_map.h +++ b/include/asm-blackfin/mach-bf548/mem_map.h | |||
@@ -47,6 +47,7 @@ | |||
47 | /* Boot ROM Memory */ | 47 | /* Boot ROM Memory */ |
48 | 48 | ||
49 | #define BOOT_ROM_START 0xEF000000 | 49 | #define BOOT_ROM_START 0xEF000000 |
50 | #define BOOT_ROM_LENGTH 0x1000 | ||
50 | 51 | ||
51 | /* Level 1 Memory */ | 52 | /* Level 1 Memory */ |
52 | 53 | ||
@@ -87,6 +88,16 @@ | |||
87 | #define BFIN_DSUPBANKS 0 | 88 | #define BFIN_DSUPBANKS 0 |
88 | #endif /*CONFIG_BFIN_DCACHE*/ | 89 | #endif /*CONFIG_BFIN_DCACHE*/ |
89 | 90 | ||
91 | /* Level 2 Memory */ | ||
92 | #if !defined(CONFIG_BF542) | ||
93 | # define L2_START 0xFEB00000 | ||
94 | # if defined(CONFIG_BF544) | ||
95 | # define L2_LENGTH 0x10000 | ||
96 | # else | ||
97 | # define L2_LENGTH 0x20000 | ||
98 | # endif | ||
99 | #endif | ||
100 | |||
90 | /* Scratch Pad Memory */ | 101 | /* Scratch Pad Memory */ |
91 | 102 | ||
92 | #define L1_SCRATCH_START 0xFFB00000 | 103 | #define L1_SCRATCH_START 0xFFB00000 |
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h index 17e1d5dcef02..3ef9e5f36136 100644 --- a/include/asm-blackfin/mach-bf561/bf561.h +++ b/include/asm-blackfin/mach-bf561/bf561.h | |||
@@ -33,25 +33,6 @@ | |||
33 | #define SUPPORTED_REVID 0x3 | 33 | #define SUPPORTED_REVID 0x3 |
34 | 34 | ||
35 | #define OFFSET_(x) ((x) & 0x0000FFFF) | 35 | #define OFFSET_(x) ((x) & 0x0000FFFF) |
36 | #define L1_ISRAM 0xFFA00000 | ||
37 | #define L1_ISRAM_END 0xFFA04000 | ||
38 | #define DATA_BANKA_SRAM 0xFF800000 | ||
39 | #define DATA_BANKA_SRAM_END 0xFF804000 | ||
40 | #define DATA_BANKB_SRAM 0xFF900000 | ||
41 | #define DATA_BANKB_SRAM_END 0xFF904000 | ||
42 | #define L1_DSRAMA 0xFF800000 | ||
43 | #define L1_DSRAMA_END 0xFF804000 | ||
44 | #define L1_DSRAMB 0xFF900000 | ||
45 | #define L1_DSRAMB_END 0xFF904000 | ||
46 | #define L2_SRAM 0xFEB00000 | ||
47 | #define L2_SRAM_END 0xFEB20000 | ||
48 | #define AMB_FLASH 0x20000000 | ||
49 | #define AMB_FLASH_END 0x21000000 | ||
50 | #define AMB_FLASH_LENGTH 0x01000000 | ||
51 | #define L1_ISRAM_LENGTH 0x4000 | ||
52 | #define L1_DSRAMA_LENGTH 0x4000 | ||
53 | #define L1_DSRAMB_LENGTH 0x4000 | ||
54 | #define L2_SRAM_LENGTH 0x20000 | ||
55 | 36 | ||
56 | /*some misc defines*/ | 37 | /*some misc defines*/ |
57 | #define IMASK_IVG15 0x8000 | 38 | #define IMASK_IVG15 0x8000 |
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h index 300a3a90d61c..c26d8486cc4b 100644 --- a/include/asm-blackfin/mach-bf561/mem_map.h +++ b/include/asm-blackfin/mach-bf561/mem_map.h | |||
@@ -19,6 +19,11 @@ | |||
19 | #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ | 19 | #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ |
20 | #define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ | 20 | #define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ |
21 | 21 | ||
22 | /* Boot ROM Memory */ | ||
23 | |||
24 | #define BOOT_ROM_START 0xEF000000 | ||
25 | #define BOOT_ROM_LENGTH 0x800 | ||
26 | |||
22 | /* Level 1 Memory */ | 27 | /* Level 1 Memory */ |
23 | 28 | ||
24 | #ifdef CONFIG_BFIN_ICACHE | 29 | #ifdef CONFIG_BFIN_ICACHE |