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-rw-r--r--drivers/net/bnx2x_hsi.h45
-rw-r--r--drivers/net/bnx2x_link.c130
-rw-r--r--drivers/net/bnx2x_link.h4
-rw-r--r--drivers/net/bnx2x_main.c31
-rw-r--r--drivers/net/bnx2x_reg.h36
5 files changed, 177 insertions, 69 deletions
diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
index 7a62bfd18aa8..8452605d0588 100644
--- a/drivers/net/bnx2x_hsi.h
+++ b/drivers/net/bnx2x_hsi.h
@@ -178,36 +178,21 @@ struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
178 u32 rdma_mac_lower; 178 u32 rdma_mac_lower;
179 179
180 u32 serdes_config; 180 u32 serdes_config;
181 /* for external PHY, or forced mode or during AN */ 181#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
182#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000 182#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
183#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16 183
184 184#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
185#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff 185#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
186#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0 186
187 187
188 u16 serdes_tx_driver_pre_emphasis[16]; 188 u32 Reserved0[16]; /* 0x158 */
189 u16 serdes_rx_driver_equalizer[16]; 189
190 190 /* for external PHY, or forced mode or during AN */
191 u32 xgxs_config_lane0; 191 u16 xgxs_config_rx[4]; /* 0x198 */
192 u32 xgxs_config_lane1; 192
193 u32 xgxs_config_lane2; 193 u16 xgxs_config_tx[4]; /* 0x1A0 */
194 u32 xgxs_config_lane3; 194
195 /* for external PHY, or forced mode or during AN */ 195 u32 Reserved1[64]; /* 0x1A8 */
196#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
197#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16
198
199#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff
200#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0
201
202 u16 xgxs_tx_driver_pre_emphasis_lane0[16];
203 u16 xgxs_tx_driver_pre_emphasis_lane1[16];
204 u16 xgxs_tx_driver_pre_emphasis_lane2[16];
205 u16 xgxs_tx_driver_pre_emphasis_lane3[16];
206
207 u16 xgxs_rx_driver_equalizer_lane0[16];
208 u16 xgxs_rx_driver_equalizer_lane1[16];
209 u16 xgxs_rx_driver_equalizer_lane2[16];
210 u16 xgxs_rx_driver_equalizer_lane3[16];
211 196
212 u32 lane_config; 197 u32 lane_config;
213#define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff 198#define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c
index b61a7a24ecc5..4a594b84ba20 100644
--- a/drivers/net/bnx2x_link.c
+++ b/drivers/net/bnx2x_link.c
@@ -1758,33 +1758,39 @@ static void bnx2x_set_gmii_tx_driver(struct link_params *params)
1758 struct bnx2x *bp = params->bp; 1758 struct bnx2x *bp = params->bp;
1759 u16 lp_up2; 1759 u16 lp_up2;
1760 u16 tx_driver; 1760 u16 tx_driver;
1761 u16 bank;
1761 1762
1762 /* read precomp */ 1763 /* read precomp */
1763
1764 CL45_RD_OVER_CL22(bp, params->port, 1764 CL45_RD_OVER_CL22(bp, params->port,
1765 params->phy_addr, 1765 params->phy_addr,
1766 MDIO_REG_BANK_OVER_1G, 1766 MDIO_REG_BANK_OVER_1G,
1767 MDIO_OVER_1G_LP_UP2, &lp_up2); 1767 MDIO_OVER_1G_LP_UP2, &lp_up2);
1768 1768
1769 CL45_RD_OVER_CL22(bp, params->port,
1770 params->phy_addr,
1771 MDIO_REG_BANK_TX0,
1772 MDIO_TX0_TX_DRIVER, &tx_driver);
1773
1774 /* bits [10:7] at lp_up2, positioned at [15:12] */ 1769 /* bits [10:7] at lp_up2, positioned at [15:12] */
1775 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 1770 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
1776 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 1771 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
1777 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 1772 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
1778 1773
1779 if ((lp_up2 != 0) && 1774 if (lp_up2 == 0)
1780 (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK))) { 1775 return;
1781 /* replace tx_driver bits [15:12] */ 1776
1782 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 1777 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
1783 tx_driver |= lp_up2; 1778 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
1784 CL45_WR_OVER_CL22(bp, params->port, 1779 CL45_RD_OVER_CL22(bp, params->port,
1785 params->phy_addr, 1780 params->phy_addr,
1786 MDIO_REG_BANK_TX0, 1781 bank,
1787 MDIO_TX0_TX_DRIVER, tx_driver); 1782 MDIO_TX0_TX_DRIVER, &tx_driver);
1783
1784 /* replace tx_driver bits [15:12] */
1785 if (lp_up2 !=
1786 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
1787 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
1788 tx_driver |= lp_up2;
1789 CL45_WR_OVER_CL22(bp, params->port,
1790 params->phy_addr,
1791 bank,
1792 MDIO_TX0_TX_DRIVER, tx_driver);
1793 }
1788 } 1794 }
1789} 1795}
1790 1796
@@ -2890,31 +2896,40 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
2890 MDIO_AN_DEVAD, 2896 MDIO_AN_DEVAD,
2891 MDIO_AN_REG_ADV_PAUSE, val); 2897 MDIO_AN_REG_ADV_PAUSE, val);
2892} 2898}
2899static void bnx2x_set_preemphasis(struct link_params *params)
2900{
2901 u16 bank, i = 0;
2902 struct bnx2x *bp = params->bp;
2893 2903
2904 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
2905 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
2906 CL45_WR_OVER_CL22(bp, params->port,
2907 params->phy_addr,
2908 bank,
2909 MDIO_RX0_RX_EQ_BOOST,
2910 params->xgxs_config_rx[i]);
2911 }
2912
2913 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
2914 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
2915 CL45_WR_OVER_CL22(bp, params->port,
2916 params->phy_addr,
2917 bank,
2918 MDIO_TX0_TX_DRIVER,
2919 params->xgxs_config_tx[i]);
2920 }
2921}
2894 2922
2895static void bnx2x_init_internal_phy(struct link_params *params, 2923static void bnx2x_init_internal_phy(struct link_params *params,
2896 struct link_vars *vars) 2924 struct link_vars *vars)
2897{ 2925{
2898 struct bnx2x *bp = params->bp; 2926 struct bnx2x *bp = params->bp;
2899 u8 port = params->port;
2900 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 2927 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2901 u16 bank, rx_eq; 2928 if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
2902 2929 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
2903 rx_eq = ((params->serdes_config & 2930 (params->feature_config_flags &
2904 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >> 2931 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2905 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT); 2932 bnx2x_set_preemphasis(params);
2906
2907 DP(NETIF_MSG_LINK, "setting rx eq to 0x%x\n", rx_eq);
2908 for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
2909 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0)) {
2910 CL45_WR_OVER_CL22(bp, port,
2911 params->phy_addr,
2912 bank ,
2913 MDIO_RX0_RX_EQ_BOOST,
2914 ((rx_eq &
2915 MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
2916 MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
2917 }
2918 2933
2919 /* forced speed requested? */ 2934 /* forced speed requested? */
2920 if (vars->line_speed != SPEED_AUTO_NEG) { 2935 if (vars->line_speed != SPEED_AUTO_NEG) {
@@ -3038,6 +3053,35 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3038 } 3053 }
3039 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized " 3054 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized "
3040 "after %d ms\n", cnt); 3055 "after %d ms\n", cnt);
3056 if ((params->feature_config_flags &
3057 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3058 u8 i;
3059 u16 reg;
3060 for (i = 0; i < 4; i++) {
3061 reg = MDIO_XS_8706_REG_BANK_RX0 +
3062 i*(MDIO_XS_8706_REG_BANK_RX1 -
3063 MDIO_XS_8706_REG_BANK_RX0);
3064 bnx2x_cl45_read(bp, params->port,
3065 ext_phy_type,
3066 ext_phy_addr,
3067 MDIO_XS_DEVAD,
3068 reg, &val);
3069 /* Clear first 3 bits of the control */
3070 val &= ~0x7;
3071 /* Set control bits according to
3072 configuation */
3073 val |= (params->xgxs_config_rx[i] &
3074 0x7);
3075 DP(NETIF_MSG_LINK, "Setting RX"
3076 "Equalizer to BCM8706 reg 0x%x"
3077 " <-- val 0x%x\n", reg, val);
3078 bnx2x_cl45_write(bp, params->port,
3079 ext_phy_type,
3080 ext_phy_addr,
3081 MDIO_XS_DEVAD,
3082 reg, val);
3083 }
3084 }
3041 /* Force speed */ 3085 /* Force speed */
3042 /* First enable LASI */ 3086 /* First enable LASI */
3043 bnx2x_cl45_write(bp, params->port, 3087 bnx2x_cl45_write(bp, params->port,
@@ -3170,6 +3214,28 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3170 ext_phy_addr, MDIO_PMA_DEVAD, 3214 ext_phy_addr, MDIO_PMA_DEVAD,
3171 MDIO_PMA_REG_LASI_CTRL, 1); 3215 MDIO_PMA_REG_LASI_CTRL, 1);
3172 } 3216 }
3217
3218 /* Set TX PreEmphasis if needed */
3219 if ((params->feature_config_flags &
3220 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3221 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
3222 "TX_CTRL2 0x%x\n",
3223 params->xgxs_config_tx[0],
3224 params->xgxs_config_tx[1]);
3225 bnx2x_cl45_write(bp, params->port,
3226 ext_phy_type,
3227 ext_phy_addr,
3228 MDIO_PMA_DEVAD,
3229 MDIO_PMA_REG_8726_TX_CTRL1,
3230 params->xgxs_config_tx[0]);
3231
3232 bnx2x_cl45_write(bp, params->port,
3233 ext_phy_type,
3234 ext_phy_addr,
3235 MDIO_PMA_DEVAD,
3236 MDIO_PMA_REG_8726_TX_CTRL2,
3237 params->xgxs_config_tx[1]);
3238 }
3173 break; 3239 break;
3174 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072: 3240 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3175 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 3241 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
diff --git a/drivers/net/bnx2x_link.h b/drivers/net/bnx2x_link.h
index 1318683f6e51..38254d084b67 100644
--- a/drivers/net/bnx2x_link.h
+++ b/drivers/net/bnx2x_link.h
@@ -77,7 +77,6 @@ struct link_params {
77#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT 77#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
78 78
79 u16 hw_led_mode; /* part of the hw_config read from the shmem */ 79 u16 hw_led_mode; /* part of the hw_config read from the shmem */
80 u32 serdes_config;
81 u32 lane_config; 80 u32 lane_config;
82 u32 ext_phy_config; 81 u32 ext_phy_config;
83#define XGXS_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \ 82#define XGXS_EXT_PHY_TYPE(ext_phy_config) (ext_phy_config & \
@@ -89,6 +88,9 @@ struct link_params {
89 88
90 /* phy_addr populated by the CLC */ 89 /* phy_addr populated by the CLC */
91 u8 phy_addr; 90 u8 phy_addr;
91 u16 xgxs_config_rx[4]; /* preemphasis values for the rx side */
92
93 u16 xgxs_config_tx[4]; /* preemphasis values for the tx side */
92 u32 feature_config_flags; 94 u32 feature_config_flags;
93#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0) 95#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
94#define FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED (2<<0) 96#define FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED (2<<0)
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index 0d2d5564f255..60a4e94e6840 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -7550,6 +7550,15 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7550 SHARED_HW_CFG_LED_MODE_MASK) >> 7550 SHARED_HW_CFG_LED_MODE_MASK) >>
7551 SHARED_HW_CFG_LED_MODE_SHIFT); 7551 SHARED_HW_CFG_LED_MODE_SHIFT);
7552 7552
7553 bp->link_params.feature_config_flags = 0;
7554 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7555 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7556 bp->link_params.feature_config_flags |=
7557 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7558 else
7559 bp->link_params.feature_config_flags &=
7560 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7561
7553 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; 7562 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7554 bp->common.bc_ver = val; 7563 bp->common.bc_ver = val;
7555 BNX2X_DEV_INFO("bc_ver %X\n", val); 7564 BNX2X_DEV_INFO("bc_ver %X\n", val);
@@ -7972,12 +7981,11 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
7972 int port = BP_PORT(bp); 7981 int port = BP_PORT(bp);
7973 u32 val, val2; 7982 u32 val, val2;
7974 u32 config; 7983 u32 config;
7984 u16 i;
7975 7985
7976 bp->link_params.bp = bp; 7986 bp->link_params.bp = bp;
7977 bp->link_params.port = port; 7987 bp->link_params.port = port;
7978 7988
7979 bp->link_params.serdes_config =
7980 SHMEM_RD(bp, dev_info.port_hw_config[port].serdes_config);
7981 bp->link_params.lane_config = 7989 bp->link_params.lane_config =
7982 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); 7990 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
7983 bp->link_params.ext_phy_config = 7991 bp->link_params.ext_phy_config =
@@ -7990,6 +7998,19 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
7990 bp->port.link_config = 7998 bp->port.link_config =
7991 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); 7999 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
7992 8000
8001 /* Get the 4 lanes xgxs config rx and tx */
8002 for (i = 0; i < 2; i++) {
8003 val = SHMEM_RD(bp,
8004 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]);
8005 bp->link_params.xgxs_config_rx[i << 1] = ((val>>16) & 0xffff);
8006 bp->link_params.xgxs_config_rx[(i << 1) + 1] = (val & 0xffff);
8007
8008 val = SHMEM_RD(bp,
8009 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]);
8010 bp->link_params.xgxs_config_tx[i << 1] = ((val>>16) & 0xffff);
8011 bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff);
8012 }
8013
7993 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); 8014 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
7994 if (config & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED) 8015 if (config & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_ENABLED)
7995 bp->link_params.feature_config_flags |= 8016 bp->link_params.feature_config_flags |=
@@ -7998,10 +8019,8 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
7998 bp->link_params.feature_config_flags &= 8019 bp->link_params.feature_config_flags &=
7999 ~FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED; 8020 ~FEATURE_CONFIG_MODULE_ENFORCMENT_ENABLED;
8000 8021
8001 BNX2X_DEV_INFO("serdes_config 0x%08x lane_config 0x%08x\n" 8022 BNX2X_DEV_INFO("lane_config 0x%08x ext_phy_config 0x%08x"
8002 KERN_INFO " ext_phy_config 0x%08x speed_cap_mask 0x%08x" 8023 " speed_cap_mask 0x%08x link_config 0x%08x\n",
8003 " link_config 0x%08x\n",
8004 bp->link_params.serdes_config,
8005 bp->link_params.lane_config, 8024 bp->link_params.lane_config,
8006 bp->link_params.ext_phy_config, 8025 bp->link_params.ext_phy_config,
8007 bp->link_params.speed_cap_mask, bp->port.link_config); 8026 bp->link_params.speed_cap_mask, bp->port.link_config);
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index d3086e924709..08e703dc2b46 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -5603,6 +5603,42 @@
5603#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 5603#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5604#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 5604#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5605 5605
5606#define MDIO_REG_BANK_TX1 0x8070
5607#define MDIO_TX1_TX_DRIVER 0x17
5608#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5609#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5610#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5611#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5612#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5613#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5614#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5615#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5616#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5617
5618#define MDIO_REG_BANK_TX2 0x8080
5619#define MDIO_TX2_TX_DRIVER 0x17
5620#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5621#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5622#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5623#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5624#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5625#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5626#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5627#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5628#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5629
5630#define MDIO_REG_BANK_TX3 0x8090
5631#define MDIO_TX3_TX_DRIVER 0x17
5632#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5633#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5634#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5635#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5636#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5637#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5638#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5639#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5640#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5641
5606#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 5642#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
5607#define MDIO_BLOCK0_XGXS_CONTROL 0x10 5643#define MDIO_BLOCK0_XGXS_CONTROL 0x10
5608 5644
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 13:22:18 -0400