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-rw-r--r--drivers/video/aty/radeon_accel.c291
-rw-r--r--drivers/video/aty/radeon_backlight.c2
-rw-r--r--drivers/video/aty/radeon_base.c22
-rw-r--r--drivers/video/aty/radeon_pm.c6
-rw-r--r--drivers/video/aty/radeonfb.h38
-rw-r--r--include/video/radeon.h18
6 files changed, 250 insertions, 127 deletions
diff --git a/drivers/video/aty/radeon_accel.c b/drivers/video/aty/radeon_accel.c
index a469a3d6edcb..8718f7349d6b 100644
--- a/drivers/video/aty/radeon_accel.c
+++ b/drivers/video/aty/radeon_accel.c
@@ -5,61 +5,61 @@
5 * --dte 5 * --dte
6 */ 6 */
7 7
8static void radeon_fixup_offset(struct radeonfb_info *rinfo) 8#define FLUSH_CACHE_WORKAROUND 1
9
10void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries)
9{ 11{
10 u32 local_base; 12 int i;
11
12 /* *** Ugly workaround *** */
13 /*
14 * On some platforms, the video memory is mapped at 0 in radeon chip space
15 * (like PPCs) by the firmware. X will always move it up so that it's seen
16 * by the chip to be at the same address as the PCI BAR.
17 * That means that when switching back from X, there is a mismatch between
18 * the offsets programmed into the engine. This means that potentially,
19 * accel operations done before radeonfb has a chance to re-init the engine
20 * will have incorrect offsets, and potentially trash system memory !
21 *
22 * The correct fix is for fbcon to never call any accel op before the engine
23 * has properly been re-initialized (by a call to set_var), but this is a
24 * complex fix. This workaround in the meantime, called before every accel
25 * operation, makes sure the offsets are in sync.
26 */
27 13
28 radeon_fifo_wait (1); 14 for (i=0; i<2000000; i++) {
29 local_base = INREG(MC_FB_LOCATION) << 16; 15 rinfo->fifo_free = INREG(RBBM_STATUS) & 0x7f;
30 if (local_base == rinfo->fb_local_base) 16 if (rinfo->fifo_free >= entries)
31 return; 17 return;
18 udelay(10);
19 }
20 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
21 /* XXX Todo: attempt to reset the engine */
22}
32 23
33 rinfo->fb_local_base = local_base; 24static inline void radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
25{
26 if (entries <= rinfo->fifo_free)
27 rinfo->fifo_free -= entries;
28 else
29 radeon_fifo_update_and_wait(rinfo, entries);
30}
34 31
35 radeon_fifo_wait (3); 32static inline void radeonfb_set_creg(struct radeonfb_info *rinfo, u32 reg,
36 OUTREG(DEFAULT_PITCH_OFFSET, (rinfo->pitch << 0x16) | 33 u32 *cache, u32 new_val)
37 (rinfo->fb_local_base >> 10)); 34{
38 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); 35 if (new_val == *cache)
39 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); 36 return;
37 *cache = new_val;
38 radeon_fifo_wait(rinfo, 1);
39 OUTREG(reg, new_val);
40} 40}
41 41
42static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo, 42static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
43 const struct fb_fillrect *region) 43 const struct fb_fillrect *region)
44{ 44{
45 radeon_fifo_wait(4); 45 radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
46 46 rinfo->dp_gui_mc_base | GMC_BRUSH_SOLID_COLOR | ROP3_P);
47 OUTREG(DP_GUI_MASTER_CNTL, 47 radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
48 rinfo->dp_gui_master_cntl /* contains, like GMC_DST_32BPP */ 48 DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
49 | GMC_BRUSH_SOLID_COLOR 49 radeonfb_set_creg(rinfo, DP_BRUSH_FRGD_CLR, &rinfo->dp_brush_fg_cache,
50 | ROP3_P); 50 region->color);
51 if (radeon_get_dstbpp(rinfo->depth) != DST_8BPP) 51
52 OUTREG(DP_BRUSH_FRGD_CLR, rinfo->pseudo_palette[region->color]); 52 /* Ensure the dst cache is flushed and the engine idle before
53 else 53 * issuing the operation.
54 OUTREG(DP_BRUSH_FRGD_CLR, region->color); 54 *
55 OUTREG(DP_WRITE_MSK, 0xffffffff); 55 * This works around engine lockups on some cards
56 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM)); 56 */
57 57#if FLUSH_CACHE_WORKAROUND
58 radeon_fifo_wait(2); 58 radeon_fifo_wait(rinfo, 2);
59 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); 59 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
60 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); 60 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
61 61#endif
62 radeon_fifo_wait(2); 62 radeon_fifo_wait(rinfo, 2);
63 OUTREG(DST_Y_X, (region->dy << 16) | region->dx); 63 OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
64 OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height); 64 OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
65} 65}
@@ -70,15 +70,14 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
70 struct fb_fillrect modded; 70 struct fb_fillrect modded;
71 int vxres, vyres; 71 int vxres, vyres;
72 72
73 if (info->state != FBINFO_STATE_RUNNING) 73 WARN_ON(rinfo->gfx_mode);
74 if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
74 return; 75 return;
75 if (info->flags & FBINFO_HWACCEL_DISABLED) { 76 if (info->flags & FBINFO_HWACCEL_DISABLED) {
76 cfb_fillrect(info, region); 77 cfb_fillrect(info, region);
77 return; 78 return;
78 } 79 }
79 80
80 radeon_fixup_offset(rinfo);
81
82 vxres = info->var.xres_virtual; 81 vxres = info->var.xres_virtual;
83 vyres = info->var.yres_virtual; 82 vyres = info->var.yres_virtual;
84 83
@@ -91,6 +90,10 @@ void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region)
91 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx; 90 if(modded.dx + modded.width > vxres) modded.width = vxres - modded.dx;
92 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy; 91 if(modded.dy + modded.height > vyres) modded.height = vyres - modded.dy;
93 92
93 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
94 info->fix.visual == FB_VISUAL_DIRECTCOLOR )
95 modded.color = ((u32 *) (info->pseudo_palette))[region->color];
96
94 radeonfb_prim_fillrect(rinfo, &modded); 97 radeonfb_prim_fillrect(rinfo, &modded);
95} 98}
96 99
@@ -109,22 +112,22 @@ static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
109 if ( xdir < 0 ) { sx += w-1; dx += w-1; } 112 if ( xdir < 0 ) { sx += w-1; dx += w-1; }
110 if ( ydir < 0 ) { sy += h-1; dy += h-1; } 113 if ( ydir < 0 ) { sy += h-1; dy += h-1; }
111 114
112 radeon_fifo_wait(3); 115 radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
113 OUTREG(DP_GUI_MASTER_CNTL, 116 rinfo->dp_gui_mc_base |
114 rinfo->dp_gui_master_cntl /* i.e. GMC_DST_32BPP */ 117 GMC_BRUSH_NONE |
115 | GMC_BRUSH_NONE 118 GMC_SRC_DATATYPE_COLOR |
116 | GMC_SRC_DSTCOLOR 119 ROP3_S |
117 | ROP3_S 120 DP_SRC_SOURCE_MEMORY);
118 | DP_SRC_SOURCE_MEMORY ); 121 radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
119 OUTREG(DP_WRITE_MSK, 0xffffffff); 122 (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) |
120 OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) 123 (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
121 | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0)); 124
122 125#if FLUSH_CACHE_WORKAROUND
123 radeon_fifo_wait(2); 126 radeon_fifo_wait(rinfo, 2);
124 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL); 127 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
125 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE)); 128 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
126 129#endif
127 radeon_fifo_wait(3); 130 radeon_fifo_wait(rinfo, 3);
128 OUTREG(SRC_Y_X, (sy << 16) | sx); 131 OUTREG(SRC_Y_X, (sy << 16) | sx);
129 OUTREG(DST_Y_X, (dy << 16) | dx); 132 OUTREG(DST_Y_X, (dy << 16) | dx);
130 OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w); 133 OUTREG(DST_HEIGHT_WIDTH, (h << 16) | w);
@@ -143,15 +146,14 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
143 modded.width = area->width; 146 modded.width = area->width;
144 modded.height = area->height; 147 modded.height = area->height;
145 148
146 if (info->state != FBINFO_STATE_RUNNING) 149 WARN_ON(rinfo->gfx_mode);
150 if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
147 return; 151 return;
148 if (info->flags & FBINFO_HWACCEL_DISABLED) { 152 if (info->flags & FBINFO_HWACCEL_DISABLED) {
149 cfb_copyarea(info, area); 153 cfb_copyarea(info, area);
150 return; 154 return;
151 } 155 }
152 156
153 radeon_fixup_offset(rinfo);
154
155 vxres = info->var.xres_virtual; 157 vxres = info->var.xres_virtual;
156 vyres = info->var.yres_virtual; 158 vyres = info->var.yres_virtual;
157 159
@@ -168,13 +170,112 @@ void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
168 radeonfb_prim_copyarea(rinfo, &modded); 170 radeonfb_prim_copyarea(rinfo, &modded);
169} 171}
170 172
173static void radeonfb_prim_imageblit(struct radeonfb_info *rinfo,
174 const struct fb_image *image,
175 u32 fg, u32 bg)
176{
177 unsigned int src_bytes, dwords;
178 u32 *bits;
179
180 radeonfb_set_creg(rinfo, DP_GUI_MASTER_CNTL, &rinfo->dp_gui_mc_cache,
181 rinfo->dp_gui_mc_base |
182 GMC_BRUSH_NONE |
183 GMC_SRC_DATATYPE_MONO_FG_BG |
184 ROP3_S |
185 GMC_BYTE_ORDER_MSB_TO_LSB |
186 DP_SRC_SOURCE_HOST_DATA);
187 radeonfb_set_creg(rinfo, DP_CNTL, &rinfo->dp_cntl_cache,
188 DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
189 radeonfb_set_creg(rinfo, DP_SRC_FRGD_CLR, &rinfo->dp_src_fg_cache, fg);
190 radeonfb_set_creg(rinfo, DP_SRC_BKGD_CLR, &rinfo->dp_src_bg_cache, bg);
191
192 radeon_fifo_wait(rinfo, 1);
193 OUTREG(DST_Y_X, (image->dy << 16) | image->dx);
194
195 /* Ensure the dst cache is flushed and the engine idle before
196 * issuing the operation.
197 *
198 * This works around engine lockups on some cards
199 */
200#if FLUSH_CACHE_WORKAROUND
201 radeon_fifo_wait(rinfo, 2);
202 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
203 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
204#endif
205
206 /* X here pads width to a multiple of 32 and uses the clipper to
207 * adjust the result. Is that really necessary ? Things seem to
208 * work ok for me without that and the doco doesn't seem to imply
209 * there is such a restriction.
210 */
211 OUTREG(DST_WIDTH_HEIGHT, (image->width << 16) | image->height);
212
213 src_bytes = (((image->width * image->depth) + 7) / 8) * image->height;
214 dwords = (src_bytes + 3) / 4;
215 bits = (u32*)(image->data);
216
217 while(dwords >= 8) {
218 radeon_fifo_wait(rinfo, 8);
219#if BITS_PER_LONG == 64
220 __raw_writeq(*((u64 *)(bits)), rinfo->mmio_base + HOST_DATA0);
221 __raw_writeq(*((u64 *)(bits+2)), rinfo->mmio_base + HOST_DATA2);
222 __raw_writeq(*((u64 *)(bits+4)), rinfo->mmio_base + HOST_DATA4);
223 __raw_writeq(*((u64 *)(bits+6)), rinfo->mmio_base + HOST_DATA6);
224 bits += 8;
225#else
226 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0);
227 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA1);
228 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA2);
229 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA3);
230 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA4);
231 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA5);
232 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA6);
233 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA7);
234#endif
235 dwords -= 8;
236 }
237 while(dwords--) {
238 radeon_fifo_wait(rinfo, 1);
239 __raw_writel(*(bits++), rinfo->mmio_base + HOST_DATA0);
240 }
241}
242
171void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image) 243void radeonfb_imageblit(struct fb_info *info, const struct fb_image *image)
172{ 244{
173 struct radeonfb_info *rinfo = info->par; 245 struct radeonfb_info *rinfo = info->par;
246 u32 fg, bg;
174 247
175 if (info->state != FBINFO_STATE_RUNNING) 248 WARN_ON(rinfo->gfx_mode);
249 if (info->state != FBINFO_STATE_RUNNING || rinfo->gfx_mode)
250 return;
251
252 if (!image->width || !image->height)
176 return; 253 return;
177 radeon_engine_idle(); 254
255 /* We only do 1 bpp color expansion for now */
256 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1)
257 goto fallback;
258
259 /* Fallback if running out of the screen. We may do clipping
260 * in the future */
261 if ((image->dx + image->width) > info->var.xres_virtual ||
262 (image->dy + image->height) > info->var.yres_virtual)
263 goto fallback;
264
265 if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
266 info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
267 fg = ((u32*)(info->pseudo_palette))[image->fg_color];
268 bg = ((u32*)(info->pseudo_palette))[image->bg_color];
269 } else {
270 fg = image->fg_color;
271 bg = image->bg_color;
272 }
273
274 radeonfb_prim_imageblit(rinfo, image, fg, bg);
275 return;
276
277 fallback:
278 radeon_engine_idle(rinfo);
178 279
179 cfb_imageblit(info, image); 280 cfb_imageblit(info, image);
180} 281}
@@ -185,7 +286,8 @@ int radeonfb_sync(struct fb_info *info)
185 286
186 if (info->state != FBINFO_STATE_RUNNING) 287 if (info->state != FBINFO_STATE_RUNNING)
187 return 0; 288 return 0;
188 radeon_engine_idle(); 289
290 radeon_engine_idle(rinfo);
189 291
190 return 0; 292 return 0;
191} 293}
@@ -261,9 +363,10 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
261 /* disable 3D engine */ 363 /* disable 3D engine */
262 OUTREG(RB3D_CNTL, 0); 364 OUTREG(RB3D_CNTL, 0);
263 365
366 rinfo->fifo_free = 0;
264 radeonfb_engine_reset(rinfo); 367 radeonfb_engine_reset(rinfo);
265 368
266 radeon_fifo_wait (1); 369 radeon_fifo_wait(rinfo, 1);
267 if (IS_R300_VARIANT(rinfo)) { 370 if (IS_R300_VARIANT(rinfo)) {
268 OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) | 371 OUTREG(RB2D_DSTCACHE_MODE, INREG(RB2D_DSTCACHE_MODE) |
269 RB2D_DC_AUTOFLUSH_ENABLE | 372 RB2D_DC_AUTOFLUSH_ENABLE |
@@ -277,7 +380,7 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
277 OUTREG(RB2D_DSTCACHE_MODE, 0); 380 OUTREG(RB2D_DSTCACHE_MODE, 0);
278 } 381 }
279 382
280 radeon_fifo_wait (3); 383 radeon_fifo_wait(rinfo, 3);
281 /* We re-read MC_FB_LOCATION from card as it can have been 384 /* We re-read MC_FB_LOCATION from card as it can have been
282 * modified by XFree drivers (ouch !) 385 * modified by XFree drivers (ouch !)
283 */ 386 */
@@ -288,41 +391,57 @@ void radeonfb_engine_init (struct radeonfb_info *rinfo)
288 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); 391 OUTREG(DST_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
289 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10)); 392 OUTREG(SRC_PITCH_OFFSET, (rinfo->pitch << 0x16) | (rinfo->fb_local_base >> 10));
290 393
291 radeon_fifo_wait (1); 394 radeon_fifo_wait(rinfo, 1);
292#if defined(__BIG_ENDIAN) 395#ifdef __BIG_ENDIAN
293 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); 396 OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
294#else 397#else
295 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); 398 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
296#endif 399#endif
297 radeon_fifo_wait (2); 400 radeon_fifo_wait(rinfo, 2);
298 OUTREG(DEFAULT_SC_TOP_LEFT, 0); 401 OUTREG(DEFAULT_SC_TOP_LEFT, 0);
299 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | 402 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
300 DEFAULT_SC_BOTTOM_MAX)); 403 DEFAULT_SC_BOTTOM_MAX));
301 404
405 /* set default DP_GUI_MASTER_CNTL */
302 temp = radeon_get_dstbpp(rinfo->depth); 406 temp = radeon_get_dstbpp(rinfo->depth);
303 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS); 407 rinfo->dp_gui_mc_base = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
304 408
305 radeon_fifo_wait (1); 409 rinfo->dp_gui_mc_cache = rinfo->dp_gui_mc_base |
306 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl | 410 GMC_BRUSH_SOLID_COLOR |
307 GMC_BRUSH_SOLID_COLOR | 411 GMC_SRC_DATATYPE_COLOR;
308 GMC_SRC_DATATYPE_COLOR)); 412 radeon_fifo_wait(rinfo, 1);
413 OUTREG(DP_GUI_MASTER_CNTL, rinfo->dp_gui_mc_cache);
309 414
310 radeon_fifo_wait (7);
311 415
312 /* clear line drawing regs */ 416 /* clear line drawing regs */
417 radeon_fifo_wait(rinfo, 2);
313 OUTREG(DST_LINE_START, 0); 418 OUTREG(DST_LINE_START, 0);
314 OUTREG(DST_LINE_END, 0); 419 OUTREG(DST_LINE_END, 0);
315 420
316 /* set brush color regs */ 421 /* set brush and source color regs */
317 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); 422 rinfo->dp_brush_fg_cache = 0xffffffff;
318 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); 423 rinfo->dp_brush_bg_cache = 0x00000000;
319 424 rinfo->dp_src_fg_cache = 0xffffffff;
320 /* set source color regs */ 425 rinfo->dp_src_bg_cache = 0x00000000;
321 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); 426 radeon_fifo_wait(rinfo, 4);
322 OUTREG(DP_SRC_BKGD_CLR, 0x00000000); 427 OUTREG(DP_BRUSH_FRGD_CLR, rinfo->dp_brush_fg_cache);
428 OUTREG(DP_BRUSH_BKGD_CLR, rinfo->dp_brush_bg_cache);
429 OUTREG(DP_SRC_FRGD_CLR, rinfo->dp_src_fg_cache);
430 OUTREG(DP_SRC_BKGD_CLR, rinfo->dp_src_bg_cache);
431
432 /* Default direction */
433 rinfo->dp_cntl_cache = DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM;
434 radeon_fifo_wait(rinfo, 1);
435 OUTREG(DP_CNTL, rinfo->dp_cntl_cache);
323 436
324 /* default write mask */ 437 /* default write mask */
438 radeon_fifo_wait(rinfo, 1);
325 OUTREG(DP_WRITE_MSK, 0xffffffff); 439 OUTREG(DP_WRITE_MSK, 0xffffffff);
326 440
327 radeon_engine_idle (); 441 /* Default to no swapping of host data */
442 radeon_fifo_wait(rinfo, 1);
443 OUTREG(RBBM_GUICNTL, RBBM_GUICNTL_HOST_DATA_SWAP_NONE);
444
445 /* Make sure it's settled */
446 radeon_engine_idle(rinfo);
328} 447}
diff --git a/drivers/video/aty/radeon_backlight.c b/drivers/video/aty/radeon_backlight.c
index 1a056adb61c8..f343ba83f0ae 100644
--- a/drivers/video/aty/radeon_backlight.c
+++ b/drivers/video/aty/radeon_backlight.c
@@ -66,7 +66,7 @@ static int radeon_bl_update_status(struct backlight_device *bd)
66 level = bd->props.brightness; 66 level = bd->props.brightness;
67 67
68 del_timer_sync(&rinfo->lvds_timer); 68 del_timer_sync(&rinfo->lvds_timer);
69 radeon_engine_idle(); 69 radeon_engine_idle(rinfo);
70 70
71 lvds_gen_cntl = INREG(LVDS_GEN_CNTL); 71 lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
72 if (level > 0) { 72 if (level > 0) {
diff --git a/drivers/video/aty/radeon_base.c b/drivers/video/aty/radeon_base.c
index d0f1a7fc2c9d..9a5821c65ebf 100644
--- a/drivers/video/aty/radeon_base.c
+++ b/drivers/video/aty/radeon_base.c
@@ -852,7 +852,6 @@ static int radeonfb_pan_display (struct fb_var_screeninfo *var,
852 if (rinfo->asleep) 852 if (rinfo->asleep)
853 return 0; 853 return 0;
854 854
855 radeon_fifo_wait(2);
856 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset) 855 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
857 * var->bits_per_pixel / 8) & ~7); 856 * var->bits_per_pixel / 8) & ~7);
858 return 0; 857 return 0;
@@ -882,7 +881,6 @@ static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
882 if (rc) 881 if (rc)
883 return rc; 882 return rc;
884 883
885 radeon_fifo_wait(2);
886 if (value & 0x01) { 884 if (value & 0x01) {
887 tmp = INREG(LVDS_GEN_CNTL); 885 tmp = INREG(LVDS_GEN_CNTL);
888 886
@@ -940,7 +938,7 @@ int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
940 if (rinfo->lock_blank) 938 if (rinfo->lock_blank)
941 return 0; 939 return 0;
942 940
943 radeon_engine_idle(); 941 radeon_engine_idle(rinfo);
944 942
945 val = INREG(CRTC_EXT_CNTL); 943 val = INREG(CRTC_EXT_CNTL);
946 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | 944 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
@@ -1048,7 +1046,7 @@ static int radeonfb_blank (int blank, struct fb_info *info)
1048 1046
1049 if (rinfo->asleep) 1047 if (rinfo->asleep)
1050 return 0; 1048 return 0;
1051 1049
1052 return radeon_screen_blank(rinfo, blank, 0); 1050 return radeon_screen_blank(rinfo, blank, 0);
1053} 1051}
1054 1052
@@ -1074,8 +1072,6 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1074 pindex = regno; 1072 pindex = regno;
1075 1073
1076 if (!rinfo->asleep) { 1074 if (!rinfo->asleep) {
1077 radeon_fifo_wait(9);
1078
1079 if (rinfo->bpp == 16) { 1075 if (rinfo->bpp == 16) {
1080 pindex = regno * 8; 1076 pindex = regno * 8;
1081 1077
@@ -1244,8 +1240,6 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg
1244{ 1240{
1245 int i; 1241 int i;
1246 1242
1247 radeon_fifo_wait(20);
1248
1249 /* Workaround from XFree */ 1243 /* Workaround from XFree */
1250 if (rinfo->is_mobility) { 1244 if (rinfo->is_mobility) {
1251 /* A temporal workaround for the occational blanking on certain laptop 1245 /* A temporal workaround for the occational blanking on certain laptop
@@ -1341,7 +1335,7 @@ static void radeon_lvds_timer_func(unsigned long data)
1341{ 1335{
1342 struct radeonfb_info *rinfo = (struct radeonfb_info *)data; 1336 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1343 1337
1344 radeon_engine_idle(); 1338 radeon_engine_idle(rinfo);
1345 1339
1346 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); 1340 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1347} 1341}
@@ -1359,10 +1353,11 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1359 if (nomodeset) 1353 if (nomodeset)
1360 return; 1354 return;
1361 1355
1356 radeon_engine_idle(rinfo);
1357
1362 if (!regs_only) 1358 if (!regs_only)
1363 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); 1359 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1364 1360
1365 radeon_fifo_wait(31);
1366 for (i=0; i<10; i++) 1361 for (i=0; i<10; i++)
1367 OUTREG(common_regs[i].reg, common_regs[i].val); 1362 OUTREG(common_regs[i].reg, common_regs[i].val);
1368 1363
@@ -1390,7 +1385,6 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1390 radeon_write_pll_regs(rinfo, mode); 1385 radeon_write_pll_regs(rinfo, mode);
1391 1386
1392 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { 1387 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1393 radeon_fifo_wait(10);
1394 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); 1388 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1395 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); 1389 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1396 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); 1390 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
@@ -1405,7 +1399,6 @@ void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1405 if (!regs_only) 1399 if (!regs_only)
1406 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); 1400 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1407 1401
1408 radeon_fifo_wait(2);
1409 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); 1402 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1410 1403
1411 return; 1404 return;
@@ -1556,7 +1549,7 @@ static int radeonfb_set_par(struct fb_info *info)
1556 /* We always want engine to be idle on a mode switch, even 1549 /* We always want engine to be idle on a mode switch, even
1557 * if we won't actually change the mode 1550 * if we won't actually change the mode
1558 */ 1551 */
1559 radeon_engine_idle(); 1552 radeon_engine_idle(rinfo);
1560 1553
1561 hSyncStart = mode->xres + mode->right_margin; 1554 hSyncStart = mode->xres + mode->right_margin;
1562 hSyncEnd = hSyncStart + mode->hsync_len; 1555 hSyncEnd = hSyncStart + mode->hsync_len;
@@ -1851,7 +1844,6 @@ static int radeonfb_set_par(struct fb_info *info)
1851 return 0; 1844 return 0;
1852} 1845}
1853 1846
1854
1855static struct fb_ops radeonfb_ops = { 1847static struct fb_ops radeonfb_ops = {
1856 .owner = THIS_MODULE, 1848 .owner = THIS_MODULE,
1857 .fb_check_var = radeonfb_check_var, 1849 .fb_check_var = radeonfb_check_var,
@@ -1875,6 +1867,7 @@ static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1875 info->par = rinfo; 1867 info->par = rinfo;
1876 info->pseudo_palette = rinfo->pseudo_palette; 1868 info->pseudo_palette = rinfo->pseudo_palette;
1877 info->flags = FBINFO_DEFAULT 1869 info->flags = FBINFO_DEFAULT
1870 | FBINFO_HWACCEL_IMAGEBLIT
1878 | FBINFO_HWACCEL_COPYAREA 1871 | FBINFO_HWACCEL_COPYAREA
1879 | FBINFO_HWACCEL_FILLRECT 1872 | FBINFO_HWACCEL_FILLRECT
1880 | FBINFO_HWACCEL_XPAN 1873 | FBINFO_HWACCEL_XPAN
@@ -2006,7 +1999,6 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo)
2006 u32 tom = INREG(NB_TOM); 1999 u32 tom = INREG(NB_TOM);
2007 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); 2000 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2008 2001
2009 radeon_fifo_wait(6);
2010 OUTREG(MC_FB_LOCATION, tom); 2002 OUTREG(MC_FB_LOCATION, tom);
2011 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2003 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2012 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 2004 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
diff --git a/drivers/video/aty/radeon_pm.c b/drivers/video/aty/radeon_pm.c
index 675abdafc2d8..3df5015f1d13 100644
--- a/drivers/video/aty/radeon_pm.c
+++ b/drivers/video/aty/radeon_pm.c
@@ -2653,9 +2653,9 @@ int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
2653 2653
2654 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { 2654 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
2655 /* Make sure engine is reset */ 2655 /* Make sure engine is reset */
2656 radeon_engine_idle(); 2656 radeon_engine_idle(rinfo);
2657 radeonfb_engine_reset(rinfo); 2657 radeonfb_engine_reset(rinfo);
2658 radeon_engine_idle(); 2658 radeon_engine_idle(rinfo);
2659 } 2659 }
2660 2660
2661 /* Blank display and LCD */ 2661 /* Blank display and LCD */
@@ -2767,7 +2767,7 @@ int radeonfb_pci_resume(struct pci_dev *pdev)
2767 2767
2768 rinfo->asleep = 0; 2768 rinfo->asleep = 0;
2769 } else 2769 } else
2770 radeon_engine_idle(); 2770 radeon_engine_idle(rinfo);
2771 2771
2772 /* Restore display & engine */ 2772 /* Restore display & engine */
2773 radeon_write_mode (rinfo, &rinfo->state, 1); 2773 radeon_write_mode (rinfo, &rinfo->state, 1);
diff --git a/drivers/video/aty/radeonfb.h b/drivers/video/aty/radeonfb.h
index 3ea1b00fdd22..ea0b5b47acaf 100644
--- a/drivers/video/aty/radeonfb.h
+++ b/drivers/video/aty/radeonfb.h
@@ -336,7 +336,15 @@ struct radeonfb_info {
336 int mon2_type; 336 int mon2_type;
337 u8 *mon2_EDID; 337 u8 *mon2_EDID;
338 338
339 u32 dp_gui_master_cntl; 339 /* accel bits */
340 u32 dp_gui_mc_base;
341 u32 dp_gui_mc_cache;
342 u32 dp_cntl_cache;
343 u32 dp_brush_fg_cache;
344 u32 dp_brush_bg_cache;
345 u32 dp_src_fg_cache;
346 u32 dp_src_bg_cache;
347 u32 fifo_free;
340 348
341 struct pll_info pll; 349 struct pll_info pll;
342 350
@@ -348,6 +356,7 @@ struct radeonfb_info {
348 int lock_blank; 356 int lock_blank;
349 int dynclk; 357 int dynclk;
350 int no_schedule; 358 int no_schedule;
359 int gfx_mode;
351 enum radeon_pm_mode pm_mode; 360 enum radeon_pm_mode pm_mode;
352 reinit_function_ptr reinit_func; 361 reinit_function_ptr reinit_func;
353 362
@@ -392,8 +401,14 @@ static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
392#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) 401#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
393#define INREG16(addr) readw((rinfo->mmio_base)+addr) 402#define INREG16(addr) readw((rinfo->mmio_base)+addr)
394#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) 403#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
404
405#ifdef CONFIG_PPC
406#define INREG(addr) ({ eieio(); ld_le32(rinfo->mmio_base+(addr)); })
407#define OUTREG(addr,val) do { eieio(); st_le32(rinfo->mmio_base+(addr),(val)); } while(0)
408#else
395#define INREG(addr) readl((rinfo->mmio_base)+addr) 409#define INREG(addr) readl((rinfo->mmio_base)+addr)
396#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) 410#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
411#endif
397 412
398static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, 413static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
399 u32 val, u32 mask) 414 u32 val, u32 mask)
@@ -535,17 +550,7 @@ static inline u32 radeon_get_dstbpp(u16 depth)
535 * 2D Engine helper routines 550 * 2D Engine helper routines
536 */ 551 */
537 552
538static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) 553extern void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries);
539{
540 int i;
541
542 for (i=0; i<2000000; i++) {
543 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
544 return;
545 udelay(1);
546 }
547 printk(KERN_ERR "radeonfb: FIFO Timeout !\n");
548}
549 554
550static inline void radeon_engine_flush (struct radeonfb_info *rinfo) 555static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
551{ 556{
@@ -558,7 +563,7 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
558 /* Ensure FIFO is empty, ie, make sure the flush commands 563 /* Ensure FIFO is empty, ie, make sure the flush commands
559 * has reached the cache 564 * has reached the cache
560 */ 565 */
561 _radeon_fifo_wait (rinfo, 64); 566 radeon_fifo_update_and_wait(rinfo, 64);
562 567
563 /* Wait for the flush to complete */ 568 /* Wait for the flush to complete */
564 for (i=0; i < 2000000; i++) { 569 for (i=0; i < 2000000; i++) {
@@ -570,12 +575,12 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
570} 575}
571 576
572 577
573static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) 578static inline void radeon_engine_idle(struct radeonfb_info *rinfo)
574{ 579{
575 int i; 580 int i;
576 581
577 /* ensure FIFO is empty before waiting for idle */ 582 /* ensure FIFO is empty before waiting for idle */
578 _radeon_fifo_wait (rinfo, 64); 583 radeon_fifo_update_and_wait (rinfo, 64);
579 584
580 for (i=0; i<2000000; i++) { 585 for (i=0; i<2000000; i++) {
581 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { 586 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
@@ -588,8 +593,6 @@ static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
588} 593}
589 594
590 595
591#define radeon_engine_idle() _radeon_engine_idle(rinfo)
592#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
593#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) 596#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
594 597
595 598
@@ -619,6 +622,7 @@ extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
619extern int radeonfb_sync(struct fb_info *info); 622extern int radeonfb_sync(struct fb_info *info);
620extern void radeonfb_engine_init (struct radeonfb_info *rinfo); 623extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
621extern void radeonfb_engine_reset(struct radeonfb_info *rinfo); 624extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
625extern void radeon_fixup_mem_offset(struct radeonfb_info *rinfo);
622 626
623/* Other functions */ 627/* Other functions */
624extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch); 628extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
diff --git a/include/video/radeon.h b/include/video/radeon.h
index 1cd09cc5b169..d5dcaf154ba4 100644
--- a/include/video/radeon.h
+++ b/include/video/radeon.h
@@ -525,6 +525,9 @@
525#define CRTC_DISPLAY_DIS (1 << 10) 525#define CRTC_DISPLAY_DIS (1 << 10)
526#define CRTC_CRT_ON (1 << 15) 526#define CRTC_CRT_ON (1 << 15)
527 527
528/* DSTCACHE_MODE bits constants */
529#define RB2D_DC_AUTOFLUSH_ENABLE (1 << 8)
530#define RB2D_DC_DC_DISABLE_IGNORE_PE (1 << 17)
528 531
529/* DSTCACHE_CTLSTAT bit constants */ 532/* DSTCACHE_CTLSTAT bit constants */
530#define RB2D_DC_FLUSH_2D (1 << 0) 533#define RB2D_DC_FLUSH_2D (1 << 0)
@@ -866,15 +869,10 @@
866#define GMC_DST_16BPP_YVYU422 0x00000c00 869#define GMC_DST_16BPP_YVYU422 0x00000c00
867#define GMC_DST_32BPP_AYUV444 0x00000e00 870#define GMC_DST_32BPP_AYUV444 0x00000e00
868#define GMC_DST_16BPP_ARGB4444 0x00000f00 871#define GMC_DST_16BPP_ARGB4444 0x00000f00
869#define GMC_SRC_MONO 0x00000000
870#define GMC_SRC_MONO_LBKGD 0x00001000
871#define GMC_SRC_DSTCOLOR 0x00003000
872#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 872#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
873#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 873#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
874#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 874#define GMC_DP_CONVERSION_TEMP_9300 0x00008000
875#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 875#define GMC_DP_CONVERSION_TEMP_6500 0x00000000
876#define GMC_DP_SRC_RECT 0x02000000
877#define GMC_DP_SRC_HOST 0x03000000
878#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 876#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
879#define GMC_3D_FCN_EN_CLR 0x00000000 877#define GMC_3D_FCN_EN_CLR 0x00000000
880#define GMC_3D_FCN_EN_SET 0x08000000 878#define GMC_3D_FCN_EN_SET 0x08000000
@@ -885,6 +883,9 @@
885#define GMC_WRITE_MASK_LEAVE 0x00000000 883#define GMC_WRITE_MASK_LEAVE 0x00000000
886#define GMC_WRITE_MASK_SET 0x40000000 884#define GMC_WRITE_MASK_SET 0x40000000
887#define GMC_CLR_CMP_CNTL_DIS (1 << 28) 885#define GMC_CLR_CMP_CNTL_DIS (1 << 28)
886#define GMC_SRC_DATATYPE_MASK (3 << 12)
887#define GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
888#define GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
888#define GMC_SRC_DATATYPE_COLOR (3 << 12) 889#define GMC_SRC_DATATYPE_COLOR (3 << 12)
889#define ROP3_S 0x00cc0000 890#define ROP3_S 0x00cc0000
890#define ROP3_SRCCOPY 0x00cc0000 891#define ROP3_SRCCOPY 0x00cc0000
@@ -893,6 +894,7 @@
893#define DP_SRC_SOURCE_MASK (7 << 24) 894#define DP_SRC_SOURCE_MASK (7 << 24)
894#define GMC_BRUSH_NONE (15 << 4) 895#define GMC_BRUSH_NONE (15 << 4)
895#define DP_SRC_SOURCE_MEMORY (2 << 24) 896#define DP_SRC_SOURCE_MEMORY (2 << 24)
897#define DP_SRC_SOURCE_HOST_DATA (3 << 24)
896#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 898#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
897 899
898/* DP_MIX bit constants */ 900/* DP_MIX bit constants */
@@ -978,6 +980,12 @@
978#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) 980#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)
979#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) 981#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)
980 982
983/* RBBM_GUICNTL constants */
984#define RBBM_GUICNTL_HOST_DATA_SWAP_NONE (0 << 0)
985#define RBBM_GUICNTL_HOST_DATA_SWAP_16BIT (1 << 0)
986#define RBBM_GUICNTL_HOST_DATA_SWAP_32BIT (2 << 0)
987#define RBBM_GUICNTL_HOST_DATA_SWAP_HDW (3 << 0)
988
981/* masks */ 989/* masks */
982 990
983#define CONFIG_MEMSIZE_MASK 0x1f000000 991#define CONFIG_MEMSIZE_MASK 0x1f000000
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 19:20:51 -0500