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-rw-r--r--arch/ia64/pci/pci.c9
-rw-r--r--arch/x86/pci/common.c8
-rw-r--r--drivers/pci/pci.c21
-rw-r--r--drivers/pci/quirks.c28
-rw-r--r--include/linux/pci.h2
5 files changed, 49 insertions, 19 deletions
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index c0fca2c1c858..d60e7195b7dd 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -720,9 +720,6 @@ int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
720 return ret; 720 return ret;
721} 721}
722 722
723/* It's defined in drivers/pci/pci.c */
724extern u8 pci_cache_line_size;
725
726/** 723/**
727 * set_pci_cacheline_size - determine cacheline size for PCI devices 724 * set_pci_cacheline_size - determine cacheline size for PCI devices
728 * 725 *
@@ -731,7 +728,7 @@ extern u8 pci_cache_line_size;
731 * 728 *
732 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info(). 729 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
733 */ 730 */
734static void __init set_pci_cacheline_size(void) 731static void __init set_pci_dfl_cacheline_size(void)
735{ 732{
736 unsigned long levels, unique_caches; 733 unsigned long levels, unique_caches;
737 long status; 734 long status;
@@ -751,7 +748,7 @@ static void __init set_pci_cacheline_size(void)
751 "(status=%ld)\n", __func__, status); 748 "(status=%ld)\n", __func__, status);
752 return; 749 return;
753 } 750 }
754 pci_cache_line_size = (1 << cci.pcci_line_size) / 4; 751 pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4;
755} 752}
756 753
757u64 ia64_dma_get_required_mask(struct device *dev) 754u64 ia64_dma_get_required_mask(struct device *dev)
@@ -782,7 +779,7 @@ EXPORT_SYMBOL_GPL(dma_get_required_mask);
782 779
783static int __init pcibios_init(void) 780static int __init pcibios_init(void)
784{ 781{
785 set_pci_cacheline_size(); 782 set_pci_dfl_cacheline_size();
786 return 0; 783 return 0;
787} 784}
788 785
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index 1331fcf26143..fbeec31316cf 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -410,8 +410,6 @@ struct pci_bus * __devinit pcibios_scan_root(int busnum)
410 return bus; 410 return bus;
411} 411}
412 412
413extern u8 pci_cache_line_size;
414
415int __init pcibios_init(void) 413int __init pcibios_init(void)
416{ 414{
417 struct cpuinfo_x86 *c = &boot_cpu_data; 415 struct cpuinfo_x86 *c = &boot_cpu_data;
@@ -426,11 +424,11 @@ int __init pcibios_init(void)
426 * and P4. It's also good for 386/486s (which actually have 16) 424 * and P4. It's also good for 386/486s (which actually have 16)
427 * as quite a few PCI devices do not support smaller values. 425 * as quite a few PCI devices do not support smaller values.
428 */ 426 */
429 pci_cache_line_size = 32 >> 2; 427 pci_dfl_cache_line_size = 32 >> 2;
430 if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD) 428 if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
431 pci_cache_line_size = 64 >> 2; /* K7 & K8 */ 429 pci_dfl_cache_line_size = 64 >> 2; /* K7 & K8 */
432 else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL) 430 else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
433 pci_cache_line_size = 128 >> 2; /* P4 */ 431 pci_dfl_cache_line_size = 128 >> 2; /* P4 */
434 432
435 pcibios_resource_survey(); 433 pcibios_resource_survey();
436 434
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 4e4c295a049f..1f9a7a03847b 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -47,6 +47,19 @@ unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
47unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; 47unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
48unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; 48unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
49 49
50#ifndef PCI_CACHE_LINE_BYTES
51#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
52#endif
53
54/*
55 * The default CLS is used if arch didn't set CLS explicitly and not
56 * all pci devices agree on the same value. Arch can override either
57 * the dfl or actual value as it sees fit. Don't forget this is
58 * measured in 32-bit words, not bytes.
59 */
60u8 pci_dfl_cache_line_size __initdata = PCI_CACHE_LINE_BYTES >> 2;
61u8 pci_cache_line_size;
62
50/** 63/**
51 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 64 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
52 * @bus: pointer to PCI bus structure to search 65 * @bus: pointer to PCI bus structure to search
@@ -1883,14 +1896,6 @@ void pci_clear_mwi(struct pci_dev *dev)
1883 1896
1884#else 1897#else
1885 1898
1886#ifndef PCI_CACHE_LINE_BYTES
1887#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1888#endif
1889
1890/* This can be overridden by arch code. */
1891/* Don't forget this is measured in 32-bit words, not bytes */
1892u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
1893
1894/** 1899/**
1895 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed 1900 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1896 * @dev: the PCI device for which MWI is to be enabled 1901 * @dev: the PCI device for which MWI is to be enabled
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 245d2cdb4765..1812ae7698de 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2595,9 +2595,37 @@ void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2595static int __init pci_apply_final_quirks(void) 2595static int __init pci_apply_final_quirks(void)
2596{ 2596{
2597 struct pci_dev *dev = NULL; 2597 struct pci_dev *dev = NULL;
2598 u8 cls = 0;
2599 u8 tmp;
2600
2601 if (pci_cache_line_size)
2602 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
2603 pci_cache_line_size << 2);
2598 2604
2599 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 2605 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2600 pci_fixup_device(pci_fixup_final, dev); 2606 pci_fixup_device(pci_fixup_final, dev);
2607 /*
2608 * If arch hasn't set it explicitly yet, use the CLS
2609 * value shared by all PCI devices. If there's a
2610 * mismatch, fall back to the default value.
2611 */
2612 if (!pci_cache_line_size) {
2613 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
2614 if (!cls)
2615 cls = tmp;
2616 if (!tmp || cls == tmp)
2617 continue;
2618
2619 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
2620 "using %u bytes\n", cls << 2, tmp << 2,
2621 pci_dfl_cache_line_size << 2);
2622 pci_cache_line_size = pci_dfl_cache_line_size;
2623 }
2624 }
2625 if (!pci_cache_line_size) {
2626 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
2627 cls << 2, pci_dfl_cache_line_size << 2);
2628 pci_cache_line_size = cls;
2601 } 2629 }
2602 2630
2603 return 0; 2631 return 0;
diff --git a/include/linux/pci.h b/include/linux/pci.h
index f5c7cd343e56..b849861d78e6 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1246,6 +1246,8 @@ extern int pci_pci_problems;
1246 1246
1247extern unsigned long pci_cardbus_io_size; 1247extern unsigned long pci_cardbus_io_size;
1248extern unsigned long pci_cardbus_mem_size; 1248extern unsigned long pci_cardbus_mem_size;
1249extern u8 pci_dfl_cache_line_size;
1250extern u8 pci_cache_line_size;
1249 1251
1250extern unsigned long pci_hotplug_io_size; 1252extern unsigned long pci_hotplug_io_size;
1251extern unsigned long pci_hotplug_mem_size; 1253extern unsigned long pci_hotplug_mem_size;