diff options
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_channel.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_display.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 32 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_object.c | 38 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_state.c | 45 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv20_graph.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_graph.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvc0_graph.c | 41 |
9 files changed, 33 insertions, 135 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c index f82a27609519..a7583a8ddb01 100644 --- a/drivers/gpu/drm/nouveau/nouveau_channel.c +++ b/drivers/gpu/drm/nouveau/nouveau_channel.c | |||
@@ -406,7 +406,7 @@ nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, | |||
406 | struct nouveau_channel *chan; | 406 | struct nouveau_channel *chan; |
407 | int ret; | 407 | int ret; |
408 | 408 | ||
409 | if (dev_priv->engine.graph.accel_blocked) | 409 | if (!dev_priv->eng[NVOBJ_ENGINE_GR]) |
410 | return -ENODEV; | 410 | return -ENODEV; |
411 | 411 | ||
412 | if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0) | 412 | if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0) |
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 764c15d537ba..eb514ea29377 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c | |||
@@ -276,7 +276,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
276 | struct nouveau_fence *fence; | 276 | struct nouveau_fence *fence; |
277 | int ret; | 277 | int ret; |
278 | 278 | ||
279 | if (dev_priv->engine.graph.accel_blocked) | 279 | if (!dev_priv->channel) |
280 | return -ENODEV; | 280 | return -ENODEV; |
281 | 281 | ||
282 | s = kzalloc(sizeof(*s), GFP_KERNEL); | 282 | s = kzalloc(sizeof(*s), GFP_KERNEL); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c index 126216fbd789..02c6f37d8bd7 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.c +++ b/drivers/gpu/drm/nouveau/nouveau_drv.c | |||
@@ -310,7 +310,6 @@ nouveau_pci_resume(struct pci_dev *pdev) | |||
310 | if (dev_priv->eng[i]) | 310 | if (dev_priv->eng[i]) |
311 | dev_priv->eng[i]->init(dev, i); | 311 | dev_priv->eng[i]->init(dev, i); |
312 | } | 312 | } |
313 | engine->graph.init(dev); | ||
314 | engine->fifo.init(dev); | 313 | engine->fifo.init(dev); |
315 | 314 | ||
316 | nouveau_irq_postinstall(dev); | 315 | nouveau_irq_postinstall(dev); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 413e2ba5e4d8..3f90f3891f59 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -241,10 +241,7 @@ struct nouveau_channel { | |||
241 | struct nouveau_gpuobj *cache; | 241 | struct nouveau_gpuobj *cache; |
242 | void *fifo_priv; | 242 | void *fifo_priv; |
243 | 243 | ||
244 | /* PGRAPH context */ | 244 | /* Execution engine contexts */ |
245 | /* XXX may be merge 2 pointers as private data ??? */ | ||
246 | struct nouveau_gpuobj *ramin_grctx; | ||
247 | void *pgraph_ctx; | ||
248 | void *engctx[NVOBJ_ENGINE_NR]; | 245 | void *engctx[NVOBJ_ENGINE_NR]; |
249 | 246 | ||
250 | /* NV50 VM */ | 247 | /* NV50 VM */ |
@@ -372,30 +369,6 @@ struct nouveau_fifo_engine { | |||
372 | void (*tlb_flush)(struct drm_device *dev); | 369 | void (*tlb_flush)(struct drm_device *dev); |
373 | }; | 370 | }; |
374 | 371 | ||
375 | struct nouveau_pgraph_engine { | ||
376 | bool accel_blocked; | ||
377 | bool registered; | ||
378 | int grctx_size; | ||
379 | void *priv; | ||
380 | |||
381 | /* NV2x/NV3x context table (0x400780) */ | ||
382 | struct nouveau_gpuobj *ctx_table; | ||
383 | |||
384 | int (*init)(struct drm_device *); | ||
385 | void (*takedown)(struct drm_device *); | ||
386 | |||
387 | void (*fifo_access)(struct drm_device *, bool); | ||
388 | |||
389 | struct nouveau_channel *(*channel)(struct drm_device *); | ||
390 | int (*create_context)(struct nouveau_channel *); | ||
391 | void (*destroy_context)(struct nouveau_channel *); | ||
392 | int (*load_context)(struct nouveau_channel *); | ||
393 | int (*unload_context)(struct drm_device *); | ||
394 | int (*object_new)(struct nouveau_channel *chan, u32 handle, u16 class); | ||
395 | void (*tlb_flush)(struct drm_device *dev); | ||
396 | |||
397 | }; | ||
398 | |||
399 | struct nouveau_display_engine { | 372 | struct nouveau_display_engine { |
400 | void *priv; | 373 | void *priv; |
401 | int (*early_init)(struct drm_device *); | 374 | int (*early_init)(struct drm_device *); |
@@ -522,7 +495,6 @@ struct nouveau_engine { | |||
522 | struct nouveau_mc_engine mc; | 495 | struct nouveau_mc_engine mc; |
523 | struct nouveau_timer_engine timer; | 496 | struct nouveau_timer_engine timer; |
524 | struct nouveau_fb_engine fb; | 497 | struct nouveau_fb_engine fb; |
525 | struct nouveau_pgraph_engine graph; | ||
526 | struct nouveau_fifo_engine fifo; | 498 | struct nouveau_fifo_engine fifo; |
527 | struct nouveau_display_engine display; | 499 | struct nouveau_display_engine display; |
528 | struct nouveau_gpio_engine gpio; | 500 | struct nouveau_gpio_engine gpio; |
@@ -1168,8 +1140,6 @@ extern struct nouveau_enum nv50_data_error_names[]; | |||
1168 | 1140 | ||
1169 | /* nvc0_graph.c */ | 1141 | /* nvc0_graph.c */ |
1170 | extern int nvc0_graph_create(struct drm_device *); | 1142 | extern int nvc0_graph_create(struct drm_device *); |
1171 | extern void nvc0_graph_fifo_access(struct drm_device *, bool); | ||
1172 | extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); | ||
1173 | 1143 | ||
1174 | /* nv84_crypt.c */ | 1144 | /* nv84_crypt.c */ |
1175 | extern int nv84_crypt_create(struct drm_device *); | 1145 | extern int nv84_crypt_create(struct drm_device *); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c index 9ea3ab98c169..8f97016f5b26 100644 --- a/drivers/gpu/drm/nouveau/nouveau_object.c +++ b/drivers/gpu/drm/nouveau/nouveau_object.c | |||
@@ -620,7 +620,6 @@ int | |||
620 | nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class) | 620 | nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class) |
621 | { | 621 | { |
622 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; | 622 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; |
623 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; | ||
624 | struct drm_device *dev = chan->dev; | 623 | struct drm_device *dev = chan->dev; |
625 | struct nouveau_gpuobj_class *oc; | 624 | struct nouveau_gpuobj_class *oc; |
626 | int ret; | 625 | int ret; |
@@ -628,37 +627,25 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class) | |||
628 | NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class); | 627 | NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class); |
629 | 628 | ||
630 | list_for_each_entry(oc, &dev_priv->classes, head) { | 629 | list_for_each_entry(oc, &dev_priv->classes, head) { |
631 | if (oc->id == class) | 630 | struct nouveau_exec_engine *eng = dev_priv->eng[oc->engine]; |
632 | goto found; | ||
633 | } | ||
634 | 631 | ||
635 | NV_ERROR(dev, "illegal object class: 0x%x\n", class); | 632 | if (oc->id != class) |
636 | return -EINVAL; | 633 | continue; |
637 | 634 | ||
638 | found: | 635 | if (oc->engine == NVOBJ_ENGINE_SW) |
639 | if (!dev_priv->eng[oc->engine]) { | ||
640 | switch (oc->engine) { | ||
641 | case NVOBJ_ENGINE_SW: | ||
642 | return nouveau_gpuobj_sw_new(chan, handle, class); | 636 | return nouveau_gpuobj_sw_new(chan, handle, class); |
643 | case NVOBJ_ENGINE_GR: | ||
644 | if ((dev_priv->card_type >= NV_20 && !chan->ramin_grctx) || | ||
645 | (dev_priv->card_type < NV_20 && !chan->pgraph_ctx)) { | ||
646 | ret = pgraph->create_context(chan); | ||
647 | if (ret) | ||
648 | return ret; | ||
649 | } | ||
650 | 637 | ||
651 | return pgraph->object_new(chan, handle, class); | 638 | if (!chan->engctx[oc->engine]) { |
639 | ret = eng->context_new(chan, oc->engine); | ||
640 | if (ret) | ||
641 | return ret; | ||
652 | } | 642 | } |
653 | } | ||
654 | 643 | ||
655 | if (!chan->engctx[oc->engine]) { | 644 | return eng->object_new(chan, oc->engine, handle, class); |
656 | ret = dev_priv->eng[oc->engine]->context_new(chan, oc->engine); | ||
657 | if (ret) | ||
658 | return ret; | ||
659 | } | 645 | } |
660 | 646 | ||
661 | return dev_priv->eng[oc->engine]->object_new(chan, oc->engine, handle, class); | 647 | NV_ERROR(dev, "illegal object class: 0x%x\n", class); |
648 | return -EINVAL; | ||
662 | } | 649 | } |
663 | 650 | ||
664 | static int | 651 | static int |
@@ -676,9 +663,6 @@ nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan) | |||
676 | size = 0x2000; | 663 | size = 0x2000; |
677 | base = 0; | 664 | base = 0; |
678 | 665 | ||
679 | /* PGRAPH context */ | ||
680 | size += dev_priv->engine.graph.grctx_size; | ||
681 | |||
682 | if (dev_priv->card_type == NV_50) { | 666 | if (dev_priv->card_type == NV_50) { |
683 | /* Various fixed table thingos */ | 667 | /* Various fixed table thingos */ |
684 | size += 0x1400; /* mostly unknown stuff */ | 668 | size += 0x1400; /* mostly unknown stuff */ |
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index 052a26777992..e50156cdcabd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c | |||
@@ -65,10 +65,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
65 | engine->timer.takedown = nv04_timer_takedown; | 65 | engine->timer.takedown = nv04_timer_takedown; |
66 | engine->fb.init = nv04_fb_init; | 66 | engine->fb.init = nv04_fb_init; |
67 | engine->fb.takedown = nv04_fb_takedown; | 67 | engine->fb.takedown = nv04_fb_takedown; |
68 | engine->graph.init = nouveau_stub_init; | ||
69 | engine->graph.takedown = nouveau_stub_takedown; | ||
70 | engine->graph.channel = nvc0_graph_channel; | ||
71 | engine->graph.fifo_access = nvc0_graph_fifo_access; | ||
72 | engine->fifo.channels = 16; | 68 | engine->fifo.channels = 16; |
73 | engine->fifo.init = nv04_fifo_init; | 69 | engine->fifo.init = nv04_fifo_init; |
74 | engine->fifo.takedown = nv04_fifo_fini; | 70 | engine->fifo.takedown = nv04_fifo_fini; |
@@ -117,10 +113,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
117 | engine->fb.init_tile_region = nv10_fb_init_tile_region; | 113 | engine->fb.init_tile_region = nv10_fb_init_tile_region; |
118 | engine->fb.set_tile_region = nv10_fb_set_tile_region; | 114 | engine->fb.set_tile_region = nv10_fb_set_tile_region; |
119 | engine->fb.free_tile_region = nv10_fb_free_tile_region; | 115 | engine->fb.free_tile_region = nv10_fb_free_tile_region; |
120 | engine->graph.init = nouveau_stub_init; | ||
121 | engine->graph.takedown = nouveau_stub_takedown; | ||
122 | engine->graph.channel = nvc0_graph_channel; | ||
123 | engine->graph.fifo_access = nvc0_graph_fifo_access; | ||
124 | engine->fifo.channels = 32; | 116 | engine->fifo.channels = 32; |
125 | engine->fifo.init = nv10_fifo_init; | 117 | engine->fifo.init = nv10_fifo_init; |
126 | engine->fifo.takedown = nv04_fifo_fini; | 118 | engine->fifo.takedown = nv04_fifo_fini; |
@@ -169,10 +161,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
169 | engine->fb.init_tile_region = nv10_fb_init_tile_region; | 161 | engine->fb.init_tile_region = nv10_fb_init_tile_region; |
170 | engine->fb.set_tile_region = nv10_fb_set_tile_region; | 162 | engine->fb.set_tile_region = nv10_fb_set_tile_region; |
171 | engine->fb.free_tile_region = nv10_fb_free_tile_region; | 163 | engine->fb.free_tile_region = nv10_fb_free_tile_region; |
172 | engine->graph.init = nouveau_stub_init; | ||
173 | engine->graph.takedown = nouveau_stub_takedown; | ||
174 | engine->graph.channel = nvc0_graph_channel; | ||
175 | engine->graph.fifo_access = nvc0_graph_fifo_access; | ||
176 | engine->fifo.channels = 32; | 164 | engine->fifo.channels = 32; |
177 | engine->fifo.init = nv10_fifo_init; | 165 | engine->fifo.init = nv10_fifo_init; |
178 | engine->fifo.takedown = nv04_fifo_fini; | 166 | engine->fifo.takedown = nv04_fifo_fini; |
@@ -221,10 +209,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
221 | engine->fb.init_tile_region = nv30_fb_init_tile_region; | 209 | engine->fb.init_tile_region = nv30_fb_init_tile_region; |
222 | engine->fb.set_tile_region = nv10_fb_set_tile_region; | 210 | engine->fb.set_tile_region = nv10_fb_set_tile_region; |
223 | engine->fb.free_tile_region = nv30_fb_free_tile_region; | 211 | engine->fb.free_tile_region = nv30_fb_free_tile_region; |
224 | engine->graph.init = nouveau_stub_init; | ||
225 | engine->graph.takedown = nouveau_stub_takedown; | ||
226 | engine->graph.channel = nvc0_graph_channel; | ||
227 | engine->graph.fifo_access = nvc0_graph_fifo_access; | ||
228 | engine->fifo.channels = 32; | 212 | engine->fifo.channels = 32; |
229 | engine->fifo.init = nv10_fifo_init; | 213 | engine->fifo.init = nv10_fifo_init; |
230 | engine->fifo.takedown = nv04_fifo_fini; | 214 | engine->fifo.takedown = nv04_fifo_fini; |
@@ -276,10 +260,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
276 | engine->fb.init_tile_region = nv30_fb_init_tile_region; | 260 | engine->fb.init_tile_region = nv30_fb_init_tile_region; |
277 | engine->fb.set_tile_region = nv40_fb_set_tile_region; | 261 | engine->fb.set_tile_region = nv40_fb_set_tile_region; |
278 | engine->fb.free_tile_region = nv30_fb_free_tile_region; | 262 | engine->fb.free_tile_region = nv30_fb_free_tile_region; |
279 | engine->graph.init = nouveau_stub_init; | ||
280 | engine->graph.takedown = nouveau_stub_takedown; | ||
281 | engine->graph.fifo_access = nvc0_graph_fifo_access; | ||
282 | engine->graph.channel = nvc0_graph_channel; | ||
283 | engine->fifo.channels = 32; | 263 | engine->fifo.channels = 32; |
284 | engine->fifo.init = nv40_fifo_init; | 264 | engine->fifo.init = nv40_fifo_init; |
285 | engine->fifo.takedown = nv04_fifo_fini; | 265 | engine->fifo.takedown = nv04_fifo_fini; |
@@ -334,10 +314,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
334 | engine->timer.takedown = nv04_timer_takedown; | 314 | engine->timer.takedown = nv04_timer_takedown; |
335 | engine->fb.init = nv50_fb_init; | 315 | engine->fb.init = nv50_fb_init; |
336 | engine->fb.takedown = nv50_fb_takedown; | 316 | engine->fb.takedown = nv50_fb_takedown; |
337 | engine->graph.init = nouveau_stub_init; | ||
338 | engine->graph.takedown = nouveau_stub_takedown; | ||
339 | engine->graph.fifo_access = nvc0_graph_fifo_access; | ||
340 | engine->graph.channel = nvc0_graph_channel; | ||
341 | engine->fifo.channels = 128; | 317 | engine->fifo.channels = 128; |
342 | engine->fifo.init = nv50_fifo_init; | 318 | engine->fifo.init = nv50_fifo_init; |
343 | engine->fifo.takedown = nv50_fifo_takedown; | 319 | engine->fifo.takedown = nv50_fifo_takedown; |
@@ -411,8 +387,6 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
411 | engine->timer.takedown = nv04_timer_takedown; | 387 | engine->timer.takedown = nv04_timer_takedown; |
412 | engine->fb.init = nvc0_fb_init; | 388 | engine->fb.init = nvc0_fb_init; |
413 | engine->fb.takedown = nvc0_fb_takedown; | 389 | engine->fb.takedown = nvc0_fb_takedown; |
414 | engine->graph.fifo_access = nvc0_graph_fifo_access; | ||
415 | engine->graph.channel = nvc0_graph_channel; | ||
416 | engine->fifo.channels = 128; | 390 | engine->fifo.channels = 128; |
417 | engine->fifo.init = nvc0_fifo_init; | 391 | engine->fifo.init = nvc0_fifo_init; |
418 | engine->fifo.takedown = nvc0_fifo_takedown; | 392 | engine->fifo.takedown = nvc0_fifo_takedown; |
@@ -624,9 +598,7 @@ nouveau_card_init(struct drm_device *dev) | |||
624 | break; | 598 | break; |
625 | } | 599 | } |
626 | 600 | ||
627 | if (nouveau_noaccel) | 601 | if (!nouveau_noaccel) { |
628 | engine->graph.accel_blocked = true; | ||
629 | else { | ||
630 | for (e = 0; e < NVOBJ_ENGINE_NR; e++) { | 602 | for (e = 0; e < NVOBJ_ENGINE_NR; e++) { |
631 | if (dev_priv->eng[e]) { | 603 | if (dev_priv->eng[e]) { |
632 | ret = dev_priv->eng[e]->init(dev, e); | 604 | ret = dev_priv->eng[e]->init(dev, e); |
@@ -635,15 +607,10 @@ nouveau_card_init(struct drm_device *dev) | |||
635 | } | 607 | } |
636 | } | 608 | } |
637 | 609 | ||
638 | /* PGRAPH */ | ||
639 | ret = engine->graph.init(dev); | ||
640 | if (ret) | ||
641 | goto out_engine; | ||
642 | |||
643 | /* PFIFO */ | 610 | /* PFIFO */ |
644 | ret = engine->fifo.init(dev); | 611 | ret = engine->fifo.init(dev); |
645 | if (ret) | 612 | if (ret) |
646 | goto out_graph; | 613 | goto out_engine; |
647 | } | 614 | } |
648 | 615 | ||
649 | ret = engine->display.create(dev); | 616 | ret = engine->display.create(dev); |
@@ -660,7 +627,7 @@ nouveau_card_init(struct drm_device *dev) | |||
660 | 627 | ||
661 | /* what about PVIDEO/PCRTC/PRAMDAC etc? */ | 628 | /* what about PVIDEO/PCRTC/PRAMDAC etc? */ |
662 | 629 | ||
663 | if (!engine->graph.accel_blocked) { | 630 | if (dev_priv->eng[NVOBJ_ENGINE_GR]) { |
664 | ret = nouveau_fence_init(dev); | 631 | ret = nouveau_fence_init(dev); |
665 | if (ret) | 632 | if (ret) |
666 | goto out_irq; | 633 | goto out_irq; |
@@ -684,9 +651,6 @@ out_vblank: | |||
684 | out_fifo: | 651 | out_fifo: |
685 | if (!nouveau_noaccel) | 652 | if (!nouveau_noaccel) |
686 | engine->fifo.takedown(dev); | 653 | engine->fifo.takedown(dev); |
687 | out_graph: | ||
688 | if (!nouveau_noaccel) | ||
689 | engine->graph.takedown(dev); | ||
690 | out_engine: | 654 | out_engine: |
691 | if (!nouveau_noaccel) { | 655 | if (!nouveau_noaccel) { |
692 | for (e = e - 1; e >= 0; e--) { | 656 | for (e = e - 1; e >= 0; e--) { |
@@ -728,14 +692,13 @@ static void nouveau_card_takedown(struct drm_device *dev) | |||
728 | struct nouveau_engine *engine = &dev_priv->engine; | 692 | struct nouveau_engine *engine = &dev_priv->engine; |
729 | int e; | 693 | int e; |
730 | 694 | ||
731 | if (!engine->graph.accel_blocked) { | 695 | if (dev_priv->channel) { |
732 | nouveau_fence_fini(dev); | 696 | nouveau_fence_fini(dev); |
733 | nouveau_channel_put_unlocked(&dev_priv->channel); | 697 | nouveau_channel_put_unlocked(&dev_priv->channel); |
734 | } | 698 | } |
735 | 699 | ||
736 | if (!nouveau_noaccel) { | 700 | if (!nouveau_noaccel) { |
737 | engine->fifo.takedown(dev); | 701 | engine->fifo.takedown(dev); |
738 | engine->graph.takedown(dev); | ||
739 | for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) { | 702 | for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) { |
740 | if (dev_priv->eng[e]) { | 703 | if (dev_priv->eng[e]) { |
741 | dev_priv->eng[e]->fini(dev, e); | 704 | dev_priv->eng[e]->fini(dev, e); |
diff --git a/drivers/gpu/drm/nouveau/nv20_graph.c b/drivers/gpu/drm/nouveau/nv20_graph.c index b47e9e226e4d..affc7d7dd029 100644 --- a/drivers/gpu/drm/nouveau/nv20_graph.c +++ b/drivers/gpu/drm/nouveau/nv20_graph.c | |||
@@ -752,8 +752,7 @@ nv20_graph_create(struct drm_device *dev) | |||
752 | pgraph->grctx_user = 0x0000; | 752 | pgraph->grctx_user = 0x0000; |
753 | break; | 753 | break; |
754 | default: | 754 | default: |
755 | NV_ERROR(dev, "unknown nv20, disabling acceleration\n"); | 755 | NV_ERROR(dev, "PGRAPH: unknown chipset\n"); |
756 | dev_priv->engine.graph.accel_blocked = true; | ||
757 | return 0; | 756 | return 0; |
758 | } | 757 | } |
759 | } else { | 758 | } else { |
@@ -774,8 +773,7 @@ nv20_graph_create(struct drm_device *dev) | |||
774 | pgraph->grctx_size = NV35_36_GRCTX_SIZE; | 773 | pgraph->grctx_size = NV35_36_GRCTX_SIZE; |
775 | break; | 774 | break; |
776 | default: | 775 | default: |
777 | NV_ERROR(dev, "unknown nv30, disabling acceleration\n"); | 776 | NV_ERROR(dev, "PGRAPH: unknown chipset\n"); |
778 | dev_priv->engine.graph.accel_blocked = true; | ||
779 | return 0; | 777 | return 0; |
780 | } | 778 | } |
781 | } | 779 | } |
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c index bffa486ec7ce..5794cdef32c5 100644 --- a/drivers/gpu/drm/nouveau/nv50_graph.c +++ b/drivers/gpu/drm/nouveau/nv50_graph.c | |||
@@ -1053,7 +1053,6 @@ nv50_graph_create(struct drm_device *dev) | |||
1053 | ret = nv50_grctx_init(&ctx); | 1053 | ret = nv50_grctx_init(&ctx); |
1054 | if (ret) { | 1054 | if (ret) { |
1055 | NV_ERROR(dev, "PGRAPH: ctxprog build failed\n"); | 1055 | NV_ERROR(dev, "PGRAPH: ctxprog build failed\n"); |
1056 | dev_priv->engine.graph.accel_blocked = true; | ||
1057 | kfree(pgraph); | 1056 | kfree(pgraph); |
1058 | return 0; | 1057 | return 0; |
1059 | } | 1058 | } |
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c index 24f036c85f30..e8473c006845 100644 --- a/drivers/gpu/drm/nouveau/nvc0_graph.c +++ b/drivers/gpu/drm/nouveau/nvc0_graph.c | |||
@@ -30,17 +30,6 @@ | |||
30 | #include "nouveau_mm.h" | 30 | #include "nouveau_mm.h" |
31 | #include "nvc0_graph.h" | 31 | #include "nvc0_graph.h" |
32 | 32 | ||
33 | void | ||
34 | nvc0_graph_fifo_access(struct drm_device *dev, bool enabled) | ||
35 | { | ||
36 | } | ||
37 | |||
38 | struct nouveau_channel * | ||
39 | nvc0_graph_channel(struct drm_device *dev) | ||
40 | { | ||
41 | return NULL; | ||
42 | } | ||
43 | |||
44 | static int | 33 | static int |
45 | nvc0_graph_load_context(struct nouveau_channel *chan) | 34 | nvc0_graph_load_context(struct nouveau_channel *chan) |
46 | { | 35 | { |
@@ -508,23 +497,8 @@ nvc0_graph_init_ctxctl(struct drm_device *dev) | |||
508 | static int | 497 | static int |
509 | nvc0_graph_init(struct drm_device *dev, int engine) | 498 | nvc0_graph_init(struct drm_device *dev, int engine) |
510 | { | 499 | { |
511 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
512 | int ret; | 500 | int ret; |
513 | 501 | ||
514 | dev_priv->engine.graph.accel_blocked = true; | ||
515 | |||
516 | switch (dev_priv->chipset) { | ||
517 | case 0xc0: | ||
518 | case 0xc3: | ||
519 | case 0xc4: | ||
520 | break; | ||
521 | default: | ||
522 | NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n"); | ||
523 | if (nouveau_noaccel != 0) | ||
524 | return 0; | ||
525 | break; | ||
526 | } | ||
527 | |||
528 | nv_mask(dev, 0x000200, 0x18001000, 0x00000000); | 502 | nv_mask(dev, 0x000200, 0x18001000, 0x00000000); |
529 | nv_mask(dev, 0x000200, 0x18001000, 0x18001000); | 503 | nv_mask(dev, 0x000200, 0x18001000, 0x18001000); |
530 | 504 | ||
@@ -551,8 +525,9 @@ nvc0_graph_init(struct drm_device *dev, int engine) | |||
551 | nv_wr32(dev, 0x400054, 0x34ce3464); | 525 | nv_wr32(dev, 0x400054, 0x34ce3464); |
552 | 526 | ||
553 | ret = nvc0_graph_init_ctxctl(dev); | 527 | ret = nvc0_graph_init_ctxctl(dev); |
554 | if (ret == 0) | 528 | if (ret) |
555 | dev_priv->engine.graph.accel_blocked = false; | 529 | return ret; |
530 | |||
556 | return 0; | 531 | return 0; |
557 | } | 532 | } |
558 | 533 | ||
@@ -686,6 +661,16 @@ nvc0_graph_create(struct drm_device *dev) | |||
686 | struct nvc0_graph_priv *priv; | 661 | struct nvc0_graph_priv *priv; |
687 | int ret, gpc, i; | 662 | int ret, gpc, i; |
688 | 663 | ||
664 | switch (dev_priv->chipset) { | ||
665 | case 0xc0: | ||
666 | case 0xc3: | ||
667 | case 0xc4: | ||
668 | break; | ||
669 | default: | ||
670 | NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n"); | ||
671 | return 0; | ||
672 | } | ||
673 | |||
689 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | 674 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
690 | if (!priv) | 675 | if (!priv) |
691 | return -ENOMEM; | 676 | return -ENOMEM; |