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-rw-r--r--MAINTAINERS10
-rw-r--r--drivers/net/Kconfig27
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/ixgbe/Makefile36
-rw-r--r--drivers/net/ixgbe/ixgbe.h259
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c589
-rw-r--r--drivers/net/ixgbe/ixgbe_common.c1175
-rw-r--r--drivers/net/ixgbe/ixgbe_common.h86
-rw-r--r--drivers/net/ixgbe/ixgbe_ethtool.c943
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c2873
-rw-r--r--drivers/net/ixgbe/ixgbe_phy.c494
-rw-r--r--drivers/net/ixgbe/ixgbe_phy.h50
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h1332
13 files changed, 7867 insertions, 8 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index e0861f7e1ccf..c35eb125e1ca 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2030,16 +2030,14 @@ W: http://sourceforge.net/projects/e1000/
2030S: Supported 2030S: Supported
2031 2031
2032INTEL PRO/10GbE SUPPORT 2032INTEL PRO/10GbE SUPPORT
2033P: Jeff Kirsher
2034M: jeffrey.t.kirsher@intel.com
2035P: Ayyappan Veeraiyan 2033P: Ayyappan Veeraiyan
2036M: ayyappan.veeraiyan@intel.com 2034M: ayyappan.veeraiyan@intel.com
2037P: John Ronciak
2038M: john.ronciak@intel.com
2039P: Jesse Brandeburg
2040M: jesse.brandeburg@intel.com
2041P: Auke Kok 2035P: Auke Kok
2042M: auke-jan.h.kok@intel.com 2036M: auke-jan.h.kok@intel.com
2037P: Jesse Brandeburg
2038M: jesse.brandeburg@intel.com
2039P: John Ronciak
2040M: john.ronciak@intel.com
2043L: e1000-devel@lists.sourceforge.net 2041L: e1000-devel@lists.sourceforge.net
2044W: http://sourceforge.net/projects/e1000/ 2042W: http://sourceforge.net/projects/e1000/
2045S: Supported 2043S: Supported
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index eeac2f49aae3..76db0bc9452d 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2518,12 +2518,35 @@ config EHEA
2518 To compile the driver as a module, choose M here. The module 2518 To compile the driver as a module, choose M here. The module
2519 will be called ehea. 2519 will be called ehea.
2520 2520
2521config IXGBE
2522 tristate "Intel(R) 10GbE PCI Express adapters support"
2523 depends on PCI
2524 ---help---
2525 This driver supports Intel(R) 10GbE PCI Express family of
2526 adapters. For more information on how to identify your adapter, go
2527 to the Adapter & Driver ID Guide at:
2528
2529 <http://support.intel.com/support/network/adapter/pro100/21397.htm>
2530
2531 For general information and support, go to the Intel support
2532 website at:
2533
2534 <http://support.intel.com>
2535
2536 More specific information on configuring the driver is in
2537 <file:Documentation/networking/ixgbe.txt>.
2538
2539 To compile this driver as a module, choose M here and read
2540 <file:Documentation/networking/net-modules.txt>. The module
2541 will be called ixgbe.
2542
2521config IXGB 2543config IXGB
2522 tristate "Intel(R) PRO/10GbE support" 2544 tristate "Intel(R) PRO/10GbE support"
2523 depends on PCI 2545 depends on PCI
2524 ---help--- 2546 ---help---
2525 This driver supports Intel(R) PRO/10GbE family of 2547 This driver supports Intel(R) PRO/10GbE family of adapters for
2526 adapters. For more information on how to identify your adapter, go 2548 PCI-X type cards. For PCI-E type cards, use the "ixgbe" driver
2549 instead. For more information on how to identify your adapter, go
2527 to the Adapter & Driver ID Guide at: 2550 to the Adapter & Driver ID Guide at:
2528 2551
2529 <http://support.intel.com/support/network/adapter/pro100/21397.htm> 2552 <http://support.intel.com/support/network/adapter/pro100/21397.htm>
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 0d2b4bee587c..c23ffdbe2599 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -5,6 +5,7 @@
5obj-$(CONFIG_E1000) += e1000/ 5obj-$(CONFIG_E1000) += e1000/
6obj-$(CONFIG_E1000E) += e1000e/ 6obj-$(CONFIG_E1000E) += e1000e/
7obj-$(CONFIG_IBM_EMAC) += ibm_emac/ 7obj-$(CONFIG_IBM_EMAC) += ibm_emac/
8obj-$(CONFIG_IXGBE) += ixgbe/
8obj-$(CONFIG_IXGB) += ixgb/ 9obj-$(CONFIG_IXGB) += ixgb/
9obj-$(CONFIG_CHELSIO_T1) += chelsio/ 10obj-$(CONFIG_CHELSIO_T1) += chelsio/
10obj-$(CONFIG_CHELSIO_T3) += cxgb3/ 11obj-$(CONFIG_CHELSIO_T3) += cxgb3/
diff --git a/drivers/net/ixgbe/Makefile b/drivers/net/ixgbe/Makefile
new file mode 100644
index 000000000000..ccd83d9f579e
--- /dev/null
+++ b/drivers/net/ixgbe/Makefile
@@ -0,0 +1,36 @@
1################################################################################
2#
3# Intel 10 Gigabit PCI Express Linux driver
4# Copyright(c) 1999 - 2007 Intel Corporation.
5#
6# This program is free software; you can redistribute it and/or modify it
7# under the terms and conditions of the GNU General Public License,
8# version 2, as published by the Free Software Foundation.
9#
10# This program is distributed in the hope it will be useful, but WITHOUT
11# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13# more details.
14#
15# You should have received a copy of the GNU General Public License along with
16# this program; if not, write to the Free Software Foundation, Inc.,
17# 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18#
19# The full GNU General Public License is included in this distribution in
20# the file called "COPYING".
21#
22# Contact Information:
23# Linux NICS <linux.nics@intel.com>
24# e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25# Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26#
27################################################################################
28
29#
30# Makefile for the Intel(R) 10GbE PCI Express ethernet driver
31#
32
33obj-$(CONFIG_IXGBE) += ixgbe.o
34
35ixgbe-objs := ixgbe_main.o ixgbe_common.o ixgbe_ethtool.o \
36 ixgbe_82598.o ixgbe_phy.o
diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h
new file mode 100644
index 000000000000..c160a7d91e21
--- /dev/null
+++ b/drivers/net/ixgbe/ixgbe.h
@@ -0,0 +1,259 @@
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _IXGBE_H_
30#define _IXGBE_H_
31
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
35
36#include "ixgbe_type.h"
37#include "ixgbe_common.h"
38
39
40#define IXGBE_ERR(args...) printk(KERN_ERR "ixgbe: " args)
41
42#define PFX "ixgbe: "
43#define DPRINTK(nlevel, klevel, fmt, args...) \
44 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
45 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
46 __FUNCTION__ , ## args)))
47
48/* TX/RX descriptor defines */
49#define IXGBE_DEFAULT_TXD 1024
50#define IXGBE_MAX_TXD 4096
51#define IXGBE_MIN_TXD 64
52
53#define IXGBE_DEFAULT_RXD 1024
54#define IXGBE_MAX_RXD 4096
55#define IXGBE_MIN_RXD 64
56
57#define IXGBE_DEFAULT_RXQ 1
58#define IXGBE_MAX_RXQ 1
59#define IXGBE_MIN_RXQ 1
60
61#define IXGBE_DEFAULT_ITR_RX_USECS 125 /* 8k irqs/sec */
62#define IXGBE_DEFAULT_ITR_TX_USECS 250 /* 4k irqs/sec */
63#define IXGBE_MIN_ITR_USECS 100 /* 500k irqs/sec */
64#define IXGBE_MAX_ITR_USECS 10000 /* 100 irqs/sec */
65
66/* flow control */
67#define IXGBE_DEFAULT_FCRTL 0x10000
68#define IXGBE_MIN_FCRTL 0
69#define IXGBE_MAX_FCRTL 0x7FF80
70#define IXGBE_DEFAULT_FCRTH 0x20000
71#define IXGBE_MIN_FCRTH 0
72#define IXGBE_MAX_FCRTH 0x7FFF0
73#define IXGBE_DEFAULT_FCPAUSE 0x6800 /* may be too long */
74#define IXGBE_MIN_FCPAUSE 0
75#define IXGBE_MAX_FCPAUSE 0xFFFF
76
77/* Supported Rx Buffer Sizes */
78#define IXGBE_RXBUFFER_64 64 /* Used for packet split */
79#define IXGBE_RXBUFFER_128 128 /* Used for packet split */
80#define IXGBE_RXBUFFER_256 256 /* Used for packet split */
81#define IXGBE_RXBUFFER_2048 2048
82
83#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
84
85#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
86
87/* How many Tx Descriptors do we need to call netif_wake_queue? */
88#define IXGBE_TX_QUEUE_WAKE 16
89
90/* How many Rx Buffers do we bundle into one write to the hardware ? */
91#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
92
93#define IXGBE_TX_FLAGS_CSUM (u32)(1)
94#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
95#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
96#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
97#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
98#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
99
100/* wrapper around a pointer to a socket buffer,
101 * so a DMA handle can be stored along with the buffer */
102struct ixgbe_tx_buffer {
103 struct sk_buff *skb;
104 dma_addr_t dma;
105 unsigned long time_stamp;
106 u16 length;
107 u16 next_to_watch;
108};
109
110struct ixgbe_rx_buffer {
111 struct sk_buff *skb;
112 dma_addr_t dma;
113 struct page *page;
114 dma_addr_t page_dma;
115};
116
117struct ixgbe_queue_stats {
118 u64 packets;
119 u64 bytes;
120};
121
122struct ixgbe_ring {
123 struct ixgbe_adapter *adapter; /* backlink */
124 void *desc; /* descriptor ring memory */
125 dma_addr_t dma; /* phys. address of descriptor ring */
126 unsigned int size; /* length in bytes */
127 unsigned int count; /* amount of descriptors */
128 unsigned int next_to_use;
129 unsigned int next_to_clean;
130
131 union {
132 struct ixgbe_tx_buffer *tx_buffer_info;
133 struct ixgbe_rx_buffer *rx_buffer_info;
134 };
135
136 u16 head;
137 u16 tail;
138
139 /* To protect race between sender and clean_tx_irq */
140 spinlock_t tx_lock;
141
142 struct ixgbe_queue_stats stats;
143
144 u32 eims_value;
145 u16 itr_register;
146
147 char name[IFNAMSIZ + 5];
148 u16 work_limit; /* max work per interrupt */
149};
150
151/* Helper macros to switch between ints/sec and what the register uses.
152 * And yes, it's the same math going both ways.
153 */
154#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
155 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
156#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
157
158#define IXGBE_DESC_UNUSED(R) \
159 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
160 (R)->next_to_clean - (R)->next_to_use - 1)
161
162#define IXGBE_RX_DESC_ADV(R, i) \
163 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
164#define IXGBE_TX_DESC_ADV(R, i) \
165 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
166#define IXGBE_TX_CTXTDESC_ADV(R, i) \
167 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
168
169#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
170
171/* board specific private data structure */
172struct ixgbe_adapter {
173 struct timer_list watchdog_timer;
174 struct vlan_group *vlgrp;
175 u16 bd_number;
176 u16 rx_buf_len;
177 atomic_t irq_sem;
178 struct work_struct reset_task;
179
180 /* TX */
181 struct ixgbe_ring *tx_ring; /* One per active queue */
182 struct napi_struct napi;
183 u64 restart_queue;
184 u64 lsc_int;
185 u64 hw_tso_ctxt;
186 u64 hw_tso6_ctxt;
187 u32 tx_timeout_count;
188 bool detect_tx_hung;
189
190 /* RX */
191 struct ixgbe_ring *rx_ring; /* One per active queue */
192 u64 hw_csum_tx_good;
193 u64 hw_csum_rx_error;
194 u64 hw_csum_rx_good;
195 u64 non_eop_descs;
196 int num_tx_queues;
197 int num_rx_queues;
198 struct msix_entry *msix_entries;
199
200 u64 rx_hdr_split;
201 u32 alloc_rx_page_failed;
202 u32 alloc_rx_buff_failed;
203
204 u32 flags;
205#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
206#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 1)
207#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 2)
208#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 3)
209#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 4)
210
211 /* Interrupt Throttle Rate */
212 u32 rx_eitr;
213 u32 tx_eitr;
214
215 /* OS defined structs */
216 struct net_device *netdev;
217 struct pci_dev *pdev;
218 struct net_device_stats net_stats;
219
220 /* structs defined in ixgbe_hw.h */
221 struct ixgbe_hw hw;
222 u16 msg_enable;
223 struct ixgbe_hw_stats stats;
224 char lsc_name[IFNAMSIZ + 5];
225
226 unsigned long state;
227 u64 tx_busy;
228};
229
230enum ixbge_state_t {
231 __IXGBE_TESTING,
232 __IXGBE_RESETTING,
233 __IXGBE_DOWN
234};
235
236enum ixgbe_boards {
237 board_82598AF,
238 board_82598EB,
239 board_82598AT,
240};
241
242extern struct ixgbe_info ixgbe_82598AF_info;
243extern struct ixgbe_info ixgbe_82598EB_info;
244extern struct ixgbe_info ixgbe_82598AT_info;
245
246extern char ixgbe_driver_name[];
247extern char ixgbe_driver_version[];
248
249extern int ixgbe_up(struct ixgbe_adapter *adapter);
250extern void ixgbe_down(struct ixgbe_adapter *adapter);
251extern void ixgbe_reset(struct ixgbe_adapter *adapter);
252extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
253extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
254extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
255 struct ixgbe_ring *rxdr);
256extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
257 struct ixgbe_ring *txdr);
258
259#endif /* _IXGBE_H_ */
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
new file mode 100644
index 000000000000..00ee20125ca9
--- /dev/null
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -0,0 +1,589 @@
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
33#include "ixgbe_type.h"
34#include "ixgbe_common.h"
35#include "ixgbe_phy.h"
36
37#define IXGBE_82598_MAX_TX_QUEUES 32
38#define IXGBE_82598_MAX_RX_QUEUES 64
39#define IXGBE_82598_RAR_ENTRIES 16
40
41static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw);
42static s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw, u32 *speed,
43 bool *autoneg);
44static s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw,
45 u32 *speed, bool *autoneg);
46static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
47static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw);
48static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, u32 *speed,
49 bool *link_up);
50static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw, u32 speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
53static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
54static s32 ixgbe_check_copper_link_82598(struct ixgbe_hw *hw, u32 *speed,
55 bool *link_up);
56static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, u32 speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
59static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
60
61
62static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
63{
64 hw->mac.num_rx_queues = IXGBE_82598_MAX_TX_QUEUES;
65 hw->mac.num_tx_queues = IXGBE_82598_MAX_RX_QUEUES;
66 hw->mac.num_rx_addrs = IXGBE_82598_RAR_ENTRIES;
67
68 return 0;
69}
70
71/**
72 * ixgbe_get_link_settings_82598 - Determines default link settings
73 * @hw: pointer to hardware structure
74 * @speed: pointer to link speed
75 * @autoneg: boolean auto-negotiation value
76 *
77 * Determines the default link settings by reading the AUTOC register.
78 **/
79static s32 ixgbe_get_link_settings_82598(struct ixgbe_hw *hw, u32 *speed,
80 bool *autoneg)
81{
82 s32 status = 0;
83 s32 autoc_reg;
84
85 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
86
87 if (hw->mac.link_settings_loaded) {
88 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
89 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
90 autoc_reg |= hw->mac.link_attach_type;
91 autoc_reg |= hw->mac.link_mode_select;
92 }
93
94 switch (autoc_reg & IXGBE_AUTOC_LMS_MASK) {
95 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
96 *speed = IXGBE_LINK_SPEED_1GB_FULL;
97 *autoneg = false;
98 break;
99
100 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
101 *speed = IXGBE_LINK_SPEED_10GB_FULL;
102 *autoneg = false;
103 break;
104
105 case IXGBE_AUTOC_LMS_1G_AN:
106 *speed = IXGBE_LINK_SPEED_1GB_FULL;
107 *autoneg = true;
108 break;
109
110 case IXGBE_AUTOC_LMS_KX4_AN:
111 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
112 *speed = IXGBE_LINK_SPEED_UNKNOWN;
113 if (autoc_reg & IXGBE_AUTOC_KX4_SUPP)
114 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
115 if (autoc_reg & IXGBE_AUTOC_KX_SUPP)
116 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
117 *autoneg = true;
118 break;
119
120 default:
121 status = IXGBE_ERR_LINK_SETUP;
122 break;
123 }
124
125 return status;
126}
127
128/**
129 * ixgbe_get_copper_link_settings_82598 - Determines default link settings
130 * @hw: pointer to hardware structure
131 * @speed: pointer to link speed
132 * @autoneg: boolean auto-negotiation value
133 *
134 * Determines the default link settings by reading the AUTOC register.
135 **/
136static s32 ixgbe_get_copper_link_settings_82598(struct ixgbe_hw *hw,
137 u32 *speed, bool *autoneg)
138{
139 s32 status = IXGBE_ERR_LINK_SETUP;
140 u16 speed_ability;
141
142 *speed = 0;
143 *autoneg = true;
144
145 status = ixgbe_read_phy_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
146 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
147 &speed_ability);
148
149 if (status == 0) {
150 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
151 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
152 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
153 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
154 }
155
156 return status;
157}
158
159/**
160 * ixgbe_get_media_type_82598 - Determines media type
161 * @hw: pointer to hardware structure
162 *
163 * Returns the media type (fiber, copper, backplane)
164 **/
165static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
166{
167 enum ixgbe_media_type media_type;
168
169 /* Media type for I82598 is based on device ID */
170 switch (hw->device_id) {
171 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
172 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
173 case IXGBE_DEV_ID_82598EB_CX4:
174 media_type = ixgbe_media_type_fiber;
175 break;
176 case IXGBE_DEV_ID_82598AT_DUAL_PORT:
177 media_type = ixgbe_media_type_copper;
178 break;
179 default:
180 media_type = ixgbe_media_type_unknown;
181 break;
182 }
183
184 return media_type;
185}
186
187/**
188 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
189 * @hw: pointer to hardware structure
190 *
191 * Configures link settings based on values in the ixgbe_hw struct.
192 * Restarts the link. Performs autonegotiation if needed.
193 **/
194static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
195{
196 u32 autoc_reg;
197 u32 links_reg;
198 u32 i;
199 s32 status = 0;
200
201 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
202
203 if (hw->mac.link_settings_loaded) {
204 autoc_reg &= ~IXGBE_AUTOC_LMS_ATTACH_TYPE;
205 autoc_reg &= ~IXGBE_AUTOC_LMS_MASK;
206 autoc_reg |= hw->mac.link_attach_type;
207 autoc_reg |= hw->mac.link_mode_select;
208
209 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
210 msleep(50);
211 }
212
213 /* Restart link */
214 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
215 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
216
217 /* Only poll for autoneg to complete if specified to do so */
218 if (hw->phy.autoneg_wait_to_complete) {
219 if (hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN ||
220 hw->mac.link_mode_select == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
221 links_reg = 0; /* Just in case Autoneg time = 0 */
222 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
223 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
224 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
225 break;
226 msleep(100);
227 }
228 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
229 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
230 hw_dbg(hw,
231 "Autonegotiation did not complete.\n");
232 }
233 }
234 }
235
236 /*
237 * We want to save off the original Flow Control configuration just in
238 * case we get disconnected and then reconnected into a different hub
239 * or switch with different Flow Control capabilities.
240 */
241 hw->fc.type = hw->fc.original_type;
242 ixgbe_setup_fc(hw, 0);
243
244 /* Add delay to filter out noises during initial link setup */
245 msleep(50);
246
247 return status;
248}
249
250/**
251 * ixgbe_check_mac_link_82598 - Get link/speed status
252 * @hw: pointer to hardware structure
253 * @speed: pointer to link speed
254 * @link_up: true is link is up, false otherwise
255 *
256 * Reads the links register to determine if link is up and the current speed
257 **/
258static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, u32 *speed,
259 bool *link_up)
260{
261 u32 links_reg;
262
263 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
264
265 if (links_reg & IXGBE_LINKS_UP)
266 *link_up = true;
267 else
268 *link_up = false;
269
270 if (links_reg & IXGBE_LINKS_SPEED)
271 *speed = IXGBE_LINK_SPEED_10GB_FULL;
272 else
273 *speed = IXGBE_LINK_SPEED_1GB_FULL;
274
275 return 0;
276}
277
278/**
279 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
280 * @hw: pointer to hardware structure
281 * @speed: new link speed
282 * @autoneg: true if auto-negotiation enabled
283 * @autoneg_wait_to_complete: true if waiting is needed to complete
284 *
285 * Set the link speed in the AUTOC register and restarts link.
286 **/
287static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
288 u32 speed, bool autoneg,
289 bool autoneg_wait_to_complete)
290{
291 s32 status = 0;
292
293 /* If speed is 10G, then check for CX4 or XAUI. */
294 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
295 (!(hw->mac.link_attach_type & IXGBE_AUTOC_10G_KX4)))
296 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
297 else if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && (!autoneg))
298 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
299 else if (autoneg) {
300 /* BX mode - Autonegotiate 1G */
301 if (!(hw->mac.link_attach_type & IXGBE_AUTOC_1G_PMA_PMD))
302 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_1G_AN;
303 else /* KX/KX4 mode */
304 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_KX4_AN_1G_AN;
305 } else {
306 status = IXGBE_ERR_LINK_SETUP;
307 }
308
309 if (status == 0) {
310 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
311
312 hw->mac.link_settings_loaded = true;
313 /*
314 * Setup and restart the link based on the new values in
315 * ixgbe_hw This will write the AUTOC register based on the new
316 * stored values
317 */
318 hw->phy.ops.setup(hw);
319 }
320
321 return status;
322}
323
324
325/**
326 * ixgbe_setup_copper_link_82598 - Setup copper link settings
327 * @hw: pointer to hardware structure
328 *
329 * Configures link settings based on values in the ixgbe_hw struct.
330 * Restarts the link. Performs autonegotiation if needed. Restart
331 * phy and wait for autonegotiate to finish. Then synchronize the
332 * MAC and PHY.
333 **/
334static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
335{
336 s32 status;
337 u32 speed = 0;
338 bool link_up = false;
339
340 /* Set up MAC */
341 hw->phy.ops.setup(hw);
342
343 /* Restart autonegotiation on PHY */
344 status = hw->phy.ops.setup(hw);
345
346 /* Synchronize MAC to PHY speed */
347 if (status == 0)
348 status = hw->phy.ops.check(hw, &speed, &link_up);
349
350 return status;
351}
352
353/**
354 * ixgbe_check_copper_link_82598 - Syncs MAC & PHY link settings
355 * @hw: pointer to hardware structure
356 * @speed: pointer to link speed
357 * @link_up: true if link is up, false otherwise
358 *
359 * Reads the mac link, phy link, and synchronizes the MAC to PHY.
360 **/
361static s32 ixgbe_check_copper_link_82598(struct ixgbe_hw *hw, u32 *speed,
362 bool *link_up)
363{
364 s32 status;
365 u32 phy_speed = 0;
366 bool phy_link = false;
367
368 /* This is the speed and link the MAC is set at */
369 hw->phy.ops.check(hw, speed, link_up);
370
371 /*
372 * Check current speed and link status of the PHY register.
373 * This is a vendor specific register and may have to
374 * be changed for other copper PHYs.
375 */
376 status = hw->phy.ops.check(hw, &phy_speed, &phy_link);
377
378 if ((status == 0) && (phy_link)) {
379 /*
380 * Check current link status of the MACs link's register
381 * matches that of the speed in the PHY register
382 */
383 if (*speed != phy_speed) {
384 /*
385 * The copper PHY requires 82598 attach type to be XAUI
386 * for 10G and BX for 1G
387 */
388 hw->mac.link_attach_type =
389 (IXGBE_AUTOC_10G_XAUI | IXGBE_AUTOC_1G_BX);
390
391 /* Synchronize the MAC speed to the PHY speed */
392 status = hw->phy.ops.setup_speed(hw, phy_speed, false,
393 false);
394 if (status == 0)
395 hw->phy.ops.check(hw, speed, link_up);
396 else
397 status = IXGBE_ERR_LINK_SETUP;
398 }
399 } else {
400 *link_up = phy_link;
401 }
402
403 return status;
404}
405
406/**
407 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
408 * @hw: pointer to hardware structure
409 * @speed: new link speed
410 * @autoneg: true if autonegotiation enabled
411 * @autoneg_wait_to_complete: true if waiting is needed to complete
412 *
413 * Sets the link speed in the AUTOC register in the MAC and restarts link.
414 **/
415static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw, u32 speed,
416 bool autoneg,
417 bool autoneg_wait_to_complete)
418{
419 s32 status;
420 bool link_up = 0;
421
422 /* Setup the PHY according to input speed */
423 status = hw->phy.ops.setup_speed(hw, speed, autoneg,
424 autoneg_wait_to_complete);
425
426 /* Synchronize MAC to PHY speed */
427 if (status == 0)
428 status = hw->phy.ops.check(hw, &speed, &link_up);
429
430 return status;
431}
432
433/**
434 * ixgbe_reset_hw_82598 - Performs hardware reset
435 * @hw: pointer to hardware structure
436 *
437 * Resets the hardware by reseting the transmit and receive units, masks and
438 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
439 * reset.
440 **/
441static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
442{
443 s32 status = 0;
444 u32 ctrl;
445 u32 gheccr;
446 u32 i;
447 u32 autoc;
448 u8 analog_val;
449
450 /* Call adapter stop to disable tx/rx and clear interrupts */
451 ixgbe_stop_adapter(hw);
452
453 /*
454 * Power up the Atlas TX lanes if they are currently powered down.
455 * Atlas TX lanes are powered down for MAC loopback tests, but
456 * they are not automatically restored on reset.
457 */
458 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
459 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
460 /* Enable TX Atlas so packets can be transmitted again */
461 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
462 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
463 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, analog_val);
464
465 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &analog_val);
466 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
467 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, analog_val);
468
469 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &analog_val);
470 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
471 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, analog_val);
472
473 ixgbe_read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &analog_val);
474 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
475 ixgbe_write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, analog_val);
476 }
477
478 /* Reset PHY */
479 ixgbe_reset_phy(hw);
480
481 /*
482 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
483 * access and verify no pending requests before reset
484 */
485 if (ixgbe_disable_pcie_master(hw) != 0) {
486 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
487 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
488 }
489
490 /*
491 * Issue global reset to the MAC. This needs to be a SW reset.
492 * If link reset is used, it might reset the MAC when mng is using it
493 */
494 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
495 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
496 IXGBE_WRITE_FLUSH(hw);
497
498 /* Poll for reset bit to self-clear indicating reset is complete */
499 for (i = 0; i < 10; i++) {
500 udelay(1);
501 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
502 if (!(ctrl & IXGBE_CTRL_RST))
503 break;
504 }
505 if (ctrl & IXGBE_CTRL_RST) {
506 status = IXGBE_ERR_RESET_FAILED;
507 hw_dbg(hw, "Reset polling failed to complete.\n");
508 }
509
510 msleep(50);
511
512 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
513 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
514 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
515
516 /*
517 * AUTOC register which stores link settings gets cleared
518 * and reloaded from EEPROM after reset. We need to restore
519 * our stored value from init in case SW changed the attach
520 * type or speed. If this is the first time and link settings
521 * have not been stored, store default settings from AUTOC.
522 */
523 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
524 if (hw->mac.link_settings_loaded) {
525 autoc &= ~(IXGBE_AUTOC_LMS_ATTACH_TYPE);
526 autoc &= ~(IXGBE_AUTOC_LMS_MASK);
527 autoc |= hw->mac.link_attach_type;
528 autoc |= hw->mac.link_mode_select;
529 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
530 } else {
531 hw->mac.link_attach_type =
532 (autoc & IXGBE_AUTOC_LMS_ATTACH_TYPE);
533 hw->mac.link_mode_select = (autoc & IXGBE_AUTOC_LMS_MASK);
534 hw->mac.link_settings_loaded = true;
535 }
536
537 /* Store the permanent mac address */
538 ixgbe_get_mac_addr(hw, hw->mac.perm_addr);
539
540 return status;
541}
542
543static struct ixgbe_mac_operations mac_ops_82598 = {
544 .reset = &ixgbe_reset_hw_82598,
545 .get_media_type = &ixgbe_get_media_type_82598,
546};
547
548static struct ixgbe_phy_operations phy_ops_82598EB = {
549 .setup = &ixgbe_setup_copper_link_82598,
550 .check = &ixgbe_check_copper_link_82598,
551 .setup_speed = &ixgbe_setup_copper_link_speed_82598,
552 .get_settings = &ixgbe_get_copper_link_settings_82598,
553};
554
555struct ixgbe_info ixgbe_82598EB_info = {
556 .mac = ixgbe_mac_82598EB,
557 .get_invariants = &ixgbe_get_invariants_82598,
558 .mac_ops = &mac_ops_82598,
559 .phy_ops = &phy_ops_82598EB,
560};
561
562static struct ixgbe_phy_operations phy_ops_82598AT = {
563 .setup = &ixgbe_setup_tnx_phy_link,
564 .check = &ixgbe_check_tnx_phy_link,
565 .setup_speed = &ixgbe_setup_tnx_phy_link_speed,
566 .get_settings = &ixgbe_get_copper_link_settings_82598,
567};
568
569struct ixgbe_info ixgbe_82598AT_info = {
570 .mac = ixgbe_mac_82598EB,
571 .get_invariants = &ixgbe_get_invariants_82598,
572 .mac_ops = &mac_ops_82598,
573 .phy_ops = &phy_ops_82598AT,
574};
575
576static struct ixgbe_phy_operations phy_ops_82598AF = {
577 .setup = &ixgbe_setup_mac_link_82598,
578 .check = &ixgbe_check_mac_link_82598,
579 .setup_speed = &ixgbe_setup_mac_link_speed_82598,
580 .get_settings = &ixgbe_get_link_settings_82598,
581};
582
583struct ixgbe_info ixgbe_82598AF_info = {
584 .mac = ixgbe_mac_82598EB,
585 .get_invariants = &ixgbe_get_invariants_82598,
586 .mac_ops = &mac_ops_82598,
587 .phy_ops = &phy_ops_82598AF,
588};
589
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c
new file mode 100644
index 000000000000..512e3b22ed08
--- /dev/null
+++ b/drivers/net/ixgbe/ixgbe_common.c
@@ -0,0 +1,1175 @@
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
33#include "ixgbe_common.h"
34#include "ixgbe_phy.h"
35
36static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw);
37
38static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
41static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
42
43static s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
44static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
45static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
46static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr);
47
48/**
49 * ixgbe_start_hw - Prepare hardware for TX/RX
50 * @hw: pointer to hardware structure
51 *
52 * Starts the hardware by filling the bus info structure and media type, clears
53 * all on chip counters, initializes receive address registers, multicast
54 * table, VLAN filter table, calls routine to set up link and flow control
55 * settings, and leaves transmit and receive units disabled and uninitialized
56 **/
57s32 ixgbe_start_hw(struct ixgbe_hw *hw)
58{
59 u32 ctrl_ext;
60
61 /* Set the media type */
62 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
63
64 /* Identify the PHY */
65 ixgbe_identify_phy(hw);
66
67 /*
68 * Store MAC address from RAR0, clear receive address registers, and
69 * clear the multicast table
70 */
71 ixgbe_init_rx_addrs(hw);
72
73 /* Clear the VLAN filter table */
74 ixgbe_clear_vfta(hw);
75
76 /* Set up link */
77 hw->phy.ops.setup(hw);
78
79 /* Clear statistics registers */
80 ixgbe_clear_hw_cntrs(hw);
81
82 /* Set No Snoop Disable */
83 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
84 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
85 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
86
87 /* Clear adapter stopped flag */
88 hw->adapter_stopped = false;
89
90 return 0;
91}
92
93/**
94 * ixgbe_init_hw - Generic hardware initialization
95 * @hw: pointer to hardware structure
96 *
97 * Initialize the hardware by reseting the hardware, filling the bus info
98 * structure and media type, clears all on chip counters, initializes receive
99 * address registers, multicast table, VLAN filter table, calls routine to set
100 * up link and flow control settings, and leaves transmit and receive units
101 * disabled and uninitialized
102 **/
103s32 ixgbe_init_hw(struct ixgbe_hw *hw)
104{
105 /* Reset the hardware */
106 hw->mac.ops.reset(hw);
107
108 /* Start the HW */
109 ixgbe_start_hw(hw);
110
111 return 0;
112}
113
114/**
115 * ixgbe_clear_hw_cntrs - Generic clear hardware counters
116 * @hw: pointer to hardware structure
117 *
118 * Clears all hardware statistics counters by reading them from the hardware
119 * Statistics counters are clear on read.
120 **/
121static s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
122{
123 u16 i = 0;
124
125 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
126 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
127 IXGBE_READ_REG(hw, IXGBE_ERRBC);
128 IXGBE_READ_REG(hw, IXGBE_MSPDC);
129 for (i = 0; i < 8; i++)
130 IXGBE_READ_REG(hw, IXGBE_MPC(i));
131
132 IXGBE_READ_REG(hw, IXGBE_MLFC);
133 IXGBE_READ_REG(hw, IXGBE_MRFC);
134 IXGBE_READ_REG(hw, IXGBE_RLEC);
135 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
136 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
137 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
138 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
139
140 for (i = 0; i < 8; i++) {
141 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
142 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
143 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
144 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
145 }
146
147 IXGBE_READ_REG(hw, IXGBE_PRC64);
148 IXGBE_READ_REG(hw, IXGBE_PRC127);
149 IXGBE_READ_REG(hw, IXGBE_PRC255);
150 IXGBE_READ_REG(hw, IXGBE_PRC511);
151 IXGBE_READ_REG(hw, IXGBE_PRC1023);
152 IXGBE_READ_REG(hw, IXGBE_PRC1522);
153 IXGBE_READ_REG(hw, IXGBE_GPRC);
154 IXGBE_READ_REG(hw, IXGBE_BPRC);
155 IXGBE_READ_REG(hw, IXGBE_MPRC);
156 IXGBE_READ_REG(hw, IXGBE_GPTC);
157 IXGBE_READ_REG(hw, IXGBE_GORCL);
158 IXGBE_READ_REG(hw, IXGBE_GORCH);
159 IXGBE_READ_REG(hw, IXGBE_GOTCL);
160 IXGBE_READ_REG(hw, IXGBE_GOTCH);
161 for (i = 0; i < 8; i++)
162 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
163 IXGBE_READ_REG(hw, IXGBE_RUC);
164 IXGBE_READ_REG(hw, IXGBE_RFC);
165 IXGBE_READ_REG(hw, IXGBE_ROC);
166 IXGBE_READ_REG(hw, IXGBE_RJC);
167 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
168 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
169 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
170 IXGBE_READ_REG(hw, IXGBE_TORL);
171 IXGBE_READ_REG(hw, IXGBE_TORH);
172 IXGBE_READ_REG(hw, IXGBE_TPR);
173 IXGBE_READ_REG(hw, IXGBE_TPT);
174 IXGBE_READ_REG(hw, IXGBE_PTC64);
175 IXGBE_READ_REG(hw, IXGBE_PTC127);
176 IXGBE_READ_REG(hw, IXGBE_PTC255);
177 IXGBE_READ_REG(hw, IXGBE_PTC511);
178 IXGBE_READ_REG(hw, IXGBE_PTC1023);
179 IXGBE_READ_REG(hw, IXGBE_PTC1522);
180 IXGBE_READ_REG(hw, IXGBE_MPTC);
181 IXGBE_READ_REG(hw, IXGBE_BPTC);
182 for (i = 0; i < 16; i++) {
183 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
184 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
185 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
186 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
187 }
188
189 return 0;
190}
191
192/**
193 * ixgbe_get_mac_addr - Generic get MAC address
194 * @hw: pointer to hardware structure
195 * @mac_addr: Adapter MAC address
196 *
197 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
198 * A reset of the adapter must be performed prior to calling this function
199 * in order for the MAC address to have been loaded from the EEPROM into RAR0
200 **/
201s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
202{
203 u32 rar_high;
204 u32 rar_low;
205 u16 i;
206
207 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
208 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
209
210 for (i = 0; i < 4; i++)
211 mac_addr[i] = (u8)(rar_low >> (i*8));
212
213 for (i = 0; i < 2; i++)
214 mac_addr[i+4] = (u8)(rar_high >> (i*8));
215
216 return 0;
217}
218
219s32 ixgbe_read_part_num(struct ixgbe_hw *hw, u32 *part_num)
220{
221 s32 ret_val;
222 u16 data;
223
224 ret_val = ixgbe_read_eeprom(hw, IXGBE_PBANUM0_PTR, &data);
225 if (ret_val) {
226 hw_dbg(hw, "NVM Read Error\n");
227 return ret_val;
228 }
229 *part_num = (u32)(data << 16);
230
231 ret_val = ixgbe_read_eeprom(hw, IXGBE_PBANUM1_PTR, &data);
232 if (ret_val) {
233 hw_dbg(hw, "NVM Read Error\n");
234 return ret_val;
235 }
236 *part_num |= data;
237
238 return 0;
239}
240
241/**
242 * ixgbe_stop_adapter - Generic stop TX/RX units
243 * @hw: pointer to hardware structure
244 *
245 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
246 * disables transmit and receive units. The adapter_stopped flag is used by
247 * the shared code and drivers to determine if the adapter is in a stopped
248 * state and should not touch the hardware.
249 **/
250s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
251{
252 u32 number_of_queues;
253 u32 reg_val;
254 u16 i;
255
256 /*
257 * Set the adapter_stopped flag so other driver functions stop touching
258 * the hardware
259 */
260 hw->adapter_stopped = true;
261
262 /* Disable the receive unit */
263 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
264 reg_val &= ~(IXGBE_RXCTRL_RXEN);
265 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
266 msleep(2);
267
268 /* Clear interrupt mask to stop from interrupts being generated */
269 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
270
271 /* Clear any pending interrupts */
272 IXGBE_READ_REG(hw, IXGBE_EICR);
273
274 /* Disable the transmit unit. Each queue must be disabled. */
275 number_of_queues = hw->mac.num_tx_queues;
276 for (i = 0; i < number_of_queues; i++) {
277 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
278 if (reg_val & IXGBE_TXDCTL_ENABLE) {
279 reg_val &= ~IXGBE_TXDCTL_ENABLE;
280 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
281 }
282 }
283
284 return 0;
285}
286
287/**
288 * ixgbe_led_on - Turns on the software controllable LEDs.
289 * @hw: pointer to hardware structure
290 * @index: led number to turn on
291 **/
292s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
293{
294 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
295
296 /* To turn on the LED, set mode to ON. */
297 led_reg &= ~IXGBE_LED_MODE_MASK(index);
298 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
299 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
300
301 return 0;
302}
303
304/**
305 * ixgbe_led_off - Turns off the software controllable LEDs.
306 * @hw: pointer to hardware structure
307 * @index: led number to turn off
308 **/
309s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
310{
311 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
312
313 /* To turn off the LED, set mode to OFF. */
314 led_reg &= ~IXGBE_LED_MODE_MASK(index);
315 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
316 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
317
318 return 0;
319}
320
321
322/**
323 * ixgbe_init_eeprom - Initialize EEPROM params
324 * @hw: pointer to hardware structure
325 *
326 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
327 * ixgbe_hw struct in order to set up EEPROM access.
328 **/
329s32 ixgbe_init_eeprom(struct ixgbe_hw *hw)
330{
331 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
332 u32 eec;
333 u16 eeprom_size;
334
335 if (eeprom->type == ixgbe_eeprom_uninitialized) {
336 eeprom->type = ixgbe_eeprom_none;
337
338 /*
339 * Check for EEPROM present first.
340 * If not present leave as none
341 */
342 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
343 if (eec & IXGBE_EEC_PRES) {
344 eeprom->type = ixgbe_eeprom_spi;
345
346 /*
347 * SPI EEPROM is assumed here. This code would need to
348 * change if a future EEPROM is not SPI.
349 */
350 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
351 IXGBE_EEC_SIZE_SHIFT);
352 eeprom->word_size = 1 << (eeprom_size +
353 IXGBE_EEPROM_WORD_SIZE_SHIFT);
354 }
355
356 if (eec & IXGBE_EEC_ADDR_SIZE)
357 eeprom->address_bits = 16;
358 else
359 eeprom->address_bits = 8;
360 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
361 "%d\n", eeprom->type, eeprom->word_size,
362 eeprom->address_bits);
363 }
364
365 return 0;
366}
367
368/**
369 * ixgbe_read_eeprom - Read EEPROM word using EERD
370 * @hw: pointer to hardware structure
371 * @offset: offset of word in the EEPROM to read
372 * @data: word read from the EEPROM
373 *
374 * Reads a 16 bit word from the EEPROM using the EERD register.
375 **/
376s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
377{
378 u32 eerd;
379 s32 status;
380
381 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
382 IXGBE_EEPROM_READ_REG_START;
383
384 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
385 status = ixgbe_poll_eeprom_eerd_done(hw);
386
387 if (status == 0)
388 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
389 IXGBE_EEPROM_READ_REG_DATA);
390 else
391 hw_dbg(hw, "Eeprom read timed out\n");
392
393 return status;
394}
395
396/**
397 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
398 * @hw: pointer to hardware structure
399 *
400 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
401 **/
402static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
403{
404 u32 i;
405 u32 reg;
406 s32 status = IXGBE_ERR_EEPROM;
407
408 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
409 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
410 if (reg & IXGBE_EEPROM_READ_REG_DONE) {
411 status = 0;
412 break;
413 }
414 udelay(5);
415 }
416 return status;
417}
418
419/**
420 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
421 * @hw: pointer to hardware structure
422 *
423 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
424 **/
425static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
426{
427 s32 status = IXGBE_ERR_EEPROM;
428 u32 timeout;
429 u32 i;
430 u32 swsm;
431
432 /* Set timeout value based on size of EEPROM */
433 timeout = hw->eeprom.word_size + 1;
434
435 /* Get SMBI software semaphore between device drivers first */
436 for (i = 0; i < timeout; i++) {
437 /*
438 * If the SMBI bit is 0 when we read it, then the bit will be
439 * set and we have the semaphore
440 */
441 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
442 if (!(swsm & IXGBE_SWSM_SMBI)) {
443 status = 0;
444 break;
445 }
446 msleep(1);
447 }
448
449 /* Now get the semaphore between SW/FW through the SWESMBI bit */
450 if (status == 0) {
451 for (i = 0; i < timeout; i++) {
452 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
453
454 /* Set the SW EEPROM semaphore bit to request access */
455 swsm |= IXGBE_SWSM_SWESMBI;
456 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
457
458 /*
459 * If we set the bit successfully then we got the
460 * semaphore.
461 */
462 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
463 if (swsm & IXGBE_SWSM_SWESMBI)
464 break;
465
466 udelay(50);
467 }
468
469 /*
470 * Release semaphores and return error if SW EEPROM semaphore
471 * was not granted because we don't have access to the EEPROM
472 */
473 if (i >= timeout) {
474 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
475 "not granted.\n");
476 ixgbe_release_eeprom_semaphore(hw);
477 status = IXGBE_ERR_EEPROM;
478 }
479 }
480
481 return status;
482}
483
484/**
485 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
486 * @hw: pointer to hardware structure
487 *
488 * This function clears hardware semaphore bits.
489 **/
490static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
491{
492 u32 swsm;
493
494 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
495
496 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
497 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
498 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
499}
500
501/**
502 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
503 * @hw: pointer to hardware structure
504 **/
505static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
506{
507 u16 i;
508 u16 j;
509 u16 checksum = 0;
510 u16 length = 0;
511 u16 pointer = 0;
512 u16 word = 0;
513
514 /* Include 0x0-0x3F in the checksum */
515 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
516 if (ixgbe_read_eeprom(hw, i, &word) != 0) {
517 hw_dbg(hw, "EEPROM read failed\n");
518 break;
519 }
520 checksum += word;
521 }
522
523 /* Include all data from pointers except for the fw pointer */
524 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
525 ixgbe_read_eeprom(hw, i, &pointer);
526
527 /* Make sure the pointer seems valid */
528 if (pointer != 0xFFFF && pointer != 0) {
529 ixgbe_read_eeprom(hw, pointer, &length);
530
531 if (length != 0xFFFF && length != 0) {
532 for (j = pointer+1; j <= pointer+length; j++) {
533 ixgbe_read_eeprom(hw, j, &word);
534 checksum += word;
535 }
536 }
537 }
538 }
539
540 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
541
542 return checksum;
543}
544
545/**
546 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
547 * @hw: pointer to hardware structure
548 * @checksum_val: calculated checksum
549 *
550 * Performs checksum calculation and validates the EEPROM checksum. If the
551 * caller does not need checksum_val, the value can be NULL.
552 **/
553s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
554{
555 s32 status;
556 u16 checksum;
557 u16 read_checksum = 0;
558
559 /*
560 * Read the first word from the EEPROM. If this times out or fails, do
561 * not continue or we could be in for a very long wait while every
562 * EEPROM read fails
563 */
564 status = ixgbe_read_eeprom(hw, 0, &checksum);
565
566 if (status == 0) {
567 checksum = ixgbe_calc_eeprom_checksum(hw);
568
569 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
570
571 /*
572 * Verify read checksum from EEPROM is the same as
573 * calculated checksum
574 */
575 if (read_checksum != checksum)
576 status = IXGBE_ERR_EEPROM_CHECKSUM;
577
578 /* If the user cares, return the calculated checksum */
579 if (checksum_val)
580 *checksum_val = checksum;
581 } else {
582 hw_dbg(hw, "EEPROM read failed\n");
583 }
584
585 return status;
586}
587
588/**
589 * ixgbe_validate_mac_addr - Validate MAC address
590 * @mac_addr: pointer to MAC address.
591 *
592 * Tests a MAC address to ensure it is a valid Individual Address
593 **/
594s32 ixgbe_validate_mac_addr(u8 *mac_addr)
595{
596 s32 status = 0;
597
598 /* Make sure it is not a multicast address */
599 if (IXGBE_IS_MULTICAST(mac_addr))
600 status = IXGBE_ERR_INVALID_MAC_ADDR;
601 /* Not a broadcast address */
602 else if (IXGBE_IS_BROADCAST(mac_addr))
603 status = IXGBE_ERR_INVALID_MAC_ADDR;
604 /* Reject the zero address */
605 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
606 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
607 status = IXGBE_ERR_INVALID_MAC_ADDR;
608
609 return status;
610}
611
612/**
613 * ixgbe_set_rar - Set RX address register
614 * @hw: pointer to hardware structure
615 * @addr: Address to put into receive address register
616 * @index: Receive address register to write
617 * @vind: Vind to set RAR to
618 * @enable_addr: set flag that address is active
619 *
620 * Puts an ethernet address into a receive address register.
621 **/
622s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vind,
623 u32 enable_addr)
624{
625 u32 rar_low, rar_high;
626
627 /*
628 * HW expects these in little endian so we reverse the byte order from
629 * network order (big endian) to little endian
630 */
631 rar_low = ((u32)addr[0] |
632 ((u32)addr[1] << 8) |
633 ((u32)addr[2] << 16) |
634 ((u32)addr[3] << 24));
635
636 rar_high = ((u32)addr[4] |
637 ((u32)addr[5] << 8) |
638 ((vind << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK));
639
640 if (enable_addr != 0)
641 rar_high |= IXGBE_RAH_AV;
642
643 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
644 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
645
646 return 0;
647}
648
649/**
650 * ixgbe_init_rx_addrs - Initializes receive address filters.
651 * @hw: pointer to hardware structure
652 *
653 * Places the MAC address in receive address register 0 and clears the rest
654 * of the receive addresss registers. Clears the multicast table. Assumes
655 * the receiver is in reset when the routine is called.
656 **/
657static s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
658{
659 u32 i;
660 u32 rar_entries = hw->mac.num_rx_addrs;
661
662 /*
663 * If the current mac address is valid, assume it is a software override
664 * to the permanent address.
665 * Otherwise, use the permanent address from the eeprom.
666 */
667 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
668 IXGBE_ERR_INVALID_MAC_ADDR) {
669 /* Get the MAC address from the RAR0 for later reference */
670 ixgbe_get_mac_addr(hw, hw->mac.addr);
671
672 hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
673 hw->mac.addr[0], hw->mac.addr[1],
674 hw->mac.addr[2]);
675 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
676 hw->mac.addr[4], hw->mac.addr[5]);
677 } else {
678 /* Setup the receive address. */
679 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
680 hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ",
681 hw->mac.addr[0], hw->mac.addr[1],
682 hw->mac.addr[2]);
683 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
684 hw->mac.addr[4], hw->mac.addr[5]);
685
686 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
687 }
688
689 hw->addr_ctrl.rar_used_count = 1;
690
691 /* Zero out the other receive addresses. */
692 hw_dbg(hw, "Clearing RAR[1-15]\n");
693 for (i = 1; i < rar_entries; i++) {
694 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
695 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
696 }
697
698 /* Clear the MTA */
699 hw->addr_ctrl.mc_addr_in_rar_count = 0;
700 hw->addr_ctrl.mta_in_use = 0;
701 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
702
703 hw_dbg(hw, " Clearing MTA\n");
704 for (i = 0; i < IXGBE_MC_TBL_SIZE; i++)
705 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
706
707 return 0;
708}
709
710/**
711 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
712 * @hw: pointer to hardware structure
713 * @mc_addr: the multicast address
714 *
715 * Extracts the 12 bits, from a multicast address, to determine which
716 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
717 * incoming rx multicast addresses, to determine the bit-vector to check in
718 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
719 * by the MO field of the MCSTCTRL. The MO field is set during initalization
720 * to mc_filter_type.
721 **/
722static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
723{
724 u32 vector = 0;
725
726 switch (hw->mac.mc_filter_type) {
727 case 0: /* use bits [47:36] of the address */
728 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
729 break;
730 case 1: /* use bits [46:35] of the address */
731 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
732 break;
733 case 2: /* use bits [45:34] of the address */
734 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
735 break;
736 case 3: /* use bits [43:32] of the address */
737 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
738 break;
739 default: /* Invalid mc_filter_type */
740 hw_dbg(hw, "MC filter type param set incorrectly\n");
741 break;
742 }
743
744 /* vector can only be 12-bits or boundary will be exceeded */
745 vector &= 0xFFF;
746 return vector;
747}
748
749/**
750 * ixgbe_set_mta - Set bit-vector in multicast table
751 * @hw: pointer to hardware structure
752 * @hash_value: Multicast address hash value
753 *
754 * Sets the bit-vector in the multicast table.
755 **/
756static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
757{
758 u32 vector;
759 u32 vector_bit;
760 u32 vector_reg;
761 u32 mta_reg;
762
763 hw->addr_ctrl.mta_in_use++;
764
765 vector = ixgbe_mta_vector(hw, mc_addr);
766 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
767
768 /*
769 * The MTA is a register array of 128 32-bit registers. It is treated
770 * like an array of 4096 bits. We want to set bit
771 * BitArray[vector_value]. So we figure out what register the bit is
772 * in, read it, OR in the new bit, then write back the new value. The
773 * register is determined by the upper 7 bits of the vector value and
774 * the bit within that register are determined by the lower 5 bits of
775 * the value.
776 */
777 vector_reg = (vector >> 5) & 0x7F;
778 vector_bit = vector & 0x1F;
779 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
780 mta_reg |= (1 << vector_bit);
781 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
782}
783
784/**
785 * ixgbe_add_mc_addr - Adds a multicast address.
786 * @hw: pointer to hardware structure
787 * @mc_addr: new multicast address
788 *
789 * Adds it to unused receive address register or to the multicast table.
790 **/
791static void ixgbe_add_mc_addr(struct ixgbe_hw *hw, u8 *mc_addr)
792{
793 u32 rar_entries = hw->mac.num_rx_addrs;
794
795 hw_dbg(hw, " MC Addr =%.2X %.2X %.2X %.2X %.2X %.2X\n",
796 mc_addr[0], mc_addr[1], mc_addr[2],
797 mc_addr[3], mc_addr[4], mc_addr[5]);
798
799 /*
800 * Place this multicast address in the RAR if there is room,
801 * else put it in the MTA
802 */
803 if (hw->addr_ctrl.rar_used_count < rar_entries) {
804 ixgbe_set_rar(hw, hw->addr_ctrl.rar_used_count,
805 mc_addr, 0, IXGBE_RAH_AV);
806 hw_dbg(hw, "Added a multicast address to RAR[%d]\n",
807 hw->addr_ctrl.rar_used_count);
808 hw->addr_ctrl.rar_used_count++;
809 hw->addr_ctrl.mc_addr_in_rar_count++;
810 } else {
811 ixgbe_set_mta(hw, mc_addr);
812 }
813
814 hw_dbg(hw, "ixgbe_add_mc_addr Complete\n");
815}
816
817/**
818 * ixgbe_update_mc_addr_list - Updates MAC list of multicast addresses
819 * @hw: pointer to hardware structure
820 * @mc_addr_list: the list of new multicast addresses
821 * @mc_addr_count: number of addresses
822 * @pad: number of bytes between addresses in the list
823 *
824 * The given list replaces any existing list. Clears the MC addrs from receive
825 * address registers and the multicast table. Uses unsed receive address
826 * registers for the first multicast addresses, and hashes the rest into the
827 * multicast table.
828 **/
829s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
830 u32 mc_addr_count, u32 pad)
831{
832 u32 i;
833 u32 rar_entries = hw->mac.num_rx_addrs;
834
835 /*
836 * Set the new number of MC addresses that we are being requested to
837 * use.
838 */
839 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
840 hw->addr_ctrl.rar_used_count -= hw->addr_ctrl.mc_addr_in_rar_count;
841 hw->addr_ctrl.mc_addr_in_rar_count = 0;
842 hw->addr_ctrl.mta_in_use = 0;
843
844 /* Zero out the other receive addresses. */
845 hw_dbg(hw, "Clearing RAR[1-15]\n");
846 for (i = hw->addr_ctrl.rar_used_count; i < rar_entries; i++) {
847 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
848 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
849 }
850
851 /* Clear the MTA */
852 hw_dbg(hw, " Clearing MTA\n");
853 for (i = 0; i < IXGBE_MC_TBL_SIZE; i++)
854 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
855
856 /* Add the new addresses */
857 for (i = 0; i < mc_addr_count; i++) {
858 hw_dbg(hw, " Adding the multicast addresses:\n");
859 ixgbe_add_mc_addr(hw, mc_addr_list +
860 (i * (IXGBE_ETH_LENGTH_OF_ADDRESS + pad)));
861 }
862
863 /* Enable mta */
864 if (hw->addr_ctrl.mta_in_use > 0)
865 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
866 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
867
868 hw_dbg(hw, "ixgbe_update_mc_addr_list Complete\n");
869 return 0;
870}
871
872/**
873 * ixgbe_clear_vfta - Clear VLAN filter table
874 * @hw: pointer to hardware structure
875 *
876 * Clears the VLAN filer table, and the VMDq index associated with the filter
877 **/
878static s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
879{
880 u32 offset;
881 u32 vlanbyte;
882
883 for (offset = 0; offset < IXGBE_VLAN_FILTER_TBL_SIZE; offset++)
884 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
885
886 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
887 for (offset = 0; offset < IXGBE_VLAN_FILTER_TBL_SIZE; offset++)
888 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
889 0);
890
891 return 0;
892}
893
894/**
895 * ixgbe_set_vfta - Set VLAN filter table
896 * @hw: pointer to hardware structure
897 * @vlan: VLAN id to write to VLAN filter
898 * @vind: VMDq output index that maps queue to VLAN id in VFTA
899 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
900 *
901 * Turn on/off specified VLAN in the VLAN filter table.
902 **/
903s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind,
904 bool vlan_on)
905{
906 u32 VftaIndex;
907 u32 BitOffset;
908 u32 VftaReg;
909 u32 VftaByte;
910
911 /* Determine 32-bit word position in array */
912 VftaIndex = (vlan >> 5) & 0x7F; /* upper seven bits */
913
914 /* Determine the location of the (VMD) queue index */
915 VftaByte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
916 BitOffset = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
917
918 /* Set the nibble for VMD queue index */
919 VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex));
920 VftaReg &= (~(0x0F << BitOffset));
921 VftaReg |= (vind << BitOffset);
922 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(VftaByte, VftaIndex), VftaReg);
923
924 /* Determine the location of the bit for this VLAN id */
925 BitOffset = vlan & 0x1F; /* lower five bits */
926
927 VftaReg = IXGBE_READ_REG(hw, IXGBE_VFTA(VftaIndex));
928 if (vlan_on)
929 /* Turn on this VLAN id */
930 VftaReg |= (1 << BitOffset);
931 else
932 /* Turn off this VLAN id */
933 VftaReg &= ~(1 << BitOffset);
934 IXGBE_WRITE_REG(hw, IXGBE_VFTA(VftaIndex), VftaReg);
935
936 return 0;
937}
938
939/**
940 * ixgbe_setup_fc - Configure flow control settings
941 * @hw: pointer to hardware structure
942 * @packetbuf_num: packet buffer number (0-7)
943 *
944 * Configures the flow control settings based on SW configuration.
945 * This function is used for 802.3x flow control configuration only.
946 **/
947s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
948{
949 u32 frctl_reg;
950 u32 rmcs_reg;
951
952 if (packetbuf_num < 0 || packetbuf_num > 7)
953 hw_dbg(hw, "Invalid packet buffer number [%d], expected range"
954 "is 0-7\n", packetbuf_num);
955
956 frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
957 frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
958
959 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
960 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
961
962 /*
963 * We want to save off the original Flow Control configuration just in
964 * case we get disconnected and then reconnected into a different hub
965 * or switch with different Flow Control capabilities.
966 */
967 hw->fc.type = hw->fc.original_type;
968
969 /*
970 * The possible values of the "flow_control" parameter are:
971 * 0: Flow control is completely disabled
972 * 1: Rx flow control is enabled (we can receive pause frames but not
973 * send pause frames).
974 * 2: Tx flow control is enabled (we can send pause frames but we do not
975 * support receiving pause frames)
976 * 3: Both Rx and TX flow control (symmetric) are enabled.
977 * other: Invalid.
978 */
979 switch (hw->fc.type) {
980 case ixgbe_fc_none:
981 break;
982 case ixgbe_fc_rx_pause:
983 /*
984 * RX Flow control is enabled,
985 * and TX Flow control is disabled.
986 */
987 frctl_reg |= IXGBE_FCTRL_RFCE;
988 break;
989 case ixgbe_fc_tx_pause:
990 /*
991 * TX Flow control is enabled, and RX Flow control is disabled,
992 * by a software over-ride.
993 */
994 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
995 break;
996 case ixgbe_fc_full:
997 /*
998 * Flow control (both RX and TX) is enabled by a software
999 * over-ride.
1000 */
1001 frctl_reg |= IXGBE_FCTRL_RFCE;
1002 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
1003 break;
1004 default:
1005 /* We should never get here. The value should be 0-3. */
1006 hw_dbg(hw, "Flow control param set incorrectly\n");
1007 break;
1008 }
1009
1010 /* Enable 802.3x based flow control settings. */
1011 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg);
1012 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
1013
1014 /*
1015 * We need to set up the Receive Threshold high and low water
1016 * marks as well as (optionally) enabling the transmission of
1017 * XON frames.
1018 */
1019 if (hw->fc.type & ixgbe_fc_tx_pause) {
1020 if (hw->fc.send_xon) {
1021 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
1022 (hw->fc.low_water | IXGBE_FCRTL_XONE));
1023 } else {
1024 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
1025 hw->fc.low_water);
1026 }
1027 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
1028 (hw->fc.high_water)|IXGBE_FCRTH_FCEN);
1029 }
1030
1031 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time);
1032 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1033
1034 return 0;
1035}
1036
1037/**
1038 * ixgbe_disable_pcie_master - Disable PCI-express master access
1039 * @hw: pointer to hardware structure
1040 *
1041 * Disables PCI-Express master access and verifies there are no pending
1042 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1043 * bit hasn't caused the master requests to be disabled, else 0
1044 * is returned signifying master requests disabled.
1045 **/
1046s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
1047{
1048 u32 ctrl;
1049 s32 i;
1050 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
1051
1052 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1053 ctrl |= IXGBE_CTRL_GIO_DIS;
1054 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1055
1056 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
1057 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
1058 status = 0;
1059 break;
1060 }
1061 udelay(100);
1062 }
1063
1064 return status;
1065}
1066
1067
1068/**
1069 * ixgbe_acquire_swfw_sync - Aquire SWFW semaphore
1070 * @hw: pointer to hardware structure
1071 * @mask: Mask to specify wich semaphore to acquire
1072 *
1073 * Aquires the SWFW semaphore throught the GSSR register for the specified
1074 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1075 **/
1076s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1077{
1078 u32 gssr;
1079 u32 swmask = mask;
1080 u32 fwmask = mask << 5;
1081 s32 timeout = 200;
1082
1083 while (timeout) {
1084 if (ixgbe_get_eeprom_semaphore(hw))
1085 return -IXGBE_ERR_SWFW_SYNC;
1086
1087 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
1088 if (!(gssr & (fwmask | swmask)))
1089 break;
1090
1091 /*
1092 * Firmware currently using resource (fwmask) or other software
1093 * thread currently using resource (swmask)
1094 */
1095 ixgbe_release_eeprom_semaphore(hw);
1096 msleep(5);
1097 timeout--;
1098 }
1099
1100 if (!timeout) {
1101 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
1102 return -IXGBE_ERR_SWFW_SYNC;
1103 }
1104
1105 gssr |= swmask;
1106 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
1107
1108 ixgbe_release_eeprom_semaphore(hw);
1109 return 0;
1110}
1111
1112/**
1113 * ixgbe_release_swfw_sync - Release SWFW semaphore
1114 * @hw: pointer to hardware structure
1115 * @mask: Mask to specify wich semaphore to release
1116 *
1117 * Releases the SWFW semaphore throught the GSSR register for the specified
1118 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1119 **/
1120void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1121{
1122 u32 gssr;
1123 u32 swmask = mask;
1124
1125 ixgbe_get_eeprom_semaphore(hw);
1126
1127 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
1128 gssr &= ~swmask;
1129 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
1130
1131 ixgbe_release_eeprom_semaphore(hw);
1132}
1133
1134/**
1135 * ixgbe_read_analog_reg8- Reads 8 bit 82598 Atlas analog register
1136 * @hw: pointer to hardware structure
1137 * @reg: analog register to read
1138 * @val: read value
1139 *
1140 * Performs write operation to analog register specified.
1141 **/
1142s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
1143{
1144 u32 atlas_ctl;
1145
1146 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1147 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1148 IXGBE_WRITE_FLUSH(hw);
1149 udelay(10);
1150 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1151 *val = (u8)atlas_ctl;
1152
1153 return 0;
1154}
1155
1156/**
1157 * ixgbe_write_analog_reg8- Writes 8 bit Atlas analog register
1158 * @hw: pointer to hardware structure
1159 * @reg: atlas register to write
1160 * @val: value to write
1161 *
1162 * Performs write operation to Atlas analog register specified.
1163 **/
1164s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
1165{
1166 u32 atlas_ctl;
1167
1168 atlas_ctl = (reg << 8) | val;
1169 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1170 IXGBE_WRITE_FLUSH(hw);
1171 udelay(10);
1172
1173 return 0;
1174}
1175
diff --git a/drivers/net/ixgbe/ixgbe_common.h b/drivers/net/ixgbe/ixgbe_common.h
new file mode 100644
index 000000000000..de6ddd5d04ad
--- /dev/null
+++ b/drivers/net/ixgbe/ixgbe_common.h
@@ -0,0 +1,86 @@
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _IXGBE_COMMON_H_
30#define _IXGBE_COMMON_H_
31
32#include "ixgbe_type.h"
33
34s32 ixgbe_init_hw(struct ixgbe_hw *hw);
35s32 ixgbe_start_hw(struct ixgbe_hw *hw);
36s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr);
37s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
38s32 ixgbe_read_part_num(struct ixgbe_hw *hw, u32 *part_num);
39
40s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
41s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
42
43s32 ixgbe_init_eeprom(struct ixgbe_hw *hw);
44s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
45s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
46
47s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vind,
48 u32 enable_addr);
49s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
50 u32 mc_addr_count, u32 pad);
51s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on);
52s32 ixgbe_validate_mac_addr(u8 *mac_addr);
53
54s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packtetbuf_num);
55
56s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
57void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
58s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
59
60s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
61s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
62
63#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
64
65#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
66
67#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
68 writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
69
70#define IXGBE_READ_REG_ARRAY(a, reg, offset) (\
71 readl((a)->hw_addr + (reg) + ((offset) << 2)))
72
73#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
74
75#ifdef DEBUG
76#define hw_dbg(hw, format, arg...) \
77printk(KERN_DEBUG, "%s: " format, ixgbe_get_hw_dev_name(hw), ##arg);
78#else
79static inline int __attribute__ ((format (printf, 2, 3)))
80hw_dbg(struct ixgbe_hw *hw, const char *format, ...)
81{
82 return 0;
83}
84#endif
85
86#endif /* IXGBE_COMMON */
diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c
new file mode 100644
index 000000000000..43a2a46e2874
--- /dev/null
+++ b/drivers/net/ixgbe/ixgbe_ethtool.c
@@ -0,0 +1,943 @@
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* ethtool support for ixgbe */
30
31#include <linux/types.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/ethtool.h>
36#include <linux/vmalloc.h>
37#include <linux/uaccess.h>
38
39#include "ixgbe.h"
40
41
42#define IXGBE_ALL_RAR_ENTRIES 16
43
44struct ixgbe_stats {
45 char stat_string[ETH_GSTRING_LEN];
46 int sizeof_stat;
47 int stat_offset;
48};
49
50#define IXGBE_STAT(m) sizeof(((struct ixgbe_adapter *)0)->m), \
51 offsetof(struct ixgbe_adapter, m)
52static struct ixgbe_stats ixgbe_gstrings_stats[] = {
53 {"rx_packets", IXGBE_STAT(net_stats.rx_packets)},
54 {"tx_packets", IXGBE_STAT(net_stats.tx_packets)},
55 {"rx_bytes", IXGBE_STAT(net_stats.rx_bytes)},
56 {"tx_bytes", IXGBE_STAT(net_stats.tx_bytes)},
57 {"lsc_int", IXGBE_STAT(lsc_int)},
58 {"tx_busy", IXGBE_STAT(tx_busy)},
59 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
60 {"rx_errors", IXGBE_STAT(net_stats.rx_errors)},
61 {"tx_errors", IXGBE_STAT(net_stats.tx_errors)},
62 {"rx_dropped", IXGBE_STAT(net_stats.rx_dropped)},
63 {"tx_dropped", IXGBE_STAT(net_stats.tx_dropped)},
64 {"multicast", IXGBE_STAT(net_stats.multicast)},
65 {"broadcast", IXGBE_STAT(stats.bprc)},
66 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
67 {"collisions", IXGBE_STAT(net_stats.collisions)},
68 {"rx_over_errors", IXGBE_STAT(net_stats.rx_over_errors)},
69 {"rx_crc_errors", IXGBE_STAT(net_stats.rx_crc_errors)},
70 {"rx_frame_errors", IXGBE_STAT(net_stats.rx_frame_errors)},
71 {"rx_fifo_errors", IXGBE_STAT(net_stats.rx_fifo_errors)},
72 {"rx_missed_errors", IXGBE_STAT(net_stats.rx_missed_errors)},
73 {"tx_aborted_errors", IXGBE_STAT(net_stats.tx_aborted_errors)},
74 {"tx_carrier_errors", IXGBE_STAT(net_stats.tx_carrier_errors)},
75 {"tx_fifo_errors", IXGBE_STAT(net_stats.tx_fifo_errors)},
76 {"tx_heartbeat_errors", IXGBE_STAT(net_stats.tx_heartbeat_errors)},
77 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
78 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
79 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
80 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
81 {"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)},
82 {"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)},
83 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
84 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
85 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
86 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
87 {"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)},
88 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
89 {"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)},
90 {"rx_header_split", IXGBE_STAT(rx_hdr_split)},
91 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
92 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
93};
94
95#define IXGBE_QUEUE_STATS_LEN \
96 ((((struct ixgbe_adapter *)netdev->priv)->num_tx_queues + \
97 ((struct ixgbe_adapter *)netdev->priv)->num_rx_queues) * \
98 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
99#define IXGBE_GLOBAL_STATS_LEN \
100 sizeof(ixgbe_gstrings_stats) / sizeof(struct ixgbe_stats)
101#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + IXGBE_QUEUE_STATS_LEN)
102
103static int ixgbe_get_settings(struct net_device *netdev,
104 struct ethtool_cmd *ecmd)
105{
106 struct ixgbe_adapter *adapter = netdev_priv(netdev);
107
108 ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
109 ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
110 ecmd->port = PORT_FIBRE;
111 ecmd->transceiver = XCVR_EXTERNAL;
112
113 if (netif_carrier_ok(adapter->netdev)) {
114 ecmd->speed = SPEED_10000;
115 ecmd->duplex = DUPLEX_FULL;
116 } else {
117 ecmd->speed = -1;
118 ecmd->duplex = -1;
119 }
120
121 ecmd->autoneg = AUTONEG_DISABLE;
122 return 0;
123}
124
125static int ixgbe_set_settings(struct net_device *netdev,
126 struct ethtool_cmd *ecmd)
127{
128 struct ixgbe_adapter *adapter = netdev_priv(netdev);
129
130 if (ecmd->autoneg == AUTONEG_ENABLE ||
131 ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL)
132 return -EINVAL;
133
134 if (netif_running(adapter->netdev)) {
135 ixgbe_down(adapter);
136 ixgbe_reset(adapter);
137 ixgbe_up(adapter);
138 } else {
139 ixgbe_reset(adapter);
140 }
141
142 return 0;
143}
144
145static void ixgbe_get_pauseparam(struct net_device *netdev,
146 struct ethtool_pauseparam *pause)
147{
148 struct ixgbe_adapter *adapter = netdev_priv(netdev);
149 struct ixgbe_hw *hw = &adapter->hw;
150
151 pause->autoneg = AUTONEG_DISABLE;
152
153 if (hw->fc.type == ixgbe_fc_rx_pause) {
154 pause->rx_pause = 1;
155 } else if (hw->fc.type == ixgbe_fc_tx_pause) {
156 pause->tx_pause = 1;
157 } else if (hw->fc.type == ixgbe_fc_full) {
158 pause->rx_pause = 1;
159 pause->tx_pause = 1;
160 }
161}
162
163static int ixgbe_set_pauseparam(struct net_device *netdev,
164 struct ethtool_pauseparam *pause)
165{
166 struct ixgbe_adapter *adapter = netdev_priv(netdev);
167 struct ixgbe_hw *hw = &adapter->hw;
168
169 if (pause->autoneg == AUTONEG_ENABLE)
170 return -EINVAL;
171
172 if (pause->rx_pause && pause->tx_pause)
173 hw->fc.type = ixgbe_fc_full;
174 else if (pause->rx_pause && !pause->tx_pause)
175 hw->fc.type = ixgbe_fc_rx_pause;
176 else if (!pause->rx_pause && pause->tx_pause)
177 hw->fc.type = ixgbe_fc_tx_pause;
178 else if (!pause->rx_pause && !pause->tx_pause)
179 hw->fc.type = ixgbe_fc_none;
180
181 hw->fc.original_type = hw->fc.type;
182
183 if (netif_running(adapter->netdev)) {
184 ixgbe_down(adapter);
185 ixgbe_up(adapter);
186 } else {
187 ixgbe_reset(adapter);
188 }
189
190 return 0;
191}
192
193static u32 ixgbe_get_rx_csum(struct net_device *netdev)
194{
195 struct ixgbe_adapter *adapter = netdev_priv(netdev);
196 return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
197}
198
199static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
200{
201 struct ixgbe_adapter *adapter = netdev_priv(netdev);
202 if (data)
203 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
204 else
205 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
206
207 if (netif_running(netdev)) {
208 ixgbe_down(adapter);
209 ixgbe_up(adapter);
210 } else {
211 ixgbe_reset(adapter);
212 }
213
214 return 0;
215}
216
217static u32 ixgbe_get_tx_csum(struct net_device *netdev)
218{
219 return (netdev->features & NETIF_F_HW_CSUM) != 0;
220}
221
222static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
223{
224 if (data)
225 netdev->features |= NETIF_F_HW_CSUM;
226 else
227 netdev->features &= ~NETIF_F_HW_CSUM;
228
229 return 0;
230}
231
232static int ixgbe_set_tso(struct net_device *netdev, u32 data)
233{
234
235 if (data) {
236 netdev->features |= NETIF_F_TSO;
237 netdev->features |= NETIF_F_TSO6;
238 } else {
239 netdev->features &= ~NETIF_F_TSO;
240 netdev->features &= ~NETIF_F_TSO6;
241 }
242 return 0;
243}
244
245static u32 ixgbe_get_msglevel(struct net_device *netdev)
246{
247 struct ixgbe_adapter *adapter = netdev_priv(netdev);
248 return adapter->msg_enable;
249}
250
251static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
252{
253 struct ixgbe_adapter *adapter = netdev_priv(netdev);
254 adapter->msg_enable = data;
255}
256
257static int ixgbe_get_regs_len(struct net_device *netdev)
258{
259#define IXGBE_REGS_LEN 1128
260 return IXGBE_REGS_LEN * sizeof(u32);
261}
262
263#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
264
265static void ixgbe_get_regs(struct net_device *netdev,
266 struct ethtool_regs *regs, void *p)
267{
268 struct ixgbe_adapter *adapter = netdev_priv(netdev);
269 struct ixgbe_hw *hw = &adapter->hw;
270 u32 *regs_buff = p;
271 u8 i;
272
273 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
274
275 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
276
277 /* General Registers */
278 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
279 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
280 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
281 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
282 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
283 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
284 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
285 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
286
287 /* NVM Register */
288 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
289 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
290 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
291 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
292 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
293 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
294 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
295 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
296 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
297 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
298
299 /* Interrupt */
300 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICR);
301 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
302 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
303 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
304 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
305 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
306 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
307 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
308 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
309 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
310 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL);
311 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
312
313 /* Flow Control */
314 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
315 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
316 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
317 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
318 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
319 for (i = 0; i < 8; i++)
320 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
321 for (i = 0; i < 8; i++)
322 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
323 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
324 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
325
326 /* Receive DMA */
327 for (i = 0; i < 64; i++)
328 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
329 for (i = 0; i < 64; i++)
330 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
331 for (i = 0; i < 64; i++)
332 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
333 for (i = 0; i < 64; i++)
334 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
335 for (i = 0; i < 64; i++)
336 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
337 for (i = 0; i < 64; i++)
338 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
339 for (i = 0; i < 16; i++)
340 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
341 for (i = 0; i < 16; i++)
342 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
343 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
344 for (i = 0; i < 8; i++)
345 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
346 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
347 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
348
349 /* Receive */
350 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
351 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
352 for (i = 0; i < 16; i++)
353 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
354 for (i = 0; i < 16; i++)
355 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
356 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE);
357 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
358 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
359 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
360 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
361 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
362 for (i = 0; i < 8; i++)
363 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
364 for (i = 0; i < 8; i++)
365 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
366 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
367
368 /* Transmit */
369 for (i = 0; i < 32; i++)
370 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
371 for (i = 0; i < 32; i++)
372 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
373 for (i = 0; i < 32; i++)
374 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
375 for (i = 0; i < 32; i++)
376 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
377 for (i = 0; i < 32; i++)
378 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
379 for (i = 0; i < 32; i++)
380 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
381 for (i = 0; i < 32; i++)
382 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
383 for (i = 0; i < 32; i++)
384 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
385 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
386 for (i = 0; i < 16; i++)
387 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
388 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
389 for (i = 0; i < 8; i++)
390 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
391 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
392
393 /* Wake Up */
394 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
395 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
396 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
397 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
398 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
399 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
400 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
401 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
402 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT);
403
404 /* DCE */
405 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
406 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
407 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
408 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
409 for (i = 0; i < 8; i++)
410 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
411 for (i = 0; i < 8; i++)
412 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
413 for (i = 0; i < 8; i++)
414 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
415 for (i = 0; i < 8; i++)
416 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
417 for (i = 0; i < 8; i++)
418 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
419 for (i = 0; i < 8; i++)
420 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
421
422 /* Statistics */
423 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
424 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
425 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
426 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
427 for (i = 0; i < 8; i++)
428 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
429 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
430 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
431 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
432 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
433 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
434 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
435 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
436 for (i = 0; i < 8; i++)
437 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
438 for (i = 0; i < 8; i++)
439 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
440 for (i = 0; i < 8; i++)
441 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
442 for (i = 0; i < 8; i++)
443 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
444 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
445 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
446 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
447 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
448 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
449 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
450 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
451 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
452 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
453 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
454 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
455 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
456 for (i = 0; i < 8; i++)
457 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
458 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
459 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
460 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
461 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
462 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
463 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
464 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
465 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
466 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
467 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
468 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
469 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
470 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
471 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
472 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
473 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
474 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
475 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
476 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
477 for (i = 0; i < 16; i++)
478 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
479 for (i = 0; i < 16; i++)
480 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
481 for (i = 0; i < 16; i++)
482 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
483 for (i = 0; i < 16; i++)
484 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
485
486 /* MAC */
487 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
488 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
489 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
490 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
491 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
492 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
493 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
494 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
495 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
496 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
497 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
498 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
499 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
500 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
501 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
502 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
503 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
504 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
505 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
506 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
507 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
508 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
509 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
510 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
511 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
512 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
513 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
514 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
515 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
516 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
517 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
518 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
519 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
520
521 /* Diagnostic */
522 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
523 for (i = 0; i < 8; i++)
524 regs_buff[1072] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
525 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
526 regs_buff[1081] = IXGBE_READ_REG(hw, IXGBE_RIC_DW0);
527 regs_buff[1082] = IXGBE_READ_REG(hw, IXGBE_RIC_DW1);
528 regs_buff[1083] = IXGBE_READ_REG(hw, IXGBE_RIC_DW2);
529 regs_buff[1084] = IXGBE_READ_REG(hw, IXGBE_RIC_DW3);
530 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
531 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
532 for (i = 0; i < 8; i++)
533 regs_buff[1087] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
534 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
535 regs_buff[1096] = IXGBE_READ_REG(hw, IXGBE_TIC_DW0);
536 regs_buff[1097] = IXGBE_READ_REG(hw, IXGBE_TIC_DW1);
537 regs_buff[1098] = IXGBE_READ_REG(hw, IXGBE_TIC_DW2);
538 regs_buff[1099] = IXGBE_READ_REG(hw, IXGBE_TIC_DW3);
539 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
540 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
541 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
542 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
543 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
544 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
545 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
546 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
547 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
548 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
549 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
550 for (i = 0; i < 8; i++)
551 regs_buff[1111] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
552 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
553 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
554 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
555 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
556 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
557 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
558 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
559 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
560 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
561}
562
563static int ixgbe_get_eeprom_len(struct net_device *netdev)
564{
565 struct ixgbe_adapter *adapter = netdev_priv(netdev);
566 return adapter->hw.eeprom.word_size * 2;
567}
568
569static int ixgbe_get_eeprom(struct net_device *netdev,
570 struct ethtool_eeprom *eeprom, u8 *bytes)
571{
572 struct ixgbe_adapter *adapter = netdev_priv(netdev);
573 struct ixgbe_hw *hw = &adapter->hw;
574 u16 *eeprom_buff;
575 int first_word, last_word, eeprom_len;
576 int ret_val = 0;
577 u16 i;
578
579 if (eeprom->len == 0)
580 return -EINVAL;
581
582 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
583
584 first_word = eeprom->offset >> 1;
585 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
586 eeprom_len = last_word - first_word + 1;
587
588 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
589 if (!eeprom_buff)
590 return -ENOMEM;
591
592 for (i = 0; i < eeprom_len; i++) {
593 if ((ret_val = ixgbe_read_eeprom(hw, first_word + i,
594 &eeprom_buff[i])))
595 break;
596 }
597
598 /* Device's eeprom is always little-endian, word addressable */
599 for (i = 0; i < eeprom_len; i++)
600 le16_to_cpus(&eeprom_buff[i]);
601
602 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
603 kfree(eeprom_buff);
604
605 return ret_val;
606}
607
608static void ixgbe_get_drvinfo(struct net_device *netdev,
609 struct ethtool_drvinfo *drvinfo)
610{
611 struct ixgbe_adapter *adapter = netdev_priv(netdev);
612
613 strncpy(drvinfo->driver, ixgbe_driver_name, 32);
614 strncpy(drvinfo->version, ixgbe_driver_version, 32);
615 strncpy(drvinfo->fw_version, "N/A", 32);
616 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
617 drvinfo->n_stats = IXGBE_STATS_LEN;
618 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
619}
620
621static void ixgbe_get_ringparam(struct net_device *netdev,
622 struct ethtool_ringparam *ring)
623{
624 struct ixgbe_adapter *adapter = netdev_priv(netdev);
625 struct ixgbe_ring *tx_ring = adapter->tx_ring;
626 struct ixgbe_ring *rx_ring = adapter->rx_ring;
627
628 ring->rx_max_pending = IXGBE_MAX_RXD;
629 ring->tx_max_pending = IXGBE_MAX_TXD;
630 ring->rx_mini_max_pending = 0;
631 ring->rx_jumbo_max_pending = 0;
632 ring->rx_pending = rx_ring->count;
633 ring->tx_pending = tx_ring->count;
634 ring->rx_mini_pending = 0;
635 ring->rx_jumbo_pending = 0;
636}
637
638static int ixgbe_set_ringparam(struct net_device *netdev,
639 struct ethtool_ringparam *ring)
640{
641 struct ixgbe_adapter *adapter = netdev_priv(netdev);
642 struct ixgbe_tx_buffer *old_buf;
643 struct ixgbe_rx_buffer *old_rx_buf;
644 void *old_desc;
645 int i, err;
646 u32 new_rx_count, new_tx_count, old_size;
647 dma_addr_t old_dma;
648
649 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
650 return -EINVAL;
651
652 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
653 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
654 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
655
656 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
657 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
658 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
659
660 if ((new_tx_count == adapter->tx_ring->count) &&
661 (new_rx_count == adapter->rx_ring->count)) {
662 /* nothing to do */
663 return 0;
664 }
665
666 if (netif_running(adapter->netdev))
667 ixgbe_down(adapter);
668
669 /*
670 * We can't just free everything and then setup again,
671 * because the ISRs in MSI-X mode get passed pointers
672 * to the tx and rx ring structs.
673 */
674 if (new_tx_count != adapter->tx_ring->count) {
675 for (i = 0; i < adapter->num_tx_queues; i++) {
676 /* Save existing descriptor ring */
677 old_buf = adapter->tx_ring[i].tx_buffer_info;
678 old_desc = adapter->tx_ring[i].desc;
679 old_size = adapter->tx_ring[i].size;
680 old_dma = adapter->tx_ring[i].dma;
681 /* Try to allocate a new one */
682 adapter->tx_ring[i].tx_buffer_info = NULL;
683 adapter->tx_ring[i].desc = NULL;
684 adapter->tx_ring[i].count = new_tx_count;
685 err = ixgbe_setup_tx_resources(adapter,
686 &adapter->tx_ring[i]);
687 if (err) {
688 /* Restore the old one so at least
689 the adapter still works, even if
690 we failed the request */
691 adapter->tx_ring[i].tx_buffer_info = old_buf;
692 adapter->tx_ring[i].desc = old_desc;
693 adapter->tx_ring[i].size = old_size;
694 adapter->tx_ring[i].dma = old_dma;
695 goto err_setup;
696 }
697 /* Free the old buffer manually */
698 vfree(old_buf);
699 pci_free_consistent(adapter->pdev, old_size,
700 old_desc, old_dma);
701 }
702 }
703
704 if (new_rx_count != adapter->rx_ring->count) {
705 for (i = 0; i < adapter->num_rx_queues; i++) {
706
707 old_rx_buf = adapter->rx_ring[i].rx_buffer_info;
708 old_desc = adapter->rx_ring[i].desc;
709 old_size = adapter->rx_ring[i].size;
710 old_dma = adapter->rx_ring[i].dma;
711
712 adapter->rx_ring[i].rx_buffer_info = NULL;
713 adapter->rx_ring[i].desc = NULL;
714 adapter->rx_ring[i].dma = 0;
715 adapter->rx_ring[i].count = new_rx_count;
716 err = ixgbe_setup_rx_resources(adapter,
717 &adapter->rx_ring[i]);
718 if (err) {
719 adapter->rx_ring[i].rx_buffer_info = old_rx_buf;
720 adapter->rx_ring[i].desc = old_desc;
721 adapter->rx_ring[i].size = old_size;
722 adapter->rx_ring[i].dma = old_dma;
723 goto err_setup;
724 }
725
726 vfree(old_rx_buf);
727 pci_free_consistent(adapter->pdev, old_size, old_desc,
728 old_dma);
729 }
730 }
731
732 err = 0;
733err_setup:
734 if (netif_running(adapter->netdev))
735 ixgbe_up(adapter);
736
737 return err;
738}
739
740static int ixgbe_get_stats_count(struct net_device *netdev)
741{
742 return IXGBE_STATS_LEN;
743}
744
745static void ixgbe_get_ethtool_stats(struct net_device *netdev,
746 struct ethtool_stats *stats, u64 *data)
747{
748 struct ixgbe_adapter *adapter = netdev_priv(netdev);
749 u64 *queue_stat;
750 int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
751 int j, k;
752 int i;
753
754 ixgbe_update_stats(adapter);
755 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
756 char *p = (char *)adapter + ixgbe_gstrings_stats[i].stat_offset;
757 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
758 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
759 }
760 for (j = 0; j < adapter->num_tx_queues; j++) {
761 queue_stat = (u64 *)&adapter->tx_ring[j].stats;
762 for (k = 0; k < stat_count; k++)
763 data[i + k] = queue_stat[k];
764 i += k;
765 }
766 for (j = 0; j < adapter->num_rx_queues; j++) {
767 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
768 for (k = 0; k < stat_count; k++)
769 data[i + k] = queue_stat[k];
770 i += k;
771 }
772}
773
774static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
775 u8 *data)
776{
777 struct ixgbe_adapter *adapter = netdev_priv(netdev);
778 u8 *p = data;
779 int i;
780
781 switch (stringset) {
782 case ETH_SS_STATS:
783 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
784 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
785 ETH_GSTRING_LEN);
786 p += ETH_GSTRING_LEN;
787 }
788 for (i = 0; i < adapter->num_tx_queues; i++) {
789 sprintf(p, "tx_queue_%u_packets", i);
790 p += ETH_GSTRING_LEN;
791 sprintf(p, "tx_queue_%u_bytes", i);
792 p += ETH_GSTRING_LEN;
793 }
794 for (i = 0; i < adapter->num_rx_queues; i++) {
795 sprintf(p, "rx_queue_%u_packets", i);
796 p += ETH_GSTRING_LEN;
797 sprintf(p, "rx_queue_%u_bytes", i);
798 p += ETH_GSTRING_LEN;
799 }
800/* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
801 break;
802 }
803}
804
805
806static void ixgbe_get_wol(struct net_device *netdev,
807 struct ethtool_wolinfo *wol)
808{
809 wol->supported = 0;
810 wol->wolopts = 0;
811
812 return;
813}
814
815static int ixgbe_nway_reset(struct net_device *netdev)
816{
817 struct ixgbe_adapter *adapter = netdev_priv(netdev);
818
819 if (netif_running(netdev)) {
820 ixgbe_down(adapter);
821 ixgbe_reset(adapter);
822 ixgbe_up(adapter);
823 }
824
825 return 0;
826}
827
828static int ixgbe_phys_id(struct net_device *netdev, u32 data)
829{
830 struct ixgbe_adapter *adapter = netdev_priv(netdev);
831 u32 led_reg = IXGBE_READ_REG(&adapter->hw, IXGBE_LEDCTL);
832 u32 i;
833
834 if (!data || data > 300)
835 data = 300;
836
837 for (i = 0; i < (data * 1000); i += 400) {
838 ixgbe_led_on(&adapter->hw, IXGBE_LED_ON);
839 msleep_interruptible(200);
840 ixgbe_led_off(&adapter->hw, IXGBE_LED_ON);
841 msleep_interruptible(200);
842 }
843
844 /* Restore LED settings */
845 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
846
847 return 0;
848}
849
850static int ixgbe_get_coalesce(struct net_device *netdev,
851 struct ethtool_coalesce *ec)
852{
853 struct ixgbe_adapter *adapter = netdev_priv(netdev);
854
855 if (adapter->rx_eitr == 0)
856 ec->rx_coalesce_usecs = 0;
857 else
858 ec->rx_coalesce_usecs = 1000000 / adapter->rx_eitr;
859
860 if (adapter->tx_eitr == 0)
861 ec->tx_coalesce_usecs = 0;
862 else
863 ec->tx_coalesce_usecs = 1000000 / adapter->tx_eitr;
864
865 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
866 return 0;
867}
868
869static int ixgbe_set_coalesce(struct net_device *netdev,
870 struct ethtool_coalesce *ec)
871{
872 struct ixgbe_adapter *adapter = netdev_priv(netdev);
873
874 if ((ec->rx_coalesce_usecs > IXGBE_MAX_ITR_USECS) ||
875 ((ec->rx_coalesce_usecs > 0) &&
876 (ec->rx_coalesce_usecs < IXGBE_MIN_ITR_USECS)))
877 return -EINVAL;
878 if ((ec->tx_coalesce_usecs > IXGBE_MAX_ITR_USECS) ||
879 ((ec->tx_coalesce_usecs > 0) &&
880 (ec->tx_coalesce_usecs < IXGBE_MIN_ITR_USECS)))
881 return -EINVAL;
882
883 /* convert to rate of irq's per second */
884 if (ec->rx_coalesce_usecs == 0)
885 adapter->rx_eitr = 0;
886 else
887 adapter->rx_eitr = (1000000 / ec->rx_coalesce_usecs);
888
889 if (ec->tx_coalesce_usecs == 0)
890 adapter->tx_eitr = 0;
891 else
892 adapter->tx_eitr = (1000000 / ec->tx_coalesce_usecs);
893
894 if (ec->tx_max_coalesced_frames_irq)
895 adapter->tx_ring[0].work_limit =
896 ec->tx_max_coalesced_frames_irq;
897
898 if (netif_running(netdev)) {
899 ixgbe_down(adapter);
900 ixgbe_up(adapter);
901 }
902
903 return 0;
904}
905
906
907static struct ethtool_ops ixgbe_ethtool_ops = {
908 .get_settings = ixgbe_get_settings,
909 .set_settings = ixgbe_set_settings,
910 .get_drvinfo = ixgbe_get_drvinfo,
911 .get_regs_len = ixgbe_get_regs_len,
912 .get_regs = ixgbe_get_regs,
913 .get_wol = ixgbe_get_wol,
914 .nway_reset = ixgbe_nway_reset,
915 .get_link = ethtool_op_get_link,
916 .get_eeprom_len = ixgbe_get_eeprom_len,
917 .get_eeprom = ixgbe_get_eeprom,
918 .get_ringparam = ixgbe_get_ringparam,
919 .set_ringparam = ixgbe_set_ringparam,
920 .get_pauseparam = ixgbe_get_pauseparam,
921 .set_pauseparam = ixgbe_set_pauseparam,
922 .get_rx_csum = ixgbe_get_rx_csum,
923 .set_rx_csum = ixgbe_set_rx_csum,
924 .get_tx_csum = ixgbe_get_tx_csum,
925 .set_tx_csum = ixgbe_set_tx_csum,
926 .get_sg = ethtool_op_get_sg,
927 .set_sg = ethtool_op_set_sg,
928 .get_msglevel = ixgbe_get_msglevel,
929 .set_msglevel = ixgbe_set_msglevel,
930 .get_tso = ethtool_op_get_tso,
931 .set_tso = ixgbe_set_tso,
932 .get_strings = ixgbe_get_strings,
933 .phys_id = ixgbe_phys_id,
934 .get_stats_count = ixgbe_get_stats_count,
935 .get_ethtool_stats = ixgbe_get_ethtool_stats,
936 .get_coalesce = ixgbe_get_coalesce,
937 .set_coalesce = ixgbe_set_coalesce,
938};
939
940void ixgbe_set_ethtool_ops(struct net_device *netdev)
941{
942 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
943}
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
new file mode 100644
index 000000000000..a08a46224c28
--- /dev/null
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -0,0 +1,2873 @@
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/ipv6.h>
39#include <net/checksum.h>
40#include <net/ip6_checksum.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
43
44#include "ixgbe.h"
45#include "ixgbe_common.h"
46
47char ixgbe_driver_name[] = "ixgbe";
48static char ixgbe_driver_string[] =
49 "Intel(R) 10 Gigabit PCI Express Network Driver";
50
51#define DRV_VERSION "1.1.18"
52char ixgbe_driver_version[] = DRV_VERSION;
53static char ixgbe_copyright[] = "Copyright (c) 1999-2007 Intel Corporation.";
54
55static const struct ixgbe_info *ixgbe_info_tbl[] = {
56 [board_82598AF] = &ixgbe_82598AF_info,
57 [board_82598EB] = &ixgbe_82598EB_info,
58 [board_82598AT] = &ixgbe_82598AT_info,
59};
60
61/* ixgbe_pci_tbl - PCI Device ID Table
62 *
63 * Wildcard entries (PCI_ANY_ID) should come last
64 * Last entry must be all 0s
65 *
66 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
67 * Class, Class Mask, private data (not used) }
68 */
69static struct pci_device_id ixgbe_pci_tbl[] = {
70 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
71 board_82598AF },
72 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
73 board_82598AF },
74 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT_DUAL_PORT),
75 board_82598AT },
76 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
77 board_82598EB },
78
79 /* required last entry */
80 {0, }
81};
82MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
83
84MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
85MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
86MODULE_LICENSE("GPL");
87MODULE_VERSION(DRV_VERSION);
88
89#define DEFAULT_DEBUG_LEVEL_SHIFT 3
90
91
92#ifdef DEBUG
93/**
94 * ixgbe_get_hw_dev_name - return device name string
95 * used by hardware layer to print debugging information
96 **/
97char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
98{
99 struct ixgbe_adapter *adapter = hw->back;
100 struct net_device *netdev = adapter->netdev;
101 return netdev->name;
102}
103#endif
104
105static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
106 u8 msix_vector)
107{
108 u32 ivar, index;
109
110 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
111 index = (int_alloc_entry >> 2) & 0x1F;
112 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
113 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
114 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
115 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
116}
117
118static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
119 struct ixgbe_tx_buffer
120 *tx_buffer_info)
121{
122 if (tx_buffer_info->dma) {
123 pci_unmap_page(adapter->pdev,
124 tx_buffer_info->dma,
125 tx_buffer_info->length, PCI_DMA_TODEVICE);
126 tx_buffer_info->dma = 0;
127 }
128 if (tx_buffer_info->skb) {
129 dev_kfree_skb_any(tx_buffer_info->skb);
130 tx_buffer_info->skb = NULL;
131 }
132 /* tx_buffer_info must be completely set up in the transmit path */
133}
134
135static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
136 struct ixgbe_ring *tx_ring,
137 unsigned int eop,
138 union ixgbe_adv_tx_desc *eop_desc)
139{
140 /* Detect a transmit hang in hardware, this serializes the
141 * check with the clearing of time_stamp and movement of i */
142 adapter->detect_tx_hung = false;
143 if (tx_ring->tx_buffer_info[eop].dma &&
144 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
145 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
146 /* detected Tx unit hang */
147 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
148 " TDH <%x>\n"
149 " TDT <%x>\n"
150 " next_to_use <%x>\n"
151 " next_to_clean <%x>\n"
152 "tx_buffer_info[next_to_clean]\n"
153 " time_stamp <%lx>\n"
154 " next_to_watch <%x>\n"
155 " jiffies <%lx>\n"
156 " next_to_watch.status <%x>\n",
157 readl(adapter->hw.hw_addr + tx_ring->head),
158 readl(adapter->hw.hw_addr + tx_ring->tail),
159 tx_ring->next_to_use,
160 tx_ring->next_to_clean,
161 tx_ring->tx_buffer_info[eop].time_stamp,
162 eop, jiffies, eop_desc->wb.status);
163 return true;
164 }
165
166 return false;
167}
168
169/**
170 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
171 * @adapter: board private structure
172 **/
173static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
174 struct ixgbe_ring *tx_ring)
175{
176 struct net_device *netdev = adapter->netdev;
177 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
178 struct ixgbe_tx_buffer *tx_buffer_info;
179 unsigned int i, eop;
180 bool cleaned = false;
181 int count = 0;
182
183 i = tx_ring->next_to_clean;
184 eop = tx_ring->tx_buffer_info[i].next_to_watch;
185 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
186 while (eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) {
187 for (cleaned = false; !cleaned;) {
188 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
189 tx_buffer_info = &tx_ring->tx_buffer_info[i];
190 cleaned = (i == eop);
191
192 tx_ring->stats.bytes += tx_buffer_info->length;
193 ixgbe_unmap_and_free_tx_resource(adapter,
194 tx_buffer_info);
195 tx_desc->wb.status = 0;
196
197 i++;
198 if (i == tx_ring->count)
199 i = 0;
200 }
201
202 tx_ring->stats.packets++;
203
204 eop = tx_ring->tx_buffer_info[i].next_to_watch;
205 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
206
207 /* weight of a sort for tx, avoid endless transmit cleanup */
208 if (count++ >= tx_ring->work_limit)
209 break;
210 }
211
212 tx_ring->next_to_clean = i;
213
214#define TX_WAKE_THRESHOLD 32
215 spin_lock(&tx_ring->tx_lock);
216
217 if (cleaned && netif_carrier_ok(netdev) &&
218 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD) &&
219 !test_bit(__IXGBE_DOWN, &adapter->state))
220 netif_wake_queue(netdev);
221
222 spin_unlock(&tx_ring->tx_lock);
223
224 if (adapter->detect_tx_hung)
225 if (ixgbe_check_tx_hang(adapter, tx_ring, eop, eop_desc))
226 netif_stop_queue(netdev);
227
228 if (count >= tx_ring->work_limit)
229 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->eims_value);
230
231 return cleaned;
232}
233
234/**
235 * ixgbe_receive_skb - Send a completed packet up the stack
236 * @adapter: board private structure
237 * @skb: packet to send up
238 * @is_vlan: packet has a VLAN tag
239 * @tag: VLAN tag from descriptor
240 **/
241static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
242 struct sk_buff *skb, bool is_vlan,
243 u16 tag)
244{
245 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
246 if (adapter->vlgrp && is_vlan)
247 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
248 else
249 netif_receive_skb(skb);
250 } else {
251
252 if (adapter->vlgrp && is_vlan)
253 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
254 else
255 netif_rx(skb);
256 }
257}
258
259static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
260 u32 status_err,
261 struct sk_buff *skb)
262{
263 skb->ip_summed = CHECKSUM_NONE;
264
265 /* Ignore Checksum bit is set */
266 if ((status_err & IXGBE_RXD_STAT_IXSM) ||
267 !(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
268 return;
269 /* TCP/UDP checksum error bit is set */
270 if (status_err & (IXGBE_RXDADV_ERR_TCPE | IXGBE_RXDADV_ERR_IPE)) {
271 /* let the stack verify checksum errors */
272 adapter->hw_csum_rx_error++;
273 return;
274 }
275 /* It must be a TCP or UDP packet with a valid checksum */
276 if (status_err & (IXGBE_RXD_STAT_L4CS | IXGBE_RXD_STAT_UDPCS))
277 skb->ip_summed = CHECKSUM_UNNECESSARY;
278 adapter->hw_csum_rx_good++;
279}
280
281/**
282 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
283 * @adapter: address of board private structure
284 **/
285static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
286 struct ixgbe_ring *rx_ring,
287 int cleaned_count)
288{
289 struct net_device *netdev = adapter->netdev;
290 struct pci_dev *pdev = adapter->pdev;
291 union ixgbe_adv_rx_desc *rx_desc;
292 struct ixgbe_rx_buffer *rx_buffer_info;
293 struct sk_buff *skb;
294 unsigned int i;
295 unsigned int bufsz = adapter->rx_buf_len + NET_IP_ALIGN;
296
297 i = rx_ring->next_to_use;
298 rx_buffer_info = &rx_ring->rx_buffer_info[i];
299
300 while (cleaned_count--) {
301 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
302
303 if (!rx_buffer_info->page &&
304 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
305 rx_buffer_info->page = alloc_page(GFP_ATOMIC);
306 if (!rx_buffer_info->page) {
307 adapter->alloc_rx_page_failed++;
308 goto no_buffers;
309 }
310 rx_buffer_info->page_dma =
311 pci_map_page(pdev, rx_buffer_info->page,
312 0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
313 }
314
315 if (!rx_buffer_info->skb) {
316 skb = netdev_alloc_skb(netdev, bufsz);
317
318 if (!skb) {
319 adapter->alloc_rx_buff_failed++;
320 goto no_buffers;
321 }
322
323 /*
324 * Make buffer alignment 2 beyond a 16 byte boundary
325 * this will result in a 16 byte aligned IP header after
326 * the 14 byte MAC header is removed
327 */
328 skb_reserve(skb, NET_IP_ALIGN);
329
330 rx_buffer_info->skb = skb;
331 rx_buffer_info->dma = pci_map_single(pdev, skb->data,
332 bufsz,
333 PCI_DMA_FROMDEVICE);
334 }
335 /* Refresh the desc even if buffer_addrs didn't change because
336 * each write-back erases this info. */
337 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
338 rx_desc->read.pkt_addr =
339 cpu_to_le64(rx_buffer_info->page_dma);
340 rx_desc->read.hdr_addr =
341 cpu_to_le64(rx_buffer_info->dma);
342 } else {
343 rx_desc->read.pkt_addr =
344 cpu_to_le64(rx_buffer_info->dma);
345 }
346
347 i++;
348 if (i == rx_ring->count)
349 i = 0;
350 rx_buffer_info = &rx_ring->rx_buffer_info[i];
351 }
352no_buffers:
353 if (rx_ring->next_to_use != i) {
354 rx_ring->next_to_use = i;
355 if (i-- == 0)
356 i = (rx_ring->count - 1);
357
358 /*
359 * Force memory writes to complete before letting h/w
360 * know there are new descriptors to fetch. (Only
361 * applicable for weak-ordered memory model archs,
362 * such as IA-64).
363 */
364 wmb();
365 writel(i, adapter->hw.hw_addr + rx_ring->tail);
366 }
367}
368
369static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
370 struct ixgbe_ring *rx_ring,
371 int *work_done, int work_to_do)
372{
373 struct net_device *netdev = adapter->netdev;
374 struct pci_dev *pdev = adapter->pdev;
375 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
376 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
377 struct sk_buff *skb;
378 unsigned int i;
379 u32 upper_len, len, staterr;
380 u16 hdr_info, vlan_tag;
381 bool is_vlan, cleaned = false;
382 int cleaned_count = 0;
383
384 i = rx_ring->next_to_clean;
385 upper_len = 0;
386 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
387 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
388 rx_buffer_info = &rx_ring->rx_buffer_info[i];
389 is_vlan = (staterr & IXGBE_RXD_STAT_VP);
390 vlan_tag = le16_to_cpu(rx_desc->wb.upper.vlan);
391
392 while (staterr & IXGBE_RXD_STAT_DD) {
393 if (*work_done >= work_to_do)
394 break;
395 (*work_done)++;
396
397 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
398 hdr_info =
399 le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info);
400 len =
401 ((hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
402 IXGBE_RXDADV_HDRBUFLEN_SHIFT);
403 if (hdr_info & IXGBE_RXDADV_SPH)
404 adapter->rx_hdr_split++;
405 if (len > IXGBE_RX_HDR_SIZE)
406 len = IXGBE_RX_HDR_SIZE;
407 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
408 } else
409 len = le16_to_cpu(rx_desc->wb.upper.length);
410
411 cleaned = true;
412 skb = rx_buffer_info->skb;
413 prefetch(skb->data - NET_IP_ALIGN);
414 rx_buffer_info->skb = NULL;
415
416 if (len && !skb_shinfo(skb)->nr_frags) {
417 pci_unmap_single(pdev, rx_buffer_info->dma,
418 adapter->rx_buf_len + NET_IP_ALIGN,
419 PCI_DMA_FROMDEVICE);
420 skb_put(skb, len);
421 }
422
423 if (upper_len) {
424 pci_unmap_page(pdev, rx_buffer_info->page_dma,
425 PAGE_SIZE, PCI_DMA_FROMDEVICE);
426 rx_buffer_info->page_dma = 0;
427 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
428 rx_buffer_info->page, 0, upper_len);
429 rx_buffer_info->page = NULL;
430
431 skb->len += upper_len;
432 skb->data_len += upper_len;
433 skb->truesize += upper_len;
434 }
435
436 i++;
437 if (i == rx_ring->count)
438 i = 0;
439 next_buffer = &rx_ring->rx_buffer_info[i];
440
441 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
442 prefetch(next_rxd);
443
444 cleaned_count++;
445 if (staterr & IXGBE_RXD_STAT_EOP) {
446 rx_ring->stats.packets++;
447 rx_ring->stats.bytes += skb->len;
448 } else {
449 rx_buffer_info->skb = next_buffer->skb;
450 rx_buffer_info->dma = next_buffer->dma;
451 next_buffer->skb = skb;
452 adapter->non_eop_descs++;
453 goto next_desc;
454 }
455
456 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
457 dev_kfree_skb_irq(skb);
458 goto next_desc;
459 }
460
461 ixgbe_rx_checksum(adapter, staterr, skb);
462 skb->protocol = eth_type_trans(skb, netdev);
463 ixgbe_receive_skb(adapter, skb, is_vlan, vlan_tag);
464 netdev->last_rx = jiffies;
465
466next_desc:
467 rx_desc->wb.upper.status_error = 0;
468
469 /* return some buffers to hardware, one at a time is too slow */
470 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
471 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
472 cleaned_count = 0;
473 }
474
475 /* use prefetched values */
476 rx_desc = next_rxd;
477 rx_buffer_info = next_buffer;
478
479 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
480 is_vlan = (staterr & IXGBE_RXD_STAT_VP);
481 vlan_tag = le16_to_cpu(rx_desc->wb.upper.vlan);
482 }
483
484 rx_ring->next_to_clean = i;
485 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
486
487 if (cleaned_count)
488 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
489
490 return cleaned;
491}
492
493#define IXGBE_MAX_INTR 10
494/**
495 * ixgbe_configure_msix - Configure MSI-X hardware
496 * @adapter: board private structure
497 *
498 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
499 * interrupts.
500 **/
501static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
502{
503 int i, vector = 0;
504
505 for (i = 0; i < adapter->num_tx_queues; i++) {
506 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(i),
507 IXGBE_MSIX_VECTOR(vector));
508 writel(EITR_INTS_PER_SEC_TO_REG(adapter->tx_eitr),
509 adapter->hw.hw_addr + adapter->tx_ring[i].itr_register);
510 vector++;
511 }
512
513 for (i = 0; i < adapter->num_rx_queues; i++) {
514 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(i),
515 IXGBE_MSIX_VECTOR(vector));
516 writel(EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr),
517 adapter->hw.hw_addr + adapter->rx_ring[i].itr_register);
518 vector++;
519 }
520
521 vector = adapter->num_tx_queues + adapter->num_rx_queues;
522 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX,
523 IXGBE_MSIX_VECTOR(vector));
524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(vector), 1950);
525}
526
527static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
528{
529 struct net_device *netdev = data;
530 struct ixgbe_adapter *adapter = netdev_priv(netdev);
531 struct ixgbe_hw *hw = &adapter->hw;
532 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
533
534 if (eicr & IXGBE_EICR_LSC) {
535 adapter->lsc_int++;
536 if (!test_bit(__IXGBE_DOWN, &adapter->state))
537 mod_timer(&adapter->watchdog_timer, jiffies);
538 }
539 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
540
541 return IRQ_HANDLED;
542}
543
544static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
545{
546 struct ixgbe_ring *txr = data;
547 struct ixgbe_adapter *adapter = txr->adapter;
548
549 ixgbe_clean_tx_irq(adapter, txr);
550
551 return IRQ_HANDLED;
552}
553
554static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
555{
556 struct ixgbe_ring *rxr = data;
557 struct ixgbe_adapter *adapter = rxr->adapter;
558
559 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rxr->eims_value);
560 netif_rx_schedule(adapter->netdev, &adapter->napi);
561 return IRQ_HANDLED;
562}
563
564static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
565{
566 struct ixgbe_adapter *adapter = container_of(napi,
567 struct ixgbe_adapter, napi);
568 struct net_device *netdev = adapter->netdev;
569 int work_done = 0;
570 struct ixgbe_ring *rxr = adapter->rx_ring;
571
572 /* Keep link state information with original netdev */
573 if (!netif_carrier_ok(netdev))
574 goto quit_polling;
575
576 ixgbe_clean_rx_irq(adapter, rxr, &work_done, budget);
577
578 /* If no Tx and not enough Rx work done, exit the polling mode */
579 if ((work_done < budget) || !netif_running(netdev)) {
580quit_polling:
581 netif_rx_complete(netdev, napi);
582 if (!test_bit(__IXGBE_DOWN, &adapter->state))
583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS,
584 rxr->eims_value);
585 }
586
587 return work_done;
588}
589
590/**
591 * ixgbe_setup_msix - Initialize MSI-X interrupts
592 *
593 * ixgbe_setup_msix allocates MSI-X vectors and requests
594 * interrutps from the kernel.
595 **/
596static int ixgbe_setup_msix(struct ixgbe_adapter *adapter)
597{
598 struct net_device *netdev = adapter->netdev;
599 int i, int_vector = 0, err = 0;
600 int max_msix_count;
601
602 /* +1 for the LSC interrupt */
603 max_msix_count = adapter->num_rx_queues + adapter->num_tx_queues + 1;
604 adapter->msix_entries = kcalloc(max_msix_count,
605 sizeof(struct msix_entry), GFP_KERNEL);
606 if (!adapter->msix_entries)
607 return -ENOMEM;
608
609 for (i = 0; i < max_msix_count; i++)
610 adapter->msix_entries[i].entry = i;
611
612 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
613 max_msix_count);
614 if (err)
615 goto out;
616
617 for (i = 0; i < adapter->num_tx_queues; i++) {
618 sprintf(adapter->tx_ring[i].name, "%s-tx%d", netdev->name, i);
619 err = request_irq(adapter->msix_entries[int_vector].vector,
620 &ixgbe_msix_clean_tx,
621 0,
622 adapter->tx_ring[i].name,
623 &(adapter->tx_ring[i]));
624 if (err) {
625 DPRINTK(PROBE, ERR,
626 "request_irq failed for MSIX interrupt "
627 "Error: %d\n", err);
628 goto release_irqs;
629 }
630 adapter->tx_ring[i].eims_value =
631 (1 << IXGBE_MSIX_VECTOR(int_vector));
632 adapter->tx_ring[i].itr_register = IXGBE_EITR(int_vector);
633 int_vector++;
634 }
635
636 for (i = 0; i < adapter->num_rx_queues; i++) {
637 if (strlen(netdev->name) < (IFNAMSIZ - 5))
638 sprintf(adapter->rx_ring[i].name,
639 "%s-rx%d", netdev->name, i);
640 else
641 memcpy(adapter->rx_ring[i].name,
642 netdev->name, IFNAMSIZ);
643 err = request_irq(adapter->msix_entries[int_vector].vector,
644 &ixgbe_msix_clean_rx, 0,
645 adapter->rx_ring[i].name,
646 &(adapter->rx_ring[i]));
647 if (err) {
648 DPRINTK(PROBE, ERR,
649 "request_irq failed for MSIX interrupt "
650 "Error: %d\n", err);
651 goto release_irqs;
652 }
653
654 adapter->rx_ring[i].eims_value =
655 (1 << IXGBE_MSIX_VECTOR(int_vector));
656 adapter->rx_ring[i].itr_register = IXGBE_EITR(int_vector);
657 int_vector++;
658 }
659
660 sprintf(adapter->lsc_name, "%s-lsc", netdev->name);
661 err = request_irq(adapter->msix_entries[int_vector].vector,
662 &ixgbe_msix_lsc, 0, adapter->lsc_name, netdev);
663 if (err) {
664 DPRINTK(PROBE, ERR,
665 "request_irq for msix_lsc failed: %d\n", err);
666 goto release_irqs;
667 }
668
669 /* FIXME: implement netif_napi_remove() instead */
670 adapter->napi.poll = ixgbe_clean_rxonly;
671 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED;
672 return 0;
673
674release_irqs:
675 int_vector--;
676 for (; int_vector >= adapter->num_tx_queues; int_vector--)
677 free_irq(adapter->msix_entries[int_vector].vector,
678 &(adapter->rx_ring[int_vector -
679 adapter->num_tx_queues]));
680
681 for (; int_vector >= 0; int_vector--)
682 free_irq(adapter->msix_entries[int_vector].vector,
683 &(adapter->tx_ring[int_vector]));
684out:
685 kfree(adapter->msix_entries);
686 adapter->msix_entries = NULL;
687 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
688 return err;
689}
690
691/**
692 * ixgbe_intr - Interrupt Handler
693 * @irq: interrupt number
694 * @data: pointer to a network interface device structure
695 * @pt_regs: CPU registers structure
696 **/
697static irqreturn_t ixgbe_intr(int irq, void *data)
698{
699 struct net_device *netdev = data;
700 struct ixgbe_adapter *adapter = netdev_priv(netdev);
701 struct ixgbe_hw *hw = &adapter->hw;
702 u32 eicr;
703
704 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
705
706 if (!eicr)
707 return IRQ_NONE; /* Not our interrupt */
708
709 if (eicr & IXGBE_EICR_LSC) {
710 adapter->lsc_int++;
711 if (!test_bit(__IXGBE_DOWN, &adapter->state))
712 mod_timer(&adapter->watchdog_timer, jiffies);
713 }
714 if (netif_rx_schedule_prep(netdev, &adapter->napi)) {
715 /* Disable interrupts and register for poll. The flush of the
716 * posted write is intentionally left out. */
717 atomic_inc(&adapter->irq_sem);
718 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
719 __netif_rx_schedule(netdev, &adapter->napi);
720 }
721
722 return IRQ_HANDLED;
723}
724
725/**
726 * ixgbe_request_irq - initialize interrupts
727 * @adapter: board private structure
728 *
729 * Attempts to configure interrupts using the best available
730 * capabilities of the hardware and kernel.
731 **/
732static int ixgbe_request_irq(struct ixgbe_adapter *adapter, u32 *num_rx_queues)
733{
734 struct net_device *netdev = adapter->netdev;
735 int flags, err;
736 irqreturn_t(*handler) (int, void *) = &ixgbe_intr;
737
738 flags = IRQF_SHARED;
739
740 err = ixgbe_setup_msix(adapter);
741 if (!err)
742 goto request_done;
743
744 /*
745 * if we can't do MSI-X, fall through and try MSI
746 * No need to reallocate memory since we're decreasing the number of
747 * queues. We just won't use the other ones, also it is freed correctly
748 * on ixgbe_remove.
749 */
750 *num_rx_queues = 1;
751
752 /* do MSI */
753 err = pci_enable_msi(adapter->pdev);
754 if (!err) {
755 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
756 flags &= ~IRQF_SHARED;
757 handler = &ixgbe_intr;
758 }
759
760 err = request_irq(adapter->pdev->irq, handler, flags,
761 netdev->name, netdev);
762 if (err)
763 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
764
765request_done:
766 return err;
767}
768
769static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
770{
771 struct net_device *netdev = adapter->netdev;
772
773 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
774 int i;
775
776 for (i = 0; i < adapter->num_tx_queues; i++)
777 free_irq(adapter->msix_entries[i].vector,
778 &(adapter->tx_ring[i]));
779 for (i = 0; i < adapter->num_rx_queues; i++)
780 free_irq(adapter->msix_entries[i +
781 adapter->num_tx_queues].vector,
782 &(adapter->rx_ring[i]));
783 i = adapter->num_rx_queues + adapter->num_tx_queues;
784 free_irq(adapter->msix_entries[i].vector, netdev);
785 pci_disable_msix(adapter->pdev);
786 kfree(adapter->msix_entries);
787 adapter->msix_entries = NULL;
788 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
789 return;
790 }
791
792 free_irq(adapter->pdev->irq, netdev);
793 if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
794 pci_disable_msi(adapter->pdev);
795 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
796 }
797}
798
799/**
800 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
801 * @adapter: board private structure
802 **/
803static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
804{
805 atomic_inc(&adapter->irq_sem);
806 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
807 IXGBE_WRITE_FLUSH(&adapter->hw);
808 synchronize_irq(adapter->pdev->irq);
809}
810
811/**
812 * ixgbe_irq_enable - Enable default interrupt generation settings
813 * @adapter: board private structure
814 **/
815static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
816{
817 if (atomic_dec_and_test(&adapter->irq_sem)) {
818 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
819 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC,
820 (IXGBE_EIMS_ENABLE_MASK &
821 ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC)));
822 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS,
823 IXGBE_EIMS_ENABLE_MASK);
824 IXGBE_WRITE_FLUSH(&adapter->hw);
825 }
826}
827
828/**
829 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
830 *
831 **/
832static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
833{
834 int i;
835 struct ixgbe_hw *hw = &adapter->hw;
836
837 if (adapter->rx_eitr)
838 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
839 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr));
840
841 /* for re-triggering the interrupt in non-NAPI mode */
842 adapter->rx_ring[0].eims_value = (1 << IXGBE_MSIX_VECTOR(0));
843 adapter->tx_ring[0].eims_value = (1 << IXGBE_MSIX_VECTOR(0));
844
845 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
846 for (i = 0; i < adapter->num_tx_queues; i++)
847 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(i), i);
848}
849
850/**
851 * ixgbe_configure_tx - Configure 8254x Transmit Unit after Reset
852 * @adapter: board private structure
853 *
854 * Configure the Tx unit of the MAC after a reset.
855 **/
856static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
857{
858 u64 tdba;
859 struct ixgbe_hw *hw = &adapter->hw;
860 u32 i, tdlen;
861
862 /* Setup the HW Tx Head and Tail descriptor pointers */
863 for (i = 0; i < adapter->num_tx_queues; i++) {
864 tdba = adapter->tx_ring[i].dma;
865 tdlen = adapter->tx_ring[i].count *
866 sizeof(union ixgbe_adv_tx_desc);
867 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(i), (tdba & DMA_32BIT_MASK));
868 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(i), (tdba >> 32));
869 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(i), tdlen);
870 IXGBE_WRITE_REG(hw, IXGBE_TDH(i), 0);
871 IXGBE_WRITE_REG(hw, IXGBE_TDT(i), 0);
872 adapter->tx_ring[i].head = IXGBE_TDH(i);
873 adapter->tx_ring[i].tail = IXGBE_TDT(i);
874 }
875
876 IXGBE_WRITE_REG(hw, IXGBE_TIPG, IXGBE_TIPG_FIBER_DEFAULT);
877}
878
879#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
880 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
881
882#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
883/**
884 * ixgbe_configure_rx - Configure 8254x Receive Unit after Reset
885 * @adapter: board private structure
886 *
887 * Configure the Rx unit of the MAC after a reset.
888 **/
889static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
890{
891 u64 rdba;
892 struct ixgbe_hw *hw = &adapter->hw;
893 struct net_device *netdev = adapter->netdev;
894 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
895 u32 rdlen, rxctrl, rxcsum;
896 u32 random[10];
897 u32 reta, mrqc;
898 int i;
899 u32 fctrl, hlreg0;
900 u32 srrctl;
901 u32 pages;
902
903 /* Decide whether to use packet split mode or not */
904 if (netdev->mtu > ETH_DATA_LEN)
905 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
906 else
907 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
908
909 /* Set the RX buffer length according to the mode */
910 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
911 adapter->rx_buf_len = IXGBE_RX_HDR_SIZE;
912 } else {
913 if (netdev->mtu <= ETH_DATA_LEN)
914 adapter->rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
915 else
916 adapter->rx_buf_len = ALIGN(max_frame, 1024);
917 }
918
919 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
920 fctrl |= IXGBE_FCTRL_BAM;
921 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
922
923 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
924 if (adapter->netdev->mtu <= ETH_DATA_LEN)
925 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
926 else
927 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
928 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
929
930 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
931
932 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(0));
933 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
934 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
935
936 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
937 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
938 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
939 srrctl |= ((IXGBE_RX_HDR_SIZE <<
940 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
941 IXGBE_SRRCTL_BSIZEHDR_MASK);
942 } else {
943 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
944
945 if (adapter->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
946 srrctl |=
947 IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
948 else
949 srrctl |=
950 adapter->rx_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
951 }
952 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(0), srrctl);
953
954 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
955 /* disable receives while setting up the descriptors */
956 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
957 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
958
959 /* Setup the HW Rx Head and Tail Descriptor Pointers and
960 * the Base and Length of the Rx Descriptor Ring */
961 for (i = 0; i < adapter->num_rx_queues; i++) {
962 rdba = adapter->rx_ring[i].dma;
963 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(i), (rdba & DMA_32BIT_MASK));
964 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(i), (rdba >> 32));
965 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(i), rdlen);
966 IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
967 IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
968 adapter->rx_ring[i].head = IXGBE_RDH(i);
969 adapter->rx_ring[i].tail = IXGBE_RDT(i);
970 }
971
972 if (adapter->num_rx_queues > 1) {
973 /* Random 40bytes used as random key in RSS hash function */
974 get_random_bytes(&random[0], 40);
975
976 switch (adapter->num_rx_queues) {
977 case 8:
978 case 4:
979 /* Bits [3:0] in each byte refers the Rx queue no */
980 reta = 0x00010203;
981 break;
982 case 2:
983 reta = 0x00010001;
984 break;
985 default:
986 reta = 0x00000000;
987 break;
988 }
989
990 /* Fill out redirection table */
991 for (i = 0; i < 32; i++) {
992 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RETA(0), i, reta);
993 if (adapter->num_rx_queues > 4) {
994 i++;
995 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RETA(0), i,
996 0x04050607);
997 }
998 }
999
1000 /* Fill out hash function seeds */
1001 for (i = 0; i < 10; i++)
1002 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, random[i]);
1003
1004 mrqc = IXGBE_MRQC_RSSEN
1005 /* Perform hash on these packet types */
1006 | IXGBE_MRQC_RSS_FIELD_IPV4
1007 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1008 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1009 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1010 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1011 | IXGBE_MRQC_RSS_FIELD_IPV6
1012 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1013 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1014 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
1015 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1016
1017 /* Multiqueue and packet checksumming are mutually exclusive. */
1018 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1019 rxcsum |= IXGBE_RXCSUM_PCSD;
1020 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1021 } else {
1022 /* Enable Receive Checksum Offload for TCP and UDP */
1023 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1024 if (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1025 /* Enable IPv4 payload checksum for UDP fragments
1026 * Must be used in conjunction with packet-split. */
1027 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1028 } else {
1029 /* don't need to clear IPPCSE as it defaults to 0 */
1030 }
1031 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1032 }
1033 /* Enable Receives */
1034 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1035 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1036}
1037
1038static void ixgbe_vlan_rx_register(struct net_device *netdev,
1039 struct vlan_group *grp)
1040{
1041 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1042 u32 ctrl;
1043
1044 ixgbe_irq_disable(adapter);
1045 adapter->vlgrp = grp;
1046
1047 if (grp) {
1048 /* enable VLAN tag insert/strip */
1049 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1050 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
1051 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1052 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1053 }
1054
1055 ixgbe_irq_enable(adapter);
1056}
1057
1058static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1059{
1060 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1061
1062 /* add VID to filter table */
1063 ixgbe_set_vfta(&adapter->hw, vid, 0, true);
1064}
1065
1066static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1067{
1068 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1069
1070 ixgbe_irq_disable(adapter);
1071 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1072 ixgbe_irq_enable(adapter);
1073
1074 /* remove VID from filter table */
1075 ixgbe_set_vfta(&adapter->hw, vid, 0, false);
1076}
1077
1078static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1079{
1080 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1081
1082 if (adapter->vlgrp) {
1083 u16 vid;
1084 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1085 if (!vlan_group_get_device(adapter->vlgrp, vid))
1086 continue;
1087 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1088 }
1089 }
1090}
1091
1092/**
1093 * ixgbe_set_multi - Multicast and Promiscuous mode set
1094 * @netdev: network interface device structure
1095 *
1096 * The set_multi entry point is called whenever the multicast address
1097 * list or the network interface flags are updated. This routine is
1098 * responsible for configuring the hardware for proper multicast,
1099 * promiscuous mode, and all-multi behavior.
1100 **/
1101static void ixgbe_set_multi(struct net_device *netdev)
1102{
1103 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1104 struct ixgbe_hw *hw = &adapter->hw;
1105 struct dev_mc_list *mc_ptr;
1106 u8 *mta_list;
1107 u32 fctrl;
1108 int i;
1109
1110 /* Check for Promiscuous and All Multicast modes */
1111
1112 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1113
1114 if (netdev->flags & IFF_PROMISC) {
1115 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1116 } else if (netdev->flags & IFF_ALLMULTI) {
1117 fctrl |= IXGBE_FCTRL_MPE;
1118 fctrl &= ~IXGBE_FCTRL_UPE;
1119 } else {
1120 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1121 }
1122
1123 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1124
1125 if (netdev->mc_count) {
1126 mta_list = kcalloc(netdev->mc_count, ETH_ALEN, GFP_ATOMIC);
1127 if (!mta_list)
1128 return;
1129
1130 /* Shared function expects packed array of only addresses. */
1131 mc_ptr = netdev->mc_list;
1132
1133 for (i = 0; i < netdev->mc_count; i++) {
1134 if (!mc_ptr)
1135 break;
1136 memcpy(mta_list + (i * ETH_ALEN), mc_ptr->dmi_addr,
1137 ETH_ALEN);
1138 mc_ptr = mc_ptr->next;
1139 }
1140
1141 ixgbe_update_mc_addr_list(hw, mta_list, i, 0);
1142 kfree(mta_list);
1143 } else {
1144 ixgbe_update_mc_addr_list(hw, NULL, 0, 0);
1145 }
1146
1147}
1148
1149static void ixgbe_configure(struct ixgbe_adapter *adapter)
1150{
1151 struct net_device *netdev = adapter->netdev;
1152 int i;
1153
1154 ixgbe_set_multi(netdev);
1155
1156 ixgbe_restore_vlan(adapter);
1157
1158 ixgbe_configure_tx(adapter);
1159 ixgbe_configure_rx(adapter);
1160 for (i = 0; i < adapter->num_rx_queues; i++)
1161 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1162 (adapter->rx_ring[i].count - 1));
1163}
1164
1165static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1166{
1167 struct net_device *netdev = adapter->netdev;
1168 int i;
1169 u32 gpie = 0;
1170 struct ixgbe_hw *hw = &adapter->hw;
1171 u32 txdctl, rxdctl, mhadd;
1172 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1173
1174 if (adapter->flags & (IXGBE_FLAG_MSIX_ENABLED |
1175 IXGBE_FLAG_MSI_ENABLED)) {
1176 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1177 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1178 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1179 } else {
1180 /* MSI only */
1181 gpie = (IXGBE_GPIE_EIAME |
1182 IXGBE_GPIE_PBA_SUPPORT);
1183 }
1184 IXGBE_WRITE_REG(&adapter->hw, IXGBE_GPIE, gpie);
1185 gpie = IXGBE_READ_REG(&adapter->hw, IXGBE_GPIE);
1186 }
1187
1188 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
1189
1190 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1191 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1192 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1193
1194 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1195 }
1196
1197 for (i = 0; i < adapter->num_tx_queues; i++) {
1198 txdctl = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(i));
1199 txdctl |= IXGBE_TXDCTL_ENABLE;
1200 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(i), txdctl);
1201 }
1202
1203 for (i = 0; i < adapter->num_rx_queues; i++) {
1204 rxdctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(i));
1205 rxdctl |= IXGBE_RXDCTL_ENABLE;
1206 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(i), rxdctl);
1207 }
1208 /* enable all receives */
1209 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1210 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1211 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1212
1213 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1214 ixgbe_configure_msix(adapter);
1215 else
1216 ixgbe_configure_msi_and_legacy(adapter);
1217
1218 clear_bit(__IXGBE_DOWN, &adapter->state);
1219 napi_enable(&adapter->napi);
1220 ixgbe_irq_enable(adapter);
1221
1222 /* bring the link up in the watchdog, this could race with our first
1223 * link up interrupt but shouldn't be a problem */
1224 mod_timer(&adapter->watchdog_timer, jiffies);
1225 return 0;
1226}
1227
1228int ixgbe_up(struct ixgbe_adapter *adapter)
1229{
1230 /* hardware has been reset, we need to reload some things */
1231 ixgbe_configure(adapter);
1232
1233 return ixgbe_up_complete(adapter);
1234}
1235
1236void ixgbe_reset(struct ixgbe_adapter *adapter)
1237{
1238 if (ixgbe_init_hw(&adapter->hw))
1239 DPRINTK(PROBE, ERR, "Hardware Error\n");
1240
1241 /* reprogram the RAR[0] in case user changed it. */
1242 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
1243
1244}
1245
1246#ifdef CONFIG_PM
1247static int ixgbe_resume(struct pci_dev *pdev)
1248{
1249 struct net_device *netdev = pci_get_drvdata(pdev);
1250 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1251 u32 err, num_rx_queues = adapter->num_rx_queues;
1252
1253 pci_set_power_state(pdev, PCI_D0);
1254 pci_restore_state(pdev);
1255 err = pci_enable_device(pdev);
1256 if (err) {
1257 printk(KERN_ERR "ixgbe: Cannot enable PCI device from " \
1258 "suspend\n");
1259 return err;
1260 }
1261 pci_set_master(pdev);
1262
1263 pci_enable_wake(pdev, PCI_D3hot, 0);
1264 pci_enable_wake(pdev, PCI_D3cold, 0);
1265
1266 if (netif_running(netdev)) {
1267 err = ixgbe_request_irq(adapter, &num_rx_queues);
1268 if (err)
1269 return err;
1270 }
1271
1272 ixgbe_reset(adapter);
1273
1274 if (netif_running(netdev))
1275 ixgbe_up(adapter);
1276
1277 netif_device_attach(netdev);
1278
1279 return 0;
1280}
1281#endif
1282
1283/**
1284 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
1285 * @adapter: board private structure
1286 * @rx_ring: ring to free buffers from
1287 **/
1288static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
1289 struct ixgbe_ring *rx_ring)
1290{
1291 struct pci_dev *pdev = adapter->pdev;
1292 unsigned long size;
1293 unsigned int i;
1294
1295 /* Free all the Rx ring sk_buffs */
1296
1297 for (i = 0; i < rx_ring->count; i++) {
1298 struct ixgbe_rx_buffer *rx_buffer_info;
1299
1300 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1301 if (rx_buffer_info->dma) {
1302 pci_unmap_single(pdev, rx_buffer_info->dma,
1303 adapter->rx_buf_len,
1304 PCI_DMA_FROMDEVICE);
1305 rx_buffer_info->dma = 0;
1306 }
1307 if (rx_buffer_info->skb) {
1308 dev_kfree_skb(rx_buffer_info->skb);
1309 rx_buffer_info->skb = NULL;
1310 }
1311 if (!rx_buffer_info->page)
1312 continue;
1313 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE,
1314 PCI_DMA_FROMDEVICE);
1315 rx_buffer_info->page_dma = 0;
1316
1317 put_page(rx_buffer_info->page);
1318 rx_buffer_info->page = NULL;
1319 }
1320
1321 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
1322 memset(rx_ring->rx_buffer_info, 0, size);
1323
1324 /* Zero out the descriptor ring */
1325 memset(rx_ring->desc, 0, rx_ring->size);
1326
1327 rx_ring->next_to_clean = 0;
1328 rx_ring->next_to_use = 0;
1329
1330 writel(0, adapter->hw.hw_addr + rx_ring->head);
1331 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1332}
1333
1334/**
1335 * ixgbe_clean_tx_ring - Free Tx Buffers
1336 * @adapter: board private structure
1337 * @tx_ring: ring to be cleaned
1338 **/
1339static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
1340 struct ixgbe_ring *tx_ring)
1341{
1342 struct ixgbe_tx_buffer *tx_buffer_info;
1343 unsigned long size;
1344 unsigned int i;
1345
1346 /* Free all the Tx ring sk_buffs */
1347
1348 for (i = 0; i < tx_ring->count; i++) {
1349 tx_buffer_info = &tx_ring->tx_buffer_info[i];
1350 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
1351 }
1352
1353 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
1354 memset(tx_ring->tx_buffer_info, 0, size);
1355
1356 /* Zero out the descriptor ring */
1357 memset(tx_ring->desc, 0, tx_ring->size);
1358
1359 tx_ring->next_to_use = 0;
1360 tx_ring->next_to_clean = 0;
1361
1362 writel(0, adapter->hw.hw_addr + tx_ring->head);
1363 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1364}
1365
1366/**
1367 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
1368 * @adapter: board private structure
1369 **/
1370static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
1371{
1372 int i;
1373
1374 for (i = 0; i < adapter->num_tx_queues; i++)
1375 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1376}
1377
1378/**
1379 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
1380 * @adapter: board private structure
1381 **/
1382static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
1383{
1384 int i;
1385
1386 for (i = 0; i < adapter->num_rx_queues; i++)
1387 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1388}
1389
1390void ixgbe_down(struct ixgbe_adapter *adapter)
1391{
1392 struct net_device *netdev = adapter->netdev;
1393 u32 rxctrl;
1394
1395 /* signal that we are down to the interrupt handler */
1396 set_bit(__IXGBE_DOWN, &adapter->state);
1397
1398 /* disable receives */
1399 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1400 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL,
1401 rxctrl & ~IXGBE_RXCTRL_RXEN);
1402
1403 netif_tx_disable(netdev);
1404
1405 /* disable transmits in the hardware */
1406
1407 /* flush both disables */
1408 IXGBE_WRITE_FLUSH(&adapter->hw);
1409 msleep(10);
1410
1411 ixgbe_irq_disable(adapter);
1412
1413 napi_disable(&adapter->napi);
1414 del_timer_sync(&adapter->watchdog_timer);
1415
1416 netif_carrier_off(netdev);
1417 netif_stop_queue(netdev);
1418
1419 ixgbe_reset(adapter);
1420 ixgbe_clean_all_tx_rings(adapter);
1421 ixgbe_clean_all_rx_rings(adapter);
1422
1423}
1424
1425static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
1426{
1427 struct net_device *netdev = pci_get_drvdata(pdev);
1428 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1429#ifdef CONFIG_PM
1430 int retval = 0;
1431#endif
1432
1433 netif_device_detach(netdev);
1434
1435 if (netif_running(netdev)) {
1436 ixgbe_down(adapter);
1437 ixgbe_free_irq(adapter);
1438 }
1439
1440#ifdef CONFIG_PM
1441 retval = pci_save_state(pdev);
1442 if (retval)
1443 return retval;
1444#endif
1445
1446 pci_enable_wake(pdev, PCI_D3hot, 0);
1447 pci_enable_wake(pdev, PCI_D3cold, 0);
1448
1449 pci_disable_device(pdev);
1450
1451 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1452
1453 return 0;
1454}
1455
1456static void ixgbe_shutdown(struct pci_dev *pdev)
1457{
1458 ixgbe_suspend(pdev, PMSG_SUSPEND);
1459}
1460
1461/**
1462 * ixgbe_clean - NAPI Rx polling callback
1463 * @adapter: board private structure
1464 **/
1465static int ixgbe_clean(struct napi_struct *napi, int budget)
1466{
1467 struct ixgbe_adapter *adapter = container_of(napi,
1468 struct ixgbe_adapter, napi);
1469 struct net_device *netdev = adapter->netdev;
1470 int tx_cleaned = 0, work_done = 0;
1471
1472 /* Keep link state information with original netdev */
1473 if (!netif_carrier_ok(adapter->netdev))
1474 goto quit_polling;
1475
1476 /* In non-MSIX case, there is no multi-Tx/Rx queue */
1477 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
1478 ixgbe_clean_rx_irq(adapter, &adapter->rx_ring[0], &work_done,
1479 budget);
1480
1481 /* If no Tx and not enough Rx work done, exit the polling mode */
1482 if ((!tx_cleaned && (work_done < budget)) ||
1483 !netif_running(adapter->netdev)) {
1484quit_polling:
1485 netif_rx_complete(netdev, napi);
1486 ixgbe_irq_enable(adapter);
1487 }
1488
1489 return work_done;
1490}
1491
1492/**
1493 * ixgbe_tx_timeout - Respond to a Tx Hang
1494 * @netdev: network interface device structure
1495 **/
1496static void ixgbe_tx_timeout(struct net_device *netdev)
1497{
1498 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1499
1500 /* Do the reset outside of interrupt context */
1501 schedule_work(&adapter->reset_task);
1502}
1503
1504static void ixgbe_reset_task(struct work_struct *work)
1505{
1506 struct ixgbe_adapter *adapter;
1507 adapter = container_of(work, struct ixgbe_adapter, reset_task);
1508
1509 adapter->tx_timeout_count++;
1510
1511 ixgbe_down(adapter);
1512 ixgbe_up(adapter);
1513}
1514
1515/**
1516 * ixgbe_alloc_queues - Allocate memory for all rings
1517 * @adapter: board private structure to initialize
1518 *
1519 * We allocate one ring per queue at run-time since we don't know the
1520 * number of queues at compile-time. The polling_netdev array is
1521 * intended for Multiqueue, but should work fine with a single queue.
1522 **/
1523static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
1524{
1525 int i;
1526
1527 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
1528 sizeof(struct ixgbe_ring), GFP_KERNEL);
1529 if (!adapter->tx_ring)
1530 return -ENOMEM;
1531
1532 for (i = 0; i < adapter->num_tx_queues; i++)
1533 adapter->tx_ring[i].count = IXGBE_DEFAULT_TXD;
1534
1535 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
1536 sizeof(struct ixgbe_ring), GFP_KERNEL);
1537 if (!adapter->rx_ring) {
1538 kfree(adapter->tx_ring);
1539 return -ENOMEM;
1540 }
1541
1542 for (i = 0; i < adapter->num_rx_queues; i++) {
1543 adapter->rx_ring[i].adapter = adapter;
1544 adapter->rx_ring[i].itr_register = IXGBE_EITR(i);
1545 adapter->rx_ring[i].count = IXGBE_DEFAULT_RXD;
1546 }
1547
1548 return 0;
1549}
1550
1551/**
1552 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
1553 * @adapter: board private structure to initialize
1554 *
1555 * ixgbe_sw_init initializes the Adapter private data structure.
1556 * Fields are initialized based on PCI device information and
1557 * OS network device settings (MTU size).
1558 **/
1559static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
1560{
1561 struct ixgbe_hw *hw = &adapter->hw;
1562 struct pci_dev *pdev = adapter->pdev;
1563
1564 /* default flow control settings */
1565 hw->fc.original_type = ixgbe_fc_full;
1566 hw->fc.type = ixgbe_fc_full;
1567
1568 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
1569 if (hw->mac.ops.reset(hw)) {
1570 dev_err(&pdev->dev, "HW Init failed\n");
1571 return -EIO;
1572 }
1573 if (hw->phy.ops.setup_speed(hw, IXGBE_LINK_SPEED_10GB_FULL, true,
1574 false)) {
1575 dev_err(&pdev->dev, "Link Speed setup failed\n");
1576 return -EIO;
1577 }
1578
1579 /* initialize eeprom parameters */
1580 if (ixgbe_init_eeprom(hw)) {
1581 dev_err(&pdev->dev, "EEPROM initialization failed\n");
1582 return -EIO;
1583 }
1584
1585 /* Set the default values */
1586 adapter->num_rx_queues = IXGBE_DEFAULT_RXQ;
1587 adapter->num_tx_queues = 1;
1588 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
1589
1590 if (ixgbe_alloc_queues(adapter)) {
1591 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1592 return -ENOMEM;
1593 }
1594
1595 atomic_set(&adapter->irq_sem, 1);
1596 set_bit(__IXGBE_DOWN, &adapter->state);
1597
1598 return 0;
1599}
1600
1601/**
1602 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
1603 * @adapter: board private structure
1604 * @txdr: tx descriptor ring (for a specific queue) to setup
1605 *
1606 * Return 0 on success, negative on failure
1607 **/
1608int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
1609 struct ixgbe_ring *txdr)
1610{
1611 struct pci_dev *pdev = adapter->pdev;
1612 int size;
1613
1614 size = sizeof(struct ixgbe_tx_buffer) * txdr->count;
1615 txdr->tx_buffer_info = vmalloc(size);
1616 if (!txdr->tx_buffer_info) {
1617 DPRINTK(PROBE, ERR,
1618 "Unable to allocate memory for the transmit descriptor ring\n");
1619 return -ENOMEM;
1620 }
1621 memset(txdr->tx_buffer_info, 0, size);
1622
1623 /* round up to nearest 4K */
1624 txdr->size = txdr->count * sizeof(union ixgbe_adv_tx_desc);
1625 txdr->size = ALIGN(txdr->size, 4096);
1626
1627 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
1628 if (!txdr->desc) {
1629 vfree(txdr->tx_buffer_info);
1630 DPRINTK(PROBE, ERR,
1631 "Memory allocation failed for the tx desc ring\n");
1632 return -ENOMEM;
1633 }
1634
1635 txdr->adapter = adapter;
1636 txdr->next_to_use = 0;
1637 txdr->next_to_clean = 0;
1638 txdr->work_limit = txdr->count;
1639 spin_lock_init(&txdr->tx_lock);
1640
1641 return 0;
1642}
1643
1644/**
1645 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
1646 * @adapter: board private structure
1647 * @rxdr: rx descriptor ring (for a specific queue) to setup
1648 *
1649 * Returns 0 on success, negative on failure
1650 **/
1651int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
1652 struct ixgbe_ring *rxdr)
1653{
1654 struct pci_dev *pdev = adapter->pdev;
1655 int size, desc_len;
1656
1657 size = sizeof(struct ixgbe_rx_buffer) * rxdr->count;
1658 rxdr->rx_buffer_info = vmalloc(size);
1659 if (!rxdr->rx_buffer_info) {
1660 DPRINTK(PROBE, ERR,
1661 "vmalloc allocation failed for the rx desc ring\n");
1662 return -ENOMEM;
1663 }
1664 memset(rxdr->rx_buffer_info, 0, size);
1665
1666 desc_len = sizeof(union ixgbe_adv_rx_desc);
1667
1668 /* Round up to nearest 4K */
1669 rxdr->size = rxdr->count * desc_len;
1670 rxdr->size = ALIGN(rxdr->size, 4096);
1671
1672 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1673
1674 if (!rxdr->desc) {
1675 DPRINTK(PROBE, ERR,
1676 "Memory allocation failed for the rx desc ring\n");
1677 vfree(rxdr->rx_buffer_info);
1678 return -ENOMEM;
1679 }
1680
1681 rxdr->next_to_clean = 0;
1682 rxdr->next_to_use = 0;
1683 rxdr->adapter = adapter;
1684
1685 return 0;
1686}
1687
1688/**
1689 * ixgbe_free_tx_resources - Free Tx Resources per Queue
1690 * @adapter: board private structure
1691 * @tx_ring: Tx descriptor ring for a specific queue
1692 *
1693 * Free all transmit software resources
1694 **/
1695static void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
1696 struct ixgbe_ring *tx_ring)
1697{
1698 struct pci_dev *pdev = adapter->pdev;
1699
1700 ixgbe_clean_tx_ring(adapter, tx_ring);
1701
1702 vfree(tx_ring->tx_buffer_info);
1703 tx_ring->tx_buffer_info = NULL;
1704
1705 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1706
1707 tx_ring->desc = NULL;
1708}
1709
1710/**
1711 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
1712 * @adapter: board private structure
1713 *
1714 * Free all transmit software resources
1715 **/
1716static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
1717{
1718 int i;
1719
1720 for (i = 0; i < adapter->num_tx_queues; i++)
1721 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
1722}
1723
1724/**
1725 * ixgbe_free_rx_resources - Free Rx Resources
1726 * @adapter: board private structure
1727 * @rx_ring: ring to clean the resources from
1728 *
1729 * Free all receive software resources
1730 **/
1731static void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
1732 struct ixgbe_ring *rx_ring)
1733{
1734 struct pci_dev *pdev = adapter->pdev;
1735
1736 ixgbe_clean_rx_ring(adapter, rx_ring);
1737
1738 vfree(rx_ring->rx_buffer_info);
1739 rx_ring->rx_buffer_info = NULL;
1740
1741 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1742
1743 rx_ring->desc = NULL;
1744}
1745
1746/**
1747 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
1748 * @adapter: board private structure
1749 *
1750 * Free all receive software resources
1751 **/
1752static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
1753{
1754 int i;
1755
1756 for (i = 0; i < adapter->num_rx_queues; i++)
1757 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
1758}
1759
1760/**
1761 * ixgbe_setup_all_tx_resources - wrapper to allocate Tx resources
1762 * (Descriptors) for all queues
1763 * @adapter: board private structure
1764 *
1765 * If this function returns with an error, then it's possible one or
1766 * more of the rings is populated (while the rest are not). It is the
1767 * callers duty to clean those orphaned rings.
1768 *
1769 * Return 0 on success, negative on failure
1770 **/
1771static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
1772{
1773 int i, err = 0;
1774
1775 for (i = 0; i < adapter->num_tx_queues; i++) {
1776 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1777 if (err) {
1778 DPRINTK(PROBE, ERR,
1779 "Allocation for Tx Queue %u failed\n", i);
1780 break;
1781 }
1782 }
1783
1784 return err;
1785}
1786
1787/**
1788 * ixgbe_setup_all_rx_resources - wrapper to allocate Rx resources
1789 * (Descriptors) for all queues
1790 * @adapter: board private structure
1791 *
1792 * If this function returns with an error, then it's possible one or
1793 * more of the rings is populated (while the rest are not). It is the
1794 * callers duty to clean those orphaned rings.
1795 *
1796 * Return 0 on success, negative on failure
1797 **/
1798
1799static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
1800{
1801 int i, err = 0;
1802
1803 for (i = 0; i < adapter->num_rx_queues; i++) {
1804 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1805 if (err) {
1806 DPRINTK(PROBE, ERR,
1807 "Allocation for Rx Queue %u failed\n", i);
1808 break;
1809 }
1810 }
1811
1812 return err;
1813}
1814
1815/**
1816 * ixgbe_change_mtu - Change the Maximum Transfer Unit
1817 * @netdev: network interface device structure
1818 * @new_mtu: new value for maximum frame size
1819 *
1820 * Returns 0 on success, negative on failure
1821 **/
1822static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
1823{
1824 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1825 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
1826
1827 if ((max_frame < (ETH_ZLEN + ETH_FCS_LEN)) ||
1828 (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
1829 return -EINVAL;
1830
1831 netdev->mtu = new_mtu;
1832
1833 if (netif_running(netdev)) {
1834 ixgbe_down(adapter);
1835 ixgbe_up(adapter);
1836 }
1837
1838 return 0;
1839}
1840
1841/**
1842 * ixgbe_open - Called when a network interface is made active
1843 * @netdev: network interface device structure
1844 *
1845 * Returns 0 on success, negative value on failure
1846 *
1847 * The open entry point is called when a network interface is made
1848 * active by the system (IFF_UP). At this point all resources needed
1849 * for transmit and receive operations are allocated, the interrupt
1850 * handler is registered with the OS, the watchdog timer is started,
1851 * and the stack is notified that the interface is ready.
1852 **/
1853static int ixgbe_open(struct net_device *netdev)
1854{
1855 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1856 int err;
1857 u32 ctrl_ext;
1858 u32 num_rx_queues = adapter->num_rx_queues;
1859
1860 /* Let firmware know the driver has taken over */
1861 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
1862 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
1863 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
1864
1865try_intr_reinit:
1866 /* allocate transmit descriptors */
1867 err = ixgbe_setup_all_tx_resources(adapter);
1868 if (err)
1869 goto err_setup_tx;
1870
1871 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1872 num_rx_queues = 1;
1873 adapter->num_rx_queues = num_rx_queues;
1874 }
1875
1876 /* allocate receive descriptors */
1877 err = ixgbe_setup_all_rx_resources(adapter);
1878 if (err)
1879 goto err_setup_rx;
1880
1881 ixgbe_configure(adapter);
1882
1883 err = ixgbe_request_irq(adapter, &num_rx_queues);
1884 if (err)
1885 goto err_req_irq;
1886
1887 /* ixgbe_request might have reduced num_rx_queues */
1888 if (num_rx_queues < adapter->num_rx_queues) {
1889 /* We didn't get MSI-X, so we need to release everything,
1890 * set our Rx queue count to num_rx_queues, and redo the
1891 * whole init process.
1892 */
1893 ixgbe_free_irq(adapter);
1894 if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1895 pci_disable_msi(adapter->pdev);
1896 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
1897 }
1898 ixgbe_free_all_rx_resources(adapter);
1899 ixgbe_free_all_tx_resources(adapter);
1900 adapter->num_rx_queues = num_rx_queues;
1901
1902 /* Reset the hardware, and start over. */
1903 ixgbe_reset(adapter);
1904
1905 goto try_intr_reinit;
1906 }
1907
1908 err = ixgbe_up_complete(adapter);
1909 if (err)
1910 goto err_up;
1911
1912 return 0;
1913
1914err_up:
1915 ixgbe_free_irq(adapter);
1916err_req_irq:
1917 ixgbe_free_all_rx_resources(adapter);
1918err_setup_rx:
1919 ixgbe_free_all_tx_resources(adapter);
1920err_setup_tx:
1921 ixgbe_reset(adapter);
1922
1923 return err;
1924}
1925
1926/**
1927 * ixgbe_close - Disables a network interface
1928 * @netdev: network interface device structure
1929 *
1930 * Returns 0, this is not allowed to fail
1931 *
1932 * The close entry point is called when an interface is de-activated
1933 * by the OS. The hardware is still under the drivers control, but
1934 * needs to be disabled. A global MAC reset is issued to stop the
1935 * hardware, and all transmit and receive resources are freed.
1936 **/
1937static int ixgbe_close(struct net_device *netdev)
1938{
1939 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1940 u32 ctrl_ext;
1941
1942 ixgbe_down(adapter);
1943 ixgbe_free_irq(adapter);
1944
1945 ixgbe_free_all_tx_resources(adapter);
1946 ixgbe_free_all_rx_resources(adapter);
1947
1948 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
1949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
1950 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
1951
1952 return 0;
1953}
1954
1955/**
1956 * ixgbe_update_stats - Update the board statistics counters.
1957 * @adapter: board private structure
1958 **/
1959void ixgbe_update_stats(struct ixgbe_adapter *adapter)
1960{
1961 struct ixgbe_hw *hw = &adapter->hw;
1962 u64 good_rx, missed_rx, bprc;
1963
1964 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1965 good_rx = IXGBE_READ_REG(hw, IXGBE_GPRC);
1966 missed_rx = IXGBE_READ_REG(hw, IXGBE_MPC(0));
1967 missed_rx += IXGBE_READ_REG(hw, IXGBE_MPC(1));
1968 missed_rx += IXGBE_READ_REG(hw, IXGBE_MPC(2));
1969 missed_rx += IXGBE_READ_REG(hw, IXGBE_MPC(3));
1970 missed_rx += IXGBE_READ_REG(hw, IXGBE_MPC(4));
1971 missed_rx += IXGBE_READ_REG(hw, IXGBE_MPC(5));
1972 missed_rx += IXGBE_READ_REG(hw, IXGBE_MPC(6));
1973 missed_rx += IXGBE_READ_REG(hw, IXGBE_MPC(7));
1974 adapter->stats.gprc += (good_rx - missed_rx);
1975
1976 adapter->stats.mpc[0] += missed_rx;
1977 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1978 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1979 adapter->stats.bprc += bprc;
1980 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1981 adapter->stats.mprc -= bprc;
1982 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1983 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1984 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1985 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1986 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1987 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1988 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1989
1990 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1991 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1992 adapter->stats.lxontxc += IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1993 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1994 adapter->stats.lxofftxc += IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1995 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1996 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1997 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1998 adapter->stats.rnbc[0] += IXGBE_READ_REG(hw, IXGBE_RNBC(0));
1999 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2000 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2001 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2002 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2003 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2004 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2005 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2006 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2007 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2008 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2009 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2010 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2011 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2012
2013 /* Fill out the OS statistics structure */
2014 adapter->net_stats.rx_packets = adapter->stats.gprc;
2015 adapter->net_stats.tx_packets = adapter->stats.gptc;
2016 adapter->net_stats.rx_bytes = adapter->stats.gorc;
2017 adapter->net_stats.tx_bytes = adapter->stats.gotc;
2018 adapter->net_stats.multicast = adapter->stats.mprc;
2019
2020 /* Rx Errors */
2021 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
2022 adapter->stats.rlec;
2023 adapter->net_stats.rx_dropped = 0;
2024 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
2025 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
2026 adapter->net_stats.rx_missed_errors = adapter->stats.mpc[0];
2027
2028}
2029
2030/**
2031 * ixgbe_watchdog - Timer Call-back
2032 * @data: pointer to adapter cast into an unsigned long
2033 **/
2034static void ixgbe_watchdog(unsigned long data)
2035{
2036 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2037 struct net_device *netdev = adapter->netdev;
2038 bool link_up;
2039 u32 link_speed = 0;
2040
2041 adapter->hw.phy.ops.check(&adapter->hw, &(link_speed), &link_up);
2042
2043 if (link_up) {
2044 if (!netif_carrier_ok(netdev)) {
2045 u32 frctl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2046 u32 rmcs = IXGBE_READ_REG(&adapter->hw, IXGBE_RMCS);
2047#define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
2048#define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
2049 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
2050 "Flow Control: %s\n",
2051 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
2052 "10 Gbps" :
2053 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
2054 "1 Gpbs" : "unknown speed")),
2055 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
2056 (FLOW_RX ? "RX" :
2057 (FLOW_TX ? "TX" : "None"))));
2058
2059 netif_carrier_on(netdev);
2060 netif_wake_queue(netdev);
2061 } else {
2062 /* Force detection of hung controller */
2063 adapter->detect_tx_hung = true;
2064 }
2065 } else {
2066 if (netif_carrier_ok(netdev)) {
2067 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2068 netif_carrier_off(netdev);
2069 netif_stop_queue(netdev);
2070 }
2071 }
2072
2073 ixgbe_update_stats(adapter);
2074
2075 /* Reset the timer */
2076 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2077 mod_timer(&adapter->watchdog_timer,
2078 round_jiffies(jiffies + 2 * HZ));
2079}
2080
2081#define IXGBE_MAX_TXD_PWR 14
2082#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
2083
2084/* Tx Descriptors needed, worst case */
2085#define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
2086 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
2087#define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
2088 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
2089
2090static int ixgbe_tso(struct ixgbe_adapter *adapter,
2091 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
2092 u32 tx_flags, u8 *hdr_len)
2093{
2094 struct ixgbe_adv_tx_context_desc *context_desc;
2095 unsigned int i;
2096 int err;
2097 struct ixgbe_tx_buffer *tx_buffer_info;
2098 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
2099 u32 mss_l4len_idx = 0, l4len;
2100 *hdr_len = 0;
2101
2102 if (skb_is_gso(skb)) {
2103 if (skb_header_cloned(skb)) {
2104 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2105 if (err)
2106 return err;
2107 }
2108 l4len = tcp_hdrlen(skb);
2109 *hdr_len += l4len;
2110
2111 if (skb->protocol == ntohs(ETH_P_IP)) {
2112 struct iphdr *iph = ip_hdr(skb);
2113 iph->tot_len = 0;
2114 iph->check = 0;
2115 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2116 iph->daddr, 0,
2117 IPPROTO_TCP,
2118 0);
2119 adapter->hw_tso_ctxt++;
2120 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2121 ipv6_hdr(skb)->payload_len = 0;
2122 tcp_hdr(skb)->check =
2123 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2124 &ipv6_hdr(skb)->daddr,
2125 0, IPPROTO_TCP, 0);
2126 adapter->hw_tso6_ctxt++;
2127 }
2128
2129 i = tx_ring->next_to_use;
2130
2131 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2132 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
2133
2134 /* VLAN MACLEN IPLEN */
2135 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2136 vlan_macip_lens |=
2137 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
2138 vlan_macip_lens |= ((skb_network_offset(skb)) <<
2139 IXGBE_ADVTXD_MACLEN_SHIFT);
2140 *hdr_len += skb_network_offset(skb);
2141 vlan_macip_lens |=
2142 (skb_transport_header(skb) - skb_network_header(skb));
2143 *hdr_len +=
2144 (skb_transport_header(skb) - skb_network_header(skb));
2145 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2146 context_desc->seqnum_seed = 0;
2147
2148 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2149 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
2150 IXGBE_ADVTXD_DTYP_CTXT);
2151
2152 if (skb->protocol == ntohs(ETH_P_IP))
2153 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
2154 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
2155 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
2156
2157 /* MSS L4LEN IDX */
2158 mss_l4len_idx |=
2159 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
2160 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
2161 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2162
2163 tx_buffer_info->time_stamp = jiffies;
2164 tx_buffer_info->next_to_watch = i;
2165
2166 i++;
2167 if (i == tx_ring->count)
2168 i = 0;
2169 tx_ring->next_to_use = i;
2170
2171 return true;
2172 }
2173 return false;
2174}
2175
2176static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
2177 struct ixgbe_ring *tx_ring,
2178 struct sk_buff *skb, u32 tx_flags)
2179{
2180 struct ixgbe_adv_tx_context_desc *context_desc;
2181 unsigned int i;
2182 struct ixgbe_tx_buffer *tx_buffer_info;
2183 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
2184
2185 if (skb->ip_summed == CHECKSUM_PARTIAL ||
2186 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
2187 i = tx_ring->next_to_use;
2188 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2189 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
2190
2191 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2192 vlan_macip_lens |=
2193 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
2194 vlan_macip_lens |= (skb_network_offset(skb) <<
2195 IXGBE_ADVTXD_MACLEN_SHIFT);
2196 if (skb->ip_summed == CHECKSUM_PARTIAL)
2197 vlan_macip_lens |= (skb_transport_header(skb) -
2198 skb_network_header(skb));
2199
2200 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
2201 context_desc->seqnum_seed = 0;
2202
2203 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
2204 IXGBE_ADVTXD_DTYP_CTXT);
2205
2206 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2207 if (skb->protocol == ntohs(ETH_P_IP))
2208 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
2209
2210 if (skb->sk->sk_protocol == IPPROTO_TCP)
2211 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
2212 }
2213
2214 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
2215 context_desc->mss_l4len_idx = 0;
2216
2217 tx_buffer_info->time_stamp = jiffies;
2218 tx_buffer_info->next_to_watch = i;
2219 adapter->hw_csum_tx_good++;
2220 i++;
2221 if (i == tx_ring->count)
2222 i = 0;
2223 tx_ring->next_to_use = i;
2224
2225 return true;
2226 }
2227 return false;
2228}
2229
2230static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
2231 struct ixgbe_ring *tx_ring,
2232 struct sk_buff *skb, unsigned int first)
2233{
2234 struct ixgbe_tx_buffer *tx_buffer_info;
2235 unsigned int len = skb->len;
2236 unsigned int offset = 0, size, count = 0, i;
2237 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
2238 unsigned int f;
2239
2240 len -= skb->data_len;
2241
2242 i = tx_ring->next_to_use;
2243
2244 while (len) {
2245 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2246 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
2247
2248 tx_buffer_info->length = size;
2249 tx_buffer_info->dma = pci_map_single(adapter->pdev,
2250 skb->data + offset,
2251 size, PCI_DMA_TODEVICE);
2252 tx_buffer_info->time_stamp = jiffies;
2253 tx_buffer_info->next_to_watch = i;
2254
2255 len -= size;
2256 offset += size;
2257 count++;
2258 i++;
2259 if (i == tx_ring->count)
2260 i = 0;
2261 }
2262
2263 for (f = 0; f < nr_frags; f++) {
2264 struct skb_frag_struct *frag;
2265
2266 frag = &skb_shinfo(skb)->frags[f];
2267 len = frag->size;
2268 offset = frag->page_offset;
2269
2270 while (len) {
2271 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2272 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
2273
2274 tx_buffer_info->length = size;
2275 tx_buffer_info->dma = pci_map_page(adapter->pdev,
2276 frag->page,
2277 offset,
2278 size, PCI_DMA_TODEVICE);
2279 tx_buffer_info->time_stamp = jiffies;
2280 tx_buffer_info->next_to_watch = i;
2281
2282 len -= size;
2283 offset += size;
2284 count++;
2285 i++;
2286 if (i == tx_ring->count)
2287 i = 0;
2288 }
2289 }
2290 if (i == 0)
2291 i = tx_ring->count - 1;
2292 else
2293 i = i - 1;
2294 tx_ring->tx_buffer_info[i].skb = skb;
2295 tx_ring->tx_buffer_info[first].next_to_watch = i;
2296
2297 return count;
2298}
2299
2300static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
2301 struct ixgbe_ring *tx_ring,
2302 int tx_flags, int count, u32 paylen, u8 hdr_len)
2303{
2304 union ixgbe_adv_tx_desc *tx_desc = NULL;
2305 struct ixgbe_tx_buffer *tx_buffer_info;
2306 u32 olinfo_status = 0, cmd_type_len = 0;
2307 unsigned int i;
2308 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
2309
2310 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
2311
2312 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
2313
2314 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
2315 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
2316
2317 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
2318 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
2319
2320 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
2321 IXGBE_ADVTXD_POPTS_SHIFT;
2322
2323 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
2324 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
2325 IXGBE_ADVTXD_POPTS_SHIFT;
2326
2327 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
2328 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
2329 IXGBE_ADVTXD_POPTS_SHIFT;
2330
2331 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
2332
2333 i = tx_ring->next_to_use;
2334 while (count--) {
2335 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2336 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
2337 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
2338 tx_desc->read.cmd_type_len =
2339 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
2340 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2341
2342 i++;
2343 if (i == tx_ring->count)
2344 i = 0;
2345 }
2346
2347 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
2348
2349 /*
2350 * Force memory writes to complete before letting h/w
2351 * know there are new descriptors to fetch. (Only
2352 * applicable for weak-ordered memory model archs,
2353 * such as IA-64).
2354 */
2355 wmb();
2356
2357 tx_ring->next_to_use = i;
2358 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2359}
2360
2361static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2362{
2363 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2364 struct ixgbe_ring *tx_ring;
2365 unsigned int len = skb->len;
2366 unsigned int first;
2367 unsigned int tx_flags = 0;
2368 unsigned long flags = 0;
2369 u8 hdr_len;
2370 int tso;
2371 unsigned int mss = 0;
2372 int count = 0;
2373 unsigned int f;
2374 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
2375 len -= skb->data_len;
2376
2377 tx_ring = adapter->tx_ring;
2378
2379 if (skb->len <= 0) {
2380 dev_kfree_skb(skb);
2381 return NETDEV_TX_OK;
2382 }
2383 mss = skb_shinfo(skb)->gso_size;
2384
2385 if (mss)
2386 count++;
2387 else if (skb->ip_summed == CHECKSUM_PARTIAL)
2388 count++;
2389
2390 count += TXD_USE_COUNT(len);
2391 for (f = 0; f < nr_frags; f++)
2392 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
2393
2394 spin_lock_irqsave(&tx_ring->tx_lock, flags);
2395 if (IXGBE_DESC_UNUSED(tx_ring) < (count + 2)) {
2396 adapter->tx_busy++;
2397 netif_stop_queue(netdev);
2398 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2399 return NETDEV_TX_BUSY;
2400 }
2401 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2402 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2403 tx_flags |= IXGBE_TX_FLAGS_VLAN;
2404 tx_flags |= (vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT);
2405 }
2406
2407 if (skb->protocol == ntohs(ETH_P_IP))
2408 tx_flags |= IXGBE_TX_FLAGS_IPV4;
2409 first = tx_ring->next_to_use;
2410 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
2411 if (tso < 0) {
2412 dev_kfree_skb_any(skb);
2413 return NETDEV_TX_OK;
2414 }
2415
2416 if (tso)
2417 tx_flags |= IXGBE_TX_FLAGS_TSO;
2418 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
2419 (skb->ip_summed == CHECKSUM_PARTIAL))
2420 tx_flags |= IXGBE_TX_FLAGS_CSUM;
2421
2422 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
2423 ixgbe_tx_map(adapter, tx_ring, skb, first),
2424 skb->len, hdr_len);
2425
2426 netdev->trans_start = jiffies;
2427
2428 spin_lock_irqsave(&tx_ring->tx_lock, flags);
2429 /* Make sure there is space in the ring for the next send. */
2430 if (IXGBE_DESC_UNUSED(tx_ring) < DESC_NEEDED)
2431 netif_stop_queue(netdev);
2432 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2433
2434 return NETDEV_TX_OK;
2435}
2436
2437/**
2438 * ixgbe_get_stats - Get System Network Statistics
2439 * @netdev: network interface device structure
2440 *
2441 * Returns the address of the device statistics structure.
2442 * The statistics are actually updated from the timer callback.
2443 **/
2444static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
2445{
2446 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2447
2448 /* only return the current stats */
2449 return &adapter->net_stats;
2450}
2451
2452/**
2453 * ixgbe_set_mac - Change the Ethernet Address of the NIC
2454 * @netdev: network interface device structure
2455 * @p: pointer to an address structure
2456 *
2457 * Returns 0 on success, negative on failure
2458 **/
2459static int ixgbe_set_mac(struct net_device *netdev, void *p)
2460{
2461 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2462 struct sockaddr *addr = p;
2463
2464 if (!is_valid_ether_addr(addr->sa_data))
2465 return -EADDRNOTAVAIL;
2466
2467 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2468 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2469
2470 ixgbe_set_rar(&adapter->hw, 0, adapter->hw.mac.addr, 0, IXGBE_RAH_AV);
2471
2472 return 0;
2473}
2474
2475#ifdef CONFIG_NET_POLL_CONTROLLER
2476/*
2477 * Polling 'interrupt' - used by things like netconsole to send skbs
2478 * without having to re-enable interrupts. It's not called while
2479 * the interrupt routine is executing.
2480 */
2481static void ixgbe_netpoll(struct net_device *netdev)
2482{
2483 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2484
2485 disable_irq(adapter->pdev->irq);
2486 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
2487 ixgbe_intr(adapter->pdev->irq, netdev);
2488 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
2489 enable_irq(adapter->pdev->irq);
2490}
2491#endif
2492
2493/**
2494 * ixgbe_probe - Device Initialization Routine
2495 * @pdev: PCI device information struct
2496 * @ent: entry in ixgbe_pci_tbl
2497 *
2498 * Returns 0 on success, negative on failure
2499 *
2500 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
2501 * The OS initialization, configuring of the adapter private structure,
2502 * and a hardware reset occur.
2503 **/
2504static int __devinit ixgbe_probe(struct pci_dev *pdev,
2505 const struct pci_device_id *ent)
2506{
2507 struct net_device *netdev;
2508 struct ixgbe_adapter *adapter = NULL;
2509 struct ixgbe_hw *hw;
2510 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
2511 unsigned long mmio_start, mmio_len;
2512 static int cards_found;
2513 int i, err, pci_using_dac;
2514 u16 link_status, link_speed, link_width;
2515 u32 part_num;
2516
2517 err = pci_enable_device(pdev);
2518 if (err)
2519 return err;
2520
2521 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
2522 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
2523 pci_using_dac = 1;
2524 } else {
2525 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2526 if (err) {
2527 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2528 if (err) {
2529 dev_err(&pdev->dev, "No usable DMA "
2530 "configuration, aborting\n");
2531 goto err_dma;
2532 }
2533 }
2534 pci_using_dac = 0;
2535 }
2536
2537 err = pci_request_regions(pdev, ixgbe_driver_name);
2538 if (err) {
2539 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
2540 goto err_pci_reg;
2541 }
2542
2543 pci_set_master(pdev);
2544
2545 netdev = alloc_etherdev(sizeof(struct ixgbe_adapter));
2546 if (!netdev) {
2547 err = -ENOMEM;
2548 goto err_alloc_etherdev;
2549 }
2550
2551 SET_MODULE_OWNER(netdev);
2552 SET_NETDEV_DEV(netdev, &pdev->dev);
2553
2554 pci_set_drvdata(pdev, netdev);
2555 adapter = netdev_priv(netdev);
2556
2557 adapter->netdev = netdev;
2558 adapter->pdev = pdev;
2559 hw = &adapter->hw;
2560 hw->back = adapter;
2561 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
2562
2563 mmio_start = pci_resource_start(pdev, 0);
2564 mmio_len = pci_resource_len(pdev, 0);
2565
2566 hw->hw_addr = ioremap(mmio_start, mmio_len);
2567 if (!hw->hw_addr) {
2568 err = -EIO;
2569 goto err_ioremap;
2570 }
2571
2572 for (i = 1; i <= 5; i++) {
2573 if (pci_resource_len(pdev, i) == 0)
2574 continue;
2575 }
2576
2577 netdev->open = &ixgbe_open;
2578 netdev->stop = &ixgbe_close;
2579 netdev->hard_start_xmit = &ixgbe_xmit_frame;
2580 netdev->get_stats = &ixgbe_get_stats;
2581 netdev->set_multicast_list = &ixgbe_set_multi;
2582 netdev->set_mac_address = &ixgbe_set_mac;
2583 netdev->change_mtu = &ixgbe_change_mtu;
2584 ixgbe_set_ethtool_ops(netdev);
2585 netdev->tx_timeout = &ixgbe_tx_timeout;
2586 netdev->watchdog_timeo = 5 * HZ;
2587 netif_napi_add(netdev, &adapter->napi, ixgbe_clean, 64);
2588 netdev->vlan_rx_register = ixgbe_vlan_rx_register;
2589 netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid;
2590 netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid;
2591#ifdef CONFIG_NET_POLL_CONTROLLER
2592 netdev->poll_controller = ixgbe_netpoll;
2593#endif
2594 strcpy(netdev->name, pci_name(pdev));
2595
2596 netdev->mem_start = mmio_start;
2597 netdev->mem_end = mmio_start + mmio_len;
2598
2599 adapter->bd_number = cards_found;
2600
2601 /* PCI config space info */
2602 hw->vendor_id = pdev->vendor;
2603 hw->device_id = pdev->device;
2604 hw->revision_id = pdev->revision;
2605 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2606 hw->subsystem_device_id = pdev->subsystem_device;
2607
2608 /* Setup hw api */
2609 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
2610 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
2611
2612 err = ii->get_invariants(hw);
2613 if (err)
2614 goto err_hw_init;
2615
2616 /* setup the private structure */
2617 err = ixgbe_sw_init(adapter);
2618 if (err)
2619 goto err_sw_init;
2620
2621 netdev->features = NETIF_F_SG |
2622 NETIF_F_HW_CSUM |
2623 NETIF_F_HW_VLAN_TX |
2624 NETIF_F_HW_VLAN_RX |
2625 NETIF_F_HW_VLAN_FILTER;
2626
2627 netdev->features |= NETIF_F_TSO;
2628
2629 netdev->features |= NETIF_F_TSO6;
2630 if (pci_using_dac)
2631 netdev->features |= NETIF_F_HIGHDMA;
2632
2633
2634 /* make sure the EEPROM is good */
2635 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
2636 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
2637 err = -EIO;
2638 goto err_eeprom;
2639 }
2640
2641 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
2642 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
2643
2644 if (ixgbe_validate_mac_addr(netdev->dev_addr)) {
2645 err = -EIO;
2646 goto err_eeprom;
2647 }
2648
2649 init_timer(&adapter->watchdog_timer);
2650 adapter->watchdog_timer.function = &ixgbe_watchdog;
2651 adapter->watchdog_timer.data = (unsigned long)adapter;
2652
2653 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
2654
2655 /* initialize default flow control settings */
2656 hw->fc.original_type = ixgbe_fc_full;
2657 hw->fc.type = ixgbe_fc_full;
2658 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2659 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2660 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2661
2662 /* Interrupt Throttle Rate */
2663 adapter->rx_eitr = (1000000 / IXGBE_DEFAULT_ITR_RX_USECS);
2664 adapter->tx_eitr = (1000000 / IXGBE_DEFAULT_ITR_TX_USECS);
2665
2666 /* print bus type/speed/width info */
2667 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
2668 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
2669 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
2670 dev_info(&pdev->dev, "(PCI Express:%s:%s) "
2671 "%02x:%02x:%02x:%02x:%02x:%02x\n",
2672 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
2673 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
2674 "Unknown"),
2675 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
2676 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
2677 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
2678 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
2679 "Unknown"),
2680 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
2681 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
2682 ixgbe_read_part_num(hw, &part_num);
2683 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
2684 hw->mac.type, hw->phy.type,
2685 (part_num >> 8), (part_num & 0xff));
2686
2687 /* reset the hardware with the new settings */
2688 ixgbe_start_hw(hw);
2689
2690 netif_carrier_off(netdev);
2691 netif_stop_queue(netdev);
2692
2693 strcpy(netdev->name, "eth%d");
2694 err = register_netdev(netdev);
2695 if (err)
2696 goto err_register;
2697
2698
2699 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
2700 cards_found++;
2701 return 0;
2702
2703err_register:
2704err_hw_init:
2705err_sw_init:
2706err_eeprom:
2707 iounmap(hw->hw_addr);
2708err_ioremap:
2709 free_netdev(netdev);
2710err_alloc_etherdev:
2711 pci_release_regions(pdev);
2712err_pci_reg:
2713err_dma:
2714 pci_disable_device(pdev);
2715 return err;
2716}
2717
2718/**
2719 * ixgbe_remove - Device Removal Routine
2720 * @pdev: PCI device information struct
2721 *
2722 * ixgbe_remove is called by the PCI subsystem to alert the driver
2723 * that it should release a PCI device. The could be caused by a
2724 * Hot-Plug event, or because the driver is going to be removed from
2725 * memory.
2726 **/
2727static void __devexit ixgbe_remove(struct pci_dev *pdev)
2728{
2729 struct net_device *netdev = pci_get_drvdata(pdev);
2730 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2731
2732 set_bit(__IXGBE_DOWN, &adapter->state);
2733 del_timer_sync(&adapter->watchdog_timer);
2734
2735 flush_scheduled_work();
2736
2737 unregister_netdev(netdev);
2738
2739 kfree(adapter->tx_ring);
2740 kfree(adapter->rx_ring);
2741
2742 iounmap(adapter->hw.hw_addr);
2743 pci_release_regions(pdev);
2744
2745 free_netdev(netdev);
2746
2747 pci_disable_device(pdev);
2748}
2749
2750/**
2751 * ixgbe_io_error_detected - called when PCI error is detected
2752 * @pdev: Pointer to PCI device
2753 * @state: The current pci connection state
2754 *
2755 * This function is called after a PCI bus error affecting
2756 * this device has been detected.
2757 */
2758static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
2759 pci_channel_state_t state)
2760{
2761 struct net_device *netdev = pci_get_drvdata(pdev);
2762 struct ixgbe_adapter *adapter = netdev->priv;
2763
2764 netif_device_detach(netdev);
2765
2766 if (netif_running(netdev))
2767 ixgbe_down(adapter);
2768 pci_disable_device(pdev);
2769
2770 /* Request a slot slot reset. */
2771 return PCI_ERS_RESULT_NEED_RESET;
2772}
2773
2774/**
2775 * ixgbe_io_slot_reset - called after the pci bus has been reset.
2776 * @pdev: Pointer to PCI device
2777 *
2778 * Restart the card from scratch, as if from a cold-boot.
2779 */
2780static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
2781{
2782 struct net_device *netdev = pci_get_drvdata(pdev);
2783 struct ixgbe_adapter *adapter = netdev->priv;
2784
2785 if (pci_enable_device(pdev)) {
2786 DPRINTK(PROBE, ERR,
2787 "Cannot re-enable PCI device after reset.\n");
2788 return PCI_ERS_RESULT_DISCONNECT;
2789 }
2790 pci_set_master(pdev);
2791
2792 pci_enable_wake(pdev, PCI_D3hot, 0);
2793 pci_enable_wake(pdev, PCI_D3cold, 0);
2794
2795 ixgbe_reset(adapter);
2796
2797 return PCI_ERS_RESULT_RECOVERED;
2798}
2799
2800/**
2801 * ixgbe_io_resume - called when traffic can start flowing again.
2802 * @pdev: Pointer to PCI device
2803 *
2804 * This callback is called when the error recovery driver tells us that
2805 * its OK to resume normal operation.
2806 */
2807static void ixgbe_io_resume(struct pci_dev *pdev)
2808{
2809 struct net_device *netdev = pci_get_drvdata(pdev);
2810 struct ixgbe_adapter *adapter = netdev->priv;
2811
2812 if (netif_running(netdev)) {
2813 if (ixgbe_up(adapter)) {
2814 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
2815 return;
2816 }
2817 }
2818
2819 netif_device_attach(netdev);
2820
2821}
2822
2823static struct pci_error_handlers ixgbe_err_handler = {
2824 .error_detected = ixgbe_io_error_detected,
2825 .slot_reset = ixgbe_io_slot_reset,
2826 .resume = ixgbe_io_resume,
2827};
2828
2829static struct pci_driver ixgbe_driver = {
2830 .name = ixgbe_driver_name,
2831 .id_table = ixgbe_pci_tbl,
2832 .probe = ixgbe_probe,
2833 .remove = __devexit_p(ixgbe_remove),
2834#ifdef CONFIG_PM
2835 .suspend = ixgbe_suspend,
2836 .resume = ixgbe_resume,
2837#endif
2838 .shutdown = ixgbe_shutdown,
2839 .err_handler = &ixgbe_err_handler
2840};
2841
2842/**
2843 * ixgbe_init_module - Driver Registration Routine
2844 *
2845 * ixgbe_init_module is the first routine called when the driver is
2846 * loaded. All it does is register with the PCI subsystem.
2847 **/
2848static int __init ixgbe_init_module(void)
2849{
2850 int ret;
2851 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
2852 ixgbe_driver_string, ixgbe_driver_version);
2853
2854 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
2855
2856 ret = pci_register_driver(&ixgbe_driver);
2857 return ret;
2858}
2859module_init(ixgbe_init_module);
2860
2861/**
2862 * ixgbe_exit_module - Driver Exit Cleanup Routine
2863 *
2864 * ixgbe_exit_module is called just before the driver is removed
2865 * from memory.
2866 **/
2867static void __exit ixgbe_exit_module(void)
2868{
2869 pci_unregister_driver(&ixgbe_driver);
2870}
2871module_exit(ixgbe_exit_module);
2872
2873/* ixgbe_main.c */
diff --git a/drivers/net/ixgbe/ixgbe_phy.c b/drivers/net/ixgbe/ixgbe_phy.c
new file mode 100644
index 000000000000..8002931ae823
--- /dev/null
+++ b/drivers/net/ixgbe/ixgbe_phy.c
@@ -0,0 +1,494 @@
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
33#include "ixgbe_common.h"
34#include "ixgbe_phy.h"
35
36static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
37static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
38static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
39static s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr,
40 u32 device_type, u16 phy_data);
41
42/**
43 * ixgbe_identify_phy - Get physical layer module
44 * @hw: pointer to hardware structure
45 *
46 * Determines the physical layer module found on the current adapter.
47 **/
48s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
49{
50 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
51 u32 phy_addr;
52
53 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
54 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
55 hw->phy.addr = phy_addr;
56 ixgbe_get_phy_id(hw);
57 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
58 status = 0;
59 break;
60 }
61 }
62 return status;
63}
64
65/**
66 * ixgbe_validate_phy_addr - Determines phy address is valid
67 * @hw: pointer to hardware structure
68 *
69 **/
70static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
71{
72 u16 phy_id = 0;
73 bool valid = false;
74
75 hw->phy.addr = phy_addr;
76 ixgbe_read_phy_reg(hw,
77 IXGBE_MDIO_PHY_ID_HIGH,
78 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
79 &phy_id);
80
81 if (phy_id != 0xFFFF && phy_id != 0x0)
82 valid = true;
83
84 return valid;
85}
86
87/**
88 * ixgbe_get_phy_id - Get the phy type
89 * @hw: pointer to hardware structure
90 *
91 **/
92static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
93{
94 u32 status;
95 u16 phy_id_high = 0;
96 u16 phy_id_low = 0;
97
98 status = ixgbe_read_phy_reg(hw,
99 IXGBE_MDIO_PHY_ID_HIGH,
100 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
101 &phy_id_high);
102
103 if (status == 0) {
104 hw->phy.id = (u32)(phy_id_high << 16);
105 status = ixgbe_read_phy_reg(hw,
106 IXGBE_MDIO_PHY_ID_LOW,
107 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
108 &phy_id_low);
109 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
110 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
111 }
112
113 return status;
114}
115
116/**
117 * ixgbe_get_phy_type_from_id - Get the phy type
118 * @hw: pointer to hardware structure
119 *
120 **/
121static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
122{
123 enum ixgbe_phy_type phy_type;
124
125 switch (phy_id) {
126 case TN1010_PHY_ID:
127 phy_type = ixgbe_phy_tn;
128 break;
129 case QT2022_PHY_ID:
130 phy_type = ixgbe_phy_qt;
131 break;
132 default:
133 phy_type = ixgbe_phy_unknown;
134 break;
135 }
136
137 return phy_type;
138}
139
140/**
141 * ixgbe_reset_phy - Performs a PHY reset
142 * @hw: pointer to hardware structure
143 **/
144s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
145{
146 /*
147 * Perform soft PHY reset to the PHY_XS.
148 * This will cause a soft reset to the PHY
149 */
150 return ixgbe_write_phy_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
151 IXGBE_MDIO_PHY_XS_DEV_TYPE,
152 IXGBE_MDIO_PHY_XS_RESET);
153}
154
155/**
156 * ixgbe_read_phy_reg - Reads a value from a specified PHY register
157 * @hw: pointer to hardware structure
158 * @reg_addr: 32 bit address of PHY register to read
159 * @phy_data: Pointer to read data from PHY register
160 **/
161s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr,
162 u32 device_type, u16 *phy_data)
163{
164 u32 command;
165 u32 i;
166 u32 timeout = 10;
167 u32 data;
168 s32 status = 0;
169 u16 gssr;
170
171 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
172 gssr = IXGBE_GSSR_PHY1_SM;
173 else
174 gssr = IXGBE_GSSR_PHY0_SM;
175
176 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
177 status = IXGBE_ERR_SWFW_SYNC;
178
179 if (status == 0) {
180 /* Setup and write the address cycle command */
181 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
182 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
183 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
184 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
185
186 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
187
188 /*
189 * Check every 10 usec to see if the address cycle completed.
190 * The MDI Command bit will clear when the operation is
191 * complete
192 */
193 for (i = 0; i < timeout; i++) {
194 udelay(10);
195
196 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
197
198 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
199 break;
200 }
201
202 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
203 hw_dbg(hw, "PHY address command did not complete.\n");
204 status = IXGBE_ERR_PHY;
205 }
206
207 if (status == 0) {
208 /*
209 * Address cycle complete, setup and write the read
210 * command
211 */
212 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
213 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
214 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
215 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
216
217 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
218
219 /*
220 * Check every 10 usec to see if the address cycle
221 * completed. The MDI Command bit will clear when the
222 * operation is complete
223 */
224 for (i = 0; i < timeout; i++) {
225 udelay(10);
226
227 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
228
229 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
230 break;
231 }
232
233 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
234 hw_dbg(hw,
235 "PHY read command didn't complete\n");
236 status = IXGBE_ERR_PHY;
237 } else {
238 /*
239 * Read operation is complete. Get the data
240 * from MSRWD
241 */
242 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
243 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
244 *phy_data = (u16)(data);
245 }
246 }
247
248 ixgbe_release_swfw_sync(hw, gssr);
249 }
250 return status;
251}
252
253/**
254 * ixgbe_write_phy_reg - Writes a value to specified PHY register
255 * @hw: pointer to hardware structure
256 * @reg_addr: 32 bit PHY register to write
257 * @device_type: 5 bit device type
258 * @phy_data: Data to write to the PHY register
259 **/
260static s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr,
261 u32 device_type, u16 phy_data)
262{
263 u32 command;
264 u32 i;
265 u32 timeout = 10;
266 s32 status = 0;
267 u16 gssr;
268
269 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
270 gssr = IXGBE_GSSR_PHY1_SM;
271 else
272 gssr = IXGBE_GSSR_PHY0_SM;
273
274 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
275 status = IXGBE_ERR_SWFW_SYNC;
276
277 if (status == 0) {
278 /* Put the data in the MDI single read and write data register*/
279 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
280
281 /* Setup and write the address cycle command */
282 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
283 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
284 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
285 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
286
287 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
288
289 /*
290 * Check every 10 usec to see if the address cycle completed.
291 * The MDI Command bit will clear when the operation is
292 * complete
293 */
294 for (i = 0; i < timeout; i++) {
295 udelay(10);
296
297 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
298
299 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
300 hw_dbg(hw, "PHY address cmd didn't complete\n");
301 break;
302 }
303 }
304
305 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0)
306 status = IXGBE_ERR_PHY;
307
308 if (status == 0) {
309 /*
310 * Address cycle complete, setup and write the write
311 * command
312 */
313 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
314 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
315 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
316 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
317
318 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
319
320 /*
321 * Check every 10 usec to see if the address cycle
322 * completed. The MDI Command bit will clear when the
323 * operation is complete
324 */
325 for (i = 0; i < timeout; i++) {
326 udelay(10);
327
328 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
329
330 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
331 hw_dbg(hw, "PHY write command did not "
332 "complete.\n");
333 break;
334 }
335 }
336
337 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0)
338 status = IXGBE_ERR_PHY;
339 }
340
341 ixgbe_release_swfw_sync(hw, gssr);
342 }
343
344 return status;
345}
346
347/**
348 * ixgbe_setup_tnx_phy_link - Set and restart autoneg
349 * @hw: pointer to hardware structure
350 *
351 * Restart autonegotiation and PHY and waits for completion.
352 **/
353s32 ixgbe_setup_tnx_phy_link(struct ixgbe_hw *hw)
354{
355 s32 status = IXGBE_NOT_IMPLEMENTED;
356 u32 time_out;
357 u32 max_time_out = 10;
358 u16 autoneg_speed_selection_register = 0x10;
359 u16 autoneg_restart_mask = 0x0200;
360 u16 autoneg_complete_mask = 0x0020;
361 u16 autoneg_reg = 0;
362
363 /*
364 * Set advertisement settings in PHY based on autoneg_advertised
365 * settings. If autoneg_advertised = 0, then advertise default values
366 * txn devices cannot be "forced" to a autoneg 10G and fail. But can
367 * for a 1G.
368 */
369 ixgbe_read_phy_reg(hw,
370 autoneg_speed_selection_register,
371 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
372 &autoneg_reg);
373
374 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
375 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
376 else
377 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */
378
379 ixgbe_write_phy_reg(hw,
380 autoneg_speed_selection_register,
381 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
382 autoneg_reg);
383
384
385 /* Restart PHY autonegotiation and wait for completion */
386 ixgbe_read_phy_reg(hw,
387 IXGBE_MDIO_AUTO_NEG_CONTROL,
388 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
389 &autoneg_reg);
390
391 autoneg_reg |= autoneg_restart_mask;
392
393 ixgbe_write_phy_reg(hw,
394 IXGBE_MDIO_AUTO_NEG_CONTROL,
395 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
396 autoneg_reg);
397
398 /* Wait for autonegotiation to finish */
399 for (time_out = 0; time_out < max_time_out; time_out++) {
400 udelay(10);
401 /* Restart PHY autonegotiation and wait for completion */
402 status = ixgbe_read_phy_reg(hw,
403 IXGBE_MDIO_AUTO_NEG_STATUS,
404 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
405 &autoneg_reg);
406
407 autoneg_reg &= autoneg_complete_mask;
408 if (autoneg_reg == autoneg_complete_mask) {
409 status = 0;
410 break;
411 }
412 }
413
414 if (time_out == max_time_out)
415 status = IXGBE_ERR_LINK_SETUP;
416
417 return status;
418}
419
420/**
421 * ixgbe_check_tnx_phy_link - Determine link and speed status
422 * @hw: pointer to hardware structure
423 *
424 * Reads the VS1 register to determine if link is up and the current speed for
425 * the PHY.
426 **/
427s32 ixgbe_check_tnx_phy_link(struct ixgbe_hw *hw, u32 *speed,
428 bool *link_up)
429{
430 s32 status = 0;
431 u32 time_out;
432 u32 max_time_out = 10;
433 u16 phy_link = 0;
434 u16 phy_speed = 0;
435 u16 phy_data = 0;
436
437 /* Initialize speed and link to default case */
438 *link_up = false;
439 *speed = IXGBE_LINK_SPEED_10GB_FULL;
440
441 /*
442 * Check current speed and link status of the PHY register.
443 * This is a vendor specific register and may have to
444 * be changed for other copper PHYs.
445 */
446 for (time_out = 0; time_out < max_time_out; time_out++) {
447 udelay(10);
448 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
449 *link_up = true;
450 if (phy_speed ==
451 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
452 *speed = IXGBE_LINK_SPEED_1GB_FULL;
453 break;
454 } else {
455 status = ixgbe_read_phy_reg(hw,
456 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
457 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
458 &phy_data);
459 phy_link = phy_data &
460 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
461 phy_speed = phy_data &
462 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
463 }
464 }
465
466 return status;
467}
468
469/**
470 * ixgbe_setup_tnx_phy_link_speed - Sets the auto advertised capabilities
471 * @hw: pointer to hardware structure
472 * @speed: new link speed
473 * @autoneg: true if autonegotiation enabled
474 **/
475s32 ixgbe_setup_tnx_phy_link_speed(struct ixgbe_hw *hw, u32 speed,
476 bool autoneg,
477 bool autoneg_wait_to_complete)
478{
479 /*
480 * Clear autoneg_advertised and set new values based on input link
481 * speed.
482 */
483 hw->phy.autoneg_advertised = 0;
484
485 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
486 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
487 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
488 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
489
490 /* Setup link based on the new speed settings */
491 ixgbe_setup_tnx_phy_link(hw);
492
493 return 0;
494}
diff --git a/drivers/net/ixgbe/ixgbe_phy.h b/drivers/net/ixgbe/ixgbe_phy.h
new file mode 100644
index 000000000000..199e8f670f3a
--- /dev/null
+++ b/drivers/net/ixgbe/ixgbe_phy.h
@@ -0,0 +1,50 @@
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _IXGBE_PHY_H_
30#define _IXGBE_PHY_H_
31
32#include "ixgbe_type.h"
33
34s32 ixgbe_init_shared_code_phy(struct ixgbe_hw *hw);
35s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
36s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, u32 *speed, bool *link_up);
37s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, u32 speed, bool autoneg,
38 bool autoneg_wait_to_complete);
39s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
40s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
41s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr,
42 u32 device_type, u16 *phy_data);
43
44/* PHY specific */
45s32 ixgbe_setup_tnx_phy_link(struct ixgbe_hw *hw);
46s32 ixgbe_check_tnx_phy_link(struct ixgbe_hw *hw, u32 *speed, bool *link_up);
47s32 ixgbe_setup_tnx_phy_link_speed(struct ixgbe_hw *hw, u32 speed, bool autoneg,
48 bool autoneg_wait_to_complete);
49
50#endif /* _IXGBE_PHY_H_ */
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
new file mode 100644
index 000000000000..fdcde16a2a99
--- /dev/null
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -0,0 +1,1332 @@
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#ifndef _IXGBE_TYPE_H_
30#define _IXGBE_TYPE_H_
31
32#include <linux/types.h>
33
34/* Vendor ID */
35#define IXGBE_INTEL_VENDOR_ID 0x8086
36
37/* Device IDs */
38#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
39#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
40#define IXGBE_DEV_ID_82598AT_DUAL_PORT 0x10C8
41#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
42
43/* General Registers */
44#define IXGBE_CTRL 0x00000
45#define IXGBE_STATUS 0x00008
46#define IXGBE_CTRL_EXT 0x00018
47#define IXGBE_ESDP 0x00020
48#define IXGBE_EODSDP 0x00028
49#define IXGBE_LEDCTL 0x00200
50#define IXGBE_FRTIMER 0x00048
51#define IXGBE_TCPTIMER 0x0004C
52
53/* NVM Registers */
54#define IXGBE_EEC 0x10010
55#define IXGBE_EERD 0x10014
56#define IXGBE_FLA 0x1001C
57#define IXGBE_EEMNGCTL 0x10110
58#define IXGBE_EEMNGDATA 0x10114
59#define IXGBE_FLMNGCTL 0x10118
60#define IXGBE_FLMNGDATA 0x1011C
61#define IXGBE_FLMNGCNT 0x10120
62#define IXGBE_FLOP 0x1013C
63#define IXGBE_GRC 0x10200
64
65/* Interrupt Registers */
66#define IXGBE_EICR 0x00800
67#define IXGBE_EICS 0x00808
68#define IXGBE_EIMS 0x00880
69#define IXGBE_EIMC 0x00888
70#define IXGBE_EIAC 0x00810
71#define IXGBE_EIAM 0x00890
72#define IXGBE_EITR(_i) (0x00820 + ((_i) * 4)) /* 0x820-0x86c */
73#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
74#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
75#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
76#define IXGBE_PBACL 0x11068
77#define IXGBE_GPIE 0x00898
78
79/* Flow Control Registers */
80#define IXGBE_PFCTOP 0x03008
81#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
82#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
83#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
84#define IXGBE_FCRTV 0x032A0
85#define IXGBE_TFCS 0x0CE00
86
87/* Receive DMA Registers */
88#define IXGBE_RDBAL(_i) (0x01000 + ((_i) * 0x40)) /* 64 of each (0-63)*/
89#define IXGBE_RDBAH(_i) (0x01004 + ((_i) * 0x40))
90#define IXGBE_RDLEN(_i) (0x01008 + ((_i) * 0x40))
91#define IXGBE_RDH(_i) (0x01010 + ((_i) * 0x40))
92#define IXGBE_RDT(_i) (0x01018 + ((_i) * 0x40))
93#define IXGBE_RXDCTL(_i) (0x01028 + ((_i) * 0x40))
94#define IXGBE_RSCCTL(_i) (0x0102C + ((_i) * 0x40))
95#define IXGBE_SRRCTL(_i) (0x02100 + ((_i) * 4))
96 /* array of 16 (0x02100-0x0213C) */
97#define IXGBE_DCA_RXCTRL(_i) (0x02200 + ((_i) * 4))
98 /* array of 16 (0x02200-0x0223C) */
99#define IXGBE_RDRXCTL 0x02F00
100#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
101 /* 8 of these 0x03C00 - 0x03C1C */
102#define IXGBE_RXCTRL 0x03000
103#define IXGBE_DROPEN 0x03D04
104#define IXGBE_RXPBSIZE_SHIFT 10
105
106/* Receive Registers */
107#define IXGBE_RXCSUM 0x05000
108#define IXGBE_RFCTL 0x05008
109#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
110 /* Multicast Table Array - 128 entries */
111#define IXGBE_RAL(_i) (0x05400 + ((_i) * 8)) /* 16 of these (0-15) */
112#define IXGBE_RAH(_i) (0x05404 + ((_i) * 8)) /* 16 of these (0-15) */
113#define IXGBE_PSRTYPE 0x05480
114 /* 0x5480-0x54BC Packet split receive type */
115#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
116 /* array of 4096 1-bit vlan filters */
117#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
118 /*array of 4096 4-bit vlan vmdq indicies */
119#define IXGBE_FCTRL 0x05080
120#define IXGBE_VLNCTRL 0x05088
121#define IXGBE_MCSTCTRL 0x05090
122#define IXGBE_MRQC 0x05818
123#define IXGBE_VMD_CTL 0x0581C
124#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
125#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
126#define IXGBE_IMIRVP 0x05AC0
127#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
128#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
129
130/* Transmit DMA registers */
131#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40))/* 32 of these (0-31)*/
132#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
133#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
134#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
135#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
136#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
137#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
138#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
139#define IXGBE_DTXCTL 0x07E00
140#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4))
141 /* there are 16 of these (0-15) */
142#define IXGBE_TIPG 0x0CB00
143#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) *0x04))
144 /* there are 8 of these */
145#define IXGBE_MNGTXMAP 0x0CD10
146#define IXGBE_TIPG_FIBER_DEFAULT 3
147#define IXGBE_TXPBSIZE_SHIFT 10
148
149/* Wake up registers */
150#define IXGBE_WUC 0x05800
151#define IXGBE_WUFC 0x05808
152#define IXGBE_WUS 0x05810
153#define IXGBE_IPAV 0x05838
154#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
155#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
156#define IXGBE_WUPL 0x05900
157#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
158#define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */
159
160/* Music registers */
161#define IXGBE_RMCS 0x03D00
162#define IXGBE_DPMCS 0x07F40
163#define IXGBE_PDPMCS 0x0CD00
164#define IXGBE_RUPPBMR 0x050A0
165#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
166#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
167#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
168#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
169#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
170#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
171
172/* Stats registers */
173#define IXGBE_CRCERRS 0x04000
174#define IXGBE_ILLERRC 0x04004
175#define IXGBE_ERRBC 0x04008
176#define IXGBE_MSPDC 0x04010
177#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
178#define IXGBE_MLFC 0x04034
179#define IXGBE_MRFC 0x04038
180#define IXGBE_RLEC 0x04040
181#define IXGBE_LXONTXC 0x03F60
182#define IXGBE_LXONRXC 0x0CF60
183#define IXGBE_LXOFFTXC 0x03F68
184#define IXGBE_LXOFFRXC 0x0CF68
185#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
186#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
187#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
188#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
189#define IXGBE_PRC64 0x0405C
190#define IXGBE_PRC127 0x04060
191#define IXGBE_PRC255 0x04064
192#define IXGBE_PRC511 0x04068
193#define IXGBE_PRC1023 0x0406C
194#define IXGBE_PRC1522 0x04070
195#define IXGBE_GPRC 0x04074
196#define IXGBE_BPRC 0x04078
197#define IXGBE_MPRC 0x0407C
198#define IXGBE_GPTC 0x04080
199#define IXGBE_GORCL 0x04088
200#define IXGBE_GORCH 0x0408C
201#define IXGBE_GOTCL 0x04090
202#define IXGBE_GOTCH 0x04094
203#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
204#define IXGBE_RUC 0x040A4
205#define IXGBE_RFC 0x040A8
206#define IXGBE_ROC 0x040AC
207#define IXGBE_RJC 0x040B0
208#define IXGBE_MNGPRC 0x040B4
209#define IXGBE_MNGPDC 0x040B8
210#define IXGBE_MNGPTC 0x0CF90
211#define IXGBE_TORL 0x040C0
212#define IXGBE_TORH 0x040C4
213#define IXGBE_TPR 0x040D0
214#define IXGBE_TPT 0x040D4
215#define IXGBE_PTC64 0x040D8
216#define IXGBE_PTC127 0x040DC
217#define IXGBE_PTC255 0x040E0
218#define IXGBE_PTC511 0x040E4
219#define IXGBE_PTC1023 0x040E8
220#define IXGBE_PTC1522 0x040EC
221#define IXGBE_MPTC 0x040F0
222#define IXGBE_BPTC 0x040F4
223#define IXGBE_XEC 0x04120
224
225#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */
226#define IXGBE_TQSMR(_i) (0x07300 + ((_i) * 4)) /* 8 of these */
227
228#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
229#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
230#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
231#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
232
233/* Management */
234#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
235#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
236#define IXGBE_MANC 0x05820
237#define IXGBE_MFVAL 0x05824
238#define IXGBE_MANC2H 0x05860
239#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
240#define IXGBE_MIPAF 0x058B0
241#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
242#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
243#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
244
245/* ARC Subsystem registers */
246#define IXGBE_HICR 0x15F00
247#define IXGBE_FWSTS 0x15F0C
248#define IXGBE_HSMC0R 0x15F04
249#define IXGBE_HSMC1R 0x15F08
250#define IXGBE_SWSR 0x15F10
251#define IXGBE_HFDR 0x15FE8
252#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
253
254/* PCI-E registers */
255#define IXGBE_GCR 0x11000
256#define IXGBE_GTV 0x11004
257#define IXGBE_FUNCTAG 0x11008
258#define IXGBE_GLT 0x1100C
259#define IXGBE_GSCL_1 0x11010
260#define IXGBE_GSCL_2 0x11014
261#define IXGBE_GSCL_3 0x11018
262#define IXGBE_GSCL_4 0x1101C
263#define IXGBE_GSCN_0 0x11020
264#define IXGBE_GSCN_1 0x11024
265#define IXGBE_GSCN_2 0x11028
266#define IXGBE_GSCN_3 0x1102C
267#define IXGBE_FACTPS 0x10150
268#define IXGBE_PCIEANACTL 0x11040
269#define IXGBE_SWSM 0x10140
270#define IXGBE_FWSM 0x10148
271#define IXGBE_GSSR 0x10160
272#define IXGBE_MREVID 0x11064
273#define IXGBE_DCA_ID 0x11070
274#define IXGBE_DCA_CTRL 0x11074
275
276/* Diagnostic Registers */
277#define IXGBE_RDSTATCTL 0x02C20
278#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
279#define IXGBE_RDHMPN 0x02F08
280#define IXGBE_RIC_DW0 0x02F10
281#define IXGBE_RIC_DW1 0x02F14
282#define IXGBE_RIC_DW2 0x02F18
283#define IXGBE_RIC_DW3 0x02F1C
284#define IXGBE_RDPROBE 0x02F20
285#define IXGBE_TDSTATCTL 0x07C20
286#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
287#define IXGBE_TDHMPN 0x07F08
288#define IXGBE_TIC_DW0 0x07F10
289#define IXGBE_TIC_DW1 0x07F14
290#define IXGBE_TIC_DW2 0x07F18
291#define IXGBE_TIC_DW3 0x07F1C
292#define IXGBE_TDPROBE 0x07F20
293#define IXGBE_TXBUFCTRL 0x0C600
294#define IXGBE_TXBUFDATA0 0x0C610
295#define IXGBE_TXBUFDATA1 0x0C614
296#define IXGBE_TXBUFDATA2 0x0C618
297#define IXGBE_TXBUFDATA3 0x0C61C
298#define IXGBE_RXBUFCTRL 0x03600
299#define IXGBE_RXBUFDATA0 0x03610
300#define IXGBE_RXBUFDATA1 0x03614
301#define IXGBE_RXBUFDATA2 0x03618
302#define IXGBE_RXBUFDATA3 0x0361C
303#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
304#define IXGBE_RFVAL 0x050A4
305#define IXGBE_MDFTC1 0x042B8
306#define IXGBE_MDFTC2 0x042C0
307#define IXGBE_MDFTFIFO1 0x042C4
308#define IXGBE_MDFTFIFO2 0x042C8
309#define IXGBE_MDFTS 0x042CC
310#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
311#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
312#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
313#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
314#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
315#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
316#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
317#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
318#define IXGBE_PCIEECCCTL 0x1106C
319#define IXGBE_PBTXECC 0x0C300
320#define IXGBE_PBRXECC 0x03300
321#define IXGBE_GHECCR 0x110B0
322
323/* MAC Registers */
324#define IXGBE_PCS1GCFIG 0x04200
325#define IXGBE_PCS1GLCTL 0x04208
326#define IXGBE_PCS1GLSTA 0x0420C
327#define IXGBE_PCS1GDBG0 0x04210
328#define IXGBE_PCS1GDBG1 0x04214
329#define IXGBE_PCS1GANA 0x04218
330#define IXGBE_PCS1GANLP 0x0421C
331#define IXGBE_PCS1GANNP 0x04220
332#define IXGBE_PCS1GANLPNP 0x04224
333#define IXGBE_HLREG0 0x04240
334#define IXGBE_HLREG1 0x04244
335#define IXGBE_PAP 0x04248
336#define IXGBE_MACA 0x0424C
337#define IXGBE_APAE 0x04250
338#define IXGBE_ARD 0x04254
339#define IXGBE_AIS 0x04258
340#define IXGBE_MSCA 0x0425C
341#define IXGBE_MSRWD 0x04260
342#define IXGBE_MLADD 0x04264
343#define IXGBE_MHADD 0x04268
344#define IXGBE_TREG 0x0426C
345#define IXGBE_PCSS1 0x04288
346#define IXGBE_PCSS2 0x0428C
347#define IXGBE_XPCSS 0x04290
348#define IXGBE_SERDESC 0x04298
349#define IXGBE_MACS 0x0429C
350#define IXGBE_AUTOC 0x042A0
351#define IXGBE_LINKS 0x042A4
352#define IXGBE_AUTOC2 0x042A8
353#define IXGBE_AUTOC3 0x042AC
354#define IXGBE_ANLP1 0x042B0
355#define IXGBE_ANLP2 0x042B4
356#define IXGBE_ATLASCTL 0x04800
357
358/* RSCCTL Bit Masks */
359#define IXGBE_RSCCTL_RSCEN 0x01
360#define IXGBE_RSCCTL_MAXDESC_1 0x00
361#define IXGBE_RSCCTL_MAXDESC_4 0x04
362#define IXGBE_RSCCTL_MAXDESC_8 0x08
363#define IXGBE_RSCCTL_MAXDESC_16 0x0C
364
365/* CTRL Bit Masks */
366#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
367#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
368#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
369
370/* FACTPS */
371#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
372
373/* MHADD Bit Masks */
374#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
375#define IXGBE_MHADD_MFS_SHIFT 16
376
377/* Extended Device Control */
378#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
379#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
380#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
381
382/* Direct Cache Access (DCA) definitions */
383#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
384#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
385
386#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
387#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
388
389#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
390#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
391#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
392#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
393
394#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
395#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
396#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* TX Desc writeback RO bit */
397#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
398
399/* MSCA Bit Masks */
400#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
401#define IXGBE_MSCA_NP_ADDR_SHIFT 0
402#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
403#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
404#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
405#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
406#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
407#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
408#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
409#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
410#define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */
411#define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/
412#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
413#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
414#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
415#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */
416#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
417#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
418
419/* MSRWD bit masks */
420#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
421#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
422#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
423#define IXGBE_MSRWD_READ_DATA_SHIFT 16
424
425/* Atlas registers */
426#define IXGBE_ATLAS_PDN_LPBK 0x24
427#define IXGBE_ATLAS_PDN_10G 0xB
428#define IXGBE_ATLAS_PDN_1G 0xC
429#define IXGBE_ATLAS_PDN_AN 0xD
430
431/* Atlas bit masks */
432#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
433#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
434#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
435#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
436#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
437
438/* Device Type definitions for new protocol MDIO commands */
439#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
440#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
441#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
442#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
443#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
444
445#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
446#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
447#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
448#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
449#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
450#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
451
452#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
453#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
454#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
455#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
456#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
457#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
458#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Abilty Reg */
459#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
460#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
461
462#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
463#define IXGBE_MAX_PHY_ADDR 32
464
465/* PHY IDs*/
466#define TN1010_PHY_ID 0x00A19410
467#define QT2022_PHY_ID 0x0043A400
468
469/* General purpose Interrupt Enable */
470#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
471#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
472#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
473#define IXGBE_GPIE_EIAME 0x40000000
474#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
475
476/* Transmit Flow Control status */
477#define IXGBE_TFCS_TXOFF 0x00000001
478#define IXGBE_TFCS_TXOFF0 0x00000100
479#define IXGBE_TFCS_TXOFF1 0x00000200
480#define IXGBE_TFCS_TXOFF2 0x00000400
481#define IXGBE_TFCS_TXOFF3 0x00000800
482#define IXGBE_TFCS_TXOFF4 0x00001000
483#define IXGBE_TFCS_TXOFF5 0x00002000
484#define IXGBE_TFCS_TXOFF6 0x00004000
485#define IXGBE_TFCS_TXOFF7 0x00008000
486
487/* TCP Timer */
488#define IXGBE_TCPTIMER_KS 0x00000100
489#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
490#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
491#define IXGBE_TCPTIMER_LOOP 0x00000800
492#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
493
494/* HLREG0 Bit Masks */
495#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
496#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
497#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
498#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
499#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
500#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
501#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
502#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
503#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
504#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
505#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
506#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
507#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
508#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
509#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
510
511/* VMD_CTL bitmasks */
512#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
513#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
514
515/* RDHMPN and TDHMPN bitmasks */
516#define IXGBE_RDHMPN_RDICADDR 0x007FF800
517#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
518#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
519#define IXGBE_TDHMPN_TDICADDR 0x003FF800
520#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
521#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
522
523/* Receive Checksum Control */
524#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
525#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
526
527/* FCRTL Bit Masks */
528#define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */
529#define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */
530
531/* PAP bit masks*/
532#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
533
534/* RMCS Bit Masks */
535#define IXGBE_RMCS_RRM 0x00000002 /* Receive Recylce Mode enable */
536/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
537#define IXGBE_RMCS_RAC 0x00000004
538#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
539#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */
540#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */
541#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
542
543/* Interrupt register bitmasks */
544
545/* Extended Interrupt Cause Read */
546#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
547#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
548#define IXGBE_EICR_MNG 0x00400000 /* Managability Event Interrupt */
549#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
550#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
551#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
552#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
553
554/* Extended Interrupt Cause Set */
555#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
556#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
557#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
558#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
559#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
560#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
561#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
562#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
563
564/* Extended Interrupt Mask Set */
565#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
566#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
567#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
568#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
569#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
570#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
571#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
572
573/* Extended Interrupt Mask Clear */
574#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
575#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
576#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
577#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
578#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Error */
579#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
580#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
581
582#define IXGBE_EIMS_ENABLE_MASK (\
583 IXGBE_EIMS_RTX_QUEUE | \
584 IXGBE_EIMS_LSC | \
585 IXGBE_EIMS_TCP_TIMER | \
586 IXGBE_EIMS_OTHER)
587
588/* Immediate Interrupt RX (A.K.A. Low Latency Interrupt) */
589#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
590#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
591#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
592#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
593#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
594#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
595#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
596#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
597#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
598#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
599
600/* Interrupt clear mask */
601#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
602
603/* Interrupt Vector Allocation Registers */
604#define IXGBE_IVAR_REG_NUM 25
605#define IXGBE_IVAR_TXRX_ENTRY 96
606#define IXGBE_IVAR_RX_ENTRY 64
607#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
608#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
609#define IXGBE_IVAR_TX_ENTRY 32
610
611#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
612#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
613
614#define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
615
616#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
617
618/* VLAN Control Bit Masks */
619#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
620#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
621#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
622#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
623#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
624
625#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
626
627/* STATUS Bit Masks */
628#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
629#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
630
631#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
632#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
633
634/* ESDP Bit Masks */
635#define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */
636#define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */
637#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
638#define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */
639
640/* LEDCTL Bit Masks */
641#define IXGBE_LED_IVRT_BASE 0x00000040
642#define IXGBE_LED_BLINK_BASE 0x00000080
643#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
644#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
645#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
646#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
647#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
648#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
649
650/* LED modes */
651#define IXGBE_LED_LINK_UP 0x0
652#define IXGBE_LED_LINK_10G 0x1
653#define IXGBE_LED_MAC 0x2
654#define IXGBE_LED_FILTER 0x3
655#define IXGBE_LED_LINK_ACTIVE 0x4
656#define IXGBE_LED_LINK_1G 0x5
657#define IXGBE_LED_ON 0xE
658#define IXGBE_LED_OFF 0xF
659
660/* AUTOC Bit Masks */
661#define IXGBE_AUTOC_KX4_SUPP 0x80000000
662#define IXGBE_AUTOC_KX_SUPP 0x40000000
663#define IXGBE_AUTOC_PAUSE 0x30000000
664#define IXGBE_AUTOC_RF 0x08000000
665#define IXGBE_AUTOC_PD_TMR 0x06000000
666#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
667#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
668#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
669#define IXGBE_AUTOC_AN_RESTART 0x00001000
670#define IXGBE_AUTOC_FLU 0x00000001
671#define IXGBE_AUTOC_LMS_SHIFT 13
672#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
673#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
674#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
675#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
676#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
677#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
678#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
679
680#define IXGBE_AUTOC_1G_PMA_PMD 0x00000200
681#define IXGBE_AUTOC_10G_PMA_PMD 0x00000180
682#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
683#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
684#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
685#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
686#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
687#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
688#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
689
690/* LINKS Bit Masks */
691#define IXGBE_LINKS_KX_AN_COMP 0x80000000
692#define IXGBE_LINKS_UP 0x40000000
693#define IXGBE_LINKS_SPEED 0x20000000
694#define IXGBE_LINKS_MODE 0x18000000
695#define IXGBE_LINKS_RX_MODE 0x06000000
696#define IXGBE_LINKS_TX_MODE 0x01800000
697#define IXGBE_LINKS_XGXS_EN 0x00400000
698#define IXGBE_LINKS_PCS_1G_EN 0x00200000
699#define IXGBE_LINKS_1G_AN_EN 0x00100000
700#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
701#define IXGBE_LINKS_1G_SYNC 0x00040000
702#define IXGBE_LINKS_10G_ALIGN 0x00020000
703#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
704#define IXGBE_LINKS_TL_FAULT 0x00001000
705#define IXGBE_LINKS_SIGNAL 0x00000F00
706
707#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
708
709/* SW Semaphore Register bitmasks */
710#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
711#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
712#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
713
714/* GSSR definitions */
715#define IXGBE_GSSR_EEP_SM 0x0001
716#define IXGBE_GSSR_PHY0_SM 0x0002
717#define IXGBE_GSSR_PHY1_SM 0x0004
718#define IXGBE_GSSR_MAC_CSR_SM 0x0008
719#define IXGBE_GSSR_FLASH_SM 0x0010
720
721/* EEC Register */
722#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
723#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
724#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
725#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
726#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
727#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
728#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
729#define IXGBE_EEC_FWE_SHIFT 4
730#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
731#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
732#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
733#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
734/* EEPROM Addressing bits based on type (0-small, 1-large) */
735#define IXGBE_EEC_ADDR_SIZE 0x00000400
736#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
737
738#define IXGBE_EEC_SIZE_SHIFT 11
739#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
740#define IXGBE_EEPROM_OPCODE_BITS 8
741
742/* Checksum and EEPROM pointers */
743#define IXGBE_EEPROM_CHECKSUM 0x3F
744#define IXGBE_EEPROM_SUM 0xBABA
745#define IXGBE_PCIE_ANALOG_PTR 0x03
746#define IXGBE_ATLAS0_CONFIG_PTR 0x04
747#define IXGBE_ATLAS1_CONFIG_PTR 0x05
748#define IXGBE_PCIE_GENERAL_PTR 0x06
749#define IXGBE_PCIE_CONFIG0_PTR 0x07
750#define IXGBE_PCIE_CONFIG1_PTR 0x08
751#define IXGBE_CORE0_PTR 0x09
752#define IXGBE_CORE1_PTR 0x0A
753#define IXGBE_MAC0_PTR 0x0B
754#define IXGBE_MAC1_PTR 0x0C
755#define IXGBE_CSR0_CONFIG_PTR 0x0D
756#define IXGBE_CSR1_CONFIG_PTR 0x0E
757#define IXGBE_FW_PTR 0x0F
758#define IXGBE_PBANUM0_PTR 0x15
759#define IXGBE_PBANUM1_PTR 0x16
760
761/* EEPROM Commands - SPI */
762#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
763#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
764#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
765#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
766#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
767#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
768/* EEPROM reset Write Enbale latch */
769#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
770#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
771#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
772#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
773#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
774#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
775
776/* EEPROM Read Register */
777#define IXGBE_EEPROM_READ_REG_DATA 16 /* data offset in EEPROM read reg */
778#define IXGBE_EEPROM_READ_REG_DONE 2 /* Offset to READ done bit */
779#define IXGBE_EEPROM_READ_REG_START 1 /* First bit to start operation */
780#define IXGBE_EEPROM_READ_ADDR_SHIFT 2 /* Shift to the address bits */
781
782#define IXGBE_ETH_LENGTH_OF_ADDRESS 6
783
784#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
785#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
786#endif
787
788#ifndef IXGBE_EERD_ATTEMPTS
789/* Number of 5 microseconds we wait for EERD read to complete */
790#define IXGBE_EERD_ATTEMPTS 100000
791#endif
792
793/* PCI Bus Info */
794#define IXGBE_PCI_LINK_STATUS 0xB2
795#define IXGBE_PCI_LINK_WIDTH 0x3F0
796#define IXGBE_PCI_LINK_WIDTH_1 0x10
797#define IXGBE_PCI_LINK_WIDTH_2 0x20
798#define IXGBE_PCI_LINK_WIDTH_4 0x40
799#define IXGBE_PCI_LINK_WIDTH_8 0x80
800#define IXGBE_PCI_LINK_SPEED 0xF
801#define IXGBE_PCI_LINK_SPEED_2500 0x1
802#define IXGBE_PCI_LINK_SPEED_5000 0x2
803
804/* Number of 100 microseconds we wait for PCI Express master disable */
805#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
806
807/* PHY Types */
808#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
809
810/* Check whether address is multicast. This is little-endian specific check.*/
811#define IXGBE_IS_MULTICAST(Address) \
812 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
813
814/* Check whether an address is broadcast. */
815#define IXGBE_IS_BROADCAST(Address) \
816 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
817 (((u8 *)(Address))[1] == ((u8)0xff)))
818
819/* RAH */
820#define IXGBE_RAH_VIND_MASK 0x003C0000
821#define IXGBE_RAH_VIND_SHIFT 18
822#define IXGBE_RAH_AV 0x80000000
823
824/* Filters */
825#define IXGBE_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
826#define IXGBE_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
827
828/* Header split receive */
829#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
830#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
831#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
832#define IXGBE_RFCTL_NFSW_DIS 0x00000040
833#define IXGBE_RFCTL_NFSR_DIS 0x00000080
834#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
835#define IXGBE_RFCTL_NFS_VER_SHIFT 8
836#define IXGBE_RFCTL_NFS_VER_2 0
837#define IXGBE_RFCTL_NFS_VER_3 1
838#define IXGBE_RFCTL_NFS_VER_4 2
839#define IXGBE_RFCTL_IPV6_DIS 0x00000400
840#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
841#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
842#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
843#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
844
845/* Transmit Config masks */
846#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
847#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
848/* Enable short packet padding to 64 bytes */
849#define IXGBE_TX_PAD_ENABLE 0x00000400
850#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
851/* This allows for 16K packets + 4k for vlan */
852#define IXGBE_MAX_FRAME_SZ 0x40040000
853
854#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
855#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq. # write-back enable */
856
857/* Receive Config masks */
858#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
859#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
860#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
861
862#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
863#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
864#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
865#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
866#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
867#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
868/* Receive Priority Flow Control Enbale */
869#define IXGBE_FCTRL_RPFCE 0x00004000
870#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
871
872/* Multiple Receive Queue Control */
873#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
874#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
875#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
876#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
877#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
878#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
879#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
880#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
881#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
882#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
883#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
884
885#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
886#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
887#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
888#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
889#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
890#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
891#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
892#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
893#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
894
895/* Receive Descriptor bit definitions */
896#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
897#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
898#define IXGBE_RXD_STAT_IXSM 0x04 /* Ignore checksum */
899#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
900#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
901#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
902#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
903#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
904#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
905#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
906#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
907#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
908#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
909#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
910#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
911#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
912#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
913#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
914#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
915#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
916#define IXGBE_RXDADV_HBO 0x00800000
917#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
918#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
919#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
920#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
921#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
922#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
923#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
924#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
925#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
926#define IXGBE_RXD_PRI_SHIFT 13
927#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
928#define IXGBE_RXD_CFI_SHIFT 12
929
930/* SRRCTL bit definitions */
931#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
932#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
933#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
934#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
935#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
936#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
937#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
938#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
939
940#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
941#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
942
943#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
944#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
945#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
946#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
947#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
948#define IXGBE_RXDADV_SPH 0x8000
949
950/* RSS Hash results */
951#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
952#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
953#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
954#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
955#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
956#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
957#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
958#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
959#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
960#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
961
962/* RSS Packet Types as indicated in the receive descriptor. */
963#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
964#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
965#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
966#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
967#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
968#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
969#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
970#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
971#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
972
973/* Masks to determine if packets should be dropped due to frame errors */
974#define IXGBE_RXD_ERR_FRAME_ERR_MASK (\
975 IXGBE_RXD_ERR_CE | \
976 IXGBE_RXD_ERR_LE | \
977 IXGBE_RXD_ERR_PE | \
978 IXGBE_RXD_ERR_OSE | \
979 IXGBE_RXD_ERR_USE)
980
981#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK (\
982 IXGBE_RXDADV_ERR_CE | \
983 IXGBE_RXDADV_ERR_LE | \
984 IXGBE_RXDADV_ERR_PE | \
985 IXGBE_RXDADV_ERR_OSE | \
986 IXGBE_RXDADV_ERR_USE)
987
988/* Multicast bit mask */
989#define IXGBE_MCSTCTRL_MFE 0x4
990
991/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
992#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
993#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
994#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
995
996/* Vlan-specific macros */
997#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
998#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
999#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
1000#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
1001
1002/* Transmit Descriptor - Legacy */
1003struct ixgbe_legacy_tx_desc {
1004 u64 buffer_addr; /* Address of the descriptor's data buffer */
1005 union {
1006 u32 data;
1007 struct {
1008 u16 length; /* Data buffer length */
1009 u8 cso; /* Checksum offset */
1010 u8 cmd; /* Descriptor control */
1011 } flags;
1012 } lower;
1013 union {
1014 u32 data;
1015 struct {
1016 u8 status; /* Descriptor status */
1017 u8 css; /* Checksum start */
1018 u16 vlan;
1019 } fields;
1020 } upper;
1021};
1022
1023/* Transmit Descriptor - Advanced */
1024union ixgbe_adv_tx_desc {
1025 struct {
1026 u64 buffer_addr; /* Address of descriptor's data buf */
1027 u32 cmd_type_len;
1028 u32 olinfo_status;
1029 } read;
1030 struct {
1031 u64 rsvd; /* Reserved */
1032 u32 nxtseq_seed;
1033 u32 status;
1034 } wb;
1035};
1036
1037/* Receive Descriptor - Legacy */
1038struct ixgbe_legacy_rx_desc {
1039 u64 buffer_addr; /* Address of the descriptor's data buffer */
1040 u16 length; /* Length of data DMAed into data buffer */
1041 u16 csum; /* Packet checksum */
1042 u8 status; /* Descriptor status */
1043 u8 errors; /* Descriptor Errors */
1044 u16 vlan;
1045};
1046
1047/* Receive Descriptor - Advanced */
1048union ixgbe_adv_rx_desc {
1049 struct {
1050 u64 pkt_addr; /* Packet buffer address */
1051 u64 hdr_addr; /* Header buffer address */
1052 } read;
1053 struct {
1054 struct {
1055 struct {
1056 u16 pkt_info; /* RSS type, Packet type */
1057 u16 hdr_info; /* Split Header, header len */
1058 } lo_dword;
1059 union {
1060 u32 rss; /* RSS Hash */
1061 struct {
1062 u16 ip_id; /* IP id */
1063 u16 csum; /* Packet Checksum */
1064 } csum_ip;
1065 } hi_dword;
1066 } lower;
1067 struct {
1068 u32 status_error; /* ext status/error */
1069 u16 length; /* Packet length */
1070 u16 vlan; /* VLAN tag */
1071 } upper;
1072 } wb; /* writeback */
1073};
1074
1075/* Context descriptors */
1076struct ixgbe_adv_tx_context_desc {
1077 u32 vlan_macip_lens;
1078 u32 seqnum_seed;
1079 u32 type_tucmd_mlhl;
1080 u32 mss_l4len_idx;
1081};
1082
1083/* Adv Transmit Descriptor Config Masks */
1084#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buffer length(bytes) */
1085#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
1086#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
1087#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
1088#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
1089#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
1090#define IXGBE_ADVTXD_DCMD_RDMA 0x04000000 /* RDMA */
1091#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
1092#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
1093#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
1094#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
1095#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
1096#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
1097#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */
1098#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
1099#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
1100#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
1101#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
1102 IXGBE_ADVTXD_POPTS_SHIFT)
1103#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
1104 IXGBE_ADVTXD_POPTS_SHIFT)
1105#define IXGBE_ADVTXD_POPTS_EOM 0x00000400 /* Enable L bit-RDMA DDP hdr */
1106#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
1107#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
1108#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
1109#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
1110#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
1111#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
1112#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
1113#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
1114#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
1115#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
1116#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
1117#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
1118#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* Req requires Markers and CRC */
1119#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
1120#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
1121
1122/* Link speed */
1123#define IXGBE_LINK_SPEED_UNKNOWN 0
1124#define IXGBE_LINK_SPEED_100_FULL 0x0008
1125#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
1126#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
1127
1128
1129enum ixgbe_eeprom_type {
1130 ixgbe_eeprom_uninitialized = 0,
1131 ixgbe_eeprom_spi,
1132 ixgbe_eeprom_none /* No NVM support */
1133};
1134
1135enum ixgbe_mac_type {
1136 ixgbe_mac_unknown = 0,
1137 ixgbe_mac_82598EB,
1138 ixgbe_num_macs
1139};
1140
1141enum ixgbe_phy_type {
1142 ixgbe_phy_unknown = 0,
1143 ixgbe_phy_tn,
1144 ixgbe_phy_qt,
1145 ixgbe_phy_xaui
1146};
1147
1148enum ixgbe_media_type {
1149 ixgbe_media_type_unknown = 0,
1150 ixgbe_media_type_fiber,
1151 ixgbe_media_type_copper,
1152 ixgbe_media_type_backplane
1153};
1154
1155/* Flow Control Settings */
1156enum ixgbe_fc_type {
1157 ixgbe_fc_none = 0,
1158 ixgbe_fc_rx_pause,
1159 ixgbe_fc_tx_pause,
1160 ixgbe_fc_full,
1161 ixgbe_fc_default
1162};
1163
1164struct ixgbe_addr_filter_info {
1165 u32 num_mc_addrs;
1166 u32 rar_used_count;
1167 u32 mc_addr_in_rar_count;
1168 u32 mta_in_use;
1169};
1170
1171/* Flow control parameters */
1172struct ixgbe_fc_info {
1173 u32 high_water; /* Flow Control High-water */
1174 u32 low_water; /* Flow Control Low-water */
1175 u16 pause_time; /* Flow Control Pause timer */
1176 bool send_xon; /* Flow control send XON */
1177 bool strict_ieee; /* Strict IEEE mode */
1178 enum ixgbe_fc_type type; /* Type of flow control */
1179 enum ixgbe_fc_type original_type;
1180};
1181
1182/* Statistics counters collected by the MAC */
1183struct ixgbe_hw_stats {
1184 u64 crcerrs;
1185 u64 illerrc;
1186 u64 errbc;
1187 u64 mspdc;
1188 u64 mpctotal;
1189 u64 mpc[8];
1190 u64 mlfc;
1191 u64 mrfc;
1192 u64 rlec;
1193 u64 lxontxc;
1194 u64 lxonrxc;
1195 u64 lxofftxc;
1196 u64 lxoffrxc;
1197 u64 pxontxc[8];
1198 u64 pxonrxc[8];
1199 u64 pxofftxc[8];
1200 u64 pxoffrxc[8];
1201 u64 prc64;
1202 u64 prc127;
1203 u64 prc255;
1204 u64 prc511;
1205 u64 prc1023;
1206 u64 prc1522;
1207 u64 gprc;
1208 u64 bprc;
1209 u64 mprc;
1210 u64 gptc;
1211 u64 gorc;
1212 u64 gotc;
1213 u64 rnbc[8];
1214 u64 ruc;
1215 u64 rfc;
1216 u64 roc;
1217 u64 rjc;
1218 u64 mngprc;
1219 u64 mngpdc;
1220 u64 mngptc;
1221 u64 tor;
1222 u64 tpr;
1223 u64 tpt;
1224 u64 ptc64;
1225 u64 ptc127;
1226 u64 ptc255;
1227 u64 ptc511;
1228 u64 ptc1023;
1229 u64 ptc1522;
1230 u64 mptc;
1231 u64 bptc;
1232 u64 xec;
1233 u64 rqsmr[16];
1234 u64 tqsmr[8];
1235 u64 qprc[16];
1236 u64 qptc[16];
1237 u64 qbrc[16];
1238 u64 qbtc[16];
1239};
1240
1241/* forward declaration */
1242struct ixgbe_hw;
1243
1244struct ixgbe_mac_operations {
1245 s32 (*reset)(struct ixgbe_hw *);
1246 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
1247};
1248
1249struct ixgbe_phy_operations {
1250 s32 (*setup)(struct ixgbe_hw *);
1251 s32 (*check)(struct ixgbe_hw *, u32 *, bool *);
1252 s32 (*setup_speed)(struct ixgbe_hw *, u32, bool, bool);
1253 s32 (*get_settings)(struct ixgbe_hw *, u32 *, bool *);
1254};
1255
1256struct ixgbe_mac_info {
1257 struct ixgbe_mac_operations ops;
1258 enum ixgbe_mac_type type;
1259 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1260 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1261 s32 mc_filter_type;
1262 u32 num_rx_queues;
1263 u32 num_tx_queues;
1264 u32 num_rx_addrs;
1265 u32 link_attach_type;
1266 u32 link_mode_select;
1267 bool link_settings_loaded;
1268};
1269
1270
1271struct ixgbe_eeprom_info {
1272 enum ixgbe_eeprom_type type;
1273 u16 word_size;
1274 u16 address_bits;
1275};
1276
1277struct ixgbe_phy_info {
1278 struct ixgbe_phy_operations ops;
1279
1280 enum ixgbe_phy_type type;
1281 u32 addr;
1282 u32 id;
1283 u32 revision;
1284 enum ixgbe_media_type media_type;
1285 u32 autoneg_advertised;
1286 bool autoneg_wait_to_complete;
1287};
1288
1289struct ixgbe_info {
1290 enum ixgbe_mac_type mac;
1291 s32 (*get_invariants)(struct ixgbe_hw *);
1292 struct ixgbe_mac_operations *mac_ops;
1293 struct ixgbe_phy_operations *phy_ops;
1294};
1295
1296struct ixgbe_hw {
1297 u8 __iomem *hw_addr;
1298 void *back;
1299 struct ixgbe_mac_info mac;
1300 struct ixgbe_addr_filter_info addr_ctrl;
1301 struct ixgbe_fc_info fc;
1302 struct ixgbe_phy_info phy;
1303 struct ixgbe_eeprom_info eeprom;
1304 u16 device_id;
1305 u16 vendor_id;
1306 u16 subsystem_device_id;
1307 u16 subsystem_vendor_id;
1308 u8 revision_id;
1309 bool adapter_stopped;
1310};
1311
1312/* Error Codes */
1313#define IXGBE_ERR_EEPROM -1
1314#define IXGBE_ERR_EEPROM_CHECKSUM -2
1315#define IXGBE_ERR_PHY -3
1316#define IXGBE_ERR_CONFIG -4
1317#define IXGBE_ERR_PARAM -5
1318#define IXGBE_ERR_MAC_TYPE -6
1319#define IXGBE_ERR_UNKNOWN_PHY -7
1320#define IXGBE_ERR_LINK_SETUP -8
1321#define IXGBE_ERR_ADAPTER_STOPPED -9
1322#define IXGBE_ERR_INVALID_MAC_ADDR -10
1323#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
1324#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
1325#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
1326#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
1327#define IXGBE_ERR_RESET_FAILED -15
1328#define IXGBE_ERR_SWFW_SYNC -16
1329#define IXGBE_ERR_PHY_ADDR_INVALID -17
1330#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
1331
1332#endif /* _IXGBE_TYPE_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 04:35:03 -0400