diff options
| -rw-r--r-- | arch/blackfin/include/asm/traps.h | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h index 34f7295fb070..3cdc454cde23 100644 --- a/arch/blackfin/include/asm/traps.h +++ b/arch/blackfin/include/asm/traps.h | |||
| @@ -111,9 +111,7 @@ | |||
| 111 | level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" | 111 | level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" |
| 112 | #define EXC_0x2A(level) \ | 112 | #define EXC_0x2A(level) \ |
| 113 | "Instruction fetch misaligned address violation\n" \ | 113 | "Instruction fetch misaligned address violation\n" \ |
| 114 | level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \ | 114 | level " - Attempted misaligned instruction cache fetch.\n" |
| 115 | level " exception, the return address provided in RETX is the destination address which is\n" \ | ||
| 116 | level " misaligned, rather than the address of the offending instruction.\n" | ||
| 117 | #define EXC_0x2B(level) \ | 115 | #define EXC_0x2B(level) \ |
| 118 | "CPLB protection violation\n" \ | 116 | "CPLB protection violation\n" \ |
| 119 | level " - Illegal instruction fetch access (memory protection violation).\n" | 117 | level " - Illegal instruction fetch access (memory protection violation).\n" |