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-rw-r--r--drivers/net/sfc/Kconfig2
-rw-r--r--drivers/net/sfc/efx.c10
-rw-r--r--drivers/net/sfc/ethtool.c18
-rw-r--r--drivers/net/sfc/falcon.c137
-rw-r--r--drivers/net/sfc/falcon_hwdefs.h3
-rw-r--r--drivers/net/sfc/falcon_xmac.c2
-rw-r--r--drivers/net/sfc/mdio_10g.c379
-rw-r--r--drivers/net/sfc/mdio_10g.h281
-rw-r--r--drivers/net/sfc/net_driver.h8
-rw-r--r--drivers/net/sfc/selftest.c21
-rw-r--r--drivers/net/sfc/selftest.h2
-rw-r--r--drivers/net/sfc/tenxpress.c227
-rw-r--r--drivers/net/sfc/xenpack.h15
-rw-r--r--drivers/net/sfc/xfp_phy.c51
14 files changed, 311 insertions, 845 deletions
diff --git a/drivers/net/sfc/Kconfig b/drivers/net/sfc/Kconfig
index 12a82966b577..260aafaac235 100644
--- a/drivers/net/sfc/Kconfig
+++ b/drivers/net/sfc/Kconfig
@@ -1,7 +1,7 @@
1config SFC 1config SFC
2 tristate "Solarflare Solarstorm SFC4000 support" 2 tristate "Solarflare Solarstorm SFC4000 support"
3 depends on PCI && INET 3 depends on PCI && INET
4 select MII 4 select MDIO
5 select CRC32 5 select CRC32
6 select I2C 6 select I2C
7 select I2C_ALGOBIT 7 select I2C_ALGOBIT
diff --git a/drivers/net/sfc/efx.c b/drivers/net/sfc/efx.c
index 7269a426051c..d3e240b736c7 100644
--- a/drivers/net/sfc/efx.c
+++ b/drivers/net/sfc/efx.c
@@ -1300,10 +1300,16 @@ out_requeue:
1300static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1300static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1301{ 1301{
1302 struct efx_nic *efx = netdev_priv(net_dev); 1302 struct efx_nic *efx = netdev_priv(net_dev);
1303 struct mii_ioctl_data *data = if_mii(ifr);
1303 1304
1304 EFX_ASSERT_RESET_SERIALISED(efx); 1305 EFX_ASSERT_RESET_SERIALISED(efx);
1305 1306
1306 return generic_mii_ioctl(&efx->mii, if_mii(ifr), cmd, NULL); 1307 /* Convert phy_id from older PRTAD/DEVAD format */
1308 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) &&
1309 (data->phy_id & 0xfc00) == 0x0400)
1310 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400;
1311
1312 return mdio_mii_ioctl(&efx->mdio, data, cmd);
1307} 1313}
1308 1314
1309/************************************************************************** 1315/**************************************************************************
@@ -1945,7 +1951,7 @@ static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type,
1945 mutex_init(&efx->mac_lock); 1951 mutex_init(&efx->mac_lock);
1946 efx->mac_op = &efx_dummy_mac_operations; 1952 efx->mac_op = &efx_dummy_mac_operations;
1947 efx->phy_op = &efx_dummy_phy_operations; 1953 efx->phy_op = &efx_dummy_phy_operations;
1948 efx->mii.dev = net_dev; 1954 efx->mdio.dev = net_dev;
1949 INIT_WORK(&efx->phy_work, efx_phy_work); 1955 INIT_WORK(&efx->phy_work, efx_phy_work);
1950 INIT_WORK(&efx->mac_work, efx_mac_work); 1956 INIT_WORK(&efx->mac_work, efx_mac_work);
1951 atomic_set(&efx->netif_stop_count, 1); 1957 atomic_set(&efx->netif_stop_count, 1);
diff --git a/drivers/net/sfc/ethtool.c b/drivers/net/sfc/ethtool.c
index 64309f4e8b19..1c7b6849fe01 100644
--- a/drivers/net/sfc/ethtool.c
+++ b/drivers/net/sfc/ethtool.c
@@ -10,6 +10,7 @@
10 10
11#include <linux/netdevice.h> 11#include <linux/netdevice.h>
12#include <linux/ethtool.h> 12#include <linux/ethtool.h>
13#include <linux/mdio.h>
13#include <linux/rtnetlink.h> 14#include <linux/rtnetlink.h>
14#include "net_driver.h" 15#include "net_driver.h"
15#include "workarounds.h" 16#include "workarounds.h"
@@ -345,8 +346,8 @@ static int efx_ethtool_fill_self_tests(struct efx_nic *efx,
345 unsigned int n = 0, i; 346 unsigned int n = 0, i;
346 enum efx_loopback_mode mode; 347 enum efx_loopback_mode mode;
347 348
348 efx_fill_test(n++, strings, data, &tests->mii, 349 efx_fill_test(n++, strings, data, &tests->mdio,
349 "core", 0, "mii", NULL); 350 "core", 0, "mdio", NULL);
350 efx_fill_test(n++, strings, data, &tests->nvram, 351 efx_fill_test(n++, strings, data, &tests->nvram,
351 "core", 0, "nvram", NULL); 352 "core", 0, "nvram", NULL);
352 efx_fill_test(n++, strings, data, &tests->interrupt, 353 efx_fill_test(n++, strings, data, &tests->interrupt,
@@ -529,14 +530,7 @@ static int efx_ethtool_nway_reset(struct net_device *net_dev)
529{ 530{
530 struct efx_nic *efx = netdev_priv(net_dev); 531 struct efx_nic *efx = netdev_priv(net_dev);
531 532
532 if (efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)) { 533 return mdio45_nway_restart(&efx->mdio);
533 mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_AN,
534 MDIO_MMDREG_CTRL1,
535 __ffs(BMCR_ANRESTART), true);
536 return 0;
537 }
538
539 return -EOPNOTSUPP;
540} 534}
541 535
542static u32 efx_ethtool_get_link(struct net_device *net_dev) 536static u32 efx_ethtool_get_link(struct net_device *net_dev)
@@ -689,7 +683,7 @@ static int efx_ethtool_set_pauseparam(struct net_device *net_dev,
689 return -EINVAL; 683 return -EINVAL;
690 } 684 }
691 685
692 if (!(efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)) && 686 if (!(efx->phy_op->mmds & MDIO_DEVS_AN) &&
693 (wanted_fc & EFX_FC_AUTO)) { 687 (wanted_fc & EFX_FC_AUTO)) {
694 EFX_LOG(efx, "PHY does not support flow control " 688 EFX_LOG(efx, "PHY does not support flow control "
695 "autonegotiation\n"); 689 "autonegotiation\n");
@@ -717,7 +711,7 @@ static int efx_ethtool_set_pauseparam(struct net_device *net_dev,
717 mutex_lock(&efx->mac_lock); 711 mutex_lock(&efx->mac_lock);
718 712
719 efx->wanted_fc = wanted_fc; 713 efx->wanted_fc = wanted_fc;
720 mdio_clause45_set_pause(efx); 714 efx_mdio_set_pause(efx);
721 __efx_reconfigure_port(efx); 715 __efx_reconfigure_port(efx);
722 716
723 mutex_unlock(&efx->mac_lock); 717 mutex_unlock(&efx->mac_lock);
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c
index 466a8abb0053..c049364aec46 100644
--- a/drivers/net/sfc/falcon.c
+++ b/drivers/net/sfc/falcon.c
@@ -2063,26 +2063,6 @@ int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2063 ************************************************************************** 2063 **************************************************************************
2064 */ 2064 */
2065 2065
2066/* Use the top bit of the MII PHY id to indicate the PHY type
2067 * (1G/10G), with the remaining bits as the actual PHY id.
2068 *
2069 * This allows us to avoid leaking information from the mii_if_info
2070 * structure into other data structures.
2071 */
2072#define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
2073#define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
2074#define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
2075#define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
2076#define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
2077
2078
2079/* Packing the clause 45 port and device fields into a single value */
2080#define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
2081#define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
2082#define MD_DEV_ADR_COMP_LBN 0
2083#define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
2084
2085
2086/* Wait for GMII access to complete */ 2066/* Wait for GMII access to complete */
2087static int falcon_gmii_wait(struct efx_nic *efx) 2067static int falcon_gmii_wait(struct efx_nic *efx)
2088{ 2068{
@@ -2108,49 +2088,29 @@ static int falcon_gmii_wait(struct efx_nic *efx)
2108 return -ETIMEDOUT; 2088 return -ETIMEDOUT;
2109} 2089}
2110 2090
2111/* Writes a GMII register of a PHY connected to Falcon using MDIO. */ 2091/* Write an MDIO register of a PHY connected to Falcon. */
2112static void falcon_mdio_write(struct net_device *net_dev, int phy_id, 2092static int falcon_mdio_write(struct net_device *net_dev,
2113 int addr, int value) 2093 int prtad, int devad, u16 addr, u16 value)
2114{ 2094{
2115 struct efx_nic *efx = netdev_priv(net_dev); 2095 struct efx_nic *efx = netdev_priv(net_dev);
2116 unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
2117 efx_oword_t reg; 2096 efx_oword_t reg;
2097 int rc;
2118 2098
2119 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently 2099 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
2120 * chosen so that the only current user, Falcon, can take the 2100 prtad, devad, addr, value);
2121 * packed value and use them directly.
2122 * Fail to build if this assumption is broken.
2123 */
2124 BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
2125 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
2126 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
2127 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
2128
2129 if (phy_id2 == PHY_ADDR_INVALID)
2130 return;
2131
2132 /* See falcon_mdio_read for an explanation. */
2133 if (!(phy_id & FALCON_PHY_ID_10G)) {
2134 int mmd = ffs(efx->phy_op->mmds) - 1;
2135 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
2136 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
2137 & FALCON_PHY_ID_ID_MASK;
2138 }
2139
2140 EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
2141 addr, value);
2142 2101
2143 spin_lock_bh(&efx->phy_lock); 2102 spin_lock_bh(&efx->phy_lock);
2144 2103
2145 /* Check MII not currently being accessed */ 2104 /* Check MDIO not currently being accessed */
2146 if (falcon_gmii_wait(efx) != 0) 2105 rc = falcon_gmii_wait(efx);
2106 if (rc)
2147 goto out; 2107 goto out;
2148 2108
2149 /* Write the address/ID register */ 2109 /* Write the address/ID register */
2150 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr); 2110 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2151 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER); 2111 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2152 2112
2153 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2); 2113 EFX_POPULATE_OWORD_2(reg, MD_PRT_ADR, prtad, MD_DEV_ADR, devad);
2154 falcon_write(efx, &reg, MD_ID_REG_KER); 2114 falcon_write(efx, &reg, MD_ID_REG_KER);
2155 2115
2156 /* Write data */ 2116 /* Write data */
@@ -2163,7 +2123,8 @@ static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
2163 falcon_write(efx, &reg, MD_CS_REG_KER); 2123 falcon_write(efx, &reg, MD_CS_REG_KER);
2164 2124
2165 /* Wait for data to be written */ 2125 /* Wait for data to be written */
2166 if (falcon_gmii_wait(efx) != 0) { 2126 rc = falcon_gmii_wait(efx);
2127 if (rc) {
2167 /* Abort the write operation */ 2128 /* Abort the write operation */
2168 EFX_POPULATE_OWORD_2(reg, 2129 EFX_POPULATE_OWORD_2(reg,
2169 MD_WRC, 0, 2130 MD_WRC, 0,
@@ -2174,45 +2135,28 @@ static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
2174 2135
2175 out: 2136 out:
2176 spin_unlock_bh(&efx->phy_lock); 2137 spin_unlock_bh(&efx->phy_lock);
2138 return rc;
2177} 2139}
2178 2140
2179/* Reads a GMII register from a PHY connected to Falcon. If no value 2141/* Read an MDIO register of a PHY connected to Falcon. */
2180 * could be read, -1 will be returned. */ 2142static int falcon_mdio_read(struct net_device *net_dev,
2181static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr) 2143 int prtad, int devad, u16 addr)
2182{ 2144{
2183 struct efx_nic *efx = netdev_priv(net_dev); 2145 struct efx_nic *efx = netdev_priv(net_dev);
2184 unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2185 efx_oword_t reg; 2146 efx_oword_t reg;
2186 int value = -1; 2147 int rc;
2187
2188 if (phy_addr == PHY_ADDR_INVALID)
2189 return -1;
2190
2191 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2192 * but the generic Linux code does not make any distinction or have
2193 * any state for this.
2194 * We spot the case where someone tried to talk 22 to a 45 PHY and
2195 * redirect the request to the lowest numbered MMD as a clause45
2196 * request. This is enough to allow simple queries like id and link
2197 * state to succeed. TODO: We may need to do more in future.
2198 */
2199 if (!(phy_id & FALCON_PHY_ID_10G)) {
2200 int mmd = ffs(efx->phy_op->mmds) - 1;
2201 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2202 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2203 & FALCON_PHY_ID_ID_MASK;
2204 }
2205 2148
2206 spin_lock_bh(&efx->phy_lock); 2149 spin_lock_bh(&efx->phy_lock);
2207 2150
2208 /* Check MII not currently being accessed */ 2151 /* Check MDIO not currently being accessed */
2209 if (falcon_gmii_wait(efx) != 0) 2152 rc = falcon_gmii_wait(efx);
2153 if (rc)
2210 goto out; 2154 goto out;
2211 2155
2212 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr); 2156 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2213 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER); 2157 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2214 2158
2215 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr); 2159 EFX_POPULATE_OWORD_2(reg, MD_PRT_ADR, prtad, MD_DEV_ADR, devad);
2216 falcon_write(efx, &reg, MD_ID_REG_KER); 2160 falcon_write(efx, &reg, MD_ID_REG_KER);
2217 2161
2218 /* Request data to be read */ 2162 /* Request data to be read */
@@ -2220,12 +2164,12 @@ static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2220 falcon_write(efx, &reg, MD_CS_REG_KER); 2164 falcon_write(efx, &reg, MD_CS_REG_KER);
2221 2165
2222 /* Wait for data to become available */ 2166 /* Wait for data to become available */
2223 value = falcon_gmii_wait(efx); 2167 rc = falcon_gmii_wait(efx);
2224 if (value == 0) { 2168 if (rc == 0) {
2225 falcon_read(efx, &reg, MD_RXD_REG_KER); 2169 falcon_read(efx, &reg, MD_RXD_REG_KER);
2226 value = EFX_OWORD_FIELD(reg, MD_RXD); 2170 rc = EFX_OWORD_FIELD(reg, MD_RXD);
2227 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n", 2171 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2228 phy_id, addr, value); 2172 prtad, devad, addr, rc);
2229 } else { 2173 } else {
2230 /* Abort the read operation */ 2174 /* Abort the read operation */
2231 EFX_POPULATE_OWORD_2(reg, 2175 EFX_POPULATE_OWORD_2(reg,
@@ -2233,22 +2177,13 @@ static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2233 MD_GC, 1); 2177 MD_GC, 1);
2234 falcon_write(efx, &reg, MD_CS_REG_KER); 2178 falcon_write(efx, &reg, MD_CS_REG_KER);
2235 2179
2236 EFX_LOG(efx, "read from GMII 0x%x register %02x, got " 2180 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2237 "error %d\n", phy_id, addr, value); 2181 prtad, devad, addr, rc);
2238 } 2182 }
2239 2183
2240 out: 2184 out:
2241 spin_unlock_bh(&efx->phy_lock); 2185 spin_unlock_bh(&efx->phy_lock);
2242 2186 return rc;
2243 return value;
2244}
2245
2246static void falcon_init_mdio(struct mii_if_info *gmii)
2247{
2248 gmii->mdio_read = falcon_mdio_read;
2249 gmii->mdio_write = falcon_mdio_write;
2250 gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2251 gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2252} 2187}
2253 2188
2254static int falcon_probe_phy(struct efx_nic *efx) 2189static int falcon_probe_phy(struct efx_nic *efx)
@@ -2342,9 +2277,11 @@ int falcon_probe_port(struct efx_nic *efx)
2342 if (rc) 2277 if (rc)
2343 return rc; 2278 return rc;
2344 2279
2345 /* Set up GMII structure for PHY */ 2280 /* Set up MDIO structure for PHY */
2346 efx->mii.supports_gmii = true; 2281 efx->mdio.mmds = efx->phy_op->mmds;
2347 falcon_init_mdio(&efx->mii); 2282 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
2283 efx->mdio.mdio_read = falcon_mdio_read;
2284 efx->mdio.mdio_write = falcon_mdio_write;
2348 2285
2349 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ 2286 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2350 if (falcon_rev(efx) >= FALCON_REV_B0) 2287 if (falcon_rev(efx) >= FALCON_REV_B0)
@@ -2761,7 +2698,7 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
2761 if (rc == -EINVAL) { 2698 if (rc == -EINVAL) {
2762 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n"); 2699 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2763 efx->phy_type = PHY_TYPE_NONE; 2700 efx->phy_type = PHY_TYPE_NONE;
2764 efx->mii.phy_id = PHY_ADDR_INVALID; 2701 efx->mdio.prtad = MDIO_PRTAD_NONE;
2765 board_rev = 0; 2702 board_rev = 0;
2766 rc = 0; 2703 rc = 0;
2767 } else if (rc) { 2704 } else if (rc) {
@@ -2771,7 +2708,7 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
2771 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3; 2708 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2772 2709
2773 efx->phy_type = v2->port0_phy_type; 2710 efx->phy_type = v2->port0_phy_type;
2774 efx->mii.phy_id = v2->port0_phy_addr; 2711 efx->mdio.prtad = v2->port0_phy_addr;
2775 board_rev = le16_to_cpu(v2->board_revision); 2712 board_rev = le16_to_cpu(v2->board_revision);
2776 2713
2777 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { 2714 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
@@ -2793,7 +2730,7 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
2793 /* Read the MAC addresses */ 2730 /* Read the MAC addresses */
2794 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN); 2731 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2795 2732
2796 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id); 2733 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
2797 2734
2798 efx_set_board_info(efx, board_rev); 2735 efx_set_board_info(efx, board_rev);
2799 2736
diff --git a/drivers/net/sfc/falcon_hwdefs.h b/drivers/net/sfc/falcon_hwdefs.h
index bda8d5bb72e4..375e2a5961ec 100644
--- a/drivers/net/sfc/falcon_hwdefs.h
+++ b/drivers/net/sfc/falcon_hwdefs.h
@@ -456,9 +456,6 @@
456#define MD_PRT_ADR_WIDTH 5 456#define MD_PRT_ADR_WIDTH 5
457#define MD_DEV_ADR_LBN 6 457#define MD_DEV_ADR_LBN 6
458#define MD_DEV_ADR_WIDTH 5 458#define MD_DEV_ADR_WIDTH 5
459/* Used for writing both at once */
460#define MD_PRT_DEV_ADR_LBN 6
461#define MD_PRT_DEV_ADR_WIDTH 10
462 459
463/* PHY management status & mask register (DWORD read only) */ 460/* PHY management status & mask register (DWORD read only) */
464#define MD_STAT_REG_KER 0xc50 461#define MD_STAT_REG_KER 0xc50
diff --git a/drivers/net/sfc/falcon_xmac.c b/drivers/net/sfc/falcon_xmac.c
index 5a03713685ac..2b3269c03263 100644
--- a/drivers/net/sfc/falcon_xmac.c
+++ b/drivers/net/sfc/falcon_xmac.c
@@ -133,7 +133,7 @@ bool falcon_xaui_link_ok(struct efx_nic *efx)
133 /* If the link is up, then check the phy side of the xaui link */ 133 /* If the link is up, then check the phy side of the xaui link */
134 if (efx->link_up && link_ok) 134 if (efx->link_up && link_ok)
135 if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS)) 135 if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS))
136 link_ok = mdio_clause45_phyxgxs_lane_sync(efx); 136 link_ok = efx_mdio_phyxgxs_lane_sync(efx);
137 137
138 return link_ok; 138 return link_ok;
139} 139}
diff --git a/drivers/net/sfc/mdio_10g.c b/drivers/net/sfc/mdio_10g.c
index 9f5ec3eb3418..11c231a1f875 100644
--- a/drivers/net/sfc/mdio_10g.c
+++ b/drivers/net/sfc/mdio_10g.c
@@ -17,7 +17,7 @@
17#include "boards.h" 17#include "boards.h"
18#include "workarounds.h" 18#include "workarounds.h"
19 19
20unsigned mdio_id_oui(u32 id) 20unsigned efx_mdio_id_oui(u32 id)
21{ 21{
22 unsigned oui = 0; 22 unsigned oui = 0;
23 int i; 23 int i;
@@ -32,52 +32,45 @@ unsigned mdio_id_oui(u32 id)
32 return oui; 32 return oui;
33} 33}
34 34
35int mdio_clause45_reset_mmd(struct efx_nic *port, int mmd, 35int efx_mdio_reset_mmd(struct efx_nic *port, int mmd,
36 int spins, int spintime) 36 int spins, int spintime)
37{ 37{
38 u32 ctrl; 38 u32 ctrl;
39 int phy_id = port->mii.phy_id;
40 39
41 /* Catch callers passing values in the wrong units (or just silly) */ 40 /* Catch callers passing values in the wrong units (or just silly) */
42 EFX_BUG_ON_PARANOID(spins * spintime >= 5000); 41 EFX_BUG_ON_PARANOID(spins * spintime >= 5000);
43 42
44 mdio_clause45_write(port, phy_id, mmd, MDIO_MMDREG_CTRL1, 43 efx_mdio_write(port, mmd, MDIO_CTRL1, MDIO_CTRL1_RESET);
45 (1 << MDIO_MMDREG_CTRL1_RESET_LBN));
46 /* Wait for the reset bit to clear. */ 44 /* Wait for the reset bit to clear. */
47 do { 45 do {
48 msleep(spintime); 46 msleep(spintime);
49 ctrl = mdio_clause45_read(port, phy_id, mmd, MDIO_MMDREG_CTRL1); 47 ctrl = efx_mdio_read(port, mmd, MDIO_CTRL1);
50 spins--; 48 spins--;
51 49
52 } while (spins && (ctrl & (1 << MDIO_MMDREG_CTRL1_RESET_LBN))); 50 } while (spins && (ctrl & MDIO_CTRL1_RESET));
53 51
54 return spins ? spins : -ETIMEDOUT; 52 return spins ? spins : -ETIMEDOUT;
55} 53}
56 54
57static int mdio_clause45_check_mmd(struct efx_nic *efx, int mmd, 55static int efx_mdio_check_mmd(struct efx_nic *efx, int mmd, int fault_fatal)
58 int fault_fatal)
59{ 56{
60 int status; 57 int status;
61 int phy_id = efx->mii.phy_id;
62 58
63 if (LOOPBACK_INTERNAL(efx)) 59 if (LOOPBACK_INTERNAL(efx))
64 return 0; 60 return 0;
65 61
66 if (mmd != MDIO_MMD_AN) { 62 if (mmd != MDIO_MMD_AN) {
67 /* Read MMD STATUS2 to check it is responding. */ 63 /* Read MMD STATUS2 to check it is responding. */
68 status = mdio_clause45_read(efx, phy_id, mmd, 64 status = efx_mdio_read(efx, mmd, MDIO_STAT2);
69 MDIO_MMDREG_STAT2); 65 if ((status & MDIO_STAT2_DEVPRST) != MDIO_STAT2_DEVPRST_VAL) {
70 if (((status >> MDIO_MMDREG_STAT2_PRESENT_LBN) &
71 ((1 << MDIO_MMDREG_STAT2_PRESENT_WIDTH) - 1)) !=
72 MDIO_MMDREG_STAT2_PRESENT_VAL) {
73 EFX_ERR(efx, "PHY MMD %d not responding.\n", mmd); 66 EFX_ERR(efx, "PHY MMD %d not responding.\n", mmd);
74 return -EIO; 67 return -EIO;
75 } 68 }
76 } 69 }
77 70
78 /* Read MMD STATUS 1 to check for fault. */ 71 /* Read MMD STATUS 1 to check for fault. */
79 status = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_STAT1); 72 status = efx_mdio_read(efx, mmd, MDIO_STAT1);
80 if ((status & (1 << MDIO_MMDREG_STAT1_FAULT_LBN)) != 0) { 73 if (status & MDIO_STAT1_FAULT) {
81 if (fault_fatal) { 74 if (fault_fatal) {
82 EFX_ERR(efx, "PHY MMD %d reporting fatal" 75 EFX_ERR(efx, "PHY MMD %d reporting fatal"
83 " fault: status %x\n", mmd, status); 76 " fault: status %x\n", mmd, status);
@@ -94,8 +87,7 @@ static int mdio_clause45_check_mmd(struct efx_nic *efx, int mmd,
94#define MDIO45_RESET_TIME 1000 /* ms */ 87#define MDIO45_RESET_TIME 1000 /* ms */
95#define MDIO45_RESET_ITERS 100 88#define MDIO45_RESET_ITERS 100
96 89
97int mdio_clause45_wait_reset_mmds(struct efx_nic *efx, 90int efx_mdio_wait_reset_mmds(struct efx_nic *efx, unsigned int mmd_mask)
98 unsigned int mmd_mask)
99{ 91{
100 const int spintime = MDIO45_RESET_TIME / MDIO45_RESET_ITERS; 92 const int spintime = MDIO45_RESET_TIME / MDIO45_RESET_ITERS;
101 int tries = MDIO45_RESET_ITERS; 93 int tries = MDIO45_RESET_ITERS;
@@ -109,16 +101,13 @@ int mdio_clause45_wait_reset_mmds(struct efx_nic *efx,
109 in_reset = 0; 101 in_reset = 0;
110 while (mask) { 102 while (mask) {
111 if (mask & 1) { 103 if (mask & 1) {
112 stat = mdio_clause45_read(efx, 104 stat = efx_mdio_read(efx, mmd, MDIO_CTRL1);
113 efx->mii.phy_id,
114 mmd,
115 MDIO_MMDREG_CTRL1);
116 if (stat < 0) { 105 if (stat < 0) {
117 EFX_ERR(efx, "failed to read status of" 106 EFX_ERR(efx, "failed to read status of"
118 " MMD %d\n", mmd); 107 " MMD %d\n", mmd);
119 return -EIO; 108 return -EIO;
120 } 109 }
121 if (stat & (1 << MDIO_MMDREG_CTRL1_RESET_LBN)) 110 if (stat & MDIO_CTRL1_RESET)
122 in_reset |= (1 << mmd); 111 in_reset |= (1 << mmd);
123 } 112 }
124 mask = mask >> 1; 113 mask = mask >> 1;
@@ -137,28 +126,26 @@ int mdio_clause45_wait_reset_mmds(struct efx_nic *efx,
137 return rc; 126 return rc;
138} 127}
139 128
140int mdio_clause45_check_mmds(struct efx_nic *efx, 129int efx_mdio_check_mmds(struct efx_nic *efx,
141 unsigned int mmd_mask, unsigned int fatal_mask) 130 unsigned int mmd_mask, unsigned int fatal_mask)
142{ 131{
143 int mmd = 0, probe_mmd, devs0, devs1; 132 int mmd = 0, probe_mmd, devs1, devs2;
144 u32 devices; 133 u32 devices;
145 134
146 /* Historically we have probed the PHYXS to find out what devices are 135 /* Historically we have probed the PHYXS to find out what devices are
147 * present,but that doesn't work so well if the PHYXS isn't expected 136 * present,but that doesn't work so well if the PHYXS isn't expected
148 * to exist, if so just find the first item in the list supplied. */ 137 * to exist, if so just find the first item in the list supplied. */
149 probe_mmd = (mmd_mask & MDIO_MMDREG_DEVS_PHYXS) ? MDIO_MMD_PHYXS : 138 probe_mmd = (mmd_mask & MDIO_DEVS_PHYXS) ? MDIO_MMD_PHYXS :
150 __ffs(mmd_mask); 139 __ffs(mmd_mask);
151 140
152 /* Check all the expected MMDs are present */ 141 /* Check all the expected MMDs are present */
153 devs0 = mdio_clause45_read(efx, efx->mii.phy_id, 142 devs1 = efx_mdio_read(efx, probe_mmd, MDIO_DEVS1);
154 probe_mmd, MDIO_MMDREG_DEVS0); 143 devs2 = efx_mdio_read(efx, probe_mmd, MDIO_DEVS2);
155 devs1 = mdio_clause45_read(efx, efx->mii.phy_id, 144 if (devs1 < 0 || devs2 < 0) {
156 probe_mmd, MDIO_MMDREG_DEVS1);
157 if (devs0 < 0 || devs1 < 0) {
158 EFX_ERR(efx, "failed to read devices present\n"); 145 EFX_ERR(efx, "failed to read devices present\n");
159 return -EIO; 146 return -EIO;
160 } 147 }
161 devices = devs0 | (devs1 << 16); 148 devices = devs1 | (devs2 << 16);
162 if ((devices & mmd_mask) != mmd_mask) { 149 if ((devices & mmd_mask) != mmd_mask) {
163 EFX_ERR(efx, "required MMDs not present: got %x, " 150 EFX_ERR(efx, "required MMDs not present: got %x, "
164 "wanted %x\n", devices, mmd_mask); 151 "wanted %x\n", devices, mmd_mask);
@@ -170,7 +157,7 @@ int mdio_clause45_check_mmds(struct efx_nic *efx,
170 while (mmd_mask) { 157 while (mmd_mask) {
171 if (mmd_mask & 1) { 158 if (mmd_mask & 1) {
172 int fault_fatal = fatal_mask & 1; 159 int fault_fatal = fatal_mask & 1;
173 if (mdio_clause45_check_mmd(efx, mmd, fault_fatal)) 160 if (efx_mdio_check_mmd(efx, mmd, fault_fatal))
174 return -EIO; 161 return -EIO;
175 } 162 }
176 mmd_mask = mmd_mask >> 1; 163 mmd_mask = mmd_mask >> 1;
@@ -181,13 +168,8 @@ int mdio_clause45_check_mmds(struct efx_nic *efx,
181 return 0; 168 return 0;
182} 169}
183 170
184bool mdio_clause45_links_ok(struct efx_nic *efx, unsigned int mmd_mask) 171bool efx_mdio_links_ok(struct efx_nic *efx, unsigned int mmd_mask)
185{ 172{
186 int phy_id = efx->mii.phy_id;
187 u32 reg;
188 bool ok = true;
189 int mmd = 0;
190
191 /* If the port is in loopback, then we should only consider a subset 173 /* If the port is in loopback, then we should only consider a subset
192 * of mmd's */ 174 * of mmd's */
193 if (LOOPBACK_INTERNAL(efx)) 175 if (LOOPBACK_INTERNAL(efx))
@@ -197,241 +179,75 @@ bool mdio_clause45_links_ok(struct efx_nic *efx, unsigned int mmd_mask)
197 else if (efx_phy_mode_disabled(efx->phy_mode)) 179 else if (efx_phy_mode_disabled(efx->phy_mode))
198 return false; 180 return false;
199 else if (efx->loopback_mode == LOOPBACK_PHYXS) 181 else if (efx->loopback_mode == LOOPBACK_PHYXS)
200 mmd_mask &= ~(MDIO_MMDREG_DEVS_PHYXS | 182 mmd_mask &= ~(MDIO_DEVS_PHYXS |
201 MDIO_MMDREG_DEVS_PCS | 183 MDIO_DEVS_PCS |
202 MDIO_MMDREG_DEVS_PMAPMD | 184 MDIO_DEVS_PMAPMD |
203 MDIO_MMDREG_DEVS_AN); 185 MDIO_DEVS_AN);
204 else if (efx->loopback_mode == LOOPBACK_PCS) 186 else if (efx->loopback_mode == LOOPBACK_PCS)
205 mmd_mask &= ~(MDIO_MMDREG_DEVS_PCS | 187 mmd_mask &= ~(MDIO_DEVS_PCS |
206 MDIO_MMDREG_DEVS_PMAPMD | 188 MDIO_DEVS_PMAPMD |
207 MDIO_MMDREG_DEVS_AN); 189 MDIO_DEVS_AN);
208 else if (efx->loopback_mode == LOOPBACK_PMAPMD) 190 else if (efx->loopback_mode == LOOPBACK_PMAPMD)
209 mmd_mask &= ~(MDIO_MMDREG_DEVS_PMAPMD | 191 mmd_mask &= ~(MDIO_DEVS_PMAPMD |
210 MDIO_MMDREG_DEVS_AN); 192 MDIO_DEVS_AN);
211
212 if (!mmd_mask) {
213 /* Use presence of XGMII faults in leui of link state */
214 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,
215 MDIO_PHYXS_STATUS2);
216 return !(reg & (1 << MDIO_PHYXS_STATUS2_RX_FAULT_LBN));
217 }
218 193
219 while (mmd_mask) { 194 return mdio45_links_ok(&efx->mdio, mmd_mask);
220 if (mmd_mask & 1) {
221 /* Double reads because link state is latched, and a
222 * read moves the current state into the register */
223 reg = mdio_clause45_read(efx, phy_id,
224 mmd, MDIO_MMDREG_STAT1);
225 reg = mdio_clause45_read(efx, phy_id,
226 mmd, MDIO_MMDREG_STAT1);
227 ok = ok && (reg & (1 << MDIO_MMDREG_STAT1_LINK_LBN));
228 }
229 mmd_mask = (mmd_mask >> 1);
230 mmd++;
231 }
232 return ok;
233} 195}
234 196
235void mdio_clause45_transmit_disable(struct efx_nic *efx) 197void efx_mdio_transmit_disable(struct efx_nic *efx)
236{ 198{
237 mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, 199 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD,
238 MDIO_MMDREG_TXDIS, MDIO_MMDREG_TXDIS_GLOBAL_LBN, 200 MDIO_PMA_TXDIS, MDIO_PMD_TXDIS_GLOBAL,
239 efx->phy_mode & PHY_MODE_TX_DISABLED); 201 efx->phy_mode & PHY_MODE_TX_DISABLED);
240} 202}
241 203
242void mdio_clause45_phy_reconfigure(struct efx_nic *efx) 204void efx_mdio_phy_reconfigure(struct efx_nic *efx)
243{ 205{
244 int phy_id = efx->mii.phy_id; 206 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD,
245 207 MDIO_CTRL1, MDIO_PMA_CTRL1_LOOPBACK,
246 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD, 208 efx->loopback_mode == LOOPBACK_PMAPMD);
247 MDIO_MMDREG_CTRL1, MDIO_PMAPMD_CTRL1_LBACK_LBN, 209 efx_mdio_set_flag(efx, MDIO_MMD_PCS,
248 efx->loopback_mode == LOOPBACK_PMAPMD); 210 MDIO_CTRL1, MDIO_PCS_CTRL1_LOOPBACK,
249 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PCS, 211 efx->loopback_mode == LOOPBACK_PCS);
250 MDIO_MMDREG_CTRL1, MDIO_MMDREG_CTRL1_LBACK_LBN, 212 efx_mdio_set_flag(efx, MDIO_MMD_PHYXS,
251 efx->loopback_mode == LOOPBACK_PCS); 213 MDIO_CTRL1, MDIO_PHYXS_CTRL1_LOOPBACK,
252 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS, 214 efx->loopback_mode == LOOPBACK_NETWORK);
253 MDIO_MMDREG_CTRL1, MDIO_MMDREG_CTRL1_LBACK_LBN,
254 efx->loopback_mode == LOOPBACK_NETWORK);
255} 215}
256 216
257static void mdio_clause45_set_mmd_lpower(struct efx_nic *efx, 217static void efx_mdio_set_mmd_lpower(struct efx_nic *efx,
258 int lpower, int mmd) 218 int lpower, int mmd)
259{ 219{
260 int phy = efx->mii.phy_id; 220 int stat = efx_mdio_read(efx, mmd, MDIO_STAT1);
261 int stat = mdio_clause45_read(efx, phy, mmd, MDIO_MMDREG_STAT1);
262 221
263 EFX_TRACE(efx, "Setting low power mode for MMD %d to %d\n", 222 EFX_TRACE(efx, "Setting low power mode for MMD %d to %d\n",
264 mmd, lpower); 223 mmd, lpower);
265 224
266 if (stat & (1 << MDIO_MMDREG_STAT1_LPABLE_LBN)) { 225 if (stat & MDIO_STAT1_LPOWERABLE) {
267 mdio_clause45_set_flag(efx, phy, mmd, MDIO_MMDREG_CTRL1, 226 efx_mdio_set_flag(efx, mmd, MDIO_CTRL1,
268 MDIO_MMDREG_CTRL1_LPOWER_LBN, lpower); 227 MDIO_CTRL1_LPOWER, lpower);
269 } 228 }
270} 229}
271 230
272void mdio_clause45_set_mmds_lpower(struct efx_nic *efx, 231void efx_mdio_set_mmds_lpower(struct efx_nic *efx,
273 int low_power, unsigned int mmd_mask) 232 int low_power, unsigned int mmd_mask)
274{ 233{
275 int mmd = 0; 234 int mmd = 0;
276 mmd_mask &= ~MDIO_MMDREG_DEVS_AN; 235 mmd_mask &= ~MDIO_DEVS_AN;
277 while (mmd_mask) { 236 while (mmd_mask) {
278 if (mmd_mask & 1) 237 if (mmd_mask & 1)
279 mdio_clause45_set_mmd_lpower(efx, low_power, mmd); 238 efx_mdio_set_mmd_lpower(efx, low_power, mmd);
280 mmd_mask = (mmd_mask >> 1); 239 mmd_mask = (mmd_mask >> 1);
281 mmd++; 240 mmd++;
282 } 241 }
283} 242}
284 243
285static u32 mdio_clause45_get_an(struct efx_nic *efx, u16 addr)
286{
287 int phy_id = efx->mii.phy_id;
288 u32 result = 0;
289 int reg;
290
291 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, addr);
292 if (reg & ADVERTISE_10HALF)
293 result |= ADVERTISED_10baseT_Half;
294 if (reg & ADVERTISE_10FULL)
295 result |= ADVERTISED_10baseT_Full;
296 if (reg & ADVERTISE_100HALF)
297 result |= ADVERTISED_100baseT_Half;
298 if (reg & ADVERTISE_100FULL)
299 result |= ADVERTISED_100baseT_Full;
300 return result;
301}
302
303/**
304 * mdio_clause45_get_settings - Read (some of) the PHY settings over MDIO.
305 * @efx: Efx NIC
306 * @ecmd: Buffer for settings
307 *
308 * On return the 'port', 'speed', 'supported' and 'advertising' fields of
309 * ecmd have been filled out.
310 */
311void mdio_clause45_get_settings(struct efx_nic *efx,
312 struct ethtool_cmd *ecmd)
313{
314 mdio_clause45_get_settings_ext(efx, ecmd, 0, 0);
315}
316
317/** 244/**
318 * mdio_clause45_get_settings_ext - Read (some of) the PHY settings over MDIO. 245 * efx_mdio_set_settings - Set (some of) the PHY settings over MDIO.
319 * @efx: Efx NIC
320 * @ecmd: Buffer for settings
321 * @xnp: Advertised Extended Next Page state
322 * @xnp_lpa: Link Partner's advertised XNP state
323 *
324 * On return the 'port', 'speed', 'supported' and 'advertising' fields of
325 * ecmd have been filled out.
326 */
327void mdio_clause45_get_settings_ext(struct efx_nic *efx,
328 struct ethtool_cmd *ecmd,
329 u32 npage_adv, u32 npage_lpa)
330{
331 int phy_id = efx->mii.phy_id;
332 int reg;
333
334 ecmd->transceiver = XCVR_INTERNAL;
335 ecmd->phy_address = phy_id;
336
337 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
338 MDIO_MMDREG_CTRL2);
339 switch (reg & MDIO_PMAPMD_CTRL2_TYPE_MASK) {
340 case MDIO_PMAPMD_CTRL2_10G_BT:
341 case MDIO_PMAPMD_CTRL2_1G_BT:
342 case MDIO_PMAPMD_CTRL2_100_BT:
343 case MDIO_PMAPMD_CTRL2_10_BT:
344 ecmd->port = PORT_TP;
345 ecmd->supported = SUPPORTED_TP;
346 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
347 MDIO_MMDREG_SPEED);
348 if (reg & (1 << MDIO_MMDREG_SPEED_10G_LBN))
349 ecmd->supported |= SUPPORTED_10000baseT_Full;
350 if (reg & (1 << MDIO_MMDREG_SPEED_1000M_LBN))
351 ecmd->supported |= (SUPPORTED_1000baseT_Full |
352 SUPPORTED_1000baseT_Half);
353 if (reg & (1 << MDIO_MMDREG_SPEED_100M_LBN))
354 ecmd->supported |= (SUPPORTED_100baseT_Full |
355 SUPPORTED_100baseT_Half);
356 if (reg & (1 << MDIO_MMDREG_SPEED_10M_LBN))
357 ecmd->supported |= (SUPPORTED_10baseT_Full |
358 SUPPORTED_10baseT_Half);
359 ecmd->advertising = ADVERTISED_TP;
360 break;
361
362 /* We represent CX4 as fibre in the absence of anything better */
363 case MDIO_PMAPMD_CTRL2_10G_CX4:
364 /* All the other defined modes are flavours of optical */
365 default:
366 ecmd->port = PORT_FIBRE;
367 ecmd->supported = SUPPORTED_FIBRE;
368 ecmd->advertising = ADVERTISED_FIBRE;
369 break;
370 }
371
372 if (efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)) {
373 ecmd->supported |= SUPPORTED_Autoneg;
374 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
375 MDIO_MMDREG_CTRL1);
376 if (reg & BMCR_ANENABLE) {
377 ecmd->autoneg = AUTONEG_ENABLE;
378 ecmd->advertising |=
379 ADVERTISED_Autoneg |
380 mdio_clause45_get_an(efx, MDIO_AN_ADVERTISE) |
381 npage_adv;
382 } else
383 ecmd->autoneg = AUTONEG_DISABLE;
384 } else
385 ecmd->autoneg = AUTONEG_DISABLE;
386
387 if (ecmd->autoneg) {
388 /* If AN is complete, report best common mode,
389 * otherwise report best advertised mode. */
390 u32 modes = 0;
391 if (mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
392 MDIO_MMDREG_STAT1) &
393 (1 << MDIO_AN_STATUS_AN_DONE_LBN))
394 modes = (ecmd->advertising &
395 (mdio_clause45_get_an(efx, MDIO_AN_LPA) |
396 npage_lpa));
397 if (modes == 0)
398 modes = ecmd->advertising;
399
400 if (modes & ADVERTISED_10000baseT_Full) {
401 ecmd->speed = SPEED_10000;
402 ecmd->duplex = DUPLEX_FULL;
403 } else if (modes & (ADVERTISED_1000baseT_Full |
404 ADVERTISED_1000baseT_Half)) {
405 ecmd->speed = SPEED_1000;
406 ecmd->duplex = !!(modes & ADVERTISED_1000baseT_Full);
407 } else if (modes & (ADVERTISED_100baseT_Full |
408 ADVERTISED_100baseT_Half)) {
409 ecmd->speed = SPEED_100;
410 ecmd->duplex = !!(modes & ADVERTISED_100baseT_Full);
411 } else {
412 ecmd->speed = SPEED_10;
413 ecmd->duplex = !!(modes & ADVERTISED_10baseT_Full);
414 }
415 } else {
416 /* Report forced settings */
417 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD,
418 MDIO_MMDREG_CTRL1);
419 ecmd->speed = (((reg & BMCR_SPEED1000) ? 100 : 1) *
420 ((reg & BMCR_SPEED100) ? 100 : 10));
421 ecmd->duplex = (reg & BMCR_FULLDPLX ||
422 ecmd->speed == SPEED_10000);
423 }
424}
425
426/**
427 * mdio_clause45_set_settings - Set (some of) the PHY settings over MDIO.
428 * @efx: Efx NIC 246 * @efx: Efx NIC
429 * @ecmd: New settings 247 * @ecmd: New settings
430 */ 248 */
431int mdio_clause45_set_settings(struct efx_nic *efx, 249int efx_mdio_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
432 struct ethtool_cmd *ecmd)
433{ 250{
434 int phy_id = efx->mii.phy_id;
435 struct ethtool_cmd prev; 251 struct ethtool_cmd prev;
436 u32 required; 252 u32 required;
437 int reg; 253 int reg;
@@ -489,94 +305,67 @@ int mdio_clause45_set_settings(struct efx_nic *efx,
489 ADVERTISED_1000baseT_Full)) 305 ADVERTISED_1000baseT_Full))
490 reg |= ADVERTISE_NPAGE; 306 reg |= ADVERTISE_NPAGE;
491 reg |= efx_fc_advertise(efx->wanted_fc); 307 reg |= efx_fc_advertise(efx->wanted_fc);
492 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN, 308 efx_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
493 MDIO_AN_ADVERTISE, reg);
494 309
495 /* Set up the (extended) next page if necessary */ 310 /* Set up the (extended) next page if necessary */
496 if (efx->phy_op->set_npage_adv) 311 if (efx->phy_op->set_npage_adv)
497 efx->phy_op->set_npage_adv(efx, ecmd->advertising); 312 efx->phy_op->set_npage_adv(efx, ecmd->advertising);
498 313
499 /* Enable and restart AN */ 314 /* Enable and restart AN */
500 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, 315 reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1);
501 MDIO_MMDREG_CTRL1); 316 reg |= MDIO_AN_CTRL1_ENABLE;
502 reg |= BMCR_ANENABLE;
503 if (!(EFX_WORKAROUND_15195(efx) && 317 if (!(EFX_WORKAROUND_15195(efx) &&
504 LOOPBACK_MASK(efx) & efx->phy_op->loopbacks)) 318 LOOPBACK_MASK(efx) & efx->phy_op->loopbacks))
505 reg |= BMCR_ANRESTART; 319 reg |= MDIO_AN_CTRL1_RESTART;
506 if (xnp) 320 if (xnp)
507 reg |= 1 << MDIO_AN_CTRL_XNP_LBN; 321 reg |= MDIO_AN_CTRL1_XNP;
508 else 322 else
509 reg &= ~(1 << MDIO_AN_CTRL_XNP_LBN); 323 reg &= ~MDIO_AN_CTRL1_XNP;
510 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN, 324 efx_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg);
511 MDIO_MMDREG_CTRL1, reg);
512 } else { 325 } else {
513 /* Disable AN */ 326 /* Disable AN */
514 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_AN, 327 efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_CTRL1,
515 MDIO_MMDREG_CTRL1, 328 MDIO_AN_CTRL1_ENABLE, false);
516 __ffs(BMCR_ANENABLE), false);
517 329
518 /* Set the basic control bits */ 330 /* Set the basic control bits */
519 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, 331 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1);
520 MDIO_MMDREG_CTRL1); 332 reg &= ~(MDIO_CTRL1_SPEEDSEL | MDIO_CTRL1_FULLDPLX);
521 reg &= ~(BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FULLDPLX |
522 0x003c);
523 if (ecmd->speed == SPEED_100) 333 if (ecmd->speed == SPEED_100)
524 reg |= BMCR_SPEED100; 334 reg |= MDIO_PMA_CTRL1_SPEED100;
525 if (ecmd->duplex) 335 if (ecmd->duplex)
526 reg |= BMCR_FULLDPLX; 336 reg |= MDIO_CTRL1_FULLDPLX;
527 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, 337 efx_mdio_write(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1, reg);
528 MDIO_MMDREG_CTRL1, reg);
529 } 338 }
530 339
531 return 0; 340 return 0;
532} 341}
533 342
534void mdio_clause45_set_pause(struct efx_nic *efx) 343void efx_mdio_set_pause(struct efx_nic *efx)
535{ 344{
536 int phy_id = efx->mii.phy_id;
537 int reg; 345 int reg;
538 346
539 if (efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN)) { 347 if (efx->phy_op->mmds & MDIO_DEVS_AN) {
540 /* Set pause capability advertising */ 348 /* Set pause capability advertising */
541 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, 349 reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
542 MDIO_AN_ADVERTISE);
543 reg &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); 350 reg &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
544 reg |= efx_fc_advertise(efx->wanted_fc); 351 reg |= efx_fc_advertise(efx->wanted_fc);
545 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN, 352 efx_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
546 MDIO_AN_ADVERTISE, reg);
547 353
548 /* Restart auto-negotiation */ 354 /* Restart auto-negotiation */
549 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, 355 reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1);
550 MDIO_MMDREG_CTRL1); 356 if (reg & MDIO_AN_CTRL1_ENABLE) {
551 if (reg & BMCR_ANENABLE) { 357 reg |= MDIO_AN_CTRL1_RESTART;
552 reg |= BMCR_ANRESTART; 358 efx_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg);
553 mdio_clause45_write(efx, phy_id, MDIO_MMD_AN,
554 MDIO_MMDREG_CTRL1, reg);
555 } 359 }
556 } 360 }
557} 361}
558 362
559enum efx_fc_type mdio_clause45_get_pause(struct efx_nic *efx) 363enum efx_fc_type efx_mdio_get_pause(struct efx_nic *efx)
560{ 364{
561 int phy_id = efx->mii.phy_id;
562 int lpa; 365 int lpa;
563 366
564 if (!(efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_AN))) 367 if (!(efx->phy_op->mmds & MDIO_DEVS_AN))
565 return efx->wanted_fc; 368 return efx->wanted_fc;
566 lpa = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, MDIO_AN_LPA); 369 lpa = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_LPA);
567 return efx_fc_resolve(efx->wanted_fc, lpa); 370 return efx_fc_resolve(efx->wanted_fc, lpa);
568} 371}
569
570void mdio_clause45_set_flag(struct efx_nic *efx, u8 prt, u8 dev,
571 u16 addr, int bit, bool sense)
572{
573 int old_val = mdio_clause45_read(efx, prt, dev, addr);
574 int new_val;
575
576 if (sense)
577 new_val = old_val | (1 << bit);
578 else
579 new_val = old_val & ~(1 << bit);
580 if (old_val != new_val)
581 mdio_clause45_write(efx, prt, dev, addr, new_val);
582}
diff --git a/drivers/net/sfc/mdio_10g.h b/drivers/net/sfc/mdio_10g.h
index 7014d2279c20..ea4587d93698 100644
--- a/drivers/net/sfc/mdio_10g.h
+++ b/drivers/net/sfc/mdio_10g.h
@@ -10,247 +10,53 @@
10#ifndef EFX_MDIO_10G_H 10#ifndef EFX_MDIO_10G_H
11#define EFX_MDIO_10G_H 11#define EFX_MDIO_10G_H
12 12
13#include <linux/mdio.h>
14
13/* 15/*
14 * Definitions needed for doing 10G MDIO as specified in clause 45 16 * Helper functions for doing 10G MDIO as specified in IEEE 802.3 clause 45.
15 * MDIO, which do not appear in Linux yet. Also some helper functions.
16 */ 17 */
17 18
18#include "efx.h" 19#include "efx.h"
19#include "boards.h" 20#include "boards.h"
20 21
21/* Numbering of the MDIO Manageable Devices (MMDs) */ 22static inline unsigned efx_mdio_id_rev(u32 id) { return id & 0xf; }
22/* Physical Medium Attachment/ Physical Medium Dependent sublayer */ 23static inline unsigned efx_mdio_id_model(u32 id) { return (id >> 4) & 0x3f; }
23#define MDIO_MMD_PMAPMD (1) 24extern unsigned efx_mdio_id_oui(u32 id);
24/* WAN Interface Sublayer */
25#define MDIO_MMD_WIS (2)
26/* Physical Coding Sublayer */
27#define MDIO_MMD_PCS (3)
28/* PHY Extender Sublayer */
29#define MDIO_MMD_PHYXS (4)
30/* Extender Sublayer */
31#define MDIO_MMD_DTEXS (5)
32/* Transmission convergence */
33#define MDIO_MMD_TC (6)
34/* Auto negotiation */
35#define MDIO_MMD_AN (7)
36/* Clause 22 extension */
37#define MDIO_MMD_C22EXT 29
38
39/* Generic register locations */
40#define MDIO_MMDREG_CTRL1 (0)
41#define MDIO_MMDREG_STAT1 (1)
42#define MDIO_MMDREG_IDHI (2)
43#define MDIO_MMDREG_IDLOW (3)
44#define MDIO_MMDREG_SPEED (4)
45#define MDIO_MMDREG_DEVS0 (5)
46#define MDIO_MMDREG_DEVS1 (6)
47#define MDIO_MMDREG_CTRL2 (7)
48#define MDIO_MMDREG_STAT2 (8)
49#define MDIO_MMDREG_TXDIS (9)
50
51/* Bits in MMDREG_CTRL1 */
52/* Reset */
53#define MDIO_MMDREG_CTRL1_RESET_LBN (15)
54#define MDIO_MMDREG_CTRL1_RESET_WIDTH (1)
55/* Loopback */
56/* Loopback bit for WIS, PCS, PHYSX and DTEXS */
57#define MDIO_MMDREG_CTRL1_LBACK_LBN (14)
58#define MDIO_MMDREG_CTRL1_LBACK_WIDTH (1)
59/* Low power */
60#define MDIO_MMDREG_CTRL1_LPOWER_LBN (11)
61#define MDIO_MMDREG_CTRL1_LPOWER_WIDTH (1)
62
63/* Bits in MMDREG_STAT1 */
64#define MDIO_MMDREG_STAT1_FAULT_LBN (7)
65#define MDIO_MMDREG_STAT1_FAULT_WIDTH (1)
66/* Link state */
67#define MDIO_MMDREG_STAT1_LINK_LBN (2)
68#define MDIO_MMDREG_STAT1_LINK_WIDTH (1)
69/* Low power ability */
70#define MDIO_MMDREG_STAT1_LPABLE_LBN (1)
71#define MDIO_MMDREG_STAT1_LPABLE_WIDTH (1)
72
73/* Bits in combined ID regs */
74static inline unsigned mdio_id_rev(u32 id) { return id & 0xf; }
75static inline unsigned mdio_id_model(u32 id) { return (id >> 4) & 0x3f; }
76extern unsigned mdio_id_oui(u32 id);
77
78/* Bits in MMDREG_DEVS0/1. Someone thoughtfully layed things out
79 * so the 'bit present' bit number of an MMD is the number of
80 * that MMD */
81#define DEV_PRESENT_BIT(_b) (1 << _b)
82
83#define MDIO_MMDREG_DEVS_PHYXS DEV_PRESENT_BIT(MDIO_MMD_PHYXS)
84#define MDIO_MMDREG_DEVS_PCS DEV_PRESENT_BIT(MDIO_MMD_PCS)
85#define MDIO_MMDREG_DEVS_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD)
86#define MDIO_MMDREG_DEVS_AN DEV_PRESENT_BIT(MDIO_MMD_AN)
87#define MDIO_MMDREG_DEVS_C22EXT DEV_PRESENT_BIT(MDIO_MMD_C22EXT)
88
89/* Bits in MMDREG_SPEED */
90#define MDIO_MMDREG_SPEED_10G_LBN 0
91#define MDIO_MMDREG_SPEED_10G_WIDTH 1
92#define MDIO_MMDREG_SPEED_1000M_LBN 4
93#define MDIO_MMDREG_SPEED_1000M_WIDTH 1
94#define MDIO_MMDREG_SPEED_100M_LBN 5
95#define MDIO_MMDREG_SPEED_100M_WIDTH 1
96#define MDIO_MMDREG_SPEED_10M_LBN 6
97#define MDIO_MMDREG_SPEED_10M_WIDTH 1
98
99/* Bits in MMDREG_STAT2 */
100#define MDIO_MMDREG_STAT2_PRESENT_VAL (2)
101#define MDIO_MMDREG_STAT2_PRESENT_LBN (14)
102#define MDIO_MMDREG_STAT2_PRESENT_WIDTH (2)
103
104/* Bits in MMDREG_TXDIS */
105#define MDIO_MMDREG_TXDIS_GLOBAL_LBN (0)
106#define MDIO_MMDREG_TXDIS_GLOBAL_WIDTH (1)
107
108/* MMD-specific bits, ordered by MMD, then register */
109#define MDIO_PMAPMD_CTRL1_LBACK_LBN (0)
110#define MDIO_PMAPMD_CTRL1_LBACK_WIDTH (1)
111
112/* PMA type (4 bits) */
113#define MDIO_PMAPMD_CTRL2_10G_CX4 (0x0)
114#define MDIO_PMAPMD_CTRL2_10G_EW (0x1)
115#define MDIO_PMAPMD_CTRL2_10G_LW (0x2)
116#define MDIO_PMAPMD_CTRL2_10G_SW (0x3)
117#define MDIO_PMAPMD_CTRL2_10G_LX4 (0x4)
118#define MDIO_PMAPMD_CTRL2_10G_ER (0x5)
119#define MDIO_PMAPMD_CTRL2_10G_LR (0x6)
120#define MDIO_PMAPMD_CTRL2_10G_SR (0x7)
121/* Reserved */
122#define MDIO_PMAPMD_CTRL2_10G_BT (0x9)
123/* Reserved */
124/* Reserved */
125#define MDIO_PMAPMD_CTRL2_1G_BT (0xc)
126/* Reserved */
127#define MDIO_PMAPMD_CTRL2_100_BT (0xe)
128#define MDIO_PMAPMD_CTRL2_10_BT (0xf)
129#define MDIO_PMAPMD_CTRL2_TYPE_MASK (0xf)
130
131/* PMA 10GBT registers */
132#define MDIO_PMAPMD_10GBT_TXPWR (131)
133#define MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN (0)
134#define MDIO_PMAPMD_10GBT_TXPWR_SHORT_WIDTH (1)
135
136/* PHY XGXS Status 2 */
137#define MDIO_PHYXS_STATUS2 (8)
138#define MDIO_PHYXS_STATUS2_RX_FAULT_LBN 10
139
140/* PHY XGXS lane state */
141#define MDIO_PHYXS_LANE_STATE (0x18)
142#define MDIO_PHYXS_LANE_ALIGNED_LBN (12)
143
144/* AN registers */
145#define MDIO_AN_CTRL_XNP_LBN 13
146#define MDIO_AN_STATUS (1)
147#define MDIO_AN_STATUS_XNP_LBN (7)
148#define MDIO_AN_STATUS_PAGE_LBN (6)
149#define MDIO_AN_STATUS_AN_DONE_LBN (5)
150#define MDIO_AN_STATUS_LP_AN_CAP_LBN (0)
151
152#define MDIO_AN_ADVERTISE 16
153#define MDIO_AN_ADVERTISE_XNP_LBN 12
154#define MDIO_AN_LPA 19
155#define MDIO_AN_XNP 22
156#define MDIO_AN_LPA_XNP 25
157
158#define MDIO_AN_10GBT_CTRL 32
159#define MDIO_AN_10GBT_CTRL_ADV_10G_LBN 12
160#define MDIO_AN_10GBT_STATUS (33)
161#define MDIO_AN_10GBT_STATUS_MS_FLT_LBN (15) /* MASTER/SLAVE config fault */
162#define MDIO_AN_10GBT_STATUS_MS_LBN (14) /* MASTER/SLAVE config */
163#define MDIO_AN_10GBT_STATUS_LOC_OK_LBN (13) /* Local OK */
164#define MDIO_AN_10GBT_STATUS_REM_OK_LBN (12) /* Remote OK */
165#define MDIO_AN_10GBT_STATUS_LP_10G_LBN (11) /* Link partner is 10GBT capable */
166#define MDIO_AN_10GBT_STATUS_LP_LTA_LBN (10) /* LP loop timing ability */
167#define MDIO_AN_10GBT_STATUS_LP_TRR_LBN (9) /* LP Training Reset Request */
168 25
169 26static inline int efx_mdio_read(struct efx_nic *efx, int devad, int addr)
170/* Packing of the prt and dev arguments of clause 45 style MDIO into a
171 * single int so they can be passed into the mdio_read/write functions
172 * that currently exist. Note that as Falcon is the only current user,
173 * the packed form is chosen to match what Falcon needs to write into
174 * a register. This is checked at compile-time so do not change it. If
175 * your target chip needs things layed out differently you will need
176 * to unpack the arguments in your chip-specific mdio functions.
177 */
178 /* These are defined by the standard. */
179#define MDIO45_PRT_ID_WIDTH (5)
180#define MDIO45_DEV_ID_WIDTH (5)
181
182/* The prt ID is just packed in immediately to the left of the dev ID */
183#define MDIO45_PRT_DEV_WIDTH (MDIO45_PRT_ID_WIDTH + MDIO45_DEV_ID_WIDTH)
184
185#define MDIO45_PRT_ID_MASK ((1 << MDIO45_PRT_DEV_WIDTH) - 1)
186/* This is the prt + dev extended by 1 bit to hold the 'is clause 45' flag. */
187#define MDIO45_XPRT_ID_WIDTH (MDIO45_PRT_DEV_WIDTH + 1)
188#define MDIO45_XPRT_ID_MASK ((1 << MDIO45_XPRT_ID_WIDTH) - 1)
189#define MDIO45_XPRT_ID_IS10G (1 << (MDIO45_XPRT_ID_WIDTH - 1))
190
191
192#define MDIO45_PRT_ID_COMP_LBN MDIO45_DEV_ID_WIDTH
193#define MDIO45_PRT_ID_COMP_WIDTH MDIO45_PRT_ID_WIDTH
194#define MDIO45_DEV_ID_COMP_LBN 0
195#define MDIO45_DEV_ID_COMP_WIDTH MDIO45_DEV_ID_WIDTH
196
197/* Compose port and device into a phy_id */
198static inline int mdio_clause45_pack(u8 prt, u8 dev)
199{
200 efx_dword_t phy_id;
201 EFX_POPULATE_DWORD_2(phy_id, MDIO45_PRT_ID_COMP, prt,
202 MDIO45_DEV_ID_COMP, dev);
203 return MDIO45_XPRT_ID_IS10G | EFX_DWORD_VAL(phy_id);
204}
205
206static inline void mdio_clause45_unpack(u32 val, u8 *prt, u8 *dev)
207{ 27{
208 efx_dword_t phy_id; 28 return efx->mdio.mdio_read(efx->net_dev, efx->mdio.prtad, devad, addr);
209 EFX_POPULATE_DWORD_1(phy_id, EFX_DWORD_0, val);
210 *prt = EFX_DWORD_FIELD(phy_id, MDIO45_PRT_ID_COMP);
211 *dev = EFX_DWORD_FIELD(phy_id, MDIO45_DEV_ID_COMP);
212} 29}
213 30
214static inline int mdio_clause45_read(struct efx_nic *efx, 31static inline void
215 u8 prt, u8 dev, u16 addr) 32efx_mdio_write(struct efx_nic *efx, int devad, int addr, int value)
216{ 33{
217 return efx->mii.mdio_read(efx->net_dev, 34 efx->mdio.mdio_write(efx->net_dev, efx->mdio.prtad, devad, addr, value);
218 mdio_clause45_pack(prt, dev), addr);
219} 35}
220 36
221static inline void mdio_clause45_write(struct efx_nic *efx, 37static inline u32 efx_mdio_read_id(struct efx_nic *efx, int mmd)
222 u8 prt, u8 dev, u16 addr, int value)
223{
224 efx->mii.mdio_write(efx->net_dev,
225 mdio_clause45_pack(prt, dev), addr, value);
226}
227
228
229static inline u32 mdio_clause45_read_id(struct efx_nic *efx, int mmd)
230{ 38{
231 int phy_id = efx->mii.phy_id; 39 u16 id_low = efx_mdio_read(efx, mmd, MDIO_DEVID2);
232 u16 id_low = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_IDLOW); 40 u16 id_hi = efx_mdio_read(efx, mmd, MDIO_DEVID1);
233 u16 id_hi = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_IDHI);
234 return (id_hi << 16) | (id_low); 41 return (id_hi << 16) | (id_low);
235} 42}
236 43
237static inline bool mdio_clause45_phyxgxs_lane_sync(struct efx_nic *efx) 44static inline bool efx_mdio_phyxgxs_lane_sync(struct efx_nic *efx)
238{ 45{
239 int i, lane_status; 46 int i, lane_status;
240 bool sync; 47 bool sync;
241 48
242 for (i = 0; i < 2; ++i) 49 for (i = 0; i < 2; ++i)
243 lane_status = mdio_clause45_read(efx, efx->mii.phy_id, 50 lane_status = efx_mdio_read(efx, MDIO_MMD_PHYXS,
244 MDIO_MMD_PHYXS, 51 MDIO_PHYXS_LNSTAT);
245 MDIO_PHYXS_LANE_STATE);
246 52
247 sync = !!(lane_status & (1 << MDIO_PHYXS_LANE_ALIGNED_LBN)); 53 sync = !!(lane_status & MDIO_PHYXS_LNSTAT_ALIGN);
248 if (!sync) 54 if (!sync)
249 EFX_LOG(efx, "XGXS lane status: %x\n", lane_status); 55 EFX_LOG(efx, "XGXS lane status: %x\n", lane_status);
250 return sync; 56 return sync;
251} 57}
252 58
253extern const char *mdio_clause45_mmd_name(int mmd); 59extern const char *efx_mdio_mmd_name(int mmd);
254 60
255/* 61/*
256 * Reset a specific MMD and wait for reset to clear. 62 * Reset a specific MMD and wait for reset to clear.
@@ -258,54 +64,47 @@ extern const char *mdio_clause45_mmd_name(int mmd);
258 * 64 *
259 * This function will sleep 65 * This function will sleep
260 */ 66 */
261extern int mdio_clause45_reset_mmd(struct efx_nic *efx, int mmd, 67extern int efx_mdio_reset_mmd(struct efx_nic *efx, int mmd,
262 int spins, int spintime); 68 int spins, int spintime);
263 69
264/* As mdio_clause45_check_mmd but for multiple MMDs */ 70/* As efx_mdio_check_mmd but for multiple MMDs */
265int mdio_clause45_check_mmds(struct efx_nic *efx, 71int efx_mdio_check_mmds(struct efx_nic *efx,
266 unsigned int mmd_mask, unsigned int fatal_mask); 72 unsigned int mmd_mask, unsigned int fatal_mask);
267 73
268/* Check the link status of specified mmds in bit mask */ 74/* Check the link status of specified mmds in bit mask */
269extern bool mdio_clause45_links_ok(struct efx_nic *efx, 75extern bool efx_mdio_links_ok(struct efx_nic *efx, unsigned int mmd_mask);
270 unsigned int mmd_mask);
271 76
272/* Generic transmit disable support though PMAPMD */ 77/* Generic transmit disable support though PMAPMD */
273extern void mdio_clause45_transmit_disable(struct efx_nic *efx); 78extern void efx_mdio_transmit_disable(struct efx_nic *efx);
274 79
275/* Generic part of reconfigure: set/clear loopback bits */ 80/* Generic part of reconfigure: set/clear loopback bits */
276extern void mdio_clause45_phy_reconfigure(struct efx_nic *efx); 81extern void efx_mdio_phy_reconfigure(struct efx_nic *efx);
277 82
278/* Set the power state of the specified MMDs */ 83/* Set the power state of the specified MMDs */
279extern void mdio_clause45_set_mmds_lpower(struct efx_nic *efx, 84extern void efx_mdio_set_mmds_lpower(struct efx_nic *efx,
280 int low_power, unsigned int mmd_mask); 85 int low_power, unsigned int mmd_mask);
281
282/* Read (some of) the PHY settings over MDIO */
283extern void mdio_clause45_get_settings(struct efx_nic *efx,
284 struct ethtool_cmd *ecmd);
285
286/* Read (some of) the PHY settings over MDIO */
287extern void
288mdio_clause45_get_settings_ext(struct efx_nic *efx, struct ethtool_cmd *ecmd,
289 u32 xnp, u32 xnp_lpa);
290 86
291/* Set (some of) the PHY settings over MDIO */ 87/* Set (some of) the PHY settings over MDIO */
292extern int mdio_clause45_set_settings(struct efx_nic *efx, 88extern int efx_mdio_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd);
293 struct ethtool_cmd *ecmd);
294 89
295/* Set pause parameters to be advertised through AN (if available) */ 90/* Set pause parameters to be advertised through AN (if available) */
296extern void mdio_clause45_set_pause(struct efx_nic *efx); 91extern void efx_mdio_set_pause(struct efx_nic *efx);
297 92
298/* Get pause parameters from AN if available (otherwise return 93/* Get pause parameters from AN if available (otherwise return
299 * requested pause parameters) 94 * requested pause parameters)
300 */ 95 */
301enum efx_fc_type mdio_clause45_get_pause(struct efx_nic *efx); 96enum efx_fc_type efx_mdio_get_pause(struct efx_nic *efx);
302 97
303/* Wait for specified MMDs to exit reset within a timeout */ 98/* Wait for specified MMDs to exit reset within a timeout */
304extern int mdio_clause45_wait_reset_mmds(struct efx_nic *efx, 99extern int efx_mdio_wait_reset_mmds(struct efx_nic *efx,
305 unsigned int mmd_mask); 100 unsigned int mmd_mask);
306 101
307/* Set or clear flag, debouncing */ 102/* Set or clear flag, debouncing */
308extern void mdio_clause45_set_flag(struct efx_nic *efx, u8 prt, u8 dev, 103static inline void
309 u16 addr, int bit, bool sense); 104efx_mdio_set_flag(struct efx_nic *efx, int devad, int addr,
105 int mask, bool state)
106{
107 mdio_set_flag(&efx->mdio, efx->mdio.prtad, devad, addr, mask, state);
108}
310 109
311#endif /* EFX_MDIO_10G_H */ 110#endif /* EFX_MDIO_10G_H */
diff --git a/drivers/net/sfc/net_driver.h b/drivers/net/sfc/net_driver.h
index e169e5dcd1e6..457e2f1d4b43 100644
--- a/drivers/net/sfc/net_driver.h
+++ b/drivers/net/sfc/net_driver.h
@@ -19,7 +19,7 @@
19#include <linux/ethtool.h> 19#include <linux/ethtool.h>
20#include <linux/if_vlan.h> 20#include <linux/if_vlan.h>
21#include <linux/timer.h> 21#include <linux/timer.h>
22#include <linux/mii.h> 22#include <linux/mdio.h>
23#include <linux/list.h> 23#include <linux/list.h>
24#include <linux/pci.h> 24#include <linux/pci.h>
25#include <linux/device.h> 25#include <linux/device.h>
@@ -458,8 +458,6 @@ enum phy_type {
458 PHY_TYPE_MAX /* Insert any new items before this */ 458 PHY_TYPE_MAX /* Insert any new items before this */
459}; 459};
460 460
461#define PHY_ADDR_INVALID 0xff
462
463#define EFX_IS10G(efx) ((efx)->link_speed == 10000) 461#define EFX_IS10G(efx) ((efx)->link_speed == 10000)
464 462
465enum nic_state { 463enum nic_state {
@@ -758,7 +756,7 @@ union efx_multicast_hash {
758 * @phy_lock: PHY access lock 756 * @phy_lock: PHY access lock
759 * @phy_op: PHY interface 757 * @phy_op: PHY interface
760 * @phy_data: PHY private data (including PHY-specific stats) 758 * @phy_data: PHY private data (including PHY-specific stats)
761 * @mii: PHY interface 759 * @mdio: PHY MDIO interface
762 * @phy_mode: PHY operating mode. Serialised by @mac_lock. 760 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
763 * @mac_up: MAC link state 761 * @mac_up: MAC link state
764 * @link_up: Link status 762 * @link_up: Link status
@@ -845,7 +843,7 @@ struct efx_nic {
845 struct work_struct phy_work; 843 struct work_struct phy_work;
846 struct efx_phy_operations *phy_op; 844 struct efx_phy_operations *phy_op;
847 void *phy_data; 845 void *phy_data;
848 struct mii_if_info mii; 846 struct mdio_if_info mdio;
849 enum efx_phy_mode phy_mode; 847 enum efx_phy_mode phy_mode;
850 848
851 bool mac_up; 849 bool mac_up;
diff --git a/drivers/net/sfc/selftest.c b/drivers/net/sfc/selftest.c
index 0a598084c513..043795715955 100644
--- a/drivers/net/sfc/selftest.c
+++ b/drivers/net/sfc/selftest.c
@@ -80,39 +80,38 @@ struct efx_loopback_state {
80 * 80 *
81 **************************************************************************/ 81 **************************************************************************/
82 82
83static int efx_test_mii(struct efx_nic *efx, struct efx_self_tests *tests) 83static int efx_test_mdio(struct efx_nic *efx, struct efx_self_tests *tests)
84{ 84{
85 int rc = 0; 85 int rc = 0;
86 int devad = __ffs(efx->mdio.mmds);
86 u16 physid1, physid2; 87 u16 physid1, physid2;
87 struct mii_if_info *mii = &efx->mii;
88 struct net_device *net_dev = efx->net_dev;
89 88
90 if (efx->phy_type == PHY_TYPE_NONE) 89 if (efx->phy_type == PHY_TYPE_NONE)
91 return 0; 90 return 0;
92 91
93 mutex_lock(&efx->mac_lock); 92 mutex_lock(&efx->mac_lock);
94 tests->mii = -1; 93 tests->mdio = -1;
95 94
96 physid1 = mii->mdio_read(net_dev, mii->phy_id, MII_PHYSID1); 95 physid1 = efx_mdio_read(efx, devad, MDIO_DEVID1);
97 physid2 = mii->mdio_read(net_dev, mii->phy_id, MII_PHYSID2); 96 physid2 = efx_mdio_read(efx, devad, MDIO_DEVID2);
98 97
99 if ((physid1 == 0x0000) || (physid1 == 0xffff) || 98 if ((physid1 == 0x0000) || (physid1 == 0xffff) ||
100 (physid2 == 0x0000) || (physid2 == 0xffff)) { 99 (physid2 == 0x0000) || (physid2 == 0xffff)) {
101 EFX_ERR(efx, "no MII PHY present with ID %d\n", 100 EFX_ERR(efx, "no MDIO PHY present with ID %d\n",
102 mii->phy_id); 101 efx->mdio.prtad);
103 rc = -EINVAL; 102 rc = -EINVAL;
104 goto out; 103 goto out;
105 } 104 }
106 105
107 if (EFX_IS10G(efx)) { 106 if (EFX_IS10G(efx)) {
108 rc = mdio_clause45_check_mmds(efx, efx->phy_op->mmds, 0); 107 rc = efx_mdio_check_mmds(efx, efx->phy_op->mmds, 0);
109 if (rc) 108 if (rc)
110 goto out; 109 goto out;
111 } 110 }
112 111
113out: 112out:
114 mutex_unlock(&efx->mac_lock); 113 mutex_unlock(&efx->mac_lock);
115 tests->mii = rc ? -1 : 1; 114 tests->mdio = rc ? -1 : 1;
116 return rc; 115 return rc;
117} 116}
118 117
@@ -673,7 +672,7 @@ int efx_selftest(struct efx_nic *efx, struct efx_self_tests *tests,
673 /* Online (i.e. non-disruptive) testing 672 /* Online (i.e. non-disruptive) testing
674 * This checks interrupt generation, event delivery and PHY presence. */ 673 * This checks interrupt generation, event delivery and PHY presence. */
675 674
676 rc = efx_test_mii(efx, tests); 675 rc = efx_test_mdio(efx, tests);
677 if (rc && !rc_test) 676 if (rc && !rc_test)
678 rc_test = rc; 677 rc_test = rc;
679 678
diff --git a/drivers/net/sfc/selftest.h b/drivers/net/sfc/selftest.h
index 39451cf938cf..f6feee04c96b 100644
--- a/drivers/net/sfc/selftest.h
+++ b/drivers/net/sfc/selftest.h
@@ -32,7 +32,7 @@ struct efx_loopback_self_tests {
32 */ 32 */
33struct efx_self_tests { 33struct efx_self_tests {
34 /* online tests */ 34 /* online tests */
35 int mii; 35 int mdio;
36 int nvram; 36 int nvram;
37 int interrupt; 37 int interrupt;
38 int eventq_dma[EFX_MAX_CHANNELS]; 38 int eventq_dma[EFX_MAX_CHANNELS];
diff --git a/drivers/net/sfc/tenxpress.c b/drivers/net/sfc/tenxpress.c
index e61dc4d4741c..403f7d70c223 100644
--- a/drivers/net/sfc/tenxpress.c
+++ b/drivers/net/sfc/tenxpress.c
@@ -23,10 +23,10 @@
23 * clause 22 extension MMD, but since it doesn't have all the generic 23 * clause 22 extension MMD, but since it doesn't have all the generic
24 * MMD registers it is pointless to include it here. 24 * MMD registers it is pointless to include it here.
25 */ 25 */
26#define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PMAPMD | \ 26#define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \
27 MDIO_MMDREG_DEVS_PCS | \ 27 MDIO_DEVS_PCS | \
28 MDIO_MMDREG_DEVS_PHYXS | \ 28 MDIO_DEVS_PHYXS | \
29 MDIO_MMDREG_DEVS_AN) 29 MDIO_DEVS_AN)
30 30
31#define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \ 31#define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
32 (1 << LOOPBACK_PCS) | \ 32 (1 << LOOPBACK_PCS) | \
@@ -153,10 +153,6 @@
153#define LOOPBACK_NEAR_LBN (8) 153#define LOOPBACK_NEAR_LBN (8)
154#define LOOPBACK_NEAR_WIDTH (1) 154#define LOOPBACK_NEAR_WIDTH (1)
155 155
156#define PCS_10GBASET_STAT1 32
157#define PCS_10GBASET_BLKLK_LBN 0
158#define PCS_10GBASET_BLKLK_WIDTH 1
159
160/* Boot status register */ 156/* Boot status register */
161#define PCS_BOOT_STATUS_REG 53248 157#define PCS_BOOT_STATUS_REG 53248
162#define PCS_BOOT_FATAL_ERROR_LBN 0 158#define PCS_BOOT_FATAL_ERROR_LBN 0
@@ -206,10 +202,8 @@ static ssize_t show_phy_short_reach(struct device *dev,
206 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 202 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
207 int reg; 203 int reg;
208 204
209 reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, 205 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR);
210 MDIO_PMAPMD_10GBT_TXPWR); 206 return sprintf(buf, "%d\n", !!(reg & MDIO_PMA_10GBT_TXPWR_SHORT));
211 return sprintf(buf, "%d\n",
212 !!(reg & (1 << MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN)));
213} 207}
214 208
215static ssize_t set_phy_short_reach(struct device *dev, 209static ssize_t set_phy_short_reach(struct device *dev,
@@ -219,10 +213,9 @@ static ssize_t set_phy_short_reach(struct device *dev,
219 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 213 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
220 214
221 rtnl_lock(); 215 rtnl_lock();
222 mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, 216 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR,
223 MDIO_PMAPMD_10GBT_TXPWR, 217 MDIO_PMA_10GBT_TXPWR_SHORT,
224 MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN, 218 count != 0 && *buf != '0');
225 count != 0 && *buf != '0');
226 efx_reconfigure_port(efx); 219 efx_reconfigure_port(efx);
227 rtnl_unlock(); 220 rtnl_unlock();
228 221
@@ -238,9 +231,8 @@ int sft9001_wait_boot(struct efx_nic *efx)
238 int boot_stat; 231 int boot_stat;
239 232
240 for (;;) { 233 for (;;) {
241 boot_stat = mdio_clause45_read(efx, efx->mii.phy_id, 234 boot_stat = efx_mdio_read(efx, MDIO_MMD_PCS,
242 MDIO_MMD_PCS, 235 PCS_BOOT_STATUS_REG);
243 PCS_BOOT_STATUS_REG);
244 if (boot_stat >= 0) { 236 if (boot_stat >= 0) {
245 EFX_LOG(efx, "PHY boot status = %#x\n", boot_stat); 237 EFX_LOG(efx, "PHY boot status = %#x\n", boot_stat);
246 switch (boot_stat & 238 switch (boot_stat &
@@ -286,38 +278,32 @@ int sft9001_wait_boot(struct efx_nic *efx)
286 278
287static int tenxpress_init(struct efx_nic *efx) 279static int tenxpress_init(struct efx_nic *efx)
288{ 280{
289 int phy_id = efx->mii.phy_id;
290 int reg; 281 int reg;
291 282
292 if (efx->phy_type == PHY_TYPE_SFX7101) { 283 if (efx->phy_type == PHY_TYPE_SFX7101) {
293 /* Enable 312.5 MHz clock */ 284 /* Enable 312.5 MHz clock */
294 mdio_clause45_write(efx, phy_id, 285 efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
295 MDIO_MMD_PCS, PCS_TEST_SELECT_REG, 286 1 << CLK312_EN_LBN);
296 1 << CLK312_EN_LBN);
297 } else { 287 } else {
298 /* Enable 312.5 MHz clock and GMII */ 288 /* Enable 312.5 MHz clock and GMII */
299 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, 289 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
300 PMA_PMD_XCONTROL_REG);
301 reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) | 290 reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) |
302 (1 << PMA_PMD_EXT_CLK_OUT_LBN) | 291 (1 << PMA_PMD_EXT_CLK_OUT_LBN) |
303 (1 << PMA_PMD_EXT_CLK312_LBN) | 292 (1 << PMA_PMD_EXT_CLK312_LBN) |
304 (1 << PMA_PMD_EXT_ROBUST_LBN)); 293 (1 << PMA_PMD_EXT_ROBUST_LBN));
305 294
306 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, 295 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
307 PMA_PMD_XCONTROL_REG, reg); 296 efx_mdio_set_flag(efx, MDIO_MMD_C22EXT,
308 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT, 297 GPHY_XCONTROL_REG, 1 << GPHY_ISOLATE_LBN,
309 GPHY_XCONTROL_REG, GPHY_ISOLATE_LBN, 298 false);
310 false);
311 } 299 }
312 300
313 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ 301 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
314 if (efx->phy_type == PHY_TYPE_SFX7101) { 302 if (efx->phy_type == PHY_TYPE_SFX7101) {
315 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD, 303 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG,
316 PMA_PMD_LED_CTRL_REG, 304 1 << PMA_PMA_LED_ACTIVITY_LBN, true);
317 PMA_PMA_LED_ACTIVITY_LBN, 305 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG,
318 true); 306 PMA_PMD_LED_DEFAULT);
319 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD,
320 PMA_PMD_LED_OVERR_REG, PMA_PMD_LED_DEFAULT);
321 } 307 }
322 308
323 return 0; 309 return 0;
@@ -337,22 +323,19 @@ static int tenxpress_phy_init(struct efx_nic *efx)
337 if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { 323 if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
338 if (efx->phy_type == PHY_TYPE_SFT9001A) { 324 if (efx->phy_type == PHY_TYPE_SFT9001A) {
339 int reg; 325 int reg;
340 reg = mdio_clause45_read(efx, efx->mii.phy_id, 326 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
341 MDIO_MMD_PMAPMD, 327 PMA_PMD_XCONTROL_REG);
342 PMA_PMD_XCONTROL_REG);
343 reg |= (1 << PMA_PMD_EXT_SSR_LBN); 328 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
344 mdio_clause45_write(efx, efx->mii.phy_id, 329 efx_mdio_write(efx, MDIO_MMD_PMAPMD,
345 MDIO_MMD_PMAPMD, 330 PMA_PMD_XCONTROL_REG, reg);
346 PMA_PMD_XCONTROL_REG, reg);
347 mdelay(200); 331 mdelay(200);
348 } 332 }
349 333
350 rc = mdio_clause45_wait_reset_mmds(efx, 334 rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
351 TENXPRESS_REQUIRED_DEVS);
352 if (rc < 0) 335 if (rc < 0)
353 goto fail; 336 goto fail;
354 337
355 rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); 338 rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
356 if (rc < 0) 339 if (rc < 0)
357 goto fail; 340 goto fail;
358 } 341 }
@@ -360,7 +343,7 @@ static int tenxpress_phy_init(struct efx_nic *efx)
360 rc = tenxpress_init(efx); 343 rc = tenxpress_init(efx);
361 if (rc < 0) 344 if (rc < 0)
362 goto fail; 345 goto fail;
363 mdio_clause45_set_pause(efx); 346 efx_mdio_set_pause(efx);
364 347
365 if (efx->phy_type == PHY_TYPE_SFT9001B) { 348 if (efx->phy_type == PHY_TYPE_SFT9001B) {
366 rc = device_create_file(&efx->pci_dev->dev, 349 rc = device_create_file(&efx->pci_dev->dev,
@@ -395,17 +378,14 @@ static int tenxpress_special_reset(struct efx_nic *efx)
395 efx_stats_disable(efx); 378 efx_stats_disable(efx);
396 379
397 /* Initiate reset */ 380 /* Initiate reset */
398 reg = mdio_clause45_read(efx, efx->mii.phy_id, 381 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
399 MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
400 reg |= (1 << PMA_PMD_EXT_SSR_LBN); 382 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
401 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, 383 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
402 PMA_PMD_XCONTROL_REG, reg);
403 384
404 mdelay(200); 385 mdelay(200);
405 386
406 /* Wait for the blocks to come out of reset */ 387 /* Wait for the blocks to come out of reset */
407 rc = mdio_clause45_wait_reset_mmds(efx, 388 rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
408 TENXPRESS_REQUIRED_DEVS);
409 if (rc < 0) 389 if (rc < 0)
410 goto out; 390 goto out;
411 391
@@ -424,7 +404,6 @@ out:
424static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) 404static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
425{ 405{
426 struct tenxpress_phy_data *pd = efx->phy_data; 406 struct tenxpress_phy_data *pd = efx->phy_data;
427 int phy_id = efx->mii.phy_id;
428 bool bad_lp; 407 bool bad_lp;
429 int reg; 408 int reg;
430 409
@@ -432,11 +411,10 @@ static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
432 bad_lp = false; 411 bad_lp = false;
433 } else { 412 } else {
434 /* Check that AN has started but not completed. */ 413 /* Check that AN has started but not completed. */
435 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, 414 reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
436 MDIO_AN_STATUS); 415 if (!(reg & MDIO_AN_STAT1_LPABLE))
437 if (!(reg & (1 << MDIO_AN_STATUS_LP_AN_CAP_LBN)))
438 return; /* LP status is unknown */ 416 return; /* LP status is unknown */
439 bad_lp = !(reg & (1 << MDIO_AN_STATUS_AN_DONE_LBN)); 417 bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE);
440 if (bad_lp) 418 if (bad_lp)
441 pd->bad_lp_tries++; 419 pd->bad_lp_tries++;
442 } 420 }
@@ -448,8 +426,8 @@ static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
448 /* Use the RX (red) LED as an error indicator once we've seen AN 426 /* Use the RX (red) LED as an error indicator once we've seen AN
449 * failure several times in a row, and also log a message. */ 427 * failure several times in a row, and also log a message. */
450 if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) { 428 if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
451 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, 429 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
452 PMA_PMD_LED_OVERR_REG); 430 PMA_PMD_LED_OVERR_REG);
453 reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN); 431 reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
454 if (!bad_lp) { 432 if (!bad_lp) {
455 reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN; 433 reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
@@ -460,23 +438,22 @@ static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
460 " supports 10GBASE-T ONLY, so no link can" 438 " supports 10GBASE-T ONLY, so no link can"
461 " be established\n"); 439 " be established\n");
462 } 440 }
463 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, 441 efx_mdio_write(efx, MDIO_MMD_PMAPMD,
464 PMA_PMD_LED_OVERR_REG, reg); 442 PMA_PMD_LED_OVERR_REG, reg);
465 pd->bad_lp_tries = bad_lp; 443 pd->bad_lp_tries = bad_lp;
466 } 444 }
467} 445}
468 446
469static bool sfx7101_link_ok(struct efx_nic *efx) 447static bool sfx7101_link_ok(struct efx_nic *efx)
470{ 448{
471 return mdio_clause45_links_ok(efx, 449 return efx_mdio_links_ok(efx,
472 MDIO_MMDREG_DEVS_PMAPMD | 450 MDIO_DEVS_PMAPMD |
473 MDIO_MMDREG_DEVS_PCS | 451 MDIO_DEVS_PCS |
474 MDIO_MMDREG_DEVS_PHYXS); 452 MDIO_DEVS_PHYXS);
475} 453}
476 454
477static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) 455static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd)
478{ 456{
479 int phy_id = efx->mii.phy_id;
480 u32 reg; 457 u32 reg;
481 458
482 if (efx_phy_mode_disabled(efx->phy_mode)) 459 if (efx_phy_mode_disabled(efx->phy_mode))
@@ -484,50 +461,43 @@ static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd)
484 else if (efx->loopback_mode == LOOPBACK_GPHY) 461 else if (efx->loopback_mode == LOOPBACK_GPHY)
485 return true; 462 return true;
486 else if (efx->loopback_mode) 463 else if (efx->loopback_mode)
487 return mdio_clause45_links_ok(efx, 464 return efx_mdio_links_ok(efx,
488 MDIO_MMDREG_DEVS_PMAPMD | 465 MDIO_DEVS_PMAPMD |
489 MDIO_MMDREG_DEVS_PHYXS); 466 MDIO_DEVS_PHYXS);
490 467
491 /* We must use the same definition of link state as LASI, 468 /* We must use the same definition of link state as LASI,
492 * otherwise we can miss a link state transition 469 * otherwise we can miss a link state transition
493 */ 470 */
494 if (ecmd->speed == 10000) { 471 if (ecmd->speed == 10000) {
495 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS, 472 reg = efx_mdio_read(efx, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
496 PCS_10GBASET_STAT1); 473 return reg & MDIO_PCS_10GBRT_STAT1_BLKLK;
497 return reg & (1 << PCS_10GBASET_BLKLK_LBN);
498 } else { 474 } else {
499 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, 475 reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_STATUS_REG);
500 C22EXT_STATUS_REG);
501 return reg & (1 << C22EXT_STATUS_LINK_LBN); 476 return reg & (1 << C22EXT_STATUS_LINK_LBN);
502 } 477 }
503} 478}
504 479
505static void tenxpress_ext_loopback(struct efx_nic *efx) 480static void tenxpress_ext_loopback(struct efx_nic *efx)
506{ 481{
507 int phy_id = efx->mii.phy_id; 482 efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1,
508 483 1 << LOOPBACK_NEAR_LBN,
509 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS, 484 efx->loopback_mode == LOOPBACK_PHYXS);
510 PHYXS_TEST1, LOOPBACK_NEAR_LBN,
511 efx->loopback_mode == LOOPBACK_PHYXS);
512 if (efx->phy_type != PHY_TYPE_SFX7101) 485 if (efx->phy_type != PHY_TYPE_SFX7101)
513 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT, 486 efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, GPHY_XCONTROL_REG,
514 GPHY_XCONTROL_REG, 487 1 << GPHY_LOOPBACK_NEAR_LBN,
515 GPHY_LOOPBACK_NEAR_LBN, 488 efx->loopback_mode == LOOPBACK_GPHY);
516 efx->loopback_mode == LOOPBACK_GPHY);
517} 489}
518 490
519static void tenxpress_low_power(struct efx_nic *efx) 491static void tenxpress_low_power(struct efx_nic *efx)
520{ 492{
521 int phy_id = efx->mii.phy_id;
522
523 if (efx->phy_type == PHY_TYPE_SFX7101) 493 if (efx->phy_type == PHY_TYPE_SFX7101)
524 mdio_clause45_set_mmds_lpower( 494 efx_mdio_set_mmds_lpower(
525 efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER), 495 efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
526 TENXPRESS_REQUIRED_DEVS); 496 TENXPRESS_REQUIRED_DEVS);
527 else 497 else
528 mdio_clause45_set_flag( 498 efx_mdio_set_flag(
529 efx, phy_id, MDIO_MMD_PMAPMD, 499 efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG,
530 PMA_PMD_XCONTROL_REG, PMA_PMD_EXT_LPOWER_LBN, 500 1 << PMA_PMD_EXT_LPOWER_LBN,
531 !!(efx->phy_mode & PHY_MODE_LOW_POWER)); 501 !!(efx->phy_mode & PHY_MODE_LOW_POWER));
532} 502}
533 503
@@ -568,8 +538,8 @@ static void tenxpress_phy_reconfigure(struct efx_nic *efx)
568 WARN_ON(rc); 538 WARN_ON(rc);
569 } 539 }
570 540
571 mdio_clause45_transmit_disable(efx); 541 efx_mdio_transmit_disable(efx);
572 mdio_clause45_phy_reconfigure(efx); 542 efx_mdio_phy_reconfigure(efx);
573 tenxpress_ext_loopback(efx); 543 tenxpress_ext_loopback(efx);
574 544
575 phy_data->loopback_mode = efx->loopback_mode; 545 phy_data->loopback_mode = efx->loopback_mode;
@@ -585,7 +555,7 @@ static void tenxpress_phy_reconfigure(struct efx_nic *efx)
585 efx->link_fd = ecmd.duplex == DUPLEX_FULL; 555 efx->link_fd = ecmd.duplex == DUPLEX_FULL;
586 efx->link_up = sft9001_link_ok(efx, &ecmd); 556 efx->link_up = sft9001_link_ok(efx, &ecmd);
587 } 557 }
588 efx->link_fc = mdio_clause45_get_pause(efx); 558 efx->link_fc = efx_mdio_get_pause(efx);
589} 559}
590 560
591/* Poll PHY for interrupt */ 561/* Poll PHY for interrupt */
@@ -599,7 +569,7 @@ static void tenxpress_phy_poll(struct efx_nic *efx)
599 if (link_ok != efx->link_up) { 569 if (link_ok != efx->link_up) {
600 change = true; 570 change = true;
601 } else { 571 } else {
602 unsigned int link_fc = mdio_clause45_get_pause(efx); 572 unsigned int link_fc = efx_mdio_get_pause(efx);
603 if (link_fc != efx->link_fc) 573 if (link_fc != efx->link_fc)
604 change = true; 574 change = true;
605 } 575 }
@@ -609,9 +579,8 @@ static void tenxpress_phy_poll(struct efx_nic *efx)
609 if (link_ok != efx->link_up) 579 if (link_ok != efx->link_up)
610 change = true; 580 change = true;
611 } else { 581 } else {
612 u32 status = mdio_clause45_read(efx, efx->mii.phy_id, 582 int status = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
613 MDIO_MMD_PMAPMD, 583 PMA_PMD_LASI_STATUS);
614 PMA_PMD_LASI_STATUS);
615 if (status & (1 << PMA_PMD_LS_ALARM_LBN)) 584 if (status & (1 << PMA_PMD_LS_ALARM_LBN))
616 change = true; 585 change = true;
617 } 586 }
@@ -634,8 +603,7 @@ static void tenxpress_phy_fini(struct efx_nic *efx)
634 if (efx->phy_type == PHY_TYPE_SFX7101) { 603 if (efx->phy_type == PHY_TYPE_SFX7101) {
635 /* Power down the LNPGA */ 604 /* Power down the LNPGA */
636 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); 605 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
637 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, 606 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
638 PMA_PMD_XCONTROL_REG, reg);
639 607
640 /* Waiting here ensures that the board fini, which can turn 608 /* Waiting here ensures that the board fini, which can turn
641 * off the power to the PHY, won't get run until the LNPGA 609 * off the power to the PHY, won't get run until the LNPGA
@@ -661,8 +629,7 @@ void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
661 else 629 else
662 reg = PMA_PMD_LED_DEFAULT; 630 reg = PMA_PMD_LED_DEFAULT;
663 631
664 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, 632 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg);
665 PMA_PMD_LED_OVERR_REG, reg);
666} 633}
667 634
668static const char *const sfx7101_test_names[] = { 635static const char *const sfx7101_test_names[] = {
@@ -698,7 +665,6 @@ static const char *const sft9001_test_names[] = {
698static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) 665static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags)
699{ 666{
700 struct ethtool_cmd ecmd; 667 struct ethtool_cmd ecmd;
701 int phy_id = efx->mii.phy_id;
702 int rc = 0, rc2, i, ctrl_reg, res_reg; 668 int rc = 0, rc2, i, ctrl_reg, res_reg;
703 669
704 if (flags & ETH_TEST_FL_OFFLINE) 670 if (flags & ETH_TEST_FL_OFFLINE)
@@ -717,11 +683,10 @@ static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags)
717 * must reset the PHY to resume normal service. */ 683 * must reset the PHY to resume normal service. */
718 ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN); 684 ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN);
719 } 685 }
720 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, 686 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG,
721 PMA_PMD_CDIAG_CTRL_REG, ctrl_reg); 687 ctrl_reg);
722 i = 0; 688 i = 0;
723 while (mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, 689 while (efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG) &
724 PMA_PMD_CDIAG_CTRL_REG) &
725 (1 << CDIAG_CTRL_IN_PROG_LBN)) { 690 (1 << CDIAG_CTRL_IN_PROG_LBN)) {
726 if (++i == 50) { 691 if (++i == 50) {
727 rc = -ETIMEDOUT; 692 rc = -ETIMEDOUT;
@@ -729,15 +694,13 @@ static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags)
729 } 694 }
730 msleep(100); 695 msleep(100);
731 } 696 }
732 res_reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, 697 res_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_RES_REG);
733 PMA_PMD_CDIAG_RES_REG);
734 for (i = 0; i < 4; i++) { 698 for (i = 0; i < 4; i++) {
735 int pair_res = 699 int pair_res =
736 (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH)) 700 (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH))
737 & ((1 << CDIAG_RES_WIDTH) - 1); 701 & ((1 << CDIAG_RES_WIDTH) - 1);
738 int len_reg = mdio_clause45_read(efx, efx->mii.phy_id, 702 int len_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
739 MDIO_MMD_PMAPMD, 703 PMA_PMD_CDIAG_LEN_REG + i);
740 PMA_PMD_CDIAG_LEN_REG + i);
741 if (pair_res == CDIAG_RES_OK) 704 if (pair_res == CDIAG_RES_OK)
742 results[1 + i] = 1; 705 results[1 + i] = 1;
743 else if (pair_res == CDIAG_RES_INVALID) 706 else if (pair_res == CDIAG_RES_INVALID)
@@ -769,32 +732,27 @@ out:
769static void 732static void
770tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) 733tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
771{ 734{
772 int phy_id = efx->mii.phy_id;
773 u32 adv = 0, lpa = 0; 735 u32 adv = 0, lpa = 0;
774 int reg; 736 int reg;
775 737
776 if (efx->phy_type != PHY_TYPE_SFX7101) { 738 if (efx->phy_type != PHY_TYPE_SFX7101) {
777 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, 739 reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL);
778 C22EXT_MSTSLV_CTRL);
779 if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN)) 740 if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN))
780 adv |= ADVERTISED_1000baseT_Full; 741 adv |= ADVERTISED_1000baseT_Full;
781 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, 742 reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_STATUS);
782 C22EXT_MSTSLV_STATUS);
783 if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN)) 743 if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN))
784 lpa |= ADVERTISED_1000baseT_Half; 744 lpa |= ADVERTISED_1000baseT_Half;
785 if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN)) 745 if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN))
786 lpa |= ADVERTISED_1000baseT_Full; 746 lpa |= ADVERTISED_1000baseT_Full;
787 } 747 }
788 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, 748 reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
789 MDIO_AN_10GBT_CTRL); 749 if (reg & MDIO_AN_10GBT_CTRL_ADV10G)
790 if (reg & (1 << MDIO_AN_10GBT_CTRL_ADV_10G_LBN))
791 adv |= ADVERTISED_10000baseT_Full; 750 adv |= ADVERTISED_10000baseT_Full;
792 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, 751 reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
793 MDIO_AN_10GBT_STATUS); 752 if (reg & MDIO_AN_10GBT_STAT_LP10G)
794 if (reg & (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN))
795 lpa |= ADVERTISED_10000baseT_Full; 753 lpa |= ADVERTISED_10000baseT_Full;
796 754
797 mdio_clause45_get_settings_ext(efx, ecmd, adv, lpa); 755 mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa);
798 756
799 if (efx->phy_type != PHY_TYPE_SFX7101) 757 if (efx->phy_type != PHY_TYPE_SFX7101)
800 ecmd->supported |= (SUPPORTED_100baseT_Full | 758 ecmd->supported |= (SUPPORTED_100baseT_Full |
@@ -813,29 +771,24 @@ static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
813 if (!ecmd->autoneg) 771 if (!ecmd->autoneg)
814 return -EINVAL; 772 return -EINVAL;
815 773
816 return mdio_clause45_set_settings(efx, ecmd); 774 return efx_mdio_set_settings(efx, ecmd);
817} 775}
818 776
819static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising) 777static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising)
820{ 778{
821 mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_AN, 779 efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
822 MDIO_AN_10GBT_CTRL, 780 MDIO_AN_10GBT_CTRL_ADV10G,
823 MDIO_AN_10GBT_CTRL_ADV_10G_LBN, 781 advertising & ADVERTISED_10000baseT_Full);
824 advertising & ADVERTISED_10000baseT_Full);
825} 782}
826 783
827static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising) 784static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising)
828{ 785{
829 int phy_id = efx->mii.phy_id; 786 efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL,
830 787 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN,
831 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT, 788 advertising & ADVERTISED_1000baseT_Full);
832 C22EXT_MSTSLV_CTRL, 789 efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
833 C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN, 790 MDIO_AN_10GBT_CTRL_ADV10G,
834 advertising & ADVERTISED_1000baseT_Full); 791 advertising & ADVERTISED_10000baseT_Full);
835 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_AN,
836 MDIO_AN_10GBT_CTRL,
837 MDIO_AN_10GBT_CTRL_ADV_10G_LBN,
838 advertising & ADVERTISED_10000baseT_Full);
839} 792}
840 793
841struct efx_phy_operations falcon_sfx7101_phy_ops = { 794struct efx_phy_operations falcon_sfx7101_phy_ops = {
diff --git a/drivers/net/sfc/xenpack.h b/drivers/net/sfc/xenpack.h
index b0d1f225b70a..4e52286e542d 100644
--- a/drivers/net/sfc/xenpack.h
+++ b/drivers/net/sfc/xenpack.h
@@ -34,29 +34,24 @@
34/* Enable LASI interrupts for PHY */ 34/* Enable LASI interrupts for PHY */
35static inline void xenpack_enable_lasi_irqs(struct efx_nic *efx) 35static inline void xenpack_enable_lasi_irqs(struct efx_nic *efx)
36{ 36{
37 int reg;
38 int phy_id = efx->mii.phy_id;
39 /* Read to clear LASI status register */ 37 /* Read to clear LASI status register */
40 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, 38 efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_XP_LASI_STAT);
41 MDIO_XP_LASI_STAT);
42 39
43 mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, 40 efx_mdio_write(efx, MDIO_MMD_PMAPMD, MDIO_XP_LASI_CTRL,
44 MDIO_XP_LASI_CTRL, XP_LASI_LS_ALARM); 41 XP_LASI_LS_ALARM);
45} 42}
46 43
47/* Read the LASI interrupt status to clear the interrupt. */ 44/* Read the LASI interrupt status to clear the interrupt. */
48static inline int xenpack_clear_lasi_irqs(struct efx_nic *efx) 45static inline int xenpack_clear_lasi_irqs(struct efx_nic *efx)
49{ 46{
50 /* Read to clear link status alarm */ 47 /* Read to clear link status alarm */
51 return mdio_clause45_read(efx, efx->mii.phy_id, 48 return efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_XP_LASI_STAT);
52 MDIO_MMD_PMAPMD, MDIO_XP_LASI_STAT);
53} 49}
54 50
55/* Turn off LASI interrupts */ 51/* Turn off LASI interrupts */
56static inline void xenpack_disable_lasi_irqs(struct efx_nic *efx) 52static inline void xenpack_disable_lasi_irqs(struct efx_nic *efx)
57{ 53{
58 mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, 54 efx_mdio_write(efx, MDIO_MMD_PMAPMD, MDIO_XP_LASI_CTRL, 0);
59 MDIO_XP_LASI_CTRL, 0);
60} 55}
61 56
62#endif /* EFX_XENPACK_H */ 57#endif /* EFX_XENPACK_H */
diff --git a/drivers/net/sfc/xfp_phy.c b/drivers/net/sfc/xfp_phy.c
index bb1ef77d5f56..aad2dca19772 100644
--- a/drivers/net/sfc/xfp_phy.c
+++ b/drivers/net/sfc/xfp_phy.c
@@ -19,9 +19,9 @@
19#include "phy.h" 19#include "phy.h"
20#include "falcon.h" 20#include "falcon.h"
21 21
22#define XFP_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PCS | \ 22#define XFP_REQUIRED_DEVS (MDIO_DEVS_PCS | \
23 MDIO_MMDREG_DEVS_PMAPMD | \ 23 MDIO_DEVS_PMAPMD | \
24 MDIO_MMDREG_DEVS_PHYXS) 24 MDIO_DEVS_PHYXS)
25 25
26#define XFP_LOOPBACKS ((1 << LOOPBACK_PCS) | \ 26#define XFP_LOOPBACKS ((1 << LOOPBACK_PCS) | \
27 (1 << LOOPBACK_PMAPMD) | \ 27 (1 << LOOPBACK_PMAPMD) | \
@@ -49,8 +49,7 @@
49void xfp_set_led(struct efx_nic *p, int led, int mode) 49void xfp_set_led(struct efx_nic *p, int led, int mode)
50{ 50{
51 int addr = MDIO_QUAKE_LED0_REG + led; 51 int addr = MDIO_QUAKE_LED0_REG + led;
52 mdio_clause45_write(p, p->mii.phy_id, MDIO_MMD_PMAPMD, addr, 52 efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
53 mode);
54} 53}
55 54
56struct xfp_phy_data { 55struct xfp_phy_data {
@@ -63,14 +62,12 @@ struct xfp_phy_data {
63static int qt2025c_wait_reset(struct efx_nic *efx) 62static int qt2025c_wait_reset(struct efx_nic *efx)
64{ 63{
65 unsigned long timeout = jiffies + 10 * HZ; 64 unsigned long timeout = jiffies + 10 * HZ;
66 int phy_id = efx->mii.phy_id;
67 int reg, old_counter = 0; 65 int reg, old_counter = 0;
68 66
69 /* Wait for firmware heartbeat to start */ 67 /* Wait for firmware heartbeat to start */
70 for (;;) { 68 for (;;) {
71 int counter; 69 int counter;
72 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS, 70 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
73 PCS_FW_HEARTBEAT_REG);
74 if (reg < 0) 71 if (reg < 0)
75 return reg; 72 return reg;
76 counter = ((reg >> PCS_FW_HEARTB_LBN) & 73 counter = ((reg >> PCS_FW_HEARTB_LBN) &
@@ -86,8 +83,7 @@ static int qt2025c_wait_reset(struct efx_nic *efx)
86 83
87 /* Wait for firmware status to look good */ 84 /* Wait for firmware status to look good */
88 for (;;) { 85 for (;;) {
89 reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS, 86 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
90 PCS_UC8051_STATUS_REG);
91 if (reg < 0) 87 if (reg < 0)
92 return reg; 88 return reg;
93 if ((reg & 89 if ((reg &
@@ -109,9 +105,9 @@ static int xfp_reset_phy(struct efx_nic *efx)
109{ 105{
110 int rc; 106 int rc;
111 107
112 rc = mdio_clause45_reset_mmd(efx, MDIO_MMD_PHYXS, 108 rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
113 XFP_MAX_RESET_TIME / XFP_RESET_WAIT, 109 XFP_MAX_RESET_TIME / XFP_RESET_WAIT,
114 XFP_RESET_WAIT); 110 XFP_RESET_WAIT);
115 if (rc < 0) 111 if (rc < 0)
116 goto fail; 112 goto fail;
117 113
@@ -126,8 +122,7 @@ static int xfp_reset_phy(struct efx_nic *efx)
126 122
127 /* Check that all the MMDs we expect are present and responding. We 123 /* Check that all the MMDs we expect are present and responding. We
128 * expect faults on some if the link is down, but not on the PHY XS */ 124 * expect faults on some if the link is down, but not on the PHY XS */
129 rc = mdio_clause45_check_mmds(efx, XFP_REQUIRED_DEVS, 125 rc = efx_mdio_check_mmds(efx, XFP_REQUIRED_DEVS, MDIO_DEVS_PHYXS);
130 MDIO_MMDREG_DEVS_PHYXS);
131 if (rc < 0) 126 if (rc < 0)
132 goto fail; 127 goto fail;
133 128
@@ -143,7 +138,7 @@ static int xfp_reset_phy(struct efx_nic *efx)
143static int xfp_phy_init(struct efx_nic *efx) 138static int xfp_phy_init(struct efx_nic *efx)
144{ 139{
145 struct xfp_phy_data *phy_data; 140 struct xfp_phy_data *phy_data;
146 u32 devid = mdio_clause45_read_id(efx, MDIO_MMD_PHYXS); 141 u32 devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
147 int rc; 142 int rc;
148 143
149 phy_data = kzalloc(sizeof(struct xfp_phy_data), GFP_KERNEL); 144 phy_data = kzalloc(sizeof(struct xfp_phy_data), GFP_KERNEL);
@@ -152,8 +147,8 @@ static int xfp_phy_init(struct efx_nic *efx)
152 efx->phy_data = phy_data; 147 efx->phy_data = phy_data;
153 148
154 EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n", 149 EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
155 devid, mdio_id_oui(devid), mdio_id_model(devid), 150 devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
156 mdio_id_rev(devid)); 151 efx_mdio_id_rev(devid));
157 152
158 phy_data->phy_mode = efx->phy_mode; 153 phy_data->phy_mode = efx->phy_mode;
159 154
@@ -179,7 +174,7 @@ static void xfp_phy_clear_interrupt(struct efx_nic *efx)
179 174
180static int xfp_link_ok(struct efx_nic *efx) 175static int xfp_link_ok(struct efx_nic *efx)
181{ 176{
182 return mdio_clause45_links_ok(efx, XFP_REQUIRED_DEVS); 177 return efx_mdio_links_ok(efx, XFP_REQUIRED_DEVS);
183} 178}
184 179
185static void xfp_phy_poll(struct efx_nic *efx) 180static void xfp_phy_poll(struct efx_nic *efx)
@@ -200,9 +195,9 @@ static void xfp_phy_reconfigure(struct efx_nic *efx)
200 * or optical transceivers, varying somewhat between 195 * or optical transceivers, varying somewhat between
201 * firmware versions. Only 'static mode' appears to 196 * firmware versions. Only 'static mode' appears to
202 * cover everything. */ 197 * cover everything. */
203 mdio_clause45_set_flag( 198 mdio_set_flag(
204 efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, 199 &efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
205 PMA_PMD_FTX_CTRL2_REG, PMA_PMD_FTX_STATIC_LBN, 200 PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
206 efx->phy_mode & PHY_MODE_TX_DISABLED || 201 efx->phy_mode & PHY_MODE_TX_DISABLED ||
207 efx->phy_mode & PHY_MODE_LOW_POWER || 202 efx->phy_mode & PHY_MODE_LOW_POWER ||
208 efx->loopback_mode == LOOPBACK_PCS || 203 efx->loopback_mode == LOOPBACK_PCS ||
@@ -213,10 +208,10 @@ static void xfp_phy_reconfigure(struct efx_nic *efx)
213 (phy_data->phy_mode & PHY_MODE_TX_DISABLED)) 208 (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
214 xfp_reset_phy(efx); 209 xfp_reset_phy(efx);
215 210
216 mdio_clause45_transmit_disable(efx); 211 efx_mdio_transmit_disable(efx);
217 } 212 }
218 213
219 mdio_clause45_phy_reconfigure(efx); 214 efx_mdio_phy_reconfigure(efx);
220 215
221 phy_data->phy_mode = efx->phy_mode; 216 phy_data->phy_mode = efx->phy_mode;
222 efx->link_up = xfp_link_ok(efx); 217 efx->link_up = xfp_link_ok(efx);
@@ -225,6 +220,10 @@ static void xfp_phy_reconfigure(struct efx_nic *efx)
225 efx->link_fc = efx->wanted_fc; 220 efx->link_fc = efx->wanted_fc;
226} 221}
227 222
223static void xfp_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
224{
225 mdio45_ethtool_gset(&efx->mdio, ecmd);
226}
228 227
229static void xfp_phy_fini(struct efx_nic *efx) 228static void xfp_phy_fini(struct efx_nic *efx)
230{ 229{
@@ -243,8 +242,8 @@ struct efx_phy_operations falcon_xfp_phy_ops = {
243 .poll = xfp_phy_poll, 242 .poll = xfp_phy_poll,
244 .fini = xfp_phy_fini, 243 .fini = xfp_phy_fini,
245 .clear_interrupt = xfp_phy_clear_interrupt, 244 .clear_interrupt = xfp_phy_clear_interrupt,
246 .get_settings = mdio_clause45_get_settings, 245 .get_settings = xfp_phy_get_settings,
247 .set_settings = mdio_clause45_set_settings, 246 .set_settings = efx_mdio_set_settings,
248 .mmds = XFP_REQUIRED_DEVS, 247 .mmds = XFP_REQUIRED_DEVS,
249 .loopbacks = XFP_LOOPBACKS, 248 .loopbacks = XFP_LOOPBACKS,
250}; 249};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 11:43:14 -0500