diff options
-rw-r--r-- | sound/soc/davinci/davinci-i2s.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c index 81ff5c37ab56..156e3e95d914 100644 --- a/sound/soc/davinci/davinci-i2s.c +++ b/sound/soc/davinci/davinci-i2s.c | |||
@@ -235,18 +235,45 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
235 | 235 | ||
236 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | 236 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { |
237 | case SND_SOC_DAIFMT_IB_NF: | 237 | case SND_SOC_DAIFMT_IB_NF: |
238 | /* CLKRP Receive clock polarity, | ||
239 | * 1 - sampled on rising edge of CLKR | ||
240 | * valid on rising edge | ||
241 | * CLKXP Transmit clock polarity, | ||
242 | * 1 - clocked on falling edge of CLKX | ||
243 | * valid on rising edge | ||
244 | * FSRP Receive frame sync pol, 0 - active high | ||
245 | * FSXP Transmit frame sync pol, 0 - active high | ||
246 | */ | ||
238 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG); | 247 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG); |
239 | MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP | | 248 | MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP | |
240 | DAVINCI_MCBSP_PCR_CLKRP, 1); | 249 | DAVINCI_MCBSP_PCR_CLKRP, 1); |
241 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w); | 250 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w); |
242 | break; | 251 | break; |
243 | case SND_SOC_DAIFMT_NB_IF: | 252 | case SND_SOC_DAIFMT_NB_IF: |
253 | /* CLKRP Receive clock polarity, | ||
254 | * 0 - sampled on falling edge of CLKR | ||
255 | * valid on falling edge | ||
256 | * CLKXP Transmit clock polarity, | ||
257 | * 0 - clocked on rising edge of CLKX | ||
258 | * valid on falling edge | ||
259 | * FSRP Receive frame sync pol, 1 - active low | ||
260 | * FSXP Transmit frame sync pol, 1 - active low | ||
261 | */ | ||
244 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG); | 262 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG); |
245 | MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP | | 263 | MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_FSXP | |
246 | DAVINCI_MCBSP_PCR_FSRP, 1); | 264 | DAVINCI_MCBSP_PCR_FSRP, 1); |
247 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w); | 265 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w); |
248 | break; | 266 | break; |
249 | case SND_SOC_DAIFMT_IB_IF: | 267 | case SND_SOC_DAIFMT_IB_IF: |
268 | /* CLKRP Receive clock polarity, | ||
269 | * 1 - sampled on rising edge of CLKR | ||
270 | * valid on rising edge | ||
271 | * CLKXP Transmit clock polarity, | ||
272 | * 1 - clocked on falling edge of CLKX | ||
273 | * valid on rising edge | ||
274 | * FSRP Receive frame sync pol, 1 - active low | ||
275 | * FSXP Transmit frame sync pol, 1 - active low | ||
276 | */ | ||
250 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG); | 277 | w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_PCR_REG); |
251 | MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP | | 278 | MOD_REG_BIT(w, DAVINCI_MCBSP_PCR_CLKXP | |
252 | DAVINCI_MCBSP_PCR_CLKRP | | 279 | DAVINCI_MCBSP_PCR_CLKRP | |
@@ -255,6 +282,15 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
255 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w); | 282 | davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, w); |
256 | break; | 283 | break; |
257 | case SND_SOC_DAIFMT_NB_NF: | 284 | case SND_SOC_DAIFMT_NB_NF: |
285 | /* CLKRP Receive clock polarity, | ||
286 | * 0 - sampled on falling edge of CLKR | ||
287 | * valid on falling edge | ||
288 | * CLKXP Transmit clock polarity, | ||
289 | * 0 - clocked on rising edge of CLKX | ||
290 | * valid on falling edge | ||
291 | * FSRP Receive frame sync pol, 0 - active high | ||
292 | * FSXP Transmit frame sync pol, 0 - active high | ||
293 | */ | ||
258 | break; | 294 | break; |
259 | default: | 295 | default: |
260 | return -EINVAL; | 296 | return -EINVAL; |