diff options
-rw-r--r-- | arch/arm/mach-tegra/include/mach/pinmux.h | 4 | ||||
-rw-r--r-- | arch/arm/mach-tegra/pinmux-t2-tables.c | 76 | ||||
-rw-r--r-- | arch/arm/mach-tegra/pinmux.c | 137 |
3 files changed, 123 insertions, 94 deletions
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h index defd8775defa..bb7dfdb61205 100644 --- a/arch/arm/mach-tegra/include/mach/pinmux.h +++ b/arch/arm/mach-tegra/include/mach/pinmux.h | |||
@@ -199,6 +199,7 @@ struct tegra_drive_pingroup_config { | |||
199 | 199 | ||
200 | struct tegra_drive_pingroup_desc { | 200 | struct tegra_drive_pingroup_desc { |
201 | const char *name; | 201 | const char *name; |
202 | s16 reg_bank; | ||
202 | s16 reg; | 203 | s16 reg; |
203 | }; | 204 | }; |
204 | 205 | ||
@@ -207,6 +208,9 @@ struct tegra_pingroup_desc { | |||
207 | int funcs[4]; | 208 | int funcs[4]; |
208 | int func_safe; | 209 | int func_safe; |
209 | int vddio; | 210 | int vddio; |
211 | s16 tri_bank; /* Register bank the tri_reg exists within */ | ||
212 | s16 mux_bank; /* Register bank the mux_reg exists within */ | ||
213 | s16 pupd_bank; /* Register bank the pupd_reg exists within */ | ||
210 | s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */ | 214 | s16 tri_reg; /* offset into the TRISTATE_REG_* register bank */ |
211 | s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */ | 215 | s16 mux_reg; /* offset into the PIN_MUX_CTL_* register bank */ |
212 | s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */ | 216 | s16 pupd_reg; /* offset into the PULL_UPDOWN_REG_* register bank */ |
diff --git a/arch/arm/mach-tegra/pinmux-t2-tables.c b/arch/arm/mach-tegra/pinmux-t2-tables.c index a475367befa3..a0dc2bc28ed3 100644 --- a/arch/arm/mach-tegra/pinmux-t2-tables.c +++ b/arch/arm/mach-tegra/pinmux-t2-tables.c | |||
@@ -31,10 +31,16 @@ | |||
31 | #include <mach/pinmux.h> | 31 | #include <mach/pinmux.h> |
32 | #include <mach/suspend.h> | 32 | #include <mach/suspend.h> |
33 | 33 | ||
34 | #define TRISTATE_REG_A 0x14 | ||
35 | #define PIN_MUX_CTL_REG_A 0x80 | ||
36 | #define PULLUPDOWN_REG_A 0xa0 | ||
37 | #define PINGROUP_REG_A 0x868 | ||
38 | |||
34 | #define DRIVE_PINGROUP(pg_name, r) \ | 39 | #define DRIVE_PINGROUP(pg_name, r) \ |
35 | [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ | 40 | [TEGRA_DRIVE_PINGROUP_ ## pg_name] = { \ |
36 | .name = #pg_name, \ | 41 | .name = #pg_name, \ |
37 | .reg = r \ | 42 | .reg_bank = 3, \ |
43 | .reg = ((r) - PINGROUP_REG_A) \ | ||
38 | } | 44 | } |
39 | 45 | ||
40 | const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { | 46 | const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE_PINGROUP] = { |
@@ -90,11 +96,14 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE | |||
90 | TEGRA_MUX_ ## f3, \ | 96 | TEGRA_MUX_ ## f3, \ |
91 | }, \ | 97 | }, \ |
92 | .func_safe = TEGRA_MUX_ ## f_safe, \ | 98 | .func_safe = TEGRA_MUX_ ## f_safe, \ |
93 | .tri_reg = tri_r, \ | 99 | .tri_bank = 0, \ |
100 | .tri_reg = ((tri_r) - TRISTATE_REG_A), \ | ||
94 | .tri_bit = tri_b, \ | 101 | .tri_bit = tri_b, \ |
95 | .mux_reg = mux_r, \ | 102 | .mux_bank = 1, \ |
103 | .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \ | ||
96 | .mux_bit = mux_b, \ | 104 | .mux_bit = mux_b, \ |
97 | .pupd_reg = pupd_r, \ | 105 | .pupd_bank = 2, \ |
106 | .pupd_reg = ((pupd_r) - PULLUPDOWN_REG_A), \ | ||
98 | .pupd_bit = pupd_b, \ | 107 | .pupd_bit = pupd_b, \ |
99 | } | 108 | } |
100 | 109 | ||
@@ -217,62 +226,3 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[TEGRA_MAX_PINGROUP] = { | |||
217 | PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30), | 226 | PINGROUP(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 30), |
218 | PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28), | 227 | PINGROUP(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, -1, -1, -1, -1, 0xA8, 28), |
219 | }; | 228 | }; |
220 | |||
221 | #ifdef CONFIG_PM | ||
222 | #define TRISTATE_REG_A 0x14 | ||
223 | #define TRISTATE_REG_NUM 4 | ||
224 | #define PIN_MUX_CTL_REG_A 0x80 | ||
225 | #define PIN_MUX_CTL_REG_NUM 8 | ||
226 | #define PULLUPDOWN_REG_A 0xa0 | ||
227 | #define PULLUPDOWN_REG_NUM 5 | ||
228 | |||
229 | static u32 pinmux_reg[TRISTATE_REG_NUM + PIN_MUX_CTL_REG_NUM + | ||
230 | PULLUPDOWN_REG_NUM + | ||
231 | ARRAY_SIZE(tegra_soc_drive_pingroups)]; | ||
232 | |||
233 | static inline unsigned long pg_readl(unsigned long offset) | ||
234 | { | ||
235 | return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset)); | ||
236 | } | ||
237 | |||
238 | static inline void pg_writel(unsigned long value, unsigned long offset) | ||
239 | { | ||
240 | writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset)); | ||
241 | } | ||
242 | |||
243 | void tegra_pinmux_suspend(void) | ||
244 | { | ||
245 | unsigned int i; | ||
246 | u32 *ctx = pinmux_reg; | ||
247 | |||
248 | for (i = 0; i < PIN_MUX_CTL_REG_NUM; i++) | ||
249 | *ctx++ = pg_readl(PIN_MUX_CTL_REG_A + i*4); | ||
250 | |||
251 | for (i = 0; i < PULLUPDOWN_REG_NUM; i++) | ||
252 | *ctx++ = pg_readl(PULLUPDOWN_REG_A + i*4); | ||
253 | |||
254 | for (i = 0; i < TRISTATE_REG_NUM; i++) | ||
255 | *ctx++ = pg_readl(TRISTATE_REG_A + i*4); | ||
256 | |||
257 | for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++) | ||
258 | *ctx++ = pg_readl(tegra_soc_drive_pingroups[i].reg); | ||
259 | } | ||
260 | |||
261 | void tegra_pinmux_resume(void) | ||
262 | { | ||
263 | unsigned int i; | ||
264 | u32 *ctx = pinmux_reg; | ||
265 | |||
266 | for (i = 0; i < PIN_MUX_CTL_REG_NUM; i++) | ||
267 | pg_writel(*ctx++, PIN_MUX_CTL_REG_A + i*4); | ||
268 | |||
269 | for (i = 0; i < PULLUPDOWN_REG_NUM; i++) | ||
270 | pg_writel(*ctx++, PULLUPDOWN_REG_A + i*4); | ||
271 | |||
272 | for (i = 0; i < TRISTATE_REG_NUM; i++) | ||
273 | pg_writel(*ctx++, TRISTATE_REG_A + i*4); | ||
274 | |||
275 | for (i = 0; i < ARRAY_SIZE(tegra_soc_drive_pingroups); i++) | ||
276 | pg_writel(*ctx++, tegra_soc_drive_pingroups[i].reg); | ||
277 | } | ||
278 | #endif | ||
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c index fb212177c515..1d201650d7a4 100644 --- a/arch/arm/mach-tegra/pinmux.c +++ b/arch/arm/mach-tegra/pinmux.c | |||
@@ -170,15 +170,17 @@ static const char *pupd_name(unsigned long val) | |||
170 | } | 170 | } |
171 | } | 171 | } |
172 | 172 | ||
173 | static int nbanks; | ||
174 | static void __iomem **regs; | ||
173 | 175 | ||
174 | static inline unsigned long pg_readl(unsigned long offset) | 176 | static inline u32 pg_readl(u32 bank, u32 reg) |
175 | { | 177 | { |
176 | return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset)); | 178 | return readl(regs[bank] + reg); |
177 | } | 179 | } |
178 | 180 | ||
179 | static inline void pg_writel(unsigned long value, unsigned long offset) | 181 | static inline void pg_writel(u32 val, u32 bank, u32 reg) |
180 | { | 182 | { |
181 | writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset)); | 183 | writel(val, regs[bank] + reg); |
182 | } | 184 | } |
183 | 185 | ||
184 | static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config) | 186 | static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config) |
@@ -218,10 +220,10 @@ static int tegra_pinmux_set_func(const struct tegra_pingroup_config *config) | |||
218 | 220 | ||
219 | spin_lock_irqsave(&mux_lock, flags); | 221 | spin_lock_irqsave(&mux_lock, flags); |
220 | 222 | ||
221 | reg = pg_readl(pingroups[pg].mux_reg); | 223 | reg = pg_readl(pingroups[pg].mux_bank, pingroups[pg].mux_reg); |
222 | reg &= ~(0x3 << pingroups[pg].mux_bit); | 224 | reg &= ~(0x3 << pingroups[pg].mux_bit); |
223 | reg |= mux << pingroups[pg].mux_bit; | 225 | reg |= mux << pingroups[pg].mux_bit; |
224 | pg_writel(reg, pingroups[pg].mux_reg); | 226 | pg_writel(reg, pingroups[pg].mux_bank, pingroups[pg].mux_reg); |
225 | 227 | ||
226 | spin_unlock_irqrestore(&mux_lock, flags); | 228 | spin_unlock_irqrestore(&mux_lock, flags); |
227 | 229 | ||
@@ -242,11 +244,11 @@ int tegra_pinmux_set_tristate(enum tegra_pingroup pg, | |||
242 | 244 | ||
243 | spin_lock_irqsave(&mux_lock, flags); | 245 | spin_lock_irqsave(&mux_lock, flags); |
244 | 246 | ||
245 | reg = pg_readl(pingroups[pg].tri_reg); | 247 | reg = pg_readl(pingroups[pg].tri_bank, pingroups[pg].tri_reg); |
246 | reg &= ~(0x1 << pingroups[pg].tri_bit); | 248 | reg &= ~(0x1 << pingroups[pg].tri_bit); |
247 | if (tristate) | 249 | if (tristate) |
248 | reg |= 1 << pingroups[pg].tri_bit; | 250 | reg |= 1 << pingroups[pg].tri_bit; |
249 | pg_writel(reg, pingroups[pg].tri_reg); | 251 | pg_writel(reg, pingroups[pg].tri_bank, pingroups[pg].tri_reg); |
250 | 252 | ||
251 | spin_unlock_irqrestore(&mux_lock, flags); | 253 | spin_unlock_irqrestore(&mux_lock, flags); |
252 | 254 | ||
@@ -273,10 +275,10 @@ int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, | |||
273 | 275 | ||
274 | spin_lock_irqsave(&mux_lock, flags); | 276 | spin_lock_irqsave(&mux_lock, flags); |
275 | 277 | ||
276 | reg = pg_readl(pingroups[pg].pupd_reg); | 278 | reg = pg_readl(pingroups[pg].pupd_bank, pingroups[pg].pupd_reg); |
277 | reg &= ~(0x3 << pingroups[pg].pupd_bit); | 279 | reg &= ~(0x3 << pingroups[pg].pupd_bit); |
278 | reg |= pupd << pingroups[pg].pupd_bit; | 280 | reg |= pupd << pingroups[pg].pupd_bit; |
279 | pg_writel(reg, pingroups[pg].pupd_reg); | 281 | pg_writel(reg, pingroups[pg].pupd_bank, pingroups[pg].pupd_reg); |
280 | 282 | ||
281 | spin_unlock_irqrestore(&mux_lock, flags); | 283 | spin_unlock_irqrestore(&mux_lock, flags); |
282 | 284 | ||
@@ -363,12 +365,12 @@ static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg, | |||
363 | 365 | ||
364 | spin_lock_irqsave(&mux_lock, flags); | 366 | spin_lock_irqsave(&mux_lock, flags); |
365 | 367 | ||
366 | reg = pg_readl(drive_pingroups[pg].reg); | 368 | reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
367 | if (hsm == TEGRA_HSM_ENABLE) | 369 | if (hsm == TEGRA_HSM_ENABLE) |
368 | reg |= (1 << 2); | 370 | reg |= (1 << 2); |
369 | else | 371 | else |
370 | reg &= ~(1 << 2); | 372 | reg &= ~(1 << 2); |
371 | pg_writel(reg, drive_pingroups[pg].reg); | 373 | pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
372 | 374 | ||
373 | spin_unlock_irqrestore(&mux_lock, flags); | 375 | spin_unlock_irqrestore(&mux_lock, flags); |
374 | 376 | ||
@@ -388,12 +390,12 @@ static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg, | |||
388 | 390 | ||
389 | spin_lock_irqsave(&mux_lock, flags); | 391 | spin_lock_irqsave(&mux_lock, flags); |
390 | 392 | ||
391 | reg = pg_readl(drive_pingroups[pg].reg); | 393 | reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
392 | if (schmitt == TEGRA_SCHMITT_ENABLE) | 394 | if (schmitt == TEGRA_SCHMITT_ENABLE) |
393 | reg |= (1 << 3); | 395 | reg |= (1 << 3); |
394 | else | 396 | else |
395 | reg &= ~(1 << 3); | 397 | reg &= ~(1 << 3); |
396 | pg_writel(reg, drive_pingroups[pg].reg); | 398 | pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
397 | 399 | ||
398 | spin_unlock_irqrestore(&mux_lock, flags); | 400 | spin_unlock_irqrestore(&mux_lock, flags); |
399 | 401 | ||
@@ -413,10 +415,10 @@ static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg, | |||
413 | 415 | ||
414 | spin_lock_irqsave(&mux_lock, flags); | 416 | spin_lock_irqsave(&mux_lock, flags); |
415 | 417 | ||
416 | reg = pg_readl(drive_pingroups[pg].reg); | 418 | reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
417 | reg &= ~(0x3 << 4); | 419 | reg &= ~(0x3 << 4); |
418 | reg |= drive << 4; | 420 | reg |= drive << 4; |
419 | pg_writel(reg, drive_pingroups[pg].reg); | 421 | pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
420 | 422 | ||
421 | spin_unlock_irqrestore(&mux_lock, flags); | 423 | spin_unlock_irqrestore(&mux_lock, flags); |
422 | 424 | ||
@@ -436,10 +438,10 @@ static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg, | |||
436 | 438 | ||
437 | spin_lock_irqsave(&mux_lock, flags); | 439 | spin_lock_irqsave(&mux_lock, flags); |
438 | 440 | ||
439 | reg = pg_readl(drive_pingroups[pg].reg); | 441 | reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
440 | reg &= ~(0x1f << 12); | 442 | reg &= ~(0x1f << 12); |
441 | reg |= pull_down << 12; | 443 | reg |= pull_down << 12; |
442 | pg_writel(reg, drive_pingroups[pg].reg); | 444 | pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
443 | 445 | ||
444 | spin_unlock_irqrestore(&mux_lock, flags); | 446 | spin_unlock_irqrestore(&mux_lock, flags); |
445 | 447 | ||
@@ -459,10 +461,10 @@ static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg, | |||
459 | 461 | ||
460 | spin_lock_irqsave(&mux_lock, flags); | 462 | spin_lock_irqsave(&mux_lock, flags); |
461 | 463 | ||
462 | reg = pg_readl(drive_pingroups[pg].reg); | 464 | reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
463 | reg &= ~(0x1f << 12); | 465 | reg &= ~(0x1f << 12); |
464 | reg |= pull_up << 12; | 466 | reg |= pull_up << 12; |
465 | pg_writel(reg, drive_pingroups[pg].reg); | 467 | pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
466 | 468 | ||
467 | spin_unlock_irqrestore(&mux_lock, flags); | 469 | spin_unlock_irqrestore(&mux_lock, flags); |
468 | 470 | ||
@@ -482,10 +484,10 @@ static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg, | |||
482 | 484 | ||
483 | spin_lock_irqsave(&mux_lock, flags); | 485 | spin_lock_irqsave(&mux_lock, flags); |
484 | 486 | ||
485 | reg = pg_readl(drive_pingroups[pg].reg); | 487 | reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
486 | reg &= ~(0x3 << 28); | 488 | reg &= ~(0x3 << 28); |
487 | reg |= slew_rising << 28; | 489 | reg |= slew_rising << 28; |
488 | pg_writel(reg, drive_pingroups[pg].reg); | 490 | pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
489 | 491 | ||
490 | spin_unlock_irqrestore(&mux_lock, flags); | 492 | spin_unlock_irqrestore(&mux_lock, flags); |
491 | 493 | ||
@@ -505,10 +507,10 @@ static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg, | |||
505 | 507 | ||
506 | spin_lock_irqsave(&mux_lock, flags); | 508 | spin_lock_irqsave(&mux_lock, flags); |
507 | 509 | ||
508 | reg = pg_readl(drive_pingroups[pg].reg); | 510 | reg = pg_readl(drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
509 | reg &= ~(0x3 << 30); | 511 | reg &= ~(0x3 << 30); |
510 | reg |= slew_falling << 30; | 512 | reg |= slew_falling << 30; |
511 | pg_writel(reg, drive_pingroups[pg].reg); | 513 | pg_writel(reg, drive_pingroups[pg].reg_bank, drive_pingroups[pg].reg); |
512 | 514 | ||
513 | spin_unlock_irqrestore(&mux_lock, flags); | 515 | spin_unlock_irqrestore(&mux_lock, flags); |
514 | 516 | ||
@@ -668,6 +670,74 @@ void tegra_pinmux_config_pullupdown_table(const struct tegra_pingroup_config *co | |||
668 | 670 | ||
669 | static int __devinit tegra_pinmux_probe(struct platform_device *pdev) | 671 | static int __devinit tegra_pinmux_probe(struct platform_device *pdev) |
670 | { | 672 | { |
673 | struct resource *res; | ||
674 | int i; | ||
675 | int config_bad = 0; | ||
676 | |||
677 | for (i = 0; ; i++) { | ||
678 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); | ||
679 | if (!res) | ||
680 | break; | ||
681 | } | ||
682 | nbanks = i; | ||
683 | |||
684 | for (i = 0; i < TEGRA_MAX_PINGROUP; i++) { | ||
685 | if (pingroups[i].tri_bank >= nbanks) { | ||
686 | dev_err(&pdev->dev, "pingroup %d: bad tri_bank\n", i); | ||
687 | config_bad = 1; | ||
688 | } | ||
689 | |||
690 | if (pingroups[i].mux_bank >= nbanks) { | ||
691 | dev_err(&pdev->dev, "pingroup %d: bad mux_bank\n", i); | ||
692 | config_bad = 1; | ||
693 | } | ||
694 | |||
695 | if (pingroups[i].pupd_bank >= nbanks) { | ||
696 | dev_err(&pdev->dev, "pingroup %d: bad pupd_bank\n", i); | ||
697 | config_bad = 1; | ||
698 | } | ||
699 | } | ||
700 | |||
701 | for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) { | ||
702 | if (drive_pingroups[i].reg_bank >= nbanks) { | ||
703 | dev_err(&pdev->dev, | ||
704 | "drive pingroup %d: bad reg_bank\n", i); | ||
705 | config_bad = 1; | ||
706 | } | ||
707 | } | ||
708 | |||
709 | if (config_bad) | ||
710 | return -ENODEV; | ||
711 | |||
712 | regs = devm_kzalloc(&pdev->dev, nbanks * sizeof(*regs), GFP_KERNEL); | ||
713 | if (!regs) { | ||
714 | dev_err(&pdev->dev, "Can't alloc regs pointer\n"); | ||
715 | return -ENODEV; | ||
716 | } | ||
717 | |||
718 | for (i = 0; i < nbanks; i++) { | ||
719 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); | ||
720 | if (!res) { | ||
721 | dev_err(&pdev->dev, "Missing MEM resource\n"); | ||
722 | return -ENODEV; | ||
723 | } | ||
724 | |||
725 | if (!devm_request_mem_region(&pdev->dev, res->start, | ||
726 | resource_size(res), | ||
727 | dev_name(&pdev->dev))) { | ||
728 | dev_err(&pdev->dev, | ||
729 | "Couldn't request MEM resource %d\n", i); | ||
730 | return -ENODEV; | ||
731 | } | ||
732 | |||
733 | regs[i] = devm_ioremap(&pdev->dev, res->start, | ||
734 | resource_size(res)); | ||
735 | if (!regs) { | ||
736 | dev_err(&pdev->dev, "Couldn't ioremap regs %d\n", i); | ||
737 | return -ENODEV; | ||
738 | } | ||
739 | } | ||
740 | |||
671 | return 0; | 741 | return 0; |
672 | } | 742 | } |
673 | 743 | ||
@@ -710,6 +780,7 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused) | |||
710 | int len; | 780 | int len; |
711 | 781 | ||
712 | for (i = 0; i < TEGRA_MAX_PINGROUP; i++) { | 782 | for (i = 0; i < TEGRA_MAX_PINGROUP; i++) { |
783 | unsigned long reg; | ||
713 | unsigned long tri; | 784 | unsigned long tri; |
714 | unsigned long mux; | 785 | unsigned long mux; |
715 | unsigned long pupd; | 786 | unsigned long pupd; |
@@ -722,8 +793,9 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused) | |||
722 | seq_printf(s, "TEGRA_MUX_NONE"); | 793 | seq_printf(s, "TEGRA_MUX_NONE"); |
723 | len = strlen("NONE"); | 794 | len = strlen("NONE"); |
724 | } else { | 795 | } else { |
725 | mux = (pg_readl(pingroups[i].mux_reg) >> | 796 | reg = pg_readl(pingroups[i].mux_bank, |
726 | pingroups[i].mux_bit) & 0x3; | 797 | pingroups[i].mux_reg); |
798 | mux = (reg >> pingroups[i].mux_bit) & 0x3; | ||
727 | if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) { | 799 | if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) { |
728 | seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1); | 800 | seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1); |
729 | len = 5; | 801 | len = 5; |
@@ -739,8 +811,9 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused) | |||
739 | seq_printf(s, "TEGRA_PUPD_NORMAL"); | 811 | seq_printf(s, "TEGRA_PUPD_NORMAL"); |
740 | len = strlen("NORMAL"); | 812 | len = strlen("NORMAL"); |
741 | } else { | 813 | } else { |
742 | pupd = (pg_readl(pingroups[i].pupd_reg) >> | 814 | reg = pg_readl(pingroups[i].pupd_bank, |
743 | pingroups[i].pupd_bit) & 0x3; | 815 | pingroups[i].pupd_reg); |
816 | pupd = (reg >> pingroups[i].pupd_bit) & 0x3; | ||
744 | seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd)); | 817 | seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd)); |
745 | len = strlen(pupd_name(pupd)); | 818 | len = strlen(pupd_name(pupd)); |
746 | } | 819 | } |
@@ -749,8 +822,9 @@ static int dbg_pinmux_show(struct seq_file *s, void *unused) | |||
749 | if (pingroups[i].tri_reg < 0) { | 822 | if (pingroups[i].tri_reg < 0) { |
750 | seq_printf(s, "TEGRA_TRI_NORMAL"); | 823 | seq_printf(s, "TEGRA_TRI_NORMAL"); |
751 | } else { | 824 | } else { |
752 | tri = (pg_readl(pingroups[i].tri_reg) >> | 825 | reg = pg_readl(pingroups[i].tri_bank, |
753 | pingroups[i].tri_bit) & 0x1; | 826 | pingroups[i].tri_reg); |
827 | tri = (reg >> pingroups[i].tri_bit) & 0x1; | ||
754 | 828 | ||
755 | seq_printf(s, "TEGRA_TRI_%s", tri_name(tri)); | 829 | seq_printf(s, "TEGRA_TRI_%s", tri_name(tri)); |
756 | } | 830 | } |
@@ -785,7 +859,8 @@ static int dbg_drive_pinmux_show(struct seq_file *s, void *unused) | |||
785 | dbg_pad_field(s, 7 - len); | 859 | dbg_pad_field(s, 7 - len); |
786 | 860 | ||
787 | 861 | ||
788 | reg = pg_readl(drive_pingroups[i].reg); | 862 | reg = pg_readl(drive_pingroups[i].reg_bank, |
863 | drive_pingroups[i].reg); | ||
789 | if (HSM_EN(reg)) { | 864 | if (HSM_EN(reg)) { |
790 | seq_printf(s, "TEGRA_HSM_ENABLE"); | 865 | seq_printf(s, "TEGRA_HSM_ENABLE"); |
791 | len = 16; | 866 | len = 16; |