250 files changed, 12675 insertions, 2282 deletions
diff --git a/Documentation/arm/Samsung-S3C24XX/EB2410ITX.txt b/Documentation/arm/Samsung-S3C24XX/EB2410ITX.txt
index 26422f0f9080..b87292e05f2f 100644
--- a/Documentation/arm/Samsung-S3C24XX/EB2410ITX.txt
+++ b/Documentation/arm/Samsung-S3C24XX/EB2410ITX.txt
@@ -55,4 +55,4 @@ Maintainers
  This board is maintained by Simtec Electronics.
-(c) 2004 Ben Dooks, Simtec Electronics
+Copyright 2004 Ben Dooks, Simtec Electronics
diff --git a/Documentation/arm/Samsung-S3C24XX/GPIO.txt b/Documentation/arm/Samsung-S3C24XX/GPIO.txt
index 948c8718d967..2af2cf39915f 100644
--- a/Documentation/arm/Samsung-S3C24XX/GPIO.txt
+++ b/Documentation/arm/Samsung-S3C24XX/GPIO.txt
@@ -134,4 +134,4 @@ Authour
 Ben Dooks, 03 October 2004
-(c) 2004 Ben Dooks, Simtec Electronics
+Copyright 2004 Ben Dooks, Simtec Electronics
diff --git a/Documentation/arm/Samsung-S3C24XX/Overview.txt b/Documentation/arm/Samsung-S3C24XX/Overview.txt
index cff6227b4484..081892df4fda 100644
--- a/Documentation/arm/Samsung-S3C24XX/Overview.txt
+++ b/Documentation/arm/Samsung-S3C24XX/Overview.txt
@@ -299,4 +299,4 @@ Port Contributors
 Document Author
 ---------------
-Ben Dooks, (c) 2004-2005,2006 Simtec Electronics
+Ben Dooks, Copyright 2004-2006 Simtec Electronics
diff --git a/Documentation/arm/Samsung-S3C24XX/S3C2412.txt b/Documentation/arm/Samsung-S3C24XX/S3C2412.txt
index 295d971a15ed..f057876b920b 100644
--- a/Documentation/arm/Samsung-S3C24XX/S3C2412.txt
+++ b/Documentation/arm/Samsung-S3C24XX/S3C2412.txt
@@ -117,4 +117,4 @@ ATA
 Document Author
 ---------------
-Ben Dooks, (c) 2006 Simtec Electronics
+Ben Dooks, Copyright 2006 Simtec Electronics
diff --git a/Documentation/arm/Samsung-S3C24XX/S3C2413.txt b/Documentation/arm/Samsung-S3C24XX/S3C2413.txt
index ab2a88858f12..909bdc7dd7b5 100644
--- a/Documentation/arm/Samsung-S3C24XX/S3C2413.txt
+++ b/Documentation/arm/Samsung-S3C24XX/S3C2413.txt
@@ -18,4 +18,4 @@ Camera Interface
 Document Author
 ---------------
-Ben Dooks, (c) 2006 Simtec Electronics
+Ben Dooks, Copyright 2006 Simtec Electronics
diff --git a/Documentation/arm/Samsung-S3C24XX/Suspend.txt b/Documentation/arm/Samsung-S3C24XX/Suspend.txt
index a30fe510572b..7edd0e2e6c5b 100644
--- a/Documentation/arm/Samsung-S3C24XX/Suspend.txt
+++ b/Documentation/arm/Samsung-S3C24XX/Suspend.txt
@@ -133,5 +133,5 @@ Configuration
 Document Author
 ---------------
-Ben Dooks, (c) 2004 Simtec Electronics
+Ben Dooks, Copyright 2004 Simtec Electronics
diff --git a/Documentation/arm/Samsung-S3C24XX/USB-Host.txt b/Documentation/arm/Samsung-S3C24XX/USB-Host.txt
index 67671eba4231..f82b1faefad5 100644
--- a/Documentation/arm/Samsung-S3C24XX/USB-Host.txt
+++ b/Documentation/arm/Samsung-S3C24XX/USB-Host.txt
@@ -90,4 +90,4 @@ Platform Data
 Document Author
 ---------------
-Ben Dooks, (c) 2005 Simtec Electronics
+Ben Dooks, Copyright 2005 Simtec Electronics
diff --git a/Documentation/filesystems/ocfs2.txt b/Documentation/filesystems/ocfs2.txt
index c2a0871280a0..c58b9f5ba002 100644
--- a/Documentation/filesystems/ocfs2.txt
+++ b/Documentation/filesystems/ocfs2.txt
@@ -20,15 +20,16 @@ Lots of code taken from ext3 and other projects.
 Authors in alphabetical order:
 Joel Becker   <joel.becker@oracle.com>
 Zach Brown    <zach.brown@oracle.com>
-Mark Fasheh   <mark.fasheh@oracle.com>
+Mark Fasheh   <mfasheh@suse.com>
 Kurt Hackel   <kurt.hackel@oracle.com>
+Tao Ma        <tao.ma@oracle.com>
 Sunil Mushran <sunil.mushran@oracle.com>
 Manish Singh  <manish.singh@oracle.com>
+Tiger Yang    <tiger.yang@oracle.com>
 Caveats
 =======
 Features which OCFS2 does not support yet:
-        - quotas
        - Directory change notification (F_NOTIFY)
        - Distributed Caching (F_SETLEASE/F_GETLEASE/break_lease)
@@ -70,7 +71,6 @@ commit=nrsec	(*)	Ocfs2 can be told to sync all its data and metadata
                        performance.
 localalloc=8(*)         Allows custom localalloc size in MB. If the value is too
                        large, the fs will silently revert it to the default.
-                        Localalloc is not enabled for local mounts.
 localflocks             This disables cluster aware flock.
 inode64                 Indicates that Ocfs2 is allowed to create inodes at
                        any location in the filesystem, including those which
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1c4119c60040..7d0818797c85 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -433,6 +433,17 @@ config ARCH_L7200
          If you have any questions or comments about the Linux kernel port
          to this board, send e-mail to <sjhill@cotw.com>.
+config ARCH_DOVE
+        bool "Marvell Dove"
+        select PCI
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select PLAT_ORION
+        help
+          Support for the Marvell Dove SoC 88AP510
 config ARCH_KIRKWOOD
        bool "Marvell Kirkwood"
        select CPU_FEROCEON
@@ -747,6 +758,9 @@ source "arch/arm/mach-orion5x/Kconfig"
 source "arch/arm/mach-kirkwood/Kconfig"
+source "arch/arm/mach-dove/Kconfig"
+source "arch/arm/plat-samsung/Kconfig"
 source "arch/arm/plat-s3c24xx/Kconfig"
 source "arch/arm/plat-s3c64xx/Kconfig"
 source "arch/arm/plat-s3c/Kconfig"
@@ -810,6 +824,8 @@ config ARCH_ACORN
 config PLAT_IOP
        bool
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_TIME
 config PLAT_ORION
        bool
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index a73caaf66763..8c0d08fbd991 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -122,6 +122,7 @@ machine-$(CONFIG_ARCH_AT91)		:= at91
 machine-$(CONFIG_ARCH_BCMRING)          := bcmring
 machine-$(CONFIG_ARCH_CLPS711X)         := clps711x
 machine-$(CONFIG_ARCH_DAVINCI)          := davinci
+machine-$(CONFIG_ARCH_DOVE)             := dove
 machine-$(CONFIG_ARCH_EBSA110)          := ebsa110
 machine-$(CONFIG_ARCH_EP93XX)           := ep93xx
 machine-$(CONFIG_ARCH_GEMINI)           := gemini
@@ -178,9 +179,9 @@ plat-$(CONFIG_ARCH_OMAP)	:= omap
 plat-$(CONFIG_PLAT_IOP)         := iop
 plat-$(CONFIG_PLAT_ORION)       := orion
 plat-$(CONFIG_PLAT_PXA)         := pxa
-plat-$(CONFIG_PLAT_S3C24XX)     := s3c24xx s3c
+plat-$(CONFIG_PLAT_S3C24XX)     := s3c24xx s3c samsung
-plat-$(CONFIG_PLAT_S3C64XX)     := s3c64xx s3c
+plat-$(CONFIG_PLAT_S3C64XX)     := s3c64xx s3c samsung
-plat-$(CONFIG_PLAT_S5PC1XX)     := s5pc1xx s3c
+plat-$(CONFIG_PLAT_S5PC1XX)     := s5pc1xx s3c samsung
 plat-$(CONFIG_ARCH_STMP3XXX)    := stmp3xxx
 ifeq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index fa6fbf45cf3b..d356af7cef82 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -743,6 +743,12 @@ proc_types:
                W(b)    __armv4_mmu_cache_off
                W(b)    __armv6_mmu_cache_flush
+                .word   0x560f5810              @ Marvell PJ4 ARMv6
+                .word   0xff0ffff0
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv6_mmu_cache_flush
                .word   0x000f0000              @ new CPU Id
                .word   0x000f0000
                W(b)    __armv7_mmu_cache_on
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
new file mode 100644
index 000000000000..b3a491675d59
--- /dev/null
+++ b/arch/arm/configs/dove_defconfig
@@ -0,0 +1,1620 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32-rc6
+# Tue Nov 24 13:53:37 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+CONFIG_ARCH_DOVE=y
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+#
+# Marvell Dove Implementations
+#
+CONFIG_MACH_DOVE_DB=y
+CONFIG_PLAT_ORION=y
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_V6=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_TAUROS2=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+# CONFIG_ARM_ERRATA_411920 is not set
+#
+# Bus support
+#
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+CONFIG_VFP=y
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+CONFIG_SATA_MV=y
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+#
+# IEEE 1394 (FireWire) support
+#
+#
+# You can enable one or both FireWire driver stacks.
+#
+#
+# See the help texts for more information.
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_NET_ETHERNET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+CONFIG_MV643XX_ETH=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+CONFIG_WLAN=y
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=y
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+#
+# I2C Hardware Bus support
+#
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_MV64XXX=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+#
+# Graphics adapter I2C/DDC channel drivers
+#
+# CONFIG_I2C_VOODOO3 is not set
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_ORION=y
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_LANGWELL is not set
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_MV=y
+CONFIG_DMADEVICES=y
+#
+# DMA Devices
+#
+CONFIG_MV_XOR=y
+CONFIG_DMA_ENGINE=y
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_ZISOFS is not set
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_UBIFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+CONFIG_CRYPTO_PCBC=m
+# CONFIG_CRYPTO_XTS is not set
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_GHASH is not set
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_BLOWFISH=y
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+CONFIG_CRYPTO_TEA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_MV_CESA is not set
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h
new file mode 100644
index 000000000000..538f17ca905b
--- /dev/null
+++ b/arch/arm/include/asm/hardware/cache-tauros2.h
@@ -0,0 +1,11 @@
+/*
+ * arch/arm/include/asm/hardware/cache-tauros2.h
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+extern void __init tauros2_init(void);
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index 8d60ad267e3a..5daea2961d48 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -234,7 +234,13 @@ extern int iop3xx_get_init_atu(void);
 void iop3xx_map_io(void);
 void iop_init_cp6_handler(void);
 void iop_init_time(unsigned long tickrate);
-unsigned long iop_gettimeoffset(void);
+static inline u32 read_tmr0(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val));
+        return val;
+}
 static inline void write_tmr0(u32 val)
 {
@@ -253,6 +259,11 @@ static inline u32 read_tcr0(void)
        return val;
 }
+static inline void write_tcr0(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val));
+}
 static inline u32 read_tcr1(void)
 {
        u32 val;
@@ -260,6 +271,11 @@ static inline u32 read_tcr1(void)
        return val;
 }
+static inline void write_tcr1(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val));
+}
 static inline void write_trr0(u32 val)
 {
        asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val));
diff --git a/arch/arm/include/asm/kmap_types.h b/arch/arm/include/asm/kmap_types.h
index d16ec97ec9a9..c019949a5189 100644
--- a/arch/arm/include/asm/kmap_types.h
+++ b/arch/arm/include/asm/kmap_types.h
@@ -22,4 +22,10 @@ enum km_type {
        KM_TYPE_NR
 };
+#ifdef CONFIG_DEBUG_HIGHMEM
+#define KM_NMI          (-1)
+#define KM_NMI_PTE      (-1)
+#define KM_IRQ_PTE      (-1)
+#endif
 #endif
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index e5dfc2895e24..573b803dc6bf 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -32,7 +32,7 @@
 * numbers for r1.
 *
 */
-        .section ".text.head", "ax"
+        __HEAD
 ENTRY(stext)
        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                @ and irqs disabled
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 38ccbe1d3b2c..eb62bf947212 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -74,7 +74,7 @@
 * crap here - that's what the boot loader (or in extreme, well justified
 * circumstances, zImage) is for.
 */
-        .section ".text.head", "ax"
+        __HEAD
 ENTRY(stext)
        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                @ and irqs disabled
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index aecf87dfbaec..71151bd87a36 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -24,13 +24,11 @@ SECTIONS
 #else
        . = PAGE_OFFSET + TEXT_OFFSET;
 #endif
-        .text.head : {
-                _stext = .;
-                _sinittext = .;
-                *(.text.head)
-        }
        .init : {                       /* Init code and data           */
+                _stext = .;
+                _sinittext = .;
+                        HEAD_TEXT
                        INIT_TEXT
                _einittext = .;
                __proc_info_begin = .;
@@ -42,43 +40,31 @@ SECTIONS
                __tagtable_begin = .;
                        *(.taglist.init)
                __tagtable_end = .;
-                . = ALIGN(16);
-                __setup_start = .;
+                INIT_SETUP(16)
-                        *(.init.setup)
-                __setup_end = .;
                __early_begin = .;
                        *(.early_param.init)
                __early_end = .;
-                __initcall_start = .;
-                        INITCALLS
+                INIT_CALLS
-                __initcall_end = .;
+                CON_INITCALL
-                __con_initcall_start = .;
+                SECURITY_INITCALL
-                        *(.con_initcall.init)
+                INIT_RAM_FS
-                __con_initcall_end = .;
-                __security_initcall_start = .;
-                        *(.security_initcall.init)
-                __security_initcall_end = .;
-#ifdef CONFIG_BLK_DEV_INITRD
-                . = ALIGN(32);
-                __initramfs_start = .;
-                        usr/built-in.o(.init.ramfs)
-                __initramfs_end = .;
-#endif
-                . = ALIGN(PAGE_SIZE);
-                __per_cpu_load = .;
-                __per_cpu_start = .;
-                        *(.data.percpu.page_aligned)
-                        *(.data.percpu)
-                        *(.data.percpu.shared_aligned)
-                __per_cpu_end = .;
 #ifndef CONFIG_XIP_KERNEL
                __init_begin = _stext;
                INIT_DATA
-                . = ALIGN(PAGE_SIZE);
-                __init_end = .;
 #endif
        }
+        PERCPU(PAGE_SIZE)
+#ifndef CONFIG_XIP_KERNEL
+        . = ALIGN(PAGE_SIZE);
+        __init_end = .;
+#endif
        /DISCARD/ : {                   /* Exit code and data           */
                EXIT_TEXT
                EXIT_DATA
@@ -157,7 +143,7 @@ SECTIONS
                 * first, the init task union, aligned
                 * to an 8192 byte boundary.
                 */
-                *(.data.init_task)
+                INIT_TASK_DATA(THREAD_SIZE)
 #ifdef CONFIG_XIP_KERNEL
                . = ALIGN(PAGE_SIZE);
@@ -167,17 +153,8 @@ SECTIONS
                __init_end = .;
 #endif
-                . = ALIGN(PAGE_SIZE);
+                NOSAVE_DATA
-                __nosave_begin = .;
+                CACHELINE_ALIGNED_DATA(32)
-                *(.data.nosave)
-                . = ALIGN(PAGE_SIZE);
-                __nosave_end = .;
-                /*
-                 * then the cacheline aligned data
-                 */
-                . = ALIGN(32);
-                *(.data.cacheline_aligned)
                /*
                 * The exception fixup table (might need resorting at runtime)
@@ -256,20 +233,10 @@ SECTIONS
        }
 #endif
-        .bss : {
+        BSS_SECTION(0, 0, 0)
-                __bss_start = .;        /* BSS                          */
+        _end = .;
-                *(.bss)
-                *(COMMON)
+        STABS_DEBUG
-                __bss_stop = .;
-                _end = .;
-        }
-                                        /* Stabs debugging sections.    */
-        .stab 0 : { *(.stab) }
-        .stabstr 0 : { *(.stabstr) }
-        .stab.excl 0 : { *(.stab.excl) }
-        .stab.exclstr 0 : { *(.stab.exclstr) }
-        .stab.index 0 : { *(.stab.index) }
-        .stab.indexstr 0 : { *(.stab.indexstr) }
        .comment 0 : { *(.comment) }
 }
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 2fd88437348b..3df124e54267 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,5 +1,20 @@
 if ARCH_AT91
+config HAVE_AT91_DATAFLASH_CARD
+        bool
+config HAVE_NAND_ATMEL_BUSWIDTH_16
+        bool
+config HAVE_AT91_USART3
+        bool
+config HAVE_AT91_USART4
+        bool
+config HAVE_AT91_USART5
+        bool
 menu "Atmel AT91 System-on-Chip"
 choice
@@ -10,54 +25,69 @@ config ARCH_AT91RM9200
        select CPU_ARM920T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_USART3
 config ARCH_AT91SAM9260
        bool "AT91SAM9260 or AT91SAM9XE"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_USART3
+        select HAVE_AT91_USART4
+        select HAVE_AT91_USART5
 config ARCH_AT91SAM9261
        bool "AT91SAM9261"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_FB_ATMEL
 config ARCH_AT91SAM9G10
        bool "AT91SAM9G10"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_FB_ATMEL
 config ARCH_AT91SAM9263
        bool "AT91SAM9263"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_FB_ATMEL
 config ARCH_AT91SAM9RL
        bool "AT91SAM9RL"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_USART3
+        select HAVE_FB_ATMEL
 config ARCH_AT91SAM9G20
        bool "AT91SAM9G20"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_USART3
+        select HAVE_AT91_USART4
+        select HAVE_AT91_USART5
 config ARCH_AT91SAM9G45
        bool "AT91SAM9G45"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_USART3
+        select HAVE_FB_ATMEL
 config ARCH_AT91CAP9
        bool "AT91CAP9"
        select CPU_ARM926T
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select HAVE_FB_ATMEL
 config ARCH_AT91X40
        bool "AT91x40"
@@ -76,89 +106,79 @@ comment "AT91RM9200 Board Type"
 config MACH_ONEARM
        bool "Ajeco 1ARM Single Board Computer"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using Ajeco's 1ARM Single Board Computer.
          <http://www.ajeco.fi/products.htm>
 config ARCH_AT91RM9200DK
        bool "Atmel AT91RM9200-DK Development board"
-        depends on ARCH_AT91RM9200
+        select HAVE_AT91_DATAFLASH_CARD
        help
          Select this if you are using Atmel's AT91RM9200-DK Development board.
          (Discontinued)
 config MACH_AT91RM9200EK
        bool "Atmel AT91RM9200-EK Evaluation Kit"
-        depends on ARCH_AT91RM9200
+        select HAVE_AT91_DATAFLASH_CARD
        help
          Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
 config MACH_CSB337
        bool "Cogent CSB337"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using Cogent's CSB337 board.
          <http://www.cogcomp.com/csb_csb337.htm>
 config MACH_CSB637
        bool "Cogent CSB637"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using Cogent's CSB637 board.
          <http://www.cogcomp.com/csb_csb637.htm>
 config MACH_CARMEVA
        bool "Conitec ARM&EVA"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using Conitec's AT91RM9200-MCU-Module.
          <http://www.conitec.net/english/linuxboard.htm>
 config MACH_ATEB9200
        bool "Embest ATEB9200"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using Embest's ATEB9200 board.
          <http://www.embedinfo.com/english/product/ATEB9200.asp>
 config MACH_KB9200
        bool "KwikByte KB920x"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using KwikByte's KB920x board.
          <http://kwikbyte.com/KB9202_description_new.htm>
 config MACH_PICOTUX2XX
        bool "picotux 200"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using a picotux 200.
          <http://www.picotux.com/>
 config MACH_KAFA
        bool "Sperry-Sun KAFA board"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using Sperry-Sun's KAFA board.
 config MACH_ECBAT91
        bool "emQbit ECB_AT91 SBC"
-        depends on ARCH_AT91RM9200
+        select HAVE_AT91_DATAFLASH_CARD
        help
          Select this if you are using emQbit's ECB_AT91 board.
          <http://wiki.emqbit.com/free-ecb-at91>
 config MACH_YL9200
        bool "ucDragon YL-9200"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using the ucDragon YL-9200 board.
 config MACH_CPUAT91
        bool "Eukrea CPUAT91"
-        depends on ARCH_AT91RM9200
        help
          Select this if you are using the Eukrea Electromatique's
          CPUAT91 board <http://www.eukrea.com/>.
@@ -173,7 +193,6 @@ comment "AT91SAM9260 Variants"
 config ARCH_AT91SAM9260_SAM9XE
        bool "AT91SAM9XE"
-        depends on ARCH_AT91SAM9260
        help
          Select this if you are using Atmel's AT91SAM9XE System-on-Chip.
          They are basically AT91SAM9260s with various sizes of embedded Flash.
@@ -182,28 +201,27 @@ comment "AT91SAM9260 / AT91SAM9XE Board Type"
 config MACH_AT91SAM9260EK
        bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit"
-        depends on ARCH_AT91SAM9260
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
 config MACH_CAM60
        bool "KwikByte KB9260 (CAM60) board"
-        depends on ARCH_AT91SAM9260
        help
          Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
          <http://www.kwikbyte.com/KB9260.html>
 config MACH_SAM9_L9260
        bool "Olimex SAM9-L9260 board"
-        depends on ARCH_AT91SAM9260
+        select HAVE_AT91_DATAFLASH_CARD
        help
          Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
          <http://www.olimex.com/dev/sam9-L9260.html>
 config MACH_AFEB9260
        bool "Custom afeb9260 board v1"
-        depends on ARCH_AT91SAM9260
        help
          Select this if you are using custom afeb9260 board based on
          open hardware design. Select this for revision 1 of the board.
@@ -212,21 +230,18 @@ config MACH_AFEB9260
 config MACH_USB_A9260
        bool "CALAO USB-A9260"
-        depends on ARCH_AT91SAM9260
        help
          Select this if you are using a Calao Systems USB-A9260.
          <http://www.calao-systems.com>
 config MACH_QIL_A9260
        bool "CALAO QIL-A9260 board"
-        depends on ARCH_AT91SAM9260
        help
          Select this if you are using a Calao Systems QIL-A9260 Board.
          <http://www.calao-systems.com>
 config MACH_CPU9260
        bool "Eukrea CPU9260 board"
-        depends on ARCH_AT91SAM9260
        help
          Select this if you are using a Eukrea Electromatique's
          CPU9260 Board <http://www.eukrea.com/>
@@ -241,7 +256,8 @@ comment "AT91SAM9261 Board Type"
 config MACH_AT91SAM9261EK
        bool "Atmel AT91SAM9261-EK Evaluation Kit"
-        depends on ARCH_AT91SAM9261
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
@@ -256,7 +272,8 @@ comment "AT91SAM9G10 Board Type"
 config MACH_AT91SAM9G10EK
        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
-        depends on ARCH_AT91SAM9G10
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
@@ -271,21 +288,21 @@ comment "AT91SAM9263 Board Type"
 config MACH_AT91SAM9263EK
        bool "Atmel AT91SAM9263-EK Evaluation Kit"
-        depends on ARCH_AT91SAM9263
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
 config MACH_USB_A9263
        bool "CALAO USB-A9263"
-        depends on ARCH_AT91SAM9263
        help
          Select this if you are using a Calao Systems USB-A9263.
          <http://www.calao-systems.com>
 config MACH_NEOCORE926
        bool "Adeneo NEOCORE926"
-        depends on ARCH_AT91SAM9263
+        select HAVE_AT91_DATAFLASH_CARD
        help
          Select this if you are using the Adeneo Neocore 926 board.
@@ -299,7 +316,6 @@ comment "AT91SAM9RL Board Type"
 config MACH_AT91SAM9RLEK
        bool "Atmel AT91SAM9RL-EK Evaluation Kit"
-        depends on ARCH_AT91SAM9RL
        help
          Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
@@ -313,14 +329,15 @@ comment "AT91SAM9G20 Board Type"
 config MACH_AT91SAM9G20EK
        bool "Atmel AT91SAM9G20-EK Evaluation Kit"
-        depends on ARCH_AT91SAM9G20
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit
          that embeds only one SD/MMC slot.
 config MACH_AT91SAM9G20EK_2MMC
        bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
-        depends on ARCH_AT91SAM9G20
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
          with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
@@ -328,7 +345,6 @@ config MACH_AT91SAM9G20EK_2MMC
 config MACH_CPU9G20
        bool "Eukrea CPU9G20 board"
-        depends on ARCH_AT91SAM9G20
        help
          Select this if you are using a Eukrea Electromatique's
          CPU9G20 Board <http://www.eukrea.com/>
@@ -343,7 +359,7 @@ comment "AT91SAM9G45 Board Type"
 config MACH_AT91SAM9G45EKES
        bool "Atmel AT91SAM9G45-EKES Evaluation Kit"
-        depends on ARCH_AT91SAM9G45
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
          "ES" at the end of the name means that this board is an
@@ -359,7 +375,8 @@ comment "AT91CAP9 Board Type"
 config MACH_AT91CAP9ADK
        bool "Atmel AT91CAP9A-DK Evaluation Kit"
-        depends on ARCH_AT91CAP9
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit.
          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138>
@@ -388,13 +405,13 @@ comment "AT91 Board Options"
 config MTD_AT91_DATAFLASH_CARD
        bool "Enable DataFlash Card support"
-        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK || MACH_NEOCORE926)
+        depends on HAVE_AT91_DATAFLASH_CARD
        help
          Enable support for the DataFlash card.
 config MTD_NAND_ATMEL_BUSWIDTH_16
        bool "Enable 16-bit data bus interface to NAND flash"
-        depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91SAM9G20EK_2MMC || MACH_AT91SAM9G45EKES || MACH_AT91CAP9ADK)
+        depends on HAVE_NAND_ATMEL_BUSWIDTH_16
        help
          On AT91SAM926x boards both types of NAND flash can be present
          (8 and 16 bit data bus width).
@@ -456,15 +473,15 @@ config AT91_EARLY_USART2
 config AT91_EARLY_USART3
        bool "USART3"
-        depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 || ARCH_AT91SAM9G45)
+        depends on HAVE_AT91_USART3
 config AT91_EARLY_USART4
        bool "USART4"
-        depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20
+        depends on HAVE_AT91_USART4
 config AT91_EARLY_USART5
        bool "USART5"
-        depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20
+        depends on HAVE_AT91_USART5
 endchoice
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
new file mode 100644
index 000000000000..3b9a32ace909
--- /dev/null
+++ b/arch/arm/mach-dove/Kconfig
@@ -0,0 +1,14 @@
+if ARCH_DOVE
+menu "Marvell Dove Implementations"
+config MACH_DOVE_DB
+        bool "Marvell DB-MV88AP510 Development Board"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell DB-MV88AP510 Development Board.
+endmenu
+endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
new file mode 100644
index 000000000000..7ab3be53f642
--- /dev/null
+++ b/arch/arm/mach-dove/Makefile
@@ -0,0 +1,3 @@
+obj-y                           += common.o addr-map.o irq.o pcie.o
+obj-$(CONFIG_MACH_DOVE_DB)      += dove-db-setup.o
diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-dove/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
new file mode 100644
index 000000000000..00be4fc26dd7
--- /dev/null
+++ b/arch/arm/mach-dove/addr-map.c
@@ -0,0 +1,149 @@
+/*
+ * arch/arm/mach-dove/addr-map.c
+ *
+ * Address map functions for Marvell Dove 88AP510 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <asm/mach/arch.h>
+#include <asm/setup.h>
+#include "common.h"
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define TARGET_DDR              0x0
+#define TARGET_BOOTROM          0x1
+#define TARGET_CESA             0x3
+#define TARGET_PCIE0            0x4
+#define TARGET_PCIE1            0x8
+#define TARGET_SCRATCHPAD       0xd
+#define ATTR_CESA               0x01
+#define ATTR_BOOTROM            0xfd
+#define ATTR_DEV_SPI0_ROM       0xfe
+#define ATTR_DEV_SPI1_ROM       0xfb
+#define ATTR_PCIE_IO            0xe0
+#define ATTR_PCIE_MEM           0xe8
+#define ATTR_SCRATCHPAD         0x0
+/*
+ * CPU Address Decode Windows registers
+ */
+#define WIN_CTRL(n)     (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0)
+#define WIN_BASE(n)     (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4)
+#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8)
+#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc)
+struct mbus_dram_target_info dove_mbus_dram_info;
+static inline void __iomem *ddr_map_sc(int i)
+{
+        return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
+}
+static int cpu_win_can_remap(int win)
+{
+        if (win < 4)
+                return 1;
+        return 0;
+}
+static void __init setup_cpu_win(int win, u32 base, u32 size,
+                                 u8 target, u8 attr, int remap)
+{
+        u32 ctrl;
+        base &= 0xffff0000;
+        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
+        writel(base, WIN_BASE(win));
+        writel(ctrl, WIN_CTRL(win));
+        if (cpu_win_can_remap(win)) {
+                if (remap < 0)
+                        remap = base;
+                writel(remap & 0xffff0000, WIN_REMAP_LO(win));
+                writel(0, WIN_REMAP_HI(win));
+        }
+}
+void __init dove_setup_cpu_mbus(void)
+{
+        int i;
+        int cs;
+        /*
+         * First, disable and clear windows.
+         */
+        for (i = 0; i < 8; i++) {
+                writel(0, WIN_BASE(i));
+                writel(0, WIN_CTRL(i));
+                if (cpu_win_can_remap(i)) {
+                        writel(0, WIN_REMAP_LO(i));
+                        writel(0, WIN_REMAP_HI(i));
+                }
+        }
+        /*
+         * Setup windows for PCIe IO+MEM space.
+         */
+        setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
+                      TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE);
+        setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
+                      TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE);
+        setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
+                      TARGET_PCIE0, ATTR_PCIE_MEM, -1);
+        setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
+                      TARGET_PCIE1, ATTR_PCIE_MEM, -1);
+        /*
+         * Setup window for CESA engine.
+         */
+        setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
+                      TARGET_CESA, ATTR_CESA, -1);
+        /*
+         * Setup the Window to the BootROM for Standby and Sleep Resume
+         */
+        setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
+                      TARGET_BOOTROM, ATTR_BOOTROM, -1);
+        /*
+         * Setup the Window to the PMU Scratch Pad space
+         */
+        setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
+                      TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1);
+        /*
+         * Setup MBUS dram target info.
+         */
+        dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+        for (i = 0, cs = 0; i < 2; i++) {
+                u32 map = readl(ddr_map_sc(i));
+                /*
+                 * Chip select enabled?
+                 */
+                if (map & 1) {
+                        struct mbus_dram_window *w;
+                        w = &dove_mbus_dram_info.cs[cs++];
+                        w->cs_index = i;
+                        w->mbus_attr = 0; /* CS address decoding done inside */
+                                          /* the DDR controller, no need to  */
+                                          /* provide attributes */
+                        w->base = map & 0xff800000;
+                        w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
+                }
+        }
+        dove_mbus_dram_info.num_cs = cs;
+}
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
new file mode 100644
index 000000000000..806972a68c87
--- /dev/null
+++ b/arch/arm/mach-dove/common.c
@@ -0,0 +1,781 @@
+/*
+ * arch/arm/mach-dove/common.c
+ *
+ * Core functions for Marvell Dove 88AP510 System On Chip
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/serial_8250.h>
+#include <linux/clk.h>
+#include <linux/mbus.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/mv643xx_i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/spi/orion_spi.h>
+#include <linux/gpio.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+#include <asm/timex.h>
+#include <asm/hardware/cache-tauros2.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/mach/pci.h>
+#include <mach/dove.h>
+#include <mach/bridge-regs.h>
+#include <asm/mach/arch.h>
+#include <linux/irq.h>
+#include <plat/mv_xor.h>
+#include <plat/ehci-orion.h>
+#include <plat/time.h>
+#include "common.h"
+/*****************************************************************************
+ * I/O Address Mapping
+ ****************************************************************************/
+static struct map_desc dove_io_desc[] __initdata = {
+        {
+                .virtual        = DOVE_SB_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
+                .length         = DOVE_SB_REGS_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = DOVE_NB_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
+                .length         = DOVE_NB_REGS_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = DOVE_PCIE0_IO_VIRT_BASE,
+                .pfn            = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
+                .length         = DOVE_PCIE0_IO_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = DOVE_PCIE1_IO_VIRT_BASE,
+                .pfn            = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
+                .length         = DOVE_PCIE1_IO_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+void __init dove_map_io(void)
+{
+        iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
+}
+/*****************************************************************************
+ * EHCI
+ ****************************************************************************/
+static struct orion_ehci_data dove_ehci_data = {
+        .dram           = &dove_mbus_dram_info,
+        .phy_version    = EHCI_PHY_NA,
+};
+static u64 ehci_dmamask = DMA_BIT_MASK(32);
+/*****************************************************************************
+ * EHCI0
+ ****************************************************************************/
+static struct resource dove_ehci0_resources[] = {
+        {
+                .start  = DOVE_USB0_PHYS_BASE,
+                .end    = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_USB0,
+                .end    = IRQ_DOVE_USB0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_ehci0 = {
+        .name           = "orion-ehci",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &dove_ehci_data,
+        },
+        .resource       = dove_ehci0_resources,
+        .num_resources  = ARRAY_SIZE(dove_ehci0_resources),
+};
+void __init dove_ehci0_init(void)
+{
+        platform_device_register(&dove_ehci0);
+}
+/*****************************************************************************
+ * EHCI1
+ ****************************************************************************/
+static struct resource dove_ehci1_resources[] = {
+        {
+                .start  = DOVE_USB1_PHYS_BASE,
+                .end    = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_USB1,
+                .end    = IRQ_DOVE_USB1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_ehci1 = {
+        .name           = "orion-ehci",
+        .id             = 1,
+        .dev            = {
+                .dma_mask               = &ehci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &dove_ehci_data,
+        },
+        .resource       = dove_ehci1_resources,
+        .num_resources  = ARRAY_SIZE(dove_ehci1_resources),
+};
+void __init dove_ehci1_init(void)
+{
+        platform_device_register(&dove_ehci1);
+}
+/*****************************************************************************
+ * GE00
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
+        .t_clk          = 0,
+        .dram           = &dove_mbus_dram_info,
+};
+static struct resource dove_ge00_shared_resources[] = {
+        {
+                .name   = "ge00 base",
+                .start  = DOVE_GE00_PHYS_BASE + 0x2000,
+                .end    = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device dove_ge00_shared = {
+        .name           = MV643XX_ETH_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &dove_ge00_shared_data,
+        },
+        .num_resources  = 1,
+        .resource       = dove_ge00_shared_resources,
+};
+static struct resource dove_ge00_resources[] = {
+        {
+                .name   = "ge00 irq",
+                .start  = IRQ_DOVE_GE00_SUM,
+                .end    = IRQ_DOVE_GE00_SUM,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_ge00 = {
+        .name           = MV643XX_ETH_NAME,
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = dove_ge00_resources,
+        .dev            = {
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
+{
+        eth_data->shared = &dove_ge00_shared;
+        dove_ge00.dev.platform_data = eth_data;
+        platform_device_register(&dove_ge00_shared);
+        platform_device_register(&dove_ge00);
+}
+/*****************************************************************************
+ * SoC RTC
+ ****************************************************************************/
+static struct resource dove_rtc_resource[] = {
+        {
+                .start  = DOVE_RTC_PHYS_BASE,
+                .end    = DOVE_RTC_PHYS_BASE + 32 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_RTC,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+void __init dove_rtc_init(void)
+{
+        platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2);
+}
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct resource dove_sata_resources[] = {
+        {
+                .name   = "sata base",
+                .start  = DOVE_SATA_PHYS_BASE,
+                .end    = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "sata irq",
+                .start  = IRQ_DOVE_SATA,
+                .end    = IRQ_DOVE_SATA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_sata = {
+        .name           = "sata_mv",
+        .id             = 0,
+        .dev            = {
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(dove_sata_resources),
+        .resource       = dove_sata_resources,
+};
+void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
+{
+        sata_data->dram = &dove_mbus_dram_info;
+        dove_sata.dev.platform_data = sata_data;
+        platform_device_register(&dove_sata);
+}
+/*****************************************************************************
+ * UART0
+ ****************************************************************************/
+static struct plat_serial8250_port dove_uart0_data[] = {
+        {
+                .mapbase        = DOVE_UART0_PHYS_BASE,
+                .membase        = (char *)DOVE_UART0_VIRT_BASE,
+                .irq            = IRQ_DOVE_UART_0,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+static struct resource dove_uart0_resources[] = {
+        {
+                .start          = DOVE_UART0_PHYS_BASE,
+                .end            = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_DOVE_UART_0,
+                .end            = IRQ_DOVE_UART_0,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_uart0 = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = dove_uart0_data,
+        },
+        .resource               = dove_uart0_resources,
+        .num_resources          = ARRAY_SIZE(dove_uart0_resources),
+};
+void __init dove_uart0_init(void)
+{
+        platform_device_register(&dove_uart0);
+}
+/*****************************************************************************
+ * UART1
+ ****************************************************************************/
+static struct plat_serial8250_port dove_uart1_data[] = {
+        {
+                .mapbase        = DOVE_UART1_PHYS_BASE,
+                .membase        = (char *)DOVE_UART1_VIRT_BASE,
+                .irq            = IRQ_DOVE_UART_1,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+static struct resource dove_uart1_resources[] = {
+        {
+                .start          = DOVE_UART1_PHYS_BASE,
+                .end            = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_DOVE_UART_1,
+                .end            = IRQ_DOVE_UART_1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_uart1 = {
+        .name                   = "serial8250",
+        .id                     = 1,
+        .dev                    = {
+                .platform_data  = dove_uart1_data,
+        },
+        .resource               = dove_uart1_resources,
+        .num_resources          = ARRAY_SIZE(dove_uart1_resources),
+};
+void __init dove_uart1_init(void)
+{
+        platform_device_register(&dove_uart1);
+}
+/*****************************************************************************
+ * UART2
+ ****************************************************************************/
+static struct plat_serial8250_port dove_uart2_data[] = {
+        {
+                .mapbase        = DOVE_UART2_PHYS_BASE,
+                .membase        = (char *)DOVE_UART2_VIRT_BASE,
+                .irq            = IRQ_DOVE_UART_2,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+static struct resource dove_uart2_resources[] = {
+        {
+                .start          = DOVE_UART2_PHYS_BASE,
+                .end            = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_DOVE_UART_2,
+                .end            = IRQ_DOVE_UART_2,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_uart2 = {
+        .name                   = "serial8250",
+        .id                     = 2,
+        .dev                    = {
+                .platform_data  = dove_uart2_data,
+        },
+        .resource               = dove_uart2_resources,
+        .num_resources          = ARRAY_SIZE(dove_uart2_resources),
+};
+void __init dove_uart2_init(void)
+{
+        platform_device_register(&dove_uart2);
+}
+/*****************************************************************************
+ * UART3
+ ****************************************************************************/
+static struct plat_serial8250_port dove_uart3_data[] = {
+        {
+                .mapbase        = DOVE_UART3_PHYS_BASE,
+                .membase        = (char *)DOVE_UART3_VIRT_BASE,
+                .irq            = IRQ_DOVE_UART_3,
+                .flags          = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = 0,
+        }, {
+        },
+};
+static struct resource dove_uart3_resources[] = {
+        {
+                .start          = DOVE_UART3_PHYS_BASE,
+                .end            = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
+                .flags          = IORESOURCE_MEM,
+        }, {
+                .start          = IRQ_DOVE_UART_3,
+                .end            = IRQ_DOVE_UART_3,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_uart3 = {
+        .name                   = "serial8250",
+        .id                     = 3,
+        .dev                    = {
+                .platform_data  = dove_uart3_data,
+        },
+        .resource               = dove_uart3_resources,
+        .num_resources          = ARRAY_SIZE(dove_uart3_resources),
+};
+void __init dove_uart3_init(void)
+{
+        platform_device_register(&dove_uart3);
+}
+/*****************************************************************************
+ * SPI0
+ ****************************************************************************/
+static struct orion_spi_info dove_spi0_data = {
+        .tclk           = 0,
+};
+static struct resource dove_spi0_resources[] = {
+        {
+                .start  = DOVE_SPI0_PHYS_BASE,
+                .end    = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_SPI0,
+                .end    = IRQ_DOVE_SPI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_spi0 = {
+        .name           = "orion_spi",
+        .id             = 0,
+        .resource       = dove_spi0_resources,
+        .dev            = {
+                .platform_data  = &dove_spi0_data,
+        },
+        .num_resources  = ARRAY_SIZE(dove_spi0_resources),
+};
+void __init dove_spi0_init(void)
+{
+        platform_device_register(&dove_spi0);
+}
+/*****************************************************************************
+ * SPI1
+ ****************************************************************************/
+static struct orion_spi_info dove_spi1_data = {
+        .tclk           = 0,
+};
+static struct resource dove_spi1_resources[] = {
+        {
+                .start  = DOVE_SPI1_PHYS_BASE,
+                .end    = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_SPI1,
+                .end    = IRQ_DOVE_SPI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_spi1 = {
+        .name           = "orion_spi",
+        .id             = 1,
+        .resource       = dove_spi1_resources,
+        .dev            = {
+                .platform_data  = &dove_spi1_data,
+        },
+        .num_resources  = ARRAY_SIZE(dove_spi1_resources),
+};
+void __init dove_spi1_init(void)
+{
+        platform_device_register(&dove_spi1);
+}
+/*****************************************************************************
+ * I2C
+ ****************************************************************************/
+static struct mv64xxx_i2c_pdata dove_i2c_data = {
+        .freq_m         = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
+        .freq_n         = 3,
+        .timeout        = 1000, /* Default timeout of 1 second */
+};
+static struct resource dove_i2c_resources[] = {
+        {
+                .name   = "i2c base",
+                .start  = DOVE_I2C_PHYS_BASE,
+                .end    = DOVE_I2C_PHYS_BASE + 0x20 - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "i2c irq",
+                .start  = IRQ_DOVE_I2C,
+                .end    = IRQ_DOVE_I2C,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device dove_i2c = {
+        .name           = MV64XXX_I2C_CTLR_NAME,
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dove_i2c_resources),
+        .resource       = dove_i2c_resources,
+        .dev            = {
+                .platform_data = &dove_i2c_data,
+        },
+};
+void __init dove_i2c_init(void)
+{
+        platform_device_register(&dove_i2c);
+}
+/*****************************************************************************
+ * Time handling
+ ****************************************************************************/
+static int get_tclk(void)
+{
+        /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
+        return 166666667;
+}
+static void dove_timer_init(void)
+{
+        orion_time_init(IRQ_DOVE_BRIDGE, get_tclk());
+}
+struct sys_timer dove_timer = {
+        .init = dove_timer_init,
+};
+/*****************************************************************************
+ * XOR
+ ****************************************************************************/
+static struct mv_xor_platform_shared_data dove_xor_shared_data = {
+        .dram           = &dove_mbus_dram_info,
+};
+/*****************************************************************************
+ * XOR 0
+ ****************************************************************************/
+static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
+static struct resource dove_xor0_shared_resources[] = {
+        {
+                .name   = "xor 0 low",
+                .start  = DOVE_XOR0_PHYS_BASE,
+                .end    = DOVE_XOR0_PHYS_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "xor 0 high",
+                .start  = DOVE_XOR0_HIGH_PHYS_BASE,
+                .end    = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device dove_xor0_shared = {
+        .name           = MV_XOR_SHARED_NAME,
+        .id             = 0,
+        .dev            = {
+                .platform_data = &dove_xor_shared_data,
+        },
+        .num_resources  = ARRAY_SIZE(dove_xor0_shared_resources),
+        .resource       = dove_xor0_shared_resources,
+};
+static struct resource dove_xor00_resources[] = {
+        [0] = {
+                .start  = IRQ_DOVE_XOR_00,
+                .end    = IRQ_DOVE_XOR_00,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct mv_xor_platform_data dove_xor00_data = {
+        .shared         = &dove_xor0_shared,
+        .hw_id          = 0,
+        .pool_size      = PAGE_SIZE,
+};
+static struct platform_device dove_xor00_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dove_xor00_resources),
+        .resource       = dove_xor00_resources,
+        .dev            = {
+                .dma_mask               = &dove_xor0_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = (void *)&dove_xor00_data,
+        },
+};
+static struct resource dove_xor01_resources[] = {
+        [0] = {
+                .start  = IRQ_DOVE_XOR_01,
+                .end    = IRQ_DOVE_XOR_01,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct mv_xor_platform_data dove_xor01_data = {
+        .shared         = &dove_xor0_shared,
+        .hw_id          = 1,
+        .pool_size      = PAGE_SIZE,
+};
+static struct platform_device dove_xor01_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(dove_xor01_resources),
+        .resource       = dove_xor01_resources,
+        .dev            = {
+                .dma_mask               = &dove_xor0_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = (void *)&dove_xor01_data,
+        },
+};
+void __init dove_xor0_init(void)
+{
+        platform_device_register(&dove_xor0_shared);
+        /*
+         * two engines can't do memset simultaneously, this limitation
+         * satisfied by removing memset support from one of the engines.
+         */
+        dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
+        dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
+        platform_device_register(&dove_xor00_channel);
+        dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
+        dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
+        dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
+        platform_device_register(&dove_xor01_channel);
+}
+/*****************************************************************************
+ * XOR 1
+ ****************************************************************************/
+static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
+static struct resource dove_xor1_shared_resources[] = {
+        {
+                .name   = "xor 0 low",
+                .start  = DOVE_XOR1_PHYS_BASE,
+                .end    = DOVE_XOR1_PHYS_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "xor 0 high",
+                .start  = DOVE_XOR1_HIGH_PHYS_BASE,
+                .end    = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device dove_xor1_shared = {
+        .name           = MV_XOR_SHARED_NAME,
+        .id             = 1,
+        .dev            = {
+                .platform_data = &dove_xor_shared_data,
+        },
+        .num_resources  = ARRAY_SIZE(dove_xor1_shared_resources),
+        .resource       = dove_xor1_shared_resources,
+};
+static struct resource dove_xor10_resources[] = {
+        [0] = {
+                .start  = IRQ_DOVE_XOR_10,
+                .end    = IRQ_DOVE_XOR_10,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct mv_xor_platform_data dove_xor10_data = {
+        .shared         = &dove_xor1_shared,
+        .hw_id          = 0,
+        .pool_size      = PAGE_SIZE,
+};
+static struct platform_device dove_xor10_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(dove_xor10_resources),
+        .resource       = dove_xor10_resources,
+        .dev            = {
+                .dma_mask               = &dove_xor1_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = (void *)&dove_xor10_data,
+        },
+};
+static struct resource dove_xor11_resources[] = {
+        [0] = {
+                .start  = IRQ_DOVE_XOR_11,
+                .end    = IRQ_DOVE_XOR_11,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct mv_xor_platform_data dove_xor11_data = {
+        .shared         = &dove_xor1_shared,
+        .hw_id          = 1,
+        .pool_size      = PAGE_SIZE,
+};
+static struct platform_device dove_xor11_channel = {
+        .name           = MV_XOR_NAME,
+        .id             = 3,
+        .num_resources  = ARRAY_SIZE(dove_xor11_resources),
+        .resource       = dove_xor11_resources,
+        .dev            = {
+                .dma_mask               = &dove_xor1_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(64),
+                .platform_data          = (void *)&dove_xor11_data,
+        },
+};
+void __init dove_xor1_init(void)
+{
+        platform_device_register(&dove_xor1_shared);
+        /*
+         * two engines can't do memset simultaneously, this limitation
+         * satisfied by removing memset support from one of the engines.
+         */
+        dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
+        dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
+        platform_device_register(&dove_xor10_channel);
+        dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
+        dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
+        dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
+        platform_device_register(&dove_xor11_channel);
+}
+void __init dove_init(void)
+{
+        int tclk;
+        tclk = get_tclk();
+        printk(KERN_INFO "Dove 88AP510 SoC, ");
+        printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000);
+#ifdef CONFIG_CACHE_TAUROS2
+        tauros2_init();
+#endif
+        dove_setup_cpu_mbus();
+        dove_ge00_shared_data.t_clk = tclk;
+        dove_uart0_data[0].uartclk = tclk;
+        dove_uart1_data[0].uartclk = tclk;
+        dove_uart2_data[0].uartclk = tclk;
+        dove_uart3_data[0].uartclk = tclk;
+        dove_spi0_data.tclk = tclk;
+        dove_spi1_data.tclk = tclk;
+        /* internal devices that every board has */
+        dove_rtc_init();
+        dove_xor0_init();
+        dove_xor1_init();
+}
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
new file mode 100644
index 000000000000..b29e8937de4f
--- /dev/null
+++ b/arch/arm/mach-dove/common.h
@@ -0,0 +1,40 @@
+/*
+ * arch/arm/mach-dove/common.h
+ *
+ * Core functions for Marvell Dove 88AP510 System On Chip
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ARCH_DOVE_COMMON_H
+#define __ARCH_DOVE_COMMON_H
+struct mv643xx_eth_platform_data;
+struct mv_sata_platform_data;
+extern struct sys_timer dove_timer;
+extern struct mbus_dram_target_info dove_mbus_dram_info;
+/*
+ * Basic Dove init functions used early by machine-setup.
+ */
+void dove_map_io(void);
+void dove_init(void);
+void dove_init_irq(void);
+void dove_setup_cpu_mbus(void);
+void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
+void dove_sata_init(struct mv_sata_platform_data *sata_data);
+void dove_pcie_init(int init_port0, int init_port1);
+void dove_ehci0_init(void);
+void dove_ehci1_init(void);
+void dove_uart0_init(void);
+void dove_uart1_init(void);
+void dove_uart2_init(void);
+void dove_uart3_init(void);
+void dove_spi0_init(void);
+void dove_spi1_init(void);
+void dove_i2c_init(void);
+#endif
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
new file mode 100644
index 000000000000..f2971b745224
--- /dev/null
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -0,0 +1,102 @@
+/*
+ * arch/arm/mach-dove/dove-db-setup.c
+ *
+ * Marvell DB-MV88AP510-BP Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/timer.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/i2c.h>
+#include <linux/pci.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <linux/spi/flash.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/dove.h>
+#include "common.h"
+static struct mv643xx_eth_platform_data dove_db_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR_DEFAULT,
+};
+static struct mv_sata_platform_data dove_db_sata_data = {
+        .n_ports        = 1,
+};
+/*****************************************************************************
+ * SPI Devices:
+ *      SPI0: 4M Flash ST-M25P32-VMF6P
+ ****************************************************************************/
+static const struct flash_platform_data dove_db_spi_flash_data = {
+        .type           = "m25p64",
+};
+static struct spi_board_info __initdata dove_db_spi_flash_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &dove_db_spi_flash_data,
+                .irq            = -1,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+/*****************************************************************************
+ * PCI
+ ****************************************************************************/
+static int __init dove_db_pci_init(void)
+{
+        if (machine_is_dove_db())
+                dove_pcie_init(1, 1);
+        return 0;
+}
+subsys_initcall(dove_db_pci_init);
+/*****************************************************************************
+ * Board Init
+ ****************************************************************************/
+static void __init dove_db_init(void)
+{
+        /*
+         * Basic Dove setup. Needs to be called early.
+         */
+        dove_init();
+        dove_ge00_init(&dove_db_ge00_data);
+        dove_ehci0_init();
+        dove_ehci1_init();
+        dove_sata_init(&dove_db_sata_data);
+        dove_spi0_init();
+        dove_spi1_init();
+        dove_uart0_init();
+        dove_uart1_init();
+        dove_i2c_init();
+        spi_register_board_info(dove_db_spi_flash_info,
+                                ARRAY_SIZE(dove_db_spi_flash_info));
+}
+MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
+        .phys_io        = DOVE_SB_REGS_PHYS_BASE,
+        .io_pg_offst    = ((DOVE_SB_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = dove_db_init,
+        .map_io         = dove_map_io,
+        .init_irq       = dove_init_irq,
+        .timer          = &dove_timer,
+MACHINE_END
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
new file mode 100644
index 000000000000..214a4c31f069
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -0,0 +1,58 @@
+/*
+ * arch/arm/mach-dove/include/mach/bridge-regs.h
+ *
+ * Mbus-L to Mbus Bridge Registers
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_BRIDGE_REGS_H
+#define __ASM_ARCH_BRIDGE_REGS_H
+#include <mach/dove.h>
+#define CPU_CONFIG              (BRIDGE_VIRT_BASE | 0x0000)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define  CPU_CTRL_PCIE0_LINK    0x00000001
+#define  CPU_RESET              0x00000002
+#define  CPU_CTRL_PCIE1_LINK    0x00000008
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define  SOFT_RESET_OUT_EN      0x00000004
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define  SOFT_RESET             0x00000001
+#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
+#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
+#define  BRIDGE_INT_TIMER0      0x0002
+#define  BRIDGE_INT_TIMER1      0x0004
+#define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_CAUSE_LOW_OFF       0x0000
+#define IRQ_MASK_LOW_OFF        0x0004
+#define FIQ_MASK_LOW_OFF        0x0008
+#define ENDPOINT_MASK_LOW_OFF   0x000c
+#define IRQ_CAUSE_HIGH_OFF      0x0010
+#define IRQ_MASK_HIGH_OFF       0x0014
+#define FIQ_MASK_HIGH_OFF       0x0018
+#define ENDPOINT_MASK_HIGH_OFF  0x001c
+#define PCIE_INTERRUPT_MASK_OFF 0x0020
+#define IRQ_MASK_LOW            (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)
+#define FIQ_MASK_LOW            (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF)
+#define ENDPOINT_MASK_LOW       (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF)
+#define IRQ_MASK_HIGH           (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)
+#define FIQ_MASK_HIGH           (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF)
+#define ENDPOINT_MASK_HIGH      (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
+#define PCIE_INTERRUPT_MASK     (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
+#define POWER_MANAGEMENT        (BRIDGE_VIRT_BASE | 0x011c)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
+#endif
diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S
new file mode 100644
index 000000000000..9b89ec7d3040
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/debug-macro.S
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-dove/include/mach/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <mach/bridge-regs.h>
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =DOVE_SB_REGS_PHYS_BASE
+        ldrne   \rx, =DOVE_SB_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
new file mode 100644
index 000000000000..f6a08397f046
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -0,0 +1,180 @@
+/*
+ * arch/arm/mach-dove/include/mach/dove.h
+ *
+ * Generic definitions for Marvell Dove 88AP510 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_DOVE_H
+#define __ASM_ARCH_DOVE_H
+#include <mach/vmalloc.h>
+/*
+ * Marvell Dove address maps.
+ *
+ * phys         virt            size
+ * c8000000     fdb00000        1M      Cryptographic SRAM
+ * e0000000     @runtime        128M    PCIe-0 Memory space
+ * e8000000     @runtime        128M    PCIe-1 Memory space
+ * f1000000     fde00000        8M      on-chip south-bridge registers
+ * f1800000     fe600000        8M      on-chip north-bridge registers
+ * f2000000     fee00000        1M      PCIe-0 I/O space
+ * f2100000     fef00000        1M      PCIe-1 I/O space
+ */
+#define DOVE_CESA_PHYS_BASE             0xc8000000
+#define DOVE_CESA_VIRT_BASE             0xfdb00000
+#define DOVE_CESA_SIZE                  SZ_1M
+#define DOVE_PCIE0_MEM_PHYS_BASE        0xe0000000
+#define DOVE_PCIE0_MEM_SIZE             SZ_128M
+#define DOVE_PCIE1_MEM_PHYS_BASE        0xe8000000
+#define DOVE_PCIE1_MEM_SIZE             SZ_128M
+#define DOVE_BOOTROM_PHYS_BASE          0xf8000000
+#define DOVE_BOOTROM_SIZE               SZ_128M
+#define DOVE_SCRATCHPAD_PHYS_BASE       0xf0000000
+#define DOVE_SCRATCHPAD_VIRT_BASE       0xfdd00000
+#define DOVE_SCRATCHPAD_SIZE            SZ_1M
+#define DOVE_SB_REGS_PHYS_BASE          0xf1000000
+#define DOVE_SB_REGS_VIRT_BASE          0xfde00000
+#define DOVE_SB_REGS_SIZE               SZ_8M
+#define DOVE_NB_REGS_PHYS_BASE          0xf1800000
+#define DOVE_NB_REGS_VIRT_BASE          0xfe600000
+#define DOVE_NB_REGS_SIZE               SZ_8M
+#define DOVE_PCIE0_IO_PHYS_BASE         0xf2000000
+#define DOVE_PCIE0_IO_VIRT_BASE         0xfee00000
+#define DOVE_PCIE0_IO_BUS_BASE          0x00000000
+#define DOVE_PCIE0_IO_SIZE              SZ_1M
+#define DOVE_PCIE1_IO_PHYS_BASE         0xf2100000
+#define DOVE_PCIE1_IO_VIRT_BASE         0xfef00000
+#define DOVE_PCIE1_IO_BUS_BASE          0x00100000
+#define DOVE_PCIE1_IO_SIZE              SZ_1M
+/*
+ * Dove Core Registers Map
+ */
+/* SPI, I2C, UART */
+#define DOVE_I2C_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x11000)
+#define DOVE_UART0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12000)
+#define DOVE_UART0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12000)
+#define DOVE_UART1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12100)
+#define DOVE_UART1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12100)
+#define DOVE_UART2_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12200)
+#define DOVE_UART2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12200)
+#define DOVE_UART3_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12300)
+#define DOVE_UART3_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12300)
+#define DOVE_SPI0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x10600)
+#define DOVE_SPI1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x14600)
+/* North-South Bridge */
+#define BRIDGE_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x20000)
+/* Cryptographic Engine */
+#define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x30000)
+/* PCIe 0 */
+#define DOVE_PCIE0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x40000)
+/* USB */
+#define DOVE_USB0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x50000)
+#define DOVE_USB1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x51000)
+/* XOR 0 Engine */
+#define DOVE_XOR0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60800)
+#define DOVE_XOR0_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60800)
+#define DOVE_XOR0_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60A00)
+#define DOVE_XOR0_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60A00)
+/* XOR 1 Engine */
+#define DOVE_XOR1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60900)
+#define DOVE_XOR1_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60900)
+#define DOVE_XOR1_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60B00)
+#define DOVE_XOR1_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60B00)
+/* Gigabit Ethernet */
+#define DOVE_GE00_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x70000)
+/* PCIe 1 */
+#define DOVE_PCIE1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x80000)
+/* CAFE */
+#define DOVE_SDIO0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x92000)
+#define DOVE_SDIO1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x90000)
+#define DOVE_CAM_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x94000)
+#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000)
+/* SATA */
+#define DOVE_SATA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xa0000)
+/* I2S/SPDIF */
+#define DOVE_AUD0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb0000)
+#define DOVE_AUD1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb4000)
+/* NAND Flash Controller */
+#define DOVE_NFC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xc0000)
+/* MPP, GPIO, Reset Sampling */
+#define DOVE_MPP_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
+#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
+#define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE | 0x014)
+#define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE | 0x018)
+#define DOVE_GPIO_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
+#define  DOVE_AU1_SPDIFO_GPIO_EN        (1 << 1)
+#define  DOVE_NAND_GPIO_EN              (1 << 0)
+#define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_VIRT_BASE + 0x40)
+/* Power Management */
+#define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
+/* Real Time Clock */
+#define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
+/* AC97 */
+#define DOVE_AC97_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe0000)
+#define DOVE_AC97_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe0000)
+/* Peripheral DMA */
+#define DOVE_PDMA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe4000)
+#define DOVE_PDMA_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe4000)
+#define DOVE_GLOBAL_CONFIG_1    (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define  DOVE_TWSI_ENABLE_OPTION1       (1 << 7)
+#define DOVE_GLOBAL_CONFIG_2    (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define  DOVE_TWSI_ENABLE_OPTION2       (1 << 20)
+#define  DOVE_TWSI_ENABLE_OPTION3       (1 << 21)
+#define  DOVE_TWSI_OPTION3_GPIO         (1 << 22)
+#define DOVE_SSP_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xec000)
+#define DOVE_SSP_CTRL_STATUS_1  (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
+#define  DOVE_SSP_ON_AU1                (1 << 0)
+#define  DOVE_SSP_CLOCK_ENABLE          (1 << 1)
+#define  DOVE_SSP_BPB_CLOCK_SRC_SSP     (1 << 11)
+/* Memory Controller */
+#define DOVE_MC_VIRT_BASE       (DOVE_NB_REGS_VIRT_BASE | 0x00000)
+/* LCD Controller */
+#define DOVE_LCD_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x10000)
+#define DOVE_LCD1_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x20000)
+#define DOVE_LCD2_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x10000)
+#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000)
+/* Graphic Engine */
+#define DOVE_GPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x40000)
+/* Video Engine */
+#define DOVE_VPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x400000)
+#endif
diff --git a/arch/arm/mach-dove/include/mach/entry-macro.S b/arch/arm/mach-dove/include/mach/entry-macro.S
new file mode 100644
index 000000000000..e84c78c2a8b7
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-dove/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Marvell Dove platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/bridge-regs.h>
+        .macro  disable_fiq
+        .endm
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IRQ_VIRT_BASE
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ check low interrupts
+        ldr     \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
+        ldr     \tmp, [\base, #IRQ_MASK_LOW_OFF]
+        mov     \irqnr, #31
+        ands    \irqstat, \irqstat, \tmp
+        @ if no low interrupts set, check high interrupts
+        ldreq   \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
+        ldreq   \tmp, [\base, #IRQ_MASK_HIGH_OFF]
+        moveq   \irqnr, #63
+        andeqs  \irqstat, \irqstat, \tmp
+        @ find first active interrupt source
+        clzne   \irqstat, \irqstat
+        subne   \irqnr, \irqnr, \irqstat
+        .endm
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h
new file mode 100644
index 000000000000..0ee70ff39e11
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/gpio.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-dove/include/mach/gpio.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+#include <asm/errno.h>
+#include <mach/irqs.h>
+#include <plat/gpio.h>
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
+#define GPIO_MAX        64
+#define GPIO_BASE_LO            (DOVE_GPIO_VIRT_BASE + 0x00)
+#define GPIO_BASE_HI            (DOVE_GPIO_VIRT_BASE + 0x20)
+#define GPIO_BASE(pin)          ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI)
+#define GPIO_OUT(pin)           (GPIO_BASE(pin) + 0x00)
+#define GPIO_IO_CONF(pin)       (GPIO_BASE(pin) + 0x04)
+#define GPIO_BLINK_EN(pin)      (GPIO_BASE(pin) + 0x08)
+#define GPIO_IN_POL(pin)        (GPIO_BASE(pin) + 0x0c)
+#define GPIO_DATA_IN(pin)       (GPIO_BASE(pin) + 0x10)
+#define GPIO_EDGE_CAUSE(pin)    (GPIO_BASE(pin) + 0x14)
+#define GPIO_EDGE_MASK(pin)     (GPIO_BASE(pin) + 0x18)
+#define GPIO_LEVEL_MASK(pin)    (GPIO_BASE(pin) + 0x1c)
+static inline int gpio_to_irq(int pin)
+{
+        if (pin < NR_GPIO_IRQS)
+                return pin + IRQ_DOVE_GPIO_START;
+        return -EINVAL;
+}
+static inline int irq_to_gpio(int irq)
+{
+        if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS)
+                return irq - IRQ_DOVE_GPIO_START;
+        return -EINVAL;
+}
+#endif
diff --git a/arch/arm/mach-dove/include/mach/hardware.h b/arch/arm/mach-dove/include/mach/hardware.h
new file mode 100644
index 000000000000..32b0826e7873
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/hardware.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-dove/include/mach/hardware.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include "dove.h"
+#define pcibios_assign_all_busses()     1
+#define PCIBIOS_MIN_IO                  0x1000
+#define PCIBIOS_MIN_MEM                 0x01000000
+#define PCIMEM_BASE                     DOVE_PCIE0_MEM_PHYS_BASE
+/* Macros below are required for compatibility with PXA AC'97 driver.   */
+#define __REG(x)        (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \
+                                DOVE_SB_REGS_VIRT_BASE)))
+#define __PREG(x)       (((u32)&(x)) - DOVE_SB_REGS_VIRT_BASE + \
+                DOVE_SB_REGS_PHYS_BASE)
+#endif
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
new file mode 100644
index 000000000000..3b3e4721ce2e
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/io.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-dove/include/mach/io.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+#include "dove.h"
+#define IO_SPACE_LIMIT          0xffffffff
+#define __io(a)  ((void __iomem *)(((a) - DOVE_PCIE0_IO_PHYS_BASE) +\
+                                   DOVE_PCIE0_IO_VIRT_BASE))
+#define __mem_pci(a)            (a)
+#endif
diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h
new file mode 100644
index 000000000000..46681466f92b
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/irqs.h
@@ -0,0 +1,101 @@
+/*
+ * arch/arm/mach-dove/include/mach/irqs.h
+ *
+ * IRQ definitions for Marvell Dove 88AP510 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+/*
+ * Dove Low Interrupt Controller
+ */
+#define IRQ_DOVE_BRIDGE         0
+#define IRQ_DOVE_H2C            1
+#define IRQ_DOVE_C2H            2
+#define IRQ_DOVE_NAND           3
+#define IRQ_DOVE_PDMA           4
+#define IRQ_DOVE_SPI1           5
+#define IRQ_DOVE_SPI0           6
+#define IRQ_DOVE_UART_0         7
+#define IRQ_DOVE_UART_1         8
+#define IRQ_DOVE_UART_2         9
+#define IRQ_DOVE_UART_3         10
+#define IRQ_DOVE_I2C            11
+#define IRQ_DOVE_GPIO_0_7       12
+#define IRQ_DOVE_GPIO_8_15      13
+#define IRQ_DOVE_GPIO_16_23     14
+#define IRQ_DOVE_PCIE0_ERR      15
+#define IRQ_DOVE_PCIE0          16
+#define IRQ_DOVE_PCIE1_ERR      17
+#define IRQ_DOVE_PCIE1          18
+#define IRQ_DOVE_I2S0           19
+#define IRQ_DOVE_I2S0_ERR       20
+#define IRQ_DOVE_I2S1           21
+#define IRQ_DOVE_I2S1_ERR       22
+#define IRQ_DOVE_USB_ERR        23
+#define IRQ_DOVE_USB0           24
+#define IRQ_DOVE_USB1           25
+#define IRQ_DOVE_GE00_RX        26
+#define IRQ_DOVE_GE00_TX        27
+#define IRQ_DOVE_GE00_MISC      28
+#define IRQ_DOVE_GE00_SUM       29
+#define IRQ_DOVE_GE00_ERR       30
+#define IRQ_DOVE_CRYPTO         31
+/*
+ * Dove High Interrupt Controller
+ */
+#define IRQ_DOVE_AC97           32
+#define IRQ_DOVE_PMU            33
+#define IRQ_DOVE_CAM            34
+#define IRQ_DOVE_SDIO0          35
+#define IRQ_DOVE_SDIO1          36
+#define IRQ_DOVE_SDIO0_WAKEUP   37
+#define IRQ_DOVE_SDIO1_WAKEUP   38
+#define IRQ_DOVE_XOR_00         39
+#define IRQ_DOVE_XOR_01         40
+#define IRQ_DOVE_XOR0_ERR       41
+#define IRQ_DOVE_XOR_10         42
+#define IRQ_DOVE_XOR_11         43
+#define IRQ_DOVE_XOR1_ERR       44
+#define IRQ_DOVE_LCD_DCON       45
+#define IRQ_DOVE_LCD1           46
+#define IRQ_DOVE_LCD0           47
+#define IRQ_DOVE_GPU            48
+#define IRQ_DOVE_PERFORM_MNTR   49
+#define IRQ_DOVE_VPRO_DMA1      51
+#define IRQ_DOVE_SSP_TIMER      54
+#define IRQ_DOVE_SSP            55
+#define IRQ_DOVE_MC_L2_ERR      56
+#define IRQ_DOVE_CRYPTO_ERR     59
+#define IRQ_DOVE_GPIO_24_31     60
+#define IRQ_DOVE_HIGH_GPIO      61
+#define IRQ_DOVE_SATA           62
+/*
+ * DOVE General Purpose Pins
+ */
+#define IRQ_DOVE_GPIO_START     64
+#define NR_GPIO_IRQS            64
+/*
+ * PMU interrupts
+ */
+#define IRQ_DOVE_PMU_START      (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS)
+#define NR_PMU_IRQS             7
+#define IRQ_DOVE_RTC            (IRQ_DOVE_PMU_START + 5)
+#define NR_IRQS                 (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
+/* Required for compatability with PXA AC97 driver.     */
+#define IRQ_AC97                IRQ_DOVE_AC97
+/* Required for compatability with PXA DMA driver.      */
+#define IRQ_DMA                 IRQ_DOVE_PDMA
+/* Required for compatability with PXA NAND driver      */
+#define IRQ_NAND                IRQ_DOVE_NAND
+#endif
diff --git a/arch/arm/mach-dove/include/mach/memory.h b/arch/arm/mach-dove/include/mach/memory.h
new file mode 100644
index 000000000000..d66872074946
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/memory.h
@@ -0,0 +1,10 @@
+/*
+ * arch/arm/mach-dove/include/mach/memory.h
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+#define PHYS_OFFSET             UL(0x00000000)
+#endif
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
new file mode 100644
index 000000000000..3ad9f946a9e8
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -0,0 +1,54 @@
+/*
+ * arch/arm/mach-dove/include/mach/pm.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_PM_H
+#define __ASM_ARCH_PM_H
+#include <asm/errno.h>
+#include <mach/irqs.h>
+#define CLOCK_GATING_CONTROL    (DOVE_PMU_VIRT_BASE + 0x38)
+#define  CLOCK_GATING_USB0_MASK         (1 << 0)
+#define  CLOCK_GATING_USB1_MASK         (1 << 1)
+#define  CLOCK_GATING_GBE_MASK          (1 << 2)
+#define  CLOCK_GATING_SATA_MASK         (1 << 3)
+#define  CLOCK_GATING_PCIE0_MASK        (1 << 4)
+#define  CLOCK_GATING_PCIE1_MASK        (1 << 5)
+#define  CLOCK_GATING_SDIO0_MASK        (1 << 8)
+#define  CLOCK_GATING_SDIO1_MASK        (1 << 9)
+#define  CLOCK_GATING_NAND_MASK         (1 << 10)
+#define  CLOCK_GATING_CAMERA_MASK       (1 << 11)
+#define  CLOCK_GATING_I2S0_MASK         (1 << 12)
+#define  CLOCK_GATING_I2S1_MASK         (1 << 13)
+#define  CLOCK_GATING_CRYPTO_MASK       (1 << 15)
+#define  CLOCK_GATING_AC97_MASK         (1 << 21)
+#define  CLOCK_GATING_PDMA_MASK         (1 << 22)
+#define  CLOCK_GATING_XOR0_MASK         (1 << 23)
+#define  CLOCK_GATING_XOR1_MASK         (1 << 24)
+#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << 30)
+#define PMU_INTERRUPT_CAUSE     (DOVE_PMU_VIRT_BASE + 0x50)
+#define PMU_INTERRUPT_MASK      (DOVE_PMU_VIRT_BASE + 0x54)
+static inline int pmu_to_irq(int pin)
+{
+        if (pin < NR_PMU_IRQS)
+                return pin + IRQ_DOVE_PMU_START;
+        return -EINVAL;
+}
+static inline int irq_to_pmu(int irq)
+{
+        if (IRQ_DOVE_PMU_START < irq && irq < NR_IRQS)
+                return irq - IRQ_DOVE_PMU_START;
+        return -EINVAL;
+}
+#endif
diff --git a/arch/arm/mach-dove/include/mach/system.h b/arch/arm/mach-dove/include/mach/system.h
new file mode 100644
index 000000000000..356afda56853
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/system.h
@@ -0,0 +1,36 @@
+/*
+ * arch/arm/mach-dove/include/mach/system.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <mach/bridge-regs.h>
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode, const char *cmd)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+        while (1)
+                ;
+}
+#endif
diff --git a/arch/arm/mach-dove/include/mach/timex.h b/arch/arm/mach-dove/include/mach/timex.h
new file mode 100644
index 000000000000..251d538541db
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/timex.h
@@ -0,0 +1,9 @@
+/*
+ * arch/arm/mach-dove/include/mach/timex.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h
new file mode 100644
index 000000000000..2c5cdd7a3eed
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/uncompress.h
@@ -0,0 +1,37 @@
+/*
+ * arch/arm/mach-dove/include/mach/uncompress.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/dove.h>
+#define UART_THR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x0))
+#define UART_LSR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x14))
+#define LSR_THRE        0x20
+static void putc(const char c)
+{
+        int i;
+        for (i = 0; i < 0x1000; i++) {
+                /* Transmit fifo not full? */
+                if (*UART_LSR & LSR_THRE)
+                        break;
+        }
+        *UART_THR = c;
+}
+static void flush(void)
+{
+}
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-dove/include/mach/vmalloc.h b/arch/arm/mach-dove/include/mach/vmalloc.h
new file mode 100644
index 000000000000..8b2c974755c6
--- /dev/null
+++ b/arch/arm/mach-dove/include/mach/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * arch/arm/mach-dove/include/mach/vmalloc.h
+ */
+#define VMALLOC_END     0xfd800000
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
new file mode 100644
index 000000000000..61bfcb3b08c2
--- /dev/null
+++ b/arch/arm/mach-dove/irq.c
@@ -0,0 +1,133 @@
+/*
+ * arch/arm/mach-dove/irq.c
+ *
+ * Dove IRQ handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <asm/mach/arch.h>
+#include <plat/irq.h>
+#include <asm/mach/irq.h>
+#include <mach/pm.h>
+#include <mach/bridge-regs.h>
+#include "common.h"
+static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        int irqoff;
+        BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO);
+        irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 :
+                3 + irq - IRQ_DOVE_GPIO_24_31;
+        orion_gpio_irq_handler(irqoff << 3);
+        if (irq == IRQ_DOVE_HIGH_GPIO) {
+                orion_gpio_irq_handler(40);
+                orion_gpio_irq_handler(48);
+                orion_gpio_irq_handler(56);
+        }
+}
+static void pmu_irq_mask(unsigned int irq)
+{
+        int pin = irq_to_pmu(irq);
+        u32 u;
+        u = readl(PMU_INTERRUPT_MASK);
+        u &= ~(1 << (pin & 31));
+        writel(u, PMU_INTERRUPT_MASK);
+}
+static void pmu_irq_unmask(unsigned int irq)
+{
+        int pin = irq_to_pmu(irq);
+        u32 u;
+        u = readl(PMU_INTERRUPT_MASK);
+        u |= 1 << (pin & 31);
+        writel(u, PMU_INTERRUPT_MASK);
+}
+static void pmu_irq_ack(unsigned int irq)
+{
+        int pin = irq_to_pmu(irq);
+        u32 u;
+        u = ~(1 << (pin & 31));
+        writel(u, PMU_INTERRUPT_CAUSE);
+}
+static struct irq_chip pmu_irq_chip = {
+        .name           = "pmu_irq",
+        .mask           = pmu_irq_mask,
+        .unmask         = pmu_irq_unmask,
+        .ack            = pmu_irq_ack,
+};
+static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
+        cause &= readl(PMU_INTERRUPT_MASK);
+        if (cause == 0) {
+                do_bad_IRQ(irq, desc);
+                return;
+        }
+        for (irq = 0; irq < NR_PMU_IRQS; irq++) {
+                if (!(cause & (1 << irq)))
+                        continue;
+                irq = pmu_to_irq(irq);
+                desc = irq_desc + irq;
+                desc_handle_irq(irq, desc);
+        }
+}
+void __init dove_init_irq(void)
+{
+        int i;
+        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
+        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+        /*
+         * Mask and clear GPIO IRQ interrupts.
+         */
+        writel(0, GPIO_LEVEL_MASK(0));
+        writel(0, GPIO_EDGE_MASK(0));
+        writel(0, GPIO_EDGE_CAUSE(0));
+        /*
+         * Mask and clear PMU interrupts
+         */
+        writel(0, PMU_INTERRUPT_MASK);
+        writel(0, PMU_INTERRUPT_CAUSE);
+        for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) {
+                set_irq_chip(i, &orion_gpio_irq_chip);
+                set_irq_handler(i, handle_level_irq);
+                irq_desc[i].status |= IRQ_LEVEL;
+                set_irq_flags(i, IRQF_VALID);
+        }
+        set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
+        for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
+                set_irq_chip(i, &pmu_irq_chip);
+                set_irq_handler(i, handle_level_irq);
+                irq_desc[i].status |= IRQ_LEVEL;
+                set_irq_flags(i, IRQF_VALID);
+        }
+        set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
+}
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
new file mode 100644
index 000000000000..502d1ca2f4b7
--- /dev/null
+++ b/arch/arm/mach-dove/pcie.c
@@ -0,0 +1,238 @@
+/*
+ * arch/arm/mach-dove/pcie.c
+ *
+ * PCIe functions for Marvell Dove 88AP510 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/mbus.h>
+#include <asm/mach/pci.h>
+#include <asm/mach/arch.h>
+#include <asm/setup.h>
+#include <asm/delay.h>
+#include <plat/pcie.h>
+#include <mach/irqs.h>
+#include <mach/bridge-regs.h>
+#include "common.h"
+struct pcie_port {
+        u8                      index;
+        u8                      root_bus_nr;
+        void __iomem            *base;
+        spinlock_t              conf_lock;
+        char                    io_space_name[16];
+        char                    mem_space_name[16];
+        struct resource         res[2];
+};
+static struct pcie_port pcie_port[2];
+static int num_pcie_ports;
+static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+        struct pcie_port *pp;
+        if (nr >= num_pcie_ports)
+                return 0;
+        pp = &pcie_port[nr];
+        pp->root_bus_nr = sys->busnr;
+        /*
+         * Generic PCIe unit setup.
+         */
+        orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
+        orion_pcie_setup(pp->base, &dove_mbus_dram_info);
+        /*
+         * IORESOURCE_IO
+         */
+        snprintf(pp->io_space_name, sizeof(pp->io_space_name),
+                 "PCIe %d I/O", pp->index);
+        pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
+        pp->res[0].name = pp->io_space_name;
+        if (pp->index == 0) {
+                pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
+                pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
+        } else {
+                pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
+                pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
+        }
+        pp->res[0].flags = IORESOURCE_IO;
+        if (request_resource(&ioport_resource, &pp->res[0]))
+                panic("Request PCIe IO resource failed\n");
+        sys->resource[0] = &pp->res[0];
+        /*
+         * IORESOURCE_MEM
+         */
+        snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
+                 "PCIe %d MEM", pp->index);
+        pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
+        pp->res[1].name = pp->mem_space_name;
+        if (pp->index == 0) {
+                pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
+                pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
+        } else {
+                pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
+                pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
+        }
+        pp->res[1].flags = IORESOURCE_MEM;
+        if (request_resource(&iomem_resource, &pp->res[1]))
+                panic("Request PCIe Memory resource failed\n");
+        sys->resource[1] = &pp->res[1];
+        sys->resource[2] = NULL;
+        return 1;
+}
+static struct pcie_port *bus_to_port(int bus)
+{
+        int i;
+        for (i = num_pcie_ports - 1; i >= 0; i--) {
+                int rbus = pcie_port[i].root_bus_nr;
+                if (rbus != -1 && rbus <= bus)
+                        break;
+        }
+        return i >= 0 ? pcie_port + i : NULL;
+}
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
+{
+        /*
+         * Don't go out when trying to access nonexisting devices
+         * on the local bus.
+         */
+        if (bus == pp->root_bus_nr && dev > 1)
+                return 0;
+        return 1;
+}
+static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+                        int size, u32 *val)
+{
+        struct pcie_port *pp = bus_to_port(bus->number);
+        unsigned long flags;
+        int ret;
+        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+        spin_lock_irqsave(&pp->conf_lock, flags);
+        ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&pp->conf_lock, flags);
+        return ret;
+}
+static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+                        int where, int size, u32 val)
+{
+        struct pcie_port *pp = bus_to_port(bus->number);
+        unsigned long flags;
+        int ret;
+        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        spin_lock_irqsave(&pp->conf_lock, flags);
+        ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&pp->conf_lock, flags);
+        return ret;
+}
+static struct pci_ops pcie_ops = {
+        .read = pcie_rd_conf,
+        .write = pcie_wr_conf,
+};
+static void __devinit rc_pci_fixup(struct pci_dev *dev)
+{
+        /*
+         * Prevent enumeration of root complex.
+         */
+        if (dev->bus->parent == NULL && dev->devfn == 0) {
+                int i;
+                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+                        dev->resource[i].start = 0;
+                        dev->resource[i].end   = 0;
+                        dev->resource[i].flags = 0;
+                }
+        }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
+static struct pci_bus __init *
+dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        struct pci_bus *bus;
+        if (nr < num_pcie_ports) {
+                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+        } else {
+                bus = NULL;
+                BUG();
+        }
+        return bus;
+}
+static int __init dove_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct pcie_port *pp = bus_to_port(dev->bus->number);
+        return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
+}
+static struct hw_pci dove_pci __initdata = {
+        .nr_controllers = 2,
+        .swizzle        = pci_std_swizzle,
+        .setup          = dove_pcie_setup,
+        .scan           = dove_pcie_scan_bus,
+        .map_irq        = dove_pcie_map_irq,
+};
+static void __init add_pcie_port(int index, unsigned long base)
+{
+        printk(KERN_INFO "Dove PCIe port %d: ", index);
+        if (orion_pcie_link_up((void __iomem *)base)) {
+                struct pcie_port *pp = &pcie_port[num_pcie_ports++];
+                printk(KERN_INFO "link up\n");
+                pp->index = index;
+                pp->root_bus_nr = -1;
+                pp->base = (void __iomem *)base;
+                spin_lock_init(&pp->conf_lock);
+                memset(pp->res, 0, sizeof(pp->res));
+        } else {
+                printk(KERN_INFO "link down, ignoring\n");
+        }
+}
+void __init dove_pcie_init(int init_port0, int init_port1)
+{
+        if (init_port0)
+                add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
+        if (init_port1)
+                add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
+        pci_common_init(&dove_pci);
+}
diff --git a/arch/arm/mach-iop13xx/include/mach/time.h b/arch/arm/mach-iop13xx/include/mach/time.h
index d6d52527589d..f1c00d6d560b 100644
--- a/arch/arm/mach-iop13xx/include/mach/time.h
+++ b/arch/arm/mach-iop13xx/include/mach/time.h
@@ -20,7 +20,6 @@
 #define IOP13XX_CORE_FREQ_1200          (5 << 16)
 void iop_init_time(unsigned long tickrate);
-unsigned long iop_gettimeoffset(void);
 static inline unsigned long iop13xx_core_freq(void)
 {
@@ -66,6 +65,13 @@ static inline unsigned long iop13xx_xsi_bus_ratio(void)
        return 2;
 }
+static inline u32 read_tmr0(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val));
+        return val;
+}
 static inline void write_tmr0(u32 val)
 {
        asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
@@ -83,6 +89,11 @@ static inline u32 read_tcr0(void)
        return val;
 }
+static inline void write_tcr0(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val));
+}
 static inline u32 read_tcr1(void)
 {
        u32 val;
@@ -90,6 +101,11 @@ static inline u32 read_tcr1(void)
        return val;
 }
+static inline void write_tcr1(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val));
+}
 static inline void write_trr0(u32 val)
 {
        asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index 5051c03d437c..f91f3154577d 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -87,7 +87,6 @@ static void __init iq81340mc_timer_init(void)
 static struct sys_timer iq81340mc_timer = {
       .init       = iq81340mc_timer_init,
-       .offset     = iop_gettimeoffset,
 };
 MACHINE_START(IQ81340MC, "Intel IQ81340MC")
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index bc443073a8e3..ddb7a3435de9 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -89,7 +89,6 @@ static void __init iq81340sc_timer_init(void)
 static struct sys_timer iq81340sc_timer = {
       .init       = iq81340sc_timer_init,
-       .offset     = iop_gettimeoffset,
 };
 MACHINE_START(IQ81340SC, "Intel IQ81340SC")
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
index 3ad4696ade42..2bef9b6e1cc9 100644
--- a/arch/arm/mach-iop32x/em7210.c
+++ b/arch/arm/mach-iop32x/em7210.c
@@ -42,7 +42,6 @@ static void __init em7210_timer_init(void)
 static struct sys_timer em7210_timer = {
        .init           = em7210_timer_init,
-        .offset         = iop_gettimeoffset,
 };
 /*
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index a9c2dfdb2507..93370a46b620 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -47,7 +47,6 @@ static void __init glantank_timer_init(void)
 static struct sys_timer glantank_timer = {
        .init           = glantank_timer_init,
-        .offset         = iop_gettimeoffset,
 };
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index dd1cd9904518..a7a08dda7f33 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -78,7 +78,6 @@ static void __init iq31244_timer_init(void)
 static struct sys_timer iq31244_timer = {
        .init           = iq31244_timer_init,
-        .offset         = iop_gettimeoffset,
 };
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index fbe27798759d..0200f80c1e17 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -46,7 +46,6 @@ static void __init iq80321_timer_init(void)
 static struct sys_timer iq80321_timer = {
        .init           = iq80321_timer_init,
-        .offset         = iop_gettimeoffset,
 };
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index d2e427899729..2a5c637639bb 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -53,7 +53,6 @@ static void __init n2100_timer_init(void)
 static struct sys_timer n2100_timer = {
        .init           = n2100_timer_init,
-        .offset         = iop_gettimeoffset,
 };
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index d51e10cddf20..394e95a30b75 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -48,7 +48,6 @@ static void __init iq80331_timer_init(void)
 static struct sys_timer iq80331_timer = {
        .init           = iq80331_timer_init,
-        .offset         = iop_gettimeoffset,
 };
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 92fb44cdbcad..a40badf126c2 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -48,7 +48,6 @@ static void __init iq80332_timer_init(void)
 static struct sys_timer iq80332_timer = {
        .init           = iq80332_timer_init,
-        .offset         = iop_gettimeoffset,
 };
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 0aca451b216d..8bf09ae5b347 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -33,10 +33,18 @@ config MACH_SHEEVAPLUG
          Marvell SheevaPlug Reference Board.
 config MACH_TS219
-        bool "QNAP TS-119 and TS-219 Turbo NAS"
+        bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS"
        help
          Say 'Y' here if you want your kernel to support the
-          QNAP TS-119 and TS-219 Turbo NAS devices.
+          QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS
+          devices.
+config MACH_TS41X
+        bool "QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS"
+        help
+          Say 'Y' here if you want your kernel to support the
+          QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS
+          devices.
 config MACH_OPENRD_BASE
        bool "Marvell OpenRD Base Board"
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 80ab0ec90ee1..9f2f67b2b63d 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -5,7 +5,8 @@ obj-$(CONFIG_MACH_RD88F6192_NAS)	+= rd88f6192-nas-setup.o
 obj-$(CONFIG_MACH_RD88F6281)            += rd88f6281-setup.o
 obj-$(CONFIG_MACH_MV88F6281GTW_GE)      += mv88f6281gtw_ge-setup.o
 obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
-obj-$(CONFIG_MACH_TS219)                += ts219-setup.o
+obj-$(CONFIG_MACH_TS219)                += ts219-setup.o tsx1x-common.o
+obj-$(CONFIG_MACH_TS41X)                += ts41x-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_OPENRD_BASE)          += openrd_base-setup.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index ec1a64f263d2..2830f0fe80e0 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -1,6 +1,6 @@
 /*
 *
- * QNAP TS-119/TS-219 Turbo NAS Board Setup
+ * QNAP TS-11x/TS-21x Turbo NAS Board Setup
 *
 * Copyright (C) 2009  Martin Michlmayr <tbm@cyrius.com>
 * Copyright (C) 2008  Byron Bradley <byron.bbradley@gmail.com>
@@ -14,87 +14,17 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/orion_spi.h>
 #include <linux/i2c.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
-#include <linux/timex.h>
-#include <linux/serial_reg.h>
-#include <linux/pci.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include "common.h"
 #include "mpp.h"
+#include "tsx1x-common.h"
-/****************************************************************************
- * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the
- *     partitions on the device because we want to keep compatability with
- *     the QNAP firmware.
- * Layout as used by QNAP:
- *  0x00000000-0x00080000 : "U-Boot"
- *  0x00200000-0x00400000 : "Kernel"
- *  0x00400000-0x00d00000 : "RootFS"
- *  0x00d00000-0x01000000 : "RootFS2"
- *  0x00080000-0x000c0000 : "U-Boot Config"
- *  0x000c0000-0x00200000 : "NAS Config"
- *
- * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout
- * used by the QNAP TS-109/TS-209.
- *
- ***************************************************************************/
-static struct mtd_partition qnap_ts219_partitions[] = {
-        {
-                .name           = "U-Boot",
-                .size           = 0x00080000,
-                .offset         = 0,
-                .mask_flags     = MTD_WRITEABLE,
-        }, {
-                .name           = "Kernel",
-                .size           = 0x00200000,
-                .offset         = 0x00200000,
-        }, {
-                .name           = "RootFS1",
-                .size           = 0x00900000,
-                .offset         = 0x00400000,
-        }, {
-                .name           = "RootFS2",
-                .size           = 0x00300000,
-                .offset         = 0x00d00000,
-        }, {
-                .name           = "U-Boot Config",
-                .size           = 0x00040000,
-                .offset         = 0x00080000,
-        }, {
-                .name           = "NAS Config",
-                .size           = 0x00140000,
-                .offset         = 0x000c0000,
-        },
-};
-static const struct flash_platform_data qnap_ts219_flash = {
-        .type           = "m25p128",
-        .name           = "spi_flash",
-        .parts          = qnap_ts219_partitions,
-        .nr_parts       = ARRAY_SIZE(qnap_ts219_partitions),
-};
-static struct spi_board_info __initdata qnap_ts219_spi_slave_info[] = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &qnap_ts219_flash,
-                .irq            = -1,
-                .max_speed_hz   = 20000000,
-                .bus_num        = 0,
-                .chip_select    = 0,
-        },
-};
 static struct i2c_board_info __initdata qnap_ts219_i2c_rtc = {
        I2C_BOARD_INFO("s35390a", 0x30),
@@ -152,36 +82,10 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
        MPP14_UART1_RXD,        /* PIC controller */
        MPP15_GPIO,             /* USB Copy button */
        MPP16_GPIO,             /* Reset button */
+        MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
        0
 };
-/*****************************************************************************
- * QNAP TS-x19 specific power off method via UART1-attached PIC
- ****************************************************************************/
-#define UART1_REG(x)    (UART1_VIRT_BASE + ((UART_##x) << 2))
-void qnap_ts219_power_off(void)
-{
-        /* 19200 baud divisor */
-        const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200));
-        pr_info("%s: triggering power-off...\n", __func__);
-        /* hijack UART1 and reset into sane state (19200,8n1) */
-        writel(0x83, UART1_REG(LCR));
-        writel(divisor & 0xff, UART1_REG(DLL));
-        writel((divisor >> 8) & 0xff, UART1_REG(DLM));
-        writel(0x03, UART1_REG(LCR));
-        writel(0x00, UART1_REG(IER));
-        writel(0x00, UART1_REG(FCR));
-        writel(0x00, UART1_REG(MCR));
-        /* send the power-off command 'A' to PIC */
-        writel('A', UART1_REG(TX));
-}
 static void __init qnap_ts219_init(void)
 {
        /*
@@ -192,9 +96,7 @@ static void __init qnap_ts219_init(void)
        kirkwood_uart0_init();
        kirkwood_uart1_init(); /* A PIC controller is connected here. */
-        spi_register_board_info(qnap_ts219_spi_slave_info,
+        qnap_tsx1x_register_flash();
-                                ARRAY_SIZE(qnap_ts219_spi_slave_info));
-        kirkwood_spi_init();
        kirkwood_i2c_init();
        i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1);
        kirkwood_ge00_init(&qnap_ts219_ge00_data);
@@ -202,7 +104,7 @@ static void __init qnap_ts219_init(void)
        kirkwood_ehci_init();
        platform_device_register(&qnap_ts219_button_device);
-        pm_power_off = qnap_ts219_power_off;
+        pm_power_off = qnap_tsx1x_power_off;
 }
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
new file mode 100644
index 000000000000..de49c2d9e74b
--- /dev/null
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -0,0 +1,154 @@
+/*
+ *
+ * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup
+ *
+ * Copyright (C) 2009  Martin Michlmayr <tbm@cyrius.com>
+ * Copyright (C) 2008  Byron Bradley <byron.bbradley@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+#include "tsx1x-common.h"
+static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
+        I2C_BOARD_INFO("s35390a", 0x30),
+};
+static struct mv643xx_eth_platform_data qnap_ts41x_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+static struct mv643xx_eth_platform_data qnap_ts41x_ge01_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+static struct mv_sata_platform_data qnap_ts41x_sata_data = {
+        .n_ports        = 2,
+};
+static struct gpio_keys_button qnap_ts41x_buttons[] = {
+        {
+                .code           = KEY_COPY,
+                .gpio           = 43,
+                .desc           = "USB Copy",
+                .active_low     = 1,
+        },
+        {
+                .code           = KEY_RESTART,
+                .gpio           = 37,
+                .desc           = "Reset",
+                .active_low     = 1,
+        },
+};
+static struct gpio_keys_platform_data qnap_ts41x_button_data = {
+        .buttons        = qnap_ts41x_buttons,
+        .nbuttons       = ARRAY_SIZE(qnap_ts41x_buttons),
+};
+static struct platform_device qnap_ts41x_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &qnap_ts41x_button_data,
+        }
+};
+static unsigned int qnap_ts41x_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP6_SYSRST_OUTn,
+        MPP7_PEX_RST_OUTn,
+        MPP8_TW_SDA,
+        MPP9_TW_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP13_UART1_TXD,        /* PIC controller */
+        MPP14_UART1_RXD,        /* PIC controller */
+        MPP15_SATA0_ACTn,
+        MPP16_SATA1_ACTn,
+        MPP20_GE1_0,
+        MPP21_GE1_1,
+        MPP22_GE1_2,
+        MPP23_GE1_3,
+        MPP24_GE1_4,
+        MPP25_GE1_5,
+        MPP26_GE1_6,
+        MPP27_GE1_7,
+        MPP30_GE1_10,
+        MPP31_GE1_11,
+        MPP32_GE1_12,
+        MPP33_GE1_13,
+        MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
+        MPP37_GPIO,             /* Reset button */
+        MPP43_GPIO,             /* USB Copy button */
+        MPP44_GPIO,             /* Board ID: 0: TS-419U, 1: TS-419 */
+        MPP45_GPIO,             /* JP1: 0: console, 1: LCD */
+        MPP46_GPIO,             /* External SATA HDD1 error indicator */
+        MPP47_GPIO,             /* External SATA HDD2 error indicator */
+        MPP48_GPIO,             /* External SATA HDD3 error indicator */
+        MPP49_GPIO,             /* External SATA HDD4 error indicator */
+        0
+};
+static void __init qnap_ts41x_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(qnap_ts41x_mpp_config);
+        kirkwood_uart0_init();
+        kirkwood_uart1_init(); /* A PIC controller is connected here. */
+        qnap_tsx1x_register_flash();
+        kirkwood_i2c_init();
+        i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1);
+        kirkwood_ge00_init(&qnap_ts41x_ge00_data);
+        kirkwood_ge01_init(&qnap_ts41x_ge01_data);
+        kirkwood_sata_init(&qnap_ts41x_sata_data);
+        kirkwood_ehci_init();
+        platform_device_register(&qnap_ts41x_button_device);
+        pm_power_off = qnap_tsx1x_power_off;
+}
+static int __init ts41x_pci_init(void)
+{
+        if (machine_is_ts41x())
+                kirkwood_pcie_init();
+   return 0;
+}
+subsys_initcall(ts41x_pci_init);
+MACHINE_START(TS41X, "QNAP TS-41x")
+        /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = qnap_ts41x_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c
new file mode 100644
index 000000000000..7221c20b2afa
--- /dev/null
+++ b/arch/arm/mach-kirkwood/tsx1x-common.c
@@ -0,0 +1,113 @@
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <linux/serial_reg.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+/*
+ * QNAP TS-x1x Boards flash
+ */
+/****************************************************************************
+ * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the
+ *     partitions on the device because we want to keep compatability with
+ *     the QNAP firmware.
+ * Layout as used by QNAP:
+ *  0x00000000-0x00080000 : "U-Boot"
+ *  0x00200000-0x00400000 : "Kernel"
+ *  0x00400000-0x00d00000 : "RootFS"
+ *  0x00d00000-0x01000000 : "RootFS2"
+ *  0x00080000-0x000c0000 : "U-Boot Config"
+ *  0x000c0000-0x00200000 : "NAS Config"
+ *
+ * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout
+ * used by the QNAP TS-109/TS-209.
+ *
+ ***************************************************************************/
+struct mtd_partition qnap_tsx1x_partitions[] = {
+        {
+                .name           = "U-Boot",
+                .size           = 0x00080000,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,
+        }, {
+                .name           = "Kernel",
+                .size           = 0x00200000,
+                .offset         = 0x00200000,
+        }, {
+                .name           = "RootFS1",
+                .size           = 0x00900000,
+                .offset         = 0x00400000,
+        }, {
+                .name           = "RootFS2",
+                .size           = 0x00300000,
+                .offset         = 0x00d00000,
+        }, {
+                .name           = "U-Boot Config",
+                .size           = 0x00040000,
+                .offset         = 0x00080000,
+        }, {
+                .name           = "NAS Config",
+                .size           = 0x00140000,
+                .offset         = 0x000c0000,
+        },
+};
+const struct flash_platform_data qnap_tsx1x_flash = {
+        .type           = "m25p128",
+        .name           = "spi_flash",
+        .parts          = qnap_tsx1x_partitions,
+        .nr_parts       = ARRAY_SIZE(qnap_tsx1x_partitions),
+};
+struct spi_board_info __initdata qnap_tsx1x_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &qnap_tsx1x_flash,
+                .irq            = -1,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+void qnap_tsx1x_register_flash(void)
+{
+        spi_register_board_info(qnap_tsx1x_spi_slave_info,
+                                ARRAY_SIZE(qnap_tsx1x_spi_slave_info));
+        kirkwood_spi_init();
+}
+/*****************************************************************************
+ * QNAP TS-x1x specific power off method via UART1-attached PIC
+ ****************************************************************************/
+#define UART1_REG(x)    (UART1_VIRT_BASE + ((UART_##x) << 2))
+void qnap_tsx1x_power_off(void)
+{
+        /* 19200 baud divisor */
+        const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200));
+        pr_info("%s: triggering power-off...\n", __func__);
+        /* hijack UART1 and reset into sane state (19200,8n1) */
+        writel(0x83, UART1_REG(LCR));
+        writel(divisor & 0xff, UART1_REG(DLL));
+        writel((divisor >> 8) & 0xff, UART1_REG(DLM));
+        writel(0x03, UART1_REG(LCR));
+        writel(0x00, UART1_REG(IER));
+        writel(0x00, UART1_REG(FCR));
+        writel(0x00, UART1_REG(MCR));
+        /* send the power-off command 'A' to PIC */
+        writel('A', UART1_REG(TX));
+}
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.h b/arch/arm/mach-kirkwood/tsx1x-common.h
new file mode 100644
index 000000000000..9a592962a6ea
--- /dev/null
+++ b/arch/arm/mach-kirkwood/tsx1x-common.h
@@ -0,0 +1,7 @@
+#ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H
+#define __ARCH_KIRKWOOD_TSX1X_COMMON_H
+extern void qnap_tsx1x_register_flash(void);
+extern void qnap_tsx1x_power_off(void);
+#endif
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
index c8a2eac4d13c..3e14da3698b5 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-mx2/Kconfig
@@ -6,11 +6,13 @@ choice
 config MACH_MX21
        bool "i.MX21 support"
+        select ARCH_MXC_AUDMUX_V1
        help
          This enables support for Freescale's MX2 based i.MX21 processor.
 config MACH_MX27
        bool "i.MX27 support"
+        select ARCH_MXC_AUDMUX_V1
        help
          This enables support for Freescale's MX2 based i.MX27 processor.
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index ff5e33298914..aa640b4876c9 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -651,8 +651,8 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
        _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
-        _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-        _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
        _REGISTER_CLOCK(NULL, "vpu", vpu_clk)
        _REGISTER_CLOCK(NULL, "dma", dma_clk)
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index 50199aff0143..3d398ce09b31 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -530,6 +530,84 @@ struct platform_device mxc_usbh2 = {
 };
 #endif
+static struct resource imx_ssi_resources0[] = {
+        {
+                .start  = SSI1_BASE_ADDR,
+                .end    = SSI1_BASE_ADDR + 0x6F,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MXC_INT_SSI1,
+                .end    = MXC_INT_SSI1,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .name   = "tx0",
+                .start  = DMA_REQ_SSI1_TX0,
+                .end    = DMA_REQ_SSI1_TX0,
+                .flags  = IORESOURCE_DMA,
+        }, {
+                .name   = "rx0",
+                .start  = DMA_REQ_SSI1_RX0,
+                .end    = DMA_REQ_SSI1_RX0,
+                .flags  = IORESOURCE_DMA,
+        }, {
+                .name   = "tx1",
+                .start  = DMA_REQ_SSI1_TX1,
+                .end    = DMA_REQ_SSI1_TX1,
+                .flags  = IORESOURCE_DMA,
+        }, {
+                .name   = "rx1",
+                .start  = DMA_REQ_SSI1_RX1,
+                .end    = DMA_REQ_SSI1_RX1,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+static struct resource imx_ssi_resources1[] = {
+        {
+                .start  = SSI2_BASE_ADDR,
+                .end    = SSI2_BASE_ADDR + 0x6F,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MXC_INT_SSI2,
+                .end    = MXC_INT_SSI2,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .name   = "tx0",
+                .start  = DMA_REQ_SSI2_TX0,
+                .end    = DMA_REQ_SSI2_TX0,
+                .flags  = IORESOURCE_DMA,
+        }, {
+                .name   = "rx0",
+                .start  = DMA_REQ_SSI2_RX0,
+                .end    = DMA_REQ_SSI2_RX0,
+                .flags  = IORESOURCE_DMA,
+        }, {
+                .name   = "tx1",
+                .start  = DMA_REQ_SSI2_TX1,
+                .end    = DMA_REQ_SSI2_TX1,
+                .flags  = IORESOURCE_DMA,
+        }, {
+                .name   = "rx1",
+                .start  = DMA_REQ_SSI2_RX1,
+                .end    = DMA_REQ_SSI2_RX1,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+struct platform_device imx_ssi_device0 = {
+        .name = "imx-ssi",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(imx_ssi_resources0),
+        .resource = imx_ssi_resources0,
+};
+struct platform_device imx_ssi_device1 = {
+        .name = "imx-ssi",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(imx_ssi_resources1),
+        .resource = imx_ssi_resources1,
+};
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
        {
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
index d315406d6725..97306aa18f1c 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-mx2/devices.h
@@ -26,4 +26,5 @@ extern struct platform_device mxc_usbh2;
 extern struct platform_device mxc_spi_device0;
 extern struct platform_device mxc_spi_device1;
 extern struct platform_device mxc_spi_device2;
+extern struct platform_device imx_ssi_device0;
+extern struct platform_device imx_ssi_device1;
diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/pca100.c
index fe5b165b88cc..aea3d340d2e1 100644
--- a/arch/arm/mach-mx2/pca100.c
+++ b/arch/arm/mach-mx2/pca100.c
@@ -237,7 +237,7 @@ MACHINE_START(PCA100, "phyCARD-i.MX27")
        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx27_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
        .init_machine   = pca100_init,
        .timer          = &pca100_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 851f2458bf65..0177b8a5fe3a 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -2,11 +2,13 @@ if ARCH_MX3
 config ARCH_MX31
        select ARCH_HAS_RNGA
+        select ARCH_MXC_AUDMUX_V2
        bool
 config ARCH_MX35
        bool
        select ARCH_MXC_IOMUX_V3
+        select ARCH_MXC_AUDMUX_V2
 comment "MX3 platforms:"
@@ -61,6 +63,7 @@ config MACH_MX31_3DS
 config MACH_MX31MOBOARD
        bool "Support mx31moboard platforms (EPFL Mobots group)"
        select ARCH_MX31
+        select MXC_ULPI
        help
          Include support for mx31moboard platform. This includes specific
          configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 6b9775471be6..940035cacae8 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -4,12 +4,12 @@
 # Object file lists.
-obj-y                           := mm.o devices.o
+obj-y                           := mm.o devices.o cpu.o
 obj-$(CONFIG_ARCH_MX31)         += clock.o iomux.o
 obj-$(CONFIG_ARCH_MX35)         += clock-imx35.o
 obj-$(CONFIG_MACH_MX31ADS)      += mx31ads.o
 obj-$(CONFIG_MACH_MX31LILLY)    += mx31lilly.o mx31lilly-db.o
-obj-$(CONFIG_MACH_MX31LITE)     += mx31lite.o
+obj-$(CONFIG_MACH_MX31LITE)     += mx31lite.o mx31lite-db.o
 obj-$(CONFIG_MACH_PCM037)       += pcm037.o
 obj-$(CONFIG_MACH_PCM037_EET)   += pcm037_eet.o
 obj-$(CONFIG_MACH_MX31_3DS)     += mx31pdk.o
diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c
index 776c0ee1b3cd..54aab401dbdf 100644
--- a/arch/arm/mach-mx3/armadillo5x0.c
+++ b/arch/arm/mach-mx3/armadillo5x0.c
@@ -33,6 +33,9 @@
 #include <linux/irq.h>
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+#include <linux/i2c.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -97,6 +100,47 @@ static int armadillo5x0_pins[] = {
        MX31_PIN_FPSHIFT__FPSHIFT,
        MX31_PIN_DRDY0__DRDY0,
        IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/
+        /* I2C2 */
+        MX31_PIN_CSPI2_MOSI__SCL,
+        MX31_PIN_CSPI2_MISO__SDA,
+};
+/* RTC over I2C*/
+#define ARMADILLO5X0_RTC_GPIO   IOMUX_TO_GPIO(MX31_PIN_SRXD4)
+static struct i2c_board_info armadillo5x0_i2c_rtc = {
+        I2C_BOARD_INFO("s35390a", 0x30),
+};
+/* GPIO BUTTONS */
+static struct gpio_keys_button armadillo5x0_buttons[] = {
+        {
+                .code           = KEY_ENTER, /*28*/
+                .gpio           = IOMUX_TO_GPIO(MX31_PIN_SCLK0),
+                .active_low     = 1,
+                .desc           = "menu",
+                .wakeup         = 1,
+        }, {
+                .code           = KEY_BACK, /*158*/
+                .gpio           = IOMUX_TO_GPIO(MX31_PIN_SRST0),
+                .active_low     = 1,
+                .desc           = "back",
+                .wakeup         = 1,
+        }
+};
+static struct gpio_keys_platform_data armadillo5x0_button_data = {
+        .buttons        = armadillo5x0_buttons,
+        .nbuttons       = ARRAY_SIZE(armadillo5x0_buttons),
+};
+static struct platform_device armadillo5x0_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &armadillo5x0_button_data,
+        }
 };
 /*
@@ -278,7 +322,7 @@ static struct resource armadillo5x0_smc911x_resources[] = {
 };
 static struct smsc911x_platform_config smsc911x_info = {
-        .flags          = SMSC911X_USE_32BIT,
+        .flags          = SMSC911X_USE_16BIT,
        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
 };
@@ -300,6 +344,8 @@ static struct imxuart_platform_data uart_pdata = {
 static struct platform_device *devices[] __initdata = {
        &armadillo5x0_smc911x_device,
+        &mxc_i2c_device1,
+        &armadillo5x0_button_device,
 };
 /*
@@ -335,6 +381,18 @@ static void __init armadillo5x0_init(void)
        /* set NAND page size to 2k if not configured via boot mode pins */
        __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
+        /* RTC */
+        /* Get RTC IRQ and register the chip */
+        if (gpio_request(ARMADILLO5X0_RTC_GPIO, "rtc") == 0) {
+                if (gpio_direction_input(ARMADILLO5X0_RTC_GPIO) == 0)
+                        armadillo5x0_i2c_rtc.irq = gpio_to_irq(ARMADILLO5X0_RTC_GPIO);
+                else
+                        gpio_free(ARMADILLO5X0_RTC_GPIO);
+        }
+        if (armadillo5x0_i2c_rtc.irq == 0)
+                pr_warning("armadillo5x0_init: failed to get RTC IRQ\n");
+        i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
 }
 static void __init armadillo5x0_timer_init(void)
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index c595260ec1f9..02a9a18e1189 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -335,7 +335,7 @@ static void clk_cgr_disable(struct clk *clk)
 DEFINE_CLOCK(asrc_clk,   0, CCM_CGR0,  0, NULL, NULL);
 DEFINE_CLOCK(ata_clk,    0, CCM_CGR0,  2, get_rate_ipg, NULL);
-DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0,  4, NULL, NULL);
+/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0,  4, NULL, NULL); */
 DEFINE_CLOCK(can1_clk,   0, CCM_CGR0,  6, get_rate_ipg, NULL);
 DEFINE_CLOCK(can2_clk,   1, CCM_CGR0,  8, get_rate_ipg, NULL);
 DEFINE_CLOCK(cspi1_clk,  0, CCM_CGR0, 10, get_rate_ipg, NULL);
@@ -381,12 +381,41 @@ DEFINE_CLOCK(uart3_clk,  2, CCM_CGR2, 20, get_rate_uart, NULL);
 DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
 DEFINE_CLOCK(wdog_clk,   0, CCM_CGR2, 24, NULL, NULL);
 DEFINE_CLOCK(max_clk,    0, CCM_CGR2, 26, NULL, NULL);
-DEFINE_CLOCK(admux_clk,  0, CCM_CGR2, 30, NULL, NULL);
+DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
 DEFINE_CLOCK(csi_clk,    0, CCM_CGR3,  0, get_rate_csi, NULL);
 DEFINE_CLOCK(iim_clk,    0, CCM_CGR3,  2, NULL, NULL);
 DEFINE_CLOCK(gpu2d_clk,  0, CCM_CGR3,  4, NULL, NULL);
+static int clk_dummy_enable(struct clk *clk)
+{
+        return 0;
+}
+static void clk_dummy_disable(struct clk *clk)
+{
+}
+static unsigned long get_rate_nfc(struct clk *clk)
+{
+        unsigned long div1;
+        div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;
+        return get_rate_ahb(NULL) / div1;
+}
+/* NAND Controller: It seems it can't be disabled */
+static struct clk nfc_clk = {
+        .id             = 0,
+        .enable_reg     = 0,
+        .enable_shift   = 0,
+        .get_rate       = get_rate_nfc,
+        .set_rate       = NULL, /* set_rate_nfc, */
+        .enable         = clk_dummy_enable,
+        .disable        = clk_dummy_disable
+};
 #define _REGISTER_CLOCK(d, n, c)        \
        {                               \
                .dev_id = d,            \
@@ -397,7 +426,6 @@ DEFINE_CLOCK(gpu2d_clk,  0, CCM_CGR3,  4, NULL, NULL);
 static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
        _REGISTER_CLOCK(NULL, "ata", ata_clk)
-        _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
        _REGISTER_CLOCK(NULL, "can", can1_clk)
        _REGISTER_CLOCK(NULL, "can", can2_clk)
        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
@@ -434,8 +462,8 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "sdma", sdma_clk)
        _REGISTER_CLOCK(NULL, "spba", spba_clk)
        _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
-        _REGISTER_CLOCK(NULL, "ssi", ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-        _REGISTER_CLOCK(NULL, "ssi", ssi2_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
        _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
        _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
        _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
@@ -445,10 +473,11 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
        _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
        _REGISTER_CLOCK(NULL, "max", max_clk)
-        _REGISTER_CLOCK(NULL, "admux", admux_clk)
+        _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
        _REGISTER_CLOCK(NULL, "csi", csi_clk)
        _REGISTER_CLOCK(NULL, "iim", iim_clk)
        _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
+        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
 };
 int __init mx35_clocks_init()
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index b2a3bcf8266e..27a318af0d20 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -558,8 +558,8 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
        _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
        _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
-        _REGISTER_CLOCK(NULL, "ssi", ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
-        _REGISTER_CLOCK(NULL, "ssi", ssi2_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
        _REGISTER_CLOCK(NULL, "firi", firi_clk)
        _REGISTER_CLOCK(NULL, "ata", ata_clk)
        _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
@@ -616,6 +616,8 @@ int __init mx31_clocks_init(unsigned long fref)
        clk_enable(&serial_pll_clk);
+        mx31_read_cpu_rev();
        if (mx31_revision() >= CHIP_REV_2_0) {
                reg = __raw_readl(MXC_CCM_PMCR1);
                /* No PLL restart on DVFS switch; enable auto EMI handshake */
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c
new file mode 100644
index 000000000000..db828809c675
--- /dev/null
+++ b/arch/arm/mach-mx3/cpu.c
@@ -0,0 +1,57 @@
+/*
+ * MX3 CPU type detection
+ *
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/iim.h>
+unsigned int mx31_cpu_rev;
+EXPORT_SYMBOL(mx31_cpu_rev);
+struct mx3_cpu_type {
+        u8 srev;
+        const char *name;
+        const char *v;
+        unsigned int rev;
+};
+static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
+        { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = CHIP_REV_1_0   },
+        { .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = CHIP_REV_1_1   },
+        { .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = CHIP_REV_1_1   },
+        { .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = CHIP_REV_1_1   },
+        { .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = CHIP_REV_1_1   },
+        { .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = CHIP_REV_1_2   },
+        { .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = CHIP_REV_1_2   },
+        { .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = CHIP_REV_2_0   },
+        { .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = CHIP_REV_2_0   },
+};
+void __init mx31_read_cpu_rev(void)
+{
+        u32 i, srev;
+        /* read SREV register from IIM module */
+        srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR) + MXC_IIMSREV);
+        for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
+                if (srev == mx31_cpu_type[i].srev) {
+                        printk(KERN_INFO
+                                "CPU identified as %s, silicon rev %s\n",
+                                mx31_cpu_type[i].name, mx31_cpu_type[i].v);
+                        mx31_cpu_rev = mx31_cpu_type[i].rev;
+                        return;
+                }
+        printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
+}
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index e6abe181b967..6adb586515ea 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -537,6 +537,44 @@ struct platform_device mxc_fec_device = {
 };
 #endif
+static struct resource imx_ssi_resources0[] = {
+        {
+                .start  = SSI1_BASE_ADDR,
+                .end    = SSI1_BASE_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MX31_INT_SSI1,
+                .end    = MX31_INT_SSI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct resource imx_ssi_resources1[] = {
+        {
+                .start  = SSI2_BASE_ADDR,
+                .end    = SSI2_BASE_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM
+        }, {
+                .start  = MX31_INT_SSI2,
+                .end    = MX31_INT_SSI2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device imx_ssi_device0 = {
+        .name = "imx-ssi",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(imx_ssi_resources0),
+        .resource = imx_ssi_resources0,
+};
+struct platform_device imx_ssi_device1 = {
+        .name = "imx-ssi",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(imx_ssi_resources1),
+        .resource = imx_ssi_resources1,
+};
 static int mx3_devices_init(void)
 {
        if (cpu_is_mx31()) {
@@ -546,7 +584,7 @@ static int mx3_devices_init(void)
        }
        if (cpu_is_mx35()) {
                mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
-                mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
+                mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff;
                otg_resources[0].start = MX35_OTG_BASE_ADDR;
                otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
                otg_resources[1].start = MXC_INT_USBOTG;
@@ -555,6 +593,10 @@ static int mx3_devices_init(void)
                mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
                mxc_usbh1_resources[1].start = MXC_INT_USBHS;
                mxc_usbh1_resources[1].end = MXC_INT_USBHS;
+                imx_ssi_resources0[1].start = MX35_INT_SSI1;
+                imx_ssi_resources0[1].end = MX35_INT_SSI1;
+                imx_ssi_resources1[1].start = MX35_INT_SSI2;
+                imx_ssi_resources1[1].end = MX35_INT_SSI2;
        }
        return 0;
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index ab87419dc9a0..42cf175eac6b 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -23,4 +23,6 @@ extern struct platform_device mxc_rnga_device;
 extern struct platform_device mxc_spi_device0;
 extern struct platform_device mxc_spi_device1;
 extern struct platform_device mxc_spi_device2;
+extern struct platform_device imx_ssi_device0;
+extern struct platform_device imx_ssi_device1;
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
index 3b3a78f49c23..7aebd74a12e8 100644
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ b/arch/arm/mach-mx3/mx31lilly-db.c
@@ -109,6 +109,9 @@ static int mxc_mmc1_get_ro(struct device *dev)
 static int gpio_det, gpio_wp;
+#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
 static int mxc_mmc1_init(struct device *dev,
                         irq_handler_t detect_irq, void *data)
 {
@@ -117,6 +120,13 @@ static int mxc_mmc1_init(struct device *dev,
        gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1);
        gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
        ret = gpio_request(gpio_det, "MMC detect");
        if (ret)
                return ret;
diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mx31lilly.c
index 423025150f6f..9ce029f554b9 100644
--- a/arch/arm/mach-mx3/mx31lilly.c
+++ b/arch/arm/mach-mx3/mx31lilly.c
@@ -31,6 +31,8 @@
 #include <linux/interrupt.h>
 #include <linux/smsc911x.h>
 #include <linux/mtd/physmap.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/mc13783.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -41,6 +43,7 @@
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
+#include <mach/spi.h>
 #include "devices.h"
@@ -108,7 +111,36 @@ static struct platform_device physmap_flash_device = {
 static struct platform_device *devices[] __initdata = {
        &smsc91x_device,
        &physmap_flash_device,
-        &mxc_i2c_device1,
+};
+/* SPI */
+static int spi_internal_chipselect[] = {
+        MXC_SPI_CS(0),
+        MXC_SPI_CS(1),
+        MXC_SPI_CS(2),
+};
+static struct spi_imx_master spi0_pdata = {
+        .chipselect = spi_internal_chipselect,
+        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
+};
+static struct spi_imx_master spi1_pdata = {
+        .chipselect = spi_internal_chipselect,
+        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
+};
+static struct mc13783_platform_data mc13783_pdata __initdata = {
+        .flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN,
+};
+static struct spi_board_info mc13783_dev __initdata = {
+        .modalias       = "mc13783",
+        .max_speed_hz   = 1000000,
+        .bus_num        = 1,
+        .chip_select    = 0,
+        .platform_data  = &mc13783_pdata,
 };
 static int mx31lilly_baseboard;
@@ -128,8 +160,27 @@ static void __init mx31lilly_board_init(void)
        }
        mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS");
-        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__SCL, "I2C SCL");
-        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__SDA, "I2C SDA");
+        /* SPI */
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
+        mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
+        mxc_register_device(&mxc_spi_device0, &spi0_pdata);
+        mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+        spi_register_board_info(&mc13783_dev, 1);
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
new file mode 100644
index 000000000000..694611d6b057
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -0,0 +1,198 @@
+/*
+ *  LogicPD i.MX31 SOM-LV development board support
+ *
+ *    Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ *  based on code for other MX31 boards,
+ *
+ *    Copyright 2005-2007 Freescale Semiconductor
+ *    Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
+ *    Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-mx31lite.h>
+#include <mach/mmc.h>
+#include <mach/spi.h>
+#include "devices.h"
+/*
+ * This file contains board-specific initialization routines for the
+ * LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'.
+ * If you design an own baseboard for the module, use this file as base
+ * for support code.
+ */
+static unsigned int litekit_db_board_pins[] __initdata = {
+        /* UART1 */
+        MX31_PIN_CTS1__CTS1,
+        MX31_PIN_RTS1__RTS1,
+        MX31_PIN_TXD1__TXD1,
+        MX31_PIN_RXD1__RXD1,
+        /* SPI 0 */
+        MX31_PIN_CSPI1_SCLK__SCLK,
+        MX31_PIN_CSPI1_MOSI__MOSI,
+        MX31_PIN_CSPI1_MISO__MISO,
+        MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
+        MX31_PIN_CSPI1_SS0__SS0,
+        MX31_PIN_CSPI1_SS1__SS1,
+        MX31_PIN_CSPI1_SS2__SS2,
+};
+/* UART */
+static struct imxuart_platform_data uart_pdata __initdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+/* MMC */
+static int gpio_det, gpio_wp;
+#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+static int mxc_mmc1_get_ro(struct device *dev)
+{
+        return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0));
+}
+static int mxc_mmc1_init(struct device *dev,
+                         irq_handler_t detect_irq, void *data)
+{
+        int ret;
+        gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1);
+        gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
+        ret = gpio_request(gpio_det, "MMC detect");
+        if (ret)
+                return ret;
+        ret = gpio_request(gpio_wp, "MMC w/p");
+        if (ret)
+                goto exit_free_det;
+        gpio_direction_input(gpio_det);
+        gpio_direction_input(gpio_wp);
+        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
+                          IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+                          "MMC detect", data);
+        if (ret)
+                goto exit_free_wp;
+        return 0;
+exit_free_wp:
+        gpio_free(gpio_wp);
+exit_free_det:
+        gpio_free(gpio_det);
+        return ret;
+}
+static void mxc_mmc1_exit(struct device *dev, void *data)
+{
+        gpio_free(gpio_det);
+        gpio_free(gpio_wp);
+        free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
+}
+static struct imxmmc_platform_data mmc_pdata = {
+        .get_ro  = mxc_mmc1_get_ro,
+        .init      = mxc_mmc1_init,
+        .exit      = mxc_mmc1_exit,
+};
+/* SPI */
+static int spi_internal_chipselect[] = {
+        MXC_SPI_CS(0),
+        MXC_SPI_CS(1),
+        MXC_SPI_CS(2),
+};
+static struct spi_imx_master spi0_pdata = {
+        .chipselect     = spi_internal_chipselect,
+        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
+};
+/* GPIO LEDs */
+static struct gpio_led litekit_leds[] = {
+        {
+                .name           = "GPIO0",
+                .gpio           = IOMUX_TO_GPIO(MX31_PIN_COMPARE),
+                .active_low     = 1,
+                .default_state  = LEDS_GPIO_DEFSTATE_OFF,
+        },
+        {
+                .name           = "GPIO1",
+                .gpio           = IOMUX_TO_GPIO(MX31_PIN_CAPTURE),
+                .active_low     = 1,
+                .default_state  = LEDS_GPIO_DEFSTATE_OFF,
+        }
+};
+static struct gpio_led_platform_data litekit_led_platform_data = {
+        .leds           = litekit_leds,
+        .num_leds       = ARRAY_SIZE(litekit_leds),
+};
+static struct platform_device litekit_led_device = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &litekit_led_platform_data,
+        },
+};
+void __init mx31lite_db_init(void)
+{
+        mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
+                                        ARRAY_SIZE(litekit_db_board_pins),
+                                        "development board pins");
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
+        mxc_register_device(&mxc_spi_device0, &spi0_pdata);
+        platform_device_register(&litekit_led_device);
+}
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
index a8d57decdfdb..def6b6736594 100644
--- a/arch/arm/mach-mx3/mx31lite.c
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -2,6 +2,7 @@
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *  Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -25,38 +26,47 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/smsc911x.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/spi/spi.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/mtd/physmap.h>
-#include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/common.h>
 #include <asm/page.h>
 #include <asm/setup.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
 #include <mach/board-mx31lite.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/irqs.h>
 #include <mach/mxc_nand.h>
+#include <mach/spi.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
 #include "devices.h"
 /*
- * This file contains the board-specific initialization routines.
+ * This file contains the module-specific initialization routines.
 */
 static unsigned int mx31lite_pins[] = {
-        /* UART1 */
-        MX31_PIN_CTS1__CTS1,
-        MX31_PIN_RTS1__RTS1,
-        MX31_PIN_TXD1__TXD1,
-        MX31_PIN_RXD1__RXD1,
        /* LAN9117 IRQ pin */
        IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
-};
+        /* SPI 1 */
+        MX31_PIN_CSPI2_SCLK__SCLK,
-static struct imxuart_platform_data uart_pdata = {
+        MX31_PIN_CSPI2_MOSI__MOSI,
-        .flags = IMXUART_HAVE_RTSCTS,
+        MX31_PIN_CSPI2_MISO__MISO,
+        MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
+        MX31_PIN_CSPI2_SS0__SS0,
+        MX31_PIN_CSPI2_SS1__SS1,
+        MX31_PIN_CSPI2_SS2__SS2,
 };
 static struct mxc_nand_platform_data mx31lite_nand_board_info = {
@@ -93,6 +103,111 @@ static struct platform_device smsc911x_device = {
 };
 /*
+ * SPI
+ *
+ * The MC13783 is the only hard-wired SPI device on the module.
+ */
+static int spi_internal_chipselect[] = {
+        MXC_SPI_CS(0),
+};
+static struct spi_imx_master spi1_pdata = {
+        .chipselect     = spi_internal_chipselect,
+        .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
+};
+static struct mc13783_platform_data mc13783_pdata __initdata = {
+        .flags  = MC13783_USE_RTC |
+                  MC13783_USE_REGULATOR,
+};
+static struct spi_board_info mc13783_spi_dev __initdata = {
+        .modalias       = "mc13783",
+        .max_speed_hz   = 1000000,
+        .bus_num        = 1,
+        .chip_select    = 0,
+        .platform_data  = &mc13783_pdata,
+        .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+};
+/*
+ * USB
+ */
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+static int usbh2_init(struct platform_device *pdev)
+{
+        int pins[] = {
+                MX31_PIN_USBH2_DATA0__USBH2_DATA0,
+                MX31_PIN_USBH2_DATA1__USBH2_DATA1,
+                MX31_PIN_USBH2_CLK__USBH2_CLK,
+                MX31_PIN_USBH2_DIR__USBH2_DIR,
+                MX31_PIN_USBH2_NXT__USBH2_NXT,
+                MX31_PIN_USBH2_STP__USBH2_STP,
+        };
+        mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
+        mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
+        mxc_iomux_set_gpr(MUX_PGP_UH2, true);
+        /* chip select */
+        mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
+                                "USBH2_CS");
+        gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
+        gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
+        return 0;
+}
+static struct mxc_usbh_platform_data usbh2_pdata = {
+        .init   = usbh2_init,
+        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
+};
+/*
+ * NOR flash
+ */
+static struct physmap_flash_data nor_flash_data = {
+        .width  = 2,
+};
+static struct resource nor_flash_resource = {
+        .start  = 0xa0000000,
+        .end    = 0xa1ffffff,
+        .flags  = IORESOURCE_MEM,
+};
+static struct platform_device physmap_flash_device = {
+        .name   = "physmap-flash",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &nor_flash_data,
+        },
+        .resource = &nor_flash_resource,
+        .num_resources = 1,
+};
+/*
 * This structure defines the MX31 memory map.
 */
 static struct map_desc mx31lite_io_desc[] __initdata = {
@@ -118,19 +233,40 @@ void __init mx31lite_map_io(void)
        iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
 }
-/*
+static int mx31lite_baseboard;
- * Board specific initialization.
+core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
- */
 static void __init mxc_board_init(void)
 {
        int ret;
+        switch (mx31lite_baseboard) {
+        case MX31LITE_NOBOARD:
+                break;
+        case MX31LITE_DB:
+                mx31lite_db_init();
+                break;
+        default:
+                printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
+                                mx31lite_baseboard);
+        }
        mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
                                      "mx31lite");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        /* NOR and NAND flash */
+        platform_device_register(&physmap_flash_device);
        mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info);
+        mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+        spi_register_board_info(&mc13783_spi_dev, 1);
+        /* USB */
+        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
        /* SMSC9117 IRQ pin */
        ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
        if (ret)
@@ -150,12 +286,7 @@ struct sys_timer mx31lite_timer = {
        .init   = mx31lite_timer_init,
 };
-/*
+MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
- * The following uses standard kernel macros defined in arch.h in order to
- * initialize __mach_desc_MX31LITE data structure.
- */
-MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT")
        /* Maintainer: Freescale Semiconductor, Inc. */
        .phys_io        = AIPS1_BASE_ADDR,
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 5592cdb8d0ad..8fc624f141cb 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -22,11 +22,15 @@
 #include <linux/platform_device.h>
 #include <linux/types.h>
+#include <linux/usb/otg.h>
 #include <mach/common.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/hardware.h>
 #include <mach/mmc.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
 #include "devices.h"
@@ -39,6 +43,12 @@ static unsigned int devboard_pins[] = {
        MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
        MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
        MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
+        /* USB H1 */
+        MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
+        MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
+        MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
+        MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
+        MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
 };
 static struct imxuart_platform_data uart_pdata = {
@@ -98,6 +108,80 @@ static struct imxmmc_platform_data sdhc2_pdata = {
        .exit   = devboard_sdhc2_exit,
 };
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+static int devboard_usbh1_hw_init(struct platform_device *pdev)
+{
+        mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
+        return 0;
+}
+#define USBH1_VBUSEN_B  IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
+#define USBH1_MODE      IOMUX_TO_GPIO(MX31_PIN_NFALE)
+static int devboard_isp1105_init(struct otg_transceiver *otg)
+{
+        int ret = gpio_request(USBH1_MODE, "usbh1-mode");
+        if (ret)
+                return ret;
+        /* single ended */
+        gpio_direction_output(USBH1_MODE, 0);
+        ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
+        if (ret) {
+                gpio_free(USBH1_MODE);
+                return ret;
+        }
+        gpio_direction_output(USBH1_VBUSEN_B, 1);
+        return 0;
+}
+static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
+{
+        if (on)
+                gpio_set_value(USBH1_VBUSEN_B, 0);
+        else
+                gpio_set_value(USBH1_VBUSEN_B, 1);
+        return 0;
+}
+static struct mxc_usbh_platform_data usbh1_pdata = {
+        .init   = devboard_usbh1_hw_init,
+        .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
+};
+static int __init devboard_usbh1_init(void)
+{
+        struct otg_transceiver *otg;
+        otg = kzalloc(sizeof(*otg), GFP_KERNEL);
+        if (!otg)
+                return -ENOMEM;
+        otg->label      = "ISP1105";
+        otg->init       = devboard_isp1105_init;
+        otg->set_vbus   = devboard_isp1105_set_vbus;
+        usbh1_pdata.otg = otg;
+        return mxc_register_device(&mx31_usbh1, &usbh1_pdata);
+}
 /*
 * system init for baseboard usage. Will be called by mx31moboard init.
 */
@@ -111,4 +195,6 @@ void __init mx31moboard_devboard_init(void)
        mxc_register_device(&mxc_uart_device1, &uart_pdata);
        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
+        devboard_usbh1_init();
 }
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 2bfaffb344f0..85184a35e674 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -16,17 +16,26 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+#include <linux/delay.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/spi/spi.h>
 #include <linux/platform_device.h>
 #include <linux/types.h>
+#include <linux/usb/otg.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/mmc.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
+#include <media/soc_camera.h>
 #include "devices.h"
@@ -37,7 +46,6 @@ static unsigned int marxbot_pins[] = {
        MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
        MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
        /* CSI */
-        MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5,
        MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
        MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
        MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
@@ -45,10 +53,19 @@ static unsigned int marxbot_pins[] = {
        MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
        MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
        MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
+        MX31_PIN_CSI_D4__GPIO3_4, MX31_PIN_CSI_D5__GPIO3_5,
        MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
        MX31_PIN_TXD2__GPIO1_28,
        /* dsPIC resets */
        MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22,
+        /*battery detection */
+        MX31_PIN_LCS0__GPIO3_23,
+        /* USB H1 */
+        MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
+        MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
+        MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
+        MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
+        MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
 };
 #define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
@@ -120,6 +137,166 @@ static void dspics_resets_init(void)
        }
 }
+static struct spi_board_info marxbot_spi_board_info[] __initdata = {
+        {
+                .modalias = "spidev",
+                .max_speed_hz = 300000,
+                .bus_num = 1,
+                .chip_select = 1, /* according spi1_cs[] ! */
+        },
+};
+#define TURRETCAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
+#define BASECAM_POWER   IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
+#define TURRETCAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
+#define BASECAM_RST_B   IOMUX_TO_GPIO(MX31_PIN_CSI_D4)
+#define CAM_CHOICE      IOMUX_TO_GPIO(MX31_PIN_TXD2)
+static int marxbot_basecam_power(struct device *dev, int on)
+{
+        gpio_set_value(BASECAM_POWER, !on);
+        return 0;
+}
+static int marxbot_basecam_reset(struct device *dev)
+{
+        gpio_set_value(BASECAM_RST_B, 0);
+        udelay(100);
+        gpio_set_value(BASECAM_RST_B, 1);
+        return 0;
+}
+static struct i2c_board_info marxbot_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("mt9t031", 0x5d),
+        },
+};
+static struct soc_camera_link base_iclink = {
+        .bus_id         = 0,            /* Must match with the camera ID */
+        .power          = marxbot_basecam_power,
+        .reset          = marxbot_basecam_reset,
+        .board_info     = &marxbot_i2c_devices[0],
+        .i2c_adapter_id = 0,
+        .module_name    = "mt9t031",
+};
+static struct platform_device marxbot_camera[] = {
+        {
+                .name   = "soc-camera-pdrv",
+                .id     = 0,
+                .dev    = {
+                        .platform_data = &base_iclink,
+                },
+        },
+};
+static struct platform_device *marxbot_cameras[] __initdata = {
+        &marxbot_camera[0],
+};
+static int __init marxbot_cam_init(void)
+{
+        int ret = gpio_request(CAM_CHOICE, "cam-choice");
+        if (ret)
+                return ret;
+        gpio_direction_output(CAM_CHOICE, 1);
+        ret = gpio_request(BASECAM_RST_B, "basecam-reset");
+        if (ret)
+                return ret;
+        gpio_direction_output(BASECAM_RST_B, 1);
+        ret = gpio_request(BASECAM_POWER, "basecam-standby");
+        if (ret)
+                return ret;
+        gpio_direction_output(BASECAM_POWER, 0);
+        ret = gpio_request(TURRETCAM_RST_B, "turretcam-reset");
+        if (ret)
+                return ret;
+        gpio_direction_output(TURRETCAM_RST_B, 1);
+        ret = gpio_request(TURRETCAM_POWER, "turretcam-standby");
+        if (ret)
+                return ret;
+        gpio_direction_output(TURRETCAM_POWER, 0);
+        return 0;
+}
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+static int marxbot_usbh1_hw_init(struct platform_device *pdev)
+{
+        mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
+        return 0;
+}
+#define USBH1_VBUSEN_B  IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
+#define USBH1_MODE      IOMUX_TO_GPIO(MX31_PIN_NFALE)
+static int marxbot_isp1105_init(struct otg_transceiver *otg)
+{
+        int ret = gpio_request(USBH1_MODE, "usbh1-mode");
+        if (ret)
+                return ret;
+        /* single ended */
+        gpio_direction_output(USBH1_MODE, 0);
+        ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
+        if (ret) {
+                gpio_free(USBH1_MODE);
+                return ret;
+        }
+        gpio_direction_output(USBH1_VBUSEN_B, 1);
+        return 0;
+}
+static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
+{
+        if (on)
+                gpio_set_value(USBH1_VBUSEN_B, 0);
+        else
+                gpio_set_value(USBH1_VBUSEN_B, 1);
+        return 0;
+}
+static struct mxc_usbh_platform_data usbh1_pdata = {
+        .init   = marxbot_usbh1_hw_init,
+        .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
+};
+static int __init marxbot_usbh1_init(void)
+{
+        struct otg_transceiver *otg;
+        otg = kzalloc(sizeof(*otg), GFP_KERNEL);
+        if (!otg)
+                return -ENOMEM;
+        otg->label      = "ISP1105";
+        otg->init       = marxbot_isp1105_init;
+        otg->set_vbus   = marxbot_isp1105_set_vbus;
+        usbh1_pdata.otg = otg;
+        return mxc_register_device(&mx31_usbh1, &usbh1_pdata);
+}
 /*
 * system init for baseboard usage. Will be called by mx31moboard init.
 */
@@ -133,4 +310,17 @@ void __init mx31moboard_marxbot_init(void)
        dspics_resets_init();
        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
+        spi_register_board_info(marxbot_spi_board_info,
+                ARRAY_SIZE(marxbot_spi_board_info));
+        marxbot_cam_init();
+        platform_add_devices(marxbot_cameras, ARRAY_SIZE(marxbot_cameras));
+        /* battery present pin */
+        gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present");
+        gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
+        gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
+        marxbot_usbh1_init();
 }
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c
index 9243de54041a..1ec679a3c72f 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mx31moboard.c
@@ -17,6 +17,7 @@
 */
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
 #include <linux/fsl_devices.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
@@ -26,8 +27,14 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
 #include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/spi/spi.h>
 #include <linux/types.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -37,16 +44,20 @@
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
+#include <mach/ipu.h>
 #include <mach/i2c.h>
 #include <mach/mmc.h>
-#include <mach/mx31.h>
+#include <mach/mxc_ehci.h>
+#include <mach/mx3_camera.h>
+#include <mach/spi.h>
+#include <mach/ulpi.h>
 #include "devices.h"
 static unsigned int moboard_pins[] = {
        /* UART0 */
-        MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1,
        MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1,
+        MX31_PIN_CTS1__GPIO2_7,
        /* UART4 */
        MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5,
        MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5,
@@ -73,12 +84,31 @@ static unsigned int moboard_pins[] = {
        MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
        MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
        MX31_PIN_USB_OC__GPIO1_30,
+        /* USB H2 */
+        MX31_PIN_USBH2_DATA0__USBH2_DATA0,
+        MX31_PIN_USBH2_DATA1__USBH2_DATA1,
+        MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3,
+        MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5,
+        MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7,
+        MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR,
+        MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP,
+        MX31_PIN_SCK6__GPIO1_25,
        /* LEDs */
        MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
        MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
        /* SEL */
        MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
        MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
+        /* SPI1 */
+        MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO,
+        MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
+        MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2,
+        /* Atlas IRQ */
+        MX31_PIN_GPIO1_3__GPIO1_3,
+        /* SPI2 */
+        MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO,
+        MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY,
+        MX31_PIN_CSPI2_SS1__CSPI3_SS1,
 };
 static struct physmap_flash_data mx31moboard_flash_data = {
@@ -101,7 +131,18 @@ static struct platform_device mx31moboard_flash = {
        .num_resources = 1,
 };
-static struct imxuart_platform_data uart_pdata = {
+static int moboard_uart0_init(struct platform_device *pdev)
+{
+        gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
+        gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
+        return 0;
+}
+static struct imxuart_platform_data uart0_pdata = {
+        .init = moboard_uart0_init,
+};
+static struct imxuart_platform_data uart4_pdata = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -113,6 +154,103 @@ static struct imxi2c_platform_data moboard_i2c1_pdata = {
        .bitrate = 100000,
 };
+static int moboard_spi1_cs[] = {
+        MXC_SPI_CS(0),
+        MXC_SPI_CS(2),
+};
+static struct spi_imx_master moboard_spi1_master = {
+        .chipselect     = moboard_spi1_cs,
+        .num_chipselect = ARRAY_SIZE(moboard_spi1_cs),
+};
+static struct regulator_consumer_supply sdhc_consumers[] = {
+        {
+                .dev    = &mxcsdhc_device0.dev,
+                .supply = "sdhc0_vcc",
+        },
+        {
+                .dev    = &mxcsdhc_device1.dev,
+                .supply = "sdhc1_vcc",
+        },
+};
+static struct regulator_init_data sdhc_vreg_data = {
+        .constraints = {
+                .min_uV = 2700000,
+                .max_uV = 3000000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                        REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+                .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                        REGULATOR_MODE_FAST,
+                .always_on = 0,
+                .boot_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(sdhc_consumers),
+        .consumer_supplies = sdhc_consumers,
+};
+static struct regulator_consumer_supply cam_consumers[] = {
+        {
+                .dev    = &mx3_camera.dev,
+                .supply = "cam_vcc",
+        },
+};
+static struct regulator_init_data cam_vreg_data = {
+        .constraints = {
+                .min_uV = 2700000,
+                .max_uV = 3000000,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+                        REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+                .valid_modes_mask = REGULATOR_MODE_NORMAL |
+                        REGULATOR_MODE_FAST,
+                .always_on = 0,
+                .boot_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(cam_consumers),
+        .consumer_supplies = cam_consumers,
+};
+static struct mc13783_regulator_init_data moboard_regulators[] = {
+        {
+                .id = MC13783_REGU_VMMC1,
+                .init_data = &sdhc_vreg_data,
+        },
+        {
+                .id = MC13783_REGU_VCAM,
+                .init_data = &cam_vreg_data,
+        },
+};
+static struct mc13783_platform_data moboard_pmic = {
+        .regulators = moboard_regulators,
+        .num_regulators = ARRAY_SIZE(moboard_regulators),
+        .flags = MC13783_USE_REGULATOR | MC13783_USE_RTC,
+                MC13783_USE_ADC,
+};
+static struct spi_board_info moboard_spi_board_info[] __initdata = {
+        {
+                .modalias = "mc13783",
+                .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+                .max_speed_hz = 300000,
+                .bus_num = 1,
+                .chip_select = 0,
+                .platform_data = &moboard_pmic,
+                .mode = SPI_CS_HIGH,
+        },
+};
+static int moboard_spi2_cs[] = {
+        MXC_SPI_CS(1),
+};
+static struct spi_imx_master moboard_spi2_master = {
+        .chipselect     = moboard_spi2_cs,
+        .num_chipselect = ARRAY_SIZE(moboard_spi2_cs),
+};
 #define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0)
 #define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1)
@@ -208,6 +346,56 @@ static struct fsl_usb2_platform_data usb_pdata = {
        .phy_mode       = FSL_USB2_PHY_ULPI,
 };
+#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
+static int moboard_usbh2_hw_init(struct platform_device *pdev)
+{
+        int ret = gpio_request(USBH2_EN_B, "usbh2-en");
+        if (ret)
+                return ret;
+        mxc_iomux_set_gpr(MUX_PGP_UH2, true);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
+        gpio_direction_output(USBH2_EN_B, 0);
+        return 0;
+}
+static int moboard_usbh2_hw_exit(struct platform_device *pdev)
+{
+        gpio_free(USBH2_EN_B);
+        return 0;
+}
+static struct mxc_usbh_platform_data usbh2_pdata = {
+        .init   = moboard_usbh2_hw_init,
+        .exit   = moboard_usbh2_hw_exit,
+        .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+        .flags  = MXC_EHCI_POWER_PINS_ENABLED,
+};
+static int __init moboard_usbh2_init(void)
+{
+        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                        USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+        return mxc_register_device(&mx31_usbh2, &usbh2_pdata);
+}
 static struct gpio_led mx31moboard_leds[] = {
        {
                .name   = "coreboard-led-0:red:running",
@@ -266,11 +454,48 @@ static void mx31moboard_init_sel_gpios(void)
        }
 }
+static struct ipu_platform_data mx3_ipu_data = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
 static struct platform_device *devices[] __initdata = {
        &mx31moboard_flash,
        &mx31moboard_leds_device,
 };
+static struct mx3_camera_pdata camera_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .flags          = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
+        .mclk_10khz     = 4800,
+};
+#define CAMERA_BUF_SIZE (4*1024*1024)
+static int __init mx31moboard_cam_alloc_dma(const size_t buf_size)
+{
+        dma_addr_t dma_handle;
+        void *buf;
+        int dma;
+        if (buf_size < 2 * 1024 * 1024)
+                return -EINVAL;
+        buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
+        if (!buf) {
+                pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
+                return -ENOMEM;
+        }
+        memset(buf, 0, buf_size);
+        dma = dma_declare_coherent_memory(&mx3_camera.dev,
+                                        dma_handle, dma_handle, buf_size,
+                                        DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+        /* The way we call dma_declare_coherent_memory only a malloc can fail */
+        return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
+}
 static int mx31moboard_baseboard;
 core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
@@ -284,20 +509,34 @@ static void __init mxc_board_init(void)
        platform_add_devices(devices, ARRAY_SIZE(devices));
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_uart_device0, &uart0_pdata);
-        mxc_register_device(&mxc_uart_device4, &uart_pdata);
+        mxc_register_device(&mxc_uart_device4, &uart4_pdata);
        mx31moboard_init_sel_gpios();
        mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
        mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
+        mxc_register_device(&mxc_spi_device1, &moboard_spi1_master);
+        mxc_register_device(&mxc_spi_device2, &moboard_spi2_master);
+        gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
+        gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
+        spi_register_board_info(moboard_spi_board_info,
+                ARRAY_SIZE(moboard_spi_board_info));
        mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata);
+        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+        if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))
+                mxc_register_device(&mx3_camera, &camera_pdata);
        usb_xcvr_reset();
        moboard_usbotg_init();
        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+        moboard_usbh2_init();
        switch (mx31moboard_baseboard) {
        case MX31NOBOARD:
diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/pcm043.c
index e18a224671fa..e3aa829be586 100644
--- a/arch/arm/mach-mx3/pcm043.c
+++ b/arch/arm/mach-mx3/pcm043.c
@@ -43,6 +43,7 @@
 #include <mach/iomux-mx35.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
+#include <mach/mxc_nand.h>
 #include "devices.h"
@@ -206,6 +207,11 @@ static struct pad_desc pcm043_pads[] = {
        MX35_PAD_ATA_CS0__GPIO2_6,
 };
+static struct mxc_nand_platform_data pcm037_nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
 /*
 * Board specific initialization.
 */
@@ -216,6 +222,7 @@ static void __init mxc_board_init(void)
        platform_add_devices(devices, ARRAY_SIZE(devices));
        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
        mxc_register_device(&mxc_uart_device1, &uart_pdata);
diff --git a/arch/arm/mach-s3c2400/include/mach/map.h b/arch/arm/mach-s3c2400/include/mach/map.h
index 1535540edc82..3fd889200e99 100644
--- a/arch/arm/mach-s3c2400/include/mach/map.h
+++ b/arch/arm/mach-s3c2400/include/mach/map.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2400/include/mach/map.h
 *
- * Copyright 2003,2007  Simtec Electronics
+ * Copyright 2003-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 3d4e9da3fa52..dd1fcc7e6708 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -81,6 +81,14 @@ config ARCH_H1940
        help
          Say Y here if you are using the HP IPAQ H1940
+config H1940BT
+        tristate "Control the state of H1940 bluetooth chip"
+        depends on ARCH_H1940
+        select RFKILL
+        help
+          This is a simple driver that is able to control
+          the state of built in bluetooth chip on h1940.
 config PM_H1940
        bool
        help
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 2ab5ba4b266f..0d468e96e83e 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -21,7 +21,8 @@ obj-$(CONFIG_S3C2410_PLLTABLE)	+= pll.o
 # Machine support
 obj-$(CONFIG_ARCH_SMDK2410)     += mach-smdk2410.o
-obj-$(CONFIG_ARCH_H1940)        += mach-h1940.o h1940-bluetooth.o
+obj-$(CONFIG_ARCH_H1940)        += mach-h1940.o
+obj-$(CONFIG_H1940BT)           += h1940-bluetooth.o
 obj-$(CONFIG_PM_H1940)          += pm-h1940.o
 obj-$(CONFIG_MACH_N30)          += mach-n30.o
 obj-$(CONFIG_ARCH_BAST)         += mach-bast.o usb-simtec.o
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 9a37c87152b0..217b102866d0 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/bast-irq.c
 *
- * Copyright (c) 2003,2005 Simtec Electronics
+ * Copyright 2003-2005 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.simtec.co.uk/products/EB2410ITX/
@@ -141,7 +141,7 @@ static __init int bast_irq_init(void)
        unsigned int i;
        if (machine_is_bast()) {
-                printk(KERN_INFO "BAST PC104 IRQ routing, (c) 2005 Simtec Electronics\n");
+                printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n");
                /* zap all the IRQs */
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c
index 9d1186877d08..75189df995ae 100644
--- a/arch/arm/mach-s3c2410/cpu-freq.c
+++ b/arch/arm/mach-s3c2410/cpu-freq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/cpu-freq.c
 *
- * Copyright (c) 2006,2008 Simtec Electronics
+ * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
index 5aabf117cbb0..b7d1f8d27bc2 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c
@@ -17,6 +17,7 @@
 #include <linux/ctype.h>
 #include <linux/leds.h>
 #include <linux/gpio.h>
+#include <linux/rfkill.h>
 #include <mach/regs-gpio.h>
 #include <mach/hardware.h>
@@ -24,21 +25,10 @@
 #define DRV_NAME              "h1940-bt"
-#ifdef CONFIG_LEDS_H1940
-DEFINE_LED_TRIGGER(bt_led_trigger);
-#endif
-static int state;
 /* Bluetooth control */
 static void h1940bt_enable(int on)
 {
        if (on) {
-#ifdef CONFIG_LEDS_H1940
-                /* flashing Blue */
-                led_trigger_event(bt_led_trigger, LED_HALF);
-#endif
                /* Power on the chip */
                h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
                /* Reset the chip */
@@ -46,48 +36,31 @@ static void h1940bt_enable(int on)
                s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
                mdelay(10);
                s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
-                state = 1;
        }
        else {
-#ifdef CONFIG_LEDS_H1940
-                led_trigger_event(bt_led_trigger, 0);
-#endif
                s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
                mdelay(10);
                s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
                mdelay(10);
                h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0);
-                state = 0;
        }
 }
-static ssize_t h1940bt_show(struct device *dev, struct device_attribute *attr, char *buf)
+static int h1940bt_set_block(void *data, bool blocked)
 {
-        return snprintf(buf, PAGE_SIZE, "%d\n", state);
+        h1940bt_enable(!blocked);
+        return 0;
 }
-static ssize_t h1940bt_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+static const struct rfkill_ops h1940bt_rfkill_ops = {
-{
+        .set_block = h1940bt_set_block,
-        int new_state;
+};
-        char *endp;
-        new_state = simple_strtoul(buf, &endp, 0);
-        if (*endp && !isspace(*endp))
-                return -EINVAL;
-        h1940bt_enable(new_state);
-        return count;
-}
-static DEVICE_ATTR(enable, 0644,
-                h1940bt_show,
-                h1940bt_store);
 static int __init h1940bt_probe(struct platform_device *pdev)
 {
+        struct rfkill *rfk;
+        int ret = 0;
        /* Configures BT serial port GPIOs */
        s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
        s3c2410_gpio_pullup(S3C2410_GPH(0), 1);
@@ -98,21 +71,44 @@ static int __init h1940bt_probe(struct platform_device *pdev)
        s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0);
        s3c2410_gpio_pullup(S3C2410_GPH(3), 1);
-#ifdef CONFIG_LEDS_H1940
-        led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger);
-#endif
-        /* disable BT by default */
+        rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH,
-        h1940bt_enable(0);
+                        &h1940bt_rfkill_ops, NULL);
+        if (!rfk) {
+                ret = -ENOMEM;
+                goto err_rfk_alloc;
+        }
+        rfkill_set_led_trigger_name(rfk, "h1940-bluetooth");
+        ret = rfkill_register(rfk);
+        if (ret)
+                goto err_rfkill;
+        platform_set_drvdata(pdev, rfk);
+        return 0;
-        return device_create_file(&pdev->dev, &dev_attr_enable);
+err_rfkill:
+        rfkill_destroy(rfk);
+err_rfk_alloc:
+        return ret;
 }
 static int h1940bt_remove(struct platform_device *pdev)
 {
-#ifdef CONFIG_LEDS_H1940
+        struct rfkill *rfk = platform_get_drvdata(pdev);
-        led_trigger_unregister_simple(bt_led_trigger);
-#endif
+        platform_set_drvdata(pdev, NULL);
+        if (rfk) {
+                rfkill_unregister(rfk);
+                rfkill_destroy(rfk);
+        }
+        rfk = NULL;
+        h1940bt_enable(0);
        return 0;
 }
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h b/arch/arm/mach-s3c2410/include/mach/bast-cpld.h
index 20493b048360..bee2a7a932a0 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h
+++ b/arch/arm/mach-s3c2410/include/mach/bast-cpld.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/bast-cpld.h
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * BAST - CPLD control constants
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-irq.h b/arch/arm/mach-s3c2410/include/mach/bast-irq.h
index 501c202b53cf..cac428c42e7f 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-irq.h
+++ b/arch/arm/mach-s3c2410/include/mach/bast-irq.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/bast-irq.h
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * Machine BAST - IRQ Number definitions
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-map.h b/arch/arm/mach-s3c2410/include/mach/bast-map.h
index c2c5baf07345..6e7dc9d0cf0e 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-map.h
+++ b/arch/arm/mach-s3c2410/include/mach/bast-map.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/bast-map.h
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * Machine BAST - Memory map definitions
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h b/arch/arm/mach-s3c2410/include/mach/bast-pmu.h
index 61684cb8ce59..4c38b39b741d 100644
--- a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h
+++ b/arch/arm/mach-s3c2410/include/mach/bast-pmu.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/bast-pmu.h
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      Vincent Sanders <vince@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index 92e2687009ea..08ac5f96c012 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/dma.h
 *
- * Copyright (C) 2003,2004,2006 Simtec Electronics
+ * Copyright (C) 2003-2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * Samsung S3C24XX DMA support
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
index 801dff13858d..035a493952db 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
 *
- * Copyright (c) 2003,2009 Simtec Electronics
+ * Copyright (c) 2003-2009 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2410 - hardware
diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-map.h b/arch/arm/mach-s3c2410/include/mach/osiris-map.h
index 639eff523d4e..17380f848428 100644
--- a/arch/arm/mach-s3c2410/include/mach/osiris-map.h
+++ b/arch/arm/mach-s3c2410/include/mach/osiris-map.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/osiris-map.h
 *
- * (c) 2005 Simtec Electronics
+ * Copyright 2005 Simtec Electronics
 *      http://www.simtec.co.uk/products/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
index 2a5d90e957fb..9a0d169be137 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h
@@ -1,7 +1,7 @@
 /* arch/arm/mach-s3c2410/include/mach/regs-clock.h
 *
- * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
- *                    http://armlinux.simtec.co.uk/
+ *      http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index f6e8eec879c8..ebc85c6dadbf 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -1,7 +1,7 @@
 /* arch/arm/mach-s3c2410/include/mach/regs-gpio.h
 *
- * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk>
- *                         http://www.simtec.co.uk/products/SWLINUX/
+ *      http://www.simtec.co.uk/products/SWLINUX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-power.h b/arch/arm/mach-s3c2410/include/mach/regs-power.h
index 2d36353f57d7..4932b87bdf3d 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-power.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-power.h
@@ -1,7 +1,7 @@
 /* arch/arm/mach-s3c2410/include/mach/regs-power.h
 *
- * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
- *                    http://armlinux.simtec.co.uk/
+ *      http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h
index c9432103750d..72f756c5e504 100644
--- a/arch/arm/mach-s3c2410/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h
@@ -1,7 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/uncompress.h
 *
- * Copyright (c) 2003, 2007 Simtec Electronics
+ * Copyright (c) 2003-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h b/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
index f53f85b4ad8b..47add133b8ee 100644
--- a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
+++ b/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * Machine VR1000 - IRQ Number definitions
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 647c9adb018f..4c79ac8a6c33 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/mach-bast.c
 *
- * Copyright (c) 2003-2005,2008 Simtec Electronics
+ * Copyright 2003-2008 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.simtec.co.uk/products/EB2410ITX/
@@ -61,11 +61,12 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
+#include <plat/audio-simtec.h>
 #include "usb-simtec.h"
 #include "nor-simtec.h"
-#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
+#define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
 /* macros for virtual address mods for the io space entries */
 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
@@ -247,7 +248,7 @@ static int chip0_map[] = { 1 };
 static int chip1_map[] = { 2 };
 static int chip2_map[] = { 3 };
-static struct mtd_partition bast_default_nand_part[] = {
+static struct mtd_partition __initdata bast_default_nand_part[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = SZ_16K,
@@ -273,7 +274,7 @@ static struct mtd_partition bast_default_nand_part[] = {
 * socket.
 */
-static struct s3c2410_nand_set bast_nand_sets[] = {
+static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
        [0] = {
                .name           = "SmartMedia",
                .nr_chips       = 1,
@@ -323,7 +324,7 @@ static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
        __raw_writeb(tmp, BAST_VA_CTRL2);
 }
-static struct s3c2410_platform_nand bast_nand_info = {
+static struct s3c2410_platform_nand __initdata bast_nand_info = {
        .tacls          = 30,
        .twrph0         = 60,
        .twrph1         = 60,
@@ -608,6 +609,11 @@ static struct s3c_cpufreq_board __initdata bast_cpufreq = {
        .need_io        = 1,
 };
+static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
+        .have_mic       = 1,
+        .have_lout      = 1,
+};
 static void __init bast_map_io(void)
 {
        /* initialise the clocks */
@@ -625,7 +631,6 @@ static void __init bast_map_io(void)
        s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
-        s3c_device_nand.dev.platform_data = &bast_nand_info;
        s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
        s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
@@ -639,6 +644,7 @@ static void __init bast_init(void)
        sysdev_register(&bast_pm_sysdev);
        s3c_i2c0_set_platdata(&bast_i2c_info);
+        s3c_nand_set_platdata(&bast_nand_info);
        s3c24xx_fb_set_platdata(&bast_fb_info);
        platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
@@ -647,6 +653,7 @@ static void __init bast_init(void)
        usb_simtec_init();
        nor_simtec_init();
+        simtec_audio_add(NULL, true, &bast_audio);
        s3c_cpufreq_setboard(&bast_cpufreq);
 }
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index d9cd5ddecf4a..49053254c98d 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -21,6 +21,11 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/pwm_backlight.h>
+#include <video/platform_lcd.h>
+#include <linux/mmc/host.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,9 +37,12 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <mach/gpio-fns.h>
+#include <mach/gpio-nrs.h>
 #include <mach/h1940.h>
 #include <mach/h1940-latch.h>
 #include <mach/fb.h>
@@ -46,6 +54,7 @@
 #include <plat/cpu.h>
 #include <plat/pll.h>
 #include <plat/pm.h>
+#include <plat/mci.h>
 static struct map_desc h1940_iodesc[] __initdata = {
        [0] = {
@@ -171,16 +180,90 @@ static struct s3c2410fb_mach_info h1940_fb_info __initdata = {
        .gpdup_mask=    0xffffffff,
 };
-static struct platform_device s3c_device_leds = {
+static struct platform_device h1940_device_leds = {
        .name             = "h1940-leds",
        .id               = -1,
 };
-static struct platform_device s3c_device_bluetooth = {
+static struct platform_device h1940_device_bluetooth = {
        .name             = "h1940-bt",
        .id               = -1,
 };
+static struct s3c24xx_mci_pdata h1940_mmc_cfg = {
+        .gpio_detect   = S3C2410_GPF(5),
+        .gpio_wprotect = S3C2410_GPH(8),
+        .set_power     = NULL,
+        .ocr_avail     = MMC_VDD_32_33,
+};
+static int h1940_backlight_init(struct device *dev)
+{
+        gpio_request(S3C2410_GPB(0), "Backlight");
+        s3c2410_gpio_setpin(S3C2410_GPB(0), 0);
+        s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
+        s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
+        return 0;
+}
+static void h1940_backlight_exit(struct device *dev)
+{
+        s3c2410_gpio_cfgpin(S3C2410_GPB(0), 1/*S3C2410_GPB0_OUTP*/);
+}
+static struct platform_pwm_backlight_data backlight_data = {
+        .pwm_id         = 0,
+        .max_brightness = 100,
+        .dft_brightness = 50,
+        /* tcnt = 0x31 */
+        .pwm_period_ns  = 36296,
+        .init           = h1940_backlight_init,
+        .exit           = h1940_backlight_exit,
+};
+static struct platform_device h1940_backlight = {
+        .name = "pwm-backlight",
+        .dev  = {
+                .parent = &s3c_device_timer[0].dev,
+                .platform_data = &backlight_data,
+        },
+        .id   = -1,
+};
+static void h1940_lcd_power_set(struct plat_lcd_data *pd,
+                                        unsigned int power)
+{
+        int value;
+        if (!power) {
+                /* set to 3ec */
+                s3c2410_gpio_setpin(S3C2410_GPC(0), 0);
+                /* wait for 3ac */
+                do {
+                        value = s3c2410_gpio_getpin(S3C2410_GPC(6));
+                } while (value);
+                /* set to 38c */
+                s3c2410_gpio_setpin(S3C2410_GPC(5), 0);
+        } else {
+                /* Set to 3ac */
+                s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
+                /* Set to 3ad */
+                s3c2410_gpio_setpin(S3C2410_GPC(0), 1);
+        }
+}
+static struct plat_lcd_data h1940_lcd_power_data = {
+        .set_power      = h1940_lcd_power_set,
+};
+static struct platform_device h1940_lcd_powerdev = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s3c_device_lcd.dev,
+        .dev.platform_data      = &h1940_lcd_power_data,
+};
 static struct platform_device *h1940_devices[] __initdata = {
        &s3c_device_usb,
        &s3c_device_lcd,
@@ -188,8 +271,13 @@ static struct platform_device *h1940_devices[] __initdata = {
        &s3c_device_i2c0,
        &s3c_device_iis,
        &s3c_device_usbgadget,
-        &s3c_device_leds,
+        &h1940_device_leds,
-        &s3c_device_bluetooth,
+        &h1940_device_bluetooth,
+        &s3c_device_sdi,
+        &s3c_device_rtc,
+        &s3c_device_timer[0],
+        &h1940_backlight,
+        &h1940_lcd_powerdev,
 };
 static void __init h1940_map_io(void)
@@ -219,6 +307,8 @@ static void __init h1940_init(void)
        s3c24xx_udc_set_platdata(&h1940_udc_cfg);
        s3c_i2c0_set_platdata(NULL);
+        s3c_device_sdi.dev.platform_data = &h1940_mmc_cfg;
        /* Turn off suspend on both USB ports, and switch the
         * selectable USB port to USB device mode. */
@@ -231,6 +321,11 @@ static void __init h1940_init(void)
              | (0x03 << S3C24XX_PLLCON_SDIVSHIFT);
        writel(tmp, S3C2410_UPLLCON);
+        gpio_request(S3C2410_GPC(0), "LCD power");
+        gpio_request(S3C2410_GPC(5), "LCD power");
+        gpio_request(S3C2410_GPC(6), "LCD power");
        platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices));
 }
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 0f6ed61af415..0405712c2263 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -338,7 +338,7 @@ static struct platform_device *n35_devices[] __initdata = {
        &n35_button_device,
 };
-static struct s3c2410_platform_i2c n30_i2ccfg = {
+static struct s3c2410_platform_i2c __initdata n30_i2ccfg = {
        .flags          = 0,
        .slave_addr     = 0x10,
        .frequency      = 10*1000,
@@ -500,8 +500,8 @@ static void __init n30_init_irq(void)
 static void __init n30_init(void)
 {
        s3c24xx_fb_set_platdata(&n30_fb_info);
-        s3c_device_i2c0.dev.platform_data = &n30_i2ccfg;
        s3c24xx_udc_set_platdata(&n30_udc_cfg);
+        s3c_i2c0_set_platdata(&n30_i2ccfg);
        /* Turn off suspend on both USB ports, and switch the
         * selectable USB port to USB device mode. */
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 2cc9849eb448..ab092bcda393 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -258,7 +258,7 @@ static struct platform_device *qt2410_devices[] __initdata = {
        &qt2410_led,
 };
-static struct mtd_partition qt2410_nand_part[] = {
+static struct mtd_partition __initdata qt2410_nand_part[] = {
        [0] = {
                .name   = "U-Boot",
                .size   = 0x30000,
@@ -286,7 +286,7 @@ static struct mtd_partition qt2410_nand_part[] = {
        },
 };
-static struct s3c2410_nand_set qt2410_nand_sets[] = {
+static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = {
        [0] = {
                .name           = "NAND",
                .nr_chips       = 1,
@@ -299,7 +299,7 @@ static struct s3c2410_nand_set qt2410_nand_sets[] = {
 * chips and beyond.
 */
-static struct s3c2410_platform_nand qt2410_nand_info = {
+static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
        .tacls          = 20,
        .twrph0         = 60,
        .twrph1         = 20,
@@ -331,7 +331,7 @@ static void __init qt2410_map_io(void)
 static void __init qt2410_machine_init(void)
 {
-        s3c_device_nand.dev.platform_data = &qt2410_nand_info;
+        s3c_nand_set_platdata(&qt2410_nand_info);
        switch (tft_type) {
        case 'p': /* production */
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 1628cc773a2c..0d61fb577170 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/mach-vr1000.c
 *
- * Copyright (c) 2003-2005,2008 Simtec Electronics
+ * Copyright (c) 2003-2008 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * Machine support for Thorcom VR1000 board. Designed for Thorcom by
@@ -49,6 +49,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/iic.h>
+#include <plat/audio-simtec.h>
 #include "usb-simtec.h"
 #include "nor-simtec.h"
@@ -393,6 +394,7 @@ static void __init vr1000_init(void)
                                ARRAY_SIZE(vr1000_i2c_devs));
        nor_simtec_init();
+        simtec_audio_add(NULL, true, NULL);
 }
 MACHINE_START(VR1000, "Thorcom-VR1000")
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c
index f178c2fd9d85..8338865e11c0 100644
--- a/arch/arm/mach-s3c2410/pll.c
+++ b/arch/arm/mach-s3c2410/pll.c
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/pll.c
 *
- * Copyright (c) 2006,2007 Simtec Electronics
+ * Copyright (c) 2006-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *      Vincent Sanders <vince@arm.linux.org.uk>
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c
index 50e25fc5f8ab..6b9d0d83a6f9 100644
--- a/arch/arm/mach-s3c2410/usb-simtec.c
+++ b/arch/arm/mach-s3c2410/usb-simtec.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2410/usb-simtec.c
 *
- * Copyright (c) 2004,2005 Simtec Electronics
+ * Copyright 2004-2005 Simtec Electronics
 *   Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.simtec.co.uk/products/EB2410ITX/
@@ -108,7 +108,7 @@ int usb_simtec_init(void)
 {
        int ret;
-        printk("USB Power Control, (c) 2004 Simtec Electronics\n");
+        printk("USB Power Control, Copyright 2004 Simtec Electronics\n");
        ret = gpio_request(S3C2410_GPB(4), "USB power control");
        if (ret < 0) {
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 8df506eac903..c9fa3fca486c 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -96,7 +96,7 @@ static struct s3c2410_uartcfg jive_uartcfgs[] = {
 * 0x017d0000-0x02bd0000 : cramfs B
 * 0x02bd0000-0x03fd0000 : yaffs
 */
-static struct mtd_partition jive_imageA_nand_part[] = {
+static struct mtd_partition __initdata jive_imageA_nand_part[] = {
 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
        /* Don't allow access to the bootloader from linux */
@@ -154,7 +154,7 @@ static struct mtd_partition jive_imageA_nand_part[] = {
        },
 };
-static struct mtd_partition jive_imageB_nand_part[] = {
+static struct mtd_partition __initdata jive_imageB_nand_part[] = {
 #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
        /* Don't allow access to the bootloader from linux */
@@ -213,7 +213,7 @@ static struct mtd_partition jive_imageB_nand_part[] = {
        },
 };
-static struct s3c2410_nand_set jive_nand_sets[] = {
+static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
        [0] = {
                .name           = "flash",
                .nr_chips       = 1,
@@ -222,7 +222,7 @@ static struct s3c2410_nand_set jive_nand_sets[] = {
        },
 };
-static struct s3c2410_platform_nand jive_nand_info = {
+static struct s3c2410_platform_nand __initdata jive_nand_info = {
        /* set taken from osiris nand timings, possibly still conservative */
        .tacls          = 30,
        .twrph0         = 55,
@@ -631,7 +631,8 @@ static void __init jive_machine_init(void)
        s3c_pm_init();
-        s3c_device_nand.dev.platform_data = &jive_nand_info;
+        /** TODO - check that this is after the cmdline option! */
+        s3c_nand_set_platdata(&jive_nand_info);
        /* initialise the spi */
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index 11e8ad49fc7b..a6ba591b26bb 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -76,7 +76,7 @@ static struct s3c2410_uartcfg vstms_uartcfgs[] __initdata = {
        }
 };
-static struct mtd_partition vstms_nand_part[] = {
+static struct mtd_partition __initdata vstms_nand_part[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = 0x7C000,
@@ -99,7 +99,7 @@ static struct mtd_partition vstms_nand_part[] = {
        },
 };
-static struct s3c2410_nand_set vstms_nand_sets[] = {
+static struct s3c2410_nand_set __initdata vstms_nand_sets[] = {
        [0] = {
                .name           = "NAND",
                .nr_chips       = 1,
@@ -112,7 +112,7 @@ static struct s3c2410_nand_set vstms_nand_sets[] = {
 * chips and beyond.
 */
-static struct s3c2410_platform_nand vstms_nand_info = {
+static struct s3c2410_platform_nand __initdata vstms_nand_info = {
        .tacls          = 20,
        .twrph0         = 60,
        .twrph1         = 20,
@@ -143,8 +143,6 @@ static void __init vstms_fixup(struct machine_desc *desc,
 static void __init vstms_map_io(void)
 {
-        s3c_device_nand.dev.platform_data = &vstms_nand_info;
        s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
@@ -153,6 +151,8 @@ static void __init vstms_map_io(void)
 static void __init vstms_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
+        s3c_nand_set_platdata(&vstms_nand_info);
        platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices));
 }
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index a8b69d77571b..cf10e14b7b49 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -53,6 +53,19 @@ config MACH_OSIRIS
          Say Y here if you are using the Simtec IM2440D20 module, also
          known as the Osiris.
+config MACH_OSIRIS_DVS
+        tristate "Simtec IM2440D20 (OSIRIS) Dynamic Voltage Scaling driver"
+        depends on MACH_OSIRIS
+        select TPS65010
+        help
+          Say Y/M here if you want to have dynamic voltage scaling support
+          on the Simtec IM2440D20 (OSIRIS) module via the TPS65011.
+          The DVS driver alters the voltage supplied to the ARM core
+          depending on the frequency it is running at. The driver itself
+          does not do any of the frequency alteration, which is left up
+          to the cpufreq driver.
 config MACH_RX3715
        bool "HP iPAQ rx3715"
        select CPU_S3C2440
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
index bfadcf684a2a..5f3224531885 100644
--- a/arch/arm/mach-s3c2440/Makefile
+++ b/arch/arm/mach-s3c2440/Makefile
@@ -23,3 +23,7 @@ obj-$(CONFIG_ARCH_S3C2440)	+= mach-smdk2440.o
 obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
 obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
 obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o
+# extra machine support
+obj-$(CONFIG_MACH_OSIRIS_DVS)   += mach-osiris-dvs.o
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index 63c5ab65727f..0c049b95c378 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/irq.c
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 68f3870991bf..62a4c3eba97f 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/mach-anubis.c
 *
- * Copyright (c) 2003-2005,2008 Simtec Electronics
+ * Copyright 2003-2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
@@ -53,8 +53,9 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/audio-simtec.h>
-#define COPYRIGHT ", (c) 2005 Simtec Electronics"
+#define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
 static struct map_desc anubis_iodesc[] __initdata = {
  /* ISA IO areas */
@@ -138,7 +139,7 @@ static int external_map[]   = { 2 };
 static int chip0_map[]      = { 0 };
 static int chip1_map[]      = { 1 };
-static struct mtd_partition anubis_default_nand_part[] = {
+static struct mtd_partition __initdata anubis_default_nand_part[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = SZ_16K,
@@ -161,7 +162,7 @@ static struct mtd_partition anubis_default_nand_part[] = {
        }
 };
-static struct mtd_partition anubis_default_nand_part_large[] = {
+static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = SZ_128K,
@@ -191,7 +192,7 @@ static struct mtd_partition anubis_default_nand_part_large[] = {
 * socket.
 */
-static struct s3c2410_nand_set anubis_nand_sets[] = {
+static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
        [1] = {
                .name           = "External",
                .nr_chips       = 1,
@@ -233,7 +234,7 @@ static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
        __raw_writeb(tmp, ANUBIS_VA_CTRL1);
 }
-static struct s3c2410_platform_nand anubis_nand_info = {
+static struct s3c2410_platform_nand __initdata anubis_nand_info = {
        .tacls          = 25,
        .twrph0         = 55,
        .twrph1         = 40,
@@ -437,6 +438,17 @@ static struct i2c_board_info anubis_i2c_devs[] __initdata = {
        }
 };
+/* Audio setup */
+static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
+        .have_mic       = 1,
+        .have_lout      = 1,
+        .output_cdclk   = 1,
+        .use_mpllin     = 1,
+        .amp_gpio       = S3C2410_GPB(2),
+        .amp_gain[0]    = S3C2410_GPD(10),
+        .amp_gain[1]    = S3C2410_GPD(11),
+};
 static void __init anubis_map_io(void)
 {
        /* initialise the clocks */
@@ -454,8 +466,6 @@ static void __init anubis_map_io(void)
        s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
-        s3c_device_nand.dev.platform_data = &anubis_nand_info;
        s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
@@ -476,6 +486,9 @@ static void __init anubis_map_io(void)
 static void __init anubis_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
+        s3c_nand_set_platdata(&anubis_nand_info);
+        simtec_audio_add(NULL, false, &anubis_audio);
        platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
        i2c_register_board_info(0, anubis_i2c_devs,
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index dfc7010935da..aa69290e04c6 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -96,7 +96,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
 /* NAND Flash on AT2440EVB board */
-static struct mtd_partition at2440evb_default_nand_part[] = {
+static struct mtd_partition __initdata at2440evb_default_nand_part[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = SZ_256K,
@@ -114,7 +114,7 @@ static struct mtd_partition at2440evb_default_nand_part[] = {
        },
 };
-static struct s3c2410_nand_set at2440evb_nand_sets[] = {
+static struct s3c2410_nand_set __initdata at2440evb_nand_sets[] = {
        [0] = {
                .name           = "nand",
                .nr_chips       = 1,
@@ -123,7 +123,7 @@ static struct s3c2410_nand_set at2440evb_nand_sets[] = {
        },
 };
-static struct s3c2410_platform_nand at2440evb_nand_info = {
+static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
        .tacls          = 25,
        .twrph0         = 55,
        .twrph1         = 40,
@@ -216,8 +216,6 @@ static struct platform_device *at2440evb_devices[] __initdata = {
 static void __init at2440evb_map_io(void)
 {
-        s3c_device_nand.dev.platform_data = &at2440evb_nand_info;
-        s3c_device_sdi.name = "s3c2440-sdi";
        s3c_device_sdi.dev.platform_data = &at2440evb_mci_pdata;
        s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
@@ -228,6 +226,7 @@ static void __init at2440evb_map_io(void)
 static void __init at2440evb_init(void)
 {
        s3c24xx_fb_set_platdata(&at2440evb_fb_info);
+        s3c_nand_set_platdata(&at2440evb_nand_info);
        s3c_i2c0_set_platdata(NULL);
        platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index 1c3382fefdd2..547d4fc99131 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -532,7 +532,6 @@ static void __init mini2440_map_io(void)
        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
-        s3c_device_nand.dev.platform_data = &mini2440_nand_info;
        s3c_device_sdi.dev.platform_data = &mini2440_mmc_cfg;
 }
@@ -677,8 +676,11 @@ static void __init mini2440_init(void)
                printk("\n");
                s3c24xx_fb_set_platdata(&mini2440_fb_info);
        }
        s3c24xx_udc_set_platdata(&mini2440_udc_cfg);
+        s3c_nand_set_platdata(&mini2440_nand_info);
        s3c_i2c0_set_platdata(NULL);
        i2c_register_board_info(0, mini2440_i2c_devs,
                                ARRAY_SIZE(mini2440_i2c_devs));
diff --git a/arch/arm/mach-s3c2440/mach-osiris-dvs.c b/arch/arm/mach-s3c2440/mach-osiris-dvs.c
new file mode 100644
index 000000000000..ad2792dfbee1
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-osiris-dvs.c
@@ -0,0 +1,194 @@
+/* linux/arch/arm/mach-s3c2440/mach-osiris-dvs.c
+ *
+ * Copyright (c) 2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Simtec Osiris Dynamic Voltage Scaling support.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/cpufreq.h>
+#include <linux/gpio.h>
+#include <linux/i2c/tps65010.h>
+#include <plat/cpu-freq.h>
+#define OSIRIS_GPIO_DVS S3C2410_GPB(5)
+static bool dvs_en;
+static void osiris_dvs_tps_setdvs(bool on)
+{
+        unsigned vregs1 = 0, vdcdc2 = 0;
+        if (!on) {
+                vdcdc2 = TPS_VCORE_DISCH | TPS_LP_COREOFF;
+                vregs1 = TPS_LDO1_OFF;  /* turn off in low-power mode */
+        }
+        dvs_en = on;
+        vdcdc2 |= TPS_VCORE_1_3V | TPS_VCORE_LP_1_0V;
+        vregs1 |= TPS_LDO2_ENABLE | TPS_LDO1_ENABLE;
+        tps65010_config_vregs1(vregs1);
+        tps65010_config_vdcdc2(vdcdc2);
+}
+static bool is_dvs(struct s3c_freq *f)
+{
+        /* at the moment, we assume ARMCLK = HCLK => DVS */
+        return f->armclk == f->hclk;
+}
+/* keep track of current state */
+static bool cur_dvs = false;
+static int osiris_dvs_notify(struct notifier_block *nb,
+                              unsigned long val, void *data)
+{
+        struct cpufreq_freqs *cf = data;
+        struct s3c_cpufreq_freqs *freqs = to_s3c_cpufreq(cf);
+        bool old_dvs = is_dvs(&freqs->old);
+        bool new_dvs = is_dvs(&freqs->new);
+        int ret = 0;
+        if (!dvs_en)
+                return 0;
+        printk(KERN_DEBUG "%s: old %ld,%ld new %ld,%ld\n", __func__,
+               freqs->old.armclk, freqs->old.hclk,
+               freqs->new.armclk, freqs->new.hclk);
+        switch (val) {
+        case CPUFREQ_PRECHANGE:
+                if (old_dvs & !new_dvs ||
+                    cur_dvs & !new_dvs) {
+                        pr_debug("%s: exiting dvs\n", __func__);
+                        cur_dvs = false;
+                        gpio_set_value(OSIRIS_GPIO_DVS, 1);
+                }
+                break;
+        case CPUFREQ_POSTCHANGE:
+                if (!old_dvs & new_dvs ||
+                    !cur_dvs & new_dvs) {
+                        pr_debug("entering dvs\n");
+                        cur_dvs = true;
+                        gpio_set_value(OSIRIS_GPIO_DVS, 0);
+                }
+                break;
+        }
+        return ret;
+}
+static struct notifier_block osiris_dvs_nb = {
+        .notifier_call  = osiris_dvs_notify,
+};
+static int __devinit osiris_dvs_probe(struct platform_device *pdev)
+{
+        int ret;
+        dev_info(&pdev->dev, "initialising\n");
+        ret = gpio_request(OSIRIS_GPIO_DVS, "osiris-dvs");
+        if (ret) {
+                dev_err(&pdev->dev, "cannot claim gpio\n");
+                goto err_nogpio;
+        }
+        /* start with dvs disabled */
+        gpio_direction_output(OSIRIS_GPIO_DVS, 1);
+        ret = cpufreq_register_notifier(&osiris_dvs_nb,
+                                        CPUFREQ_TRANSITION_NOTIFIER);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register with cpufreq\n");
+                goto err_nofreq;
+        }
+        osiris_dvs_tps_setdvs(true);
+        return 0;
+err_nofreq:
+        gpio_free(OSIRIS_GPIO_DVS);
+err_nogpio:
+        return ret;
+}
+static int __devexit osiris_dvs_remove(struct platform_device *pdev)
+{
+        dev_info(&pdev->dev, "exiting\n");
+        /* disable any current dvs */
+        gpio_set_value(OSIRIS_GPIO_DVS, 1);
+        osiris_dvs_tps_setdvs(false);
+        cpufreq_unregister_notifier(&osiris_dvs_nb,
+                                    CPUFREQ_TRANSITION_NOTIFIER);
+        gpio_free(OSIRIS_GPIO_DVS);
+        return 0;
+}
+/* the CONFIG_PM block is so small, it isn't worth actaully compiling it
+ * out if the configuration isn't set. */
+static int osiris_dvs_suspend(struct device *dev)
+{
+        gpio_set_value(OSIRIS_GPIO_DVS, 1);
+        osiris_dvs_tps_setdvs(false);
+        cur_dvs = false;
+        return 0;
+}
+static int osiris_dvs_resume(struct device *dev)
+{
+        osiris_dvs_tps_setdvs(true);
+        return 0;
+}
+static const struct dev_pm_ops osiris_dvs_pm = {
+        .suspend        = osiris_dvs_suspend,
+        .resume         = osiris_dvs_resume,
+};
+static struct platform_driver osiris_dvs_driver = {
+        .probe          = osiris_dvs_probe,
+        .remove         = __devexit_p(osiris_dvs_remove),
+        .driver         = {
+                .name   = "osiris-dvs",
+                .owner  = THIS_MODULE,
+                .pm     = &osiris_dvs_pm,
+        },
+};
+static int __init osiris_dvs_init(void)
+{
+        return platform_driver_register(&osiris_dvs_driver);
+}
+static void __exit osiris_dvs_exit(void)
+{
+        platform_driver_unregister(&osiris_dvs_driver);
+}
+module_init(osiris_dvs_init);
+module_exit(osiris_dvs_exit);
+MODULE_DESCRIPTION("Simtec OSIRIS DVS support");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:osiris-dvs");
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 2105a41281a4..015dfb2a80da 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
 *
- * Copyright (c) 2005,2008 Simtec Electronics
+ * Copyright (c) 2005-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
@@ -23,6 +23,8 @@
 #include <linux/i2c.h>
 #include <linux/io.h>
+#include <linux/i2c/tps65010.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -148,7 +150,7 @@ static int external_map[]   = { 2 };
 static int chip0_map[]      = { 0 };
 static int chip1_map[]      = { 1 };
-static struct mtd_partition osiris_default_nand_part[] = {
+static struct mtd_partition __initdata osiris_default_nand_part[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = SZ_16K,
@@ -171,7 +173,7 @@ static struct mtd_partition osiris_default_nand_part[] = {
        }
 };
-static struct mtd_partition osiris_default_nand_part_large[] = {
+static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
        [0] = {
                .name   = "Boot Agent",
                .size   = SZ_128K,
@@ -201,7 +203,7 @@ static struct mtd_partition osiris_default_nand_part_large[] = {
 * socket.
 */
-static struct s3c2410_nand_set osiris_nand_sets[] = {
+static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
        [1] = {
                .name           = "External",
                .nr_chips       = 1,
@@ -243,7 +245,7 @@ static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
        __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 }
-static struct s3c2410_platform_nand osiris_nand_info = {
+static struct s3c2410_platform_nand __initdata osiris_nand_info = {
        .tacls          = 25,
        .twrph0         = 60,
        .twrph1         = 60,
@@ -326,12 +328,44 @@ static struct sys_device osiris_pm_sysdev = {
        .cls            = &osiris_pm_sysclass,
 };
+/* Link for DVS driver to TPS65011 */
+static void osiris_tps_release(struct device *dev)
+{
+        /* static device, do not need to release anything */
+}
+static struct platform_device osiris_tps_device = {
+        .name   = "osiris-dvs",
+        .id     = -1,
+        .dev.release = osiris_tps_release,
+};
+static int osiris_tps_setup(struct i2c_client *client, void *context)
+{
+        osiris_tps_device.dev.parent = &client->dev;
+        return platform_device_register(&osiris_tps_device);
+}
+static int osiris_tps_remove(struct i2c_client *client, void *context)
+{
+        platform_device_unregister(&osiris_tps_device);
+        return 0;
+}
+static struct tps65010_board osiris_tps_board = {
+        .base           = -1,   /* GPIO can go anywhere at the moment */
+        .setup          = osiris_tps_setup,
+        .teardown       = osiris_tps_remove,
+};
 /* I2C devices fitted. */
 static struct i2c_board_info osiris_i2c_devs[] __initdata = {
        {
                I2C_BOARD_INFO("tps65011", 0x48),
                .irq    = IRQ_EINT20,
+                .platform_data = &osiris_tps_board,
        },
 };
@@ -377,8 +411,6 @@ static void __init osiris_map_io(void)
        s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
-        s3c_device_nand.dev.platform_data = &osiris_nand_info;
        s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
@@ -408,6 +440,7 @@ static void __init osiris_init(void)
        sysdev_register(&osiris_pm_sysdev);
        s3c_i2c0_set_platdata(NULL);
+        s3c_nand_set_platdata(&osiris_nand_info);
        s3c_cpufreq_setboard(&osiris_cpufreq);
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index bc8d8d1ebd1a..a952a13afb1f 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/mach-rx3715.c
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.handhelds.org/projects/rx3715.html
@@ -149,7 +149,7 @@ static struct s3c2410fb_mach_info rx3715_fb_info __initdata = {
        .gpdup_mask =   0xffffffff,
 };
-static struct mtd_partition rx3715_nand_part[] = {
+static struct mtd_partition __initdata rx3715_nand_part[] = {
        [0] = {
                .name           = "Whole Flash",
                .offset         = 0,
@@ -158,7 +158,7 @@ static struct mtd_partition rx3715_nand_part[] = {
        }
 };
-static struct s3c2410_nand_set rx3715_nand_sets[] = {
+static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = {
        [0] = {
                .name           = "Internal",
                .nr_chips       = 1,
@@ -167,7 +167,7 @@ static struct s3c2410_nand_set rx3715_nand_sets[] = {
        },
 };
-static struct s3c2410_platform_nand rx3715_nand_info = {
+static struct s3c2410_platform_nand __initdata rx3715_nand_info = {
        .tacls          = 25,
        .twrph0         = 50,
        .twrph1         = 15,
@@ -186,8 +186,6 @@ static struct platform_device *rx3715_devices[] __initdata = {
 static void __init rx3715_map_io(void)
 {
-        s3c_device_nand.dev.platform_data = &rx3715_nand_info;
        s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
        s3c24xx_init_clocks(16934000);
        s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
@@ -205,6 +203,7 @@ static void __init rx3715_init_machine(void)
 #endif
        s3c_pm_init();
+        s3c_nand_set_platdata(&rx3715_nand_info);
        s3c24xx_fb_set_platdata(&rx3715_fb_info);
        platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
 }
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index db6eafbd4d90..ec13e748ccc5 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c2440/mach-smdk2440.c
 *
- * Copyright (c) 2004,2005 Simtec Electronics
+ * Copyright (c) 2004-2005 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * http://www.fluff.org/ben/smdk2440/
diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c
index 0fb385bd9cd9..f76d6ff4aeb9 100644
--- a/arch/arm/mach-s3c2442/mach-gta02.c
+++ b/arch/arm/mach-s3c2442/mach-gta02.c
@@ -423,7 +423,7 @@ static struct i2c_board_info gta02_i2c_devs[] __initdata = {
        },
 };
-static struct s3c2410_nand_set gta02_nand_sets[] = {
+static struct s3c2410_nand_set __initdata gta02_nand_sets[] = {
        [0] = {
                /*
                 * This name is also hard-coded in the boot loaders, so
@@ -442,7 +442,7 @@ static struct s3c2410_nand_set gta02_nand_sets[] = {
 * data sheet (K5D2G13ACM-D075 MCP Memory).
 */
-static struct s3c2410_platform_nand gta02_nand_info = {
+static struct s3c2410_platform_nand __initdata gta02_nand_info = {
        .tacls          = 0,
        .twrph0         = 25,
        .twrph1         = 15,
@@ -621,9 +621,9 @@ static void __init gta02_machine_init(void)
 #endif
        s3c_device_usb.dev.platform_data = &gta02_usb_info;
-        s3c_device_nand.dev.platform_data = &gta02_nand_info;
        s3c24xx_udc_set_platdata(&gta02_udc_cfg);
+        s3c_nand_set_platdata(&gta02_nand_info);
        s3c_i2c0_set_platdata(NULL);
        i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs));
diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h
index 79e4d93ea2b6..d88c8b24fe34 100644
--- a/arch/arm/mach-s3c24a0/include/mach/map.h
+++ b/arch/arm/mach-s3c24a0/include/mach/map.h
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s3c24a0/include/mach/map.h
 *
- * Copyright 2003,2007  Simtec Electronics
+ * Copyright 2003-2007  Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/mach-s3c24a0/include/mach/regs-clock.h b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
index af2abd756c30..be0af518b488 100644
--- a/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
@@ -1,7 +1,7 @@
 /* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
 *
- * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
- *                    http://armlinux.simtec.co.uk/
+ *      http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h
index fc8b223bad4f..f3b48f841d84 100644
--- a/arch/arm/mach-s3c6400/include/mach/map.h
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -64,6 +64,9 @@
 #define S3C64XX_PA_USBHOST      (0x74300000)
+#define S3C64XX_PA_USB_HSPHY    (0x7C100000)
+#define S3C64XX_VA_USB_HSPHY    S3C_ADDR_CPU(0x00200000)
 /* place VICs close together */
 #define S3C_VA_VIC0             (S3C_VA_IRQ + 0x00)
 #define S3C_VA_VIC1             (S3C_VA_IRQ + 0x10000)
@@ -79,5 +82,6 @@
 #define S3C_PA_FB               S3C64XX_PA_FB
 #define S3C_PA_USBHOST          S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
+#define S3C_VA_USB_HSPHY        S3C64XX_VA_USB_HSPHY
 #endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/regs-fb.h b/arch/arm/mach-s3c6400/include/mach/regs-fb.h
index 47019795ce06..f56611526c63 100644
--- a/arch/arm/mach-s3c6400/include/mach/regs-fb.h
+++ b/arch/arm/mach-s3c6400/include/mach/regs-fb.h
@@ -1,195 +1,30 @@
-/* arch/arm/mach-s3c6400/include/mach/regs-fb.h
+/*
- *
 * Copyright 2008 Openmoko, Inc.
 * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
+ * Copyright 2009 Samsung Electronics Co.
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C64XX - new-style framebuffer register definitions
 *
- * This is the register set for the new style framebuffer interface
+ * Pawel Osciak <p.osciak@samsung.com>
- * found from the S3C2443 onwards and specifically the S3C64XX series
+ * Based on plat-s3c/include/plat/regs-fb.h by Ben Dooks <ben@simtec.co.uk>
- * S3C6400 and S3C6410.
 *
- * The file contains the cpu specific items which change between whichever
+ * Framebuffer register definitions for Samsung S3C64xx.
- * architecture is selected. See <plat/regs-fb.h> for the core definitions
- * that are the same.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-/* include the core definitions here, in case we really do need to
+#ifndef __ASM_ARCH_MACH_REGS_FB_H
- * override them at a later date.
+#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
-*/
-#include <plat/regs-fb.h>
-#define S3C_FB_MAX_WIN (5)  /* number of hardware windows available. */
-#define VIDCON1_FSTATUS_EVEN    (1 << 15)
-/* Video timing controls */
-#define VIDTCON0                                (0x10)
-#define VIDTCON1                                (0x14)
-#define VIDTCON2                                (0x18)
-/* Window position controls */
-#define WINCON(_win)                            (0x20 + ((_win) * 4))
-/* OSD1 and OSD4 do not have register D */
-#define VIDOSD_A(_win)                          (0x40 + ((_win) * 16))
-#define VIDOSD_B(_win)                          (0x44 + ((_win) * 16))
-#define VIDOSD_C(_win)                          (0x48 + ((_win) * 16))
-#define VIDOSD_D(_win)                          (0x4C + ((_win) * 16))
-/* Video buffer addresses */
-#define VIDW_BUF_START(_buff)                   (0xA0 + ((_buff) * 8))
-#define VIDW_BUF_START1(_buff)                  (0xA4 + ((_buff) * 8))
-#define VIDW_BUF_END(_buff)                     (0xD0 + ((_buff) * 8))
-#define VIDW_BUF_END1(_buff)                    (0xD4 + ((_buff) * 8))
-#define VIDW_BUF_SIZE(_buff)                    (0x100 + ((_buff) * 4))
-#define VIDINTCON0                              (0x130)
-#define WxKEYCONy(_win, _con)                   ((0x140 + ((_win) * 8)) + ((_con) * 4))
-/* WINCONx */
-#define WINCONx_CSCWIDTH_MASK                   (0x3 << 26)
-#define WINCONx_CSCWIDTH_SHIFT                  (26)
-#define WINCONx_CSCWIDTH_WIDE                   (0x0 << 26)
-#define WINCONx_CSCWIDTH_NARROW                 (0x3 << 26)
-#define WINCONx_ENLOCAL                         (1 << 22)
-#define WINCONx_BUFSTATUS                       (1 << 21)
-#define WINCONx_BUFSEL                          (1 << 20)
-#define WINCONx_BUFAUTOEN                       (1 << 19)
-#define WINCONx_YCbCr                           (1 << 13)
-#define WINCON1_LOCALSEL_CAMIF                  (1 << 23)
-#define WINCON2_LOCALSEL_CAMIF                  (1 << 23)
-#define WINCON2_BLD_PIX                         (1 << 6)
-#define WINCON2_ALPHA_SEL                       (1 << 1)
-#define WINCON2_BPPMODE_MASK                    (0xf << 2)
-#define WINCON2_BPPMODE_SHIFT                   (2)
-#define WINCON2_BPPMODE_1BPP                    (0x0 << 2)
-#define WINCON2_BPPMODE_2BPP                    (0x1 << 2)
-#define WINCON2_BPPMODE_4BPP                    (0x2 << 2)
-#define WINCON2_BPPMODE_8BPP_1232               (0x4 << 2)
-#define WINCON2_BPPMODE_16BPP_565               (0x5 << 2)
-#define WINCON2_BPPMODE_16BPP_A1555             (0x6 << 2)
-#define WINCON2_BPPMODE_16BPP_I1555             (0x7 << 2)
-#define WINCON2_BPPMODE_18BPP_666               (0x8 << 2)
-#define WINCON2_BPPMODE_18BPP_A1665             (0x9 << 2)
-#define WINCON2_BPPMODE_19BPP_A1666             (0xa << 2)
-#define WINCON2_BPPMODE_24BPP_888               (0xb << 2)
-#define WINCON2_BPPMODE_24BPP_A1887             (0xc << 2)
-#define WINCON2_BPPMODE_25BPP_A1888             (0xd << 2)
-#define WINCON2_BPPMODE_28BPP_A4888             (0xd << 2)
-#define WINCON3_BLD_PIX                         (1 << 6)
-#define WINCON3_ALPHA_SEL                       (1 << 1)
-#define WINCON3_BPPMODE_MASK                    (0xf << 2)
-#define WINCON3_BPPMODE_SHIFT                   (2)
-#define WINCON3_BPPMODE_1BPP                    (0x0 << 2)
-#define WINCON3_BPPMODE_2BPP                    (0x1 << 2)
-#define WINCON3_BPPMODE_4BPP                    (0x2 << 2)
-#define WINCON3_BPPMODE_16BPP_565               (0x5 << 2)
-#define WINCON3_BPPMODE_16BPP_A1555             (0x6 << 2)
-#define WINCON3_BPPMODE_16BPP_I1555             (0x7 << 2)
-#define WINCON3_BPPMODE_18BPP_666               (0x8 << 2)
-#define WINCON3_BPPMODE_18BPP_A1665             (0x9 << 2)
-#define WINCON3_BPPMODE_19BPP_A1666             (0xa << 2)
-#define WINCON3_BPPMODE_24BPP_888               (0xb << 2)
-#define WINCON3_BPPMODE_24BPP_A1887             (0xc << 2)
-#define WINCON3_BPPMODE_25BPP_A1888             (0xd << 2)
-#define WINCON3_BPPMODE_28BPP_A4888             (0xd << 2)
-#define VIDINTCON0_FIFIOSEL_WINDOW2             (0x10 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW3             (0x20 << 5)
-#define VIDINTCON0_FIFIOSEL_WINDOW4             (0x40 << 5)
-#define DITHMODE                                (0x170)
-#define WINxMAP(_win)                           (0x180 + ((_win) * 4))
-#define DITHMODE_R_POS_MASK                     (0x3 << 5)
-#define DITHMODE_R_POS_SHIFT                    (5)
-#define DITHMODE_R_POS_8BIT                     (0x0 << 5)
-#define DITHMODE_R_POS_6BIT                     (0x1 << 5)
-#define DITHMODE_R_POS_5BIT                     (0x2 << 5)
-#define DITHMODE_G_POS_MASK                     (0x3 << 3)
-#define DITHMODE_G_POS_SHIFT                    (3)
-#define DITHMODE_G_POS_8BIT                     (0x0 << 3)
-#define DITHMODE_G_POS_6BIT                     (0x1 << 3)
-#define DITHMODE_G_POS_5BIT                     (0x2 << 3)
-#define DITHMODE_B_POS_MASK                     (0x3 << 1)
-#define DITHMODE_B_POS_SHIFT                    (1)
-#define DITHMODE_B_POS_8BIT                     (0x0 << 1)
-#define DITHMODE_B_POS_6BIT                     (0x1 << 1)
-#define DITHMODE_B_POS_5BIT                     (0x2 << 1)
-#define DITHMODE_DITH_EN                        (1 << 0)
+#include <plat/regs-fb-v4.h>
-#define WPALCON                                 (0x1A0)
-#define WPALCON_W4PAL_16BPP_A555                (1 << 8)
-#define WPALCON_W3PAL_16BPP_A555                (1 << 7)
-#define WPALCON_W2PAL_16BPP_A555                (1 << 6)
 /* Palette registers */
 #define WIN2_PAL(_entry)                        (0x300 + ((_entry) * 2))
 #define WIN3_PAL(_entry)                        (0x320 + ((_entry) * 2))
 #define WIN4_PAL(_entry)                        (0x340 + ((_entry) * 2))
 #define WIN0_PAL(_entry)                        (0x400 + ((_entry) * 4))
 #define WIN1_PAL(_entry)                        (0x800 + ((_entry) * 4))
-/* system specific implementation code for palette sizes, and other
- * information that changes depending on which architecture is being
- * compiled.
-*/
-/* return true if window _win has OSD register D */
-#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
-static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
-{
-        if (win < 2)
-                return 256;
-        if (win < 4)
-                return 16;
-        if (win == 4)
-                return 4;
-        BUG();  /* shouldn't get here */
-}
-static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
-{
-        /* all windows can do 1/2 bpp */
-        if ((bpp == 25 || bpp == 19) && win == 0)
-                return 0;       /* win 0 does not have 19 or 25bpp modes */
-        if (bpp == 4 && win == 4)
-                return 0;
-        if (bpp == 8 && (win >= 3))
-                return 0;       /* win 3/4 cannot do 8bpp in any mode */
-        return 1;
-}
 static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
 {
        switch (window) {
@@ -203,57 +38,4 @@ static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
        BUG();
 }
-static inline int s3c_fb_pal_is16(unsigned int window)
+#endif /* __ASM_ARCH_MACH_REGS_FB_H */
-{
-        return window > 1;
-}
-struct s3c_fb_palette {
-        struct fb_bitfield      r;
-        struct fb_bitfield      g;
-        struct fb_bitfield      b;
-        struct fb_bitfield      a;
-};
-static inline void s3c_fb_init_palette(unsigned int window,
-                                       struct s3c_fb_palette *palette)
-{
-        if (window < 2) {
-                /* Windows 0/1 are 8/8/8 or A/8/8/8 */
-                palette->r.offset = 16;
-                palette->r.length = 8;
-                palette->g.offset = 8;
-                palette->g.length = 8;
-                palette->b.offset = 0;
-                palette->b.length = 8;
-        } else {
-                /* currently we assume RGB 5/6/5 */
-                palette->r.offset = 11;
-                palette->r.length = 5;
-                palette->g.offset = 5;
-                palette->g.length = 6;
-                palette->b.offset = 0;
-                palette->b.length = 5;
-        }
-}
-/* Notes on per-window bpp settings
- *
- * Value        Win0     Win1     Win2     Win3     Win 4
- * 0000         1(P)     1(P)     1(P)     1(P)     1(P)
- * 0001         2(P)     2(P)     2(P)     2(P)     2(P)
- * 0010         4(P)     4(P)     4(P)     4(P)     -none-
- * 0011         8(P)     8(P)     -none-   -none-   -none-
- * 0100         -none-   8(A232)  8(A232)  -none-   -none-
- * 0101         16(565)  16(565)  16(565)  16(565)   16(565)
- * 0110         -none-   16(A555) 16(A555) 16(A555)  16(A555)
- * 0111         16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
- * 1000         18(666)  18(666)  18(666)  18(666)   18(666)
- * 1001         -none-   18(A665) 18(A665) 18(A665)  16(A665)
- * 1010         -none-   19(A666) 19(A666) 19(A666)  19(A666)
- * 1011         24(888)  24(888)  24(888)  24(888)   24(888)
- * 1100         -none-   24(A887) 24(A887) 24(A887)  24(A887)
- * 1101         -none-   25(A888) 25(A888) 25(A888)  25(A888)
- * 1110         -none-   -none-   -none-   -none-    -none-
- * 1111         -none-   -none-   -none-   -none-    -none-
-*/
diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c
index b42bdd0f2138..d876ee503671 100644
--- a/arch/arm/mach-s3c6400/s3c6400.c
+++ b/arch/arm/mach-s3c6400/s3c6400.c
@@ -45,6 +45,7 @@ void __init s3c6400_map_io(void)
        s3c6400_default_sdhci0();
        s3c6400_default_sdhci1();
+        s3c6400_default_sdhci2();
        /* the i2c devices are directly compatible with s3c2440 */
        s3c_i2c0_setname("s3c2440-i2c");
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c
index 9b67c663d9d8..522c08691952 100644
--- a/arch/arm/mach-s3c6410/cpu.c
+++ b/arch/arm/mach-s3c6410/cpu.c
@@ -58,6 +58,7 @@ void __init s3c6410_map_io(void)
        /* initialise device information early */
        s3c6410_default_sdhci0();
        s3c6410_default_sdhci1();
+        s3c6410_default_sdhci2();
        /* the i2c devices are directly compatible with s3c2440 */
        s3c_i2c0_setname("s3c2440-i2c");
diff --git a/arch/arm/mach-s3c6410/mach-hmt.c b/arch/arm/mach-s3c6410/mach-hmt.c
index c5741056193f..cdd4b5378552 100644
--- a/arch/arm/mach-s3c6410/mach-hmt.c
+++ b/arch/arm/mach-s3c6410/mach-hmt.c
@@ -250,7 +250,7 @@ static void __init hmt_machine_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
        s3c_fb_set_platdata(&hmt_lcd_pdata);
-        s3c_device_nand.dev.platform_data = &hmt_nand_info;
+        s3c_nand_set_platdata(&hmt_nand_info);
        gpio_request(S3C64XX_GPC(7), "usb power");
        gpio_direction_output(S3C64XX_GPC(7), 0);
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
index 9f1a21462620..480d297c1de2 100644
--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
+++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
@@ -25,6 +25,7 @@
 #include <linux/gpio.h>
 #include <linux/delay.h>
 #include <linux/smsc911x.h>
+#include <linux/regulator/fixed.h>
 #ifdef CONFIG_SMDK6410_WM1190_EV1
 #include <linux/mfd/wm8350/core.h>
@@ -184,6 +185,43 @@ static struct platform_device smdk6410_smsc911x = {
        },
 };
+#ifdef CONFIG_REGULATOR
+static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
+        {
+                /* WM8580 */
+                .supply = "PVDD",
+                .dev_name = "0-001b",
+        },
+        {
+                /* WM8580 */
+                .supply = "AVDD",
+                .dev_name = "0-001b",
+        },
+};
+static struct regulator_init_data smdk6410_b_pwr_5v_data = {
+        .constraints = {
+                .always_on = 1,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
+        .consumer_supplies = smdk6410_b_pwr_5v_consumers,
+};
+static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
+        .supply_name = "B_PWR_5V",
+        .microvolts = 5000000,
+        .init_data = &smdk6410_b_pwr_5v_data,
+};
+static struct platform_device smdk6410_b_pwr_5v = {
+        .name          = "reg-fixed-voltage",
+        .id            = -1,
+        .dev = {
+                .platform_data = &smdk6410_b_pwr_5v_pdata,
+        },
+};
+#endif
 static struct map_desc smdk6410_iodesc[] = {};
 static struct platform_device *smdk6410_devices[] __initdata = {
@@ -198,6 +236,10 @@ static struct platform_device *smdk6410_devices[] __initdata = {
        &s3c_device_fb,
        &s3c_device_usb,
        &s3c_device_usb_hsotg,
+#ifdef CONFIG_REGULATOR
+        &smdk6410_b_pwr_5v,
+#endif
        &smdk6410_lcd_powerdev,
        &smdk6410_smsc911x,
@@ -232,6 +274,14 @@ static struct regulator_init_data wm8350_dcdc3_data = {
 };
 /* USB, EXT, PCM, ADC/DAC, USB, MMC */
+static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
+        {
+                /* WM8580 */
+                .supply = "DVDD",
+                .dev_name = "0-001b",
+        },
+};
 static struct regulator_init_data wm8350_dcdc4_data = {
        .constraints = {
                .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
@@ -239,6 +289,8 @@ static struct regulator_init_data wm8350_dcdc4_data = {
                .max_uV = 3000000,
                .always_on = 1,
        },
+        .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
+        .consumer_supplies = wm8350_dcdc4_consumers,
 };
 /* ARM core */
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index b1a4ba504416..0dd2b8c6eabe 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -14,9 +14,23 @@ config CPU_S5PC100
        help
          Enable S5PC100 CPU support
+config S5PC100_SETUP_SDHCI
+        bool
+        select S5PC1XX_SETUP_SDHCI_GPIO
+        help
+          Internal helper functions for S5PC100 based SDHCI systems
 config MACH_SMDKC100
        bool "SMDKC100"
        select CPU_S5PC100
+        select S3C_DEV_FB
+        select S3C_DEV_I2C1
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
+        select S5PC1XX_SETUP_I2C0
        select S5PC1XX_SETUP_I2C1
+        select S5PC1XX_SETUP_FB_24BPP
+        select S5PC100_SETUP_SDHCI
        help
          Machine support for the Samsung SMDKC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index afc89b381d7a..809ff10f768f 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -13,5 +13,9 @@ obj-				:=
 obj-$(CONFIG_CPU_S5PC100)       += cpu.o
+# Helper and device support
+obj-$(CONFIG_S5PC100_SETUP_SDHCI)       += setup-sdhci.o
 # machine support
 obj-$(CONFIG_MACH_SMDKC100)     += mach-smdkc100.o
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index 0e718890da32..d79e7574a852 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -22,6 +22,8 @@
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
+#include <asm/proc-fns.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -32,6 +34,7 @@
 #include <plat/cpu-freq.h>
 #include <plat/regs-serial.h>
+#include <plat/regs-power.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
@@ -45,6 +48,23 @@
 static struct map_desc s5pc100_iodesc[] __initdata = {
 };
+static void s5pc100_idle(void)
+{
+        unsigned long tmp;
+        tmp = __raw_readl(S5PC100_PWR_CFG);
+        tmp &= ~S5PC100_PWRCFG_CFG_DEEP_IDLE;
+        tmp &= ~S5PC100_PWRCFG_CFG_WFI_MASK;
+        tmp |= S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE;
+        __raw_writel(tmp, S5PC100_PWR_CFG);
+        tmp = __raw_readl(S5PC100_OTHERS);
+        tmp |= S5PC100_PMU_INT_DISABLE;
+        __raw_writel(tmp, S5PC100_OTHERS);
+        cpu_do_idle();
+}
 /* s5pc100_map_io
 *
 * register the standard cpu IO areas
@@ -55,6 +75,13 @@ void __init s5pc100_map_io(void)
        iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
        /* initialise device information early */
+        s5pc100_default_sdhci0();
+        s5pc100_default_sdhci1();
+        s5pc100_default_sdhci2();
+        /* the i2c devices are directly compatible with s3c2440 */
+        s3c_i2c0_setname("s3c2440-i2c");
+        s3c_i2c1_setname("s3c2440-i2c");
 }
 void __init s5pc100_init_clocks(int xtal)
@@ -93,5 +120,7 @@ int __init s5pc100_init(void)
 {
        printk(KERN_DEBUG "S5PC100: Initialising architecture\n");
+        s5pc1xx_idle = s5pc100_idle;
        return sysdev_register(&s5pc100_sysdev);
 }
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index c74fc93d7d15..2c4cbe8ee6b7 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -18,40 +18,45 @@
 #define gpio_to_irq     __gpio_to_irq
 /* GPIO bank sizes */
-#define S5PC1XX_GPIO_A0_NR      (8)
+#define S5PC100_GPIO_A0_NR      (8)
-#define S5PC1XX_GPIO_A1_NR      (5)
+#define S5PC100_GPIO_A1_NR      (5)
-#define S5PC1XX_GPIO_B_NR       (8)
+#define S5PC100_GPIO_B_NR       (8)
-#define S5PC1XX_GPIO_C_NR       (5)
+#define S5PC100_GPIO_C_NR       (5)
-#define S5PC1XX_GPIO_D_NR       (7)
+#define S5PC100_GPIO_D_NR       (7)
-#define S5PC1XX_GPIO_E0_NR      (8)
+#define S5PC100_GPIO_E0_NR      (8)
-#define S5PC1XX_GPIO_E1_NR      (6)
+#define S5PC100_GPIO_E1_NR      (6)
-#define S5PC1XX_GPIO_F0_NR      (8)
+#define S5PC100_GPIO_F0_NR      (8)
-#define S5PC1XX_GPIO_F1_NR      (8)
+#define S5PC100_GPIO_F1_NR      (8)
-#define S5PC1XX_GPIO_F2_NR      (8)
+#define S5PC100_GPIO_F2_NR      (8)
-#define S5PC1XX_GPIO_F3_NR      (4)
+#define S5PC100_GPIO_F3_NR      (4)
-#define S5PC1XX_GPIO_G0_NR      (8)
+#define S5PC100_GPIO_G0_NR      (8)
-#define S5PC1XX_GPIO_G1_NR      (3)
+#define S5PC100_GPIO_G1_NR      (3)
-#define S5PC1XX_GPIO_G2_NR      (7)
+#define S5PC100_GPIO_G2_NR      (7)
-#define S5PC1XX_GPIO_G3_NR      (7)
+#define S5PC100_GPIO_G3_NR      (7)
-#define S5PC1XX_GPIO_H0_NR      (8)
+#define S5PC100_GPIO_H0_NR      (8)
-#define S5PC1XX_GPIO_H1_NR      (8)
+#define S5PC100_GPIO_H1_NR      (8)
-#define S5PC1XX_GPIO_H2_NR      (8)
+#define S5PC100_GPIO_H2_NR      (8)
-#define S5PC1XX_GPIO_H3_NR      (8)
+#define S5PC100_GPIO_H3_NR      (8)
-#define S5PC1XX_GPIO_I_NR       (8)
+#define S5PC100_GPIO_I_NR       (8)
-#define S5PC1XX_GPIO_J0_NR      (8)
+#define S5PC100_GPIO_J0_NR      (8)
-#define S5PC1XX_GPIO_J1_NR      (5)
+#define S5PC100_GPIO_J1_NR      (5)
-#define S5PC1XX_GPIO_J2_NR      (8)
+#define S5PC100_GPIO_J2_NR      (8)
-#define S5PC1XX_GPIO_J3_NR      (8)
+#define S5PC100_GPIO_J3_NR      (8)
-#define S5PC1XX_GPIO_J4_NR      (4)
+#define S5PC100_GPIO_J4_NR      (4)
-#define S5PC1XX_GPIO_K0_NR      (8)
+#define S5PC100_GPIO_K0_NR      (8)
-#define S5PC1XX_GPIO_K1_NR      (6)
+#define S5PC100_GPIO_K1_NR      (6)
-#define S5PC1XX_GPIO_K2_NR      (8)
+#define S5PC100_GPIO_K2_NR      (8)
-#define S5PC1XX_GPIO_K3_NR      (8)
+#define S5PC100_GPIO_K3_NR      (8)
-#define S5PC1XX_GPIO_MP00_NR    (8)
+#define S5PC100_GPIO_L0_NR      (8)
-#define S5PC1XX_GPIO_MP01_NR    (8)
+#define S5PC100_GPIO_L1_NR      (8)
-#define S5PC1XX_GPIO_MP02_NR    (8)
+#define S5PC100_GPIO_L2_NR      (8)
-#define S5PC1XX_GPIO_MP03_NR    (8)
+#define S5PC100_GPIO_L3_NR      (8)
-#define S5PC1XX_GPIO_MP04_NR    (5)
+#define S5PC100_GPIO_L4_NR      (8)
+#define S5PC100_GPIO_MP00_NR    (8)
+#define S5PC100_GPIO_MP01_NR    (8)
+#define S5PC100_GPIO_MP02_NR    (8)
+#define S5PC100_GPIO_MP03_NR    (8)
+#define S5PC100_GPIO_MP04_NR    (5)
 /* GPIO bank numbes */
@@ -64,83 +69,94 @@
        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
 enum s3c_gpio_number {
-        S5PC1XX_GPIO_A0_START   = 0,
+        S5PC100_GPIO_A0_START   = 0,
-        S5PC1XX_GPIO_A1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0),
+        S5PC100_GPIO_A1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A0),
-        S5PC1XX_GPIO_B_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1),
+        S5PC100_GPIO_B_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A1),
-        S5PC1XX_GPIO_C_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B),
+        S5PC100_GPIO_C_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_B),
-        S5PC1XX_GPIO_D_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C),
+        S5PC100_GPIO_D_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_C),
-        S5PC1XX_GPIO_E0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D),
+        S5PC100_GPIO_E0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_D),
-        S5PC1XX_GPIO_E1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E0),
+        S5PC100_GPIO_E1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E0),
-        S5PC1XX_GPIO_F0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E1),
+        S5PC100_GPIO_F0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E1),
-        S5PC1XX_GPIO_F1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F0),
+        S5PC100_GPIO_F1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F0),
-        S5PC1XX_GPIO_F2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F1),
+        S5PC100_GPIO_F2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F1),
-        S5PC1XX_GPIO_F3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F2),
+        S5PC100_GPIO_F3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F2),
-        S5PC1XX_GPIO_G0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F3),
+        S5PC100_GPIO_G0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F3),
-        S5PC1XX_GPIO_G1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G0),
+        S5PC100_GPIO_G1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G0),
-        S5PC1XX_GPIO_G2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G1),
+        S5PC100_GPIO_G2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G1),
-        S5PC1XX_GPIO_G3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G2),
+        S5PC100_GPIO_G3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G2),
-        S5PC1XX_GPIO_H0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G3),
+        S5PC100_GPIO_H0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G3),
-        S5PC1XX_GPIO_H1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H0),
+        S5PC100_GPIO_H1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H0),
-        S5PC1XX_GPIO_H2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H1),
+        S5PC100_GPIO_H2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H1),
-        S5PC1XX_GPIO_H3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H2),
+        S5PC100_GPIO_H3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H2),
-        S5PC1XX_GPIO_I_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H3),
+        S5PC100_GPIO_I_START    = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H3),
-        S5PC1XX_GPIO_J0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_I),
+        S5PC100_GPIO_J0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_I),
-        S5PC1XX_GPIO_J1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J0),
+        S5PC100_GPIO_J1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J0),
-        S5PC1XX_GPIO_J2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J1),
+        S5PC100_GPIO_J2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J1),
-        S5PC1XX_GPIO_J3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J2),
+        S5PC100_GPIO_J3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J2),
-        S5PC1XX_GPIO_J4_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J3),
+        S5PC100_GPIO_J4_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J3),
-        S5PC1XX_GPIO_K0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J4),
+        S5PC100_GPIO_K0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J4),
-        S5PC1XX_GPIO_K1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0),
+        S5PC100_GPIO_K1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K0),
-        S5PC1XX_GPIO_K2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1),
+        S5PC100_GPIO_K2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K1),
-        S5PC1XX_GPIO_K3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2),
+        S5PC100_GPIO_K3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K2),
-        S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3),
+        S5PC100_GPIO_L0_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K3),
-        S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00),
+        S5PC100_GPIO_L1_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L0),
-        S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01),
+        S5PC100_GPIO_L2_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L1),
-        S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02),
+        S5PC100_GPIO_L3_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L2),
-        S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03),
+        S5PC100_GPIO_L4_START   = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L3),
+        S5PC100_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L4),
+        S5PC100_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP00),
+        S5PC100_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP01),
+        S5PC100_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP02),
+        S5PC100_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP03),
+        S5PC100_GPIO_END        = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP04),
 };
-/* S5PC1XX GPIO number definitions. */
+/* S5PC100 GPIO number definitions. */
-#define S5PC1XX_GPA0(_nr)       (S5PC1XX_GPIO_A0_START + (_nr))
+#define S5PC100_GPA0(_nr)       (S5PC100_GPIO_A0_START + (_nr))
-#define S5PC1XX_GPA1(_nr)       (S5PC1XX_GPIO_A1_START + (_nr))
+#define S5PC100_GPA1(_nr)       (S5PC100_GPIO_A1_START + (_nr))
-#define S5PC1XX_GPB(_nr)        (S5PC1XX_GPIO_B_START + (_nr))
+#define S5PC100_GPB(_nr)        (S5PC100_GPIO_B_START + (_nr))
-#define S5PC1XX_GPC(_nr)        (S5PC1XX_GPIO_C_START + (_nr))
+#define S5PC100_GPC(_nr)        (S5PC100_GPIO_C_START + (_nr))
-#define S5PC1XX_GPD(_nr)        (S5PC1XX_GPIO_D_START + (_nr))
+#define S5PC100_GPD(_nr)        (S5PC100_GPIO_D_START + (_nr))
-#define S5PC1XX_GPE0(_nr)       (S5PC1XX_GPIO_E0_START + (_nr))
+#define S5PC100_GPE0(_nr)       (S5PC100_GPIO_E0_START + (_nr))
-#define S5PC1XX_GPE1(_nr)       (S5PC1XX_GPIO_E1_START + (_nr))
+#define S5PC100_GPE1(_nr)       (S5PC100_GPIO_E1_START + (_nr))
-#define S5PC1XX_GPF0(_nr)       (S5PC1XX_GPIO_F0_START + (_nr))
+#define S5PC100_GPF0(_nr)       (S5PC100_GPIO_F0_START + (_nr))
-#define S5PC1XX_GPF1(_nr)       (S5PC1XX_GPIO_F1_START + (_nr))
+#define S5PC100_GPF1(_nr)       (S5PC100_GPIO_F1_START + (_nr))
-#define S5PC1XX_GPF2(_nr)       (S5PC1XX_GPIO_F2_START + (_nr))
+#define S5PC100_GPF2(_nr)       (S5PC100_GPIO_F2_START + (_nr))
-#define S5PC1XX_GPF3(_nr)       (S5PC1XX_GPIO_F3_START + (_nr))
+#define S5PC100_GPF3(_nr)       (S5PC100_GPIO_F3_START + (_nr))
-#define S5PC1XX_GPG0(_nr)       (S5PC1XX_GPIO_G0_START + (_nr))
+#define S5PC100_GPG0(_nr)       (S5PC100_GPIO_G0_START + (_nr))
-#define S5PC1XX_GPG1(_nr)       (S5PC1XX_GPIO_G1_START + (_nr))
+#define S5PC100_GPG1(_nr)       (S5PC100_GPIO_G1_START + (_nr))
-#define S5PC1XX_GPG2(_nr)       (S5PC1XX_GPIO_G2_START + (_nr))
+#define S5PC100_GPG2(_nr)       (S5PC100_GPIO_G2_START + (_nr))
-#define S5PC1XX_GPG3(_nr)       (S5PC1XX_GPIO_G3_START + (_nr))
+#define S5PC100_GPG3(_nr)       (S5PC100_GPIO_G3_START + (_nr))
-#define S5PC1XX_GPH0(_nr)       (S5PC1XX_GPIO_H0_START + (_nr))
+#define S5PC100_GPH0(_nr)       (S5PC100_GPIO_H0_START + (_nr))
-#define S5PC1XX_GPH1(_nr)       (S5PC1XX_GPIO_H1_START + (_nr))
+#define S5PC100_GPH1(_nr)       (S5PC100_GPIO_H1_START + (_nr))
-#define S5PC1XX_GPH2(_nr)       (S5PC1XX_GPIO_H2_START + (_nr))
+#define S5PC100_GPH2(_nr)       (S5PC100_GPIO_H2_START + (_nr))
-#define S5PC1XX_GPH3(_nr)       (S5PC1XX_GPIO_H3_START + (_nr))
+#define S5PC100_GPH3(_nr)       (S5PC100_GPIO_H3_START + (_nr))
-#define S5PC1XX_GPI(_nr)        (S5PC1XX_GPIO_I_START + (_nr))
+#define S5PC100_GPI(_nr)        (S5PC100_GPIO_I_START + (_nr))
-#define S5PC1XX_GPJ0(_nr)       (S5PC1XX_GPIO_J0_START + (_nr))
+#define S5PC100_GPJ0(_nr)       (S5PC100_GPIO_J0_START + (_nr))
-#define S5PC1XX_GPJ1(_nr)       (S5PC1XX_GPIO_J1_START + (_nr))
+#define S5PC100_GPJ1(_nr)       (S5PC100_GPIO_J1_START + (_nr))
-#define S5PC1XX_GPJ2(_nr)       (S5PC1XX_GPIO_J2_START + (_nr))
+#define S5PC100_GPJ2(_nr)       (S5PC100_GPIO_J2_START + (_nr))
-#define S5PC1XX_GPJ3(_nr)       (S5PC1XX_GPIO_J3_START + (_nr))
+#define S5PC100_GPJ3(_nr)       (S5PC100_GPIO_J3_START + (_nr))
-#define S5PC1XX_GPJ4(_nr)       (S5PC1XX_GPIO_J4_START + (_nr))
+#define S5PC100_GPJ4(_nr)       (S5PC100_GPIO_J4_START + (_nr))
-#define S5PC1XX_GPK0(_nr)       (S5PC1XX_GPIO_K0_START + (_nr))
+#define S5PC100_GPK0(_nr)       (S5PC100_GPIO_K0_START + (_nr))
-#define S5PC1XX_GPK1(_nr)       (S5PC1XX_GPIO_K1_START + (_nr))
+#define S5PC100_GPK1(_nr)       (S5PC100_GPIO_K1_START + (_nr))
-#define S5PC1XX_GPK2(_nr)       (S5PC1XX_GPIO_K2_START + (_nr))
+#define S5PC100_GPK2(_nr)       (S5PC100_GPIO_K2_START + (_nr))
-#define S5PC1XX_GPK3(_nr)       (S5PC1XX_GPIO_K3_START + (_nr))
+#define S5PC100_GPK3(_nr)       (S5PC100_GPIO_K3_START + (_nr))
-#define S5PC1XX_MP00(_nr)       (S5PC1XX_GPIO_MP00_START + (_nr))
+#define S5PC100_GPL0(_nr)       (S5PC100_GPIO_L0_START + (_nr))
-#define S5PC1XX_MP01(_nr)       (S5PC1XX_GPIO_MP01_START + (_nr))
+#define S5PC100_GPL1(_nr)       (S5PC100_GPIO_L1_START + (_nr))
-#define S5PC1XX_MP02(_nr)       (S5PC1XX_GPIO_MP02_START + (_nr))
+#define S5PC100_GPL2(_nr)       (S5PC100_GPIO_L2_START + (_nr))
-#define S5PC1XX_MP03(_nr)       (S5PC1XX_GPIO_MP03_START + (_nr))
+#define S5PC100_GPL3(_nr)       (S5PC100_GPIO_L3_START + (_nr))
-#define S5PC1XX_MP04(_nr)       (S5PC1XX_GPIO_MP04_START + (_nr))
+#define S5PC100_GPL4(_nr)       (S5PC100_GPIO_L4_START + (_nr))
+#define S5PC100_MP00(_nr)       (S5PC100_GPIO_MP00_START + (_nr))
+#define S5PC100_MP01(_nr)       (S5PC100_GPIO_MP01_START + (_nr))
+#define S5PC100_MP02(_nr)       (S5PC100_GPIO_MP02_START + (_nr))
+#define S5PC100_MP03(_nr)       (S5PC100_GPIO_MP03_START + (_nr))
+#define S5PC100_MP04(_nr)       (S5PC100_GPIO_MP04_START + (_nr))
+#define S5PC100_MP05(_nr)       (S5PC100_GPIO_MP05_START + (_nr))
-/* the end of the S5PC1XX specific gpios */
+/* It used the end of the S5PC1XX gpios */
-#define S5PC1XX_GPIO_END        (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
+#define S3C_GPIO_END            S5PC100_GPIO_END
-#define S3C_GPIO_END            S5PC1XX_GPIO_END
 /* define the number of gpios we need to the one after the MP04() range */
-#define ARCH_NR_GPIOS   (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
+#define ARCH_NR_GPIOS           (S5PC100_GPIO_END + 1)
 #include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index 622720dba289..b53fa48a52c6 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -11,4 +11,9 @@
 #include <plat/irqs.h>
+/* LCD */
+#define IRQ_LCD_FIFO            IRQ_LCD0
+#define IRQ_LCD_VSYNC           IRQ_LCD1
+#define IRQ_LCD_SYSTEM          IRQ_LCD2
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 9e9f39130b2c..4681ebe8bef6 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -17,6 +17,19 @@
 #include <plat/map-base.h>
+/*
+ * map-base.h has already defined virtual memory address
+ * S3C_VA_IRQ           S3C_ADDR(0x00000000)    irq controller(s)
+ * S3C_VA_SYS           S3C_ADDR(0x00100000)    system control
+ * S3C_VA_MEM           S3C_ADDR(0x00200000)    system control (not used)
+ * S3C_VA_TIMER         S3C_ADDR(0x00300000)    timer block
+ * S3C_VA_WATCHDOG      S3C_ADDR(0x00400000)    watchdog
+ * S3C_VA_UART          S3C_ADDR(0x01000000)    UART
+ *
+ * S5PC100 specific virtual memory address can be defined here
+ * S5PC1XX_VA_GPIO      S3C_ADDR(0x00500000)    GPIO
+ *
+ */
 /* Chip ID */
 #define S5PC100_PA_CHIPID       (0xE0000000)
@@ -24,13 +37,20 @@
 #define S5PC1XX_VA_CHIPID       S3C_VA_SYS
 /* System */
-#define S5PC100_PA_SYS          (0xE0100000)
+#define S5PC100_PA_CLK          (0xE0100000)
-#define S5PC100_PA_CLK          (S5PC100_PA_SYS + 0x0)
+#define S5PC100_PA_CLK_OTHER    (0xE0200000)
-#define S5PC100_PA_PWR          (S5PC100_PA_SYS + 0x8000)
+#define S5PC100_PA_PWR          (0xE0108000)
 #define S5PC1XX_PA_CLK          S5PC100_PA_CLK
 #define S5PC1XX_PA_PWR          S5PC100_PA_PWR
+#define S5PC1XX_PA_CLK_OTHER    S5PC100_PA_CLK_OTHER
 #define S5PC1XX_VA_CLK          (S3C_VA_SYS + 0x10000)
 #define S5PC1XX_VA_PWR          (S3C_VA_SYS + 0x20000)
+#define S5PC1XX_VA_CLK_OTHER    (S3C_VA_SYS + 0x30000)
+/* GPIO */
+#define S5PC100_PA_GPIO         (0xE0300000)
+#define S5PC1XX_PA_GPIO         S5PC100_PA_GPIO
+#define S5PC1XX_VA_GPIO         S3C_ADDR(0x00500000)
 /* Interrupt */
 #define S5PC100_PA_VIC          (0xE4000000)
@@ -40,23 +60,64 @@
 #define S5PC1XX_PA_VIC(x)       (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
 #define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
+/* DMA */
+#define S5PC100_PA_MDMA         (0xE8100000)
+#define S5PC100_PA_PDMA0        (0xE9000000)
+#define S5PC100_PA_PDMA1        (0xE9200000)
 /* Timer */
 #define S5PC100_PA_TIMER        (0xEA000000)
 #define S5PC1XX_PA_TIMER        S5PC100_PA_TIMER
 #define S5PC1XX_VA_TIMER        S3C_VA_TIMER
+/* RTC */
+#define S5PC100_PA_RTC          (0xEA300000)
 /* UART */
 #define S5PC100_PA_UART         (0xEC000000)
 #define S5PC1XX_PA_UART         S5PC100_PA_UART
 #define S5PC1XX_VA_UART         S3C_VA_UART
-/* IIC */
+/* I2C */
-#define S5PC100_PA_IIC          (0xEC100000)
+#define S5PC100_PA_I2C          (0xEC100000)
+#define S5PC100_PA_I2C1         (0xEC200000)
+/* USB HS OTG */
+#define S5PC100_PA_USB_HSOTG    (0xED200000)
+#define S5PC100_PA_USB_HSPHY    (0xED300000)
+/* SD/MMC */
+#define S5PC100_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
+#define S5PC100_PA_HSMMC0       S5PC100_PA_HSMMC(0)
+#define S5PC100_PA_HSMMC1       S5PC100_PA_HSMMC(1)
+#define S5PC100_PA_HSMMC2       S5PC100_PA_HSMMC(2)
+/* LCD */
+#define S5PC100_PA_FB           (0xEE000000)
+/* Multimedia */
+#define S5PC100_PA_G2D          (0xEE800000)
+#define S5PC100_PA_JPEG         (0xEE500000)
+#define S5PC100_PA_ROTATOR      (0xEE100000)
+#define S5PC100_PA_G3D          (0xEF000000)
+/* I2S */
+#define S5PC100_PA_I2S0         (0xF2000000)
+#define S5PC100_PA_I2S1         (0xF2100000)
+#define S5PC100_PA_I2S2         (0xF2200000)
+/* KEYPAD */
+#define S5PC100_PA_KEYPAD       (0xF3100000)
+/* ADC & TouchScreen */
+#define S5PC100_PA_TSADC        (0xF3000000)
 /* ETC */
 #define S5PC100_PA_SDRAM        (0x20000000)
+#define S5PC1XX_PA_SDRAM        S5PC100_PA_SDRAM
 /* compatibility defines. */
+#define S3C_PA_RTC              S5PC100_PA_RTC
 #define S3C_PA_UART             S5PC100_PA_UART
 #define S3C_PA_UART0            (S5PC100_PA_UART + 0x0)
 #define S3C_PA_UART1            (S5PC100_PA_UART + 0x400)
@@ -67,9 +128,23 @@
 #define S3C_VA_UART2            (S3C_VA_UART + 0x800)
 #define S3C_VA_UART3            (S3C_VA_UART + 0xC00)
 #define S3C_UART_OFFSET         0x400
+#define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define S3C_PA_FB               S5PC100_PA_FB
+#define S3C_PA_G2D              S5PC100_PA_G2D
+#define S3C_PA_G3D              S5PC100_PA_G3D
+#define S3C_PA_JPEG             S5PC100_PA_JPEG
+#define S3C_PA_ROTATOR          S5PC100_PA_ROTATOR
 #define S3C_VA_VIC0             (S3C_VA_IRQ + 0x0)
 #define S3C_VA_VIC1             (S3C_VA_IRQ + 0x10000)
 #define S3C_VA_VIC2             (S3C_VA_IRQ + 0x20000)
-#define S3C_PA_IIC              S5PC100_PA_IIC
+#define S3C_PA_IIC              S5PC100_PA_I2C
+#define S3C_PA_IIC1             S5PC100_PA_I2C1
+#define S3C_PA_USB_HSOTG        S5PC100_PA_USB_HSOTG
+#define S3C_PA_USB_HSPHY        S5PC100_PA_USB_HSPHY
+#define S3C_PA_HSMMC0           S5PC100_PA_HSMMC0
+#define S3C_PA_HSMMC1           S5PC100_PA_HSMMC1
+#define S3C_PA_HSMMC2           S5PC100_PA_HSMMC2
+#define S3C_PA_KEYPAD           S5PC100_PA_KEYPAD
+#define S3C_PA_TSADC            S5PC100_PA_TSADC
 #endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
new file mode 100644
index 000000000000..1732cd28c765
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
@@ -0,0 +1,139 @@
+/* arch/arm/mach-s5pc100/include/mach/regs-fb.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *   Pawel Osciak <p.osciak@samsung.com>
+ *
+ * Framebuffer register definitions for Samsung S5PC100.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_REGS_FB_H
+#define __ASM_ARCH_REGS_FB_H __FILE__
+#include <plat/regs-fb-v4.h>
+/* VP1 interface timing control */
+#define VP1CON0                                         (0x118)
+#define VP1_RATECON_EN                                  (1 << 31)
+#define VP1_CLKRATE_MASK                                (0xff)
+#define VP1CON1                                         (0x11c)
+#define VP1_VTREGCON_EN                                 (1 << 31)
+#define VP1_VBPD_MASK                                   (0xfff)
+#define VP1_VBPD_SHIFT                                  (16)
+#define WPALCON_H                                       (0x19c)
+#define WPALCON_L                                       (0x1a0)
+/* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but
+ * different for WPAL2-4
+ */
+/* In WPALCON_L (aka WPALCON) */
+#define WPALCON_W1PAL_32BPP_A888                        (0x7 << 3)
+#define WPALCON_W0PAL_32BPP_A888                        (0x7 << 0)
+/* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
+ * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]).
+ */
+#define WPALCON_L_WxPAL_L_MASK                          (0x1)
+#define WPALCON_L_W2PAL_L_SHIFT                         (6)
+#define WPALCON_L_W3PAL_L_SHIFT                         (7)
+#define WPALCON_L_W4PAL_L_SHIFT                         (8)
+#define WPALCON_L_WxPAL_H_MASK                          (0x3)
+#define WPALCON_H_W2PAL_H_SHIFT                         (9)
+#define WPALCON_H_W3PAL_H_SHIFT                         (13)
+#define WPALCON_H_W4PAL_H_SHIFT                         (17)
+/* Per-window alpha value registers */
+/* For window 0 8-bit alpha values are in VIDW0ALPHAx,
+ * for windows 1-4 alpha values consist of two parts, the 4 low bits are
+ * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC,
+ * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0])
+ */
+#define VIDWxALPHA0(_win)                               (0x200 + (_win * 8))
+#define VIDWxALPHA1(_win)                               (0x204 + (_win * 8))
+/* Only for window 0 in VIDW0ALPHAx. */
+#define VIDW0ALPHAx_R(_x)                               ((_x) << 16)
+#define VIDW0ALPHAx_R_MASK                              (0xff << 16)
+#define VIDW0ALPHAx_R_SHIFT                             (16)
+#define VIDW0ALPHAx_G(_x)                               ((_x) << 8)
+#define VIDW0ALPHAx_G_MASK                              (0xff << 8)
+#define VIDW0ALPHAx_G_SHIFT                             (8)
+#define VIDW0ALPHAx_B(_x)                               ((_x) << 0)
+#define VIDW0ALPHAx_B_MASK                              (0xff << 0)
+#define VIDW0ALPHAx_B_SHIFT                             (0)
+/* Low 4 bits of alpha0-1 for windows 1-4 */
+#define VIDW14ALPHAx_R_L(_x)                            ((_x) << 16)
+#define VIDW14ALPHAx_R_L_MASK                           (0xf << 16)
+#define VIDW14ALPHAx_R_L_SHIFT                          (16)
+#define VIDW14ALPHAx_G_L(_x)                            ((_x) << 8)
+#define VIDW14ALPHAx_G_L_MASK                           (0xf << 8)
+#define VIDW14ALPHAx_G_L_SHIFT                          (8)
+#define VIDW14ALPHAx_B_L(_x)                            ((_x) << 0)
+#define VIDW14ALPHAx_B_L_MASK                           (0xf << 0)
+#define VIDW14ALPHAx_B_L_SHIFT                          (0)
+/* Per-window blending equation control registers */
+#define BLENDEQx(_win)                                  (0x244 + ((_win) * 4))
+#define BLENDEQ1                                        (0x244)
+#define BLENDEQ2                                        (0x248)
+#define BLENDEQ3                                        (0x24c)
+#define BLENDEQ4                                        (0x250)
+#define BLENDEQx_Q_FUNC(_x)                             ((_x) << 18)
+#define BLENDEQx_Q_FUNC_MASK                            (0xf << 18)
+#define BLENDEQx_P_FUNC(_x)                             ((_x) << 12)
+#define BLENDEQx_P_FUNC_MASK                            (0xf << 12)
+#define BLENDEQx_B_FUNC(_x)                             ((_x) << 6)
+#define BLENDEQx_B_FUNC_MASK                            (0xf << 6)
+#define BLENDEQx_A_FUNC(_x)                             ((_x) << 0)
+#define BLENDEQx_A_FUNC_MASK                            (0xf << 0)
+#define BLENDCON                                        (0x260)
+#define BLENDCON_8BIT_ALPHA                             (1 << 0)
+/* Per-window palette base addresses (start of palette memory).
+ * Each window palette area consists of 256 32-bit entries.
+ * START is the first address (entry 0th), END is the address of 255th entry.
+ */
+#define WIN0_PAL_BASE                                   (0x2400)
+#define WIN0_PAL_END                                    (0x27fc)
+#define WIN1_PAL_BASE                                   (0x2800)
+#define WIN1_PAL_END                                    (0x2bfc)
+#define WIN2_PAL_BASE                                   (0x2c00)
+#define WIN2_PAL_END                                    (0x2ffc)
+#define WIN3_PAL_BASE                                   (0x3000)
+#define WIN3_PAL_END                                    (0x33fc)
+#define WIN4_PAL_BASE                                   (0x3400)
+#define WIN4_PAL_END                                    (0x37fc)
+#define WIN0_PAL(_entry)                        (WIN0_PAL_BASE + ((_entry) * 4))
+#define WIN1_PAL(_entry)                        (WIN1_PAL_BASE + ((_entry) * 4))
+#define WIN2_PAL(_entry)                        (WIN2_PAL_BASE + ((_entry) * 4))
+#define WIN3_PAL(_entry)                        (WIN3_PAL_BASE + ((_entry) * 4))
+#define WIN4_PAL(_entry)                        (WIN4_PAL_BASE + ((_entry) * 4))
+static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
+{
+        switch (window) {
+        case 0: return WIN0_PAL(reg);
+        case 1: return WIN1_PAL(reg);
+        case 2: return WIN2_PAL(reg);
+        case 3: return WIN3_PAL(reg);
+        case 4: return WIN4_PAL(reg);
+        }
+        BUG();
+}
+#endif /* __ASM_ARCH_REGS_FB_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
index e39014375470..f0d31a2a598c 100644
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -11,14 +11,21 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
+#include <linux/io.h>
+#include <mach/map.h>
+#include <plat/regs-clock.h>
+void (*s5pc1xx_idle)(void);
 static void arch_idle(void)
 {
-        /* nothing here yet */
+        if (s5pc1xx_idle)
+                s5pc1xx_idle();
 }
 static void arch_reset(char mode, const char *cmd)
 {
-        /* nothing here yet */
+        __raw_writel(S5PC100_SWRESET_RESETVAL, S5PC100_SWRESET);
+        return;
 }
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 214093cd7632..ae3c52cd0ebb 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -27,16 +27,22 @@
 #include <asm/mach/map.h>
 #include <mach/map.h>
+#include <mach/regs-fb.h>
+#include <video/platform_lcd.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-gpio.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/s5pc100.h>
+#include <plat/fb.h>
+#include <plat/iic.h>
 #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
@@ -73,9 +79,78 @@ static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
        },
 };
+/* I2C0 */
+static struct i2c_board_info i2c_devs0[] __initdata = {
+};
+/* I2C1 */
+static struct i2c_board_info i2c_devs1[] __initdata = {
+};
+/* LCD power controller */
+static void smdkc100_lcd_power_set(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        /* backlight */
+        gpio_direction_output(S5PC100_GPD(0), power);
+        if (power) {
+                /* module reset */
+                gpio_direction_output(S5PC100_GPH0(6), 1);
+                mdelay(100);
+                gpio_direction_output(S5PC100_GPH0(6), 0);
+                mdelay(10);
+                gpio_direction_output(S5PC100_GPH0(6), 1);
+                mdelay(10);
+        }
+}
+static struct plat_lcd_data smdkc100_lcd_power_data = {
+        .set_power      = smdkc100_lcd_power_set,
+};
+static struct platform_device smdkc100_lcd_powerdev = {
+        .name                   = "platform-lcd",
+        .dev.parent             = &s3c_device_fb.dev,
+        .dev.platform_data      = &smdkc100_lcd_power_data,
+};
+/* Frame Buffer */
+static struct s3c_fb_pd_win smdkc100_fb_win0 = {
+        /* this is to ensure we use win0 */
+        .win_mode       = {
+                .refresh        = 70,
+                .pixclock       = (8+13+3+800)*(7+5+1+480),
+                .left_margin    = 8,
+                .right_margin   = 13,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp        = 32,
+        .default_bpp    = 16,
+};
+static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
+        .win[0]         = &smdkc100_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = s5pc100_fb_gpio_setup_24bpp,
+};
 static struct map_desc smdkc100_iodesc[] = {};
 static struct platform_device *smdkc100_devices[] __initdata = {
+        &s3c_device_i2c0,
+        &s3c_device_i2c1,
+        &s3c_device_fb,
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+        &s3c_device_hsmmc2,
+        &smdkc100_lcd_powerdev,
 };
 static void __init smdkc100_map_io(void)
@@ -87,12 +162,24 @@ static void __init smdkc100_map_io(void)
 static void __init smdkc100_machine_init(void)
 {
+        /* I2C */
+        s3c_i2c0_set_platdata(NULL);
+        s3c_i2c1_set_platdata(NULL);
+        i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+        i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+        s3c_fb_set_platdata(&smdkc100_lcd_pdata);
+        /* LCD init */
+        gpio_request(S5PC100_GPD(0), "GPD");
+        gpio_request(S5PC100_GPH0(6), "GPH0");
+        smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
        platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
 }
 MACHINE_START(SMDKC100, "SMDKC100")
        /* Maintainer: Byungho Min <bhmin@samsung.com> */
-        .phys_io        = S5PC1XX_PA_UART & 0xfff00000,
+        .phys_io        = S5PC100_PA_UART & 0xfff00000,
        .io_pg_offst    = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc,
        .boot_params    = S5PC100_PA_SDRAM + 0x100,
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
new file mode 100644
index 000000000000..4385986a3da0
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-sdhci.c
@@ -0,0 +1,65 @@
+/* linux/arch/arm/mach-s5pc100/setup-sdhci.c
+ *
+ * Copyright 2008 Samsung Electronics
+ *
+ * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * Based on mach-s3c6410/setup-sdhci.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+char *s5pc100_hsmmc_clksrcs[4] = {
+        [0] = "hsmmc",
+        [1] = "hsmmc",
+        /* [2] = "mmc_bus", not yet succesfuuly used yet */
+        /* [3] = "48m", - note not succesfully used yet */
+};
+void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
+                                    void __iomem *r,
+                                    struct mmc_ios *ios,
+                                    struct mmc_card *card)
+{
+        u32 ctrl2, ctrl3;
+        /* don't need to alter anything acording to card-type */
+        writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4);
+        ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
+        ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+        ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+                  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+                  S3C_SDHCI_CTRL2_ENFBCLKRX |
+                  S3C_SDHCI_CTRL2_DFCNT_NONE |
+                  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+        if (ios->clock < 25 * 1000000)
+                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+                         S3C_SDHCI_CTRL3_FCSEL2 |
+                         S3C_SDHCI_CTRL3_FCSEL1 |
+                         S3C_SDHCI_CTRL3_FCSEL0);
+        else
+                ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+        writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+        writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 9264d814cd7a..4958ef2c6254 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -388,7 +388,7 @@ config CPU_FEROCEON_OLD_ID
 # ARMv6
 config CPU_V6
-        bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
+        bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE
        select CPU_32v6
        select CPU_ABRT_EV6
        select CPU_PABRT_V6
@@ -764,6 +764,15 @@ config CACHE_L2X0
        help
          This option enables the L2x0 PrimeCell.
+config CACHE_TAUROS2
+        bool "Enable the Tauros2 L2 cache controller"
+        depends on ARCH_DOVE
+        default y
+        select OUTER_CACHE
+        help
+          This option enables the Tauros2 L2 cache controller (as
+          found on PJ1/PJ4).
 config CACHE_XSC3L2
        bool "Enable the L2 cache on XScale3"
        depends on CPU_XSC3
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 055cb2aa8134..06bcf2e73858 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -87,4 +87,4 @@ obj-$(CONFIG_CPU_V7)		+= proc-v7.o
 obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_CACHE_XSC3L2)      += cache-xsc3l2.o
+obj-$(CONFIG_CACHE_TAUROS2)     += cache-tauros2.o
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
new file mode 100644
index 000000000000..50868651890f
--- /dev/null
+++ b/arch/arm/mm/cache-tauros2.c
@@ -0,0 +1,263 @@
+/*
+ * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * References:
+ * - PJ1 CPU Core Datasheet,
+ *   Document ID MV-S104837-01, Rev 0.7, January 24 2008.
+ * - PJ4 CPU Core Datasheet,
+ *   Document ID MV-S105190-00, Rev 0.7, March 14 2008.
+ */
+#include <linux/init.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-tauros2.h>
+/*
+ * When Tauros2 is used on a CPU that supports the v7 hierarchical
+ * cache operations, the cache handling code in proc-v7.S takes care
+ * of everything, including handling DMA coherency.
+ *
+ * So, we only need to register outer cache operations here if we're
+ * being used on a pre-v7 CPU, and we only need to build support for
+ * outer cache operations into the kernel image if the kernel has been
+ * configured to support a pre-v7 CPU.
+ */
+#if __LINUX_ARM_ARCH__ < 7
+/*
+ * Low-level cache maintenance operations.
+ */
+static inline void tauros2_clean_pa(unsigned long addr)
+{
+        __asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr));
+}
+static inline void tauros2_clean_inv_pa(unsigned long addr)
+{
+        __asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr));
+}
+static inline void tauros2_inv_pa(unsigned long addr)
+{
+        __asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr));
+}
+/*
+ * Linux primitives.
+ *
+ * Note that the end addresses passed to Linux primitives are
+ * noninclusive.
+ */
+#define CACHE_LINE_SIZE         32
+static void tauros2_inv_range(unsigned long start, unsigned long end)
+{
+        /*
+         * Clean and invalidate partial first cache line.
+         */
+        if (start & (CACHE_LINE_SIZE - 1)) {
+                tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
+                start = (start | (CACHE_LINE_SIZE - 1)) + 1;
+        }
+        /*
+         * Clean and invalidate partial last cache line.
+         */
+        if (end & (CACHE_LINE_SIZE - 1)) {
+                tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
+                end &= ~(CACHE_LINE_SIZE - 1);
+        }
+        /*
+         * Invalidate all full cache lines between 'start' and 'end'.
+         */
+        while (start < end) {
+                tauros2_inv_pa(start);
+                start += CACHE_LINE_SIZE;
+        }
+        dsb();
+}
+static void tauros2_clean_range(unsigned long start, unsigned long end)
+{
+        start &= ~(CACHE_LINE_SIZE - 1);
+        while (start < end) {
+                tauros2_clean_pa(start);
+                start += CACHE_LINE_SIZE;
+        }
+        dsb();
+}
+static void tauros2_flush_range(unsigned long start, unsigned long end)
+{
+        start &= ~(CACHE_LINE_SIZE - 1);
+        while (start < end) {
+                tauros2_clean_inv_pa(start);
+                start += CACHE_LINE_SIZE;
+        }
+        dsb();
+}
+#endif
+static inline u32 __init read_extra_features(void)
+{
+        u32 u;
+        __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
+        return u;
+}
+static inline void __init write_extra_features(u32 u)
+{
+        __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
+}
+static void __init disable_l2_prefetch(void)
+{
+        u32 u;
+        /*
+         * Read the CPU Extra Features register and verify that the
+         * Disable L2 Prefetch bit is set.
+         */
+        u = read_extra_features();
+        if (!(u & 0x01000000)) {
+                printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n");
+                write_extra_features(u | 0x01000000);
+        }
+}
+static inline int __init cpuid_scheme(void)
+{
+        extern int processor_id;
+        return !!((processor_id & 0x000f0000) == 0x000f0000);
+}
+static inline u32 __init read_mmfr3(void)
+{
+        u32 mmfr3;
+        __asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3));
+        return mmfr3;
+}
+static inline u32 __init read_actlr(void)
+{
+        u32 actlr;
+        __asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
+        return actlr;
+}
+static inline void __init write_actlr(u32 actlr)
+{
+        __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
+}
+void __init tauros2_init(void)
+{
+        extern int processor_id;
+        char *mode;
+        disable_l2_prefetch();
+#ifdef CONFIG_CPU_32v5
+        if ((processor_id & 0xff0f0000) == 0x56050000) {
+                u32 feat;
+                /*
+                 * v5 CPUs with Tauros2 have the L2 cache enable bit
+                 * located in the CPU Extra Features register.
+                 */
+                feat = read_extra_features();
+                if (!(feat & 0x00400000)) {
+                        printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
+                        write_extra_features(feat | 0x00400000);
+                }
+                mode = "ARMv5";
+                outer_cache.inv_range = tauros2_inv_range;
+                outer_cache.clean_range = tauros2_clean_range;
+                outer_cache.flush_range = tauros2_flush_range;
+        }
+#endif
+#ifdef CONFIG_CPU_32v6
+        /*
+         * Check whether this CPU lacks support for the v7 hierarchical
+         * cache ops.  (PJ4 is in its v6 personality mode if the MMFR3
+         * register indicates no support for the v7 hierarchical cache
+         * ops.)
+         */
+        if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) {
+                /*
+                 * When Tauros2 is used in an ARMv6 system, the L2
+                 * enable bit is in the ARMv6 ARM-mandated position
+                 * (bit [26] of the System Control Register).
+                 */
+                if (!(get_cr() & 0x04000000)) {
+                        printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
+                        adjust_cr(0x04000000, 0x04000000);
+                }
+                mode = "ARMv6";
+                outer_cache.inv_range = tauros2_inv_range;
+                outer_cache.clean_range = tauros2_clean_range;
+                outer_cache.flush_range = tauros2_flush_range;
+        }
+#endif
+#ifdef CONFIG_CPU_32v7
+        /*
+         * Check whether this CPU has support for the v7 hierarchical
+         * cache ops.  (PJ4 is in its v7 personality mode if the MMFR3
+         * register indicates support for the v7 hierarchical cache
+         * ops.)
+         *
+         * (Although strictly speaking there may exist CPUs that
+         * implement the v7 cache ops but are only ARMv6 CPUs (due to
+         * not complying with all of the other ARMv7 requirements),
+         * there are no real-life examples of Tauros2 being used on
+         * such CPUs as of yet.)
+         */
+        if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) {
+                u32 actlr;
+                /*
+                 * When Tauros2 is used in an ARMv7 system, the L2
+                 * enable bit is located in the Auxiliary System Control
+                 * Register (which is the only register allowed by the
+                 * ARMv7 spec to contain fine-grained cache control bits).
+                 */
+                actlr = read_actlr();
+                if (!(actlr & 0x00000002)) {
+                        printk(KERN_INFO "Tauros2: Enabling L2 cache.\n");
+                        write_actlr(actlr | 0x00000002);
+                }
+                mode = "ARMv7";
+        }
+#endif
+        if (mode == NULL) {
+                printk(KERN_CRIT "Tauros2: Unable to detect CPU mode.\n");
+                return;
+        }
+        printk(KERN_INFO "Tauros2: L2 cache support initialised "
+                         "in %s mode.\n", mode);
+}
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 70f75d2e3ead..5485c821101c 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -130,9 +130,16 @@ ENTRY(cpu_v6_set_pte_ext)
+        .type   cpu_v6_name, #object
 cpu_v6_name:
        .asciz  "ARMv6-compatible processor"
+        .size   cpu_v6_name, . - cpu_v6_name
+        .type   cpu_pj4_name, #object
+cpu_pj4_name:
+        .asciz  "Marvell PJ4 processor"
+        .size   cpu_pj4_name, . - cpu_pj4_name
        .align
        __INIT
@@ -241,3 +248,27 @@ __v6_proc_info:
        .long   v6_user_fns
        .long   v6_cache_fns
        .size   __v6_proc_info, . - __v6_proc_info
+        .type   __pj4_v6_proc_info, #object
+__pj4_v6_proc_info:
+        .long   0x560f5810
+        .long   0xff0ffff0
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_BUFFERABLE | \
+                PMD_SECT_CACHEABLE | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        .long   PMD_TYPE_SECT | \
+                PMD_SECT_XN | \
+                PMD_SECT_AP_WRITE | \
+                PMD_SECT_AP_READ
+        b       __v6_setup
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+        .long   cpu_pj4_name
+        .long   v6_processor_functions
+        .long   v6wbi_tlb_fns
+        .long   v6_user_fns
+        .long   v6_cache_fns
+        .size   __pj4_v6_proc_info, . - __pj4_v6_proc_info
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 2028f3702881..fab134e29826 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -396,7 +396,7 @@ __xsc3_setup:
        orr     r4, r4, #0x18                   @ cache the page table in L2
        mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
-        mov     r0, #0                          @ don't allow CP access
+        mov     r0, #1 << 6                     @ cp6 access for early sched_clock
        mcr     p15, 0, r0, c15, c1, 0          @ write CP access register
        mrc     p15, 0, r0, c1, c0, 1           @ get auxiliary control reg
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index 8da95d57c21f..6c8a02ad98e3 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -19,6 +19,8 @@
 #include <linux/init.h>
 #include <linux/timex.h>
 #include <linux/io.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/uaccess.h>
@@ -26,45 +28,136 @@
 #include <asm/mach/time.h>
 #include <mach/time.h>
+/*
+ * IOP clocksource (free-running timer 1).
+ */
+static cycle_t iop_clocksource_read(struct clocksource *unused)
+{
+        return 0xffffffffu - read_tcr1();
+}
+static struct clocksource iop_clocksource = {
+        .name           = "iop_timer1",
+        .rating         = 300,
+        .read           = iop_clocksource_read,
+        .mask           = CLOCKSOURCE_MASK(32),
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz)
+{
+        u64 temp;
+        u32 shift;
+        /* Find shift and mult values for hz. */
+        shift = 32;
+        do {
+                temp = (u64) NSEC_PER_SEC << shift;
+                do_div(temp, hz);
+                if ((temp >> 32) == 0)
+                        break;
+        } while (--shift != 0);
+        cs->shift = shift;
+        cs->mult = (u32) temp;
+        printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n",
+               cs->name, cs->shift, cs->mult);
+}
+/*
+ * IOP sched_clock() implementation via its clocksource.
+ */
+unsigned long long sched_clock(void)
+{
+        cycle_t cyc = iop_clocksource_read(NULL);
+        struct clocksource *cs = &iop_clocksource;
+        return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
+}
+/*
+ * IOP clockevents (interrupting timer 0).
+ */
+static int iop_set_next_event(unsigned long delta,
+                              struct clock_event_device *unused)
+{
+        u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;
+        BUG_ON(delta == 0);
+        write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
+        write_tcr0(delta);
+        write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);
+        return 0;
+}
 static unsigned long ticks_per_jiffy;
-static unsigned long ticks_per_usec;
-static unsigned long next_jiffy_time;
-unsigned long iop_gettimeoffset(void)
+static void iop_set_mode(enum clock_event_mode mode,
+                         struct clock_event_device *unused)
 {
-        unsigned long offset, temp;
+        u32 tmr = read_tmr0();
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                write_tmr0(tmr & ~IOP_TMR_EN);
+                write_tcr0(ticks_per_jiffy - 1);
+                tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* ->set_next_event sets period and enables timer */
+                tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                tmr |= IOP_TMR_EN;
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+        default:
+                tmr &= ~IOP_TMR_EN;
+                break;
+        }
-        /* enable cp6, if necessary, to avoid taking the overhead of an
+        write_tmr0(tmr);
-         * undefined instruction trap
+}
-         */
-        asm volatile (
+static struct clock_event_device iop_clockevent = {
-        "mrc    p15, 0, %0, c15, c1, 0\n\t"
+        .name           = "iop_timer0",
-        "tst    %0, #(1 << 6)\n\t"
+        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        "orreq  %0, %0, #(1 << 6)\n\t"
+        .rating         = 300,
-        "mcreq  p15, 0, %0, c15, c1, 0\n\t"
+        .set_next_event = iop_set_next_event,
-#ifdef CONFIG_CPU_XSCALE
+        .set_mode       = iop_set_mode,
-        "mrceq  p15, 0, %0, c15, c1, 0\n\t"
+};
-        "moveq  %0, %0\n\t"
-        "subeq  pc, pc, #4\n\t"
+static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz)
-#endif
+{
-        : "=r"(temp) : : "cc");
+        u64 temp;
+        u32 shift;
-        offset = next_jiffy_time - read_tcr1();
+        /* Find shift and mult values for hz. */
-        return offset / ticks_per_usec;
+        shift = 32;
+        do {
+                temp = (u64) hz << shift;
+                do_div(temp, NSEC_PER_SEC);
+                if ((temp >> 32) == 0)
+                        break;
+        } while (--shift != 0);
+        ce->shift = shift;
+        ce->mult = (u32) temp;
+        printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n",
+               ce->name, ce->shift, ce->mult);
 }
 static irqreturn_t
 iop_timer_interrupt(int irq, void *dev_id)
 {
-        write_tisr(1);
+        struct clock_event_device *evt = dev_id;
-        while ((signed long)(next_jiffy_time - read_tcr1())
-                >= ticks_per_jiffy) {
-                timer_tick();
-                next_jiffy_time -= ticks_per_jiffy;
-        }
+        write_tisr(1);
+        evt->event_handler(evt);
        return IRQ_HANDLED;
 }
@@ -72,6 +165,7 @@ static struct irqaction iop_timer_irq = {
        .name           = "IOP Timer Tick",
        .handler        = iop_timer_interrupt,
        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .dev_id         = &iop_clockevent,
 };
 static unsigned long iop_tick_rate;
@@ -86,21 +180,33 @@ void __init iop_init_time(unsigned long tick_rate)
        u32 timer_ctl;
        ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
-        ticks_per_usec = tick_rate / 1000000;
-        next_jiffy_time = 0xffffffff;
        iop_tick_rate = tick_rate;
        timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
                        IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
        /*
-         * We use timer 0 for our timer interrupt, and timer 1 as
+         * Set up interrupting clockevent timer 0.
-         * monotonic counter for tracking missed jiffies.
         */
+        write_tmr0(timer_ctl & ~IOP_TMR_EN);
+        setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
+        iop_clockevent_set_hz(&iop_clockevent, tick_rate);
+        iop_clockevent.max_delta_ns =
+                clockevent_delta2ns(0xfffffffe, &iop_clockevent);
+        iop_clockevent.min_delta_ns =
+                clockevent_delta2ns(0xf, &iop_clockevent);
+        iop_clockevent.cpumask = cpumask_of(0);
+        clockevents_register_device(&iop_clockevent);
        write_trr0(ticks_per_jiffy - 1);
+        write_tcr0(ticks_per_jiffy - 1);
        write_tmr0(timer_ctl);
+        /*
+         * Set up free-running clocksource timer 1.
+         */
        write_trr1(0xffffffff);
+        write_tcr1(0xffffffff);
        write_tmr1(timer_ctl);
+        iop_clocksource_set_hz(&iop_clocksource, tick_rate);
-        setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
+        clocksource_register(&iop_clocksource);
 }
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index ca5c7c226341..8b0a1ee039fa 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -69,10 +69,20 @@ config MXC_PWM
        help
          Enable support for the i.MX PWM controller(s).
+config MXC_ULPI
+        bool
 config ARCH_HAS_RNGA
        bool
        depends on ARCH_MXC
 config ARCH_MXC_IOMUX_V3
        bool
+config ARCH_MXC_AUDMUX_V1
+        bool
+config ARCH_MXC_AUDMUX_V2
+        bool
 endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index e3212c8ff421..4cbca9da1505 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -9,3 +9,6 @@ obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
 obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
+obj-$(CONFIG_MXC_ULPI) += ulpi.o
+obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
+obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
new file mode 100644
index 000000000000..70ab5aff2b9e
--- /dev/null
+++ b/arch/arm/plat-mxc/audmux-v1.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * Initial development of this code was funded by
+ * Phytec Messtechnik GmbH, http://www.phytec.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <mach/audmux.h>
+#include <mach/hardware.h>
+static void __iomem *audmux_base;
+#define MXC_AUDMUX_V1_PCR(x)    ((x) * 4)
+int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr)
+{
+        if (!audmux_base) {
+                printk("%s: not configured\n", __func__);
+                return -ENOSYS;
+        }
+        writel(pcr, audmux_base + MXC_AUDMUX_V1_PCR(port));
+        return 0;
+}
+EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port);
+static int mxc_audmux_v1_init(void)
+{
+        if (cpu_is_mx27() || cpu_is_mx21())
+                audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
+        return 0;
+}
+postcore_initcall(mxc_audmux_v1_init);
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
new file mode 100644
index 000000000000..6f21096086fd
--- /dev/null
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * Initial development of this code was funded by
+ * Phytec Messtechnik GmbH, http://www.phytec.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <mach/audmux.h>
+#include <mach/hardware.h>
+static struct clk *audmux_clk;
+static void __iomem *audmux_base;
+#define MXC_AUDMUX_V2_PTCR(x)           ((x) * 8)
+#define MXC_AUDMUX_V2_PDCR(x)           ((x) * 8 + 4)
+int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
+                unsigned int pdcr)
+{
+        if (!audmux_base)
+                return -ENOSYS;
+        if (audmux_clk)
+                clk_enable(audmux_clk);
+        writel(ptcr, audmux_base + MXC_AUDMUX_V2_PTCR(port));
+        writel(pdcr, audmux_base + MXC_AUDMUX_V2_PDCR(port));
+        if (audmux_clk)
+                clk_disable(audmux_clk);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
+static int mxc_audmux_v2_init(void)
+{
+        int ret;
+        if (cpu_is_mx35()) {
+                audmux_clk = clk_get(NULL, "audmux");
+                if (IS_ERR(audmux_clk)) {
+                        ret = PTR_ERR(audmux_clk);
+                        printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
+                                        ret);
+                        return ret;
+                }
+        }
+        if (cpu_is_mx31() || cpu_is_mx35())
+                audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
+        return 0;
+}
+postcore_initcall(mxc_audmux_v2_init);
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
index 77646436c00e..9c1b3f9c4f4d 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -156,7 +156,8 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
        }
        now = min(imxdma->resbytes, sg->length);
-        imxdma->resbytes -= now;
+        if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
+                imxdma->resbytes -= now;
        if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
                __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel));
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index cfc4a8b43e6a..d65ebe303b9f 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -282,7 +282,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                for (j = port[i].virtual_irq_start;
                        j < port[i].virtual_irq_start + 32; j++) {
                        set_irq_chip(j, &gpio_irq_chip);
-                        set_irq_handler(j, handle_edge_irq);
+                        set_irq_handler(j, handle_level_irq);
                        set_irq_flags(j, IRQF_VALID);
                }
diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h
new file mode 100644
index 000000000000..5cd6466964af
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/audmux.h
@@ -0,0 +1,52 @@
+#ifndef __MACH_AUDMUX_H
+#define __MACH_AUDMUX_H
+#define MX27_AUDMUX_HPCR1_SSI0          0
+#define MX27_AUDMUX_HPCR2_SSI1          1
+#define MX27_AUDMUX_HPCR3_SSI_PINS_4    2
+#define MX27_AUDMUX_PPCR1_SSI_PINS_1    3
+#define MX27_AUDMUX_PPCR2_SSI_PINS_2    4
+#define MX27_AUDMUX_PPCR3_SSI_PINS_3    5
+#define MX31_AUDMUX_PORT1_SSI0          0
+#define MX31_AUDMUX_PORT2_SSI1          1
+#define MX31_AUDMUX_PORT3_SSI_PINS_3    2
+#define MX31_AUDMUX_PORT4_SSI_PINS_4    3
+#define MX31_AUDMUX_PORT5_SSI_PINS_5    4
+#define MX31_AUDMUX_PORT6_SSI_PINS_6    5
+/* Register definitions for the i.MX21/27 Digital Audio Multiplexer */
+#define MXC_AUDMUX_V1_PCR_INMMASK(x)    ((x) & 0xff)
+#define MXC_AUDMUX_V1_PCR_INMEN         (1 << 8)
+#define MXC_AUDMUX_V1_PCR_TXRXEN        (1 << 10)
+#define MXC_AUDMUX_V1_PCR_SYN           (1 << 12)
+#define MXC_AUDMUX_V1_PCR_RXDSEL(x)     (((x) & 0x7) << 13)
+#define MXC_AUDMUX_V1_PCR_RFCSEL(x)     (((x) & 0xf) << 20)
+#define MXC_AUDMUX_V1_PCR_RCLKDIR       (1 << 24)
+#define MXC_AUDMUX_V1_PCR_RFSDIR        (1 << 25)
+#define MXC_AUDMUX_V1_PCR_TFCSEL(x)     (((x) & 0xf) << 26)
+#define MXC_AUDMUX_V1_PCR_TCLKDIR       (1 << 30)
+#define MXC_AUDMUX_V1_PCR_TFSDIR        (1 << 31)
+/* Register definitions for the i.MX25/31/35 Digital Audio Multiplexer */
+#define MXC_AUDMUX_V2_PTCR_TFSDIR       (1 << 31)
+#define MXC_AUDMUX_V2_PTCR_TFSEL(x)     (((x) & 0xf) << 27)
+#define MXC_AUDMUX_V2_PTCR_TCLKDIR      (1 << 26)
+#define MXC_AUDMUX_V2_PTCR_TCSEL(x)     (((x) & 0xf) << 22)
+#define MXC_AUDMUX_V2_PTCR_RFSDIR       (1 << 21)
+#define MXC_AUDMUX_V2_PTCR_RFSEL(x)     (((x) & 0xf) << 17)
+#define MXC_AUDMUX_V2_PTCR_RCLKDIR      (1 << 16)
+#define MXC_AUDMUX_V2_PTCR_RCSEL(x)     (((x) & 0xf) << 12)
+#define MXC_AUDMUX_V2_PTCR_SYN          (1 << 11)
+#define MXC_AUDMUX_V2_PDCR_RXDSEL(x)    (((x) & 0x7) << 13)
+#define MXC_AUDMUX_V2_PDCR_TXRXEN       (1 << 12)
+#define MXC_AUDMUX_V2_PDCR_MODE(x)      (((x) & 0x3) << 8)
+#define MXC_AUDMUX_V2_PDCR_INMMASK(x)   ((x) & 0xff)
+int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr);
+int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
+                unsigned int pdcr);
+#endif /* __MACH_AUDMUX_H */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 8e64325d6905..0184b638c268 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -1,15 +1,42 @@
 /*
 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * Based on code for mobots boards,
+ *   Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
 */
+#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+#ifndef __ASSEMBLY__
+enum mx31lilly_boards {
+        MX31LITE_NOBOARD        = 0,
+        MX31LITE_DB             = 1,
+};
 /*
- * This program is free software; you can redistribute it and/or modify
+ * This CPU module needs a baseboard to work. After basic initializing
- * it under the terms of the GNU General Public License version 2 as
+ * its own devices, it calls baseboard's init function.
- * published by the Free Software Foundation.
 */
-#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
+extern void mx31lite_db_init(void);
-#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
-#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
+#endif
+#endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
index b3876cc238ca..07be8ad7ec37 100644
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
@@ -58,6 +58,14 @@ imx_dma_setup_single(int channel, dma_addr_t dma_address,
                unsigned int dma_length, unsigned int dev_addr,
                unsigned int dmamode);
+/*
+ * Use this flag as the dma_length argument to imx_dma_setup_sg()
+ * to create an endless running dma loop. The end of the scatterlist
+ * must be linked to the beginning for this to work.
+ */
+#define IMX_DMA_LENGTH_LOOP     ((unsigned int)-1)
 int
 imx_dma_setup_sg(int channel, struct scatterlist *sg,
                unsigned int sgcount, unsigned int dma_length,
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 446f86763816..2f6583e185aa 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -623,6 +623,8 @@ enum iomux_pins {
 #define MX31_PIN_GPIO3_0__GPIO3_0       IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_GPIO3_1__GPIO3_1       IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_TXD2__GPIO1_28         IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CSI_D4__GPIO3_4        IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CSI_D5__GPIO3_5        IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0    IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1    IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2    IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC)
@@ -642,12 +644,22 @@ enum iomux_pins {
 #define MX31_PIN_CSPI1_SS2__USBH1_RCV          IOMUX_MODE(MX31_PIN_CSPI1_SS2,  IOMUX_CONFIG_ALT1)
 #define MX31_PIN_CSPI1_SCLK__USBH1_OEB         IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
 #define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS       IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_SFS6__USBH1_SUSPEND    IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_NFRE_B__GPIO1_11       IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_NFALE__GPIO1_12        IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_USBH2_DATA0__USBH2_DATA0      IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBH2_DATA1__USBH2_DATA1      IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_STXD3__USBH2_DATA2     IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SRXD3__USBH2_DATA3     IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SCK3__USBH2_DATA4      IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SFS3__USBH2_DATA5      IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_STXD6__USBH2_DATA6     IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SRXD6__USBH2_DATA7     IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBH2_CLK__USBH2_CLK          IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBH2_DIR__USBH2_DIR          IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBH2_NXT__USBH2_NXT          IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBH2_STP__USBH2_STP          IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SCK6__GPIO1_25         IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_USB_OC__GPIO1_30       IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_I2C_DAT__I2C1_SDA      IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_I2C_CLK__I2C1_SCL      IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
@@ -693,7 +705,19 @@ enum iomux_pins {
 #define MX31_PIN_DCD_DCE1__GPIO2_11     IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_STXD5__GPIO1_21       IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_SRXD5__GPIO1_22       IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_GPIO1_3__GPIO1_3       IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CSPI2_SS1__CSPI3_SS1   IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_RTS1__GPIO2_6          IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_CTS1__GPIO2_7          IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_LCS0__GPIO3_23         IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_STXD4__STXD4           IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SRXD4__SRXD4           IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SCK4__SCK4             IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SFS4__SFS4             IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_STXD5__STXD5           IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SRXD5__SRXD5           IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SCK5__SCK5             IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_SFS5__SFS5             IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC)
 /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
 * cspi1_ss1*/
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index a0fa40265468..1deda0184892 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -88,9 +88,7 @@ struct pad_desc {
 #define PAD_CTL_SRE_FAST                (1 << 0)
 /*
- * setups a single pad:
+ * setups a single pad in the iomuxer
- *      - reserves the pad so that it is not claimed by another driver
- *      - setups the iomux according to the configuration
 */
 int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
@@ -101,19 +99,6 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
 int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
 /*
- * releases a single pad:
- *      - make it available for a future use by another driver
- *      - DOES NOT reconfigure the IOMUX in its reset state
- */
-void mxc_iomux_v3_release_pad(struct pad_desc *pad);
-/*
- * releases multiple pads
- * convenvient way to call the above function with tables
- */
-void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
-/*
 * Initialise the iomux controller
 */
 void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 21112c695ec5..bb297d8765a7 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -25,46 +25,191 @@
 #ifndef __ASM_ARCH_MXC_MX21_H__
 #define __ASM_ARCH_MXC_MX21_H__
+#define MX21_AIPI_BASE_ADDR             0x10000000
+#define MX21_AIPI_BASE_ADDR_VIRT        0xf4000000
+#define MX21_AIPI_SIZE                  SZ_1M
+#define MX21_DMA_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x01000)
+#define MX21_WDOG_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x02000)
+#define MX21_GPT1_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x03000)
+#define MX21_GPT2_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x04000)
+#define MX21_GPT3_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x05000)
+#define MX21_PWM_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x06000)
+#define MX21_RTC_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x07000)
+#define MX21_KPP_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x08000)
+#define MX21_OWIRE_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x09000)
+#define MX21_UART1_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0a000)
+#define MX21_UART2_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0b000)
+#define MX21_UART3_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0c000)
+#define MX21_UART4_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0d000)
+#define MX21_CSPI1_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0e000)
+#define MX21_CSPI2_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x0f000)
+#define MX21_SSI1_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x10000)
+#define MX21_SSI2_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x11000)
+#define MX21_I2C_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x12000)
+#define MX21_SDHC1_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x13000)
+#define MX21_SDHC2_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x14000)
+#define MX21_GPIO_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x15000)
+#define MX21_AUDMUX_BASE_ADDR                   (MX21_AIPI_BASE_ADDR + 0x16000)
+#define MX21_CSPI3_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x17000)
+#define MX21_LCDC_BASE_ADDR                     (MX21_AIPI_BASE_ADDR + 0x21000)
+#define MX21_SLCDC_BASE_ADDR                    (MX21_AIPI_BASE_ADDR + 0x22000)
+#define MX21_USBOTG_BASE_ADDR                   (MX21_AIPI_BASE_ADDR + 0x24000)
+#define MX21_EMMA_PP_BASE_ADDR                  (MX21_AIPI_BASE_ADDR + 0x26000)
+#define MX21_EMMA_PRP_BASE_ADDR                 (MX21_AIPI_BASE_ADDR + 0x26400)
+#define MX21_CCM_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x27000)
+#define MX21_SYSCTRL_BASE_ADDR                  (MX21_AIPI_BASE_ADDR + 0x27800)
+#define MX21_JAM_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x3e000)
+#define MX21_MAX_BASE_ADDR                      (MX21_AIPI_BASE_ADDR + 0x3f000)
+#define MX21_AVIC_BASE_ADDR             0x10040000
+#define MX21_SAHB1_BASE_ADDR            0x80000000
+#define MX21_SAHB1_BASE_ADDR_VIRT       0xf4100000
+#define MX21_SAHB1_SIZE                 SZ_1M
+#define MX21_CSI_BASE_ADDR                      (MX2x_SAHB1_BASE_ADDR + 0x0000)
 /* Memory regions and CS */
-#define SDRAM_BASE_ADDR         0xC0000000
+#define MX21_SDRAM_BASE_ADDR            0xc0000000
-#define CSD1_BASE_ADDR          0xC4000000
+#define MX21_CSD1_BASE_ADDR             0xc4000000
-#define CS0_BASE_ADDR           0xC8000000
+#define MX21_CS0_BASE_ADDR              0xc8000000
-#define CS1_BASE_ADDR           0xCC000000
+#define MX21_CS1_BASE_ADDR              0xcc000000
-#define CS2_BASE_ADDR           0xD0000000
+#define MX21_CS2_BASE_ADDR              0xd0000000
-#define CS3_BASE_ADDR           0xD1000000
+#define MX21_CS3_BASE_ADDR              0xd1000000
-#define CS4_BASE_ADDR           0xD2000000
+#define MX21_CS4_BASE_ADDR              0xd2000000
-#define CS5_BASE_ADDR           0xDD000000
+#define MX21_PCMCIA_MEM_BASE_ADDR       0xd4000000
-#define PCMCIA_MEM_BASE_ADDR    0xD4000000
+#define MX21_CS5_BASE_ADDR              0xdd000000
 /* NAND, SDRAM, WEIM etc controllers */
-#define X_MEMC_BASE_ADDR        0xDF000000
+#define MX21_X_MEMC_BASE_ADDR           0xdf000000
-#define X_MEMC_BASE_ADDR_VIRT   0xF4200000
+#define MX21_X_MEMC_BASE_ADDR_VIRT      0xf4200000
-#define X_MEMC_SIZE             SZ_256K
+#define MX21_X_MEMC_SIZE                SZ_256K
-#define SDRAMC_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x0000)
+#define MX21_SDRAMC_BASE_ADDR           (MX21_X_MEMC_BASE_ADDR + 0x0000)
-#define EIM_BASE_ADDR           (X_MEMC_BASE_ADDR + 0x1000)
+#define MX21_EIM_BASE_ADDR              (MX21_X_MEMC_BASE_ADDR + 0x1000)
-#define PCMCIA_CTL_BASE_ADDR    (X_MEMC_BASE_ADDR + 0x2000)
+#define MX21_PCMCIA_CTL_BASE_ADDR       (MX21_X_MEMC_BASE_ADDR + 0x2000)
-#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR + 0x3000)
+#define MX21_NFC_BASE_ADDR              (MX21_X_MEMC_BASE_ADDR + 0x3000)
-#define IRAM_BASE_ADDR          0xFFFFE800      /* internal ram */
+#define MX21_IRAM_BASE_ADDR             0xffffe800      /* internal ram */
 /* fixed interrupt numbers */
-#define MXC_INT_USBCTRL         58
+#define MX21_INT_CSPI3          6
-#define MXC_INT_USBCTRL         58
+#define MX21_INT_GPIO           8
-#define MXC_INT_USBMNP          57
+#define MX21_INT_FIRI           9
-#define MXC_INT_USBFUNC         56
+#define MX21_INT_SDHC2          10
-#define MXC_INT_USBHOST         55
+#define MX21_INT_SDHC1          11
-#define MXC_INT_USBDMA          54
+#define MX21_INT_I2C            12
-#define MXC_INT_USBWKUP         53
+#define MX21_INT_SSI2           13
-#define MXC_INT_EMMADEC         50
+#define MX21_INT_SSI1           14
-#define MXC_INT_EMMAENC         49
+#define MX21_INT_CSPI2          15
-#define MXC_INT_BMI             30
+#define MX21_INT_CSPI1          16
-#define MXC_INT_FIRI            9
+#define MX21_INT_UART4          17
+#define MX21_INT_UART3          18
+#define MX21_INT_UART2          19
+#define MX21_INT_UART1          20
+#define MX21_INT_KPP            21
+#define MX21_INT_RTC            22
+#define MX21_INT_PWM            23
+#define MX21_INT_GPT3           24
+#define MX21_INT_GPT2           25
+#define MX21_INT_GPT1           26
+#define MX21_INT_WDOG           27
+#define MX21_INT_PCMCIA         28
+#define MX21_INT_NANDFC         29
+#define MX21_INT_BMI            30
+#define MX21_INT_CSI            31
+#define MX21_INT_DMACH0         32
+#define MX21_INT_DMACH1         33
+#define MX21_INT_DMACH2         34
+#define MX21_INT_DMACH3         35
+#define MX21_INT_DMACH4         36
+#define MX21_INT_DMACH5         37
+#define MX21_INT_DMACH6         38
+#define MX21_INT_DMACH7         39
+#define MX21_INT_DMACH8         40
+#define MX21_INT_DMACH9         41
+#define MX21_INT_DMACH10        42
+#define MX21_INT_DMACH11        43
+#define MX21_INT_DMACH12        44
+#define MX21_INT_DMACH13        45
+#define MX21_INT_DMACH14        46
+#define MX21_INT_DMACH15        47
+#define MX21_INT_EMMAENC        49
+#define MX21_INT_EMMADEC        50
+#define MX21_INT_EMMAPRP        51
+#define MX21_INT_EMMAPP         52
+#define MX21_INT_USBWKUP        53
+#define MX21_INT_USBDMA         54
+#define MX21_INT_USBHOST        55
+#define MX21_INT_USBFUNC        56
+#define MX21_INT_USBMNP         57
+#define MX21_INT_USBCTRL        58
+#define MX21_INT_SLCDC          60
+#define MX21_INT_LCDC           61
 /* fixed DMA request numbers */
-#define DMA_REQ_BMI_RX          29
+#define MX21_DMA_REQ_CSPI3_RX   1
-#define DMA_REQ_BMI_TX          28
+#define MX21_DMA_REQ_CSPI3_TX   2
-#define DMA_REQ_FIRI_RX         4
+#define MX21_DMA_REQ_EXT        3
+#define MX21_DMA_REQ_FIRI_RX    4
+#define MX21_DMA_REQ_SDHC2      6
+#define MX21_DMA_REQ_SDHC1      7
+#define MX21_DMA_REQ_SSI2_RX0   8
+#define MX21_DMA_REQ_SSI2_TX0   9
+#define MX21_DMA_REQ_SSI2_RX1   10
+#define MX21_DMA_REQ_SSI2_TX1   11
+#define MX21_DMA_REQ_SSI1_RX0   12
+#define MX21_DMA_REQ_SSI1_TX0   13
+#define MX21_DMA_REQ_SSI1_RX1   14
+#define MX21_DMA_REQ_SSI1_TX1   15
+#define MX21_DMA_REQ_CSPI2_RX   16
+#define MX21_DMA_REQ_CSPI2_TX   17
+#define MX21_DMA_REQ_CSPI1_RX   18
+#define MX21_DMA_REQ_CSPI1_TX   19
+#define MX21_DMA_REQ_UART4_RX   20
+#define MX21_DMA_REQ_UART4_TX   21
+#define MX21_DMA_REQ_UART3_RX   22
+#define MX21_DMA_REQ_UART3_TX   23
+#define MX21_DMA_REQ_UART2_RX   24
+#define MX21_DMA_REQ_UART2_TX   25
+#define MX21_DMA_REQ_UART1_RX   26
+#define MX21_DMA_REQ_UART1_TX   27
+#define MX21_DMA_REQ_BMI_TX     28
+#define MX21_DMA_REQ_BMI_RX     29
+#define MX21_DMA_REQ_CSI_STAT   30
+#define MX21_DMA_REQ_CSI_RX     31
+/* these should go away */
+#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
+#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
+#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
+#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
+#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
+#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
+#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
+#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
+#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
+#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
+#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
+#define X_MEMC_SIZE MX21_X_MEMC_SIZE
+#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
+#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
+#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
+#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
+#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
+#define MXC_INT_FIRI MX21_INT_FIRI
+#define MXC_INT_BMI MX21_INT_BMI
+#define MXC_INT_EMMAENC MX21_INT_EMMAENC
+#define MXC_INT_EMMADEC MX21_INT_EMMADEC
+#define MXC_INT_USBWKUP MX21_INT_USBWKUP
+#define MXC_INT_USBDMA MX21_INT_USBDMA
+#define MXC_INT_USBHOST MX21_INT_USBHOST
+#define MXC_INT_USBFUNC MX21_INT_USBFUNC
+#define MXC_INT_USBMNP MX21_INT_USBMNP
+#define MXC_INT_USBCTRL MX21_INT_USBCTRL
+#define MXC_INT_USBCTRL MX21_INT_USBCTRL
+#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
+#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
+#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
 #endif /* __ASM_ARCH_MXC_MX21_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index ec64bd9a8ab1..91e738144804 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -1,14 +1,14 @@
 #ifndef __MACH_MX25_H__
 #define __MACH_MX25_H__
-#define MX25_AIPS1_BASE_ADDR            0x43F00000
+#define MX25_AIPS1_BASE_ADDR            0x43f00000
-#define MX25_AIPS1_BASE_ADDR_VIRT       0xFC000000
+#define MX25_AIPS1_BASE_ADDR_VIRT       0xfc000000
 #define MX25_AIPS1_SIZE                 SZ_1M
-#define MX25_AIPS2_BASE_ADDR            0x53F00000
+#define MX25_AIPS2_BASE_ADDR            0x53f00000
-#define MX25_AIPS2_BASE_ADDR_VIRT       0xFC200000
+#define MX25_AIPS2_BASE_ADDR_VIRT       0xfc200000
 #define MX25_AIPS2_SIZE                 SZ_1M
 #define MX25_AVIC_BASE_ADDR             0x68000000
-#define MX25_AVIC_BASE_ADDR_VIRT        0xFC400000
+#define MX25_AVIC_BASE_ADDR_VIRT        0xfc400000
 #define MX25_AVIC_SIZE                  SZ_1M
 #define MX25_IOMUXC_BASE_ADDR           (MX25_AIPS1_BASE_ADDR + 0xac000)
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index dc3ad9aa952a..e2ae19f51710 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -24,87 +24,198 @@
 #ifndef __ASM_ARCH_MXC_MX27_H__
 #define __ASM_ARCH_MXC_MX27_H__
-/* IRAM */
+#define MX27_AIPI_BASE_ADDR             0x10000000
-#define IRAM_BASE_ADDR          0xFFFF4C00      /* internal ram */
+#define MX27_AIPI_BASE_ADDR_VIRT        0xf4000000
+#define MX27_AIPI_SIZE                  SZ_1M
-#define MSHC_BASE_ADDR          (AIPI_BASE_ADDR + 0x18000)
+#define MX27_DMA_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x01000)
-#define GPT5_BASE_ADDR          (AIPI_BASE_ADDR + 0x19000)
+#define MX27_WDOG_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x02000)
-#define GPT4_BASE_ADDR          (AIPI_BASE_ADDR + 0x1A000)
+#define MX27_GPT1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x03000)
-#define UART5_BASE_ADDR         (AIPI_BASE_ADDR + 0x1B000)
+#define MX27_GPT2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x04000)
-#define UART6_BASE_ADDR         (AIPI_BASE_ADDR + 0x1C000)
+#define MX27_GPT3_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x05000)
-#define I2C2_BASE_ADDR          (AIPI_BASE_ADDR + 0x1D000)
+#define MX27_PWM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x06000)
-#define SDHC3_BASE_ADDR         (AIPI_BASE_ADDR + 0x1E000)
+#define MX27_RTC_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x07000)
-#define GPT6_BASE_ADDR          (AIPI_BASE_ADDR + 0x1F000)
+#define MX27_KPP_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x08000)
-#define VPU_BASE_ADDR           (AIPI_BASE_ADDR + 0x23000)
+#define MX27_OWIRE_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x09000)
-#define OTG_BASE_ADDR           USBOTG_BASE_ADDR
+#define MX27_UART1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0a000)
-#define SAHARA_BASE_ADDR        (AIPI_BASE_ADDR + 0x25000)
+#define MX27_UART2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0b000)
-#define IIM_BASE_ADDR           (AIPI_BASE_ADDR + 0x28000)
+#define MX27_UART3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0c000)
-#define RTIC_BASE_ADDR          (AIPI_BASE_ADDR + 0x2A000)
+#define MX27_UART4_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0d000)
-#define FEC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2B000)
+#define MX27_CSPI1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0e000)
-#define SCC_BASE_ADDR           (AIPI_BASE_ADDR + 0x2C000)
+#define MX27_CSPI2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0f000)
-#define ETB_BASE_ADDR           (AIPI_BASE_ADDR + 0x3B000)
+#define MX27_SSI1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x10000)
-#define ETB_RAM_BASE_ADDR       (AIPI_BASE_ADDR + 0x3C000)
+#define MX27_SSI2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x11000)
+#define MX27_I2C_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x12000)
+#define MX27_SDHC1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x13000)
+#define MX27_SDHC2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x14000)
+#define MX27_GPIO_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x15000)
+#define MX27_AUDMUX_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x16000)
+#define MX27_CSPI3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x17000)
+#define MX27_MSHC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x18000)
+#define MX27_GPT5_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x19000)
+#define MX27_GPT4_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1a000)
+#define MX27_UART5_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1b000)
+#define MX27_UART6_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1c000)
+#define MX27_I2C2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1d000)
+#define MX27_SDHC3_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x1e000)
+#define MX27_GPT6_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x1f000)
+#define MX27_LCDC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x21000)
+#define MX27_SLCDC_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x22000)
+#define MX27_VPU_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x23000)
+#define MX27_USBOTG_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x24000)
+#define MX27_OTG_BASE_ADDR                      MX27_USBOTG_BASE_ADDR
+#define MX27_SAHARA_BASE_ADDR                   (MX27_AIPI_BASE_ADDR + 0x25000)
+#define MX27_EMMA_PP_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x26000)
+#define MX27_EMMA_PRP_BASE_ADDR                 (MX27_AIPI_BASE_ADDR + 0x26400)
+#define MX27_CCM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x27000)
+#define MX27_SYSCTRL_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x27800)
+#define MX27_IIM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x28000)
+#define MX27_RTIC_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x2a000)
+#define MX27_FEC_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x2b000)
+#define MX27_SCC_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x2c000)
+#define MX27_ETB_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x3b000)
+#define MX27_ETB_RAM_BASE_ADDR                  (MX27_AIPI_BASE_ADDR + 0x3c000)
+#define MX27_JAM_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x3e000)
+#define MX27_MAX_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x3f000)
+#define MX27_AVIC_BASE_ADDR             0x10040000
 /* ROM patch */
-#define ROMP_BASE_ADDR          0x10041000
+#define MX27_ROMP_BASE_ADDR             0x10041000
-#define ATA_BASE_ADDR           (SAHB1_BASE_ADDR + 0x1000)
+#define MX27_SAHB1_BASE_ADDR            0x80000000
+#define MX27_SAHB1_BASE_ADDR_VIRT       0xf4100000
+#define MX27_SAHB1_SIZE                 SZ_1M
+#define MX27_CSI_BASE_ADDR                      (MX27_SAHB1_BASE_ADDR + 0x0000)
+#define MX27_ATA_BASE_ADDR                      (MX27_SAHB1_BASE_ADDR + 0x1000)
 /* Memory regions and CS */
-#define SDRAM_BASE_ADDR         0xA0000000
+#define MX27_SDRAM_BASE_ADDR            0xa0000000
-#define CSD1_BASE_ADDR          0xB0000000
+#define MX27_CSD1_BASE_ADDR             0xb0000000
-#define CS0_BASE_ADDR           0xC0000000
+#define MX27_CS0_BASE_ADDR              0xc0000000
-#define CS1_BASE_ADDR           0xC8000000
+#define MX27_CS1_BASE_ADDR              0xc8000000
-#define CS2_BASE_ADDR           0xD0000000
+#define MX27_CS2_BASE_ADDR              0xd0000000
-#define CS3_BASE_ADDR           0xD2000000
+#define MX27_CS3_BASE_ADDR              0xd2000000
-#define CS4_BASE_ADDR           0xD4000000
+#define MX27_CS4_BASE_ADDR              0xd4000000
-#define CS5_BASE_ADDR           0xD6000000
+#define MX27_CS5_BASE_ADDR              0xd6000000
-#define PCMCIA_MEM_BASE_ADDR    0xDC000000
 /* NAND, SDRAM, WEIM, M3IF, EMI controllers */
-#define X_MEMC_BASE_ADDR        0xD8000000
+#define MX27_X_MEMC_BASE_ADDR           0xd8000000
-#define X_MEMC_BASE_ADDR_VIRT   0xF4200000
+#define MX27_X_MEMC_BASE_ADDR_VIRT      0xf4200000
-#define X_MEMC_SIZE             SZ_1M
+#define MX27_X_MEMC_SIZE                SZ_1M
+#define MX27_NFC_BASE_ADDR                      (MX27_X_MEMC_BASE_ADDR)
+#define MX27_SDRAMC_BASE_ADDR                   (MX27_X_MEMC_BASE_ADDR + 0x1000)
+#define MX27_WEIM_BASE_ADDR                     (MX27_X_MEMC_BASE_ADDR + 0x2000)
+#define MX27_M3IF_BASE_ADDR                     (MX27_X_MEMC_BASE_ADDR + 0x3000)
+#define MX27_PCMCIA_CTL_BASE_ADDR               (MX27_X_MEMC_BASE_ADDR + 0x4000)
-#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR)
+#define MX27_PCMCIA_MEM_BASE_ADDR       0xdc000000
-#define SDRAMC_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
-#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
+/* IRAM */
-#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
+#define MX27_IRAM_BASE_ADDR             0xffff4c00      /* internal ram */
-#define PCMCIA_CTL_BASE_ADDR    (X_MEMC_BASE_ADDR + 0x4000)
 /* fixed interrupt numbers */
-#define MXC_INT_CCM             63
+#define MX27_INT_I2C2           1
-#define MXC_INT_IIM             62
+#define MX27_INT_GPT6           2
-#define MXC_INT_SAHARA          59
+#define MX27_INT_GPT5           3
-#define MXC_INT_SCC_SCM         58
+#define MX27_INT_GPT4           4
-#define MXC_INT_SCC_SMN         57
+#define MX27_INT_RTIC           5
-#define MXC_INT_USB3            56
+#define MX27_INT_CSPI3          6
-#define MXC_INT_USB2            55
+#define MX27_INT_SDHC           7
-#define MXC_INT_USB1            54
+#define MX27_INT_GPIO           8
-#define MXC_INT_VPU             53
+#define MX27_INT_SDHC3          9
-#define MXC_INT_FEC             50
+#define MX27_INT_SDHC2          10
-#define MXC_INT_UART5           49
+#define MX27_INT_SDHC1          11
-#define MXC_INT_UART6           48
+#define MX27_INT_I2C            12
-#define MXC_INT_ATA             30
+#define MX27_INT_SSI2           13
-#define MXC_INT_SDHC3           9
+#define MX27_INT_SSI1           14
-#define MXC_INT_SDHC            7
+#define MX27_INT_CSPI2          15
-#define MXC_INT_RTIC            5
+#define MX27_INT_CSPI1          16
-#define MXC_INT_GPT4            4
+#define MX27_INT_UART4          17
-#define MXC_INT_GPT5            3
+#define MX27_INT_UART3          18
-#define MXC_INT_GPT6            2
+#define MX27_INT_UART2          19
-#define MXC_INT_I2C2            1
+#define MX27_INT_UART1          20
+#define MX27_INT_KPP            21
+#define MX27_INT_RTC            22
+#define MX27_INT_PWM            23
+#define MX27_INT_GPT3           24
+#define MX27_INT_GPT2           25
+#define MX27_INT_GPT1           26
+#define MX27_INT_WDOG           27
+#define MX27_INT_PCMCIA         28
+#define MX27_INT_NANDFC         29
+#define MX27_INT_ATA            30
+#define MX27_INT_CSI            31
+#define MX27_INT_DMACH0         32
+#define MX27_INT_DMACH1         33
+#define MX27_INT_DMACH2         34
+#define MX27_INT_DMACH3         35
+#define MX27_INT_DMACH4         36
+#define MX27_INT_DMACH5         37
+#define MX27_INT_DMACH6         38
+#define MX27_INT_DMACH7         39
+#define MX27_INT_DMACH8         40
+#define MX27_INT_DMACH9         41
+#define MX27_INT_DMACH10        42
+#define MX27_INT_DMACH11        43
+#define MX27_INT_DMACH12        44
+#define MX27_INT_DMACH13        45
+#define MX27_INT_DMACH14        46
+#define MX27_INT_DMACH15        47
+#define MX27_INT_UART6          48
+#define MX27_INT_UART5          49
+#define MX27_INT_FEC            50
+#define MX27_INT_EMMAPRP        51
+#define MX27_INT_EMMAPP         52
+#define MX27_INT_VPU            53
+#define MX27_INT_USB1           54
+#define MX27_INT_USB2           55
+#define MX27_INT_USB3           56
+#define MX27_INT_SCC_SMN        57
+#define MX27_INT_SCC_SCM        58
+#define MX27_INT_SAHARA         59
+#define MX27_INT_SLCDC          60
+#define MX27_INT_LCDC           61
+#define MX27_INT_IIM            62
+#define MX27_INT_CCM            63
 /* fixed DMA request numbers */
-#define DMA_REQ_NFC             37
+#define MX27_DMA_REQ_CSPI3_RX   1
-#define DMA_REQ_SDHC3           36
+#define MX27_DMA_REQ_CSPI3_TX   2
-#define DMA_REQ_UART6_RX        35
+#define MX27_DMA_REQ_EXT        3
-#define DMA_REQ_UART6_TX        34
+#define MX27_DMA_REQ_MSHC       4
-#define DMA_REQ_UART5_RX        33
+#define MX27_DMA_REQ_SDHC2      6
-#define DMA_REQ_UART5_TX        32
+#define MX27_DMA_REQ_SDHC1      7
-#define DMA_REQ_ATA_RCV         29
+#define MX27_DMA_REQ_SSI2_RX0   8
-#define DMA_REQ_ATA_TX          28
+#define MX27_DMA_REQ_SSI2_TX0   9
-#define DMA_REQ_MSHC            4
+#define MX27_DMA_REQ_SSI2_RX1   10
+#define MX27_DMA_REQ_SSI2_TX1   11
+#define MX27_DMA_REQ_SSI1_RX0   12
+#define MX27_DMA_REQ_SSI1_TX0   13
+#define MX27_DMA_REQ_SSI1_RX1   14
+#define MX27_DMA_REQ_SSI1_TX1   15
+#define MX27_DMA_REQ_CSPI2_RX   16
+#define MX27_DMA_REQ_CSPI2_TX   17
+#define MX27_DMA_REQ_CSPI1_RX   18
+#define MX27_DMA_REQ_CSPI1_TX   19
+#define MX27_DMA_REQ_UART4_RX   20
+#define MX27_DMA_REQ_UART4_TX   21
+#define MX27_DMA_REQ_UART3_RX   22
+#define MX27_DMA_REQ_UART3_TX   23
+#define MX27_DMA_REQ_UART2_RX   24
+#define MX27_DMA_REQ_UART2_TX   25
+#define MX27_DMA_REQ_UART1_RX   26
+#define MX27_DMA_REQ_UART1_TX   27
+#define MX27_DMA_REQ_ATA_TX     28
+#define MX27_DMA_REQ_ATA_RCV    29
+#define MX27_DMA_REQ_CSI_STAT   30
+#define MX27_DMA_REQ_CSI_RX     31
+#define MX27_DMA_REQ_UART5_TX   32
+#define MX27_DMA_REQ_UART5_RX   33
+#define MX27_DMA_REQ_UART6_TX   34
+#define MX27_DMA_REQ_UART6_RX   35
+#define MX27_DMA_REQ_SDHC3      36
+#define MX27_DMA_REQ_NFC        37
 /* silicon revisions specific to i.MX27 */
 #define CHIP_REV_1_0            0x00
@@ -114,6 +225,72 @@
 extern int mx27_revision(void);
 #endif
-/* Mandatory defines used globally */
+/* these should go away */
+#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
+#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
+#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
+#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
+#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
+#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
+#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
+#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
+#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
+#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
+#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
+#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
+#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
+#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
+#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
+#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
+#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
+#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
+#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
+#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
+#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
+#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
+#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
+#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
+#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
+#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
+#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
+#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
+#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
+#define X_MEMC_SIZE MX27_X_MEMC_SIZE
+#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
+#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
+#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
+#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
+#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
+#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
+#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
+#define MXC_INT_I2C2 MX27_INT_I2C2
+#define MXC_INT_GPT6 MX27_INT_GPT6
+#define MXC_INT_GPT5 MX27_INT_GPT5
+#define MXC_INT_GPT4 MX27_INT_GPT4
+#define MXC_INT_RTIC MX27_INT_RTIC
+#define MXC_INT_SDHC MX27_INT_SDHC
+#define MXC_INT_SDHC3 MX27_INT_SDHC3
+#define MXC_INT_ATA MX27_INT_ATA
+#define MXC_INT_UART6 MX27_INT_UART6
+#define MXC_INT_UART5 MX27_INT_UART5
+#define MXC_INT_FEC MX27_INT_FEC
+#define MXC_INT_VPU MX27_INT_VPU
+#define MXC_INT_USB1 MX27_INT_USB1
+#define MXC_INT_USB2 MX27_INT_USB2
+#define MXC_INT_USB3 MX27_INT_USB3
+#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
+#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
+#define MXC_INT_SAHARA MX27_INT_SAHARA
+#define MXC_INT_IIM MX27_INT_IIM
+#define MXC_INT_CCM MX27_INT_CCM
+#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
+#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
+#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
+#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
+#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
+#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
+#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
+#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
+#define DMA_REQ_NFC MX27_DMA_REQ_NFC
 #endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index db5d921e0fe6..f2eaf140ed02 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -25,51 +25,49 @@
 /* The following addresses are common between i.MX21 and i.MX27 */
-/* Register offests */
+/* Register offsets */
-#define AIPI_BASE_ADDR          0x10000000
+#define MX2x_AIPI_BASE_ADDR             0x10000000
-#define AIPI_BASE_ADDR_VIRT     0xF4000000
+#define MX2x_AIPI_BASE_ADDR_VIRT        0xf4000000
-#define AIPI_SIZE               SZ_1M
+#define MX2x_AIPI_SIZE                  SZ_1M
+#define MX2x_DMA_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x01000)
-#define DMA_BASE_ADDR           (AIPI_BASE_ADDR + 0x01000)
+#define MX2x_WDOG_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x02000)
-#define WDOG_BASE_ADDR          (AIPI_BASE_ADDR + 0x02000)
+#define MX2x_GPT1_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x03000)
-#define GPT1_BASE_ADDR          (AIPI_BASE_ADDR + 0x03000)
+#define MX2x_GPT2_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x04000)
-#define GPT2_BASE_ADDR          (AIPI_BASE_ADDR + 0x04000)
+#define MX2x_GPT3_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x05000)
-#define GPT3_BASE_ADDR          (AIPI_BASE_ADDR + 0x05000)
+#define MX2x_PWM_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x06000)
-#define PWM_BASE_ADDR           (AIPI_BASE_ADDR + 0x06000)
+#define MX2x_RTC_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x07000)
-#define RTC_BASE_ADDR           (AIPI_BASE_ADDR + 0x07000)
+#define MX2x_KPP_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x08000)
-#define KPP_BASE_ADDR           (AIPI_BASE_ADDR + 0x08000)
+#define MX2x_OWIRE_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x09000)
-#define OWIRE_BASE_ADDR         (AIPI_BASE_ADDR + 0x09000)
+#define MX2x_UART1_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0a000)
-#define UART1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0A000)
+#define MX2x_UART2_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0b000)
-#define UART2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0B000)
+#define MX2x_UART3_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0c000)
-#define UART3_BASE_ADDR         (AIPI_BASE_ADDR + 0x0C000)
+#define MX2x_UART4_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0d000)
-#define UART4_BASE_ADDR         (AIPI_BASE_ADDR + 0x0D000)
+#define MX2x_CSPI1_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0e000)
-#define CSPI1_BASE_ADDR         (AIPI_BASE_ADDR + 0x0E000)
+#define MX2x_CSPI2_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x0f000)
-#define CSPI2_BASE_ADDR         (AIPI_BASE_ADDR + 0x0F000)
+#define MX2x_SSI1_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x10000)
-#define SSI1_BASE_ADDR          (AIPI_BASE_ADDR + 0x10000)
+#define MX2x_SSI2_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x11000)
-#define SSI2_BASE_ADDR          (AIPI_BASE_ADDR + 0x11000)
+#define MX2x_I2C_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x12000)
-#define I2C_BASE_ADDR           (AIPI_BASE_ADDR + 0x12000)
+#define MX2x_SDHC1_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x13000)
-#define SDHC1_BASE_ADDR         (AIPI_BASE_ADDR + 0x13000)
+#define MX2x_SDHC2_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x14000)
-#define SDHC2_BASE_ADDR         (AIPI_BASE_ADDR + 0x14000)
+#define MX2x_GPIO_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x15000)
-#define GPIO_BASE_ADDR          (AIPI_BASE_ADDR + 0x15000)
+#define MX2x_AUDMUX_BASE_ADDR                   (MX2x_AIPI_BASE_ADDR + 0x16000)
-#define AUDMUX_BASE_ADDR        (AIPI_BASE_ADDR + 0x16000)
+#define MX2x_CSPI3_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x17000)
-#define CSPI3_BASE_ADDR         (AIPI_BASE_ADDR + 0x17000)
+#define MX2x_LCDC_BASE_ADDR                     (MX2x_AIPI_BASE_ADDR + 0x21000)
-#define LCDC_BASE_ADDR          (AIPI_BASE_ADDR + 0x21000)
+#define MX2x_SLCDC_BASE_ADDR                    (MX2x_AIPI_BASE_ADDR + 0x22000)
-#define SLCDC_BASE_ADDR         (AIPI_BASE_ADDR + 0x22000)
+#define MX2x_USBOTG_BASE_ADDR                   (MX2x_AIPI_BASE_ADDR + 0x24000)
-#define USBOTG_BASE_ADDR        (AIPI_BASE_ADDR + 0x24000)
+#define MX2x_EMMA_PP_BASE_ADDR                  (MX2x_AIPI_BASE_ADDR + 0x26000)
-#define EMMA_PP_BASE_ADDR       (AIPI_BASE_ADDR + 0x26000)
+#define MX2x_EMMA_PRP_BASE_ADDR                 (MX2x_AIPI_BASE_ADDR + 0x26400)
-#define EMMA_PRP_BASE_ADDR      (AIPI_BASE_ADDR + 0x26400)
+#define MX2x_CCM_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x27000)
-#define CCM_BASE_ADDR           (AIPI_BASE_ADDR + 0x27000)
+#define MX2x_SYSCTRL_BASE_ADDR                  (MX2x_AIPI_BASE_ADDR + 0x27800)
-#define SYSCTRL_BASE_ADDR       (AIPI_BASE_ADDR + 0x27800)
+#define MX2x_JAM_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x3e000)
-#define JAM_BASE_ADDR           (AIPI_BASE_ADDR + 0x3E000)
+#define MX2x_MAX_BASE_ADDR                      (MX2x_AIPI_BASE_ADDR + 0x3f000)
-#define MAX_BASE_ADDR           (AIPI_BASE_ADDR + 0x3F000)
+#define MX2x_AVIC_BASE_ADDR             0x10040000
-#define AVIC_BASE_ADDR          0x10040000
+#define MX2x_SAHB1_BASE_ADDR            0x80000000
-#define SAHB1_BASE_ADDR         0x80000000
+#define MX2x_SAHB1_BASE_ADDR_VIRT       0xf4100000
-#define SAHB1_BASE_ADDR_VIRT    0xF4100000
+#define MX2x_SAHB1_SIZE                 SZ_1M
-#define SAHB1_SIZE              SZ_1M
+#define MX2x_CSI_BASE_ADDR                      (MX2x_SAHB1_BASE_ADDR + 0x0000)
-#define CSI_BASE_ADDR           (SAHB1_BASE_ADDR + 0x0000)
 /*
 * This macro defines the physical to virtual address mapping for all the
@@ -105,78 +103,189 @@
        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
 /* fixed interrupt numbers */
-#define MXC_INT_LCDC            61
+#define MX2x_INT_CSPI3          6
-#define MXC_INT_SLCDC           60
+#define MX2x_INT_GPIO           8
-#define MXC_INT_EMMAPP          52
+#define MX2x_INT_SDHC2          10
-#define MXC_INT_EMMAPRP         51
+#define MX2x_INT_SDHC1          11
-#define MXC_INT_DMACH15         47
+#define MX2x_INT_I2C            12
-#define MXC_INT_DMACH14         46
+#define MX2x_INT_SSI2           13
-#define MXC_INT_DMACH13         45
+#define MX2x_INT_SSI1           14
-#define MXC_INT_DMACH12         44
+#define MX2x_INT_CSPI2          15
-#define MXC_INT_DMACH11         43
+#define MX2x_INT_CSPI1          16
-#define MXC_INT_DMACH10         42
+#define MX2x_INT_UART4          17
-#define MXC_INT_DMACH9          41
+#define MX2x_INT_UART3          18
-#define MXC_INT_DMACH8          40
+#define MX2x_INT_UART2          19
-#define MXC_INT_DMACH7          39
+#define MX2x_INT_UART1          20
-#define MXC_INT_DMACH6          38
+#define MX2x_INT_KPP            21
-#define MXC_INT_DMACH5          37
+#define MX2x_INT_RTC            22
-#define MXC_INT_DMACH4          36
+#define MX2x_INT_PWM            23
-#define MXC_INT_DMACH3          35
+#define MX2x_INT_GPT3           24
-#define MXC_INT_DMACH2          34
+#define MX2x_INT_GPT2           25
-#define MXC_INT_DMACH1          33
+#define MX2x_INT_GPT1           26
-#define MXC_INT_DMACH0          32
+#define MX2x_INT_WDOG           27
-#define MXC_INT_CSI             31
+#define MX2x_INT_PCMCIA         28
-#define MXC_INT_NANDFC          29
+#define MX2x_INT_NANDFC         29
-#define MXC_INT_PCMCIA          28
+#define MX2x_INT_CSI            31
-#define MXC_INT_WDOG            27
+#define MX2x_INT_DMACH0         32
-#define MXC_INT_GPT1            26
+#define MX2x_INT_DMACH1         33
-#define MXC_INT_GPT2            25
+#define MX2x_INT_DMACH2         34
-#define MXC_INT_GPT3            24
+#define MX2x_INT_DMACH3         35
-#define MXC_INT_GPT             INT_GPT1
+#define MX2x_INT_DMACH4         36
-#define MXC_INT_PWM             23
+#define MX2x_INT_DMACH5         37
-#define MXC_INT_RTC             22
+#define MX2x_INT_DMACH6         38
-#define MXC_INT_KPP             21
+#define MX2x_INT_DMACH7         39
-#define MXC_INT_UART1           20
+#define MX2x_INT_DMACH8         40
-#define MXC_INT_UART2           19
+#define MX2x_INT_DMACH9         41
-#define MXC_INT_UART3           18
+#define MX2x_INT_DMACH10        42
-#define MXC_INT_UART4           17
+#define MX2x_INT_DMACH11        43
-#define MXC_INT_CSPI1           16
+#define MX2x_INT_DMACH12        44
-#define MXC_INT_CSPI2           15
+#define MX2x_INT_DMACH13        45
-#define MXC_INT_SSI1            14
+#define MX2x_INT_DMACH14        46
-#define MXC_INT_SSI2            13
+#define MX2x_INT_DMACH15        47
-#define MXC_INT_I2C             12
+#define MX2x_INT_EMMAPRP        51
-#define MXC_INT_SDHC1           11
+#define MX2x_INT_EMMAPP         52
-#define MXC_INT_SDHC2           10
+#define MX2x_INT_SLCDC          60
-#define MXC_INT_GPIO            8
+#define MX2x_INT_LCDC           61
-#define MXC_INT_CSPI3           6
 /* fixed DMA request numbers */
-#define DMA_REQ_CSI_RX          31
+#define MX2x_DMA_REQ_CSPI3_RX   1
-#define DMA_REQ_CSI_STAT        30
+#define MX2x_DMA_REQ_CSPI3_TX   2
-#define DMA_REQ_UART1_TX        27
+#define MX2x_DMA_REQ_EXT        3
-#define DMA_REQ_UART1_RX        26
+#define MX2x_DMA_REQ_SDHC2      6
-#define DMA_REQ_UART2_TX        25
+#define MX2x_DMA_REQ_SDHC1      7
-#define DMA_REQ_UART2_RX        24
+#define MX2x_DMA_REQ_SSI2_RX0   8
-#define DMA_REQ_UART3_TX        23
+#define MX2x_DMA_REQ_SSI2_TX0   9
-#define DMA_REQ_UART3_RX        22
+#define MX2x_DMA_REQ_SSI2_RX1   10
-#define DMA_REQ_UART4_TX        21
+#define MX2x_DMA_REQ_SSI2_TX1   11
-#define DMA_REQ_UART4_RX        20
+#define MX2x_DMA_REQ_SSI1_RX0   12
-#define DMA_REQ_CSPI1_TX        19
+#define MX2x_DMA_REQ_SSI1_TX0   13
-#define DMA_REQ_CSPI1_RX        18
+#define MX2x_DMA_REQ_SSI1_RX1   14
-#define DMA_REQ_CSPI2_TX        17
+#define MX2x_DMA_REQ_SSI1_TX1   15
-#define DMA_REQ_CSPI2_RX        16
+#define MX2x_DMA_REQ_CSPI2_RX   16
-#define DMA_REQ_SSI1_TX1        15
+#define MX2x_DMA_REQ_CSPI2_TX   17
-#define DMA_REQ_SSI1_RX1        14
+#define MX2x_DMA_REQ_CSPI1_RX   18
-#define DMA_REQ_SSI1_TX0        13
+#define MX2x_DMA_REQ_CSPI1_TX   19
-#define DMA_REQ_SSI1_RX0        12
+#define MX2x_DMA_REQ_UART4_RX   20
-#define DMA_REQ_SSI2_TX1        11
+#define MX2x_DMA_REQ_UART4_TX   21
-#define DMA_REQ_SSI2_RX1        10
+#define MX2x_DMA_REQ_UART3_RX   22
-#define DMA_REQ_SSI2_TX0        9
+#define MX2x_DMA_REQ_UART3_TX   23
-#define DMA_REQ_SSI2_RX0        8
+#define MX2x_DMA_REQ_UART2_RX   24
-#define DMA_REQ_SDHC1           7
+#define MX2x_DMA_REQ_UART2_TX   25
-#define DMA_REQ_SDHC2           6
+#define MX2x_DMA_REQ_UART1_RX   26
-#define DMA_REQ_EXT             3
+#define MX2x_DMA_REQ_UART1_TX   27
-#define DMA_REQ_CSPI3_TX        2
+#define MX2x_DMA_REQ_CSI_STAT   30
-#define DMA_REQ_CSPI3_RX        1
+#define MX2x_DMA_REQ_CSI_RX     31
+/* these should go away */
+#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
+#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
+#define AIPI_SIZE MX2x_AIPI_SIZE
+#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
+#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
+#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
+#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
+#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
+#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
+#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
+#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
+#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
+#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
+#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
+#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
+#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
+#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
+#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
+#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
+#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
+#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
+#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
+#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
+#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
+#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
+#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
+#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
+#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
+#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
+#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
+#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
+#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
+#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
+#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
+#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
+#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
+#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
+#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
+#define SAHB1_SIZE MX2x_SAHB1_SIZE
+#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
+#define MXC_INT_CSPI3 MX2x_INT_CSPI3
+#define MXC_INT_GPIO MX2x_INT_GPIO
+#define MXC_INT_SDHC2 MX2x_INT_SDHC2
+#define MXC_INT_SDHC1 MX2x_INT_SDHC1
+#define MXC_INT_I2C MX2x_INT_I2C
+#define MXC_INT_SSI2 MX2x_INT_SSI2
+#define MXC_INT_SSI1 MX2x_INT_SSI1
+#define MXC_INT_CSPI2 MX2x_INT_CSPI2
+#define MXC_INT_CSPI1 MX2x_INT_CSPI1
+#define MXC_INT_UART4 MX2x_INT_UART4
+#define MXC_INT_UART3 MX2x_INT_UART3
+#define MXC_INT_UART2 MX2x_INT_UART2
+#define MXC_INT_UART1 MX2x_INT_UART1
+#define MXC_INT_KPP MX2x_INT_KPP
+#define MXC_INT_RTC MX2x_INT_RTC
+#define MXC_INT_PWM MX2x_INT_PWM
+#define MXC_INT_GPT3 MX2x_INT_GPT3
+#define MXC_INT_GPT2 MX2x_INT_GPT2
+#define MXC_INT_GPT1 MX2x_INT_GPT1
+#define MXC_INT_WDOG MX2x_INT_WDOG
+#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
+#define MXC_INT_NANDFC MX2x_INT_NANDFC
+#define MXC_INT_CSI MX2x_INT_CSI
+#define MXC_INT_DMACH0 MX2x_INT_DMACH0
+#define MXC_INT_DMACH1 MX2x_INT_DMACH1
+#define MXC_INT_DMACH2 MX2x_INT_DMACH2
+#define MXC_INT_DMACH3 MX2x_INT_DMACH3
+#define MXC_INT_DMACH4 MX2x_INT_DMACH4
+#define MXC_INT_DMACH5 MX2x_INT_DMACH5
+#define MXC_INT_DMACH6 MX2x_INT_DMACH6
+#define MXC_INT_DMACH7 MX2x_INT_DMACH7
+#define MXC_INT_DMACH8 MX2x_INT_DMACH8
+#define MXC_INT_DMACH9 MX2x_INT_DMACH9
+#define MXC_INT_DMACH10 MX2x_INT_DMACH10
+#define MXC_INT_DMACH11 MX2x_INT_DMACH11
+#define MXC_INT_DMACH12 MX2x_INT_DMACH12
+#define MXC_INT_DMACH13 MX2x_INT_DMACH13
+#define MXC_INT_DMACH14 MX2x_INT_DMACH14
+#define MXC_INT_DMACH15 MX2x_INT_DMACH15
+#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
+#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
+#define MXC_INT_SLCDC MX2x_INT_SLCDC
+#define MXC_INT_LCDC MX2x_INT_LCDC
+#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
+#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
+#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
+#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
+#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
+#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
+#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
+#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
+#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
+#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
+#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
+#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
+#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
+#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
+#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
+#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
+#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
+#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
+#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
+#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
+#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
+#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
+#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
+#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
+#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
+#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
+#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
 #endif /* __ASM_ARCH_MXC_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 14ac0dcc82f4..b8b47d139eb5 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -1,45 +1,218 @@
 /*
 * IRAM
 */
-#define MX31_IRAM_BASE_ADDR             0x1FFC0000      /* internal ram */
+#define MX31_IRAM_BASE_ADDR             0x1ffc0000      /* internal ram */
 #define MX31_IRAM_SIZE                  SZ_16K
-#define MX31_OTG_BASE_ADDR      (AIPS1_BASE_ADDR + 0x00088000)
+#define MX31_L2CC_BASE_ADDR             0x30000000
-#define ATA_BASE_ADDR           (AIPS1_BASE_ADDR + 0x0008C000)
+#define MX31_L2CC_SIZE                  SZ_1M
-#define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B0000)
-#define UART5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B4000)
-#define MMC_SDHC1_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00004000)
+#define MX31_AIPS1_BASE_ADDR            0x43f00000
-#define MMC_SDHC2_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00008000)
+#define MX31_AIPS1_BASE_ADDR_VIRT       0xfc000000
-#define SIM1_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00018000)
+#define MX31_AIPS1_SIZE                 SZ_1M
-#define IIM_BASE_ADDR           (SPBA0_BASE_ADDR + 0x0001C000)
+#define MX31_MAX_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x04000)
+#define MX31_EVTMON_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0x08000)
+#define MX31_CLKCTL_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0x0c000)
+#define MX31_ETB_SLOT4_BASE_ADDR                (MX31_AIPS1_BASE_ADDR + 0x10000)
+#define MX31_ETB_SLOT5_BASE_ADDR                (MX31_AIPS1_BASE_ADDR + 0x14000)
+#define MX31_ECT_CTIO_BASE_ADDR                 (MX31_AIPS1_BASE_ADDR + 0x18000)
+#define MX31_I2C_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x80000)
+#define MX31_I2C3_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x84000)
+#define MX31_OTG_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define MX31_ATA_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x8c000)
+#define MX31_UART1_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x90000)
+#define MX31_UART2_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x94000)
+#define MX31_I2C2_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x98000)
+#define MX31_OWIRE_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0x9c000)
+#define MX31_SSI1_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0xa0000)
+#define MX31_CSPI1_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0xa4000)
+#define MX31_KPP_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0xa8000)
+#define MX31_IOMUXC_BASE_ADDR                   (MX31_AIPS1_BASE_ADDR + 0xac000)
+#define MX31_UART4_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0xb0000)
+#define MX31_UART5_BASE_ADDR                    (MX31_AIPS1_BASE_ADDR + 0xb4000)
+#define MX31_ECT_IP1_BASE_ADDR                  (MX31_AIPS1_BASE_ADDR + 0xb8000)
+#define MX31_ECT_IP2_BASE_ADDR                  (MX31_AIPS1_BASE_ADDR + 0xbc000)
-#define CSPI3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00084000)
+#define MX31_SPBA0_BASE_ADDR            0x50000000
-#define FIRI_BASE_ADDR          (AIPS2_BASE_ADDR + 0x0008C000)
+#define MX31_SPBA0_BASE_ADDR_VIRT       0xfc100000
-#define SCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AE000)
+#define MX31_SPBA0_SIZE                 SZ_1M
-#define SMN_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AF000)
+#define MX31_MMC_SDHC1_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x04000)
-#define MPEG4_ENC_BASE_ADDR     (AIPS2_BASE_ADDR + 0x000C8000)
+#define MX31_MMC_SDHC2_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x08000)
+#define MX31_UART3_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x0c000)
+#define MX31_CSPI2_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x10000)
+#define MX31_SSI2_BASE_ADDR                     (MX31_SPBA0_BASE_ADDR + 0x14000)
+#define MX31_SIM1_BASE_ADDR                     (MX31_SPBA0_BASE_ADDR + 0x18000)
+#define MX31_IIM_BASE_ADDR                      (MX31_SPBA0_BASE_ADDR + 0x1c000)
+#define MX31_ATA_DMA_BASE_ADDR                  (MX31_SPBA0_BASE_ADDR + 0x20000)
+#define MX31_MSHC1_BASE_ADDR                    (MX31_SPBA0_BASE_ADDR + 0x24000)
+#define MX31_SPBA_CTRL_BASE_ADDR                (MX31_SPBA0_BASE_ADDR + 0x3c000)
-#define MX31_NFC_BASE_ADDR      (X_MEMC_BASE_ADDR + 0x0000)
+#define MX31_AIPS2_BASE_ADDR            0x53f00000
+#define MX31_AIPS2_BASE_ADDR_VIRT       0xfc200000
+#define MX31_AIPS2_SIZE                 SZ_1M
+#define MX31_CCM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0x80000)
+#define MX31_CSPI3_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x84000)
+#define MX31_FIRI_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0x8c000)
+#define MX31_GPT1_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0x90000)
+#define MX31_EPIT1_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x94000)
+#define MX31_EPIT2_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0x98000)
+#define MX31_GPIO3_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0xa4000)
+#define MX31_SCC_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xac000)
+#define MX31_SCM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xae000)
+#define MX31_SMN_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xaf000)
+#define MX31_RNGA_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xb0000)
+#define MX31_IPU_CTRL_BASE_ADDR                 (MX31_AIPS2_BASE_ADDR + 0xc0000)
+#define MX31_AUDMUX_BASE_ADDR                   (MX31_AIPS2_BASE_ADDR + 0xc4000)
+#define MX31_MPEG4_ENC_BASE_ADDR                (MX31_AIPS2_BASE_ADDR + 0xc8000)
+#define MX31_GPIO1_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0xcc000)
+#define MX31_GPIO2_BASE_ADDR                    (MX31_AIPS2_BASE_ADDR + 0xd0000)
+#define MX31_SDMA_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xd4000)
+#define MX31_RTC_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xd8000)
+#define MX31_WDOG_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xdc000)
+#define MX31_PWM_BASE_ADDR                      (MX31_AIPS2_BASE_ADDR + 0xe0000)
+#define MX31_RTIC_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xec000)
-#define MXC_INT_MPEG4_ENCODER   5
+#define MX31_ROMP_BASE_ADDR             0x60000000
-#define MXC_INT_FIRI            7
+#define MX31_ROMP_BASE_ADDR_VIRT        0xfc500000
+#define MX31_ROMP_SIZE                  SZ_1M
+#define MX31_AVIC_BASE_ADDR             0x68000000
+#define MX31_AVIC_BASE_ADDR_VIRT        0xfc400000
+#define MX31_AVIC_SIZE                  SZ_1M
+#define MX31_IPU_MEM_BASE_ADDR          0x70000000
+#define MX31_CSD0_BASE_ADDR             0x80000000
+#define MX31_CSD1_BASE_ADDR             0x90000000
+#define MX31_CS0_BASE_ADDR              0xa0000000
+#define MX31_CS1_BASE_ADDR              0xa8000000
+#define MX31_CS2_BASE_ADDR              0xb0000000
+#define MX31_CS3_BASE_ADDR              0xb2000000
+#define MX31_CS4_BASE_ADDR              0xb4000000
+#define MX31_CS4_BASE_ADDR_VIRT         0xf4000000
+#define MX31_CS4_SIZE                   SZ_32M
+#define MX31_CS5_BASE_ADDR              0xb6000000
+#define MX31_CS5_BASE_ADDR_VIRT         0xf6000000
+#define MX31_CS5_SIZE                   SZ_32M
+#define MX31_X_MEMC_BASE_ADDR           0xb8000000
+#define MX31_X_MEMC_BASE_ADDR_VIRT      0xfc320000
+#define MX31_X_MEMC_SIZE                SZ_64K
+#define MX31_NFC_BASE_ADDR                      (MX31_X_MEMC_BASE_ADDR + 0x0000)
+#define MX31_ESDCTL_BASE_ADDR                   (MX31_X_MEMC_BASE_ADDR + 0x1000)
+#define MX31_WEIM_BASE_ADDR                     (MX31_X_MEMC_BASE_ADDR + 0x2000)
+#define MX31_M3IF_BASE_ADDR                     (MX31_X_MEMC_BASE_ADDR + 0x3000)
+#define MX31_EMI_CTL_BASE_ADDR                  (MX31_X_MEMC_BASE_ADDR + 0x4000)
+#define MX31_PCMCIA_CTL_BASE_ADDR               MX31_EMI_CTL_BASE_ADDR
+#define MX31_PCMCIA_MEM_BASE_ADDR       0xbc000000
+#define MX31_INT_I2C3           3
+#define MX31_INT_I2C2           4
+#define MX31_INT_MPEG4_ENCODER  5
+#define MX31_INT_RTIC           6
+#define MX31_INT_FIRI           7
 #define MX31_INT_MMC_SDHC2      8
-#define MXC_INT_MMC_SDHC1       9
+#define MX31_INT_MMC_SDHC1      9
+#define MX31_INT_I2C            10
 #define MX31_INT_SSI2           11
 #define MX31_INT_SSI1           12
-#define MXC_INT_MBX             16
+#define MX31_INT_CSPI2          13
-#define MXC_INT_CSPI3           17
+#define MX31_INT_CSPI1          14
-#define MXC_INT_SIM2            20
+#define MX31_INT_ATA            15
-#define MXC_INT_SIM1            21
+#define MX31_INT_MBX            16
-#define MXC_INT_CCM_DVFS        31
+#define MX31_INT_CSPI3          17
-#define MXC_INT_USB1            35
+#define MX31_INT_UART3          18
-#define MXC_INT_USB2            36
+#define MX31_INT_IIM            19
-#define MXC_INT_USB3            37
+#define MX31_INT_SIM2           20
-#define MXC_INT_USB4            38
+#define MX31_INT_SIM1           21
-#define MXC_INT_MSHC2           40
+#define MX31_INT_RNGA           22
-#define MXC_INT_UART4           46
+#define MX31_INT_EVTMON         23
-#define MXC_INT_UART5           47
+#define MX31_INT_KPP            24
-#define MXC_INT_CCM             53
+#define MX31_INT_RTC            25
-#define MXC_INT_PCMCIA          54
+#define MX31_INT_PWM            26
+#define MX31_INT_EPIT2          27
+#define MX31_INT_EPIT1          28
+#define MX31_INT_GPT            29
+#define MX31_INT_POWER_FAIL     30
+#define MX31_INT_CCM_DVFS       31
+#define MX31_INT_UART2          32
+#define MX31_INT_NANDFC         33
+#define MX31_INT_SDMA           34
+#define MX31_INT_USB1           35
+#define MX31_INT_USB2           36
+#define MX31_INT_USB3           37
+#define MX31_INT_USB4           38
+#define MX31_INT_MSHC1          39
+#define MX31_INT_MSHC2          40
+#define MX31_INT_IPU_ERR        41
+#define MX31_INT_IPU_SYN        42
+#define MX31_INT_UART1          45
+#define MX31_INT_UART4          46
+#define MX31_INT_UART5          47
+#define MX31_INT_ECT            48
+#define MX31_INT_SCC_SCM        49
+#define MX31_INT_SCC_SMN        50
+#define MX31_INT_GPIO2          51
+#define MX31_INT_GPIO1          52
+#define MX31_INT_CCM            53
+#define MX31_INT_PCMCIA         54
+#define MX31_INT_WDOG           55
+#define MX31_INT_GPIO3          56
+#define MX31_INT_EXT_POWER      58
+#define MX31_INT_EXT_TEMPER     59
+#define MX31_INT_EXT_SENSOR60   60
+#define MX31_INT_EXT_SENSOR61   61
+#define MX31_INT_EXT_WDOG       62
+#define MX31_INT_EXT_TV         63
+#define MX31_PROD_SIGNATURE             0x1     /* For MX31 */
+/* silicon revisions specific to i.MX31 */
+#define MX31_CHIP_REV_1_0               0x10
+#define MX31_CHIP_REV_1_1               0x11
+#define MX31_CHIP_REV_1_2               0x12
+#define MX31_CHIP_REV_1_3               0x13
+#define MX31_CHIP_REV_2_0               0x20
+#define MX31_CHIP_REV_2_1               0x21
+#define MX31_CHIP_REV_2_2               0x22
+#define MX31_CHIP_REV_2_3               0x23
+#define MX31_CHIP_REV_3_0               0x30
+#define MX31_CHIP_REV_3_1               0x31
+#define MX31_CHIP_REV_3_2               0x32
+#define MX31_SYSTEM_REV_MIN             MX31_CHIP_REV_1_0
+#define MX31_SYSTEM_REV_NUM             3
+/* these should go away */
+#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
+#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
+#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
+#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
+#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
+#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
+#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
+#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
+#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
+#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
+#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
+#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
+#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
+#define MXC_INT_FIRI MX31_INT_FIRI
+#define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1
+#define MXC_INT_MBX MX31_INT_MBX
+#define MXC_INT_CSPI3 MX31_INT_CSPI3
+#define MXC_INT_SIM2 MX31_INT_SIM2
+#define MXC_INT_SIM1 MX31_INT_SIM1
+#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
+#define MXC_INT_USB1 MX31_INT_USB1
+#define MXC_INT_USB2 MX31_INT_USB2
+#define MXC_INT_USB3 MX31_INT_USB3
+#define MXC_INT_USB4 MX31_INT_USB4
+#define MXC_INT_MSHC2 MX31_INT_MSHC2
+#define MXC_INT_UART4 MX31_INT_UART4
+#define MXC_INT_UART5 MX31_INT_UART5
+#define MXC_INT_CCM MX31_INT_CCM
+#define MXC_INT_PCMCIA MX31_INT_PCMCIA
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index ab4cfec6c8ab..af871bce35b6 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -2,29 +2,196 @@
 * IRAM
 */
 #define MX35_IRAM_BASE_ADDR             0x10000000      /* internal ram */
-#define MX35_IRAM_SIZE          SZ_128K
+#define MX35_IRAM_SIZE                  SZ_128K
-#define MXC_FEC_BASE_ADDR       0x50038000
+#define MX35_L2CC_BASE_ADDR             0x30000000
-#define MX35_OTG_BASE_ADDR      0x53ff4000
+#define MX35_L2CC_SIZE                  SZ_1M
-#define MX35_NFC_BASE_ADDR      0xBB000000
+#define MX35_AIPS1_BASE_ADDR            0x43f00000
+#define MX35_AIPS1_BASE_ADDR_VIRT       0xfc000000
+#define MX35_AIPS1_SIZE                 SZ_1M
+#define MX35_MAX_BASE_ADDR                      (MX35_AIPS1_BASE_ADDR + 0x04000)
+#define MX35_EVTMON_BASE_ADDR                   (MX35_AIPS1_BASE_ADDR + 0x08000)
+#define MX35_CLKCTL_BASE_ADDR                   (MX35_AIPS1_BASE_ADDR + 0x0c000)
+#define MX35_ETB_SLOT4_BASE_ADDR                (MX35_AIPS1_BASE_ADDR + 0x10000)
+#define MX35_ETB_SLOT5_BASE_ADDR                (MX35_AIPS1_BASE_ADDR + 0x14000)
+#define MX35_ECT_CTIO_BASE_ADDR                 (MX35_AIPS1_BASE_ADDR + 0x18000)
+#define MX35_I2C_BASE_ADDR                      (MX35_AIPS1_BASE_ADDR + 0x80000)
+#define MX35_I2C3_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0x84000)
+#define MX35_UART1_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x90000)
+#define MX35_UART2_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x94000)
+#define MX35_I2C2_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0x98000)
+#define MX35_OWIRE_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x9c000)
+#define MX35_SSI1_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0xa0000)
+#define MX35_CSPI1_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0xa4000)
+#define MX35_KPP_BASE_ADDR                      (MX35_AIPS1_BASE_ADDR + 0xa8000)
+#define MX35_IOMUXC_BASE_ADDR                   (MX35_AIPS1_BASE_ADDR + 0xac000)
+#define MX35_ECT_IP1_BASE_ADDR                  (MX35_AIPS1_BASE_ADDR + 0xb8000)
+#define MX35_ECT_IP2_BASE_ADDR                  (MX35_AIPS1_BASE_ADDR + 0xbc000)
+#define MX35_SPBA0_BASE_ADDR            0x50000000
+#define MX35_SPBA0_BASE_ADDR_VIRT       0xfc100000
+#define MX35_SPBA0_SIZE                 SZ_1M
+#define MX35_UART3_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x0c000)
+#define MX35_CSPI2_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x10000)
+#define MX35_SSI2_BASE_ADDR                     (MX35_SPBA0_BASE_ADDR + 0x14000)
+#define MX35_ATA_DMA_BASE_ADDR                  (MX35_SPBA0_BASE_ADDR + 0x20000)
+#define MX35_MSHC1_BASE_ADDR                    (MX35_SPBA0_BASE_ADDR + 0x24000)
+#define MX35_FEC_BASE_ADDR              0x50038000
+#define MX35_SPBA_CTRL_BASE_ADDR                (MX35_SPBA0_BASE_ADDR + 0x3c000)
+#define MX35_AIPS2_BASE_ADDR            0x53f00000
+#define MX35_AIPS2_BASE_ADDR_VIRT       0xfc200000
+#define MX35_AIPS2_SIZE                 SZ_1M
+#define MX35_CCM_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0x80000)
+#define MX35_GPT1_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0x90000)
+#define MX35_EPIT1_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0x94000)
+#define MX35_EPIT2_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0x98000)
+#define MX35_GPIO3_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xa4000)
+#define MX35_SCC_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xac000)
+#define MX35_RNGA_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xb0000)
+#define MX35_IPU_CTRL_BASE_ADDR                 (MX35_AIPS2_BASE_ADDR + 0xc0000)
+#define MX35_AUDMUX_BASE_ADDR                   (MX35_AIPS2_BASE_ADDR + 0xc4000)
+#define MX35_GPIO1_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xcc000)
+#define MX35_GPIO2_BASE_ADDR                    (MX35_AIPS2_BASE_ADDR + 0xd0000)
+#define MX35_SDMA_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xd4000)
+#define MX35_RTC_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xd8000)
+#define MX35_WDOG_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xdc000)
+#define MX35_PWM_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xe0000)
+#define MX35_RTIC_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xec000)
+#define MX35_OTG_BASE_ADDR              0x53ff4000
+#define MX35_ROMP_BASE_ADDR             0x60000000
+#define MX35_ROMP_BASE_ADDR_VIRT        0xfc500000
+#define MX35_ROMP_SIZE                  SZ_1M
+#define MX35_AVIC_BASE_ADDR             0x68000000
+#define MX35_AVIC_BASE_ADDR_VIRT        0xfc400000
+#define MX35_AVIC_SIZE                  SZ_1M
+/*
+ * Memory regions and CS
+ */
+#define MX35_IPU_MEM_BASE_ADDR          0x70000000
+#define MX35_CSD0_BASE_ADDR             0x80000000
+#define MX35_CSD1_BASE_ADDR             0x90000000
+#define MX35_CS0_BASE_ADDR              0xa0000000
+#define MX35_CS1_BASE_ADDR              0xa8000000
+#define MX35_CS2_BASE_ADDR              0xb0000000
+#define MX35_CS3_BASE_ADDR              0xb2000000
+#define MX35_CS4_BASE_ADDR              0xb4000000
+#define MX35_CS4_BASE_ADDR_VIRT         0xf4000000
+#define MX35_CS4_SIZE                   SZ_32M
+#define MX35_CS5_BASE_ADDR              0xb6000000
+#define MX35_CS5_BASE_ADDR_VIRT         0xf6000000
+#define MX35_CS5_SIZE                   SZ_32M
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define MX35_X_MEMC_BASE_ADDR           0xb8000000
+#define MX35_X_MEMC_BASE_ADDR_VIRT      0xfc320000
+#define MX35_X_MEMC_SIZE                SZ_64K
+#define MX35_ESDCTL_BASE_ADDR                   (MX35_X_MEMC_BASE_ADDR + 0x1000)
+#define MX35_WEIM_BASE_ADDR                     (MX35_X_MEMC_BASE_ADDR + 0x2000)
+#define MX35_M3IF_BASE_ADDR                     (MX35_X_MEMC_BASE_ADDR + 0x3000)
+#define MX35_EMI_CTL_BASE_ADDR                  (MX35_X_MEMC_BASE_ADDR + 0x4000)
+#define MX35_PCMCIA_CTL_BASE_ADDR               MX35_EMI_CTL_BASE_ADDR
+#define MX35_NFC_BASE_ADDR              0xbb000000
+#define MX35_PCMCIA_MEM_BASE_ADDR       0xbc000000
 /*
 * Interrupt numbers
 */
-#define MXC_INT_OWIRE           2
+#define MX35_INT_OWIRE          2
+#define MX35_INT_I2C3           3
+#define MX35_INT_I2C2           4
+#define MX35_INT_RTIC           6
 #define MX35_INT_MMC_SDHC1      7
-#define MXC_INT_MMC_SDHC2       8
+#define MX35_INT_MMC_SDHC2      8
-#define MXC_INT_MMC_SDHC3       9
+#define MX35_INT_MMC_SDHC3      9
+#define MX35_INT_I2C            10
 #define MX35_INT_SSI1           11
 #define MX35_INT_SSI2           12
-#define MXC_INT_GPU2D           16
+#define MX35_INT_CSPI2          13
-#define MXC_INT_ASRC            17
+#define MX35_INT_CSPI1          14
-#define MXC_INT_USBHS           35
+#define MX35_INT_ATA            15
-#define MXC_INT_USBOTG          37
+#define MX35_INT_GPU2D          16
-#define MXC_INT_ESAI            40
+#define MX35_INT_ASRC           17
-#define MXC_INT_CAN1            43
+#define MX35_INT_UART3          18
-#define MXC_INT_CAN2            44
+#define MX35_INT_IIM            19
-#define MXC_INT_MLB             46
+#define MX35_INT_RNGA           22
-#define MXC_INT_SPDIF           47
+#define MX35_INT_EVTMON         23
-#define MXC_INT_FEC             57
+#define MX35_INT_KPP            24
+#define MX35_INT_RTC            25
+#define MX35_INT_PWM            26
+#define MX35_INT_EPIT2          27
+#define MX35_INT_EPIT1          28
+#define MX35_INT_GPT            29
+#define MX35_INT_POWER_FAIL     30
+#define MX35_INT_UART2          32
+#define MX35_INT_NANDFC         33
+#define MX35_INT_SDMA           34
+#define MX35_INT_USBHS          35
+#define MX35_INT_USBOTG         37
+#define MX35_INT_MSHC1          39
+#define MX35_INT_ESAI           40
+#define MX35_INT_IPU_ERR        41
+#define MX35_INT_IPU_SYN        42
+#define MX35_INT_CAN1           43
+#define MX35_INT_CAN2           44
+#define MX35_INT_UART1          45
+#define MX35_INT_MLB            46
+#define MX35_INT_SPDIF          47
+#define MX35_INT_ECT            48
+#define MX35_INT_SCC_SCM        49
+#define MX35_INT_SCC_SMN        50
+#define MX35_INT_GPIO2          51
+#define MX35_INT_GPIO1          52
+#define MX35_INT_WDOG           55
+#define MX35_INT_GPIO3          56
+#define MX35_INT_FEC            57
+#define MX35_INT_EXT_POWER      58
+#define MX35_INT_EXT_TEMPER     59
+#define MX35_INT_EXT_SENSOR60   60
+#define MX35_INT_EXT_SENSOR61   61
+#define MX35_INT_EXT_WDOG       62
+#define MX35_INT_EXT_TV         63
+#define MX35_PROD_SIGNATURE             0x1     /* For MX31 */
+/* silicon revisions specific to i.MX31 */
+#define MX35_CHIP_REV_1_0               0x10
+#define MX35_CHIP_REV_1_1               0x11
+#define MX35_CHIP_REV_1_2               0x12
+#define MX35_CHIP_REV_1_3               0x13
+#define MX35_CHIP_REV_2_0               0x20
+#define MX35_CHIP_REV_2_1               0x21
+#define MX35_CHIP_REV_2_2               0x22
+#define MX35_CHIP_REV_2_3               0x23
+#define MX35_CHIP_REV_3_0               0x30
+#define MX35_CHIP_REV_3_1               0x31
+#define MX35_CHIP_REV_3_2               0x32
+#define MX35_SYSTEM_REV_MIN             MX35_CHIP_REV_1_0
+#define MX35_SYSTEM_REV_NUM             3
+/* these should go away */
+#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
+#define MXC_INT_OWIRE MX35_INT_OWIRE
+#define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2
+#define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3
+#define MXC_INT_GPU2D MX35_INT_GPU2D
+#define MXC_INT_ASRC MX35_INT_ASRC
+#define MXC_INT_USBHS MX35_INT_USBHS
+#define MXC_INT_USBOTG MX35_INT_USBOTG
+#define MXC_INT_ESAI MX35_INT_ESAI
+#define MXC_INT_CAN1 MX35_INT_CAN1
+#define MXC_INT_CAN2 MX35_INT_CAN2
+#define MXC_INT_MLB MX35_INT_MLB
+#define MXC_INT_SPDIF MX35_INT_SPDIF
+#define MXC_INT_FEC MX35_INT_FEC
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 009f4440276b..be69272407ad 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -34,120 +34,117 @@
 *              C0000000        64M     PCMCIA/CF
 */
-#define CS0_BASE_ADDR           0xA0000000
-#define CS1_BASE_ADDR           0xA8000000
-#define CS2_BASE_ADDR           0xB0000000
-#define CS3_BASE_ADDR           0xB2000000
-#define CS4_BASE_ADDR           0xB4000000
-#define CS4_BASE_ADDR_VIRT      0xF4000000
-#define CS4_SIZE                SZ_32M
-#define CS5_BASE_ADDR           0xB6000000
-#define CS5_BASE_ADDR_VIRT      0xF6000000
-#define CS5_SIZE                SZ_32M
-#define PCMCIA_MEM_BASE_ADDR    0xBC000000
 /*
 * L2CC
 */
-#define L2CC_BASE_ADDR          0x30000000
+#define MX3x_L2CC_BASE_ADDR             0x30000000
-#define L2CC_SIZE               SZ_1M
+#define MX3x_L2CC_SIZE                  SZ_1M
 /*
 * AIPS 1
 */
-#define AIPS1_BASE_ADDR         0x43F00000
+#define MX3x_AIPS1_BASE_ADDR            0x43f00000
-#define AIPS1_BASE_ADDR_VIRT    0xFC000000
+#define MX3x_AIPS1_BASE_ADDR_VIRT       0xfc000000
-#define AIPS1_SIZE              SZ_1M
+#define MX3x_AIPS1_SIZE                 SZ_1M
+#define MX3x_MAX_BASE_ADDR                      (MX3x_AIPS1_BASE_ADDR + 0x04000)
-#define MAX_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00004000)
+#define MX3x_EVTMON_BASE_ADDR                   (MX3x_AIPS1_BASE_ADDR + 0x08000)
-#define EVTMON_BASE_ADDR        (AIPS1_BASE_ADDR + 0x00008000)
+#define MX3x_CLKCTL_BASE_ADDR                   (MX3x_AIPS1_BASE_ADDR + 0x0c000)
-#define CLKCTL_BASE_ADDR        (AIPS1_BASE_ADDR + 0x0000C000)
+#define MX3x_ETB_SLOT4_BASE_ADDR                (MX3x_AIPS1_BASE_ADDR + 0x10000)
-#define ETB_SLOT4_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00010000)
+#define MX3x_ETB_SLOT5_BASE_ADDR                (MX3x_AIPS1_BASE_ADDR + 0x14000)
-#define ETB_SLOT5_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00014000)
+#define MX3x_ECT_CTIO_BASE_ADDR                 (MX3x_AIPS1_BASE_ADDR + 0x18000)
-#define ECT_CTIO_BASE_ADDR      (AIPS1_BASE_ADDR + 0x00018000)
+#define MX3x_I2C_BASE_ADDR                      (MX3x_AIPS1_BASE_ADDR + 0x80000)
-#define I2C_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00080000)
+#define MX3x_I2C3_BASE_ADDR                     (MX3x_AIPS1_BASE_ADDR + 0x84000)
-#define I2C3_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00084000)
+#define MX3x_UART1_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0x90000)
-#define UART1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00090000)
+#define MX3x_UART2_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0x94000)
-#define UART2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00094000)
+#define MX3x_I2C2_BASE_ADDR                     (MX3x_AIPS1_BASE_ADDR + 0x98000)
-#define I2C2_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00098000)
+#define MX3x_OWIRE_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0x9c000)
-#define OWIRE_BASE_ADDR         (AIPS1_BASE_ADDR + 0x0009C000)
+#define MX3x_SSI1_BASE_ADDR                     (MX3x_AIPS1_BASE_ADDR + 0xa0000)
-#define SSI1_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000A0000)
+#define MX3x_CSPI1_BASE_ADDR                    (MX3x_AIPS1_BASE_ADDR + 0xa4000)
-#define CSPI1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000A4000)
+#define MX3x_KPP_BASE_ADDR                      (MX3x_AIPS1_BASE_ADDR + 0xa8000)
-#define KPP_BASE_ADDR           (AIPS1_BASE_ADDR + 0x000A8000)
+#define MX3x_IOMUXC_BASE_ADDR                   (MX3x_AIPS1_BASE_ADDR + 0xac000)
-#define IOMUXC_BASE_ADDR        (AIPS1_BASE_ADDR + 0x000AC000)
+#define MX3x_ECT_IP1_BASE_ADDR                  (MX3x_AIPS1_BASE_ADDR + 0xb8000)
-#define ECT_IP1_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000B8000)
+#define MX3x_ECT_IP2_BASE_ADDR                  (MX3x_AIPS1_BASE_ADDR + 0xbc000)
-#define ECT_IP2_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000BC000)
 /*
 * SPBA global module enabled #0
 */
-#define SPBA0_BASE_ADDR         0x50000000
+#define MX3x_SPBA0_BASE_ADDR            0x50000000
-#define SPBA0_BASE_ADDR_VIRT    0xFC100000
+#define MX3x_SPBA0_BASE_ADDR_VIRT       0xfc100000
-#define SPBA0_SIZE              SZ_1M
+#define MX3x_SPBA0_SIZE                 SZ_1M
+#define MX3x_UART3_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x0c000)
-#define UART3_BASE_ADDR         (SPBA0_BASE_ADDR + 0x0000C000)
+#define MX3x_CSPI2_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x10000)
-#define CSPI2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00010000)
+#define MX3x_SSI2_BASE_ADDR                     (MX3x_SPBA0_BASE_ADDR + 0x14000)
-#define SSI2_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00014000)
+#define MX3x_ATA_DMA_BASE_ADDR                  (MX3x_SPBA0_BASE_ADDR + 0x20000)
-#define ATA_DMA_BASE_ADDR       (SPBA0_BASE_ADDR + 0x00020000)
+#define MX3x_MSHC1_BASE_ADDR                    (MX3x_SPBA0_BASE_ADDR + 0x24000)
-#define MSHC1_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00024000)
+#define MX3x_SPBA_CTRL_BASE_ADDR                (MX3x_SPBA0_BASE_ADDR + 0x3c000)
-#define SPBA_CTRL_BASE_ADDR     (SPBA0_BASE_ADDR + 0x0003C000)
 /*
 * AIPS 2
 */
-#define AIPS2_BASE_ADDR         0x53F00000
+#define MX3x_AIPS2_BASE_ADDR            0x53f00000
-#define AIPS2_BASE_ADDR_VIRT    0xFC200000
+#define MX3x_AIPS2_BASE_ADDR_VIRT       0xfc200000
-#define AIPS2_SIZE              SZ_1M
+#define MX3x_AIPS2_SIZE                 SZ_1M
-#define CCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x00080000)
+#define MX3x_CCM_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0x80000)
-#define GPT1_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00090000)
+#define MX3x_GPT1_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0x90000)
-#define EPIT1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00094000)
+#define MX3x_EPIT1_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0x94000)
-#define EPIT2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00098000)
+#define MX3x_EPIT2_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0x98000)
-#define GPIO3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000A4000)
+#define MX3x_GPIO3_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0xa4000)
-#define SCC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AC000)
+#define MX3x_SCC_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0xac000)
-#define RNGA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000B0000)
+#define MX3x_RNGA_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xb0000)
-#define IPU_CTRL_BASE_ADDR      (AIPS2_BASE_ADDR + 0x000C0000)
+#define MX3x_IPU_CTRL_BASE_ADDR                 (MX3x_AIPS2_BASE_ADDR + 0xc0000)
-#define AUDMUX_BASE_ADDR        (AIPS2_BASE_ADDR + 0x000C4000)
+#define MX3x_AUDMUX_BASE_ADDR                   (MX3x_AIPS2_BASE_ADDR + 0xc4000)
-#define GPIO1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000CC000)
+#define MX3x_GPIO1_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0xcc000)
-#define GPIO2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000D0000)
+#define MX3x_GPIO2_BASE_ADDR                    (MX3x_AIPS2_BASE_ADDR + 0xd0000)
-#define SDMA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000D4000)
+#define MX3x_SDMA_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xd4000)
-#define RTC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000D8000)
+#define MX3x_RTC_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0xd8000)
-#define WDOG_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000DC000)
+#define MX3x_WDOG_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xdc000)
-#define PWM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000E0000)
+#define MX3x_PWM_BASE_ADDR                      (MX3x_AIPS2_BASE_ADDR + 0xe0000)
-#define RTIC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000EC000)
+#define MX3x_RTIC_BASE_ADDR                     (MX3x_AIPS2_BASE_ADDR + 0xec000)
 /*
 * ROMP and AVIC
 */
-#define ROMP_BASE_ADDR          0x60000000
+#define MX3x_ROMP_BASE_ADDR             0x60000000
-#define ROMP_BASE_ADDR_VIRT     0xFC500000
+#define MX3x_ROMP_BASE_ADDR_VIRT        0xfc500000
-#define ROMP_SIZE               SZ_1M
+#define MX3x_ROMP_SIZE                  SZ_1M
-#define AVIC_BASE_ADDR          0x68000000
+#define MX3x_AVIC_BASE_ADDR             0x68000000
-#define AVIC_BASE_ADDR_VIRT     0xFC400000
+#define MX3x_AVIC_BASE_ADDR_VIRT        0xfc400000
-#define AVIC_SIZE               SZ_1M
+#define MX3x_AVIC_SIZE                  SZ_1M
 /*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ * Memory regions and CS
 */
-#define X_MEMC_BASE_ADDR        0xB8000000
+#define MX3x_IPU_MEM_BASE_ADDR          0x70000000
-#define X_MEMC_BASE_ADDR_VIRT   0xFC320000
+#define MX3x_CSD0_BASE_ADDR             0x80000000
-#define X_MEMC_SIZE             SZ_64K
+#define MX3x_CSD1_BASE_ADDR             0x90000000
-#define ESDCTL_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
+#define MX3x_CS0_BASE_ADDR              0xa0000000
-#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
+#define MX3x_CS1_BASE_ADDR              0xa8000000
-#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
+#define MX3x_CS2_BASE_ADDR              0xb0000000
-#define EMI_CTL_BASE_ADDR       (X_MEMC_BASE_ADDR + 0x4000)
+#define MX3x_CS3_BASE_ADDR              0xb2000000
-#define PCMCIA_CTL_BASE_ADDR    EMI_CTL_BASE_ADDR
+#define MX3x_CS4_BASE_ADDR              0xb4000000
+#define MX3x_CS4_BASE_ADDR_VIRT         0xf4000000
+#define MX3x_CS4_SIZE                   SZ_32M
+#define MX3x_CS5_BASE_ADDR              0xb6000000
+#define MX3x_CS5_BASE_ADDR_VIRT         0xf6000000
+#define MX3x_CS5_SIZE                   SZ_32M
 /*
- * Memory regions and CS
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
 */
-#define IPU_MEM_BASE_ADDR       0x70000000
+#define MX3x_X_MEMC_BASE_ADDR           0xb8000000
-#define CSD0_BASE_ADDR          0x80000000
+#define MX3x_X_MEMC_BASE_ADDR_VIRT      0xfc320000
-#define CSD1_BASE_ADDR          0x90000000
+#define MX3x_X_MEMC_SIZE                SZ_64K
+#define MX3x_ESDCTL_BASE_ADDR                   (MX3x_X_MEMC_BASE_ADDR + 0x1000)
+#define MX3x_WEIM_BASE_ADDR                     (MX3x_X_MEMC_BASE_ADDR + 0x2000)
+#define MX3x_M3IF_BASE_ADDR                     (MX3x_X_MEMC_BASE_ADDR + 0x3000)
+#define MX3x_EMI_CTL_BASE_ADDR                  (MX3x_X_MEMC_BASE_ADDR + 0x4000)
+#define MX3x_PCMCIA_CTL_BASE_ADDR               MX3x_EMI_CTL_BASE_ADDR
+#define MX3x_PCMCIA_MEM_BASE_ADDR       0xbc000000
 /*!
 * This macro defines the physical to virtual address mapping for all the
@@ -202,74 +199,207 @@
 /*
 * Interrupt numbers
 */
-#define MXC_INT_I2C3            3
+#define MX3x_INT_I2C3           3
-#define MXC_INT_I2C2            4
+#define MX3x_INT_I2C2           4
-#define MXC_INT_RTIC            6
+#define MX3x_INT_RTIC           6
-#define MXC_INT_I2C             10
+#define MX3x_INT_I2C            10
-#define MXC_INT_CSPI2           13
+#define MX3x_INT_CSPI2          13
-#define MXC_INT_CSPI1           14
+#define MX3x_INT_CSPI1          14
-#define MXC_INT_ATA             15
+#define MX3x_INT_ATA            15
-#define MXC_INT_UART3           18
+#define MX3x_INT_UART3          18
-#define MXC_INT_IIM             19
+#define MX3x_INT_IIM            19
-#define MXC_INT_RNGA            22
+#define MX3x_INT_RNGA           22
-#define MXC_INT_EVTMON          23
+#define MX3x_INT_EVTMON         23
-#define MXC_INT_KPP             24
+#define MX3x_INT_KPP            24
-#define MXC_INT_RTC             25
+#define MX3x_INT_RTC            25
-#define MXC_INT_PWM             26
+#define MX3x_INT_PWM            26
-#define MXC_INT_EPIT2           27
+#define MX3x_INT_EPIT2          27
-#define MXC_INT_EPIT1           28
+#define MX3x_INT_EPIT1          28
-#define MXC_INT_GPT             29
+#define MX3x_INT_GPT            29
-#define MXC_INT_POWER_FAIL      30
+#define MX3x_INT_POWER_FAIL     30
-#define MXC_INT_UART2           32
+#define MX3x_INT_UART2          32
-#define MXC_INT_NANDFC          33
+#define MX3x_INT_NANDFC         33
-#define MXC_INT_SDMA            34
+#define MX3x_INT_SDMA           34
-#define MXC_INT_MSHC1           39
+#define MX3x_INT_MSHC1          39
-#define MXC_INT_IPU_ERR         41
+#define MX3x_INT_IPU_ERR        41
-#define MXC_INT_IPU_SYN         42
+#define MX3x_INT_IPU_SYN        42
-#define MXC_INT_UART1           45
+#define MX3x_INT_UART1          45
-#define MXC_INT_ECT             48
+#define MX3x_INT_ECT            48
-#define MXC_INT_SCC_SCM         49
+#define MX3x_INT_SCC_SCM        49
-#define MXC_INT_SCC_SMN         50
+#define MX3x_INT_SCC_SMN        50
-#define MXC_INT_GPIO2           51
+#define MX3x_INT_GPIO2          51
-#define MXC_INT_GPIO1           52
+#define MX3x_INT_GPIO1          52
-#define MXC_INT_WDOG            55
+#define MX3x_INT_WDOG           55
-#define MXC_INT_GPIO3           56
+#define MX3x_INT_GPIO3          56
-#define MXC_INT_EXT_POWER       58
+#define MX3x_INT_EXT_POWER      58
-#define MXC_INT_EXT_TEMPER      59
+#define MX3x_INT_EXT_TEMPER     59
-#define MXC_INT_EXT_SENSOR60    60
+#define MX3x_INT_EXT_SENSOR60   60
-#define MXC_INT_EXT_SENSOR61    61
+#define MX3x_INT_EXT_SENSOR61   61
-#define MXC_INT_EXT_WDOG        62
+#define MX3x_INT_EXT_WDOG       62
-#define MXC_INT_EXT_TV          63
+#define MX3x_INT_EXT_TV         63
-#define PROD_SIGNATURE          0x1     /* For MX31 */
+#define MX3x_PROD_SIGNATURE             0x1     /* For MX31 */
 /* silicon revisions specific to i.MX31 */
-#define CHIP_REV_1_0            0x10
+#define MX3x_CHIP_REV_1_0               0x10
-#define CHIP_REV_1_1            0x11
+#define MX3x_CHIP_REV_1_1               0x11
-#define CHIP_REV_1_2            0x12
+#define MX3x_CHIP_REV_1_2               0x12
-#define CHIP_REV_1_3            0x13
+#define MX3x_CHIP_REV_1_3               0x13
-#define CHIP_REV_2_0            0x20
+#define MX3x_CHIP_REV_2_0               0x20
-#define CHIP_REV_2_1            0x21
+#define MX3x_CHIP_REV_2_1               0x21
-#define CHIP_REV_2_2            0x22
+#define MX3x_CHIP_REV_2_2               0x22
-#define CHIP_REV_2_3            0x23
+#define MX3x_CHIP_REV_2_3               0x23
-#define CHIP_REV_3_0            0x30
+#define MX3x_CHIP_REV_3_0               0x30
-#define CHIP_REV_3_1            0x31
+#define MX3x_CHIP_REV_3_1               0x31
-#define CHIP_REV_3_2            0x32
+#define MX3x_CHIP_REV_3_2               0x32
-#define SYSTEM_REV_MIN          CHIP_REV_1_0
+#define MX3x_SYSTEM_REV_MIN             MX3x_CHIP_REV_1_0
-#define SYSTEM_REV_NUM          3
+#define MX3x_SYSTEM_REV_NUM             3
 /* Mandatory defines used globally */
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-extern unsigned int system_rev;
+extern unsigned int mx31_cpu_rev;
+extern void mx31_read_cpu_rev(void);
 static inline int mx31_revision(void)
 {
-        return system_rev;
+        return mx31_cpu_rev;
 }
 #endif
-#endif /*  __ASM_ARCH_MXC_MX31_H__ */
+/* these should go away */
+#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
+#define L2CC_SIZE MX3x_L2CC_SIZE
+#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
+#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT
+#define AIPS1_SIZE MX3x_AIPS1_SIZE
+#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
+#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
+#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
+#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
+#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
+#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
+#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
+#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
+#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
+#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
+#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
+#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
+#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
+#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
+#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
+#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
+#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
+#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
+#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
+#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
+#define SPBA0_SIZE MX3x_SPBA0_SIZE
+#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
+#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
+#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
+#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
+#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
+#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
+#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
+#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
+#define AIPS2_SIZE MX3x_AIPS2_SIZE
+#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
+#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
+#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
+#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
+#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
+#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
+#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
+#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
+#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
+#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
+#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
+#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
+#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
+#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
+#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
+#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
+#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
+#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
+#define ROMP_SIZE MX3x_ROMP_SIZE
+#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
+#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
+#define AVIC_SIZE MX3x_AVIC_SIZE
+#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
+#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
+#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
+#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
+#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
+#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
+#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
+#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
+#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
+#define CS4_SIZE MX3x_CS4_SIZE
+#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
+#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
+#define CS5_SIZE MX3x_CS5_SIZE
+#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
+#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
+#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
+#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
+#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
+#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
+#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
+#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
+#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
+#define MXC_INT_I2C3 MX3x_INT_I2C3
+#define MXC_INT_I2C2 MX3x_INT_I2C2
+#define MXC_INT_RTIC MX3x_INT_RTIC
+#define MXC_INT_I2C MX3x_INT_I2C
+#define MXC_INT_CSPI2 MX3x_INT_CSPI2
+#define MXC_INT_CSPI1 MX3x_INT_CSPI1
+#define MXC_INT_ATA MX3x_INT_ATA
+#define MXC_INT_UART3 MX3x_INT_UART3
+#define MXC_INT_IIM MX3x_INT_IIM
+#define MXC_INT_RNGA MX3x_INT_RNGA
+#define MXC_INT_EVTMON MX3x_INT_EVTMON
+#define MXC_INT_KPP MX3x_INT_KPP
+#define MXC_INT_RTC MX3x_INT_RTC
+#define MXC_INT_PWM MX3x_INT_PWM
+#define MXC_INT_EPIT2 MX3x_INT_EPIT2
+#define MXC_INT_EPIT1 MX3x_INT_EPIT1
+#define MXC_INT_GPT MX3x_INT_GPT
+#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
+#define MXC_INT_UART2 MX3x_INT_UART2
+#define MXC_INT_NANDFC MX3x_INT_NANDFC
+#define MXC_INT_SDMA MX3x_INT_SDMA
+#define MXC_INT_MSHC1 MX3x_INT_MSHC1
+#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
+#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
+#define MXC_INT_UART1 MX3x_INT_UART1
+#define MXC_INT_ECT MX3x_INT_ECT
+#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
+#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
+#define MXC_INT_GPIO2 MX3x_INT_GPIO2
+#define MXC_INT_GPIO1 MX3x_INT_GPIO1
+#define MXC_INT_WDOG MX3x_INT_WDOG
+#define MXC_INT_GPIO3 MX3x_INT_GPIO3
+#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
+#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
+#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
+#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
+#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
+#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
+#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
+#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
+#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
+#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
+#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
+#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
+#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
+#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
+#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
+#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
+#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
+#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
+#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
+#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
+#endif /*  __ASM_ARCH_MXC_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h
new file mode 100644
index 000000000000..96b6ab4c40c3
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/ulpi.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_ULPI_H
+#define __MACH_ULPI_H
+extern struct otg_io_access_ops mxc_ulpi_access_ops;
+#endif /* __MACH_ULPI_H */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 082a3908256b..a41bf57fb3de 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -83,6 +83,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
        case MACH_TYPE_MX27ADS:
        case MACH_TYPE_PCM038:
        case MACH_TYPE_MX21ADS:
+        case MACH_TYPE_PCA100:
                uart_base = MX2X_UART1_BASE_ADDR;
                break;
        case MACH_TYPE_MX31LITE:
@@ -94,6 +95,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
        case MACH_TYPE_MX31ADS:
        case MACH_TYPE_MX35_3DS:
        case MACH_TYPE_PCM043:
+        case MACH_TYPE_LILLY1131:
                uart_base = MX3X_UART1_BASE_ADDR;
                break;
        case MACH_TYPE_MAGX_ZN5:
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index 851ca99bf1b1..b318c6a222d5 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -31,19 +31,11 @@
 static void __iomem *base;
-static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG];
 /*
- * setups a single pin:
+ * setups a single pad in the iomuxer
- *      - reserves the pin so that it is not claimed by another driver
- *      - setups the iomux according to the configuration
 */
 int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
 {
-        unsigned int pad_ofs = pad->pad_ctrl_ofs;
-        if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map))
-                return -EBUSY;
        if (pad->mux_ctrl_ofs)
                __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs);
@@ -66,37 +58,13 @@ int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count)
        for (i = 0; i < count; i++) {
                ret = mxc_iomux_v3_setup_pad(p);
                if (ret)
-                        goto setup_error;
+                        return ret;
                p++;
        }
        return 0;
-setup_error:
-        mxc_iomux_v3_release_multiple_pads(pad_list, i);
-        return ret;
 }
 EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
-void mxc_iomux_v3_release_pad(struct pad_desc *pad)
-{
-        unsigned int pad_ofs = pad->pad_ctrl_ofs;
-        clear_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map);
-}
-EXPORT_SYMBOL(mxc_iomux_v3_release_pad);
-void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count)
-{
-        struct pad_desc *p = pad_list;
-        int i;
-        for (i = 0; i < count; i++) {
-                mxc_iomux_v3_release_pad(p);
-                p++;
-        }
-}
-EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads);
 void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
 {
        base = iomux_v3_base;
diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c
new file mode 100644
index 000000000000..582c6dfaba4a
--- /dev/null
+++ b/arch/arm/plat-mxc/ulpi.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * Copyright 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA  02110-1301, USA.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/usb/otg.h>
+#include <mach/ulpi.h>
+/* ULPIVIEW register bits */
+#define ULPIVW_WU               (1 << 31)       /* Wakeup */
+#define ULPIVW_RUN              (1 << 30)       /* read/write run */
+#define ULPIVW_WRITE            (1 << 29)       /* 0 = read  1 = write */
+#define ULPIVW_SS               (1 << 27)       /* SyncState */
+#define ULPIVW_PORT_MASK        0x07    /* Port field */
+#define ULPIVW_PORT_SHIFT       24
+#define ULPIVW_ADDR_MASK        0xff    /* data address field */
+#define ULPIVW_ADDR_SHIFT       16
+#define ULPIVW_RDATA_MASK       0xff    /* read data field */
+#define ULPIVW_RDATA_SHIFT      8
+#define ULPIVW_WDATA_MASK       0xff    /* write data field */
+#define ULPIVW_WDATA_SHIFT      0
+static int ulpi_poll(void __iomem *view, u32 bit)
+{
+        int timeout = 10000;
+        while (timeout--) {
+                u32 data = __raw_readl(view);
+                if (!(data & bit))
+                        return 0;
+                cpu_relax();
+        };
+        printk(KERN_WARNING "timeout polling for ULPI device\n");
+        return -ETIMEDOUT;
+}
+static int ulpi_read(struct otg_transceiver *otg, u32 reg)
+{
+        int ret;
+        void __iomem *view = otg->io_priv;
+        /* make sure interface is running */
+        if (!(__raw_readl(view) & ULPIVW_SS)) {
+                __raw_writel(ULPIVW_WU, view);
+                /* wait for wakeup */
+                ret = ulpi_poll(view, ULPIVW_WU);
+                if (ret)
+                        return ret;
+        }
+        /* read the register */
+        __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view);
+        /* wait for completion */
+        ret = ulpi_poll(view, ULPIVW_RUN);
+        if (ret)
+                return ret;
+        return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
+}
+static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
+{
+        int ret;
+        void __iomem *view = otg->io_priv;
+        /* make sure the interface is running */
+        if (!(__raw_readl(view) & ULPIVW_SS)) {
+                __raw_writel(ULPIVW_WU, view);
+                /* wait for wakeup */
+                ret = ulpi_poll(view, ULPIVW_WU);
+                if (ret)
+                        return ret;
+        }
+        __raw_writel((ULPIVW_RUN | ULPIVW_WRITE |
+                      (reg << ULPIVW_ADDR_SHIFT) |
+                      ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
+        /* wait for completion */
+        return ulpi_poll(view, ULPIVW_RUN);
+}
+struct otg_io_access_ops mxc_ulpi_access_ops = {
+        .read   = ulpi_read,
+        .write  = ulpi_write,
+};
+EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
index 8931c5f0e46b..e139a72c2149 100644
--- a/arch/arm/plat-s3c/Kconfig
+++ b/arch/arm/plat-s3c/Kconfig
@@ -159,6 +159,12 @@ config S3C_GPIO_CFG_S3C64XX
          Internal configuration to enable S3C64XX style GPIO configuration
          functions.
+config S5P_GPIO_CFG_S5PC1XX
+        bool
+        help
+          Internal configuration to enable S5PC1XX style GPIO configuration
+          functions.
 # DMA
 config S3C_DMA
@@ -178,6 +184,11 @@ config S3C_DEV_HSMMC1
        help
          Compile in platform device definitions for HSMMC channel 1
+config S3C_DEV_HSMMC2
+        bool
+        help
+          Compile in platform device definitions for HSMMC channel 2
 config S3C_DEV_I2C1
        bool
        help
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 3c09109e9e84..50444da98425 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_HAVE_PWM)		+= pwm.o
 obj-$(CONFIG_S3C_DEV_HSMMC)     += dev-hsmmc.o
 obj-$(CONFIG_S3C_DEV_HSMMC1)    += dev-hsmmc1.o
+obj-$(CONFIG_S3C_DEV_HSMMC2)    += dev-hsmmc2.o
 obj-y                           += dev-i2c0.o
 obj-$(CONFIG_S3C_DEV_I2C1)      += dev-i2c1.o
 obj-$(CONFIG_S3C_DEV_FB)        += dev-fb.o
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c
index 4d01ef1a25dd..619cfa82dcab 100644
--- a/arch/arm/plat-s3c/clock.c
+++ b/arch/arm/plat-s3c/clock.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/clock.c
 *
- * Copyright (c) 2004-2005 Simtec Electronics
+ * Copyright 2004-2005 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C24XX Core clock control support
@@ -337,7 +337,7 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks)
 int __init s3c24xx_register_baseclocks(unsigned long xtal)
 {
-        printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
+        printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n");
        clk_xtal.rate = xtal;
diff --git a/arch/arm/plat-s3c/dev-hsmmc2.c b/arch/arm/plat-s3c/dev-hsmmc2.c
new file mode 100644
index 000000000000..824580bc0e06
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-hsmmc2.c
@@ -0,0 +1,69 @@
+/* linux/arch/arm/plat-s3c/dev-hsmmc2.c
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ * Copyright (c) 2009 Maurus Cuelenaere
+ *
+ * Based on arch/arm/plat-s3c/dev-hsmmc1.c
+ * original file Copyright (c) 2008 Simtec Electronics
+ *
+ * S3C series device definition for hsmmc device 2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+#include <mach/map.h>
+#include <plat/sdhci.h>
+#include <plat/devs.h>
+#define S3C_SZ_HSMMC    (0x1000)
+static struct resource s3c_hsmmc2_resource[] = {
+        [0] = {
+                .start = S3C_PA_HSMMC2,
+                .end   = S3C_PA_HSMMC2 + S3C_SZ_HSMMC - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_HSMMC2,
+                .end   = IRQ_HSMMC2,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+static u64 s3c_device_hsmmc2_dmamask = 0xffffffffUL;
+struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
+        .max_width      = 4,
+        .host_caps      = (MMC_CAP_4_BIT_DATA |
+                           MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+};
+struct platform_device s3c_device_hsmmc2 = {
+        .name           = "s3c-sdhci",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(s3c_hsmmc2_resource),
+        .resource       = s3c_hsmmc2_resource,
+        .dev            = {
+                .dma_mask               = &s3c_device_hsmmc2_dmamask,
+                .coherent_dma_mask      = 0xffffffffUL,
+                .platform_data          = &s3c_hsmmc2_def_platdata,
+        },
+};
+void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
+{
+        struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata;
+        set->max_width = pd->max_width;
+        if (pd->cfg_gpio)
+                set->cfg_gpio = pd->cfg_gpio;
+        if (pd->cfg_card)
+                set->cfg_card = pd->cfg_card;
+}
diff --git a/arch/arm/plat-s3c/dev-i2c0.c b/arch/arm/plat-s3c/dev-i2c0.c
index 428372868fbb..4c761529b949 100644
--- a/arch/arm/plat-s3c/dev-i2c0.c
+++ b/arch/arm/plat-s3c/dev-i2c0.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c/dev-i2c0.c
 *
- * Copyright 2008,2009 Simtec Electronics
+ * Copyright 2008-2009 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
diff --git a/arch/arm/plat-s3c/dev-i2c1.c b/arch/arm/plat-s3c/dev-i2c1.c
index 8349c462788c..d44f79110506 100644
--- a/arch/arm/plat-s3c/dev-i2c1.c
+++ b/arch/arm/plat-s3c/dev-i2c1.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c/dev-i2c1.c
 *
- * Copyright 2008,2009 Simtec Electronics
+ * Copyright 2008-2009 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
diff --git a/arch/arm/plat-s3c/dev-nand.c b/arch/arm/plat-s3c/dev-nand.c
index 4e5323732434..e771e77dcd54 100644
--- a/arch/arm/plat-s3c/dev-nand.c
+++ b/arch/arm/plat-s3c/dev-nand.c
@@ -9,8 +9,12 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
 #include <mach/map.h>
 #include <plat/devs.h>
+#include <plat/nand.h>
 static struct resource s3c_nand_resource[] = {
        [0] = {
@@ -28,3 +32,96 @@ struct platform_device s3c_device_nand = {
 };
 EXPORT_SYMBOL(s3c_device_nand);
+/**
+ * s3c_nand_copy_set() - copy nand set data
+ * @set: The new structure, directly copied from the old.
+ *
+ * Copy all the fields from the NAND set field from what is probably __initdata
+ * to new kernel memory. The code returns 0 if the copy happened correctly or
+ * an error code for the calling function to display.
+ *
+ * Note, we currently do not try and look to see if we've already copied the
+ * data in a previous set.
+ */
+static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
+{
+        void *ptr;
+        int size;
+        size = sizeof(struct mtd_partition) * set->nr_partitions;
+        if (size) {
+                ptr = kmemdup(set->partitions, size, GFP_KERNEL);
+                set->partitions = ptr;
+                if (!ptr)
+                        return -ENOMEM;
+        }
+        
+        size = sizeof(int) * set->nr_chips;
+        if (size) {
+                ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
+                set->nr_map = ptr;
+                if (!ptr)
+                        return -ENOMEM;
+        }
+        if (set->ecc_layout) {
+                ptr = kmemdup(set->ecc_layout,
+                              sizeof(struct nand_ecclayout), GFP_KERNEL);
+                set->ecc_layout = ptr;
+                if (!ptr)
+                        return -ENOMEM;
+        }
+        
+        return 0;
+}
+void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
+{
+        struct s3c2410_platform_nand *npd;
+        int size;
+        int ret;
+        /* note, if we get a failure in allocation, we simply drop out of the
+         * function. If there is so little memory available at initialisation
+         * time then there is little chance the system is going to run.
+         */ 
+        npd = kmemdup(nand, sizeof(struct s3c2410_platform_nand), GFP_KERNEL);
+        if (!npd) {
+                printk(KERN_ERR "%s: failed copying platform data\n", __func__);
+                return;
+        }
+        /* now see if we need to copy any of the nand set data */
+        size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
+        if (size) {
+                struct s3c2410_nand_set *from = npd->sets;
+                struct s3c2410_nand_set *to;
+                int i;
+                to = kmemdup(from, size, GFP_KERNEL);
+                npd->sets = to; /* set, even if we failed */
+                if (!to) {
+                        printk(KERN_ERR "%s: no memory for sets\n", __func__);
+                        return;
+                }
+                
+                for (i = 0; i < npd->nr_sets; i++) {
+                        ret = s3c_nand_copy_set(to);
+                        if (!ret) {
+                                printk(KERN_ERR "%s: failed to copy set %d\n",
+                                __func__, i);
+                                return;
+                        }
+                        to++;
+                }
+        }
+}
+EXPORT_SYMBOL_GPL(s3c_nand_set_platdata);
diff --git a/arch/arm/plat-s3c/dma.c b/arch/arm/plat-s3c/dma.c
index c9db75c06af5..a995850cd9d5 100644
--- a/arch/arm/plat-s3c/dma.c
+++ b/arch/arm/plat-s3c/dma.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c/dma.c
 *
- * Copyright (c) 2003-2005,2006,2009 Simtec Electronics
+ * Copyright (c) 2003-2009 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
diff --git a/arch/arm/plat-s3c/include/plat/audio-simtec.h b/arch/arm/plat-s3c/include/plat/audio-simtec.h
index 0f440b9168db..53a93656d5db 100644
--- a/arch/arm/plat-s3c/include/plat/audio-simtec.h
+++ b/arch/arm/plat-s3c/include/plat/audio-simtec.h
@@ -33,5 +33,5 @@ struct s3c24xx_audio_simtec_pdata {
        void    (*startup)(void);
 };
-extern int simtec_audio_add(const char *codec_name,
+extern int simtec_audio_add(const char *codec_name, bool has_lr_routing,
                            struct s3c24xx_audio_simtec_pdata *pdata);
diff --git a/arch/arm/plat-s3c/include/plat/cpu-freq.h b/arch/arm/plat-s3c/include/plat/cpu-freq.h
index 7b982b7f28cd..94eb06a2ea5c 100644
--- a/arch/arm/plat-s3c/include/plat/cpu-freq.h
+++ b/arch/arm/plat-s3c/include/plat/cpu-freq.h
@@ -1,6 +1,6 @@
 /* arch/arm/plat-s3c/include/plat/cpu-freq.h
 *
- * Copyright (c) 2006,2007 Simtec Electronics
+ * Copyright (c) 2006-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h
index fbc3d498e02e..d1131ca11e97 100644
--- a/arch/arm/plat-s3c/include/plat/cpu.h
+++ b/arch/arm/plat-s3c/include/plat/cpu.h
@@ -12,6 +12,9 @@
 /* todo - fix when rmk changes iodescs to use `void __iomem *` */
+#ifndef __SAMSUNG_PLAT_CPU_H
+#define __SAMSUNG_PLAT_CPU_H
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 #ifndef MHZ
@@ -73,3 +76,6 @@ extern struct sysdev_class s3c2443_sysclass;
 extern struct sysdev_class s3c6410_sysclass;
 extern struct sysdev_class s3c64xx_sysclass;
+extern void (*s5pc1xx_idle)(void);
+#endif
diff --git a/arch/arm/plat-s3c/include/plat/dma.h b/arch/arm/plat-s3c/include/plat/dma.h
index 34dba98f08e1..e429d10be3ad 100644
--- a/arch/arm/plat-s3c/include/plat/dma.h
+++ b/arch/arm/plat-s3c/include/plat/dma.h
@@ -1,6 +1,6 @@
 /* arch/arm/plat-s3c/include/plat/dma.h
 *
- * Copyright (C) 2003,2004,2006 Simtec Electronics
+ * Copyright (C) 2003-2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * Samsung S3C DMA support
diff --git a/arch/arm/plat-s3c/include/plat/fb.h b/arch/arm/plat-s3c/include/plat/fb.h
index 214ff561b0dd..f8db87930f8b 100644
--- a/arch/arm/plat-s3c/include/plat/fb.h
+++ b/arch/arm/plat-s3c/include/plat/fb.h
@@ -70,4 +70,11 @@ extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
 */
 extern void s3c64xx_fb_gpio_setup_24bpp(void);
+/**
+ * s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD
+ *
+ * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
+ */
+extern void s5pc100_fb_gpio_setup_24bpp(void);
 #endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-s3c/include/plat/iic.h b/arch/arm/plat-s3c/include/plat/iic.h
index 67450f115748..3083df00dee6 100644
--- a/arch/arm/plat-s3c/include/plat/iic.h
+++ b/arch/arm/plat-s3c/include/plat/iic.h
@@ -1,6 +1,6 @@
 /* arch/arm/plat-s3c/include/plat/iic.h
 *
- * Copyright 2004,2009 Simtec Electronics
+ * Copyright 2004-2009 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C - I2C Controller platform_device info
diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h
index 18f958801e64..065985978413 100644
--- a/arch/arm/plat-s3c/include/plat/nand.h
+++ b/arch/arm/plat-s3c/include/plat/nand.h
@@ -55,3 +55,11 @@ struct s3c2410_platform_nand {
                                               int chip);
 };
+/**
+ * s3c_nand_set_platdata() - register NAND platform data.
+ * @nand: The NAND platform data to register with s3c_device_nand.
+ *
+ * This function copies the given NAND platform data, @nand and registers
+ * it with the s3c_device_nand. This allows @nand to be __initdata.
+*/
+extern void s3c_nand_set_platdata(struct s3c2410_platform_nand *nand);
diff --git a/arch/arm/plat-s3c/include/plat/regs-fb-v4.h b/arch/arm/plat-s3c/include/plat/regs-fb-v4.h
new file mode 100644
index 000000000000..a60ed0d06c94
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-fb-v4.h
@@ -0,0 +1,235 @@
+/* arch/arm/plat-s3c/include/plat/regs-fb-v4.h
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C64XX - new-style framebuffer register definitions
+ *
+ * This is the register set for the new style framebuffer interface
+ * found from the S3C2443 onwards and specifically the S3C64XX series
+ * S3C6400 and S3C6410.
+ *
+ * The file contains the cpu specific items which change between whichever
+ * architecture is selected. See <plat/regs-fb.h> for the core definitions
+ * that are the same.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/* include the core definitions here, in case we really do need to
+ * override them at a later date.
+*/
+#include <plat/regs-fb.h>
+#define S3C_FB_MAX_WIN (5)  /* number of hardware windows available. */
+#define VIDCON1_FSTATUS_EVEN    (1 << 15)
+/* Video timing controls */
+#define VIDTCON0                                (0x10)
+#define VIDTCON1                                (0x14)
+#define VIDTCON2                                (0x18)
+/* Window position controls */
+#define WINCON(_win)                            (0x20 + ((_win) * 4))
+/* OSD1 and OSD4 do not have register D */
+#define VIDOSD_A(_win)                          (0x40 + ((_win) * 16))
+#define VIDOSD_B(_win)                          (0x44 + ((_win) * 16))
+#define VIDOSD_C(_win)                          (0x48 + ((_win) * 16))
+#define VIDOSD_D(_win)                          (0x4C + ((_win) * 16))
+#define VIDINTCON0                              (0x130)
+#define WxKEYCONy(_win, _con)                   ((0x140 + ((_win) * 8)) + ((_con) * 4))
+/* WINCONx */
+#define WINCONx_CSCWIDTH_MASK                   (0x3 << 26)
+#define WINCONx_CSCWIDTH_SHIFT                  (26)
+#define WINCONx_CSCWIDTH_WIDE                   (0x0 << 26)
+#define WINCONx_CSCWIDTH_NARROW                 (0x3 << 26)
+#define WINCONx_ENLOCAL                         (1 << 22)
+#define WINCONx_BUFSTATUS                       (1 << 21)
+#define WINCONx_BUFSEL                          (1 << 20)
+#define WINCONx_BUFAUTOEN                       (1 << 19)
+#define WINCONx_YCbCr                           (1 << 13)
+#define WINCON1_LOCALSEL_CAMIF                  (1 << 23)
+#define WINCON2_LOCALSEL_CAMIF                  (1 << 23)
+#define WINCON2_BLD_PIX                         (1 << 6)
+#define WINCON2_ALPHA_SEL                       (1 << 1)
+#define WINCON2_BPPMODE_MASK                    (0xf << 2)
+#define WINCON2_BPPMODE_SHIFT                   (2)
+#define WINCON2_BPPMODE_1BPP                    (0x0 << 2)
+#define WINCON2_BPPMODE_2BPP                    (0x1 << 2)
+#define WINCON2_BPPMODE_4BPP                    (0x2 << 2)
+#define WINCON2_BPPMODE_8BPP_1232               (0x4 << 2)
+#define WINCON2_BPPMODE_16BPP_565               (0x5 << 2)
+#define WINCON2_BPPMODE_16BPP_A1555             (0x6 << 2)
+#define WINCON2_BPPMODE_16BPP_I1555             (0x7 << 2)
+#define WINCON2_BPPMODE_18BPP_666               (0x8 << 2)
+#define WINCON2_BPPMODE_18BPP_A1665             (0x9 << 2)
+#define WINCON2_BPPMODE_19BPP_A1666             (0xa << 2)
+#define WINCON2_BPPMODE_24BPP_888               (0xb << 2)
+#define WINCON2_BPPMODE_24BPP_A1887             (0xc << 2)
+#define WINCON2_BPPMODE_25BPP_A1888             (0xd << 2)
+#define WINCON2_BPPMODE_28BPP_A4888             (0xd << 2)
+#define WINCON3_BLD_PIX                         (1 << 6)
+#define WINCON3_ALPHA_SEL                       (1 << 1)
+#define WINCON3_BPPMODE_MASK                    (0xf << 2)
+#define WINCON3_BPPMODE_SHIFT                   (2)
+#define WINCON3_BPPMODE_1BPP                    (0x0 << 2)
+#define WINCON3_BPPMODE_2BPP                    (0x1 << 2)
+#define WINCON3_BPPMODE_4BPP                    (0x2 << 2)
+#define WINCON3_BPPMODE_16BPP_565               (0x5 << 2)
+#define WINCON3_BPPMODE_16BPP_A1555             (0x6 << 2)
+#define WINCON3_BPPMODE_16BPP_I1555             (0x7 << 2)
+#define WINCON3_BPPMODE_18BPP_666               (0x8 << 2)
+#define WINCON3_BPPMODE_18BPP_A1665             (0x9 << 2)
+#define WINCON3_BPPMODE_19BPP_A1666             (0xa << 2)
+#define WINCON3_BPPMODE_24BPP_888               (0xb << 2)
+#define WINCON3_BPPMODE_24BPP_A1887             (0xc << 2)
+#define WINCON3_BPPMODE_25BPP_A1888             (0xd << 2)
+#define WINCON3_BPPMODE_28BPP_A4888             (0xd << 2)
+#define VIDINTCON0_FIFIOSEL_WINDOW2             (0x10 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW3             (0x20 << 5)
+#define VIDINTCON0_FIFIOSEL_WINDOW4             (0x40 << 5)
+#define DITHMODE                                (0x170)
+#define WINxMAP(_win)                           (0x180 + ((_win) * 4))
+#define DITHMODE_R_POS_MASK                     (0x3 << 5)
+#define DITHMODE_R_POS_SHIFT                    (5)
+#define DITHMODE_R_POS_8BIT                     (0x0 << 5)
+#define DITHMODE_R_POS_6BIT                     (0x1 << 5)
+#define DITHMODE_R_POS_5BIT                     (0x2 << 5)
+#define DITHMODE_G_POS_MASK                     (0x3 << 3)
+#define DITHMODE_G_POS_SHIFT                    (3)
+#define DITHMODE_G_POS_8BIT                     (0x0 << 3)
+#define DITHMODE_G_POS_6BIT                     (0x1 << 3)
+#define DITHMODE_G_POS_5BIT                     (0x2 << 3)
+#define DITHMODE_B_POS_MASK                     (0x3 << 1)
+#define DITHMODE_B_POS_SHIFT                    (1)
+#define DITHMODE_B_POS_8BIT                     (0x0 << 1)
+#define DITHMODE_B_POS_6BIT                     (0x1 << 1)
+#define DITHMODE_B_POS_5BIT                     (0x2 << 1)
+#define DITHMODE_DITH_EN                        (1 << 0)
+#define WPALCON                                 (0x1A0)
+/* Palette control */
+/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
+ * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
+#define WPALCON_W4PAL_16BPP_A555                (1 << 8)
+#define WPALCON_W3PAL_16BPP_A555                (1 << 7)
+#define WPALCON_W2PAL_16BPP_A555                (1 << 6)
+/* system specific implementation code for palette sizes, and other
+ * information that changes depending on which architecture is being
+ * compiled.
+*/
+/* return true if window _win has OSD register D */
+#define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0)
+static inline unsigned int s3c_fb_win_pal_size(unsigned int win)
+{
+        if (win < 2)
+                return 256;
+        if (win < 4)
+                return 16;
+        if (win == 4)
+                return 4;
+        BUG();  /* shouldn't get here */
+}
+static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp)
+{
+        /* all windows can do 1/2 bpp */
+        if ((bpp == 25 || bpp == 19) && win == 0)
+                return 0;       /* win 0 does not have 19 or 25bpp modes */
+        if (bpp == 4 && win == 4)
+                return 0;
+        if (bpp == 8 && (win >= 3))
+                return 0;       /* win 3/4 cannot do 8bpp in any mode */
+        return 1;
+}
+static inline int s3c_fb_pal_is16(unsigned int window)
+{
+        return window > 1;
+}
+struct s3c_fb_palette {
+        struct fb_bitfield      r;
+        struct fb_bitfield      g;
+        struct fb_bitfield      b;
+        struct fb_bitfield      a;
+};
+static inline void s3c_fb_init_palette(unsigned int window,
+                                       struct s3c_fb_palette *palette)
+{
+        if (window < 2) {
+                /* Windows 0/1 are 8/8/8 or A/8/8/8 */
+                palette->r.offset = 16;
+                palette->r.length = 8;
+                palette->g.offset = 8;
+                palette->g.length = 8;
+                palette->b.offset = 0;
+                palette->b.length = 8;
+        } else {
+                /* currently we assume RGB 5/6/5 */
+                palette->r.offset = 11;
+                palette->r.length = 5;
+                palette->g.offset = 5;
+                palette->g.length = 6;
+                palette->b.offset = 0;
+                palette->b.length = 5;
+        }
+}
+/* Notes on per-window bpp settings
+ *
+ * Value        Win0     Win1     Win2     Win3     Win 4
+ * 0000         1(P)     1(P)     1(P)     1(P)     1(P)
+ * 0001         2(P)     2(P)     2(P)     2(P)     2(P)
+ * 0010         4(P)     4(P)     4(P)     4(P)     -none-
+ * 0011         8(P)     8(P)     -none-   -none-   -none-
+ * 0100         -none-   8(A232)  8(A232)  -none-   -none-
+ * 0101         16(565)  16(565)  16(565)  16(565)   16(565)
+ * 0110         -none-   16(A555) 16(A555) 16(A555)  16(A555)
+ * 0111         16(I555) 16(I565) 16(I555) 16(I555)  16(I555)
+ * 1000         18(666)  18(666)  18(666)  18(666)   18(666)
+ * 1001         -none-   18(A665) 18(A665) 18(A665)  16(A665)
+ * 1010         -none-   19(A666) 19(A666) 19(A666)  19(A666)
+ * 1011         24(888)  24(888)  24(888)  24(888)   24(888)
+ * 1100         -none-   24(A887) 24(A887) 24(A887)  24(A887)
+ * 1101         -none-   25(A888) 25(A888) 25(A888)  25(A888)
+ * 1110         -none-   -none-   -none-   -none-    -none-
+ * 1111         -none-   -none-   -none-   -none-    -none-
+*/
diff --git a/arch/arm/plat-s3c/include/plat/regs-nand.h b/arch/arm/plat-s3c/include/plat/regs-nand.h
index b2caa4bca270..238efea7b9e4 100644
--- a/arch/arm/plat-s3c/include/plat/regs-nand.h
+++ b/arch/arm/plat-s3c/include/plat/regs-nand.h
@@ -1,7 +1,7 @@
 /* arch/arm/mach-s3c2410/include/mach/regs-nand.h
 *
- * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
+ * Copyright (c) 2004-2005 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
+ *      http://www.simtec.co.uk/products/SWLINUX/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h
index 66af75a5cdd1..85d8904e7f24 100644
--- a/arch/arm/plat-s3c/include/plat/regs-serial.h
+++ b/arch/arm/plat-s3c/include/plat/regs-serial.h
@@ -6,7 +6,7 @@
 *
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *
- *  Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
+ *  Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
 *
 *  Adapted from:
 *
diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h
index f615308ccdfb..53198673b6bd 100644
--- a/arch/arm/plat-s3c/include/plat/sdhci.h
+++ b/arch/arm/plat-s3c/include/plat/sdhci.h
@@ -57,6 +57,7 @@ struct s3c_sdhci_platdata {
 */
 extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
 extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
+extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd);
 /* Default platform data, exported so that per-cpu initialisation can
 * set the correct one when there are more than one cpu type selected.
@@ -64,11 +65,16 @@ extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
 extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
 extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
+extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata;
 /* Helper function availablity */
 extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
+extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 /* S3C6400 SDHCI setup */
@@ -103,6 +109,17 @@ static inline void s3c6400_default_sdhci1(void)
 static inline void s3c6400_default_sdhci1(void) { }
 #endif /* CONFIG_S3C_DEV_HSMMC1 */
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s3c6400_default_sdhci2(void)
+{
+        s3c_hsmmc2_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c6400_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC2 */
 #else
 static inline void s3c6400_default_sdhci0(void) { }
 static inline void s3c6400_default_sdhci1(void) { }
@@ -140,9 +157,70 @@ static inline void s3c6410_default_sdhci1(void)
 static inline void s3c6410_default_sdhci1(void) { }
 #endif /* CONFIG_S3C_DEV_HSMMC1 */
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s3c6410_default_sdhci2(void)
+{
+        s3c_hsmmc2_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s3c6410_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC2 */
 #else
 static inline void s3c6410_default_sdhci0(void) { }
 static inline void s3c6410_default_sdhci1(void) { }
 #endif /* CONFIG_S3C6410_SETUP_SDHCI */
+/* S5PC100 SDHCI setup */
+#ifdef CONFIG_S5PC100_SETUP_SDHCI
+extern char *s5pc100_hsmmc_clksrcs[4];
+extern void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev,
+                                           void __iomem *r,
+                                           struct mmc_ios *ios,
+                                           struct mmc_card *card);
+#ifdef CONFIG_S3C_DEV_HSMMC
+static inline void s5pc100_default_sdhci0(void)
+{
+        s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
+        s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
+        s3c_hsmmc0_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s5pc100_default_sdhci0(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC */
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static inline void s5pc100_default_sdhci1(void)
+{
+        s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
+        s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
+        s3c_hsmmc1_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s5pc100_default_sdhci1(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+#ifdef CONFIG_S3C_DEV_HSMMC2
+static inline void s5pc100_default_sdhci2(void)
+{
+        s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs;
+        s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
+        s3c_hsmmc2_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card;
+}
+#else
+static inline void s5pc100_default_sdhci2(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+#else
+static inline void s5pc100_default_sdhci0(void) { }
+static inline void s5pc100_default_sdhci1(void) { }
+static inline void s5pc100_default_sdhci2(void) { }
+#endif /* CONFIG_S5PC100_SETUP_SDHCI */
 #endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-s3c/pm-check.c b/arch/arm/plat-s3c/pm-check.c
index 39f2555564da..8eb1f439861c 100644
--- a/arch/arm/plat-s3c/pm-check.c
+++ b/arch/arm/plat-s3c/pm-check.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/plat-s3c/pm-check.c
 *  originally in linux/arch/arm/plat-s3c24xx/pm.c
 *
- * Copyright (c) 2004,2006,2008 Simtec Electronics
+ * Copyright (c) 2004-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c
index 8d97db2c7a0d..767470601e5c 100644
--- a/arch/arm/plat-s3c/pm.c
+++ b/arch/arm/plat-s3c/pm.c
@@ -1,7 +1,7 @@
 /* linux/arch/arm/plat-s3c/pm.c
 *
 * Copyright 2008 Openmoko, Inc.
- * Copyright 2004,2006,2008 Simtec Electronics
+ * Copyright 2004-2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 9c7aca489643..20fbf936bb93 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -178,4 +178,11 @@ config MACH_SMDK
        help
          Common machine code for SMDK2410 and SMDK2440
+config S3C24XX_SIMTEC_AUDIO
+        bool
+        depends on (ARCH_BAST || MACH_VR1000 || MACH_OSIRIS || MACH_ANUBIS)
+        default y
+        help
+          Add audio devices for common Simtec S3C24XX boards
 endif
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 7780d2dd833a..5dee8c12e8b4 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10)	 += spi-bus1-gpd8_9_10.o
 # machine common support
 obj-$(CONFIG_MACH_SMDK)         += common-smdk.o
+obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO)      += simtec-audio.o
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index 0afb217a775e..ac061a1bcb37 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/clock-dclk.c
 *
- * Copyright (c) 2004,2008 Simtec Electronics
+ * Copyright (c) 2004-2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index aa119863c5ce..9e0e20ad2e46 100644
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -198,7 +198,7 @@ void __init smdk_machine_init(void)
        if (machine_is_smdk2443())
                smdk_nand_info.twrph0 = 50;
-        s3c_device_nand.dev.platform_data = &smdk_nand_info;
+        s3c_nand_set_platdata(&smdk_nand_info);
        platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs));
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c
index 4f1b789a1173..2d42efb9f4e9 100644
--- a/arch/arm/plat-s3c24xx/cpu-freq.c
+++ b/arch/arm/plat-s3c24xx/cpu-freq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/cpu-freq.c
 *
- * Copyright (c) 2006,2007,2008 Simtec Electronics
+ * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index f046f8c51084..f65192d5b1d7 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/dma.c
 *
- * Copyright (c) 2003-2005,2006 Simtec Electronics
+ * Copyright 2003-2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2410 DMA core
@@ -1310,7 +1310,7 @@ int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
        int channel;
        int ret;
-        printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n");
+        printk("S3C24XX DMA Driver, Copyright 2003-2006 Simtec Electronics\n");
        dma_channels = channels;
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
index c776120b99e6..33d421d78bad 100644
--- a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
@@ -1,6 +1,6 @@
 /* arch/arm/plat-s3c/include/plat/cpu-freq.h
 *
- * Copyright (c) 2006,2007,2009 Simtec Electronics
+ * Copyright (c) 2006-2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-s3c24xx/include/plat/mci.h
index c2cef6139683..36aaa10fad06 100644
--- a/arch/arm/plat-s3c24xx/include/plat/mci.h
+++ b/arch/arm/plat-s3c24xx/include/plat/mci.h
@@ -1,6 +1,31 @@
 #ifndef _ARCH_MCI_H
 #define _ARCH_MCI_H
+/**
+ * struct s3c24xx_mci_pdata - sd/mmc controller platform data
+ * @no_wprotect: Set this to indicate there is no write-protect switch.
+ * @no_detect: Set this if there is no detect switch.
+ * @wprotect_invert: Invert the default sense of the write protect switch.
+ * @detect_invert: Invert the default sense of the write protect switch.
+ * @use_dma: Set to allow the use of DMA.
+ * @gpio_detect: GPIO number for the card detect line.
+ * @gpio_wprotect: GPIO number for the write protect line.
+ * @ocr_avail: The mask of the available power states, non-zero to use.
+ * @set_power: Callback to control the power mode.
+ *
+ * The @gpio_detect is used for card detection when @no_wprotect is unset,
+ * and the default sense is that 0 returned from gpio_get_value() means
+ * that a card is inserted. If @detect_invert is set, then the value from
+ * gpio_get_value() is inverted, which makes 1 mean card inserted.
+ *
+ * The driver will use @gpio_wprotect to signal whether the card is write
+ * protected if @no_wprotect is not set. A 0 returned from gpio_get_value()
+ * means the card is read/write, and 1 means read-only. The @wprotect_invert
+ * will invert the value returned from gpio_get_value().
+ *
+ * Card power is set by @ocr_availa, using MCC_VDD_ constants if it is set
+ * to a non-zero value, otherwise the default of 3.2-3.4V is used.
+ */
 struct s3c24xx_mci_pdata {
        unsigned int    no_wprotect : 1;
        unsigned int    no_detect : 1;
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
index 3bc0a216df97..1b0f4c36d384 100644
--- a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h
@@ -1,6 +1,6 @@
 /* arch/arm/mach-s3c2410/include/mach/dma.h
 *
- * Copyright (C) 2003,2004,2006 Simtec Electronics
+ * Copyright (C) 2003-2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * Samsung S3C24XX DMA support
diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c
index b7acf1a8ecd2..ea8dea3339a4 100644
--- a/arch/arm/plat-s3c24xx/irq-pm.c
+++ b/arch/arm/plat-s3c24xx/irq-pm.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/irq-om.c
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *      http://armlinux.simtec.co.uk/
 *
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index d02f5f02045e..ef0f521437d7 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/irq.c
 *
- * Copyright (c) 2003,2004 Simtec Electronics 
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c
index da0d3217d3e3..663b280d65da 100644
--- a/arch/arm/plat-s3c24xx/pm-simtec.c
+++ b/arch/arm/plat-s3c24xx/pm-simtec.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/pm-simtec.c
 *
- * Copyright (c) 2004 Simtec Electronics
+ * Copyright 2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * http://armlinux.simtec.co.uk/
@@ -35,7 +35,7 @@
 #include <plat/pm.h>
-#define COPYRIGHT ", (c) 2005 Simtec Electronics"
+#define COPYRIGHT ", Copyright 2005 Simtec Electronics"
 /* pm_simtec_init
 *
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 56e5253ca02c..3620dd299095 100644
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/pm.c
 *
- * Copyright (c) 2004,2006 Simtec Electronics
+ * Copyright (c) 2004-2006 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C24XX Power Manager (Suspend-To-RAM) support
diff --git a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
index d0a3a145cd4d..963fb0b4379e 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
 *
- * Copyright (c) 2006,2008,2009 Simtec Electronics
+ * Copyright (c) 2006-2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
index fd45e47facbc..24993dce10b5 100644
--- a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
+++ b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
 *
- * Copyright (c) 2006,2008 Simtec Electronics
+ * Copyright (c) 2006-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
index ae2e6c604f27..976002fb1b8f 100644
--- a/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
+++ b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
 *
- * Copyright (c) 2006,2008,2009 Simtec Electronics
+ * Copyright (c) 2006-2009 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *      Vincent Sanders <vince@simtec.co.uk>
diff --git a/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
index ff9443b233aa..49f65032f2c0 100644
--- a/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
+++ b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
@@ -1,6 +1,6 @@
 /* arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
 *
- * Copyright (c) 2006,2007 Simtec Electronics
+ * Copyright (c) 2006-2007 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *      Vincent Sanders <vince@arm.linux.org.uk>
diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c
index dde41f171aff..79371091aa38 100644
--- a/arch/arm/plat-s3c24xx/s3c244x-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
 *
- * Copyright (c) 2004-2005,2008 Simtec Electronics
+ * Copyright (c) 2004-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
diff --git a/arch/arm/plat-s3c24xx/s3c244x-irq.c b/arch/arm/plat-s3c24xx/s3c244x-irq.c
index 0902afd227ca..a75c0c2431ea 100644
--- a/arch/arm/plat-s3c24xx/s3c244x-irq.c
+++ b/arch/arm/plat-s3c24xx/s3c244x-irq.c
@@ -1,6 +1,6 @@
 /* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c
 *
- * Copyright (c) 2003,2004 Simtec Electronics
+ * Copyright (c) 2003-2004 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
diff --git a/arch/arm/plat-s3c24xx/simtec-audio.c b/arch/arm/plat-s3c24xx/simtec-audio.c
new file mode 100644
index 000000000000..6bc832e0d8ea
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/simtec-audio.c
@@ -0,0 +1,77 @@
+/* linux/arch/arm/plat-s3c24xx/simtec-audio.c
+ *
+ * Copyright (c) 2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Audio setup for various Simtec S3C24XX implementations
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <mach/bast-map.h>
+#include <mach/bast-irq.h>
+#include <mach/bast-cpld.h>
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+#include <plat/audio-simtec.h>
+#include <plat/devs.h>
+/* platform ops for audio */
+static void simtec_audio_startup_lrroute(void)
+{
+        unsigned int tmp;
+        unsigned long flags;
+        local_irq_save(flags);
+        tmp = __raw_readb(BAST_VA_CTRL1);
+        tmp &= ~BAST_CPLD_CTRL1_LRMASK;
+        tmp |= BAST_CPLD_CTRL1_LRCDAC;
+        __raw_writeb(tmp, BAST_VA_CTRL1);
+        local_irq_restore(flags);
+}
+static struct s3c24xx_audio_simtec_pdata simtec_audio_platdata;
+static char our_name[32];
+static struct platform_device simtec_audio_dev = {
+        .name   = our_name,
+        .id     = -1,
+        .dev    = {
+                .parent         = &s3c_device_iis.dev,
+                .platform_data  = &simtec_audio_platdata,
+        },
+};
+int __init simtec_audio_add(const char *name, bool has_lr_routing,
+                            struct s3c24xx_audio_simtec_pdata *spd)
+{
+        if (!name)
+                name = "tlv320aic23";
+        snprintf(our_name, sizeof(our_name)-1, "s3c24xx-simtec-%s", name);
+        /* copy platform data so the source can be __initdata */
+        if (spd)
+                simtec_audio_platdata = *spd;
+        if (has_lr_routing)
+                simtec_audio_platdata.startup = simtec_audio_startup_lrroute;
+        platform_device_register(&s3c_device_iis);
+        platform_device_register(&simtec_audio_dev);
+        return 0;
+}
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c
index b1fdd83940a6..49796d2db86d 100644
--- a/arch/arm/plat-s3c64xx/cpu.c
+++ b/arch/arm/plat-s3c64xx/cpu.c
@@ -107,6 +107,11 @@ static struct map_desc s3c_iodesc[] __initdata = {
                .pfn            = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
+                .length         = SZ_1K,
+                .type           = MT_DEVICE,
        },
 };
diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c
index e6e0843215df..74c0e8347de5 100644
--- a/arch/arm/plat-s3c64xx/cpufreq.c
+++ b/arch/arm/plat-s3c64xx/cpufreq.c
@@ -19,6 +19,7 @@
 static struct clk *armclk;
 static struct regulator *vddarm;
+static unsigned long regulator_latency;
 #ifdef CONFIG_CPU_S3C6410
 struct s3c64xx_dvfs {
@@ -27,11 +28,10 @@ struct s3c64xx_dvfs {
 };
 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
-        [0] = { 1000000, 1000000 },
+        [0] = { 1000000, 1150000 },
-        [1] = { 1000000, 1050000 },
+        [1] = { 1050000, 1150000 },
-        [2] = { 1050000, 1100000 },
+        [2] = { 1100000, 1150000 },
-        [3] = { 1050000, 1150000 },
+        [3] = { 1200000, 1350000 },
-        [4] = { 1250000, 1350000 },
 };
 static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
@@ -41,9 +41,9 @@ static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
        { 1, 266000 },
        { 2, 333000 },
        { 2, 400000 },
-        { 3, 532000 },
+        { 2, 532000 },
-        { 3, 533000 },
+        { 2, 533000 },
-        { 4, 667000 },
+        { 3, 667000 },
        { 0, CPUFREQ_TABLE_END },
 };
 #endif
@@ -141,7 +141,7 @@ err:
 }
 #ifdef CONFIG_REGULATOR
-static void __init s3c64xx_cpufreq_constrain_voltages(void)
+static void __init s3c64xx_cpufreq_config_regulator(void)
 {
        int count, v, i, found;
        struct cpufreq_frequency_table *freq;
@@ -150,11 +150,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void)
        count = regulator_count_voltages(vddarm);
        if (count < 0) {
                pr_err("cpufreq: Unable to check supported voltages\n");
-                return;
        }
        freq = s3c64xx_freq_table;
-        while (freq->frequency != CPUFREQ_TABLE_END) {
+        while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
                if (freq->frequency == CPUFREQ_ENTRY_INVALID)
                        continue;
@@ -175,6 +174,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void)
                freq++;
        }
+        /* Guess based on having to do an I2C/SPI write; in future we
+         * will be able to query the regulator performance here. */
+        regulator_latency = 1 * 1000 * 1000;
 }
 #endif
@@ -206,7 +209,7 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
                pr_err("cpufreq: Only frequency scaling available\n");
                vddarm = NULL;
        } else {
-                s3c64xx_cpufreq_constrain_voltages();
+                s3c64xx_cpufreq_config_regulator();
        }
 #endif
@@ -217,8 +220,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
                /* Check for frequencies we can generate */
                r = clk_round_rate(armclk, freq->frequency * 1000);
                r /= 1000;
-                if (r != freq->frequency)
+                if (r != freq->frequency) {
+                        pr_debug("cpufreq: %dkHz unsupported by clock\n",
+                                 freq->frequency);
                        freq->frequency = CPUFREQ_ENTRY_INVALID;
+                }
                /* If we have no regulator then assume startup
                 * frequency is the maximum we can support. */
@@ -230,9 +236,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
        policy->cur = clk_get_rate(armclk) / 1000;
-        /* Pick a conservative guess in ns: we'll need ~1 I2C/SPI
+        /* Datasheet says PLL stabalisation time (if we were to use
-         * write plus clock reprogramming. */
+         * the PLLs, which we don't currently) is ~300us worst case,
-        policy->cpuinfo.transition_latency = 2 * 1000 * 1000;
+         * but add some fudge.
+         */
+        policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
        ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
        if (ret != 0) {
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c
index 92859290ea33..778560457277 100644
--- a/arch/arm/plat-s3c64xx/gpiolib.c
+++ b/arch/arm/plat-s3c64xx/gpiolib.c
@@ -213,6 +213,11 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
        .get_pull       = s3c_gpio_getpull_updown,
 };
+int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
+{
+        return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
+}
 static struct s3c_gpio_chip gpio_4bit[] = {
        {
                .base   = S3C64XX_GPA_BASE,
@@ -269,10 +274,16 @@ static struct s3c_gpio_chip gpio_4bit[] = {
                        .base   = S3C64XX_GPM(0),
                        .ngpio  = S3C64XX_GPIO_M_NR,
                        .label  = "GPM",
+                        .to_irq = s3c64xx_gpio2int_gpm,
                },
        },
 };
+int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
+{
+        return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
+}
 static struct s3c_gpio_chip gpio_4bit2[] = {
        {
                .base   = S3C64XX_GPH_BASE + 0x4,
@@ -297,6 +308,7 @@ static struct s3c_gpio_chip gpio_4bit2[] = {
                        .base   = S3C64XX_GPL(0),
                        .ngpio  = S3C64XX_GPIO_L_NR,
                        .label  = "GPL",
+                        .to_irq = s3c64xx_gpio2int_gpl,
                },
        },
 };
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
index c47daf7e2723..e22b49f4f982 100644
--- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h
@@ -36,18 +36,18 @@
 #define S3C64XX_GPC4_SPI_MISO1          (0x02 << 16)
 #define S3C64XX_GPC4_MMC2_CMD           (0x03 << 16)
-#define S3C64XX_GPC4_I2S0_V40_DO        (0x05 << 16)
+#define S3C64XX_GPC4_I2S_V40_DO0        (0x05 << 16)
 #define S3C64XX_GPC4_EINT_G2_4          (0x07 << 16)
 #define S3C64XX_GPC5_SPI_CLK1           (0x02 << 20)
 #define S3C64XX_GPC5_MMC2_CLK           (0x03 << 20)
-#define S3C64XX_GPC5_I2S1_V40_DO        (0x05 << 20)
+#define S3C64XX_GPC5_I2S_V40_DO1        (0x05 << 20)
 #define S3C64XX_GPC5_EINT_G2_5          (0x07 << 20)
 #define S3C64XX_GPC6_SPI_MOSI1          (0x02 << 24)
 #define S3C64XX_GPC6_EINT_G2_6          (0x07 << 24)
 #define S3C64XX_GPC7_SPI_nCS1           (0x02 << 28)
-#define S3C64XX_GPC7_I2S2_V40_DO        (0x05 << 28)
+#define S3C64XX_GPC7_I2S_V40_DO2        (0x05 << 28)
 #define S3C64XX_GPC7_EINT_G2_7          (0x07 << 28)
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c
index f81b7b818ba0..ebdf183a0911 100644
--- a/arch/arm/plat-s3c64xx/irq-eint.c
+++ b/arch/arm/plat-s3c64xx/irq-eint.c
@@ -65,7 +65,7 @@ static void s3c_irq_eint_maskack(unsigned int irq)
 static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
 {
        int offs = eint_offset(irq);
-        int pin;
+        int pin, pin_val;
        int shift;
        u32 ctrl, mask;
        u32 newvalue = 0;
@@ -109,7 +109,10 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
                return -1;
        }
-        shift = (offs / 2) * 4;
+        if (offs <= 15)
+                shift = (offs / 2) * 4;
+        else
+                shift = ((offs - 16) / 2) * 4;
        mask = 0x7 << shift;
        ctrl = __raw_readl(reg);
@@ -119,12 +122,18 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
        /* set the GPIO pin appropriately */
-        if (offs < 23)
+        if (offs < 16) {
                pin = S3C64XX_GPN(offs);
-        else
+                pin_val = S3C_GPIO_SFN(2);
+        } else if (offs < 23) {
+                pin = S3C64XX_GPL(offs + 8 - 16);
+                pin_val = S3C_GPIO_SFN(3);
+        } else {
                pin = S3C64XX_GPM(offs - 23);
+                pin_val = S3C_GPIO_SFN(3);
+        }
-        s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2));
+        s3c_gpio_cfgpin(pin, pin_val);
        return 0;
 }
diff --git a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
index 5417123b0ac1..a58c0cc7ba5e 100644
--- a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
+++ b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
@@ -53,3 +53,23 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
        s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
        s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
 }
+void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+        end = S3C64XX_GPH(6 + width);
+        /* Set all the necessary GPH pins to special-function 1 */
+        for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        /* Set all the necessary GPC pins to special-function 1 */
+        for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+}
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
index a8a711c3c064..1608e62b0c9d 100644
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -15,6 +15,9 @@ config PLAT_S5PC1XX
        select ARCH_REQUIRE_GPIOLIB
        select S3C_GPIO_TRACK
        select S3C_GPIO_PULL_UPDOWN
+        select S3C_GPIO_CFG_S3C24XX
+        select S3C_GPIO_CFG_S3C64XX
+        select S5P_GPIO_CFG_S5PC1XX
        help
          Base platform code for any Samsung S5PC1XX device
@@ -34,7 +37,12 @@ config CPU_S5PC100_CLOCK
 # platform specific device setup
-config S5PC100_SETUP_I2C0
+config S5PC1XX_SETUP_FB_24BPP
+        bool
+        help
+          Common setup code for S5PC1XX with an 24bpp RGB display helper.
+config S5PC1XX_SETUP_I2C0
        bool
        default y
        help
@@ -43,8 +51,14 @@ config S5PC100_SETUP_I2C0
          Note, currently since i2c0 is always compiled, this setup helper
          is always compiled with it.
-config S5PC100_SETUP_I2C1
+config S5PC1XX_SETUP_I2C1
        bool
        help
          Common setup code for i2c bus 1.
+config S5PC1XX_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for SDHCI gpio.
 endif
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
index f1ecb2c37ee2..278f26806089 100644
--- a/arch/arm/plat-s5pc1xx/Makefile
+++ b/arch/arm/plat-s5pc1xx/Makefile
@@ -13,7 +13,9 @@ obj-				:=
 obj-y                           += dev-uart.o
 obj-y                           += cpu.o
-obj-y                           += irq.o
+obj-y                           += irq.o irq-gpio.o irq-eint.o
+obj-y                           += clock.o
+obj-y                           += gpiolib.o
 # CPU support
@@ -22,5 +24,8 @@ obj-$(CONFIG_CPU_S5PC100_CLOCK)	+= s5pc100-clock.o
 # Device setup
-obj-$(CONFIG_S5PC100_SETUP_I2C0) += setup-i2c0.o
+obj-$(CONFIG_S5P_GPIO_CFG_S5PC1XX) += gpio-config.o
-obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
+obj-$(CONFIG_S5PC1XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
+obj-$(CONFIG_S5PC1XX_SETUP_I2C0) += setup-i2c0.o
+obj-$(CONFIG_S5PC1XX_SETUP_I2C1) += setup-i2c1.o
+obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
new file mode 100644
index 000000000000..26c21d849790
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/clock.c
@@ -0,0 +1,728 @@
+/* linux/arch/arm/plat-s5pc1xx/clock.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *
+ * S5PC1XX Base clock support
+ *
+ * Based on plat-s3c64xx/clock.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <plat/regs-clock.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+struct clk clk_27m = {
+        .name           = "clk_27m",
+        .id             = -1,
+        .rate           = 27000000,
+};
+static int clk_48m_ctrl(struct clk *clk, int enable)
+{
+        unsigned long flags;
+        u32 val;
+        /* can't rely on clock lock, this register has other usages */
+        local_irq_save(flags);
+        val = __raw_readl(S5PC100_CLKSRC1);
+        if (enable)
+                val |= S5PC100_CLKSRC1_CLK48M_MASK;
+        else
+                val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
+        __raw_writel(val, S5PC100_CLKSRC1);
+        local_irq_restore(flags);
+        return 0;
+}
+struct clk clk_48m = {
+        .name           = "clk_48m",
+        .id             = -1,
+        .rate           = 48000000,
+        .enable         = clk_48m_ctrl,
+};
+struct clk clk_54m = {
+        .name           = "clk_54m",
+        .id             = -1,
+        .rate           = 54000000,
+};
+static int clk_default_setrate(struct clk *clk, unsigned long rate)
+{
+        clk->rate = rate;
+        return 0;
+}
+static int clk_dummy_enable(struct clk *clk, int enable)
+{
+        return 0;
+}
+struct clk clk_hd0 = {
+        .name           = "hclkd0",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = NULL,
+        .ctrlbit        = 0,
+        .set_rate       = clk_default_setrate,
+        .enable         = clk_dummy_enable,
+};
+struct clk clk_pd0 = {
+        .name           = "pclkd0",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = NULL,
+        .ctrlbit        = 0,
+        .set_rate       = clk_default_setrate,
+        .enable         = clk_dummy_enable,
+};
+static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
+{
+        unsigned int ctrlbit = clk->ctrlbit;
+        u32 con;
+        con = __raw_readl(reg);
+        if (enable)
+                con |= ctrlbit;
+        else
+                con &= ~ctrlbit;
+        __raw_writel(con, reg);
+        return 0;
+}
+static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
+}
+static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
+}
+static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
+}
+static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
+}
+static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
+}
+static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
+}
+static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
+}
+static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
+}
+static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
+}
+static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
+}
+int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
+}
+int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
+}
+static struct clk s5pc100_init_clocks_disable[] = {
+        {
+                .name           = "dsi",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_DSI,
+        }, {
+                .name           = "csi",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_CSI,
+        }, {
+                .name           = "ccan",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN0,
+        }, {
+                .name           = "ccan",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN1,
+        }, {
+                .name           = "keypad",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_KEYIF,
+        }, {
+                .name           = "hclkd2",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc100_clk_d20_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D20_HCLKD2,
+        }, {
+                .name           = "iis-d2",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc100_clk_d20_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D20_I2SD2,
+        },
+};
+static struct clk s5pc100_init_clocks[] = {
+        /* System1 (D0_0) devices */
+        {
+                .name           = "intc",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_INTC,
+        }, {
+                .name           = "tzic",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_TZIC,
+        }, {
+                .name           = "cf-ata",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_CFCON,
+        }, {
+                .name           = "mdma",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_MDMA,
+        }, {
+                .name           = "g2d",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_G2D,
+        }, {
+                .name           = "secss",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_SECSS,
+        }, {
+                .name           = "cssys",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_CSSYS,
+        },
+        /* Memory (D0_1) devices */
+        {
+                .name           = "dmc",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_DMC,
+        }, {
+                .name           = "sromc",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_SROMC,
+        }, {
+                .name           = "onenand",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_ONENAND,
+        }, {
+                .name           = "nand",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_NFCON,
+        }, {
+                .name           = "intmem",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_INTMEM,
+        }, {
+                .name           = "ebi",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_EBI,
+        },
+        /* System2 (D0_2) devices */
+        {
+                .name           = "seckey",
+                .id             = -1,
+                .parent         = &clk_pd0,
+                .enable         = s5pc100_clk_d02_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D02_SECKEY,
+        }, {
+                .name           = "sdm",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc100_clk_d02_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D02_SDM,
+        },
+        /* File (D1_0) devices */
+        {
+                .name           = "pdma",
+                .id             = 0,
+                .parent         = &clk_h,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA0,
+        }, {
+                .name           = "pdma",
+                .id             = 1,
+                .parent         = &clk_h,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA1,
+        }, {
+                .name           = "usb-host",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_USBHOST,
+        }, {
+                .name           = "otg",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_USBOTG,
+        }, {
+                .name           = "modem",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_MODEMIF,
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC0,
+        }, {
+                .name           = "hsmmc",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC1,
+        }, {
+                .name           = "hsmmc",
+                .id             = 2,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC2,
+        },
+        /* Multimedia1 (D1_1) devices */
+        {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_LCD,
+        }, {
+                .name           = "rotator",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_ROTATOR,
+        }, {
+                .name           = "fimc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC0,
+        }, {
+                .name           = "fimc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC1,
+        }, {
+                .name           = "fimc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC2,
+        }, {
+                .name           = "jpeg",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_JPEG,
+        }, {
+                .name           = "g3d",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_G3D,
+        },
+        /* Multimedia2 (D1_2) devices */
+        {
+                .name           = "tv",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_TV,
+        }, {
+                .name           = "vp",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_VP,
+        }, {
+                .name           = "mixer",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_MIXER,
+        }, {
+                .name           = "hdmi",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_HDMI,
+        }, {
+                .name           = "mfc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_MFC,
+        },
+        /* System (D1_3) devices */
+        {
+                .name           = "chipid",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_CHIPID,
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_GPIO,
+        }, {
+                .name           = "apc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_APC,
+        }, {
+                .name           = "iec",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_IEC,
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_PWM,
+        }, {
+                .name           = "systimer",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_SYSTIMER,
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_WDT,
+        }, {
+                .name           = "rtc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_RTC,
+        },
+        /* Connectivity (D1_4) devices */
+        {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART0,
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART1,
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART2,
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART3,
+        }, {
+                .name           = "i2c",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_IIC,
+        }, {
+                .name           = "hdmi-i2c",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_HDMI_IIC,
+        }, {
+                .name           = "spi",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_SPI0,
+        }, {
+                .name           = "spi",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_SPI1,
+        }, {
+                .name           = "spi",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_SPI2,
+        }, {
+                .name           = "irda",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_IRDA,
+        }, {
+                .name           = "hsitx",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_HSITX,
+        }, {
+                .name           = "hsirx",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_HSIRX,
+        },
+        /* Audio (D1_5) devices */
+        {
+                .name           = "iis",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_IIS0,
+        }, {
+                .name           = "iis",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_IIS1,
+        }, {
+                .name           = "iis",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_IIS2,
+        }, {
+                .name           = "ac97",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_AC97,
+        }, {
+                .name           = "pcm",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_PCM0,
+        }, {
+                .name           = "pcm",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_PCM1,
+        }, {
+                .name           = "spdif",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_SPDIF,
+        }, {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_TSADC,
+        }, {
+                .name           = "cg",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc100_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_CG,
+        },
+        /* Audio (D2_0) devices: all disabled */
+        /* Special Clocks 0 */
+        {
+                .name           = "sclk_hpm",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_HPM,
+        }, {
+                .name           = "sclk_onenand",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_ONENAND,
+        }, {
+                .name           = "spi_48",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI0_48,
+        }, {
+                .name           = "spi_48",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI1_48,
+        }, {
+                .name           = "spi_48",
+                .id             = 2,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI2_48,
+        }, {
+                .name           = "mmc_48",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC0_48,
+        }, {
+                .name           = "mmc_48",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC1_48,
+        }, {
+                .name           = "mmc_48",
+                .id             = 2,
+                .parent         = &clk_48m,
+                .enable         = s5pc100_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC2_48,
+        },
+        /* Special Clocks 1 */
+};
+static struct clk *clks[] __initdata = {
+        &clk_ext,
+        &clk_epll,
+        &clk_27m,
+        &clk_48m,
+        &clk_54m,
+};
+void __init s5pc1xx_register_clocks(void)
+{
+        struct clk *clkp;
+        int ret;
+        int ptr;
+        int size;
+        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+        clkp = s5pc100_init_clocks;
+        size = ARRAY_SIZE(s5pc100_init_clocks);
+        for (ptr = 0; ptr < size; ptr++, clkp++) {
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+        }
+        clkp = s5pc100_init_clocks_disable;
+        size = ARRAY_SIZE(s5pc100_init_clocks_disable);
+        for (ptr = 0; ptr < size; ptr++, clkp++) {
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+                (clkp->enable)(clkp, 0);
+        }
+        s3c_pwmclk_init();
+}
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
index 715a7330794d..02baeaa2a121 100644
--- a/arch/arm/plat-s5pc1xx/cpu.c
+++ b/arch/arm/plat-s5pc1xx/cpu.c
@@ -55,6 +55,16 @@ static struct cpu_table cpu_ids[] __initdata = {
 static struct map_desc s5pc1xx_iodesc[] __initdata = {
        {
+                .virtual        = (unsigned long)S5PC1XX_VA_CLK_OTHER,
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_CLK_OTHER),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5PC100_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
                .virtual        = (unsigned long)S5PC1XX_VA_CHIPID,
                .pfn            = __phys_to_pfn(S5PC1XX_PA_CHIPID),
                .length         = SZ_16,
diff --git a/arch/arm/plat-s5pc1xx/gpio-config.c b/arch/arm/plat-s5pc1xx/gpio-config.c
new file mode 100644
index 000000000000..bba675df9c75
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/gpio-config.c
@@ -0,0 +1,62 @@
+/* linux/arch/arm/plat-s5pc1xx/gpio-config.c
+ *
+ * Copyright 2009 Samsung Electronics
+ *
+ * S5PC1XX GPIO Configuration.
+ *
+ * Based on plat-s3c64xx/gpio-config.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <mach/gpio-core.h>
+#include <plat/gpio-cfg-s5pc1xx.h>
+s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off)
+{
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        void __iomem *reg;
+        int shift = off * 2;
+        u32 drvstr;
+        if (!chip)
+                return -EINVAL;
+        reg = chip->base + 0x0C;
+        drvstr = __raw_readl(reg);
+        drvstr = 0xffff & (0x3 << shift);
+        drvstr = drvstr >> shift;
+        return (__force s5p_gpio_drvstr_t)drvstr;
+}
+EXPORT_SYMBOL(s5p_gpio_get_drvstr);
+int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off,
+                        s5p_gpio_drvstr_t drvstr)
+{
+        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+        void __iomem *reg;
+        int shift = off * 2;
+        u32 tmp;
+        if (!chip)
+                return -EINVAL;
+        reg = chip->base + 0x0C;
+        tmp = __raw_readl(reg);
+        tmp |= drvstr << shift;
+        __raw_writel(tmp, reg);
+        return 0;
+}
+EXPORT_SYMBOL(s5p_gpio_set_drvstr);
diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c
new file mode 100644
index 000000000000..facb410e7a71
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/gpiolib.c
@@ -0,0 +1,503 @@
+/*
+ * arch/arm/plat-s5pc1xx/gpiolib.c
+ *
+ *  Copyright 2009 Samsung Electronics Co
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * S5PC1XX - GPIOlib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <mach/map.h>
+#include <mach/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
+#include <plat/regs-gpio.h>
+/* S5PC100 GPIO bank summary:
+ *
+ * Bank GPIOs   Style   INT Type
+ * A0   8       4Bit    GPIO_INT0
+ * A1   5       4Bit    GPIO_INT1
+ * B    8       4Bit    GPIO_INT2
+ * C    5       4Bit    GPIO_INT3
+ * D    7       4Bit    GPIO_INT4
+ * E0   8       4Bit    GPIO_INT5
+ * E1   6       4Bit    GPIO_INT6
+ * F0   8       4Bit    GPIO_INT7
+ * F1   8       4Bit    GPIO_INT8
+ * F2   8       4Bit    GPIO_INT9
+ * F3   4       4Bit    GPIO_INT10
+ * G0   8       4Bit    GPIO_INT11
+ * G1   3       4Bit    GPIO_INT12
+ * G2   7       4Bit    GPIO_INT13
+ * G3   7       4Bit    GPIO_INT14
+ * H0   8       4Bit    WKUP_INT
+ * H1   8       4Bit    WKUP_INT
+ * H2   8       4Bit    WKUP_INT
+ * H3   8       4Bit    WKUP_INT
+ * I    8       4Bit    GPIO_INT15
+ * J0   8       4Bit    GPIO_INT16
+ * J1   5       4Bit    GPIO_INT17
+ * J2   8       4Bit    GPIO_INT18
+ * J3   8       4Bit    GPIO_INT19
+ * J4   4       4Bit    GPIO_INT20
+ * K0   8       4Bit    None
+ * K1   6       4Bit    None
+ * K2   8       4Bit    None
+ * K3   8       4Bit    None
+ * L0   8       4Bit    None
+ * L1   8       4Bit    None
+ * L2   8       4Bit    None
+ * L3   8       4Bit    None
+ */
+#define OFF_GPCON       (0x00)
+#define OFF_GPDAT       (0x04)
+#define con_4bit_shift(__off) ((__off) * 4)
+#if 1
+#define gpio_dbg(x...) do { } while (0)
+#else
+#define gpio_dbg(x...) printk(KERN_DEBUG x)
+#endif
+/* The s5pc1xx_gpiolib routines are to control the gpio banks where
+ * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
+ * following example:
+ *
+ * base + 0x00: Control register, 4 bits per gpio
+ *              gpio n: 4 bits starting at (4*n)
+ *              0000 = input, 0001 = output, others mean special-function
+ * base + 0x04: Data register, 1 bit per gpio
+ *              bit n: data bit n
+ *
+ * Note, since the data register is one bit per gpio and is at base + 0x4
+ * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
+ * the output.
+ */
+static int s5pc1xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long con;
+        con = __raw_readl(base + OFF_GPCON);
+        con &= ~(0xf << con_4bit_shift(offset));
+        __raw_writel(con, base + OFF_GPCON);
+        gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
+        return 0;
+}
+static int s5pc1xx_gpiolib_output(struct gpio_chip *chip,
+                                       unsigned offset, int value)
+{
+        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
+        void __iomem *base = ourchip->base;
+        unsigned long con;
+        unsigned long dat;
+        con = __raw_readl(base + OFF_GPCON);
+        con &= ~(0xf << con_4bit_shift(offset));
+        con |= 0x1 << con_4bit_shift(offset);
+        dat = __raw_readl(base + OFF_GPDAT);
+        if (value)
+                dat |= 1 << offset;
+        else
+                dat &= ~(1 << offset);
+        __raw_writel(dat, base + OFF_GPDAT);
+        __raw_writel(con, base + OFF_GPCON);
+        __raw_writel(dat, base + OFF_GPDAT);
+        gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
+        return 0;
+}
+static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+        return S3C_IRQ_GPIO(chip->base + offset);
+}
+static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
+{
+        int base;
+        base = chip->base - S5PC100_GPH0(0);
+        if (base == 0)
+                return IRQ_EINT(offset);
+        base = chip->base - S5PC100_GPH1(0);
+        if (base == 0)
+                return IRQ_EINT(8 + offset);
+        base = chip->base - S5PC100_GPH2(0);
+        if (base == 0)
+                return IRQ_EINT(16 + offset);
+        base = chip->base - S5PC100_GPH3(0);
+        if (base == 0)
+                return IRQ_EINT(24 + offset);
+        return -EINVAL;
+}
+static struct s3c_gpio_cfg gpio_cfg = {
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+static struct s3c_gpio_cfg gpio_cfg_eint = {
+        .cfg_eint       = 0xf,
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+static struct s3c_gpio_cfg gpio_cfg_noint = {
+        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
+        .set_pull       = s3c_gpio_setpull_updown,
+        .get_pull       = s3c_gpio_getpull_updown,
+};
+static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
+        {
+                .base   = S5PC100_GPA0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPA0(0),
+                        .ngpio  = S5PC100_GPIO_A0_NR,
+                        .label  = "GPA0",
+                },
+        }, {
+                .base   = S5PC100_GPA1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPA1(0),
+                        .ngpio  = S5PC100_GPIO_A1_NR,
+                        .label  = "GPA1",
+                },
+        }, {
+                .base   = S5PC100_GPB_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPB(0),
+                        .ngpio  = S5PC100_GPIO_B_NR,
+                        .label  = "GPB",
+                },
+        }, {
+                .base   = S5PC100_GPC_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPC(0),
+                        .ngpio  = S5PC100_GPIO_C_NR,
+                        .label  = "GPC",
+                },
+        }, {
+                .base   = S5PC100_GPD_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPD(0),
+                        .ngpio  = S5PC100_GPIO_D_NR,
+                        .label  = "GPD",
+                },
+        }, {
+                .base   = S5PC100_GPE0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPE0(0),
+                        .ngpio  = S5PC100_GPIO_E0_NR,
+                        .label  = "GPE0",
+                },
+        }, {
+                .base   = S5PC100_GPE1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPE1(0),
+                        .ngpio  = S5PC100_GPIO_E1_NR,
+                        .label  = "GPE1",
+                },
+        }, {
+                .base   = S5PC100_GPF0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPF0(0),
+                        .ngpio  = S5PC100_GPIO_F0_NR,
+                        .label  = "GPF0",
+                },
+        }, {
+                .base   = S5PC100_GPF1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPF1(0),
+                        .ngpio  = S5PC100_GPIO_F1_NR,
+                        .label  = "GPF1",
+                },
+        }, {
+                .base   = S5PC100_GPF2_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPF2(0),
+                        .ngpio  = S5PC100_GPIO_F2_NR,
+                        .label  = "GPF2",
+                },
+        }, {
+                .base   = S5PC100_GPF3_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPF3(0),
+                        .ngpio  = S5PC100_GPIO_F3_NR,
+                        .label  = "GPF3",
+                },
+        }, {
+                .base   = S5PC100_GPG0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPG0(0),
+                        .ngpio  = S5PC100_GPIO_G0_NR,
+                        .label  = "GPG0",
+                },
+        }, {
+                .base   = S5PC100_GPG1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPG1(0),
+                        .ngpio  = S5PC100_GPIO_G1_NR,
+                        .label  = "GPG1",
+                },
+        }, {
+                .base   = S5PC100_GPG2_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPG2(0),
+                        .ngpio  = S5PC100_GPIO_G2_NR,
+                        .label  = "GPG2",
+                },
+        }, {
+                .base   = S5PC100_GPG3_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPG3(0),
+                        .ngpio  = S5PC100_GPIO_G3_NR,
+                        .label  = "GPG3",
+                },
+        }, {
+                .base   = S5PC100_GPH0_BASE,
+                .config = &gpio_cfg_eint,
+                .chip   = {
+                        .base   = S5PC100_GPH0(0),
+                        .ngpio  = S5PC100_GPIO_H0_NR,
+                        .label  = "GPH0",
+                },
+        }, {
+                .base   = S5PC100_GPH1_BASE,
+                .config = &gpio_cfg_eint,
+                .chip   = {
+                        .base   = S5PC100_GPH1(0),
+                        .ngpio  = S5PC100_GPIO_H1_NR,
+                        .label  = "GPH1",
+                },
+        }, {
+                .base   = S5PC100_GPH2_BASE,
+                .config = &gpio_cfg_eint,
+                .chip   = {
+                        .base   = S5PC100_GPH2(0),
+                        .ngpio  = S5PC100_GPIO_H2_NR,
+                        .label  = "GPH2",
+                },
+        }, {
+                .base   = S5PC100_GPH3_BASE,
+                .config = &gpio_cfg_eint,
+                .chip   = {
+                        .base   = S5PC100_GPH3(0),
+                        .ngpio  = S5PC100_GPIO_H3_NR,
+                        .label  = "GPH3",
+                },
+        }, {
+                .base   = S5PC100_GPI_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPI(0),
+                        .ngpio  = S5PC100_GPIO_I_NR,
+                        .label  = "GPI",
+                },
+        }, {
+                .base   = S5PC100_GPJ0_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ0(0),
+                        .ngpio  = S5PC100_GPIO_J0_NR,
+                        .label  = "GPJ0",
+                },
+        }, {
+                .base   = S5PC100_GPJ1_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ1(0),
+                        .ngpio  = S5PC100_GPIO_J1_NR,
+                        .label  = "GPJ1",
+                },
+        }, {
+                .base   = S5PC100_GPJ2_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ2(0),
+                        .ngpio  = S5PC100_GPIO_J2_NR,
+                        .label  = "GPJ2",
+                },
+        }, {
+                .base   = S5PC100_GPJ3_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ3(0),
+                        .ngpio  = S5PC100_GPIO_J3_NR,
+                        .label  = "GPJ3",
+                },
+        }, {
+                .base   = S5PC100_GPJ4_BASE,
+                .config = &gpio_cfg,
+                .chip   = {
+                        .base   = S5PC100_GPJ4(0),
+                        .ngpio  = S5PC100_GPIO_J4_NR,
+                        .label  = "GPJ4",
+                },
+        }, {
+                .base   = S5PC100_GPK0_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPK0(0),
+                        .ngpio  = S5PC100_GPIO_K0_NR,
+                        .label  = "GPK0",
+                },
+        }, {
+                .base   = S5PC100_GPK1_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPK1(0),
+                        .ngpio  = S5PC100_GPIO_K1_NR,
+                        .label  = "GPK1",
+                },
+        }, {
+                .base   = S5PC100_GPK2_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPK2(0),
+                        .ngpio  = S5PC100_GPIO_K2_NR,
+                        .label  = "GPK2",
+                },
+        }, {
+                .base   = S5PC100_GPK3_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPK3(0),
+                        .ngpio  = S5PC100_GPIO_K3_NR,
+                        .label  = "GPK3",
+                },
+        }, {
+                .base   = S5PC100_GPL0_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL0(0),
+                        .ngpio  = S5PC100_GPIO_L0_NR,
+                        .label  = "GPL0",
+                },
+        }, {
+                .base   = S5PC100_GPL1_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL1(0),
+                        .ngpio  = S5PC100_GPIO_L1_NR,
+                        .label  = "GPL1",
+                },
+        }, {
+                .base   = S5PC100_GPL2_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL2(0),
+                        .ngpio  = S5PC100_GPIO_L2_NR,
+                        .label  = "GPL2",
+                },
+        }, {
+                .base   = S5PC100_GPL3_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL3(0),
+                        .ngpio  = S5PC100_GPIO_L3_NR,
+                        .label  = "GPL3",
+                },
+        }, {
+                .base   = S5PC100_GPL4_BASE,
+                .config = &gpio_cfg_noint,
+                .chip   = {
+                        .base   = S5PC100_GPL4(0),
+                        .ngpio  = S5PC100_GPIO_L4_NR,
+                        .label  = "GPL4",
+                },
+        },
+};
+/* FIXME move from irq-gpio.c */
+extern struct irq_chip s5pc1xx_gpioint;
+extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
+static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip)
+{
+        chip->chip.direction_input = s5pc1xx_gpiolib_input;
+        chip->chip.direction_output = s5pc1xx_gpiolib_output;
+        chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
+        /* Interrupt */
+        if (chip->config == &gpio_cfg) {
+                int i, irq;
+                chip->chip.to_irq = s5pc1xx_gpiolib_to_irq;
+                for (i = 0;  i < chip->chip.ngpio; i++) {
+                        irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
+                        set_irq_chip(irq, &s5pc1xx_gpioint);
+                        set_irq_data(irq, &chip->chip);
+                        set_irq_handler(irq, handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID);
+                }
+        } else if (chip->config == &gpio_cfg_eint)
+                chip->chip.to_irq = s5pc1xx_gpiolib_to_eint;
+}
+static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips,
+                                       int nr_chips,
+                                       void (*fn)(struct s3c_gpio_chip *))
+{
+        for (; nr_chips > 0; nr_chips--, chips++) {
+                if (fn)
+                        (fn)(chips);
+                s3c_gpiolib_add(chips);
+        }
+}
+static __init int s5pc1xx_gpiolib_init(void)
+{
+        struct s3c_gpio_chip *chips;
+        int nr_chips;
+                chips = s5pc100_gpio_chips;
+                nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
+        s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link);
+        /* Interrupt */
+        set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler);
+        return 0;
+}
+core_initcall(s5pc1xx_gpiolib_init);
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h
new file mode 100644
index 000000000000..72ad59f61efc
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h
@@ -0,0 +1,32 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg.h
+ *
+ * Copyright 2009 Samsung Electronic
+ *
+ * S5PC1XX Platform - GPIO pin configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/* This file contains the necessary definitions to get the basic gpio
+ * pin configuration done such as setting a pin to input or output or
+ * changing the pull-{up,down} configurations.
+ */
+#ifndef __GPIO_CFG_S5PC1XX_H
+#define __GPIO_CFG_S5PC1XX_H __FILE__
+typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
+#define S5P_GPIO_DRVSTR_LV1     0x00
+#define S5P_GPIO_DRVSTR_LV2     0x01
+#define S5P_GPIO_DRVSTR_LV3     0x10
+#define S5P_GPIO_DRVSTR_LV4     0x11
+extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off);
+extern int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off,
+                        s5p_gpio_drvstr_t drvstr);
+#endif /* __GPIO_CFG_S5PC1XX_H */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h
new file mode 100644
index 000000000000..33ad267e8477
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h
@@ -0,0 +1,44 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-eint.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *
+ * External Interrupt (GPH0 ~ GPH3) control register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#define S5PC1XX_WKUP_INT_CON0_7         (S5PC1XX_EINT_BASE + 0x0)
+#define S5PC1XX_WKUP_INT_CON8_15        (S5PC1XX_EINT_BASE + 0x4)
+#define S5PC1XX_WKUP_INT_CON16_23       (S5PC1XX_EINT_BASE + 0x8)
+#define S5PC1XX_WKUP_INT_CON24_31       (S5PC1XX_EINT_BASE + 0xC)
+#define S5PC1XX_WKUP_INT_CON(x)         (S5PC1XX_WKUP_INT_CON0_7 + (x * 0x4))
+#define S5PC1XX_WKUP_INT_FLTCON0_3      (S5PC1XX_EINT_BASE + 0x80)
+#define S5PC1XX_WKUP_INT_FLTCON4_7      (S5PC1XX_EINT_BASE + 0x84)
+#define S5PC1XX_WKUP_INT_FLTCON8_11     (S5PC1XX_EINT_BASE + 0x88)
+#define S5PC1XX_WKUP_INT_FLTCON12_15    (S5PC1XX_EINT_BASE + 0x8C)
+#define S5PC1XX_WKUP_INT_FLTCON16_19    (S5PC1XX_EINT_BASE + 0x90)
+#define S5PC1XX_WKUP_INT_FLTCON20_23    (S5PC1XX_EINT_BASE + 0x94)
+#define S5PC1XX_WKUP_INT_FLTCON24_27    (S5PC1XX_EINT_BASE + 0x98)
+#define S5PC1XX_WKUP_INT_FLTCON28_31    (S5PC1XX_EINT_BASE + 0x9C)
+#define S5PC1XX_WKUP_INT_FLTCON(x)      (S5PC1XX_WKUP_INT_FLTCON0_3 + (x * 0x4))
+#define S5PC1XX_WKUP_INT_MASK0_7        (S5PC1XX_EINT_BASE + 0x100)
+#define S5PC1XX_WKUP_INT_MASK8_15       (S5PC1XX_EINT_BASE + 0x104)
+#define S5PC1XX_WKUP_INT_MASK16_23      (S5PC1XX_EINT_BASE + 0x108)
+#define S5PC1XX_WKUP_INT_MASK24_31      (S5PC1XX_EINT_BASE + 0x10C)
+#define S5PC1XX_WKUP_INT_MASK(x)        (S5PC1XX_WKUP_INT_MASK0_7 + (x * 0x4))
+#define S5PC1XX_WKUP_INT_PEND0_7        (S5PC1XX_EINT_BASE + 0x140)
+#define S5PC1XX_WKUP_INT_PEND8_15       (S5PC1XX_EINT_BASE + 0x144)
+#define S5PC1XX_WKUP_INT_PEND16_23      (S5PC1XX_EINT_BASE + 0x148)
+#define S5PC1XX_WKUP_INT_PEND24_31      (S5PC1XX_EINT_BASE + 0x14C)
+#define S5PC1XX_WKUP_INT_PEND(x)        (S5PC1XX_WKUP_INT_PEND0_7 + (x * 0x4))
+#define S5PC1XX_WKUP_INT_LOWLEV         (0x00)
+#define S5PC1XX_WKUP_INT_HILEV          (0x01)
+#define S5PC1XX_WKUP_INT_FALLEDGE       (0x02)
+#define S5PC1XX_WKUP_INT_RISEEDGE       (0x03)
+#define S5PC1XX_WKUP_INT_BOTHEDGE       (0x04)
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
index f07d8c3b25d6..ef8736366f0d 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
@@ -171,12 +171,21 @@
 #define IRQ_SDMIRQ              S5PC1XX_IRQ_VIC2(30)
 #define IRQ_SDMFIQ              S5PC1XX_IRQ_VIC2(31)
+/* External interrupt */
 #define S3C_IRQ_EINT_BASE       (IRQ_SDMFIQ + 1)
-#define S3C_EINT(x)             ((x) + S3C_IRQ_EINT_BASE)
+#define S3C_EINT(x)             (S3C_IRQ_EINT_BASE + (x - 16))
-#define IRQ_EINT(x)             S3C_EINT(x)
+#define IRQ_EINT(x)             (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x))
+#define IRQ_EINT_BIT(x)         (x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0))
-#define NR_IRQS                 (IRQ_EINT(31)+1)
+/* GPIO interrupt */
+#define S3C_IRQ_GPIO_BASE       (IRQ_EINT(31) + 1)
+#define S3C_IRQ_GPIO(x)         (S3C_IRQ_GPIO_BASE + (x))
+/*
+ * Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs
+ */
+#define NR_IRQS                 (S3C_IRQ_GPIO(320) + 1)
 #endif /* __ASM_PLAT_S5PC1XX_IRQS_H */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
index 75c8390cb827..c5cc86e92d65 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
@@ -13,68 +13,69 @@
 #ifndef __PLAT_REGS_CLOCK_H
 #define __PLAT_REGS_CLOCK_H __FILE__
-#define S5PC1XX_CLKREG(x)               (S5PC1XX_VA_CLK + (x))
+#define S5PC100_CLKREG(x)               (S5PC1XX_VA_CLK + (x))
+#define S5PC100_CLKREG_OTHER(x)         (S5PC1XX_VA_CLK_OTHER + (x))
-#define S5PC1XX_APLL_LOCK               S5PC1XX_CLKREG(0x00)
-#define S5PC1XX_MPLL_LOCK               S5PC1XX_CLKREG(0x04)
+/* s5pc100 register for clock */
-#define S5PC1XX_EPLL_LOCK               S5PC1XX_CLKREG(0x08)
+#define S5PC100_APLL_LOCK               S5PC100_CLKREG(0x00)
-#define S5PC100_HPLL_LOCK               S5PC1XX_CLKREG(0x0C)
+#define S5PC100_MPLL_LOCK               S5PC100_CLKREG(0x04)
+#define S5PC100_EPLL_LOCK               S5PC100_CLKREG(0x08)
-#define S5PC1XX_APLL_CON                S5PC1XX_CLKREG(0x100)
+#define S5PC100_HPLL_LOCK               S5PC100_CLKREG(0x0C)
-#define S5PC1XX_MPLL_CON                S5PC1XX_CLKREG(0x104)
-#define S5PC1XX_EPLL_CON                S5PC1XX_CLKREG(0x108)
+#define S5PC100_APLL_CON                S5PC100_CLKREG(0x100)
-#define S5PC100_HPLL_CON                S5PC1XX_CLKREG(0x10C)
+#define S5PC100_MPLL_CON                S5PC100_CLKREG(0x104)
+#define S5PC100_EPLL_CON                S5PC100_CLKREG(0x108)
-#define S5PC1XX_CLK_SRC0                S5PC1XX_CLKREG(0x200)
+#define S5PC100_HPLL_CON                S5PC100_CLKREG(0x10C)
-#define S5PC1XX_CLK_SRC1                S5PC1XX_CLKREG(0x204)
-#define S5PC1XX_CLK_SRC2                S5PC1XX_CLKREG(0x208)
+#define S5PC100_CLKSRC0                 S5PC100_CLKREG(0x200)
-#define S5PC1XX_CLK_SRC3                S5PC1XX_CLKREG(0x20C)
+#define S5PC100_CLKSRC1                 S5PC100_CLKREG(0x204)
+#define S5PC100_CLKSRC2                 S5PC100_CLKREG(0x208)
-#define S5PC1XX_CLK_DIV0                S5PC1XX_CLKREG(0x300)
+#define S5PC100_CLKSRC3                 S5PC100_CLKREG(0x20C)
-#define S5PC1XX_CLK_DIV1                S5PC1XX_CLKREG(0x304)
-#define S5PC1XX_CLK_DIV2                S5PC1XX_CLKREG(0x308)
+#define S5PC100_CLKDIV0                 S5PC100_CLKREG(0x300)
-#define S5PC1XX_CLK_DIV3                S5PC1XX_CLKREG(0x30C)
+#define S5PC100_CLKDIV1                 S5PC100_CLKREG(0x304)
-#define S5PC1XX_CLK_DIV4                S5PC1XX_CLKREG(0x310)
+#define S5PC100_CLKDIV2                 S5PC100_CLKREG(0x308)
+#define S5PC100_CLKDIV3                 S5PC100_CLKREG(0x30C)
-#define S5PC100_CLK_OUT                 S5PC1XX_CLKREG(0x400)
+#define S5PC100_CLKDIV4                 S5PC100_CLKREG(0x310)
-#define S5PC100_CLKGATE_D00             S5PC1XX_CLKREG(0x500)
+#define S5PC100_CLK_OUT                 S5PC100_CLKREG(0x400)
-#define S5PC100_CLKGATE_D01             S5PC1XX_CLKREG(0x504)
-#define S5PC100_CLKGATE_D02             S5PC1XX_CLKREG(0x508)
+#define S5PC100_CLKGATE_D00             S5PC100_CLKREG(0x500)
+#define S5PC100_CLKGATE_D01             S5PC100_CLKREG(0x504)
-#define S5PC100_CLKGATE_D10             S5PC1XX_CLKREG(0x520)
+#define S5PC100_CLKGATE_D02             S5PC100_CLKREG(0x508)
-#define S5PC100_CLKGATE_D11             S5PC1XX_CLKREG(0x524)
-#define S5PC100_CLKGATE_D12             S5PC1XX_CLKREG(0x528)
+#define S5PC100_CLKGATE_D10             S5PC100_CLKREG(0x520)
-#define S5PC100_CLKGATE_D13             S5PC1XX_CLKREG(0x52C)
+#define S5PC100_CLKGATE_D11             S5PC100_CLKREG(0x524)
-#define S5PC100_CLKGATE_D14             S5PC1XX_CLKREG(0x530)
+#define S5PC100_CLKGATE_D12             S5PC100_CLKREG(0x528)
-#define S5PC100_CLKGATE_D15             S5PC1XX_CLKREG(0x534)
+#define S5PC100_CLKGATE_D13             S5PC100_CLKREG(0x52C)
+#define S5PC100_CLKGATE_D14             S5PC100_CLKREG(0x530)
-#define S5PC100_CLKGATE_D20             S5PC1XX_CLKREG(0x540)
+#define S5PC100_CLKGATE_D15             S5PC100_CLKREG(0x534)
-#define S5PC100_SCLKGATE0               S5PC1XX_CLKREG(0x560)
+#define S5PC100_CLKGATE_D20             S5PC100_CLKREG(0x540)
-#define S5PC100_SCLKGATE1               S5PC1XX_CLKREG(0x564)
+#define S5PC100_SCLKGATE0               S5PC100_CLKREG(0x560)
-#define S5PC100_OTHERS          S5PC1XX_CLKREG(0x8200)
+#define S5PC100_SCLKGATE1               S5PC100_CLKREG(0x564)
-#define S5PC1XX_EPLL_EN     (1<<31)
+/* EPLL_CON */
-#define S5PC1XX_EPLL_MASK   0xffffffff
+#define S5PC100_EPLL_EN                 (1<<31)
-#define S5PC1XX_EPLLVAL(_m, _p, _s)   ((_m) << 16 | ((_p) << 8) | ((_s)))
+#define S5PC100_EPLL_MASK               0xffffffff
+#define S5PC100_EPLLVAL(_m, _p, _s)     ((_m) << 16 | ((_p) << 8) | ((_s)))
 /* CLKSRC0 */
-#define S5PC1XX_CLKSRC0_APLL_MASK               (0x1<<0)
+#define S5PC100_CLKSRC0_APLL_MASK               (0x1<<0)
-#define S5PC1XX_CLKSRC0_APLL_SHIFT              (0)
+#define S5PC100_CLKSRC0_APLL_SHIFT              (0)
-#define S5PC1XX_CLKSRC0_MPLL_MASK               (0x1<<4)
+#define S5PC100_CLKSRC0_MPLL_MASK               (0x1<<4)
-#define S5PC1XX_CLKSRC0_MPLL_SHIFT              (4)
+#define S5PC100_CLKSRC0_MPLL_SHIFT              (4)
-#define S5PC1XX_CLKSRC0_EPLL_MASK               (0x1<<8)
+#define S5PC100_CLKSRC0_EPLL_MASK               (0x1<<8)
-#define S5PC1XX_CLKSRC0_EPLL_SHIFT              (8)
+#define S5PC100_CLKSRC0_EPLL_SHIFT              (8)
 #define S5PC100_CLKSRC0_HPLL_MASK               (0x1<<12)
 #define S5PC100_CLKSRC0_HPLL_SHIFT              (12)
 #define S5PC100_CLKSRC0_AMMUX_MASK              (0x1<<16)
 #define S5PC100_CLKSRC0_AMMUX_SHIFT             (16)
 #define S5PC100_CLKSRC0_HREF_MASK               (0x1<<20)
 #define S5PC100_CLKSRC0_HREF_SHIFT              (20)
-#define S5PC1XX_CLKSRC0_ONENAND_MASK    (0x1<<24)
+#define S5PC100_CLKSRC0_ONENAND_MASK    (0x1<<24)
-#define S5PC1XX_CLKSRC0_ONENAND_SHIFT   (24)
+#define S5PC100_CLKSRC0_ONENAND_SHIFT   (24)
 /* CLKSRC1 */
@@ -127,10 +128,9 @@
 #define S5PC100_CLKSRC3_SPDIF_MASK              (0x3<<24)
 #define S5PC100_CLKSRC3_SPDIF_SHIFT             (24)
 /* CLKDIV0 */
-#define S5PC1XX_CLKDIV0_APLL_MASK               (0x1<<0)
+#define S5PC100_CLKDIV0_APLL_MASK               (0x1<<0)
-#define S5PC1XX_CLKDIV0_APLL_SHIFT              (0)
+#define S5PC100_CLKDIV0_APLL_SHIFT              (0)
 #define S5PC100_CLKDIV0_ARM_MASK                (0x7<<4)
 #define S5PC100_CLKDIV0_ARM_SHIFT               (4)
 #define S5PC100_CLKDIV0_D0_MASK         (0x7<<8)
@@ -141,8 +141,8 @@
 #define S5PC100_CLKDIV0_SECSS_SHIFT             (16)
 /* CLKDIV1 */
-#define S5PC100_CLKDIV1_AM_MASK         (0x7<<0)
+#define S5PC100_CLKDIV1_APLL2_MASK              (0x7<<0)
-#define S5PC100_CLKDIV1_AM_SHIFT                (0)
+#define S5PC100_CLKDIV1_APLL2_SHIFT             (0)
 #define S5PC100_CLKDIV1_MPLL_MASK               (0x3<<4)
 #define S5PC100_CLKDIV1_MPLL_SHIFT              (4)
 #define S5PC100_CLKDIV1_MPLL2_MASK              (0x1<<8)
@@ -202,7 +202,6 @@
 #define S5PC100_CLKDIV4_AUDIO2_MASK             (0xf<<20)
 #define S5PC100_CLKDIV4_AUDIO2_SHIFT    (20)
 /* HCLKD0/PCLKD0 Clock Gate 0 Registers */
 #define S5PC100_CLKGATE_D00_INTC                (1<<0)
 #define S5PC100_CLKGATE_D00_TZIC                (1<<1)
@@ -295,8 +294,8 @@
 #define S5PC100_CLKGATE_D20_I2SD2               (1<<1)
 /* Special Clock Gate 0 Registers */
-#define S5PC1XX_CLKGATE_SCLK0_HPM               (1<<0)
+#define S5PC100_CLKGATE_SCLK0_HPM               (1<<0)
-#define S5PC1XX_CLKGATE_SCLK0_PWI               (1<<1)
+#define S5PC100_CLKGATE_SCLK0_PWI               (1<<1)
 #define S5PC100_CLKGATE_SCLK0_ONENAND   (1<<2)
 #define S5PC100_CLKGATE_SCLK0_UART              (1<<3)
 #define S5PC100_CLKGATE_SCLK0_SPI0              (1<<4)
@@ -329,89 +328,28 @@
 #define S5PC100_CLKGATE_SCLK1_SPDIF             (1<<11)
 #define S5PC100_CLKGATE_SCLK1_CAM               (1<<12)
-/* register for power management */
+#define S5PC100_SWRESET         S5PC100_CLKREG_OTHER(0x000)
-#define S5PC100_PWR_CFG                 S5PC1XX_CLKREG(0x8000)
+#define S5PC100_OND_SWRESET     S5PC100_CLKREG_OTHER(0x008)
-#define S5PC100_EINT_WAKEUP_MASK        S5PC1XX_CLKREG(0x8004)
+#define S5PC100_GEN_CTRL        S5PC100_CLKREG_OTHER(0x100)
-#define S5PC100_NORMAL_CFG              S5PC1XX_CLKREG(0x8010)
+#define S5PC100_GEN_STATUS      S5PC100_CLKREG_OTHER(0x104)
-#define S5PC100_STOP_CFG                S5PC1XX_CLKREG(0x8014)
+#define S5PC100_MEM_SYS_CFG     S5PC100_CLKREG_OTHER(0x200)
-#define S5PC100_SLEEP_CFG               S5PC1XX_CLKREG(0x8018)
+#define S5PC100_CAM_MUX_SEL     S5PC100_CLKREG_OTHER(0x300)
-#define S5PC100_STOP_MEM_CFG    S5PC1XX_CLKREG(0x801C)
+#define S5PC100_MIXER_OUT_SEL   S5PC100_CLKREG_OTHER(0x304)
-#define S5PC100_OSC_FREQ                S5PC1XX_CLKREG(0x8100)
+#define S5PC100_LPMP_MODE_SEL   S5PC100_CLKREG_OTHER(0x308)
-#define S5PC100_OSC_STABLE              S5PC1XX_CLKREG(0x8104)
+#define S5PC100_MIPI_PHY_CON0   S5PC100_CLKREG_OTHER(0x400)
-#define S5PC100_PWR_STABLE              S5PC1XX_CLKREG(0x8108)
+#define S5PC100_MIPI_PHY_CON1   S5PC100_CLKREG_OTHER(0x414)
-#define S5PC100_MTC_STABLE              S5PC1XX_CLKREG(0x8110)
+#define S5PC100_HDMI_PHY_CON0   S5PC100_CLKREG_OTHER(0x420)
-#define S5PC100_CLAMP_STABLE    S5PC1XX_CLKREG(0x8114)
-#define S5PC100_OTHERS          S5PC1XX_CLKREG(0x8200)
+#define S5PC100_SWRESET_RESETVAL        0xc100
-#define S5PC100_RST_STAT                S5PC1XX_CLKREG(0x8300)
-#define S5PC100_WAKEUP_STAT     S5PC1XX_CLKREG(0x8304)
-#define S5PC100_BLK_PWR_STAT    S5PC1XX_CLKREG(0x8308)
-#define S5PC100_INFORM0                 S5PC1XX_CLKREG(0x8400)
-#define S5PC100_INFORM1                 S5PC1XX_CLKREG(0x8404)
-#define S5PC100_INFORM2                 S5PC1XX_CLKREG(0x8408)
-#define S5PC100_INFORM3                 S5PC1XX_CLKREG(0x840C)
-#define S5PC100_INFORM4                 S5PC1XX_CLKREG(0x8410)
-#define S5PC100_INFORM5                 S5PC1XX_CLKREG(0x8414)
-#define S5PC100_INFORM6                 S5PC1XX_CLKREG(0x8418)
-#define S5PC100_INFORM7                 S5PC1XX_CLKREG(0x841C)
-#define S5PC100_DCGIDX_MAP0     S5PC1XX_CLKREG(0x8500)
-#define S5PC100_DCGIDX_MAP1     S5PC1XX_CLKREG(0x8504)
-#define S5PC100_DCGIDX_MAP2     S5PC1XX_CLKREG(0x8508)
-#define S5PC100_DCGPERF_MAP0    S5PC1XX_CLKREG(0x850C)
-#define S5PC100_DCGPERF_MAP1    S5PC1XX_CLKREG(0x8510)
-#define S5PC100_DVCIDX_MAP              S5PC1XX_CLKREG(0x8514)
-#define S5PC100_FREQ_CPU                S5PC1XX_CLKREG(0x8518)
-#define S5PC100_FREQ_DPM                S5PC1XX_CLKREG(0x851C)
-#define S5PC100_DVSEMCLK_EN     S5PC1XX_CLKREG(0x8520)
-#define S5PC100_APLL_CON_L8     S5PC1XX_CLKREG(0x8600)
-#define S5PC100_APLL_CON_L7     S5PC1XX_CLKREG(0x8604)
-#define S5PC100_APLL_CON_L6     S5PC1XX_CLKREG(0x8608)
-#define S5PC100_APLL_CON_L5     S5PC1XX_CLKREG(0x860C)
-#define S5PC100_APLL_CON_L4     S5PC1XX_CLKREG(0x8610)
-#define S5PC100_APLL_CON_L3     S5PC1XX_CLKREG(0x8614)
-#define S5PC100_APLL_CON_L2     S5PC1XX_CLKREG(0x8618)
-#define S5PC100_APLL_CON_L1     S5PC1XX_CLKREG(0x861C)
-#define S5PC100_IEM_CONTROL     S5PC1XX_CLKREG(0x8620)
-#define S5PC100_CLKDIV_IEM_L8   S5PC1XX_CLKREG(0x8700)
-#define S5PC100_CLKDIV_IEM_L7   S5PC1XX_CLKREG(0x8704)
-#define S5PC100_CLKDIV_IEM_L6   S5PC1XX_CLKREG(0x8708)
-#define S5PC100_CLKDIV_IEM_L5   S5PC1XX_CLKREG(0x870C)
-#define S5PC100_CLKDIV_IEM_L4   S5PC1XX_CLKREG(0x8710)
-#define S5PC100_CLKDIV_IEM_L3   S5PC1XX_CLKREG(0x8714)
-#define S5PC100_CLKDIV_IEM_L2   S5PC1XX_CLKREG(0x8718)
-#define S5PC100_CLKDIV_IEM_L1   S5PC1XX_CLKREG(0x871C)
-#define S5PC100_IEM_HPMCLK_DIV  S5PC1XX_CLKREG(0x8724)
-#define S5PC100_SWRESET         S5PC1XX_CLKREG(0x100000)
-#define S5PC100_OND_SWRESET             S5PC1XX_CLKREG(0x100008)
-#define S5PC100_GEN_CTRL                S5PC1XX_CLKREG(0x100100)
-#define S5PC100_GEN_STATUS              S5PC1XX_CLKREG(0x100104)
-#define S5PC100_MEM_SYS_CFG             S5PC1XX_CLKREG(0x100200)
-#define S5PC100_CAM_MUX_SEL             S5PC1XX_CLKREG(0x100300)
-#define S5PC100_MIXER_OUT_SEL   S5PC1XX_CLKREG(0x100304)
-#define S5PC100_LPMP_MODE_SEL   S5PC1XX_CLKREG(0x100308)
-#define S5PC100_MIPI_PHY_CON0   S5PC1XX_CLKREG(0x100400)
-#define S5PC100_MIPI_PHY_CON1   S5PC1XX_CLKREG(0x100414)
-#define S5PC100_HDMI_PHY_CON0   S5PC1XX_CLKREG(0x100420)
-#define S5PC100_CFG_WFI_CLEAN   (~(3<<5))
-#define S5PC100_CFG_WFI_IDLE    (1<<5)
-#define S5PC100_CFG_WFI_STOP    (2<<5)
-#define S5PC100_CFG_WFI_SLEEP   (3<<5)
 #define S5PC100_OTHER_SYS_INT   24
 #define S5PC100_OTHER_STA_TYPE  23
 #define STA_TYPE_EXPON          0
 #define STA_TYPE_SFR            1
-#define S5PC100_PWR_STA_EXP_SCALE       0
-#define S5PC100_PWR_STA_CNT             4
-#define S5PC100_PWR_STABLE_COUNT        85500
 #define S5PC100_SLEEP_CFG_OSC_EN        0
 /* OTHERS Resgister */
-#define S5PC100_OTHERS_USB_SIG_MASK     (1 << 16)
+#define S5PC100_OTHERS_USB_SIG_MASK     (1 << 16)
 #define S5PC100_OTHERS_MIPI_DPHY_EN             (1 << 28)
 /* MIPI D-PHY Control Register 0 */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h b/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
new file mode 100644
index 000000000000..43c7bc8bf784
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
@@ -0,0 +1,70 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX - GPIO register definitions
+ */
+#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H
+#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__
+#include <mach/map.h>
+/* S5PC100 */
+#define S5PC100_GPIO_BASE       S5PC1XX_VA_GPIO
+#define S5PC100_GPA0_BASE       (S5PC100_GPIO_BASE + 0x0000)
+#define S5PC100_GPA1_BASE       (S5PC100_GPIO_BASE + 0x0020)
+#define S5PC100_GPB_BASE        (S5PC100_GPIO_BASE + 0x0040)
+#define S5PC100_GPC_BASE        (S5PC100_GPIO_BASE + 0x0060)
+#define S5PC100_GPD_BASE        (S5PC100_GPIO_BASE + 0x0080)
+#define S5PC100_GPE0_BASE       (S5PC100_GPIO_BASE + 0x00A0)
+#define S5PC100_GPE1_BASE       (S5PC100_GPIO_BASE + 0x00C0)
+#define S5PC100_GPF0_BASE       (S5PC100_GPIO_BASE + 0x00E0)
+#define S5PC100_GPF1_BASE       (S5PC100_GPIO_BASE + 0x0100)
+#define S5PC100_GPF2_BASE       (S5PC100_GPIO_BASE + 0x0120)
+#define S5PC100_GPF3_BASE       (S5PC100_GPIO_BASE + 0x0140)
+#define S5PC100_GPG0_BASE       (S5PC100_GPIO_BASE + 0x0160)
+#define S5PC100_GPG1_BASE       (S5PC100_GPIO_BASE + 0x0180)
+#define S5PC100_GPG2_BASE       (S5PC100_GPIO_BASE + 0x01A0)
+#define S5PC100_GPG3_BASE       (S5PC100_GPIO_BASE + 0x01C0)
+#define S5PC100_GPH0_BASE       (S5PC100_GPIO_BASE + 0x0C00)
+#define S5PC100_GPH1_BASE       (S5PC100_GPIO_BASE + 0x0C20)
+#define S5PC100_GPH2_BASE       (S5PC100_GPIO_BASE + 0x0C40)
+#define S5PC100_GPH3_BASE       (S5PC100_GPIO_BASE + 0x0C60)
+#define S5PC100_GPI_BASE        (S5PC100_GPIO_BASE + 0x01E0)
+#define S5PC100_GPJ0_BASE       (S5PC100_GPIO_BASE + 0x0200)
+#define S5PC100_GPJ1_BASE       (S5PC100_GPIO_BASE + 0x0220)
+#define S5PC100_GPJ2_BASE       (S5PC100_GPIO_BASE + 0x0240)
+#define S5PC100_GPJ3_BASE       (S5PC100_GPIO_BASE + 0x0260)
+#define S5PC100_GPJ4_BASE       (S5PC100_GPIO_BASE + 0x0280)
+#define S5PC100_GPK0_BASE       (S5PC100_GPIO_BASE + 0x02A0)
+#define S5PC100_GPK1_BASE       (S5PC100_GPIO_BASE + 0x02C0)
+#define S5PC100_GPK2_BASE       (S5PC100_GPIO_BASE + 0x02E0)
+#define S5PC100_GPK3_BASE       (S5PC100_GPIO_BASE + 0x0300)
+#define S5PC100_GPL0_BASE       (S5PC100_GPIO_BASE + 0x0320)
+#define S5PC100_GPL1_BASE       (S5PC100_GPIO_BASE + 0x0340)
+#define S5PC100_GPL2_BASE       (S5PC100_GPIO_BASE + 0x0360)
+#define S5PC100_GPL3_BASE       (S5PC100_GPIO_BASE + 0x0380)
+#define S5PC100_GPL4_BASE       (S5PC100_GPIO_BASE + 0x03A0)
+#define S5PC100_EINT_BASE       (S5PC100_GPIO_BASE + 0x0E00)
+#define S5PC100_UHOST           (S5PC100_GPIO_BASE + 0x0B68)
+#define S5PC100_PDNEN           (S5PC100_GPIO_BASE + 0x0F80)
+/* PDNEN */
+#define S5PC100_PDNEN_CFG_PDNEN (1 << 1)
+#define S5PC100_PDNEN_CFG_AUTO  (0 << 1)
+#define S5PC100_PDNEN_POWERDOWN (1 << 0)
+#define S5PC100_PDNEN_NORMAL    (0 << 0)
+/* Common part */
+/* External interrupt base is same at both s5pc100 and s5pc110 */
+#define S5PC1XX_EINT_BASE       (S5PC100_EINT_BASE)
+#define S5PC100_GPx_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
+#define S5PC100_GPx_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
+#define S5PC100_GPx_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
+#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
new file mode 100644
index 000000000000..02ffa491b53a
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
@@ -0,0 +1,84 @@
+/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Jongse Won <jongse.won@samsung.com>
+ *
+ * S5PC1XX clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARM_REGS_PWR
+#define __ASM_ARM_REGS_PWR __FILE__
+#define S5PC1XX_PWRREG(x)                       (S5PC1XX_VA_PWR + (x))
+/* s5pc100 (0xE0108000) register for power management */
+#define S5PC100_PWR_CFG                         S5PC1XX_PWRREG(0x0)
+#define S5PC100_EINT_WAKEUP_MASK                S5PC1XX_PWRREG(0x4)
+#define S5PC100_NORMAL_CFG                      S5PC1XX_PWRREG(0x10)
+#define S5PC100_STOP_CFG                        S5PC1XX_PWRREG(0x14)
+#define S5PC100_SLEEP_CFG                       S5PC1XX_PWRREG(0x18)
+#define S5PC100_STOP_MEM_CFG                    S5PC1XX_PWRREG(0x1C)
+#define S5PC100_OSC_FREQ                        S5PC1XX_PWRREG(0x100)
+#define S5PC100_OSC_STABLE                      S5PC1XX_PWRREG(0x104)
+#define S5PC100_PWR_STABLE                      S5PC1XX_PWRREG(0x108)
+#define S5PC100_MTC_STABLE                      S5PC1XX_PWRREG(0x110)
+#define S5PC100_CLAMP_STABLE                    S5PC1XX_PWRREG(0x114)
+#define S5PC100_OTHERS                          S5PC1XX_PWRREG(0x200)
+#define S5PC100_RST_STAT                        S5PC1XX_PWRREG(0x300)
+#define S5PC100_WAKEUP_STAT                     S5PC1XX_PWRREG(0x304)
+#define S5PC100_BLK_PWR_STAT                    S5PC1XX_PWRREG(0x308)
+#define S5PC100_INFORM0                         S5PC1XX_PWRREG(0x400)
+#define S5PC100_INFORM1                         S5PC1XX_PWRREG(0x404)
+#define S5PC100_INFORM2                         S5PC1XX_PWRREG(0x408)
+#define S5PC100_INFORM3                         S5PC1XX_PWRREG(0x40C)
+#define S5PC100_INFORM4                         S5PC1XX_PWRREG(0x410)
+#define S5PC100_INFORM5                         S5PC1XX_PWRREG(0x414)
+#define S5PC100_INFORM6                         S5PC1XX_PWRREG(0x418)
+#define S5PC100_INFORM7                         S5PC1XX_PWRREG(0x41C)
+#define S5PC100_DCGIDX_MAP0                     S5PC1XX_PWRREG(0x500)
+#define S5PC100_DCGIDX_MAP1                     S5PC1XX_PWRREG(0x504)
+#define S5PC100_DCGIDX_MAP2                     S5PC1XX_PWRREG(0x508)
+#define S5PC100_DCGPERF_MAP0                    S5PC1XX_PWRREG(0x50C)
+#define S5PC100_DCGPERF_MAP1                    S5PC1XX_PWRREG(0x510)
+#define S5PC100_DVCIDX_MAP                      S5PC1XX_PWRREG(0x514)
+#define S5PC100_FREQ_CPU                        S5PC1XX_PWRREG(0x518)
+#define S5PC100_FREQ_DPM                        S5PC1XX_PWRREG(0x51C)
+#define S5PC100_DVSEMCLK_EN                     S5PC1XX_PWRREG(0x520)
+#define S5PC100_APLL_CON_L8                     S5PC1XX_PWRREG(0x600)
+#define S5PC100_APLL_CON_L7                     S5PC1XX_PWRREG(0x604)
+#define S5PC100_APLL_CON_L6                     S5PC1XX_PWRREG(0x608)
+#define S5PC100_APLL_CON_L5                     S5PC1XX_PWRREG(0x60C)
+#define S5PC100_APLL_CON_L4                     S5PC1XX_PWRREG(0x610)
+#define S5PC100_APLL_CON_L3                     S5PC1XX_PWRREG(0x614)
+#define S5PC100_APLL_CON_L2                     S5PC1XX_PWRREG(0x618)
+#define S5PC100_APLL_CON_L1                     S5PC1XX_PWRREG(0x61C)
+#define S5PC100_IEM_CONTROL                     S5PC1XX_PWRREG(0x620)
+#define S5PC100_CLKDIV_IEM_L8                   S5PC1XX_PWRREG(0x700)
+#define S5PC100_CLKDIV_IEM_L7                   S5PC1XX_PWRREG(0x704)
+#define S5PC100_CLKDIV_IEM_L6                   S5PC1XX_PWRREG(0x708)
+#define S5PC100_CLKDIV_IEM_L5                   S5PC1XX_PWRREG(0x70C)
+#define S5PC100_CLKDIV_IEM_L4                   S5PC1XX_PWRREG(0x710)
+#define S5PC100_CLKDIV_IEM_L3                   S5PC1XX_PWRREG(0x714)
+#define S5PC100_CLKDIV_IEM_L2                   S5PC1XX_PWRREG(0x718)
+#define S5PC100_CLKDIV_IEM_L1                   S5PC1XX_PWRREG(0x71C)
+#define S5PC100_IEM_HPMCLK_DIV                  S5PC1XX_PWRREG(0x724)
+/* PWR_CFG */
+#define S5PC100_PWRCFG_CFG_DEEP_IDLE            (1 << 31)
+#define S5PC100_PWRCFG_CFG_WFI_MASK             (3 << 5)
+#define S5PC100_PWRCFG_CFG_WFI_IDLE             (0 << 5)
+#define S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE        (1 << 5)
+#define S5PC100_PWRCFG_CFG_WFI_STOP             (2 << 5)
+#define S5PC100_PWRCFG_CFG_WFI_SLEEP            (3 << 5)
+/* SLEEP_CFG */
+#define S5PC100_SLEEP_OSC_EN_SLEEP              (1 << 0)
+/* OTHERS */
+#define S5PC100_PMU_INT_DISABLE                 (1 << 24)
+#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
index 45e275131665..2531f34a56f3 100644
--- a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
@@ -35,10 +35,9 @@ extern struct clk clk_hpll;
 extern struct clk clk_hd0;
 extern struct clk clk_pd0;
 extern struct clk clk_54m;
-extern struct clk clk_dout_mpll2;
 extern void s5pc1xx_register_clocks(void);
-extern int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable);
+extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable);
-extern int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable);
+extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable);
 /* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */
 extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
diff --git a/arch/arm/plat-s5pc1xx/irq-eint.c b/arch/arm/plat-s5pc1xx/irq-eint.c
new file mode 100644
index 000000000000..373122f57d56
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/irq-eint.c
@@ -0,0 +1,281 @@
+/*
+ * linux/arch/arm/plat-s5pc1xx/irq-eint.c
+ *
+ *  Copyright 2009 Samsung Electronics Co.
+ *  Byungho Min <bhmin@samsung.com>
+ *  Kyungin Park <kyungmin.park@samsung.com>
+ *
+ * Based on plat-s3c64xx/irq-eint.c
+ *
+ * S5PC1XX - Interrupt handling for IRQ_EINT(x)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/pm.h>
+#include <linux/gpio.h>
+#include <asm/hardware/vic.h>
+#include <mach/map.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-ext.h>
+#include <plat/pm.h>
+#include <plat/regs-gpio.h>
+#include <plat/regs-irqtype.h>
+/*
+ * bank is a group of external interrupt
+ * bank0 means EINT0 ... EINT7
+ * bank1 means EINT8 ... EINT15
+ * bank2 means EINT16 ... EINT23
+ * bank3 means EINT24 ... EINT31
+ */
+static inline int s3c_get_eint(unsigned int irq)
+{
+        int real;
+        if (irq < IRQ_EINT16_31)
+                real = (irq - IRQ_EINT0);
+        else
+                real = (irq - S3C_IRQ_EINT_BASE) + IRQ_EINT16_31 - IRQ_EINT0;
+        return real;
+}
+static inline int s3c_get_bank(unsigned int irq)
+{
+        return s3c_get_eint(irq) >> 3;
+}
+static inline int s3c_eint_to_bit(unsigned int irq)
+{
+        int real, bit;
+        real = s3c_get_eint(irq);
+        bit = 1 << (real & (8 - 1));
+        return bit;
+}
+static inline void s3c_irq_eint_mask(unsigned int irq)
+{
+        u32 mask;
+        u32 bank = s3c_get_bank(irq);
+        mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
+        mask |= s3c_eint_to_bit(irq);
+        __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
+}
+static void s3c_irq_eint_unmask(unsigned int irq)
+{
+        u32 mask;
+        u32 bank = s3c_get_bank(irq);
+        mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
+        mask &= ~(s3c_eint_to_bit(irq));
+        __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
+}
+static inline void s3c_irq_eint_ack(unsigned int irq)
+{
+        u32 bank = s3c_get_bank(irq);
+        __raw_writel(s3c_eint_to_bit(irq), S5PC1XX_WKUP_INT_PEND(bank));
+}
+static void s3c_irq_eint_maskack(unsigned int irq)
+{
+        /* compiler should in-line these */
+        s3c_irq_eint_mask(irq);
+        s3c_irq_eint_ack(irq);
+}
+static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
+{
+        u32 bank = s3c_get_bank(irq);
+        int real = s3c_get_eint(irq);
+        int gpio, shift, sfn;
+        u32 ctrl, con = 0;
+        switch (type) {
+        case IRQ_TYPE_NONE:
+                printk(KERN_WARNING "No edge setting!\n");
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+                con = S5PC1XX_WKUP_INT_RISEEDGE;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                con = S5PC1XX_WKUP_INT_FALLEDGE;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                con = S5PC1XX_WKUP_INT_BOTHEDGE;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                con = S5PC1XX_WKUP_INT_LOWLEV;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                con = S5PC1XX_WKUP_INT_HILEV;
+                break;
+        default:
+                printk(KERN_ERR "No such irq type %d", type);
+                return -EINVAL;
+        }
+        gpio = real & (8 - 1);
+        shift = gpio << 2;
+        ctrl = __raw_readl(S5PC1XX_WKUP_INT_CON(bank));
+        ctrl &= ~(0x7 << shift);
+        ctrl |= con << shift;
+        __raw_writel(ctrl, S5PC1XX_WKUP_INT_CON(bank));
+        switch (real) {
+        case 0 ... 7:
+                        gpio = S5PC100_GPH0(gpio);
+                break;
+        case 8 ... 15:
+                        gpio = S5PC100_GPH1(gpio);
+                break;
+        case 16 ... 23:
+                        gpio = S5PC100_GPH2(gpio);
+                break;
+        case 24 ... 31:
+                        gpio = S5PC100_GPH3(gpio);
+                break;
+        default:
+                return -EINVAL;
+        }
+        sfn = S3C_GPIO_SFN(0x2);
+        s3c_gpio_cfgpin(gpio, sfn);
+        return 0;
+}
+static struct irq_chip s3c_irq_eint = {
+        .name           = "EINT",
+        .mask           = s3c_irq_eint_mask,
+        .unmask         = s3c_irq_eint_unmask,
+        .mask_ack       = s3c_irq_eint_maskack,
+        .ack            = s3c_irq_eint_ack,
+        .set_type       = s3c_irq_eint_set_type,
+        .set_wake       = s3c_irqext_wake,
+};
+/* s3c_irq_demux_eint
+ *
+ * This function demuxes the IRQ from external interrupts,
+ * from IRQ_EINT(16) to IRQ_EINT(31). It is designed to be inlined into
+ * the specific handlers s3c_irq_demux_eintX_Y.
+ */
+static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
+{
+        u32 status = __raw_readl(S5PC1XX_WKUP_INT_PEND((start >> 3)));
+        u32 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK((start >> 3)));
+        unsigned int irq;
+        status &= ~mask;
+        status &= (1 << (end - start + 1)) - 1;
+        for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
+                if (status & 1)
+                        generic_handle_irq(irq);
+                status >>= 1;
+        }
+}
+static void s3c_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_eint(16, 23);
+        s3c_irq_demux_eint(24, 31);
+}
+/*
+ * Handle EINT0 ... EINT15 at VIC directly
+ */
+static void s3c_irq_vic_eint_mask(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        unsigned int real;
+        s3c_irq_eint_mask(irq);
+        real = s3c_get_eint(irq);
+        writel(1 << real, base + VIC_INT_ENABLE_CLEAR);
+}
+static void s3c_irq_vic_eint_unmask(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        unsigned int real;
+        s3c_irq_eint_unmask(irq);
+        real = s3c_get_eint(irq);
+        writel(1 << real, base + VIC_INT_ENABLE);
+}
+static inline void s3c_irq_vic_eint_ack(unsigned int irq)
+{
+        u32 bit;
+        u32 bank = s3c_get_bank(irq);
+        bit = s3c_eint_to_bit(irq);
+        __raw_writel(bit, S5PC1XX_WKUP_INT_PEND(bank));
+}
+static void s3c_irq_vic_eint_maskack(unsigned int irq)
+{
+        /* compiler should in-line these */
+        s3c_irq_vic_eint_mask(irq);
+        s3c_irq_vic_eint_ack(irq);
+}
+static struct irq_chip s3c_irq_vic_eint = {
+        .name           = "EINT",
+        .mask           = s3c_irq_vic_eint_mask,
+        .unmask         = s3c_irq_vic_eint_unmask,
+        .mask_ack       = s3c_irq_vic_eint_maskack,
+        .ack            = s3c_irq_vic_eint_ack,
+        .set_type       = s3c_irq_eint_set_type,
+        .set_wake       = s3c_irqext_wake,
+};
+static int __init s5pc1xx_init_irq_eint(void)
+{
+        int irq;
+        for (irq = IRQ_EINT0; irq <= IRQ_EINT15; irq++) {
+                set_irq_chip(irq, &s3c_irq_vic_eint);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
+                set_irq_chip(irq, &s3c_irq_eint);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        set_irq_chained_handler(IRQ_EINT16_31, s3c_irq_demux_eint16_31);
+        return 0;
+}
+arch_initcall(s5pc1xx_init_irq_eint);
diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/plat-s5pc1xx/irq-gpio.c
new file mode 100644
index 000000000000..fecca7a679b0
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/irq-gpio.c
@@ -0,0 +1,266 @@
+/*
+ * arch/arm/plat-s5pc1xx/irq-gpio.c
+ *
+ * Copyright (C) 2009 Samsung Electronics
+ *
+ * S5PC1XX - Interrupt handling for IRQ_GPIO${group}(x)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <mach/map.h>
+#include <plat/gpio-cfg.h>
+#define S5PC1XX_GPIOREG(x)              (S5PC1XX_VA_GPIO + (x))
+#define CON_OFFSET                      0x700
+#define MASK_OFFSET                     0x900
+#define PEND_OFFSET                     0xA00
+#define CON_OFFSET_2                    0xE00
+#define MASK_OFFSET_2                   0xF00
+#define PEND_OFFSET_2                   0xF40
+#define GPIOINT_LEVEL_LOW               0x0
+#define GPIOINT_LEVEL_HIGH              0x1
+#define GPIOINT_EDGE_FALLING            0x2
+#define GPIOINT_EDGE_RISING             0x3
+#define GPIOINT_EDGE_BOTH               0x4
+static int group_to_con_offset(int group)
+{
+        return group << 2;
+}
+static int group_to_mask_offset(int group)
+{
+        return group << 2;
+}
+static int group_to_pend_offset(int group)
+{
+        return group << 2;
+}
+static int s5pc1xx_get_start(unsigned int group)
+{
+        switch (group) {
+        case 0: return S5PC100_GPIO_A0_START;
+        case 1: return S5PC100_GPIO_A1_START;
+        case 2: return S5PC100_GPIO_B_START;
+        case 3: return S5PC100_GPIO_C_START;
+        case 4: return S5PC100_GPIO_D_START;
+        case 5: return S5PC100_GPIO_E0_START;
+        case 6: return S5PC100_GPIO_E1_START;
+        case 7: return S5PC100_GPIO_F0_START;
+        case 8: return S5PC100_GPIO_F1_START;
+        case 9: return S5PC100_GPIO_F2_START;
+        case 10: return S5PC100_GPIO_F3_START;
+        case 11: return S5PC100_GPIO_G0_START;
+        case 12: return S5PC100_GPIO_G1_START;
+        case 13: return S5PC100_GPIO_G2_START;
+        case 14: return S5PC100_GPIO_G3_START;
+        case 15: return S5PC100_GPIO_I_START;
+        case 16: return S5PC100_GPIO_J0_START;
+        case 17: return S5PC100_GPIO_J1_START;
+        case 18: return S5PC100_GPIO_J2_START;
+        case 19: return S5PC100_GPIO_J3_START;
+        case 20: return S5PC100_GPIO_J4_START;
+        default:
+                BUG();
+        }
+        return -EINVAL;
+}
+static int s5pc1xx_get_group(unsigned int irq)
+{
+        irq -= S3C_IRQ_GPIO(0);
+        switch (irq) {
+        case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
+                return 0;
+        case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
+                return 1;
+        case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
+                return 2;
+        case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
+                return 3;
+        case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
+                return 4;
+        case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
+                return 5;
+        case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
+                return 6;
+        case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
+                return 7;
+        case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
+                return 8;
+        case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
+                return 9;
+        case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
+                return 10;
+        case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
+                return 11;
+        case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
+                return 12;
+        case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
+                return 13;
+        case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
+                return 14;
+        case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
+                return 15;
+        case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
+                return 16;
+        case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
+                return 17;
+        case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
+                return 18;
+        case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
+                return 19;
+        case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
+                return 20;
+        default:
+                BUG();
+        }
+        return -EINVAL;
+}
+static int s5pc1xx_get_offset(unsigned int irq)
+{
+        struct gpio_chip *chip = get_irq_data(irq);
+        return irq - S3C_IRQ_GPIO(chip->base);
+}
+static void s5pc1xx_gpioint_ack(unsigned int irq)
+{
+        int group, offset, pend_offset;
+        unsigned int value;
+        group = s5pc1xx_get_group(irq);
+        offset = s5pc1xx_get_offset(irq);
+        pend_offset = group_to_pend_offset(group);
+        value = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
+        value |= 1 << offset;
+        __raw_writel(value, S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
+}
+static void s5pc1xx_gpioint_mask(unsigned int irq)
+{
+        int group, offset, mask_offset;
+        unsigned int value;
+        group = s5pc1xx_get_group(irq);
+        offset = s5pc1xx_get_offset(irq);
+        mask_offset = group_to_mask_offset(group);
+        value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+        value |= 1 << offset;
+        __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+}
+static void s5pc1xx_gpioint_unmask(unsigned int irq)
+{
+        int group, offset, mask_offset;
+        unsigned int value;
+        group = s5pc1xx_get_group(irq);
+        offset = s5pc1xx_get_offset(irq);
+        mask_offset = group_to_mask_offset(group);
+        value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+        value &= ~(1 << offset);
+        __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+}
+static void s5pc1xx_gpioint_mask_ack(unsigned int irq)
+{
+        s5pc1xx_gpioint_mask(irq);
+        s5pc1xx_gpioint_ack(irq);
+}
+static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type)
+{
+        int group, offset, con_offset;
+        unsigned int value;
+        group = s5pc1xx_get_group(irq);
+        offset = s5pc1xx_get_offset(irq);
+        con_offset = group_to_con_offset(group);
+        switch (type) {
+        case IRQ_TYPE_NONE:
+                printk(KERN_WARNING "No irq type\n");
+                return -EINVAL;
+        case IRQ_TYPE_EDGE_RISING:
+                type = GPIOINT_EDGE_RISING;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                type = GPIOINT_EDGE_FALLING;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                type = GPIOINT_EDGE_BOTH;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                type = GPIOINT_LEVEL_HIGH;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                type = GPIOINT_LEVEL_LOW;
+                break;
+        default:
+                BUG();
+        }
+        value = __raw_readl(S5PC1XX_GPIOREG(CON_OFFSET) + con_offset);
+        value &= ~(0xf << (offset * 0x4));
+        value |= (type << (offset * 0x4));
+        __raw_writel(value, S5PC1XX_GPIOREG(CON_OFFSET) + con_offset);
+        return 0;
+}
+struct irq_chip s5pc1xx_gpioint = {
+        .name           = "GPIO",
+        .ack            = s5pc1xx_gpioint_ack,
+        .mask           = s5pc1xx_gpioint_mask,
+        .mask_ack       = s5pc1xx_gpioint_mask_ack,
+        .unmask         = s5pc1xx_gpioint_unmask,
+        .set_type       = s5pc1xx_gpioint_set_type,
+};
+void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
+{
+        int group, offset, pend_offset, mask_offset;
+        int real_irq, group_end;
+        unsigned int pend, mask;
+        group_end = 21;
+        for (group = 0; group < group_end; group++) {
+                pend_offset = group_to_pend_offset(group);
+                pend = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset);
+                if (!pend)
+                        continue;
+                mask_offset = group_to_mask_offset(group);
+                mask = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset);
+                pend &= ~mask;
+                for (offset = 0; offset < 8; offset++) {
+                        if (pend & (1 << offset)) {
+                                real_irq = s5pc1xx_get_start(group) + offset;
+                                generic_handle_irq(S3C_IRQ_GPIO(real_irq));
+                        }
+                }
+        }
+}
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c
index 80d6dd942cb8..e44fd04ef333 100644
--- a/arch/arm/plat-s5pc1xx/irq.c
+++ b/arch/arm/plat-s5pc1xx/irq.c
@@ -79,7 +79,7 @@ static void s3c_irq_timer_ack(unsigned int irq)
 {
        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
-        reg &= 0x1f;
+        reg &= 0x1f;  /* mask out pending interrupts */
        reg |= (1 << 5) << (irq - IRQ_TIMER0);
        __raw_writel(reg, S3C64XX_TINT_CSTAT);
 }
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
index 6b24035172fa..b436d44510c8 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
@@ -49,6 +49,7 @@ static struct clk clk_ext_xtal_mux = {
 #define clk_fin_hpll clk_ext_xtal_mux
 #define clk_fout_mpll   clk_mpll
+#define clk_vclk_54m    clk_54m
 struct clk_sources {
        unsigned int    nr_sources;
@@ -67,746 +68,327 @@ struct clksrc_clk {
        void __iomem            *reg_source;
 };
-static int clk_default_setrate(struct clk *clk, unsigned long rate)
+/* APLL */
-{
+static struct clk clk_fout_apll = {
-        clk->rate = rate;
+        .name           = "fout_apll",
-        return 1;
-}
-struct clk clk_27m = {
-        .name           = "clk_27m",
        .id             = -1,
        .rate           = 27000000,
 };
-static int clk_48m_ctrl(struct clk *clk, int enable)
+static struct clk *clk_src_apll_list[] = {
-{
+        [0] = &clk_fin_apll,
-        unsigned long flags;
+        [1] = &clk_fout_apll,
-        u32 val;
+};
+static struct clk_sources clk_src_apll = {
+        .sources        = clk_src_apll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
+};
-        /* can't rely on clock lock, this register has other usages */
+static struct clksrc_clk clk_mout_apll = {
-        local_irq_save(flags);
+        .clk    = {
+                .name           = "mout_apll",
+                .id             = -1,
+        },
+        .shift          = S5PC100_CLKSRC0_APLL_SHIFT,
+        .mask           = S5PC100_CLKSRC0_APLL_MASK,
+        .sources        = &clk_src_apll,
+        .reg_source     = S5PC100_CLKSRC0,
+};
-        val = __raw_readl(S5PC1XX_CLK_SRC1);
+static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk)
-        if (enable)
+{
-                val |= S5PC100_CLKSRC1_CLK48M_MASK;
+        unsigned long rate = clk_get_rate(clk->parent);
-        else
+        unsigned int ratio;
-                val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
-        __raw_writel(val, S5PC1XX_CLK_SRC1);
+        ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_APLL_MASK;
-        local_irq_restore(flags);
+        ratio >>= S5PC100_CLKDIV0_APLL_SHIFT;
-        return 0;
+        return rate / (ratio + 1);
 }
-struct clk clk_48m = {
+static struct clk clk_dout_apll = {
-        .name           = "clk_48m",
+        .name           = "dout_apll",
        .id             = -1,
-        .rate           = 48000000,
+        .parent         = &clk_mout_apll.clk,
-        .enable         = clk_48m_ctrl,
+        .get_rate       = s5pc100_clk_dout_apll_get_rate,
 };
-struct clk clk_54m = {
+static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk)
-        .name           = "clk_54m",
+{
-        .id             = -1,
+        unsigned long rate = clk_get_rate(clk->parent);
-        .rate           = 54000000,
+        unsigned int ratio;
-};
-struct clk clk_hpll = {
-        .name           = "hpll",
-        .id             = -1,
-};
-struct clk clk_hd0 = {
+        ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_ARM_MASK;
-        .name           = "hclkd0",
+        ratio >>= S5PC100_CLKDIV0_ARM_SHIFT;
-        .id             = -1,
-        .rate           = 0,
-        .parent         = NULL,
-        .ctrlbit        = 0,
-        .set_rate       = clk_default_setrate,
-};
-struct clk clk_pd0 = {
+        return rate / (ratio + 1);
-        .name           = "pclkd0",
+}
-        .id             = -1,
-        .rate           = 0,
-        .parent         = NULL,
-        .ctrlbit        = 0,
-        .set_rate       = clk_default_setrate,
-};
-static int s5pc1xx_clk_gate(void __iomem *reg,
+static unsigned long s5pc100_clk_arm_round_rate(struct clk *clk,
-                                struct clk *clk,
+                                                unsigned long rate)
-                                int enable)
 {
-        unsigned int ctrlbit = clk->ctrlbit;
+        unsigned long parent = clk_get_rate(clk->parent);
-        u32 con;
+        u32 div;
-        con = __raw_readl(reg);
+        if (parent < rate)
+                return rate;
-        if (enable)
+        div = (parent / rate) - 1;
-                con |= ctrlbit;
+        if (div > S5PC100_CLKDIV0_ARM_MASK)
-        else
+                div = S5PC100_CLKDIV0_ARM_MASK;
-                con &= ~ctrlbit;
-        __raw_writel(con, reg);
+        return parent / (div + 1);
-        return 0;
 }
-static int s5pc1xx_clk_d00_ctrl(struct clk *clk, int enable)
+static int s5pc100_clk_arm_set_rate(struct clk *clk, unsigned long rate)
 {
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
+        unsigned long parent = clk_get_rate(clk->parent);
-}
+        u32 div;
+        u32 val;
-static int s5pc1xx_clk_d01_ctrl(struct clk *clk, int enable)
+        if (rate < parent / (S5PC100_CLKDIV0_ARM_MASK + 1))
-{
+                return -EINVAL;
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
-}
-static int s5pc1xx_clk_d02_ctrl(struct clk *clk, int enable)
+        rate = clk_round_rate(clk, rate);
-{
+        div = clk_get_rate(clk->parent) / rate;
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
-}
-static int s5pc1xx_clk_d10_ctrl(struct clk *clk, int enable)
+        val = __raw_readl(S5PC100_CLKDIV0);
-{
+        val &= S5PC100_CLKDIV0_ARM_MASK;
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
+        val |= (div - 1);
-}
+        __raw_writel(val, S5PC100_CLKDIV0);
-static int s5pc1xx_clk_d11_ctrl(struct clk *clk, int enable)
+        return 0;
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
 }
-static int s5pc1xx_clk_d12_ctrl(struct clk *clk, int enable)
+static struct clk clk_arm = {
-{
+        .name           = "armclk",
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
+        .id             = -1,
-}
+        .parent         = &clk_dout_apll,
+        .get_rate       = s5pc100_clk_arm_get_rate,
+        .set_rate       = s5pc100_clk_arm_set_rate,
+        .round_rate     = s5pc100_clk_arm_round_rate,
+};
-static int s5pc1xx_clk_d13_ctrl(struct clk *clk, int enable)
+static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk)
 {
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
+        unsigned long rate = clk_get_rate(clk->parent);
-}
+        unsigned int ratio;
-static int s5pc1xx_clk_d14_ctrl(struct clk *clk, int enable)
+        ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_D0_MASK;
-{
+        ratio >>= S5PC100_CLKDIV0_D0_SHIFT;
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
-}
-static int s5pc1xx_clk_d15_ctrl(struct clk *clk, int enable)
+        return rate / (ratio + 1);
-{
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
 }
-static int s5pc1xx_clk_d20_ctrl(struct clk *clk, int enable)
+static struct clk clk_dout_d0_bus = {
-{
+        .name           = "dout_d0_bus",
-        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
+        .id             = -1,
-}
+        .parent         = &clk_arm,
+        .get_rate       = s5pc100_clk_dout_d0_bus_get_rate,
+};
-int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable)
+static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk)
 {
-        return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned int ratio;
+        ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_PCLKD0_MASK;
+        ratio >>= S5PC100_CLKDIV0_PCLKD0_SHIFT;
+        return rate / (ratio + 1);
 }
-int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable)
+static struct clk clk_dout_pclkd0 = {
+        .name           = "dout_pclkd0",
+        .id             = -1,
+        .parent         = &clk_dout_d0_bus,
+        .get_rate       = s5pc100_clk_dout_pclkd0_get_rate,
+};
+static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk)
 {
-        return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned int ratio;
+        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_APLL2_MASK;
+        ratio >>= S5PC100_CLKDIV1_APLL2_SHIFT;
+        return rate / (ratio + 1);
 }
-static struct clk init_clocks_disable[] = {
+static struct clk clk_dout_apll2 = {
-        {
+        .name           = "dout_apll2",
-                .name           = "dsi",
+        .id             = -1,
-                .id             = -1,
+        .parent         = &clk_mout_apll.clk,
-                .parent         = &clk_p,
+        .get_rate       = s5pc100_clk_dout_apll2_get_rate,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_DSI,
-        }, {
-                .name           = "csi",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_CSI,
-        }, {
-                .name           = "ccan0",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN0,
-        }, {
-                .name           = "ccan1",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN1,
-        }, {
-                .name           = "keypad",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_KEYIF,
-        }, {
-                .name           = "hclkd2",
-                .id             = -1,
-                .parent         = NULL,
-                .enable         = s5pc1xx_clk_d20_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D20_HCLKD2,
-        }, {
-                .name           = "iis-d2",
-                .id             = -1,
-                .parent         = NULL,
-                .enable         = s5pc1xx_clk_d20_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D20_I2SD2,
-        }, {
-                .name           = "otg",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_USBOTG,
-        },
 };
-static struct clk init_clocks[] = {
+/* MPLL */
-        /* System1 (D0_0) devices */
+static struct clk *clk_src_mpll_list[] = {
-        {
+        [0] = &clk_fin_mpll,
-                .name           = "intc",
+        [1] = &clk_fout_mpll,
-                .id             = -1,
+};
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_INTC,
-        }, {
-                .name           = "tzic",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_TZIC,
-        }, {
-                .name           = "cf-ata",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_CFCON,
-        }, {
-                .name           = "mdma",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_MDMA,
-        }, {
-                .name           = "g2d",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_G2D,
-        }, {
-                .name           = "secss",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_SECSS,
-        }, {
-                .name           = "cssys",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d00_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D00_CSSYS,
-        },
-        /* Memory (D0_1) devices */
+static struct clk_sources clk_src_mpll = {
-        {
+        .sources        = clk_src_mpll_list,
-                .name           = "dmc",
+        .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
-                .id             = -1,
+};
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_DMC,
-        }, {
-                .name           = "sromc",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_SROMC,
-        }, {
-                .name           = "onenand",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_ONENAND,
-        }, {
-                .name           = "nand",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_NFCON,
-        }, {
-                .name           = "intmem",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_INTMEM,
-        }, {
-                .name           = "ebi",
-                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d01_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D01_EBI,
-        },
-        /* System2 (D0_2) devices */
+static struct clksrc_clk clk_mout_mpll = {
-        {
+        .clk = {
-                .name           = "seckey",
+                .name           = "mout_mpll",
-                .id             = -1,
-                .parent         = &clk_pd0,
-                .enable         = s5pc1xx_clk_d02_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D02_SECKEY,
-        }, {
-                .name           = "sdm",
                .id             = -1,
-                .parent         = &clk_hd0,
-                .enable         = s5pc1xx_clk_d02_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D02_SDM,
        },
+        .shift          = S5PC100_CLKSRC0_MPLL_SHIFT,
+        .mask           = S5PC100_CLKSRC0_MPLL_MASK,
+        .sources        = &clk_src_mpll,
+        .reg_source     = S5PC100_CLKSRC0,
+};
-        /* File (D1_0) devices */
+static struct clk *clkset_am_list[] = {
-        {
+        [0] = &clk_mout_mpll.clk,
-                .name           = "pdma0",
+        [1] = &clk_dout_apll2,
-                .id             = -1,
+};
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA0,
-        }, {
-                .name           = "pdma1",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA1,
-        }, {
-                .name           = "usb-host",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_USBHOST,
-        }, {
-                .name           = "modem",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_MODEMIF,
-        }, {
-                .name           = "hsmmc",
-                .id             = 0,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC0,
-        }, {
-                .name           = "hsmmc",
-                .id             = 1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC1,
-        }, {
-                .name           = "hsmmc",
-                .id             = 2,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d10_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC2,
-        },
-        /* Multimedia1 (D1_1) devices */
+static struct clk_sources clk_src_am = {
-        {
+        .sources        = clkset_am_list,
-                .name           = "lcd",
+        .nr_sources     = ARRAY_SIZE(clkset_am_list),
-                .id             = -1,
+};
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_LCD,
-        }, {
-                .name           = "rotator",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_ROTATOR,
-        }, {
-                .name           = "fimc",
-                .id             = 0,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC0,
-        }, {
-                .name           = "fimc",
-                .id             = 1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC1,
-        }, {
-                .name           = "fimc",
-                .id             = 2,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC2,
-        }, {
-                .name           = "jpeg",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_JPEG,
-        }, {
-                .name           = "g3d",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d11_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D11_G3D,
-        },
-        /* Multimedia2 (D1_2) devices */
+static struct clksrc_clk clk_mout_am = {
-        {
+        .clk = {
-                .name           = "tv",
+                .name           = "mout_am",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_TV,
-        }, {
-                .name           = "vp",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_VP,
-        }, {
-                .name           = "mixer",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_MIXER,
-        }, {
-                .name           = "hdmi",
-                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_HDMI,
-        }, {
-                .name           = "mfc",
                .id             = -1,
-                .parent         = &clk_h,
-                .enable         = s5pc1xx_clk_d12_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D12_MFC,
        },
+        .shift          = S5PC100_CLKSRC0_AMMUX_SHIFT,
+        .mask           = S5PC100_CLKSRC0_AMMUX_MASK,
+        .sources        = &clk_src_am,
+        .reg_source     = S5PC100_CLKSRC0,
+};
-        /* System (D1_3) devices */
+static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk)
-        {
+{
-                .name           = "chipid",
+        unsigned long rate = clk_get_rate(clk->parent);
-                .id             = -1,
+        unsigned int ratio;
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_CHIPID,
-        }, {
-                .name           = "gpio",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_GPIO,
-        }, {
-                .name           = "apc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_APC,
-        }, {
-                .name           = "iec",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_IEC,
-        }, {
-                .name           = "timers",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_PWM,
-        }, {
-                .name           = "systimer",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_SYSTIMER,
-        }, {
-                .name           = "watchdog",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_WDT,
-        }, {
-                .name           = "rtc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d13_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D13_RTC,
-        },
-        /* Connectivity (D1_4) devices */
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-        {
-                .name           = "uart",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_UART0,
-        }, {
-                .name           = "uart",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_UART1,
-        }, {
-                .name           = "uart",
-                .id             = 2,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_UART2,
-        }, {
-                .name           = "uart",
-                .id             = 3,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_UART3,
-        }, {
-                .name           = "i2c",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_IIC,
-        }, {
-                .name           = "hdmi-i2c",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_HDMI_IIC,
-        }, {
-                .name           = "spi",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_SPI0,
-        }, {
-                .name           = "spi",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_SPI1,
-        }, {
-                .name           = "spi",
-                .id             = 2,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_SPI2,
-        }, {
-                .name           = "irda",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_IRDA,
-        }, {
-                .name           = "hsitx",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_HSITX,
-        }, {
-                .name           = "hsirx",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d14_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D14_HSIRX,
-        },
-        /* Audio (D1_5) devices */
+        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_D1_MASK;
-        {
+        ratio >>= S5PC100_CLKDIV1_D1_SHIFT;
-                .name           = "iis",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_IIS0,
-        }, {
-                .name           = "iis",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_IIS1,
-        }, {
-                .name           = "iis",
-                .id             = 2,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_IIS2,
-        }, {
-                .name           = "ac97",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_AC97,
-        }, {
-                .name           = "pcm",
-                .id             = 0,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_PCM0,
-        }, {
-                .name           = "pcm",
-                .id             = 1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_PCM1,
-        }, {
-                .name           = "spdif",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_SPDIF,
-        }, {
-                .name           = "adc",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_TSADC,
-        }, {
-                .name           = "keyif",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_KEYIF,
-        }, {
-                .name           = "cg",
-                .id             = -1,
-                .parent         = &clk_p,
-                .enable         = s5pc1xx_clk_d15_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_D15_CG,
-        },
-        /* Audio (D2_0) devices: all disabled */
+        return rate / (ratio + 1);
+}
-        /* Special Clocks 1 */
+static struct clk clk_dout_d1_bus = {
-        {
+        .name           = "dout_d1_bus",
-                .name           = "sclk_hpm",
+        .id             = -1,
-                .id             = -1,
+        .parent         = &clk_mout_am.clk,
-                .parent         = NULL,
+        .get_rate       = s5pc100_clk_dout_d1_bus_get_rate,
-                .enable         = s5pc1xx_sclk0_ctrl,
+};
-                .ctrlbit        = S5PC1XX_CLKGATE_SCLK0_HPM,
-        }, {
-                .name           = "sclk_onenand",
-                .id             = -1,
-                .parent         = NULL,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_ONENAND,
-        }, {
-                .name           = "sclk_spi_48",
-                .id             = 0,
-                .parent         = &clk_48m,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI0_48,
-        }, {
-                .name           = "sclk_spi_48",
-                .id             = 1,
-                .parent         = &clk_48m,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI1_48,
-        }, {
-                .name           = "sclk_spi_48",
-                .id             = 2,
-                .parent         = &clk_48m,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI2_48,
-        }, {
-                .name           = "sclk_mmc_48",
-                .id             = 0,
-                .parent         = &clk_48m,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC0_48,
-        }, {
-                .name           = "sclk_mmc_48",
-                .id             = 1,
-                .parent         = &clk_48m,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC1_48,
-        }, {
-                .name           = "sclk_mmc_48",
-                .id             = 2,
-                .parent         = &clk_48m,
-                .enable         = s5pc1xx_sclk0_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC2_48,
-        },
-        /* Special Clocks 2 */
+static struct clk *clkset_onenand_list[] = {
-        {
+        [0] = &clk_dout_d0_bus,
-                .name           = "sclk_tv_54",
+        [1] = &clk_dout_d1_bus,
-                .id             = -1,
+};
-                .parent         = &clk_54m,
-                .enable         = s5pc1xx_sclk1_ctrl,
+static struct clk_sources clk_src_onenand = {
-                .ctrlbit        = S5PC100_CLKGATE_SCLK1_TV54,
+        .sources        = clkset_onenand_list,
-        }, {
+        .nr_sources     = ARRAY_SIZE(clkset_onenand_list),
-                .name           = "sclk_vdac_54",
+};
-                .id             = -1,
-                .parent         = &clk_54m,
+static struct clksrc_clk clk_mout_onenand = {
-                .enable         = s5pc1xx_sclk1_ctrl,
+        .clk = {
-                .ctrlbit        = S5PC100_CLKGATE_SCLK1_VDAC54,
+                .name           = "mout_onenand",
-        }, {
-                .name           = "sclk_spdif",
                .id             = -1,
-                .parent         = NULL,
-                .enable         = s5pc1xx_sclk1_ctrl,
-                .ctrlbit        = S5PC100_CLKGATE_SCLK1_SPDIF,
        },
+        .shift          = S5PC100_CLKSRC0_ONENAND_SHIFT,
+        .mask           = S5PC100_CLKSRC0_ONENAND_MASK,
+        .sources        = &clk_src_onenand,
+        .reg_source     = S5PC100_CLKSRC0,
 };
-void __init s5pc1xx_register_clocks(void)
+static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk)
 {
-        struct clk *clkp;
+        unsigned long rate = clk_get_rate(clk->parent);
-        int ret;
+        unsigned int ratio;
-        int ptr;
-        clkp = init_clocks;
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-        }
-        clkp = init_clocks_disable;
+        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_PCLKD1_MASK;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+        ratio >>= S5PC100_CLKDIV1_PCLKD1_SHIFT;
-                ret = s3c24xx_register_clock(clkp);
+        return rate / (ratio + 1);
-                if (ret < 0) {
+}
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-                (clkp->enable)(clkp, 0);
+static struct clk clk_dout_pclkd1 = {
-        }
+        .name           = "dout_pclkd1",
+        .id             = -1,
+        .parent         = &clk_dout_d1_bus,
+        .get_rate       = s5pc100_clk_dout_pclkd1_get_rate,
+};
+static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned int ratio;
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
+        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
+        ratio >>= S5PC100_CLKDIV1_MPLL2_SHIFT;
-        s3c_pwmclk_init();
+        return rate / (ratio + 1);
 }
-static struct clk clk_fout_apll = {
-        .name           = "fout_apll",
+static struct clk clk_dout_mpll2 = {
+        .name           = "dout_mpll2",
        .id             = -1,
+        .parent         = &clk_mout_am.clk,
+        .get_rate       = s5pc100_clk_dout_mpll2_get_rate,
 };
-static struct clk *clk_src_apll_list[] = {
+static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk)
-        [0] = &clk_fin_apll,
+{
-        [1] = &clk_fout_apll,
+        unsigned long rate = clk_get_rate(clk->parent);
-};
+        unsigned int ratio;
-static struct clk_sources clk_src_apll = {
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-        .sources        = clk_src_apll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
+        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_CAM_MASK;
+        ratio >>= S5PC100_CLKDIV1_CAM_SHIFT;
+        return rate / (ratio + 1);
+}
+static struct clk clk_dout_cam = {
+        .name           = "dout_cam",
+        .id             = -1,
+        .parent         = &clk_dout_mpll2,
+        .get_rate       = s5pc100_clk_dout_cam_get_rate,
 };
-static struct clksrc_clk clk_mout_apll = {
+static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk)
-        .clk    = {
+{
-                .name           = "mout_apll",
+        unsigned long rate = clk_get_rate(clk->parent);
-                .id             = -1,
+        unsigned int ratio;
-        },
-        .shift          = S5PC1XX_CLKSRC0_APLL_SHIFT,
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-        .mask           = S5PC1XX_CLKSRC0_APLL_MASK,
-        .sources        = &clk_src_apll,
+        ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK;
-        .reg_source     = S5PC1XX_CLK_SRC0,
+        ratio >>= S5PC100_CLKDIV1_MPLL_SHIFT;
+        return rate / (ratio + 1);
+}
+static struct clk clk_dout_mpll = {
+        .name           = "dout_mpll",
+        .id             = -1,
+        .parent         = &clk_mout_am.clk,
+        .get_rate       = s5pc100_clk_dout_mpll_get_rate,
 };
+/* EPLL */
 static struct clk clk_fout_epll = {
        .name           = "fout_epll",
        .id             = -1,
@@ -827,91 +409,57 @@ static struct clksrc_clk clk_mout_epll = {
                .name           = "mout_epll",
                .id             = -1,
        },
-        .shift          = S5PC1XX_CLKSRC0_EPLL_SHIFT,
+        .shift          = S5PC100_CLKSRC0_EPLL_SHIFT,
-        .mask           = S5PC1XX_CLKSRC0_EPLL_MASK,
+        .mask           = S5PC100_CLKSRC0_EPLL_MASK,
        .sources        = &clk_src_epll,
-        .reg_source     = S5PC1XX_CLK_SRC0,
+        .reg_source     = S5PC100_CLKSRC0,
 };
-static struct clk *clk_src_mpll_list[] = {
+/* HPLL */
-        [0] = &clk_fin_mpll,
+static struct clk clk_fout_hpll = {
-        [1] = &clk_fout_mpll,
+        .name           = "fout_hpll",
-};
-static struct clk_sources clk_src_mpll = {
-        .sources        = clk_src_mpll_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
-};
-static struct clksrc_clk clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-                .id             = -1,
-        },
-        .shift          = S5PC1XX_CLKSRC0_MPLL_SHIFT,
-        .mask           = S5PC1XX_CLKSRC0_MPLL_MASK,
-        .sources        = &clk_src_mpll,
-        .reg_source     = S5PC1XX_CLK_SRC0,
-};
-static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned long clkdiv;
-        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-        clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL_MASK;
-        rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL_SHIFT) + 1;
-        return rate;
-}
-static struct clk clk_dout_mpll = {
-        .name           = "dout_mpll",
        .id             = -1,
-        .parent         = &clk_mout_mpll.clk,
-        .get_rate       = s5pc1xx_clk_doutmpll_get_rate,
 };
-static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk)
+static struct clk *clk_src_hpll_list[] = {
-{
+        [0] = &clk_27m,
-        unsigned long rate = clk_get_rate(clk->parent);
+        [1] = &clk_fout_hpll,
-        unsigned long clkdiv;
-        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
-        clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
-        rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL2_SHIFT) + 1;
-        return rate;
-}
-struct clk clk_dout_mpll2 = {
-        .name           = "dout_mpll2",
-        .id             = -1,
-        .parent         = &clk_mout_mpll.clk,
-        .get_rate       = s5pc1xx_clk_doutmpll2_get_rate,
 };
-static struct clk *clkset_uart_list[] = {
+static struct clk_sources clk_src_hpll = {
-        &clk_mout_epll.clk,
+        .sources        = clk_src_hpll_list,
-        &clk_dout_mpll,
+        .nr_sources     = ARRAY_SIZE(clk_src_hpll_list),
-        NULL,
-        NULL
 };
-static struct clk_sources clkset_uart = {
+static struct clksrc_clk clk_mout_hpll = {
-        .sources        = clkset_uart_list,
+        .clk    = {
-        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+                .name           = "mout_hpll",
+                .id             = -1,
+        },
+        .shift          = S5PC100_CLKSRC0_HPLL_SHIFT,
+        .mask           = S5PC100_CLKSRC0_HPLL_MASK,
+        .sources        = &clk_src_hpll,
+        .reg_source     = S5PC100_CLKSRC0,
 };
+/* Peripherals */
+/*
+ * The peripheral clocks are all controlled via clocksource followed
+ * by an optional divider and gate stage. We currently roll this into
+ * one clock which hides the intermediate clock from the mux.
+ *
+ * Note, the JPEG clock can only be an even divider...
+ *
+ * The scaler and LCD clocks depend on the S5PC100 version, and also
+ * have a common parent divisor so are not included here.
+ */
 static inline struct clksrc_clk *to_clksrc(struct clk *clk)
 {
        return container_of(clk, struct clksrc_clk, clk);
 }
-static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk)
+static unsigned long s5pc100_getrate_clksrc(struct clk *clk)
 {
        struct clksrc_clk *sclk = to_clksrc(clk);
        unsigned long rate = clk_get_rate(clk->parent);
@@ -925,7 +473,7 @@ static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk)
        return rate;
 }
-static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate)
+static int s5pc100_setrate_clksrc(struct clk *clk, unsigned long rate)
 {
        struct clksrc_clk *sclk = to_clksrc(clk);
        void __iomem *reg = sclk->reg_divider;
@@ -938,14 +486,14 @@ static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate)
                return -EINVAL;
        val = __raw_readl(reg);
-        val &= ~(0xf << sclk->shift);
+        val &= ~(0xf << sclk->divider_shift);
-        val |= (div - 1) << sclk->shift;
+        val |= (div - 1) << sclk->divider_shift;
        __raw_writel(val, reg);
        return 0;
 }
-static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent)
+static int s5pc100_setparent_clksrc(struct clk *clk, struct clk *parent)
 {
        struct clksrc_clk *sclk = to_clksrc(clk);
        struct clk_sources *srcs = sclk->sources;
@@ -970,7 +518,7 @@ static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent)
        return -EINVAL;
 }
-static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk,
+static unsigned long s5pc100_roundrate_clksrc(struct clk *clk,
                                              unsigned long rate)
 {
        unsigned long parent_rate = clk_get_rate(clk->parent);
@@ -992,35 +540,466 @@ static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk,
        return rate;
 }
+static struct clk *clkset_spi_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll2,
+        &clk_fin_epll,
+        &clk_mout_hpll.clk,
+};
+static struct clk_sources clkset_spi = {
+        .sources        = clkset_spi_list,
+        .nr_sources     = ARRAY_SIZE(clkset_spi_list),
+};
+static struct clksrc_clk clk_spi0 = {
+        .clk    = {
+                .name           = "spi_bus",
+                .id             = 0,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI0,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC1_SPI0_SHIFT,
+        .mask           = S5PC100_CLKSRC1_SPI0_MASK,
+        .sources        = &clkset_spi,
+        .divider_shift  = S5PC100_CLKDIV2_SPI0_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV2,
+        .reg_source     = S5PC100_CLKSRC1,
+};
+static struct clksrc_clk clk_spi1 = {
+        .clk    = {
+                .name           = "spi_bus",
+                .id             = 1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI1,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC1_SPI1_SHIFT,
+        .mask           = S5PC100_CLKSRC1_SPI1_MASK,
+        .sources        = &clkset_spi,
+        .divider_shift  = S5PC100_CLKDIV2_SPI1_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV2,
+        .reg_source     = S5PC100_CLKSRC1,
+};
+static struct clksrc_clk clk_spi2 = {
+        .clk    = {
+                .name           = "spi_bus",
+                .id             = 2,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI2,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC1_SPI2_SHIFT,
+        .mask           = S5PC100_CLKSRC1_SPI2_MASK,
+        .sources        = &clkset_spi,
+        .divider_shift  = S5PC100_CLKDIV2_SPI2_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV2,
+        .reg_source     = S5PC100_CLKSRC1,
+};
+static struct clk *clkset_uart_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+};
+static struct clk_sources clkset_uart = {
+        .sources        = clkset_uart_list,
+        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+};
 static struct clksrc_clk clk_uart_uclk1 = {
        .clk    = {
                .name           = "uclk1",
                .id             = -1,
                .ctrlbit        = S5PC100_CLKGATE_SCLK0_UART,
-                .enable         = s5pc1xx_sclk0_ctrl,
+                .enable         = s5pc100_sclk0_ctrl,
-                .set_parent     = s5pc1xx_setparent_clksrc,
+                .set_parent     = s5pc100_setparent_clksrc,
-                .get_rate       = s5pc1xx_getrate_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
-                .set_rate       = s5pc1xx_setrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
-                .round_rate     = s5pc1xx_roundrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
        },
        .shift          = S5PC100_CLKSRC1_UART_SHIFT,
        .mask           = S5PC100_CLKSRC1_UART_MASK,
        .sources        = &clkset_uart,
        .divider_shift  = S5PC100_CLKDIV2_UART_SHIFT,
-        .reg_divider    = S5PC1XX_CLK_DIV2,
+        .reg_divider    = S5PC100_CLKDIV2,
-        .reg_source     = S5PC1XX_CLK_SRC1,
+        .reg_source     = S5PC100_CLKSRC1,
+};
+static struct clk clk_iis_cd0 = {
+        .name           = "iis_cdclk0",
+        .id             = -1,
+};
+static struct clk clk_iis_cd1 = {
+        .name           = "iis_cdclk1",
+        .id             = -1,
+};
+static struct clk clk_iis_cd2 = {
+        .name           = "iis_cdclk2",
+        .id             = -1,
+};
+static struct clk clk_pcm_cd0 = {
+        .name           = "pcm_cdclk0",
+        .id             = -1,
+};
+static struct clk clk_pcm_cd1 = {
+        .name           = "pcm_cdclk1",
+        .id             = -1,
+};
+static struct clk *clkset_audio0_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        &clk_fin_epll,
+        &clk_iis_cd0,
+        &clk_pcm_cd0,
+        &clk_mout_hpll.clk,
+};
+static struct clk_sources clkset_audio0 = {
+        .sources        = clkset_audio0_list,
+        .nr_sources     = ARRAY_SIZE(clkset_audio0_list),
+};
+static struct clksrc_clk clk_audio0 = {
+        .clk    = {
+                .name           = "audio-bus",
+                .id             = 0,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_AUDIO0,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC3_AUDIO0_SHIFT,
+        .mask           = S5PC100_CLKSRC3_AUDIO0_MASK,
+        .sources        = &clkset_audio0,
+        .divider_shift  = S5PC100_CLKDIV4_AUDIO0_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV4,
+        .reg_source     = S5PC100_CLKSRC3,
+};
+static struct clk *clkset_audio1_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        &clk_fin_epll,
+        &clk_iis_cd1,
+        &clk_pcm_cd1,
+        &clk_mout_hpll.clk,
+};
+static struct clk_sources clkset_audio1 = {
+        .sources        = clkset_audio1_list,
+        .nr_sources     = ARRAY_SIZE(clkset_audio1_list),
+};
+static struct clksrc_clk clk_audio1 = {
+        .clk    = {
+                .name           = "audio-bus",
+                .id             = 1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_AUDIO1,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC3_AUDIO1_SHIFT,
+        .mask           = S5PC100_CLKSRC3_AUDIO1_MASK,
+        .sources        = &clkset_audio1,
+        .divider_shift  = S5PC100_CLKDIV4_AUDIO1_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV4,
+        .reg_source     = S5PC100_CLKSRC3,
+};
+static struct clk *clkset_audio2_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        &clk_fin_epll,
+        &clk_iis_cd2,
+        &clk_mout_hpll.clk,
+};
+static struct clk_sources clkset_audio2 = {
+        .sources        = clkset_audio2_list,
+        .nr_sources     = ARRAY_SIZE(clkset_audio2_list),
+};
+static struct clksrc_clk clk_audio2 = {
+        .clk    = {
+                .name           = "audio-bus",
+                .id             = 2,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_AUDIO2,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC3_AUDIO2_SHIFT,
+        .mask           = S5PC100_CLKSRC3_AUDIO2_MASK,
+        .sources        = &clkset_audio2,
+        .divider_shift  = S5PC100_CLKDIV4_AUDIO2_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV4,
+        .reg_source     = S5PC100_CLKSRC3,
+};
+static struct clk *clkset_spdif_list[] = {
+        &clk_audio0.clk,
+        &clk_audio1.clk,
+        &clk_audio2.clk,
+};
+static struct clk_sources clkset_spdif = {
+        .sources        = clkset_spdif_list,
+        .nr_sources     = ARRAY_SIZE(clkset_spdif_list),
+};
+static struct clksrc_clk clk_spdif = {
+        .clk    = {
+                .name           = "spdif",
+                .id             = -1,
+        },
+        .shift          = S5PC100_CLKSRC3_SPDIF_SHIFT,
+        .mask           = S5PC100_CLKSRC3_SPDIF_MASK,
+        .sources        = &clkset_spdif,
+        .reg_source     = S5PC100_CLKSRC3,
+};
+static struct clk *clkset_lcd_fimc_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        &clk_mout_hpll.clk,
+        &clk_vclk_54m,
+};
+static struct clk_sources clkset_lcd_fimc = {
+        .sources        = clkset_lcd_fimc_list,
+        .nr_sources     = ARRAY_SIZE(clkset_lcd_fimc_list),
+};
+static struct clksrc_clk clk_lcd = {
+        .clk    = {
+                .name           = "lcd",
+                .id             = -1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_LCD,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_LCD_SHIFT,
+        .mask           = S5PC100_CLKSRC2_LCD_MASK,
+        .sources        = &clkset_lcd_fimc,
+        .divider_shift  = S5PC100_CLKDIV3_LCD_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clksrc_clk clk_fimc0 = {
+        .clk    = {
+                .name           = "fimc",
+                .id             = 0,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_FIMC0,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_FIMC0_SHIFT,
+        .mask           = S5PC100_CLKSRC2_FIMC0_MASK,
+        .sources        = &clkset_lcd_fimc,
+        .divider_shift  = S5PC100_CLKDIV3_FIMC0_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clksrc_clk clk_fimc1 = {
+        .clk    = {
+                .name           = "fimc",
+                .id             = 1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_FIMC1,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_FIMC1_SHIFT,
+        .mask           = S5PC100_CLKSRC2_FIMC1_MASK,
+        .sources        = &clkset_lcd_fimc,
+        .divider_shift  = S5PC100_CLKDIV3_FIMC1_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clksrc_clk clk_fimc2 = {
+        .clk    = {
+                .name           = "fimc",
+                .id             = 2,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_FIMC2,
+                .enable         = s5pc100_sclk1_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_FIMC2_SHIFT,
+        .mask           = S5PC100_CLKSRC2_FIMC2_MASK,
+        .sources        = &clkset_lcd_fimc,
+        .divider_shift  = S5PC100_CLKDIV3_FIMC2_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clk *clkset_mmc_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        &clk_fin_epll,
+        &clk_mout_hpll.clk ,
+};
+static struct clk_sources clkset_mmc = {
+        .sources        = clkset_mmc_list,
+        .nr_sources     = ARRAY_SIZE(clkset_mmc_list),
+};
+static struct clksrc_clk clk_mmc0 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .id             = 0,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC0,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_MMC0_SHIFT,
+        .mask           = S5PC100_CLKSRC2_MMC0_MASK,
+        .sources        = &clkset_mmc,
+        .divider_shift  = S5PC100_CLKDIV3_MMC0_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clksrc_clk clk_mmc1 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .id             = 1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC1,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_MMC1_SHIFT,
+        .mask           = S5PC100_CLKSRC2_MMC1_MASK,
+        .sources        = &clkset_mmc,
+        .divider_shift  = S5PC100_CLKDIV3_MMC1_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clksrc_clk clk_mmc2 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .id             = 2,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC2,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC2_MMC2_SHIFT,
+        .mask           = S5PC100_CLKSRC2_MMC2_MASK,
+        .sources        = &clkset_mmc,
+        .divider_shift  = S5PC100_CLKDIV3_MMC2_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV3,
+        .reg_source     = S5PC100_CLKSRC2,
+};
+static struct clk *clkset_usbhost_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        &clk_mout_hpll.clk,
+        &clk_48m,
+};
+static struct clk_sources clkset_usbhost = {
+        .sources        = clkset_usbhost_list,
+        .nr_sources     = ARRAY_SIZE(clkset_usbhost_list),
+};
+static struct clksrc_clk clk_usbhost = {
+        .clk    = {
+                .name           = "usbhost",
+                .id             = -1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_USBHOST,
+                .enable         = s5pc100_sclk0_ctrl,
+                .set_parent     = s5pc100_setparent_clksrc,
+                .get_rate       = s5pc100_getrate_clksrc,
+                .set_rate       = s5pc100_setrate_clksrc,
+                .round_rate     = s5pc100_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC1_UHOST_SHIFT,
+        .mask           = S5PC100_CLKSRC1_UHOST_MASK,
+        .sources        = &clkset_usbhost,
+        .divider_shift  = S5PC100_CLKDIV2_UHOST_SHIFT,
+        .reg_divider    = S5PC100_CLKDIV2,
+        .reg_source     = S5PC100_CLKSRC1,
 };
 /* Clock initialisation code */
 static struct clksrc_clk *init_parents[] = {
        &clk_mout_apll,
-        &clk_mout_epll,
        &clk_mout_mpll,
+        &clk_mout_am,
+        &clk_mout_onenand,
+        &clk_mout_epll,
+        &clk_mout_hpll,
+        &clk_spi0,
+        &clk_spi1,
+        &clk_spi2,
        &clk_uart_uclk1,
+        &clk_audio0,
+        &clk_audio1,
+        &clk_audio2,
+        &clk_spdif,
+        &clk_lcd,
+        &clk_fimc0,
+        &clk_fimc1,
+        &clk_fimc2,
+        &clk_mmc0,
+        &clk_mmc1,
+        &clk_mmc2,
+        &clk_usbhost,
 };
-static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk)
+static void __init_or_cpufreq s5pc100_set_clksrc(struct clksrc_clk *clk)
 {
        struct clk_sources *srcs = clk->sources;
        u32 clksrc = __raw_readl(clk->reg_source);
@@ -1036,9 +1015,9 @@ static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk)
        clk->clk.parent = srcs->sources[clksrc];
-        printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
+        printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n",
-               clk->clk.name, clk->clk.parent->name, clksrc,
+                clk->clk.name, clk->clk.parent->name, clksrc,
-               clk_get_rate(&clk->clk));
+                print_mhz(clk_get_rate(&clk->clk)));
 }
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@@ -1052,20 +1031,16 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
        unsigned long hclk;
        unsigned long pclkd0;
        unsigned long pclk;
-        unsigned long apll;
+        unsigned long apll, mpll, epll, hpll;
-        unsigned long mpll;
-        unsigned long hpll;
-        unsigned long epll;
        unsigned int ptr;
        u32 clkdiv0, clkdiv1;
        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-        clkdiv0 = __raw_readl(S5PC1XX_CLK_DIV0);
+        clkdiv0 = __raw_readl(S5PC100_CLKDIV0);
-        clkdiv1 = __raw_readl(S5PC1XX_CLK_DIV1);
+        clkdiv1 = __raw_readl(S5PC100_CLKDIV1);
-        printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
+        printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1);
-                        __func__, clkdiv0, clkdiv1);
        xtal_clk = clk_get(NULL, "xtal");
        BUG_ON(IS_ERR(xtal_clk));
@@ -1075,48 +1050,81 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-        apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_APLL_CON));
+        apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON));
-        mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_MPLL_CON));
+        mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON));
-        epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_EPLL_CON));
+        epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON));
        hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
-        printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n",
+        printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz"
-               apll, mpll, epll, hpll);
+                ", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n",
+                print_mhz(apll), print_mhz(mpll),
+                print_mhz(epll), print_mhz(hpll));
-        armclk = apll / GET_DIV(clkdiv0, S5PC1XX_CLKDIV0_APLL);
+        armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL);
        armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM);
        hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0);
        pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0);
        hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1);
        pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1);
-        printk(KERN_INFO "S5PC100: ARMCLK=%ld, HCLKD0=%ld, PCLKD0=%ld, HCLK=%ld, PCLK=%ld\n",
+        printk(KERN_INFO "S5PC100: ARMCLK=%ld.%03ld MHz, HCLKD0=%ld.%03ld MHz,"
-               armclk, hclkd0, pclkd0, hclk, pclk);
+                " PCLKD0=%ld.%03ld MHz\n, HCLK=%ld.%03ld MHz,"
+                " PCLK=%ld.%03ld MHz\n",
+                print_mhz(armclk), print_mhz(hclkd0),
+                print_mhz(pclkd0), print_mhz(hclk), print_mhz(pclk));
        clk_fout_apll.rate = apll;
        clk_fout_mpll.rate = mpll;
        clk_fout_epll.rate = epll;
-        clk_fout_apll.rate = apll;
+        clk_fout_hpll.rate = hpll;
        clk_h.rate = hclk;
        clk_p.rate = pclk;
+        clk_f.rate = armclk;
        for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
-                s5pc1xx_set_clksrc(init_parents[ptr]);
+                s5pc100_set_clksrc(init_parents[ptr]);
 }
 static struct clk *clks[] __initdata = {
        &clk_ext_xtal_mux,
-        &clk_mout_epll.clk,
+        &clk_mout_apll.clk,
-        &clk_fout_epll,
+        &clk_dout_apll,
+        &clk_dout_d0_bus,
+        &clk_dout_pclkd0,
+        &clk_dout_apll2,
        &clk_mout_mpll.clk,
+        &clk_mout_am.clk,
+        &clk_dout_d1_bus,
+        &clk_mout_onenand.clk,
+        &clk_dout_pclkd1,
+        &clk_dout_mpll2,
+        &clk_dout_cam,
        &clk_dout_mpll,
+        &clk_mout_epll.clk,
+        &clk_fout_epll,
+        &clk_iis_cd0,
+        &clk_iis_cd1,
+        &clk_iis_cd2,
+        &clk_pcm_cd0,
+        &clk_pcm_cd1,
+        &clk_spi0.clk,
+        &clk_spi1.clk,
+        &clk_spi2.clk,
        &clk_uart_uclk1.clk,
-        &clk_ext,
+        &clk_audio0.clk,
-        &clk_epll,
+        &clk_audio1.clk,
-        &clk_27m,
+        &clk_audio2.clk,
-        &clk_48m,
+        &clk_spdif.clk,
-        &clk_54m,
+        &clk_lcd.clk,
+        &clk_fimc0.clk,
+        &clk_fimc1.clk,
+        &clk_fimc2.clk,
+        &clk_mmc0.clk,
+        &clk_mmc1.clk,
+        &clk_mmc2.clk,
+        &clk_usbhost.clk,
+        &clk_arm,
 };
 void __init s5pc100_register_clocks(void)
@@ -1133,7 +1141,4 @@ void __init s5pc100_register_clocks(void)
                               clkp->name, ret);
                }
        }
-        clk_mpll.parent = &clk_mout_mpll.clk;
-        clk_epll.parent = &clk_mout_epll.clk;
 }
diff --git a/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c b/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c
new file mode 100644
index 000000000000..1a63768a9a2e
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c
@@ -0,0 +1,49 @@
+/*
+ * linux/arch/arm/plat-s5pc100/setup-fb-24bpp.c
+ *
+ * Copyright 2009 Samsung Electronics
+ *
+ * Base S5PC1XX setup information for 24bpp LCD framebuffer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <mach/regs-fb.h>
+#include <mach/map.h>
+#include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-s5pc1xx.h>
+#define DISR_OFFSET     0x7008
+void s5pc100_fb_gpio_setup_24bpp(void)
+{
+        unsigned int gpio = 0;
+        for (gpio = S5PC100_GPF0(0); gpio <= S5PC100_GPF0(7); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        for (gpio = S5PC100_GPF1(0); gpio <= S5PC100_GPF1(7); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        for (gpio = S5PC100_GPF2(0); gpio <= S5PC100_GPF2(7); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        for (gpio = S5PC100_GPF3(0); gpio <= S5PC100_GPF3(3); gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+}
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c0.c b/arch/arm/plat-s5pc1xx/setup-i2c0.c
index 3d00c025fffb..5e4a7c3a231e 100644
--- a/arch/arm/plat-s5pc1xx/setup-i2c0.c
+++ b/arch/arm/plat-s5pc1xx/setup-i2c0.c
@@ -17,9 +17,14 @@
 struct platform_device; /* don't need the contents */
+#include <linux/gpio.h>
 #include <plat/iic.h>
+#include <plat/gpio-cfg.h>
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        /* Pin configuration would be needed */
+        s3c_gpio_cfgpin(S5PC100_GPD(3), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PC100_GPD(3), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPD(4), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PC100_GPD(4), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c1.c b/arch/arm/plat-s5pc1xx/setup-i2c1.c
index c8f3ca42f51d..a0a8b4ae6ad8 100644
--- a/arch/arm/plat-s5pc1xx/setup-i2c1.c
+++ b/arch/arm/plat-s5pc1xx/setup-i2c1.c
@@ -17,9 +17,14 @@
 struct platform_device; /* don't need the contents */
+#include <linux/gpio.h>
 #include <plat/iic.h>
+#include <plat/gpio-cfg.h>
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
 {
-        /* Pin configuration would be needed */
+        s3c_gpio_cfgpin(S5PC100_GPD(5), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PC100_GPD(5), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPD(6), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PC100_GPD(6), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c b/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
new file mode 100644
index 000000000000..185c8941e644
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
@@ -0,0 +1,86 @@
+/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
+ *
+ * Copyright 2009 Samsung Eletronics
+ *
+ * S5PC1XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-sdhci.h>
+void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+        unsigned int num;
+        num = width;
+        /* In case of 8 width, we should decrease the 2 */
+        if (width == 8)
+                num = width - 2;
+        end = S5PC100_GPG0(2 + num);
+        /* Set all the necessary GPG0/GPG1 pins to special-function 0 */
+        for (gpio = S5PC100_GPG0(0); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        if (width == 8) {
+                for (gpio = S5PC100_GPG1(0); gpio <= S5PC100_GPG1(1); gpio++) {
+                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+                }
+        }
+        s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2));
+}
+void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+        end = S5PC100_GPG2(2 + width);
+        /* Set all the necessary GPG2 pins to special-function 2 */
+        for (gpio = S5PC100_GPG2(0); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2));
+}
+void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        unsigned int gpio;
+        unsigned int end;
+        end = S5PC100_GPG3(2 + width);
+        /* Set all the necessary GPG3 pins to special-function 2 */
+        for (gpio = S5PC100_GPG3(0); gpio < end; gpio++) {
+                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+        }
+        s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2));
+}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
new file mode 100644
index 000000000000..486a0d6301e7
--- /dev/null
+++ b/arch/arm/plat-samsung/Kconfig
@@ -0,0 +1,17 @@
+# arch/arm/plat-samsung/Kconfig
+#
+# Copyright 2009 Simtec Electronics
+#
+# Licensed under GPLv2
+config PLAT_SAMSUNG
+        bool
+        depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX || ARCH_S5PC1XX
+        default y
+        help
+          Base platform code for all Samsung SoC based systems
+if PLAT_SAMSUNG
+endif
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
new file mode 100644
index 000000000000..4478b9f7dc34
--- /dev/null
+++ b/arch/arm/plat-samsung/Makefile
@@ -0,0 +1,11 @@
+# arch/arm/plat-s3c64xx/Makefile
+#
+# Copyright 2009 Simtec Electronics
+#
+# Licensed under GPLv2
+obj-y                           :=
+obj-m                           :=
+obj-n                           := dummy.o
+obj-                            :=
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index 35e3bd9858df..d856354f4272 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -92,6 +92,7 @@ config PLATFORM_AT32AP
        select PERFORMANCE_COUNTERS
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_ALLOCATOR
+        select HAVE_FB_ATMEL
 #
 # CPU types
diff --git a/drivers/i2c/busses/i2c-pnx.c b/drivers/i2c/busses/i2c-pnx.c
index 6ff6c20f1e78..1fca59077949 100644
--- a/drivers/i2c/busses/i2c-pnx.c
+++ b/drivers/i2c/busses/i2c-pnx.c
@@ -19,7 +19,9 @@
 #include <linux/completion.h>
 #include <linux/platform_device.h>
 #include <linux/i2c-pnx.h>
+#include <linux/io.h>
 #include <mach/hardware.h>
+#include <mach/i2c.h>
 #include <asm/irq.h>
 #include <asm/uaccess.h>
@@ -54,6 +56,9 @@ static inline void i2c_pnx_arm_timer(struct i2c_adapter *adap)
        struct timer_list *timer = &data->mif.timer;
        int expires = I2C_PNX_TIMEOUT / (1000 / HZ);
+        if (expires <= 1)
+                expires = 2;
        del_timer_sync(timer);
        dev_dbg(&adap->dev, "Timer armed at %lu plus %u jiffies.\n",
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 3c20dae43ce2..e11e1cda4ba2 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -780,7 +780,7 @@ config RTC_DRV_TX4939
 config RTC_DRV_MV
        tristate "Marvell SoC RTC"
-        depends on ARCH_KIRKWOOD
+        depends on ARCH_KIRKWOOD || ARCH_DOVE
        help
          If you say yes here you will get support for the in-chip RTC
          that can be found in some of Marvell's SoC devices, such as
diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c
index c99f0821cae3..73f089d3efd6 100644
--- a/drivers/serial/s3c2410.c
+++ b/drivers/serial/s3c2410.c
@@ -2,7 +2,7 @@
 *
 * Driver for Samsung S3C2410 SoC onboard UARTs.
 *
- * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
+ * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
diff --git a/drivers/serial/s3c2412.c b/drivers/serial/s3c2412.c
index 6e057d8809d3..ce75e28e36ef 100644
--- a/drivers/serial/s3c2412.c
+++ b/drivers/serial/s3c2412.c
@@ -2,7 +2,7 @@
 *
 * Driver for Samsung S3C2412 and S3C2413 SoC onboard UARTs.
 *
- * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
+ * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
diff --git a/drivers/serial/s3c2440.c b/drivers/serial/s3c2440.c
index 69ff5d340f04..094cc3904b13 100644
--- a/drivers/serial/s3c2440.c
+++ b/drivers/serial/s3c2440.c
@@ -2,7 +2,7 @@
 *
 * Driver for Samsung S3C2440 and S3C2442 SoC onboard UARTs.
 *
- * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
+ * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
diff --git a/drivers/serial/s3c24a0.c b/drivers/serial/s3c24a0.c
index 26c49e18bdd1..fad6083ca427 100644
--- a/drivers/serial/s3c24a0.c
+++ b/drivers/serial/s3c24a0.c
@@ -6,7 +6,7 @@
 *
 * Author: Sandeep Patil <sandeep.patil@azingo.com>
 *
- * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
+ * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c
index 1523e8d9ae77..52e3df113ec0 100644
--- a/drivers/serial/samsung.c
+++ b/drivers/serial/samsung.c
@@ -2,7 +2,7 @@
 *
 * Driver core for Samsung SoC onboard UARTs.
 *
- * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
+ * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
diff --git a/drivers/serial/samsung.h b/drivers/serial/samsung.h
index d3fe315969f6..1fb22343df42 100644
--- a/drivers/serial/samsung.h
+++ b/drivers/serial/samsung.h
@@ -2,7 +2,7 @@
 *
 * Driver for Samsung SoC onboard UARTs.
 *
- * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
+ * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
 *      http://armlinux.simtec.co.uk/
 *
 * This program is free software; you can redistribute it and/or modify
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 188e1ba3b69f..6b89eb55ed32 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -5,6 +5,9 @@
 menu "Graphics support"
        depends on HAS_IOMEM
+config HAVE_FB_ATMEL
+        bool
 source "drivers/char/agp/Kconfig"
 source "drivers/gpu/vga/Kconfig"
@@ -937,7 +940,7 @@ config FB_S1D13XXX
 config FB_ATMEL
        tristate "AT91/AT32 LCD Controller support"
-        depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9G10 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 || ARCH_AT91CAP9 || AVR32)
+        depends on FB && HAVE_FB_ATMEL
        select FB_CFB_FILLRECT
        select FB_CFB_COPYAREA
        select FB_CFB_IMAGEBLIT
diff --git a/drivers/watchdog/pnx4008_wdt.c b/drivers/watchdog/pnx4008_wdt.c
index f24d04132eda..4d227b152001 100644
--- a/drivers/watchdog/pnx4008_wdt.c
+++ b/drivers/watchdog/pnx4008_wdt.c
@@ -317,7 +317,7 @@ static int __devexit pnx4008_wdt_remove(struct platform_device *pdev)
 static struct platform_driver platform_wdt_driver = {
        .driver = {
-                .name = "watchdog",
+                .name = "pnx4008-watchdog",
                .owner  = THIS_MODULE,
        },
        .probe = pnx4008_wdt_probe,
@@ -352,4 +352,4 @@ MODULE_PARM_DESC(nowayout,
 MODULE_LICENSE("GPL");
 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-MODULE_ALIAS("platform:watchdog");
+MODULE_ALIAS("platform:pnx4008-watchdog");
diff --git a/fs/ocfs2/file.c b/fs/ocfs2/file.c
index 89fc8ee1f5a5..de059f490586 100644
--- a/fs/ocfs2/file.c
+++ b/fs/ocfs2/file.c
@@ -1712,7 +1712,8 @@ int ocfs2_check_range_for_refcount(struct inode *inode, loff_t pos,
        struct super_block *sb = inode->i_sb;
        if (!ocfs2_refcount_tree(OCFS2_SB(inode->i_sb)) ||
-            !(OCFS2_I(inode)->ip_dyn_features & OCFS2_HAS_REFCOUNT_FL))
+            !(OCFS2_I(inode)->ip_dyn_features & OCFS2_HAS_REFCOUNT_FL) ||
+            OCFS2_I(inode)->ip_dyn_features & OCFS2_INLINE_DATA_FL)
                return 0;
        cpos = pos >> OCFS2_SB(sb)->s_clustersize_bits;
diff --git a/fs/ocfs2/ocfs2.h b/fs/ocfs2/ocfs2.h
index eae404602424..d963d8638709 100644
--- a/fs/ocfs2/ocfs2.h
+++ b/fs/ocfs2/ocfs2.h
@@ -35,12 +35,7 @@
 #include <linux/kref.h>
 #include <linux/mutex.h>
 #include <linux/lockdep.h>
-#ifndef CONFIG_OCFS2_COMPAT_JBD
+#include <linux/jbd2.h>
-# include <linux/jbd2.h>
-#else
-# include <linux/jbd.h>
-# include "ocfs2_jbd_compat.h"
-#endif
 /* For union ocfs2_dlm_lksb */
 #include "stackglue.h"
diff --git a/fs/ocfs2/refcounttree.c b/fs/ocfs2/refcounttree.c
index 60287fc56bcb..3a0df7a1b810 100644
--- a/fs/ocfs2/refcounttree.c
+++ b/fs/ocfs2/refcounttree.c
@@ -3743,6 +3743,9 @@ static int ocfs2_attach_refcount_tree(struct inode *inode,
                goto out;
        }
+        if (oi->ip_dyn_features & OCFS2_INLINE_DATA_FL)
+                goto attach_xattr;
        ocfs2_init_dinode_extent_tree(&di_et, INODE_CACHE(inode), di_bh);
        size = i_size_read(inode);
@@ -3769,6 +3772,7 @@ static int ocfs2_attach_refcount_tree(struct inode *inode,
                cpos += num_clusters;
        }
+attach_xattr:
        if (oi->ip_dyn_features & OCFS2_HAS_XATTR_FL) {
                ret = ocfs2_xattr_attach_refcount_tree(inode, di_bh,
                                                       &ref_tree->rf_ci,
@@ -3858,6 +3862,49 @@ out:
        return ret;
 }
+static int ocfs2_duplicate_inline_data(struct inode *s_inode,
+                                       struct buffer_head *s_bh,
+                                       struct inode *t_inode,
+                                       struct buffer_head *t_bh)
+{
+        int ret;
+        handle_t *handle;
+        struct ocfs2_super *osb = OCFS2_SB(s_inode->i_sb);
+        struct ocfs2_dinode *s_di = (struct ocfs2_dinode *)s_bh->b_data;
+        struct ocfs2_dinode *t_di = (struct ocfs2_dinode *)t_bh->b_data;
+        BUG_ON(!(OCFS2_I(s_inode)->ip_dyn_features & OCFS2_INLINE_DATA_FL));
+        handle = ocfs2_start_trans(osb, OCFS2_INODE_UPDATE_CREDITS);
+        if (IS_ERR(handle)) {
+                ret = PTR_ERR(handle);
+                mlog_errno(ret);
+                goto out;
+        }
+        ret = ocfs2_journal_access_di(handle, INODE_CACHE(t_inode), t_bh,
+                                      OCFS2_JOURNAL_ACCESS_WRITE);
+        if (ret) {
+                mlog_errno(ret);
+                goto out_commit;
+        }
+        t_di->id2.i_data.id_count = s_di->id2.i_data.id_count;
+        memcpy(t_di->id2.i_data.id_data, s_di->id2.i_data.id_data,
+               le16_to_cpu(s_di->id2.i_data.id_count));
+        spin_lock(&OCFS2_I(t_inode)->ip_lock);
+        OCFS2_I(t_inode)->ip_dyn_features |= OCFS2_INLINE_DATA_FL;
+        t_di->i_dyn_features = cpu_to_le16(OCFS2_I(t_inode)->ip_dyn_features);
+        spin_unlock(&OCFS2_I(t_inode)->ip_lock);
+        ocfs2_journal_dirty(handle, t_bh);
+out_commit:
+        ocfs2_commit_trans(osb, handle);
+out:
+        return ret;
+}
 static int ocfs2_duplicate_extent_list(struct inode *s_inode,
                                struct inode *t_inode,
                                struct buffer_head *t_bh,
@@ -3997,6 +4044,14 @@ static int ocfs2_create_reflink_node(struct inode *s_inode,
                goto out;
        }
+        if (OCFS2_I(s_inode)->ip_dyn_features & OCFS2_INLINE_DATA_FL) {
+                ret = ocfs2_duplicate_inline_data(s_inode, s_bh,
+                                                  t_inode, t_bh);
+                if (ret)
+                        mlog_errno(ret);
+                goto out;
+        }
        ret = ocfs2_lock_refcount_tree(osb, le64_to_cpu(di->i_refcount_loc),
                                       1, &ref_tree, &ref_root_bh);
        if (ret) {
@@ -4013,10 +4068,6 @@ static int ocfs2_create_reflink_node(struct inode *s_inode,
                goto out_unlock_refcount;
        }
-        ret = ocfs2_complete_reflink(s_inode, s_bh, t_inode, t_bh, preserve);
-        if (ret)
-                mlog_errno(ret);
 out_unlock_refcount:
        ocfs2_unlock_refcount_tree(osb, ref_tree, 1);
        brelse(ref_root_bh);
@@ -4068,9 +4119,17 @@ static int __ocfs2_reflink(struct dentry *old_dentry,
                ret = ocfs2_reflink_xattrs(inode, old_bh,
                                           new_inode, new_bh,
                                           preserve);
-                if (ret)
+                if (ret) {
                        mlog_errno(ret);
+                        goto inode_unlock;
+                }
        }
+        ret = ocfs2_complete_reflink(inode, old_bh,
+                                     new_inode, new_bh, preserve);
+        if (ret)
+                mlog_errno(ret);
 inode_unlock:
        ocfs2_inode_unlock(new_inode, 1);
        brelse(new_bh);
diff --git a/fs/ocfs2/super.c b/fs/ocfs2/super.c
index c0e48aeebb1c..14f47d2bfe02 100644
--- a/fs/ocfs2/super.c
+++ b/fs/ocfs2/super.c
@@ -773,18 +773,20 @@ static int ocfs2_sb_probe(struct super_block *sb,
                if (tmpstat < 0) {
                        status = tmpstat;
                        mlog_errno(status);
-                        goto bail;
+                        break;
                }
                di = (struct ocfs2_dinode *) (*bh)->b_data;
                memset(stats, 0, sizeof(struct ocfs2_blockcheck_stats));
                spin_lock_init(&stats->b_lock);
-                status = ocfs2_verify_volume(di, *bh, blksize, stats);
+                tmpstat = ocfs2_verify_volume(di, *bh, blksize, stats);
-                if (status >= 0)
+                if (tmpstat < 0) {
-                        goto bail;
+                        brelse(*bh);
-                brelse(*bh);
+                        *bh = NULL;
-                *bh = NULL;
+                }
-                if (status != -EAGAIN)
+                if (tmpstat != -EAGAIN) {
+                        status = tmpstat;
                        break;
+                }
        }
 bail:
@@ -1645,6 +1647,10 @@ static int ocfs2_statfs(struct dentry *dentry, struct kstatfs *buf)
        buf->f_bavail = buf->f_bfree;
        buf->f_files = numbits;
        buf->f_ffree = freebits;
+        buf->f_fsid.val[0] = crc32_le(0, osb->uuid_str, OCFS2_VOL_UUID_LEN)
+                                & 0xFFFFFFFFUL;
+        buf->f_fsid.val[1] = crc32_le(0, osb->uuid_str + OCFS2_VOL_UUID_LEN,
+                                OCFS2_VOL_UUID_LEN) & 0xFFFFFFFFUL;
        brelse(bh);
diff --git a/fs/ocfs2/uptodate.c b/fs/ocfs2/uptodate.c
index b6284f235d2f..c61369342a27 100644
--- a/fs/ocfs2/uptodate.c
+++ b/fs/ocfs2/uptodate.c
@@ -53,11 +53,6 @@
 #include <linux/highmem.h>
 #include <linux/buffer_head.h>
 #include <linux/rbtree.h>
-#ifndef CONFIG_OCFS2_COMPAT_JBD
-# include <linux/jbd2.h>
-#else
-# include <linux/jbd.h>
-#endif
 #define MLOG_MASK_PREFIX ML_UPTODATE
diff --git a/include/linux/i2c-pnx.h b/include/linux/i2c-pnx.h
index f13255e06406..9eb07bbc6522 100644
--- a/include/linux/i2c-pnx.h
+++ b/include/linux/i2c-pnx.h
@@ -21,7 +21,7 @@ struct i2c_pnx_mif {
        int                     mode;           /* Interface mode */
        struct completion       complete;       /* I/O completion */
        struct timer_list       timer;          /* Timeout */
-        char *                  buf;            /* Data buffer */
+        u8 *                    buf;            /* Data buffer */
        int                     len;            /* Length of data buffer */
 };