diff options
-rw-r--r-- | drivers/net/ethernet/broadcom/tg3.c | 791 | ||||
-rw-r--r-- | drivers/net/ethernet/broadcom/tg3.h | 18 |
2 files changed, 408 insertions, 401 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index f511e8b6e7f5..fdb9b5655414 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c | |||
@@ -618,7 +618,7 @@ static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |||
618 | { | 618 | { |
619 | unsigned long flags; | 619 | unsigned long flags; |
620 | 620 | ||
621 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && | 621 | if (tg3_asic_rev(tp) == ASIC_REV_5906 && |
622 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) | 622 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) |
623 | return; | 623 | return; |
624 | 624 | ||
@@ -643,7 +643,7 @@ static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) | |||
643 | { | 643 | { |
644 | unsigned long flags; | 644 | unsigned long flags; |
645 | 645 | ||
646 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 && | 646 | if (tg3_asic_rev(tp) == ASIC_REV_5906 && |
647 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { | 647 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { |
648 | *val = 0; | 648 | *val = 0; |
649 | return; | 649 | return; |
@@ -671,7 +671,7 @@ static void tg3_ape_lock_init(struct tg3 *tp) | |||
671 | int i; | 671 | int i; |
672 | u32 regbase, bit; | 672 | u32 regbase, bit; |
673 | 673 | ||
674 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | 674 | if (tg3_asic_rev(tp) == ASIC_REV_5761) |
675 | regbase = TG3_APE_LOCK_GRANT; | 675 | regbase = TG3_APE_LOCK_GRANT; |
676 | else | 676 | else |
677 | regbase = TG3_APE_PER_LOCK_GRANT; | 677 | regbase = TG3_APE_PER_LOCK_GRANT; |
@@ -707,7 +707,7 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum) | |||
707 | 707 | ||
708 | switch (locknum) { | 708 | switch (locknum) { |
709 | case TG3_APE_LOCK_GPIO: | 709 | case TG3_APE_LOCK_GPIO: |
710 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | 710 | if (tg3_asic_rev(tp) == ASIC_REV_5761) |
711 | return 0; | 711 | return 0; |
712 | case TG3_APE_LOCK_GRC: | 712 | case TG3_APE_LOCK_GRC: |
713 | case TG3_APE_LOCK_MEM: | 713 | case TG3_APE_LOCK_MEM: |
@@ -726,7 +726,7 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum) | |||
726 | return -EINVAL; | 726 | return -EINVAL; |
727 | } | 727 | } |
728 | 728 | ||
729 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | 729 | if (tg3_asic_rev(tp) == ASIC_REV_5761) { |
730 | req = TG3_APE_LOCK_REQ; | 730 | req = TG3_APE_LOCK_REQ; |
731 | gnt = TG3_APE_LOCK_GRANT; | 731 | gnt = TG3_APE_LOCK_GRANT; |
732 | } else { | 732 | } else { |
@@ -764,7 +764,7 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |||
764 | 764 | ||
765 | switch (locknum) { | 765 | switch (locknum) { |
766 | case TG3_APE_LOCK_GPIO: | 766 | case TG3_APE_LOCK_GPIO: |
767 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | 767 | if (tg3_asic_rev(tp) == ASIC_REV_5761) |
768 | return; | 768 | return; |
769 | case TG3_APE_LOCK_GRC: | 769 | case TG3_APE_LOCK_GRC: |
770 | case TG3_APE_LOCK_MEM: | 770 | case TG3_APE_LOCK_MEM: |
@@ -783,7 +783,7 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |||
783 | return; | 783 | return; |
784 | } | 784 | } |
785 | 785 | ||
786 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | 786 | if (tg3_asic_rev(tp) == ASIC_REV_5761) |
787 | gnt = TG3_APE_LOCK_GRANT; | 787 | gnt = TG3_APE_LOCK_GRANT; |
788 | else | 788 | else |
789 | gnt = TG3_APE_PER_LOCK_GRANT; | 789 | gnt = TG3_APE_PER_LOCK_GRANT; |
@@ -1479,7 +1479,7 @@ static void tg3_mdio_start(struct tg3 *tp) | |||
1479 | udelay(80); | 1479 | udelay(80); |
1480 | 1480 | ||
1481 | if (tg3_flag(tp, MDIOBUS_INITED) && | 1481 | if (tg3_flag(tp, MDIOBUS_INITED) && |
1482 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | 1482 | tg3_asic_rev(tp) == ASIC_REV_5785) |
1483 | tg3_mdio_config_5785(tp); | 1483 | tg3_mdio_config_5785(tp); |
1484 | } | 1484 | } |
1485 | 1485 | ||
@@ -1494,7 +1494,7 @@ static int tg3_mdio_init(struct tg3 *tp) | |||
1494 | 1494 | ||
1495 | tp->phy_addr = tp->pci_fn + 1; | 1495 | tp->phy_addr = tp->pci_fn + 1; |
1496 | 1496 | ||
1497 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) | 1497 | if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) |
1498 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | 1498 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; |
1499 | else | 1499 | else |
1500 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | 1500 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & |
@@ -1582,7 +1582,7 @@ static int tg3_mdio_init(struct tg3 *tp) | |||
1582 | 1582 | ||
1583 | tg3_flag_set(tp, MDIOBUS_INITED); | 1583 | tg3_flag_set(tp, MDIOBUS_INITED); |
1584 | 1584 | ||
1585 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | 1585 | if (tg3_asic_rev(tp) == ASIC_REV_5785) |
1586 | tg3_mdio_config_5785(tp); | 1586 | tg3_mdio_config_5785(tp); |
1587 | 1587 | ||
1588 | return 0; | 1588 | return 0; |
@@ -1804,7 +1804,7 @@ static int tg3_poll_fw(struct tg3 *tp) | |||
1804 | return 0; | 1804 | return 0; |
1805 | } | 1805 | } |
1806 | 1806 | ||
1807 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 1807 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
1808 | /* Wait up to 20ms for init done. */ | 1808 | /* Wait up to 20ms for init done. */ |
1809 | for (i = 0; i < 200; i++) { | 1809 | for (i = 0; i < 200; i++) { |
1810 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) | 1810 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) |
@@ -1833,7 +1833,7 @@ static int tg3_poll_fw(struct tg3 *tp) | |||
1833 | netdev_info(tp->dev, "No firmware running\n"); | 1833 | netdev_info(tp->dev, "No firmware running\n"); |
1834 | } | 1834 | } |
1835 | 1835 | ||
1836 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | 1836 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { |
1837 | /* The 57765 A0 needs a little more | 1837 | /* The 57765 A0 needs a little more |
1838 | * time to do some important work. | 1838 | * time to do some important work. |
1839 | */ | 1839 | */ |
@@ -1963,7 +1963,7 @@ static void tg3_adjust_link(struct net_device *dev) | |||
1963 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | 1963 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) |
1964 | mac_mode |= MAC_MODE_PORT_MODE_MII; | 1964 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
1965 | else if (phydev->speed == SPEED_1000 || | 1965 | else if (phydev->speed == SPEED_1000 || |
1966 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | 1966 | tg3_asic_rev(tp) != ASIC_REV_5785) |
1967 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | 1967 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
1968 | else | 1968 | else |
1969 | mac_mode |= MAC_MODE_PORT_MODE_MII; | 1969 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
@@ -1990,7 +1990,7 @@ static void tg3_adjust_link(struct net_device *dev) | |||
1990 | udelay(40); | 1990 | udelay(40); |
1991 | } | 1991 | } |
1992 | 1992 | ||
1993 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | 1993 | if (tg3_asic_rev(tp) == ASIC_REV_5785) { |
1994 | if (phydev->speed == SPEED_10) | 1994 | if (phydev->speed == SPEED_10) |
1995 | tw32(MAC_MI_STAT, | 1995 | tw32(MAC_MI_STAT, |
1996 | MAC_MI_STAT_10MBPS_MODE | | 1996 | MAC_MI_STAT_10MBPS_MODE | |
@@ -2182,7 +2182,7 @@ static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) | |||
2182 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | 2182 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | |
2183 | MII_TG3_MISC_SHDW_SCR5_SDTL | | 2183 | MII_TG3_MISC_SHDW_SCR5_SDTL | |
2184 | MII_TG3_MISC_SHDW_SCR5_C125OE; | 2184 | MII_TG3_MISC_SHDW_SCR5_C125OE; |
2185 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | 2185 | if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable) |
2186 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | 2186 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; |
2187 | 2187 | ||
2188 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | 2188 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); |
@@ -2337,8 +2337,8 @@ static void tg3_phy_eee_enable(struct tg3 *tp) | |||
2337 | u32 val; | 2337 | u32 val; |
2338 | 2338 | ||
2339 | if (tp->link_config.active_speed == SPEED_1000 && | 2339 | if (tp->link_config.active_speed == SPEED_1000 && |
2340 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 2340 | (tg3_asic_rev(tp) == ASIC_REV_5717 || |
2341 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | 2341 | tg3_asic_rev(tp) == ASIC_REV_5719 || |
2342 | tg3_flag(tp, 57765_CLASS)) && | 2342 | tg3_flag(tp, 57765_CLASS)) && |
2343 | !tg3_phy_toggle_auxctl_smdsp(tp, true)) { | 2343 | !tg3_phy_toggle_auxctl_smdsp(tp, true)) { |
2344 | val = MII_TG3_DSP_TAP26_ALNOKO | | 2344 | val = MII_TG3_DSP_TAP26_ALNOKO | |
@@ -2542,7 +2542,7 @@ static int tg3_phy_reset(struct tg3 *tp) | |||
2542 | u32 val, cpmuctrl; | 2542 | u32 val, cpmuctrl; |
2543 | int err; | 2543 | int err; |
2544 | 2544 | ||
2545 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 2545 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
2546 | val = tr32(GRC_MISC_CFG); | 2546 | val = tr32(GRC_MISC_CFG); |
2547 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | 2547 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); |
2548 | udelay(40); | 2548 | udelay(40); |
@@ -2557,9 +2557,9 @@ static int tg3_phy_reset(struct tg3 *tp) | |||
2557 | tg3_link_report(tp); | 2557 | tg3_link_report(tp); |
2558 | } | 2558 | } |
2559 | 2559 | ||
2560 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | 2560 | if (tg3_asic_rev(tp) == ASIC_REV_5703 || |
2561 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | 2561 | tg3_asic_rev(tp) == ASIC_REV_5704 || |
2562 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | 2562 | tg3_asic_rev(tp) == ASIC_REV_5705) { |
2563 | err = tg3_phy_reset_5703_4_5(tp); | 2563 | err = tg3_phy_reset_5703_4_5(tp); |
2564 | if (err) | 2564 | if (err) |
2565 | return err; | 2565 | return err; |
@@ -2567,8 +2567,8 @@ static int tg3_phy_reset(struct tg3 *tp) | |||
2567 | } | 2567 | } |
2568 | 2568 | ||
2569 | cpmuctrl = 0; | 2569 | cpmuctrl = 0; |
2570 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | 2570 | if (tg3_asic_rev(tp) == ASIC_REV_5784 && |
2571 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | 2571 | tg3_chip_rev(tp) != CHIPREV_5784_AX) { |
2572 | cpmuctrl = tr32(TG3_CPMU_CTRL); | 2572 | cpmuctrl = tr32(TG3_CPMU_CTRL); |
2573 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | 2573 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) |
2574 | tw32(TG3_CPMU_CTRL, | 2574 | tw32(TG3_CPMU_CTRL, |
@@ -2586,8 +2586,8 @@ static int tg3_phy_reset(struct tg3 *tp) | |||
2586 | tw32(TG3_CPMU_CTRL, cpmuctrl); | 2586 | tw32(TG3_CPMU_CTRL, cpmuctrl); |
2587 | } | 2587 | } |
2588 | 2588 | ||
2589 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || | 2589 | if (tg3_chip_rev(tp) == CHIPREV_5784_AX || |
2590 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | 2590 | tg3_chip_rev(tp) == CHIPREV_5761_AX) { |
2591 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); | 2591 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2592 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | 2592 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == |
2593 | CPMU_LSPD_1000MB_MACCLK_12_5) { | 2593 | CPMU_LSPD_1000MB_MACCLK_12_5) { |
@@ -2665,12 +2665,12 @@ out: | |||
2665 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); | 2665 | val | MII_TG3_EXT_CTRL_FIFO_ELASTIC); |
2666 | } | 2666 | } |
2667 | 2667 | ||
2668 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 2668 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
2669 | /* adjust output voltage */ | 2669 | /* adjust output voltage */ |
2670 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); | 2670 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
2671 | } | 2671 | } |
2672 | 2672 | ||
2673 | if (tp->pci_chip_rev_id == CHIPREV_ID_5762_A0) | 2673 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0) |
2674 | tg3_phydsp_write(tp, 0xffb, 0x4000); | 2674 | tg3_phydsp_write(tp, 0xffb, 0x4000); |
2675 | 2675 | ||
2676 | tg3_phy_toggle_automdix(tp, 1); | 2676 | tg3_phy_toggle_automdix(tp, 1); |
@@ -2698,8 +2698,8 @@ static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) | |||
2698 | { | 2698 | { |
2699 | u32 status, shift; | 2699 | u32 status, shift; |
2700 | 2700 | ||
2701 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 2701 | if (tg3_asic_rev(tp) == ASIC_REV_5717 || |
2702 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | 2702 | tg3_asic_rev(tp) == ASIC_REV_5719) |
2703 | status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); | 2703 | status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); |
2704 | else | 2704 | else |
2705 | status = tr32(TG3_CPMU_DRV_STATUS); | 2705 | status = tr32(TG3_CPMU_DRV_STATUS); |
@@ -2708,8 +2708,8 @@ static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) | |||
2708 | status &= ~(TG3_GPIO_MSG_MASK << shift); | 2708 | status &= ~(TG3_GPIO_MSG_MASK << shift); |
2709 | status |= (newstat << shift); | 2709 | status |= (newstat << shift); |
2710 | 2710 | ||
2711 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 2711 | if (tg3_asic_rev(tp) == ASIC_REV_5717 || |
2712 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | 2712 | tg3_asic_rev(tp) == ASIC_REV_5719) |
2713 | tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); | 2713 | tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); |
2714 | else | 2714 | else |
2715 | tw32(TG3_CPMU_DRV_STATUS, status); | 2715 | tw32(TG3_CPMU_DRV_STATUS, status); |
@@ -2722,9 +2722,9 @@ static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) | |||
2722 | if (!tg3_flag(tp, IS_NIC)) | 2722 | if (!tg3_flag(tp, IS_NIC)) |
2723 | return 0; | 2723 | return 0; |
2724 | 2724 | ||
2725 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 2725 | if (tg3_asic_rev(tp) == ASIC_REV_5717 || |
2726 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | 2726 | tg3_asic_rev(tp) == ASIC_REV_5719 || |
2727 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | 2727 | tg3_asic_rev(tp) == ASIC_REV_5720) { |
2728 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) | 2728 | if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) |
2729 | return -EIO; | 2729 | return -EIO; |
2730 | 2730 | ||
@@ -2747,8 +2747,8 @@ static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) | |||
2747 | u32 grc_local_ctrl; | 2747 | u32 grc_local_ctrl; |
2748 | 2748 | ||
2749 | if (!tg3_flag(tp, IS_NIC) || | 2749 | if (!tg3_flag(tp, IS_NIC) || |
2750 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 2750 | tg3_asic_rev(tp) == ASIC_REV_5700 || |
2751 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) | 2751 | tg3_asic_rev(tp) == ASIC_REV_5701) |
2752 | return; | 2752 | return; |
2753 | 2753 | ||
2754 | grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; | 2754 | grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; |
@@ -2771,8 +2771,8 @@ static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) | |||
2771 | if (!tg3_flag(tp, IS_NIC)) | 2771 | if (!tg3_flag(tp, IS_NIC)) |
2772 | return; | 2772 | return; |
2773 | 2773 | ||
2774 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 2774 | if (tg3_asic_rev(tp) == ASIC_REV_5700 || |
2775 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | 2775 | tg3_asic_rev(tp) == ASIC_REV_5701) { |
2776 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | 2776 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2777 | (GRC_LCLCTRL_GPIO_OE0 | | 2777 | (GRC_LCLCTRL_GPIO_OE0 | |
2778 | GRC_LCLCTRL_GPIO_OE1 | | 2778 | GRC_LCLCTRL_GPIO_OE1 | |
@@ -2804,7 +2804,7 @@ static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) | |||
2804 | u32 grc_local_ctrl = 0; | 2804 | u32 grc_local_ctrl = 0; |
2805 | 2805 | ||
2806 | /* Workaround to prevent overdrawing Amps. */ | 2806 | /* Workaround to prevent overdrawing Amps. */ |
2807 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | 2807 | if (tg3_asic_rev(tp) == ASIC_REV_5714) { |
2808 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | 2808 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; |
2809 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | | 2809 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2810 | grc_local_ctrl, | 2810 | grc_local_ctrl, |
@@ -2876,9 +2876,9 @@ static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) | |||
2876 | if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) | 2876 | if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) |
2877 | return; | 2877 | return; |
2878 | 2878 | ||
2879 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 2879 | if (tg3_asic_rev(tp) == ASIC_REV_5717 || |
2880 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | 2880 | tg3_asic_rev(tp) == ASIC_REV_5719 || |
2881 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | 2881 | tg3_asic_rev(tp) == ASIC_REV_5720) { |
2882 | tg3_frob_aux_power_5717(tp, include_wol ? | 2882 | tg3_frob_aux_power_5717(tp, include_wol ? |
2883 | tg3_flag(tp, WOL_ENABLE) != 0 : 0); | 2883 | tg3_flag(tp, WOL_ENABLE) != 0 : 0); |
2884 | return; | 2884 | return; |
@@ -2930,7 +2930,7 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) | |||
2930 | u32 val; | 2930 | u32 val; |
2931 | 2931 | ||
2932 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { | 2932 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
2933 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | 2933 | if (tg3_asic_rev(tp) == ASIC_REV_5704) { |
2934 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | 2934 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); |
2935 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | 2935 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); |
2936 | 2936 | ||
@@ -2942,7 +2942,7 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) | |||
2942 | return; | 2942 | return; |
2943 | } | 2943 | } |
2944 | 2944 | ||
2945 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 2945 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
2946 | tg3_bmcr_reset(tp); | 2946 | tg3_bmcr_reset(tp); |
2947 | val = tr32(GRC_MISC_CFG); | 2947 | val = tr32(GRC_MISC_CFG); |
2948 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | 2948 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); |
@@ -2981,16 +2981,16 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) | |||
2981 | /* The PHY should not be powered down on some chips because | 2981 | /* The PHY should not be powered down on some chips because |
2982 | * of bugs. | 2982 | * of bugs. |
2983 | */ | 2983 | */ |
2984 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 2984 | if (tg3_asic_rev(tp) == ASIC_REV_5700 || |
2985 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | 2985 | tg3_asic_rev(tp) == ASIC_REV_5704 || |
2986 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | 2986 | (tg3_asic_rev(tp) == ASIC_REV_5780 && |
2987 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) || | 2987 | (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) || |
2988 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && | 2988 | (tg3_asic_rev(tp) == ASIC_REV_5717 && |
2989 | !tp->pci_fn)) | 2989 | !tp->pci_fn)) |
2990 | return; | 2990 | return; |
2991 | 2991 | ||
2992 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || | 2992 | if (tg3_chip_rev(tp) == CHIPREV_5784_AX || |
2993 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | 2993 | tg3_chip_rev(tp) == CHIPREV_5761_AX) { |
2994 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); | 2994 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2995 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | 2995 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; |
2996 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | 2996 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; |
@@ -3373,7 +3373,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |||
3373 | !tg3_flag(tp, 57765_PLUS)) | 3373 | !tg3_flag(tp, 57765_PLUS)) |
3374 | tw32(NVRAM_ADDR, phy_addr); | 3374 | tw32(NVRAM_ADDR, phy_addr); |
3375 | 3375 | ||
3376 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && | 3376 | if (tg3_asic_rev(tp) != ASIC_REV_5752 && |
3377 | !tg3_flag(tp, 5755_PLUS) && | 3377 | !tg3_flag(tp, 5755_PLUS) && |
3378 | (tp->nvram_jedecnum == JEDEC_ST) && | 3378 | (tp->nvram_jedecnum == JEDEC_ST) && |
3379 | (nvram_cmd & NVRAM_CMD_FIRST)) { | 3379 | (nvram_cmd & NVRAM_CMD_FIRST)) { |
@@ -3458,7 +3458,7 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |||
3458 | 3458 | ||
3459 | BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); | 3459 | BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); |
3460 | 3460 | ||
3461 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 3461 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
3462 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | 3462 | u32 val = tr32(GRC_VCPU_EXT_CTRL); |
3463 | 3463 | ||
3464 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | 3464 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); |
@@ -3636,7 +3636,7 @@ static int tg3_load_tso_firmware(struct tg3 *tp) | |||
3636 | info.fw_len = tp->fw->size - 12; | 3636 | info.fw_len = tp->fw->size - 12; |
3637 | info.fw_data = &fw_data[3]; | 3637 | info.fw_data = &fw_data[3]; |
3638 | 3638 | ||
3639 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | 3639 | if (tg3_asic_rev(tp) == ASIC_REV_5705) { |
3640 | cpu_base = RX_CPU_BASE; | 3640 | cpu_base = RX_CPU_BASE; |
3641 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | 3641 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; |
3642 | } else { | 3642 | } else { |
@@ -3694,8 +3694,8 @@ static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |||
3694 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | 3694 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); |
3695 | } | 3695 | } |
3696 | 3696 | ||
3697 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | 3697 | if (tg3_asic_rev(tp) == ASIC_REV_5703 || |
3698 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | 3698 | tg3_asic_rev(tp) == ASIC_REV_5704) { |
3699 | for (i = 0; i < 12; i++) { | 3699 | for (i = 0; i < 12; i++) { |
3700 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | 3700 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); |
3701 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | 3701 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); |
@@ -3814,7 +3814,7 @@ static int tg3_power_down_prepare(struct tg3 *tp) | |||
3814 | tg3_setup_phy(tp, 0); | 3814 | tg3_setup_phy(tp, 0); |
3815 | } | 3815 | } |
3816 | 3816 | ||
3817 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 3817 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
3818 | u32 val; | 3818 | u32 val; |
3819 | 3819 | ||
3820 | val = tr32(GRC_VCPU_EXT_CTRL); | 3820 | val = tr32(GRC_VCPU_EXT_CTRL); |
@@ -3856,8 +3856,7 @@ static int tg3_power_down_prepare(struct tg3 *tp) | |||
3856 | mac_mode = MAC_MODE_PORT_MODE_MII; | 3856 | mac_mode = MAC_MODE_PORT_MODE_MII; |
3857 | 3857 | ||
3858 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; | 3858 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
3859 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | 3859 | if (tg3_asic_rev(tp) == ASIC_REV_5700) { |
3860 | ASIC_REV_5700) { | ||
3861 | u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? | 3860 | u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? |
3862 | SPEED_100 : SPEED_10; | 3861 | SPEED_100 : SPEED_10; |
3863 | if (tg3_5700_link_polarity(tp, speed)) | 3862 | if (tg3_5700_link_polarity(tp, speed)) |
@@ -3890,8 +3889,8 @@ static int tg3_power_down_prepare(struct tg3 *tp) | |||
3890 | } | 3889 | } |
3891 | 3890 | ||
3892 | if (!tg3_flag(tp, WOL_SPEED_100MB) && | 3891 | if (!tg3_flag(tp, WOL_SPEED_100MB) && |
3893 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 3892 | (tg3_asic_rev(tp) == ASIC_REV_5700 || |
3894 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | 3893 | tg3_asic_rev(tp) == ASIC_REV_5701)) { |
3895 | u32 base_val; | 3894 | u32 base_val; |
3896 | 3895 | ||
3897 | base_val = tp->pci_clock_ctrl; | 3896 | base_val = tp->pci_clock_ctrl; |
@@ -3902,13 +3901,13 @@ static int tg3_power_down_prepare(struct tg3 *tp) | |||
3902 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | 3901 | CLOCK_CTRL_PWRDOWN_PLL133, 40); |
3903 | } else if (tg3_flag(tp, 5780_CLASS) || | 3902 | } else if (tg3_flag(tp, 5780_CLASS) || |
3904 | tg3_flag(tp, CPMU_PRESENT) || | 3903 | tg3_flag(tp, CPMU_PRESENT) || |
3905 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 3904 | tg3_asic_rev(tp) == ASIC_REV_5906) { |
3906 | /* do nothing */ | 3905 | /* do nothing */ |
3907 | } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { | 3906 | } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { |
3908 | u32 newbits1, newbits2; | 3907 | u32 newbits1, newbits2; |
3909 | 3908 | ||
3910 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 3909 | if (tg3_asic_rev(tp) == ASIC_REV_5700 || |
3911 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | 3910 | tg3_asic_rev(tp) == ASIC_REV_5701) { |
3912 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | 3911 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | |
3913 | CLOCK_CTRL_TXCLK_DISABLE | | 3912 | CLOCK_CTRL_TXCLK_DISABLE | |
3914 | CLOCK_CTRL_ALTCLK); | 3913 | CLOCK_CTRL_ALTCLK); |
@@ -3930,8 +3929,8 @@ static int tg3_power_down_prepare(struct tg3 *tp) | |||
3930 | if (!tg3_flag(tp, 5705_PLUS)) { | 3929 | if (!tg3_flag(tp, 5705_PLUS)) { |
3931 | u32 newbits3; | 3930 | u32 newbits3; |
3932 | 3931 | ||
3933 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 3932 | if (tg3_asic_rev(tp) == ASIC_REV_5700 || |
3934 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | 3933 | tg3_asic_rev(tp) == ASIC_REV_5701) { |
3935 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | 3934 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | |
3936 | CLOCK_CTRL_TXCLK_DISABLE | | 3935 | CLOCK_CTRL_TXCLK_DISABLE | |
3937 | CLOCK_CTRL_44MHZ_CORE); | 3936 | CLOCK_CTRL_44MHZ_CORE); |
@@ -3951,8 +3950,8 @@ static int tg3_power_down_prepare(struct tg3 *tp) | |||
3951 | 3950 | ||
3952 | /* Workaround for unstable PLL clock */ | 3951 | /* Workaround for unstable PLL clock */ |
3953 | if ((!tg3_flag(tp, IS_SSB_CORE)) && | 3952 | if ((!tg3_flag(tp, IS_SSB_CORE)) && |
3954 | ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | 3953 | ((tg3_chip_rev(tp) == CHIPREV_5750_AX) || |
3955 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX))) { | 3954 | (tg3_chip_rev(tp) == CHIPREV_5750_BX))) { |
3956 | u32 val = tr32(0x7d00); | 3955 | u32 val = tr32(0x7d00); |
3957 | 3956 | ||
3958 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | 3957 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); |
@@ -4043,8 +4042,8 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) | |||
4043 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { | 4042 | if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { |
4044 | new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise); | 4043 | new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise); |
4045 | 4044 | ||
4046 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | 4045 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || |
4047 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | 4046 | tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) |
4048 | new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; | 4047 | new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; |
4049 | 4048 | ||
4050 | err = tg3_writephy(tp, MII_CTRL1000, new_adv); | 4049 | err = tg3_writephy(tp, MII_CTRL1000, new_adv); |
@@ -4073,7 +4072,7 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) | |||
4073 | if (err) | 4072 | if (err) |
4074 | val = 0; | 4073 | val = 0; |
4075 | 4074 | ||
4076 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { | 4075 | switch (tg3_asic_rev(tp)) { |
4077 | case ASIC_REV_5717: | 4076 | case ASIC_REV_5717: |
4078 | case ASIC_REV_57765: | 4077 | case ASIC_REV_57765: |
4079 | case ASIC_REV_57766: | 4078 | case ASIC_REV_57766: |
@@ -4221,8 +4220,8 @@ static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) | |||
4221 | return false; | 4220 | return false; |
4222 | 4221 | ||
4223 | if (tgtadv && | 4222 | if (tgtadv && |
4224 | (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | 4223 | (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || |
4225 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) { | 4224 | tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) { |
4226 | tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; | 4225 | tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER; |
4227 | tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL | | 4226 | tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL | |
4228 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); | 4227 | CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER); |
@@ -4306,9 +4305,9 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | |||
4306 | /* Some third-party PHYs need to be reset on link going | 4305 | /* Some third-party PHYs need to be reset on link going |
4307 | * down. | 4306 | * down. |
4308 | */ | 4307 | */ |
4309 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | 4308 | if ((tg3_asic_rev(tp) == ASIC_REV_5703 || |
4310 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | 4309 | tg3_asic_rev(tp) == ASIC_REV_5704 || |
4311 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | 4310 | tg3_asic_rev(tp) == ASIC_REV_5705) && |
4312 | tp->link_up) { | 4311 | tp->link_up) { |
4313 | tg3_readphy(tp, MII_BMSR, &bmsr); | 4312 | tg3_readphy(tp, MII_BMSR, &bmsr); |
4314 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | 4313 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && |
@@ -4350,8 +4349,8 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | |||
4350 | return err; | 4349 | return err; |
4351 | } | 4350 | } |
4352 | } | 4351 | } |
4353 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | 4352 | } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || |
4354 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | 4353 | tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) { |
4355 | /* 5701 {A0,B0} CRC bug workaround */ | 4354 | /* 5701 {A0,B0} CRC bug workaround */ |
4356 | tg3_writephy(tp, 0x15, 0x0a75); | 4355 | tg3_writephy(tp, 0x15, 0x0a75); |
4357 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); | 4356 | tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); |
@@ -4368,8 +4367,8 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) | |||
4368 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) | 4367 | else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) |
4369 | tg3_writephy(tp, MII_TG3_IMASK, ~0); | 4368 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
4370 | 4369 | ||
4371 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 4370 | if (tg3_asic_rev(tp) == ASIC_REV_5700 || |
4372 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | 4371 | tg3_asic_rev(tp) == ASIC_REV_5701) { |
4373 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | 4372 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) |
4374 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | 4373 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
4375 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | 4374 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); |
@@ -4524,7 +4523,7 @@ relink: | |||
4524 | if (tp->link_config.active_duplex == DUPLEX_HALF) | 4523 | if (tp->link_config.active_duplex == DUPLEX_HALF) |
4525 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | 4524 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; |
4526 | 4525 | ||
4527 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { | 4526 | if (tg3_asic_rev(tp) == ASIC_REV_5700) { |
4528 | if (current_link_up == 1 && | 4527 | if (current_link_up == 1 && |
4529 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | 4528 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) |
4530 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | 4529 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
@@ -4536,7 +4535,7 @@ relink: | |||
4536 | * ??? send/receive packets... | 4535 | * ??? send/receive packets... |
4537 | */ | 4536 | */ |
4538 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && | 4537 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
4539 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { | 4538 | tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) { |
4540 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | 4539 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; |
4541 | tw32_f(MAC_MI_MODE, tp->mi_mode); | 4540 | tw32_f(MAC_MI_MODE, tp->mi_mode); |
4542 | udelay(80); | 4541 | udelay(80); |
@@ -4555,7 +4554,7 @@ relink: | |||
4555 | } | 4554 | } |
4556 | udelay(40); | 4555 | udelay(40); |
4557 | 4556 | ||
4558 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | 4557 | if (tg3_asic_rev(tp) == ASIC_REV_5700 && |
4559 | current_link_up == 1 && | 4558 | current_link_up == 1 && |
4560 | tp->link_config.active_speed == SPEED_1000 && | 4559 | tp->link_config.active_speed == SPEED_1000 && |
4561 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { | 4560 | (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { |
@@ -5010,8 +5009,8 @@ static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |||
5010 | port_a = 1; | 5009 | port_a = 1; |
5011 | current_link_up = 0; | 5010 | current_link_up = 0; |
5012 | 5011 | ||
5013 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | 5012 | if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 && |
5014 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | 5013 | tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) { |
5015 | workaround = 1; | 5014 | workaround = 1; |
5016 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | 5015 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
5017 | port_a = 0; | 5016 | port_a = 0; |
@@ -5340,7 +5339,7 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) | |||
5340 | 5339 | ||
5341 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | 5340 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); |
5342 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | 5341 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); |
5343 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | 5342 | if (tg3_asic_rev(tp) == ASIC_REV_5714) { |
5344 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | 5343 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) |
5345 | bmsr |= BMSR_LSTATUS; | 5344 | bmsr |= BMSR_LSTATUS; |
5346 | else | 5345 | else |
@@ -5409,8 +5408,7 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) | |||
5409 | bmcr = new_bmcr; | 5408 | bmcr = new_bmcr; |
5410 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | 5409 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); |
5411 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | 5410 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); |
5412 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | 5411 | if (tg3_asic_rev(tp) == ASIC_REV_5714) { |
5413 | ASIC_REV_5714) { | ||
5414 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | 5412 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) |
5415 | bmsr |= BMSR_LSTATUS; | 5413 | bmsr |= BMSR_LSTATUS; |
5416 | else | 5414 | else |
@@ -5545,7 +5543,7 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset) | |||
5545 | else | 5543 | else |
5546 | err = tg3_setup_copper_phy(tp, force_reset); | 5544 | err = tg3_setup_copper_phy(tp, force_reset); |
5547 | 5545 | ||
5548 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { | 5546 | if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { |
5549 | u32 scale; | 5547 | u32 scale; |
5550 | 5548 | ||
5551 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | 5549 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; |
@@ -5563,8 +5561,8 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset) | |||
5563 | 5561 | ||
5564 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | | 5562 | val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) | |
5565 | (6 << TX_LENGTHS_IPG_SHIFT); | 5563 | (6 << TX_LENGTHS_IPG_SHIFT); |
5566 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | 5564 | if (tg3_asic_rev(tp) == ASIC_REV_5720 || |
5567 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 5565 | tg3_asic_rev(tp) == ASIC_REV_5762) |
5568 | val |= tr32(MAC_TX_LENGTHS) & | 5566 | val |= tr32(MAC_TX_LENGTHS) & |
5569 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | 5567 | (TX_LENGTHS_JMB_FRM_LEN_MSK | |
5570 | TX_LENGTHS_CNT_DWN_VAL_MSK); | 5568 | TX_LENGTHS_CNT_DWN_VAL_MSK); |
@@ -7188,7 +7186,7 @@ static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, | |||
7188 | dma_addr_t new_addr = 0; | 7186 | dma_addr_t new_addr = 0; |
7189 | int ret = 0; | 7187 | int ret = 0; |
7190 | 7188 | ||
7191 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | 7189 | if (tg3_asic_rev(tp) != ASIC_REV_5701) |
7192 | new_skb = skb_copy(skb, GFP_ATOMIC); | 7190 | new_skb = skb_copy(skb, GFP_ATOMIC); |
7193 | else { | 7191 | else { |
7194 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | 7192 | int more_headroom = 4 - ((unsigned long)skb->data & 3); |
@@ -7362,7 +7360,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
7362 | } else if (tg3_flag(tp, HW_TSO_2)) | 7360 | } else if (tg3_flag(tp, HW_TSO_2)) |
7363 | mss |= hdr_len << 9; | 7361 | mss |= hdr_len << 9; |
7364 | else if (tg3_flag(tp, HW_TSO_1) || | 7362 | else if (tg3_flag(tp, HW_TSO_1) || |
7365 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | 7363 | tg3_asic_rev(tp) == ASIC_REV_5705) { |
7366 | if (tcp_opt_len || iph->ihl > 5) { | 7364 | if (tcp_opt_len || iph->ihl > 5) { |
7367 | int tsflags; | 7365 | int tsflags; |
7368 | 7366 | ||
@@ -7518,7 +7516,7 @@ static void tg3_mac_loopback(struct tg3 *tp, bool enable) | |||
7518 | 7516 | ||
7519 | if (tg3_flag(tp, 5705_PLUS) || | 7517 | if (tg3_flag(tp, 5705_PLUS) || |
7520 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || | 7518 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || |
7521 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | 7519 | tg3_asic_rev(tp) == ASIC_REV_5700) |
7522 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | 7520 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; |
7523 | } | 7521 | } |
7524 | 7522 | ||
@@ -7577,7 +7575,7 @@ static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) | |||
7577 | udelay(40); | 7575 | udelay(40); |
7578 | 7576 | ||
7579 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && | 7577 | if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && |
7580 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | 7578 | tg3_asic_rev(tp) == ASIC_REV_5785) { |
7581 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | | 7579 | tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | |
7582 | MII_TG3_FET_PTEST_FRC_TX_LINK | | 7580 | MII_TG3_FET_PTEST_FRC_TX_LINK | |
7583 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | 7581 | MII_TG3_FET_PTEST_FRC_TX_LOCK); |
@@ -7601,7 +7599,7 @@ static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) | |||
7601 | else | 7599 | else |
7602 | mac_mode |= MAC_MODE_PORT_MODE_MII; | 7600 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
7603 | 7601 | ||
7604 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { | 7602 | if (tg3_asic_rev(tp) == ASIC_REV_5700) { |
7605 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; | 7603 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; |
7606 | 7604 | ||
7607 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | 7605 | if (masked_phy_id == TG3_PHY_ID_BCM5401) |
@@ -8279,7 +8277,7 @@ static void tg3_restore_pci_state(struct tg3 *tp) | |||
8279 | 8277 | ||
8280 | /* Set MAX PCI retry to zero. */ | 8278 | /* Set MAX PCI retry to zero. */ |
8281 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | 8279 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); |
8282 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | 8280 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && |
8283 | tg3_flag(tp, PCIX_MODE)) | 8281 | tg3_flag(tp, PCIX_MODE)) |
8284 | val |= PCISTATE_RETRY_SAME_DMA; | 8282 | val |= PCISTATE_RETRY_SAME_DMA; |
8285 | /* Allow reads and writes to the APE register and memory space. */ | 8283 | /* Allow reads and writes to the APE register and memory space. */ |
@@ -8351,7 +8349,7 @@ static int tg3_chip_reset(struct tg3 *tp) | |||
8351 | */ | 8349 | */ |
8352 | tg3_save_pci_state(tp); | 8350 | tg3_save_pci_state(tp); |
8353 | 8351 | ||
8354 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | 8352 | if (tg3_asic_rev(tp) == ASIC_REV_5752 || |
8355 | tg3_flag(tp, 5755_PLUS)) | 8353 | tg3_flag(tp, 5755_PLUS)) |
8356 | tw32(GRC_FASTBOOT_PC, 0); | 8354 | tw32(GRC_FASTBOOT_PC, 0); |
8357 | 8355 | ||
@@ -8386,7 +8384,7 @@ static int tg3_chip_reset(struct tg3 *tp) | |||
8386 | for (i = 0; i < tp->irq_cnt; i++) | 8384 | for (i = 0; i < tp->irq_cnt; i++) |
8387 | synchronize_irq(tp->napi[i].irq_vec); | 8385 | synchronize_irq(tp->napi[i].irq_vec); |
8388 | 8386 | ||
8389 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | 8387 | if (tg3_asic_rev(tp) == ASIC_REV_57780) { |
8390 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | 8388 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
8391 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | 8389 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); |
8392 | } | 8390 | } |
@@ -8396,19 +8394,19 @@ static int tg3_chip_reset(struct tg3 *tp) | |||
8396 | 8394 | ||
8397 | if (tg3_flag(tp, PCI_EXPRESS)) { | 8395 | if (tg3_flag(tp, PCI_EXPRESS)) { |
8398 | /* Force PCIe 1.0a mode */ | 8396 | /* Force PCIe 1.0a mode */ |
8399 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | 8397 | if (tg3_asic_rev(tp) != ASIC_REV_5785 && |
8400 | !tg3_flag(tp, 57765_PLUS) && | 8398 | !tg3_flag(tp, 57765_PLUS) && |
8401 | tr32(TG3_PCIE_PHY_TSTCTL) == | 8399 | tr32(TG3_PCIE_PHY_TSTCTL) == |
8402 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) | 8400 | (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM)) |
8403 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); | 8401 | tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM); |
8404 | 8402 | ||
8405 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { | 8403 | if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) { |
8406 | tw32(GRC_MISC_CFG, (1 << 29)); | 8404 | tw32(GRC_MISC_CFG, (1 << 29)); |
8407 | val |= (1 << 29); | 8405 | val |= (1 << 29); |
8408 | } | 8406 | } |
8409 | } | 8407 | } |
8410 | 8408 | ||
8411 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 8409 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
8412 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | 8410 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); |
8413 | tw32(GRC_VCPU_EXT_CTRL, | 8411 | tw32(GRC_VCPU_EXT_CTRL, |
8414 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | 8412 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); |
@@ -8451,7 +8449,7 @@ static int tg3_chip_reset(struct tg3 *tp) | |||
8451 | if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { | 8449 | if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { |
8452 | u16 val16; | 8450 | u16 val16; |
8453 | 8451 | ||
8454 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { | 8452 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) { |
8455 | int j; | 8453 | int j; |
8456 | u32 cfg_val; | 8454 | u32 cfg_val; |
8457 | 8455 | ||
@@ -8492,7 +8490,7 @@ static int tg3_chip_reset(struct tg3 *tp) | |||
8492 | val = tr32(MEMARB_MODE); | 8490 | val = tr32(MEMARB_MODE); |
8493 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | 8491 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
8494 | 8492 | ||
8495 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | 8493 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) { |
8496 | tg3_stop_fw(tp); | 8494 | tg3_stop_fw(tp); |
8497 | tw32(0x5000, 0x400); | 8495 | tw32(0x5000, 0x400); |
8498 | } | 8496 | } |
@@ -8509,16 +8507,16 @@ static int tg3_chip_reset(struct tg3 *tp) | |||
8509 | 8507 | ||
8510 | tw32(GRC_MODE, tp->grc_mode); | 8508 | tw32(GRC_MODE, tp->grc_mode); |
8511 | 8509 | ||
8512 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | 8510 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) { |
8513 | val = tr32(0xc4); | 8511 | val = tr32(0xc4); |
8514 | 8512 | ||
8515 | tw32(0xc4, val | (1 << 15)); | 8513 | tw32(0xc4, val | (1 << 15)); |
8516 | } | 8514 | } |
8517 | 8515 | ||
8518 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | 8516 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && |
8519 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | 8517 | tg3_asic_rev(tp) == ASIC_REV_5705) { |
8520 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | 8518 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; |
8521 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | 8519 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) |
8522 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | 8520 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; |
8523 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | 8521 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); |
8524 | } | 8522 | } |
@@ -8544,15 +8542,15 @@ static int tg3_chip_reset(struct tg3 *tp) | |||
8544 | tg3_mdio_start(tp); | 8542 | tg3_mdio_start(tp); |
8545 | 8543 | ||
8546 | if (tg3_flag(tp, PCI_EXPRESS) && | 8544 | if (tg3_flag(tp, PCI_EXPRESS) && |
8547 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | 8545 | tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && |
8548 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | 8546 | tg3_asic_rev(tp) != ASIC_REV_5785 && |
8549 | !tg3_flag(tp, 57765_PLUS)) { | 8547 | !tg3_flag(tp, 57765_PLUS)) { |
8550 | val = tr32(0x7c00); | 8548 | val = tr32(0x7c00); |
8551 | 8549 | ||
8552 | tw32(0x7c00, val | (1 << 25)); | 8550 | tw32(0x7c00, val | (1 << 25)); |
8553 | } | 8551 | } |
8554 | 8552 | ||
8555 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | 8553 | if (tg3_asic_rev(tp) == ASIC_REV_5720) { |
8556 | val = tr32(TG3_CPMU_CLCK_ORIDE); | 8554 | val = tr32(TG3_CPMU_CLCK_ORIDE); |
8557 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); | 8555 | tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN); |
8558 | } | 8556 | } |
@@ -8764,7 +8762,7 @@ static void tg3_rings_reset(struct tg3 *tp) | |||
8764 | else if (tg3_flag(tp, 5717_PLUS)) | 8762 | else if (tg3_flag(tp, 5717_PLUS)) |
8765 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; | 8763 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; |
8766 | else if (tg3_flag(tp, 57765_CLASS) || | 8764 | else if (tg3_flag(tp, 57765_CLASS) || |
8767 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 8765 | tg3_asic_rev(tp) == ASIC_REV_5762) |
8768 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; | 8766 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; |
8769 | else | 8767 | else |
8770 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | 8768 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; |
@@ -8780,8 +8778,8 @@ static void tg3_rings_reset(struct tg3 *tp) | |||
8780 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; | 8778 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; |
8781 | else if (!tg3_flag(tp, 5705_PLUS)) | 8779 | else if (!tg3_flag(tp, 5705_PLUS)) |
8782 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; | 8780 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
8783 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | 8781 | else if (tg3_asic_rev(tp) == ASIC_REV_5755 || |
8784 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762 || | 8782 | tg3_asic_rev(tp) == ASIC_REV_5762 || |
8785 | tg3_flag(tp, 57765_CLASS)) | 8783 | tg3_flag(tp, 57765_CLASS)) |
8786 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; | 8784 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
8787 | else | 8785 | else |
@@ -8887,12 +8885,12 @@ static void tg3_setup_rxbd_thresholds(struct tg3 *tp) | |||
8887 | 8885 | ||
8888 | if (!tg3_flag(tp, 5750_PLUS) || | 8886 | if (!tg3_flag(tp, 5750_PLUS) || |
8889 | tg3_flag(tp, 5780_CLASS) || | 8887 | tg3_flag(tp, 5780_CLASS) || |
8890 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | 8888 | tg3_asic_rev(tp) == ASIC_REV_5750 || |
8891 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | 8889 | tg3_asic_rev(tp) == ASIC_REV_5752 || |
8892 | tg3_flag(tp, 57765_PLUS)) | 8890 | tg3_flag(tp, 57765_PLUS)) |
8893 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; | 8891 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700; |
8894 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | 8892 | else if (tg3_asic_rev(tp) == ASIC_REV_5755 || |
8895 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) | 8893 | tg3_asic_rev(tp) == ASIC_REV_5787) |
8896 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; | 8894 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755; |
8897 | else | 8895 | else |
8898 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; | 8896 | bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906; |
@@ -9074,7 +9072,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9074 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { | 9072 | if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) { |
9075 | val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | | 9073 | val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 | |
9076 | TG3_CPMU_EEE_LNKIDL_UART_IDL; | 9074 | TG3_CPMU_EEE_LNKIDL_UART_IDL; |
9077 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) | 9075 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) |
9078 | val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT; | 9076 | val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT; |
9079 | 9077 | ||
9080 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val); | 9078 | tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val); |
@@ -9087,7 +9085,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9087 | TG3_CPMU_EEEMD_LPI_IN_RX | | 9085 | TG3_CPMU_EEEMD_LPI_IN_RX | |
9088 | TG3_CPMU_EEEMD_EEE_ENABLE; | 9086 | TG3_CPMU_EEEMD_EEE_ENABLE; |
9089 | 9087 | ||
9090 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) | 9088 | if (tg3_asic_rev(tp) != ASIC_REV_5717) |
9091 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; | 9089 | val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN; |
9092 | 9090 | ||
9093 | if (tg3_flag(tp, ENABLE_APE)) | 9091 | if (tg3_flag(tp, ENABLE_APE)) |
@@ -9113,7 +9111,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9113 | 9111 | ||
9114 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | 9112 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); |
9115 | 9113 | ||
9116 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { | 9114 | if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { |
9117 | val = tr32(TG3_CPMU_CTRL); | 9115 | val = tr32(TG3_CPMU_CTRL); |
9118 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | 9116 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); |
9119 | tw32(TG3_CPMU_CTRL, val); | 9117 | tw32(TG3_CPMU_CTRL, val); |
@@ -9134,7 +9132,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9134 | tw32(TG3_CPMU_HST_ACC, val); | 9132 | tw32(TG3_CPMU_HST_ACC, val); |
9135 | } | 9133 | } |
9136 | 9134 | ||
9137 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | 9135 | if (tg3_asic_rev(tp) == ASIC_REV_57780) { |
9138 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | 9136 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; |
9139 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | 9137 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | |
9140 | PCIE_PWR_MGMT_L1_THRESH_4MS; | 9138 | PCIE_PWR_MGMT_L1_THRESH_4MS; |
@@ -9164,7 +9162,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9164 | } | 9162 | } |
9165 | 9163 | ||
9166 | if (tg3_flag(tp, 57765_CLASS)) { | 9164 | if (tg3_flag(tp, 57765_CLASS)) { |
9167 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | 9165 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { |
9168 | u32 grc_mode = tr32(GRC_MODE); | 9166 | u32 grc_mode = tr32(GRC_MODE); |
9169 | 9167 | ||
9170 | /* Access the lower 1K of PL PCIE block registers. */ | 9168 | /* Access the lower 1K of PL PCIE block registers. */ |
@@ -9179,7 +9177,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9179 | tw32(GRC_MODE, grc_mode); | 9177 | tw32(GRC_MODE, grc_mode); |
9180 | } | 9178 | } |
9181 | 9179 | ||
9182 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) { | 9180 | if (tg3_chip_rev(tp) != CHIPREV_57765_AX) { |
9183 | u32 grc_mode; | 9181 | u32 grc_mode; |
9184 | 9182 | ||
9185 | /* Fix transmit hangs */ | 9183 | /* Fix transmit hangs */ |
@@ -9219,7 +9217,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9219 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | 9217 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); |
9220 | } | 9218 | } |
9221 | 9219 | ||
9222 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | 9220 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && |
9223 | tg3_flag(tp, PCIX_MODE)) { | 9221 | tg3_flag(tp, PCIX_MODE)) { |
9224 | val = tr32(TG3PCI_PCISTATE); | 9222 | val = tr32(TG3PCI_PCISTATE); |
9225 | val |= PCISTATE_RETRY_SAME_DMA; | 9223 | val |= PCISTATE_RETRY_SAME_DMA; |
@@ -9237,7 +9235,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9237 | tw32(TG3PCI_PCISTATE, val); | 9235 | tw32(TG3PCI_PCISTATE, val); |
9238 | } | 9236 | } |
9239 | 9237 | ||
9240 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { | 9238 | if (tg3_chip_rev(tp) == CHIPREV_5704_BX) { |
9241 | /* Enable some hw fixes. */ | 9239 | /* Enable some hw fixes. */ |
9242 | val = tr32(TG3PCI_MSI_DATA); | 9240 | val = tr32(TG3PCI_MSI_DATA); |
9243 | val |= (1 << 26) | (1 << 28) | (1 << 29); | 9241 | val |= (1 << 26) | (1 << 28) | (1 << 29); |
@@ -9256,15 +9254,15 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9256 | if (tg3_flag(tp, 57765_PLUS)) { | 9254 | if (tg3_flag(tp, 57765_PLUS)) { |
9257 | val = tr32(TG3PCI_DMA_RW_CTRL) & | 9255 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
9258 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | 9256 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
9259 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) | 9257 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) |
9260 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | 9258 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; |
9261 | if (!tg3_flag(tp, 57765_CLASS) && | 9259 | if (!tg3_flag(tp, 57765_CLASS) && |
9262 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | 9260 | tg3_asic_rev(tp) != ASIC_REV_5717 && |
9263 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5762) | 9261 | tg3_asic_rev(tp) != ASIC_REV_5762) |
9264 | val |= DMA_RWCTRL_TAGGED_STAT_WA; | 9262 | val |= DMA_RWCTRL_TAGGED_STAT_WA; |
9265 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); | 9263 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
9266 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | 9264 | } else if (tg3_asic_rev(tp) != ASIC_REV_5784 && |
9267 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | 9265 | tg3_asic_rev(tp) != ASIC_REV_5761) { |
9268 | /* This value is determined during the probe time DMA | 9266 | /* This value is determined during the probe time DMA |
9269 | * engine test, tg3_test_dma. | 9267 | * engine test, tg3_test_dma. |
9270 | */ | 9268 | */ |
@@ -9304,9 +9302,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9304 | /* Initialize MBUF/DESC pool. */ | 9302 | /* Initialize MBUF/DESC pool. */ |
9305 | if (tg3_flag(tp, 5750_PLUS)) { | 9303 | if (tg3_flag(tp, 5750_PLUS)) { |
9306 | /* Do nothing. */ | 9304 | /* Do nothing. */ |
9307 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | 9305 | } else if (tg3_asic_rev(tp) != ASIC_REV_5705) { |
9308 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | 9306 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); |
9309 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | 9307 | if (tg3_asic_rev(tp) == ASIC_REV_5704) |
9310 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | 9308 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); |
9311 | else | 9309 | else |
9312 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | 9310 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); |
@@ -9344,11 +9342,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9344 | tp->bufmgr_config.dma_high_water); | 9342 | tp->bufmgr_config.dma_high_water); |
9345 | 9343 | ||
9346 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; | 9344 | val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE; |
9347 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | 9345 | if (tg3_asic_rev(tp) == ASIC_REV_5719) |
9348 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; | 9346 | val |= BUFMGR_MODE_NO_TX_UNDERRUN; |
9349 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 9347 | if (tg3_asic_rev(tp) == ASIC_REV_5717 || |
9350 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | 9348 | tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || |
9351 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) | 9349 | tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) |
9352 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; | 9350 | val |= BUFMGR_MODE_MBLOW_ATTN_ENAB; |
9353 | tw32(BUFMGR_MODE, val); | 9351 | tw32(BUFMGR_MODE, val); |
9354 | for (i = 0; i < 2000; i++) { | 9352 | for (i = 0; i < 2000; i++) { |
@@ -9361,7 +9359,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9361 | return -ENODEV; | 9359 | return -ENODEV; |
9362 | } | 9360 | } |
9363 | 9361 | ||
9364 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) | 9362 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1) |
9365 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | 9363 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); |
9366 | 9364 | ||
9367 | tg3_setup_rxbd_thresholds(tp); | 9365 | tg3_setup_rxbd_thresholds(tp); |
@@ -9399,7 +9397,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9399 | /* Program the jumbo buffer descriptor ring control | 9397 | /* Program the jumbo buffer descriptor ring control |
9400 | * blocks on those devices that have them. | 9398 | * blocks on those devices that have them. |
9401 | */ | 9399 | */ |
9402 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | 9400 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || |
9403 | (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { | 9401 | (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { |
9404 | 9402 | ||
9405 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) { | 9403 | if (tg3_flag(tp, JUMBO_RING_ENABLE)) { |
@@ -9413,7 +9411,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9413 | val | BDINFO_FLAGS_USE_EXT_RECV); | 9411 | val | BDINFO_FLAGS_USE_EXT_RECV); |
9414 | if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || | 9412 | if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || |
9415 | tg3_flag(tp, 57765_CLASS) || | 9413 | tg3_flag(tp, 57765_CLASS) || |
9416 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 9414 | tg3_asic_rev(tp) == ASIC_REV_5762) |
9417 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, | 9415 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
9418 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | 9416 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); |
9419 | } else { | 9417 | } else { |
@@ -9455,8 +9453,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9455 | (6 << TX_LENGTHS_IPG_SHIFT) | | 9453 | (6 << TX_LENGTHS_IPG_SHIFT) | |
9456 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); | 9454 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT); |
9457 | 9455 | ||
9458 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | 9456 | if (tg3_asic_rev(tp) == ASIC_REV_5720 || |
9459 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 9457 | tg3_asic_rev(tp) == ASIC_REV_5762) |
9460 | val |= tr32(MAC_TX_LENGTHS) & | 9458 | val |= tr32(MAC_TX_LENGTHS) & |
9461 | (TX_LENGTHS_JMB_FRM_LEN_MSK | | 9459 | (TX_LENGTHS_JMB_FRM_LEN_MSK | |
9462 | TX_LENGTHS_CNT_DWN_VAL_MSK); | 9460 | TX_LENGTHS_CNT_DWN_VAL_MSK); |
@@ -9476,20 +9474,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9476 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | 9474 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | |
9477 | RDMAC_MODE_LNGREAD_ENAB); | 9475 | RDMAC_MODE_LNGREAD_ENAB); |
9478 | 9476 | ||
9479 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | 9477 | if (tg3_asic_rev(tp) == ASIC_REV_5717) |
9480 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; | 9478 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; |
9481 | 9479 | ||
9482 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | 9480 | if (tg3_asic_rev(tp) == ASIC_REV_5784 || |
9483 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | 9481 | tg3_asic_rev(tp) == ASIC_REV_5785 || |
9484 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | 9482 | tg3_asic_rev(tp) == ASIC_REV_57780) |
9485 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | | 9483 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
9486 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | 9484 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | |
9487 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | 9485 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; |
9488 | 9486 | ||
9489 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | 9487 | if (tg3_asic_rev(tp) == ASIC_REV_5705 && |
9490 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | 9488 | tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { |
9491 | if (tg3_flag(tp, TSO_CAPABLE) && | 9489 | if (tg3_flag(tp, TSO_CAPABLE) && |
9492 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | 9490 | tg3_asic_rev(tp) == ASIC_REV_5705) { |
9493 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; | 9491 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
9494 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | 9492 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && |
9495 | !tg3_flag(tp, IS_5788)) { | 9493 | !tg3_flag(tp, IS_5788)) { |
@@ -9500,7 +9498,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9500 | if (tg3_flag(tp, PCI_EXPRESS)) | 9498 | if (tg3_flag(tp, PCI_EXPRESS)) |
9501 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | 9499 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; |
9502 | 9500 | ||
9503 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) { | 9501 | if (tg3_asic_rev(tp) == ASIC_REV_57766) { |
9504 | tp->dma_limit = 0; | 9502 | tp->dma_limit = 0; |
9505 | if (tp->dev->mtu <= ETH_DATA_LEN) { | 9503 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
9506 | rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR; | 9504 | rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR; |
@@ -9514,29 +9512,29 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9514 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; | 9512 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
9515 | 9513 | ||
9516 | if (tg3_flag(tp, 57765_PLUS) || | 9514 | if (tg3_flag(tp, 57765_PLUS) || |
9517 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | 9515 | tg3_asic_rev(tp) == ASIC_REV_5785 || |
9518 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | 9516 | tg3_asic_rev(tp) == ASIC_REV_57780) |
9519 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | 9517 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; |
9520 | 9518 | ||
9521 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | 9519 | if (tg3_asic_rev(tp) == ASIC_REV_5720 || |
9522 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 9520 | tg3_asic_rev(tp) == ASIC_REV_5762) |
9523 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; | 9521 | rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET; |
9524 | 9522 | ||
9525 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | 9523 | if (tg3_asic_rev(tp) == ASIC_REV_5761 || |
9526 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | 9524 | tg3_asic_rev(tp) == ASIC_REV_5784 || |
9527 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | 9525 | tg3_asic_rev(tp) == ASIC_REV_5785 || |
9528 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | 9526 | tg3_asic_rev(tp) == ASIC_REV_57780 || |
9529 | tg3_flag(tp, 57765_PLUS)) { | 9527 | tg3_flag(tp, 57765_PLUS)) { |
9530 | u32 tgtreg; | 9528 | u32 tgtreg; |
9531 | 9529 | ||
9532 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 9530 | if (tg3_asic_rev(tp) == ASIC_REV_5762) |
9533 | tgtreg = TG3_RDMA_RSRVCTRL_REG2; | 9531 | tgtreg = TG3_RDMA_RSRVCTRL_REG2; |
9534 | else | 9532 | else |
9535 | tgtreg = TG3_RDMA_RSRVCTRL_REG; | 9533 | tgtreg = TG3_RDMA_RSRVCTRL_REG; |
9536 | 9534 | ||
9537 | val = tr32(tgtreg); | 9535 | val = tr32(tgtreg); |
9538 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | 9536 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || |
9539 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) { | 9537 | tg3_asic_rev(tp) == ASIC_REV_5762) { |
9540 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | | 9538 | val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK | |
9541 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | | 9539 | TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK | |
9542 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); | 9540 | TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK); |
@@ -9547,12 +9545,12 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9547 | tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); | 9545 | tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); |
9548 | } | 9546 | } |
9549 | 9547 | ||
9550 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | 9548 | if (tg3_asic_rev(tp) == ASIC_REV_5719 || |
9551 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | 9549 | tg3_asic_rev(tp) == ASIC_REV_5720 || |
9552 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) { | 9550 | tg3_asic_rev(tp) == ASIC_REV_5762) { |
9553 | u32 tgtreg; | 9551 | u32 tgtreg; |
9554 | 9552 | ||
9555 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 9553 | if (tg3_asic_rev(tp) == ASIC_REV_5762) |
9556 | tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2; | 9554 | tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2; |
9557 | else | 9555 | else |
9558 | tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL; | 9556 | tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL; |
@@ -9635,7 +9633,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9635 | tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | 9633 | tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; |
9636 | if (!tg3_flag(tp, 5705_PLUS) && | 9634 | if (!tg3_flag(tp, 5705_PLUS) && |
9637 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && | 9635 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
9638 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) | 9636 | tg3_asic_rev(tp) != ASIC_REV_5700) |
9639 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | 9637 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
9640 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); | 9638 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
9641 | udelay(40); | 9639 | udelay(40); |
@@ -9653,11 +9651,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9653 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | 9651 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | |
9654 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | 9652 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; |
9655 | 9653 | ||
9656 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | 9654 | if (tg3_asic_rev(tp) == ASIC_REV_5752) |
9657 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | 9655 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | |
9658 | GRC_LCLCTRL_GPIO_OUTPUT3; | 9656 | GRC_LCLCTRL_GPIO_OUTPUT3; |
9659 | 9657 | ||
9660 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | 9658 | if (tg3_asic_rev(tp) == ASIC_REV_5755) |
9661 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | 9659 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; |
9662 | 9660 | ||
9663 | tp->grc_local_ctrl &= ~gpio_mask; | 9661 | tp->grc_local_ctrl &= ~gpio_mask; |
@@ -9692,11 +9690,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9692 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | 9690 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | |
9693 | WDMAC_MODE_LNGREAD_ENAB); | 9691 | WDMAC_MODE_LNGREAD_ENAB); |
9694 | 9692 | ||
9695 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | 9693 | if (tg3_asic_rev(tp) == ASIC_REV_5705 && |
9696 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | 9694 | tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { |
9697 | if (tg3_flag(tp, TSO_CAPABLE) && | 9695 | if (tg3_flag(tp, TSO_CAPABLE) && |
9698 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || | 9696 | (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 || |
9699 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | 9697 | tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) { |
9700 | /* nothing */ | 9698 | /* nothing */ |
9701 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | 9699 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && |
9702 | !tg3_flag(tp, IS_5788)) { | 9700 | !tg3_flag(tp, IS_5788)) { |
@@ -9708,7 +9706,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9708 | if (tg3_flag(tp, 5755_PLUS)) | 9706 | if (tg3_flag(tp, 5755_PLUS)) |
9709 | val |= WDMAC_MODE_STATUS_TAG_FIX; | 9707 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
9710 | 9708 | ||
9711 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | 9709 | if (tg3_asic_rev(tp) == ASIC_REV_5785) |
9712 | val |= WDMAC_MODE_BURST_ALL_DATA; | 9710 | val |= WDMAC_MODE_BURST_ALL_DATA; |
9713 | 9711 | ||
9714 | tw32_f(WDMAC_MODE, val); | 9712 | tw32_f(WDMAC_MODE, val); |
@@ -9719,10 +9717,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9719 | 9717 | ||
9720 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | 9718 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
9721 | &pcix_cmd); | 9719 | &pcix_cmd); |
9722 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { | 9720 | if (tg3_asic_rev(tp) == ASIC_REV_5703) { |
9723 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; | 9721 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
9724 | pcix_cmd |= PCI_X_CMD_READ_2K; | 9722 | pcix_cmd |= PCI_X_CMD_READ_2K; |
9725 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | 9723 | } else if (tg3_asic_rev(tp) == ASIC_REV_5704) { |
9726 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); | 9724 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
9727 | pcix_cmd |= PCI_X_CMD_READ_2K; | 9725 | pcix_cmd |= PCI_X_CMD_READ_2K; |
9728 | } | 9726 | } |
@@ -9733,7 +9731,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9733 | tw32_f(RDMAC_MODE, rdmac_mode); | 9731 | tw32_f(RDMAC_MODE, rdmac_mode); |
9734 | udelay(40); | 9732 | udelay(40); |
9735 | 9733 | ||
9736 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) { | 9734 | if (tg3_asic_rev(tp) == ASIC_REV_5719) { |
9737 | for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) { | 9735 | for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) { |
9738 | if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) | 9736 | if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) |
9739 | break; | 9737 | break; |
@@ -9750,7 +9748,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9750 | if (!tg3_flag(tp, 5705_PLUS)) | 9748 | if (!tg3_flag(tp, 5705_PLUS)) |
9751 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); | 9749 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); |
9752 | 9750 | ||
9753 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | 9751 | if (tg3_asic_rev(tp) == ASIC_REV_5761) |
9754 | tw32(SNDDATAC_MODE, | 9752 | tw32(SNDDATAC_MODE, |
9755 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | 9753 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); |
9756 | else | 9754 | else |
@@ -9773,7 +9771,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9773 | tw32(SNDBDI_MODE, val); | 9771 | tw32(SNDBDI_MODE, val); |
9774 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); | 9772 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
9775 | 9773 | ||
9776 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | 9774 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { |
9777 | err = tg3_load_5701_a0_firmware_fix(tp); | 9775 | err = tg3_load_5701_a0_firmware_fix(tp); |
9778 | if (err) | 9776 | if (err) |
9779 | return err; | 9777 | return err; |
@@ -9788,11 +9786,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9788 | tp->tx_mode = TX_MODE_ENABLE; | 9786 | tp->tx_mode = TX_MODE_ENABLE; |
9789 | 9787 | ||
9790 | if (tg3_flag(tp, 5755_PLUS) || | 9788 | if (tg3_flag(tp, 5755_PLUS) || |
9791 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | 9789 | tg3_asic_rev(tp) == ASIC_REV_5906) |
9792 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; | 9790 | tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; |
9793 | 9791 | ||
9794 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | 9792 | if (tg3_asic_rev(tp) == ASIC_REV_5720 || |
9795 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) { | 9793 | tg3_asic_rev(tp) == ASIC_REV_5762) { |
9796 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; | 9794 | val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE; |
9797 | tp->tx_mode &= ~val; | 9795 | tp->tx_mode &= ~val; |
9798 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; | 9796 | tp->tx_mode |= tr32(MAC_TX_MODE) & val; |
@@ -9843,8 +9841,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9843 | udelay(10); | 9841 | udelay(10); |
9844 | 9842 | ||
9845 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { | 9843 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
9846 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && | 9844 | if ((tg3_asic_rev(tp) == ASIC_REV_5704) && |
9847 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { | 9845 | !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { |
9848 | /* Set drive transmission level to 1.2V */ | 9846 | /* Set drive transmission level to 1.2V */ |
9849 | /* only if the signal pre-emphasis bit is not set */ | 9847 | /* only if the signal pre-emphasis bit is not set */ |
9850 | val = tr32(MAC_SERDES_CFG); | 9848 | val = tr32(MAC_SERDES_CFG); |
@@ -9852,7 +9850,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9852 | val |= 0x880; | 9850 | val |= 0x880; |
9853 | tw32(MAC_SERDES_CFG, val); | 9851 | tw32(MAC_SERDES_CFG, val); |
9854 | } | 9852 | } |
9855 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | 9853 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) |
9856 | tw32(MAC_SERDES_CFG, 0x616000); | 9854 | tw32(MAC_SERDES_CFG, 0x616000); |
9857 | } | 9855 | } |
9858 | 9856 | ||
@@ -9865,14 +9863,14 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
9865 | val = 2; | 9863 | val = 2; |
9866 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | 9864 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); |
9867 | 9865 | ||
9868 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | 9866 | if (tg3_asic_rev(tp) == ASIC_REV_5704 && |
9869 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { | 9867 | (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
9870 | /* Use hardware link auto-negotiation */ | 9868 | /* Use hardware link auto-negotiation */ |
9871 | tg3_flag_set(tp, HW_AUTONEG); | 9869 | tg3_flag_set(tp, HW_AUTONEG); |
9872 | } | 9870 | } |
9873 | 9871 | ||
9874 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && | 9872 | if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && |
9875 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | 9873 | tg3_asic_rev(tp) == ASIC_REV_5714) { |
9876 | u32 tmp; | 9874 | u32 tmp; |
9877 | 9875 | ||
9878 | tmp = tr32(SERDES_RX_CTRL); | 9876 | tmp = tr32(SERDES_RX_CTRL); |
@@ -10126,9 +10124,9 @@ static void tg3_periodic_fetch_stats(struct tg3 *tp) | |||
10126 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | 10124 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); |
10127 | 10125 | ||
10128 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | 10126 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); |
10129 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | 10127 | if (tg3_asic_rev(tp) != ASIC_REV_5717 && |
10130 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 && | 10128 | tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 && |
10131 | tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) { | 10129 | tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) { |
10132 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); | 10130 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); |
10133 | } else { | 10131 | } else { |
10134 | u32 val = tr32(HOSTCC_FLOW_ATTN); | 10132 | u32 val = tr32(HOSTCC_FLOW_ATTN); |
@@ -10176,7 +10174,7 @@ static void tg3_timer(unsigned long __opaque) | |||
10176 | 10174 | ||
10177 | spin_lock(&tp->lock); | 10175 | spin_lock(&tp->lock); |
10178 | 10176 | ||
10179 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 10177 | if (tg3_asic_rev(tp) == ASIC_REV_5717 || |
10180 | tg3_flag(tp, 57765_CLASS)) | 10178 | tg3_flag(tp, 57765_CLASS)) |
10181 | tg3_chk_missed_msi(tp); | 10179 | tg3_chk_missed_msi(tp); |
10182 | 10180 | ||
@@ -10302,7 +10300,7 @@ restart_timer: | |||
10302 | static void tg3_timer_init(struct tg3 *tp) | 10300 | static void tg3_timer_init(struct tg3 *tp) |
10303 | { | 10301 | { |
10304 | if (tg3_flag(tp, TAGGED_STATUS) && | 10302 | if (tg3_flag(tp, TAGGED_STATUS) && |
10305 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | 10303 | tg3_asic_rev(tp) != ASIC_REV_5717 && |
10306 | !tg3_flag(tp, 57765_CLASS)) | 10304 | !tg3_flag(tp, 57765_CLASS)) |
10307 | tp->timer_offset = HZ; | 10305 | tp->timer_offset = HZ; |
10308 | else | 10306 | else |
@@ -10883,7 +10881,7 @@ static int tg3_open(struct net_device *dev) | |||
10883 | 10881 | ||
10884 | if (tp->fw_needed) { | 10882 | if (tp->fw_needed) { |
10885 | err = tg3_request_firmware(tp); | 10883 | err = tg3_request_firmware(tp); |
10886 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | 10884 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { |
10887 | if (err) | 10885 | if (err) |
10888 | return err; | 10886 | return err; |
10889 | } else if (err) { | 10887 | } else if (err) { |
@@ -10953,8 +10951,8 @@ static u64 tg3_calc_crc_errors(struct tg3 *tp) | |||
10953 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | 10951 | struct tg3_hw_stats *hw_stats = tp->hw_stats; |
10954 | 10952 | ||
10955 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && | 10953 | if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
10956 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 10954 | (tg3_asic_rev(tp) == ASIC_REV_5700 || |
10957 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | 10955 | tg3_asic_rev(tp) == ASIC_REV_5701)) { |
10958 | u32 val; | 10956 | u32 val; |
10959 | 10957 | ||
10960 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { | 10958 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
@@ -12479,11 +12477,11 @@ static int tg3_test_memory(struct tg3 *tp) | |||
12479 | if (tg3_flag(tp, 5717_PLUS)) | 12477 | if (tg3_flag(tp, 5717_PLUS)) |
12480 | mem_tbl = mem_tbl_5717; | 12478 | mem_tbl = mem_tbl_5717; |
12481 | else if (tg3_flag(tp, 57765_CLASS) || | 12479 | else if (tg3_flag(tp, 57765_CLASS) || |
12482 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 12480 | tg3_asic_rev(tp) == ASIC_REV_5762) |
12483 | mem_tbl = mem_tbl_57765; | 12481 | mem_tbl = mem_tbl_57765; |
12484 | else if (tg3_flag(tp, 5755_PLUS)) | 12482 | else if (tg3_flag(tp, 5755_PLUS)) |
12485 | mem_tbl = mem_tbl_5755; | 12483 | mem_tbl = mem_tbl_5755; |
12486 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | 12484 | else if (tg3_asic_rev(tp) == ASIC_REV_5906) |
12487 | mem_tbl = mem_tbl_5906; | 12485 | mem_tbl = mem_tbl_5906; |
12488 | else if (tg3_flag(tp, 5705_PLUS)) | 12486 | else if (tg3_flag(tp, 5705_PLUS)) |
12489 | mem_tbl = mem_tbl_5705; | 12487 | mem_tbl = mem_tbl_5705; |
@@ -12595,7 +12593,7 @@ static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) | |||
12595 | } else if (tg3_flag(tp, HW_TSO_2)) | 12593 | } else if (tg3_flag(tp, HW_TSO_2)) |
12596 | mss |= hdr_len << 9; | 12594 | mss |= hdr_len << 9; |
12597 | else if (tg3_flag(tp, HW_TSO_1) || | 12595 | else if (tg3_flag(tp, HW_TSO_1) || |
12598 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | 12596 | tg3_asic_rev(tp) == ASIC_REV_5705) { |
12599 | mss |= (TG3_TSO_TCP_OPT_LEN << 9); | 12597 | mss |= (TG3_TSO_TCP_OPT_LEN << 9); |
12600 | } else { | 12598 | } else { |
12601 | base_flags |= (TG3_TSO_TCP_OPT_LEN << 10); | 12599 | base_flags |= (TG3_TSO_TCP_OPT_LEN << 10); |
@@ -12781,7 +12779,7 @@ static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) | |||
12781 | * errata. Also, the MAC loopback test is deprecated for | 12779 | * errata. Also, the MAC loopback test is deprecated for |
12782 | * all newer ASIC revisions. | 12780 | * all newer ASIC revisions. |
12783 | */ | 12781 | */ |
12784 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | 12782 | if (tg3_asic_rev(tp) != ASIC_REV_5780 && |
12785 | !tg3_flag(tp, CPMU_PRESENT)) { | 12783 | !tg3_flag(tp, CPMU_PRESENT)) { |
12786 | tg3_mac_loopback(tp, true); | 12784 | tg3_mac_loopback(tp, true); |
12787 | 12785 | ||
@@ -13268,7 +13266,7 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |||
13268 | /* Reset PHY, otherwise the read DMA engine will be in a mode that | 13266 | /* Reset PHY, otherwise the read DMA engine will be in a mode that |
13269 | * breaks all requests to 256 bytes. | 13267 | * breaks all requests to 256 bytes. |
13270 | */ | 13268 | */ |
13271 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) | 13269 | if (tg3_asic_rev(tp) == ASIC_REV_57766) |
13272 | reset_phy = 1; | 13270 | reset_phy = 1; |
13273 | 13271 | ||
13274 | err = tg3_restart_hw(tp, reset_phy); | 13272 | err = tg3_restart_hw(tp, reset_phy); |
@@ -13381,7 +13379,7 @@ static void tg3_get_nvram_info(struct tg3 *tp) | |||
13381 | tw32(NVRAM_CFG1, nvcfg1); | 13379 | tw32(NVRAM_CFG1, nvcfg1); |
13382 | } | 13380 | } |
13383 | 13381 | ||
13384 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | 13382 | if (tg3_asic_rev(tp) == ASIC_REV_5750 || |
13385 | tg3_flag(tp, 5780_CLASS)) { | 13383 | tg3_flag(tp, 5780_CLASS)) { |
13386 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { | 13384 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
13387 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: | 13385 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
@@ -13822,7 +13820,7 @@ static void tg3_get_5720_nvram_info(struct tg3 *tp) | |||
13822 | nvcfg1 = tr32(NVRAM_CFG1); | 13820 | nvcfg1 = tr32(NVRAM_CFG1); |
13823 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; | 13821 | nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK; |
13824 | 13822 | ||
13825 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) { | 13823 | if (tg3_asic_rev(tp) == ASIC_REV_5762) { |
13826 | if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) { | 13824 | if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) { |
13827 | tg3_flag_set(tp, NO_NVRAM); | 13825 | tg3_flag_set(tp, NO_NVRAM); |
13828 | return; | 13826 | return; |
@@ -13883,7 +13881,7 @@ static void tg3_get_5720_nvram_info(struct tg3 *tp) | |||
13883 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | 13881 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; |
13884 | break; | 13882 | break; |
13885 | default: | 13883 | default: |
13886 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5762) | 13884 | if (tg3_asic_rev(tp) != ASIC_REV_5762) |
13887 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | 13885 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; |
13888 | break; | 13886 | break; |
13889 | } | 13887 | } |
@@ -13930,7 +13928,7 @@ static void tg3_get_5720_nvram_info(struct tg3 *tp) | |||
13930 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | 13928 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; |
13931 | break; | 13929 | break; |
13932 | default: | 13930 | default: |
13933 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5762) | 13931 | if (tg3_asic_rev(tp) != ASIC_REV_5762) |
13934 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | 13932 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; |
13935 | break; | 13933 | break; |
13936 | } | 13934 | } |
@@ -13944,7 +13942,7 @@ static void tg3_get_5720_nvram_info(struct tg3 *tp) | |||
13944 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | 13942 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) |
13945 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); | 13943 | tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); |
13946 | 13944 | ||
13947 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) { | 13945 | if (tg3_asic_rev(tp) == ASIC_REV_5762) { |
13948 | u32 val; | 13946 | u32 val; |
13949 | 13947 | ||
13950 | if (tg3_nvram_read(tp, 0, &val)) | 13948 | if (tg3_nvram_read(tp, 0, &val)) |
@@ -13979,8 +13977,8 @@ static void tg3_nvram_init(struct tg3 *tp) | |||
13979 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | 13977 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); |
13980 | udelay(100); | 13978 | udelay(100); |
13981 | 13979 | ||
13982 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | 13980 | if (tg3_asic_rev(tp) != ASIC_REV_5700 && |
13983 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | 13981 | tg3_asic_rev(tp) != ASIC_REV_5701) { |
13984 | tg3_flag_set(tp, NVRAM); | 13982 | tg3_flag_set(tp, NVRAM); |
13985 | 13983 | ||
13986 | if (tg3_nvram_lock(tp)) { | 13984 | if (tg3_nvram_lock(tp)) { |
@@ -13993,26 +13991,26 @@ static void tg3_nvram_init(struct tg3 *tp) | |||
13993 | 13991 | ||
13994 | tp->nvram_size = 0; | 13992 | tp->nvram_size = 0; |
13995 | 13993 | ||
13996 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | 13994 | if (tg3_asic_rev(tp) == ASIC_REV_5752) |
13997 | tg3_get_5752_nvram_info(tp); | 13995 | tg3_get_5752_nvram_info(tp); |
13998 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | 13996 | else if (tg3_asic_rev(tp) == ASIC_REV_5755) |
13999 | tg3_get_5755_nvram_info(tp); | 13997 | tg3_get_5755_nvram_info(tp); |
14000 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | 13998 | else if (tg3_asic_rev(tp) == ASIC_REV_5787 || |
14001 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | 13999 | tg3_asic_rev(tp) == ASIC_REV_5784 || |
14002 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | 14000 | tg3_asic_rev(tp) == ASIC_REV_5785) |
14003 | tg3_get_5787_nvram_info(tp); | 14001 | tg3_get_5787_nvram_info(tp); |
14004 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | 14002 | else if (tg3_asic_rev(tp) == ASIC_REV_5761) |
14005 | tg3_get_5761_nvram_info(tp); | 14003 | tg3_get_5761_nvram_info(tp); |
14006 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | 14004 | else if (tg3_asic_rev(tp) == ASIC_REV_5906) |
14007 | tg3_get_5906_nvram_info(tp); | 14005 | tg3_get_5906_nvram_info(tp); |
14008 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | 14006 | else if (tg3_asic_rev(tp) == ASIC_REV_57780 || |
14009 | tg3_flag(tp, 57765_CLASS)) | 14007 | tg3_flag(tp, 57765_CLASS)) |
14010 | tg3_get_57780_nvram_info(tp); | 14008 | tg3_get_57780_nvram_info(tp); |
14011 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 14009 | else if (tg3_asic_rev(tp) == ASIC_REV_5717 || |
14012 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | 14010 | tg3_asic_rev(tp) == ASIC_REV_5719) |
14013 | tg3_get_5717_nvram_info(tp); | 14011 | tg3_get_5717_nvram_info(tp); |
14014 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | 14012 | else if (tg3_asic_rev(tp) == ASIC_REV_5720 || |
14015 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 14013 | tg3_asic_rev(tp) == ASIC_REV_5762) |
14016 | tg3_get_5720_nvram_info(tp); | 14014 | tg3_get_5720_nvram_info(tp); |
14017 | else | 14015 | else |
14018 | tg3_get_nvram_info(tp); | 14016 | tg3_get_nvram_info(tp); |
@@ -14125,7 +14123,7 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) | |||
14125 | tg3_flag_set(tp, EEPROM_WRITE_PROT); | 14123 | tg3_flag_set(tp, EEPROM_WRITE_PROT); |
14126 | tg3_flag_set(tp, WOL_CAP); | 14124 | tg3_flag_set(tp, WOL_CAP); |
14127 | 14125 | ||
14128 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 14126 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
14129 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { | 14127 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
14130 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); | 14128 | tg3_flag_clear(tp, EEPROM_WRITE_PROT); |
14131 | tg3_flag_set(tp, IS_NIC); | 14129 | tg3_flag_set(tp, IS_NIC); |
@@ -14152,13 +14150,13 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) | |||
14152 | 14150 | ||
14153 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | 14151 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); |
14154 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | 14152 | ver >>= NIC_SRAM_DATA_VER_SHIFT; |
14155 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | 14153 | if (tg3_asic_rev(tp) != ASIC_REV_5700 && |
14156 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | 14154 | tg3_asic_rev(tp) != ASIC_REV_5701 && |
14157 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 && | 14155 | tg3_asic_rev(tp) != ASIC_REV_5703 && |
14158 | (ver > 0) && (ver < 0x100)) | 14156 | (ver > 0) && (ver < 0x100)) |
14159 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | 14157 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); |
14160 | 14158 | ||
14161 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | 14159 | if (tg3_asic_rev(tp) == ASIC_REV_5785) |
14162 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | 14160 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); |
14163 | 14161 | ||
14164 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == | 14162 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
@@ -14206,18 +14204,16 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) | |||
14206 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | 14204 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is |
14207 | * read on some older 5700/5701 bootcode. | 14205 | * read on some older 5700/5701 bootcode. |
14208 | */ | 14206 | */ |
14209 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | 14207 | if (tg3_asic_rev(tp) == ASIC_REV_5700 || |
14210 | ASIC_REV_5700 || | 14208 | tg3_asic_rev(tp) == ASIC_REV_5701) |
14211 | GET_ASIC_REV(tp->pci_chip_rev_id) == | ||
14212 | ASIC_REV_5701) | ||
14213 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | 14209 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
14214 | 14210 | ||
14215 | break; | 14211 | break; |
14216 | 14212 | ||
14217 | case SHASTA_EXT_LED_SHARED: | 14213 | case SHASTA_EXT_LED_SHARED: |
14218 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | 14214 | tp->led_ctrl = LED_CTRL_MODE_SHARED; |
14219 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | 14215 | if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && |
14220 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | 14216 | tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1) |
14221 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | 14217 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | |
14222 | LED_CTRL_MODE_PHY_2); | 14218 | LED_CTRL_MODE_PHY_2); |
14223 | break; | 14219 | break; |
@@ -14228,19 +14224,19 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) | |||
14228 | 14224 | ||
14229 | case SHASTA_EXT_LED_COMBO: | 14225 | case SHASTA_EXT_LED_COMBO: |
14230 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | 14226 | tp->led_ctrl = LED_CTRL_MODE_COMBO; |
14231 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | 14227 | if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) |
14232 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | 14228 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | |
14233 | LED_CTRL_MODE_PHY_2); | 14229 | LED_CTRL_MODE_PHY_2); |
14234 | break; | 14230 | break; |
14235 | 14231 | ||
14236 | } | 14232 | } |
14237 | 14233 | ||
14238 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 14234 | if ((tg3_asic_rev(tp) == ASIC_REV_5700 || |
14239 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | 14235 | tg3_asic_rev(tp) == ASIC_REV_5701) && |
14240 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | 14236 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) |
14241 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | 14237 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; |
14242 | 14238 | ||
14243 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) | 14239 | if (tg3_chip_rev(tp) == CHIPREV_5784_AX) |
14244 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | 14240 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
14245 | 14241 | ||
14246 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { | 14242 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
@@ -14284,13 +14280,13 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) | |||
14284 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; | 14280 | tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; |
14285 | 14281 | ||
14286 | if ((tg3_flag(tp, 57765_PLUS) || | 14282 | if ((tg3_flag(tp, 57765_PLUS) || |
14287 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | 14283 | (tg3_asic_rev(tp) == ASIC_REV_5784 && |
14288 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | 14284 | tg3_chip_rev(tp) != CHIPREV_5784_AX)) && |
14289 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) | 14285 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
14290 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; | 14286 | tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; |
14291 | 14287 | ||
14292 | if (tg3_flag(tp, PCI_EXPRESS) && | 14288 | if (tg3_flag(tp, PCI_EXPRESS) && |
14293 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | 14289 | tg3_asic_rev(tp) != ASIC_REV_5785 && |
14294 | !tg3_flag(tp, 57765_PLUS)) { | 14290 | !tg3_flag(tp, 57765_PLUS)) { |
14295 | u32 cfg3; | 14291 | u32 cfg3; |
14296 | 14292 | ||
@@ -14513,13 +14509,13 @@ static int tg3_phy_probe(struct tg3 *tp) | |||
14513 | } | 14509 | } |
14514 | 14510 | ||
14515 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && | 14511 | if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && |
14516 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | 14512 | (tg3_asic_rev(tp) == ASIC_REV_5719 || |
14517 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | 14513 | tg3_asic_rev(tp) == ASIC_REV_5720 || |
14518 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762 || | 14514 | tg3_asic_rev(tp) == ASIC_REV_5762 || |
14519 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && | 14515 | (tg3_asic_rev(tp) == ASIC_REV_5717 && |
14520 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) || | 14516 | tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) || |
14521 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | 14517 | (tg3_asic_rev(tp) == ASIC_REV_57765 && |
14522 | tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))) | 14518 | tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) |
14523 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; | 14519 | tp->phy_flags |= TG3_PHYFLG_EEE_CAP; |
14524 | 14520 | ||
14525 | tg3_phy_init_link_config(tp); | 14521 | tg3_phy_init_link_config(tp); |
@@ -14629,7 +14625,7 @@ out_not_found: | |||
14629 | return; | 14625 | return; |
14630 | 14626 | ||
14631 | out_no_vpd: | 14627 | out_no_vpd: |
14632 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | 14628 | if (tg3_asic_rev(tp) == ASIC_REV_5717) { |
14633 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || | 14629 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
14634 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) | 14630 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) |
14635 | strcpy(tp->board_part_number, "BCM5717"); | 14631 | strcpy(tp->board_part_number, "BCM5717"); |
@@ -14637,7 +14633,7 @@ out_no_vpd: | |||
14637 | strcpy(tp->board_part_number, "BCM5718"); | 14633 | strcpy(tp->board_part_number, "BCM5718"); |
14638 | else | 14634 | else |
14639 | goto nomatch; | 14635 | goto nomatch; |
14640 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { | 14636 | } else if (tg3_asic_rev(tp) == ASIC_REV_57780) { |
14641 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | 14637 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) |
14642 | strcpy(tp->board_part_number, "BCM57780"); | 14638 | strcpy(tp->board_part_number, "BCM57780"); |
14643 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | 14639 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) |
@@ -14648,7 +14644,7 @@ out_no_vpd: | |||
14648 | strcpy(tp->board_part_number, "BCM57788"); | 14644 | strcpy(tp->board_part_number, "BCM57788"); |
14649 | else | 14645 | else |
14650 | goto nomatch; | 14646 | goto nomatch; |
14651 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | 14647 | } else if (tg3_asic_rev(tp) == ASIC_REV_57765) { |
14652 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | 14648 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) |
14653 | strcpy(tp->board_part_number, "BCM57761"); | 14649 | strcpy(tp->board_part_number, "BCM57761"); |
14654 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | 14650 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) |
@@ -14663,7 +14659,7 @@ out_no_vpd: | |||
14663 | strcpy(tp->board_part_number, "BCM57795"); | 14659 | strcpy(tp->board_part_number, "BCM57795"); |
14664 | else | 14660 | else |
14665 | goto nomatch; | 14661 | goto nomatch; |
14666 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) { | 14662 | } else if (tg3_asic_rev(tp) == ASIC_REV_57766) { |
14667 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) | 14663 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) |
14668 | strcpy(tp->board_part_number, "BCM57762"); | 14664 | strcpy(tp->board_part_number, "BCM57762"); |
14669 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) | 14665 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) |
@@ -14674,7 +14670,7 @@ out_no_vpd: | |||
14674 | strcpy(tp->board_part_number, "BCM57786"); | 14670 | strcpy(tp->board_part_number, "BCM57786"); |
14675 | else | 14671 | else |
14676 | goto nomatch; | 14672 | goto nomatch; |
14677 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 14673 | } else if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
14678 | strcpy(tp->board_part_number, "BCM95906"); | 14674 | strcpy(tp->board_part_number, "BCM95906"); |
14679 | } else { | 14675 | } else { |
14680 | nomatch: | 14676 | nomatch: |
@@ -14915,7 +14911,7 @@ static void tg3_read_otp_ver(struct tg3 *tp) | |||
14915 | { | 14911 | { |
14916 | u32 val, val2; | 14912 | u32 val, val2; |
14917 | 14913 | ||
14918 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5762) | 14914 | if (tg3_asic_rev(tp) != ASIC_REV_5762) |
14919 | return; | 14915 | return; |
14920 | 14916 | ||
14921 | if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) && | 14917 | if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) && |
@@ -15021,7 +15017,7 @@ static struct pci_dev *tg3_find_peer(struct tg3 *tp) | |||
15021 | static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg) | 15017 | static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg) |
15022 | { | 15018 | { |
15023 | tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; | 15019 | tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; |
15024 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { | 15020 | if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) { |
15025 | u32 reg; | 15021 | u32 reg; |
15026 | 15022 | ||
15027 | /* All devices that use the alternate | 15023 | /* All devices that use the alternate |
@@ -15058,47 +15054,47 @@ static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg) | |||
15058 | /* Wrong chip ID in 5752 A0. This code can be removed later | 15054 | /* Wrong chip ID in 5752 A0. This code can be removed later |
15059 | * as A0 is not in production. | 15055 | * as A0 is not in production. |
15060 | */ | 15056 | */ |
15061 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | 15057 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW) |
15062 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | 15058 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; |
15063 | 15059 | ||
15064 | if (tp->pci_chip_rev_id == CHIPREV_ID_5717_C0) | 15060 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0) |
15065 | tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; | 15061 | tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; |
15066 | 15062 | ||
15067 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 15063 | if (tg3_asic_rev(tp) == ASIC_REV_5717 || |
15068 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | 15064 | tg3_asic_rev(tp) == ASIC_REV_5719 || |
15069 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | 15065 | tg3_asic_rev(tp) == ASIC_REV_5720) |
15070 | tg3_flag_set(tp, 5717_PLUS); | 15066 | tg3_flag_set(tp, 5717_PLUS); |
15071 | 15067 | ||
15072 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 || | 15068 | if (tg3_asic_rev(tp) == ASIC_REV_57765 || |
15073 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) | 15069 | tg3_asic_rev(tp) == ASIC_REV_57766) |
15074 | tg3_flag_set(tp, 57765_CLASS); | 15070 | tg3_flag_set(tp, 57765_CLASS); |
15075 | 15071 | ||
15076 | if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) || | 15072 | if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) || |
15077 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 15073 | tg3_asic_rev(tp) == ASIC_REV_5762) |
15078 | tg3_flag_set(tp, 57765_PLUS); | 15074 | tg3_flag_set(tp, 57765_PLUS); |
15079 | 15075 | ||
15080 | /* Intentionally exclude ASIC_REV_5906 */ | 15076 | /* Intentionally exclude ASIC_REV_5906 */ |
15081 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | 15077 | if (tg3_asic_rev(tp) == ASIC_REV_5755 || |
15082 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | 15078 | tg3_asic_rev(tp) == ASIC_REV_5787 || |
15083 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | 15079 | tg3_asic_rev(tp) == ASIC_REV_5784 || |
15084 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | 15080 | tg3_asic_rev(tp) == ASIC_REV_5761 || |
15085 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | 15081 | tg3_asic_rev(tp) == ASIC_REV_5785 || |
15086 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | 15082 | tg3_asic_rev(tp) == ASIC_REV_57780 || |
15087 | tg3_flag(tp, 57765_PLUS)) | 15083 | tg3_flag(tp, 57765_PLUS)) |
15088 | tg3_flag_set(tp, 5755_PLUS); | 15084 | tg3_flag_set(tp, 5755_PLUS); |
15089 | 15085 | ||
15090 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || | 15086 | if (tg3_asic_rev(tp) == ASIC_REV_5780 || |
15091 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) | 15087 | tg3_asic_rev(tp) == ASIC_REV_5714) |
15092 | tg3_flag_set(tp, 5780_CLASS); | 15088 | tg3_flag_set(tp, 5780_CLASS); |
15093 | 15089 | ||
15094 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | 15090 | if (tg3_asic_rev(tp) == ASIC_REV_5750 || |
15095 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | 15091 | tg3_asic_rev(tp) == ASIC_REV_5752 || |
15096 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || | 15092 | tg3_asic_rev(tp) == ASIC_REV_5906 || |
15097 | tg3_flag(tp, 5755_PLUS) || | 15093 | tg3_flag(tp, 5755_PLUS) || |
15098 | tg3_flag(tp, 5780_CLASS)) | 15094 | tg3_flag(tp, 5780_CLASS)) |
15099 | tg3_flag_set(tp, 5750_PLUS); | 15095 | tg3_flag_set(tp, 5750_PLUS); |
15100 | 15096 | ||
15101 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || | 15097 | if (tg3_asic_rev(tp) == ASIC_REV_5705 || |
15102 | tg3_flag(tp, 5750_PLUS)) | 15098 | tg3_flag(tp, 5750_PLUS)) |
15103 | tg3_flag_set(tp, 5705_PLUS); | 15099 | tg3_flag_set(tp, 5705_PLUS); |
15104 | } | 15100 | } |
@@ -15108,13 +15104,13 @@ static bool tg3_10_100_only_device(struct tg3 *tp, | |||
15108 | { | 15104 | { |
15109 | u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK; | 15105 | u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK; |
15110 | 15106 | ||
15111 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | 15107 | if ((tg3_asic_rev(tp) == ASIC_REV_5703 && |
15112 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | 15108 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || |
15113 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) | 15109 | (tp->phy_flags & TG3_PHYFLG_IS_FET)) |
15114 | return true; | 15110 | return true; |
15115 | 15111 | ||
15116 | if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) { | 15112 | if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) { |
15117 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | 15113 | if (tg3_asic_rev(tp) == ASIC_REV_5705) { |
15118 | if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100) | 15114 | if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100) |
15119 | return true; | 15115 | return true; |
15120 | } else { | 15116 | } else { |
@@ -15175,8 +15171,8 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15175 | * enable this workaround if the 5703 is on the secondary | 15171 | * enable this workaround if the 5703 is on the secondary |
15176 | * bus of these ICH bridges. | 15172 | * bus of these ICH bridges. |
15177 | */ | 15173 | */ |
15178 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | 15174 | if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) || |
15179 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | 15175 | (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) { |
15180 | static struct tg3_dev_id { | 15176 | static struct tg3_dev_id { |
15181 | u32 vendor; | 15177 | u32 vendor; |
15182 | u32 device; | 15178 | u32 device; |
@@ -15216,7 +15212,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15216 | } | 15212 | } |
15217 | } | 15213 | } |
15218 | 15214 | ||
15219 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | 15215 | if (tg3_asic_rev(tp) == ASIC_REV_5701) { |
15220 | static struct tg3_dev_id { | 15216 | static struct tg3_dev_id { |
15221 | u32 vendor; | 15217 | u32 vendor; |
15222 | u32 device; | 15218 | u32 device; |
@@ -15276,29 +15272,29 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15276 | } while (bridge); | 15272 | } while (bridge); |
15277 | } | 15273 | } |
15278 | 15274 | ||
15279 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | 15275 | if (tg3_asic_rev(tp) == ASIC_REV_5704 || |
15280 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) | 15276 | tg3_asic_rev(tp) == ASIC_REV_5714) |
15281 | tp->pdev_peer = tg3_find_peer(tp); | 15277 | tp->pdev_peer = tg3_find_peer(tp); |
15282 | 15278 | ||
15283 | /* Determine TSO capabilities */ | 15279 | /* Determine TSO capabilities */ |
15284 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) | 15280 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0) |
15285 | ; /* Do nothing. HW bug. */ | 15281 | ; /* Do nothing. HW bug. */ |
15286 | else if (tg3_flag(tp, 57765_PLUS)) | 15282 | else if (tg3_flag(tp, 57765_PLUS)) |
15287 | tg3_flag_set(tp, HW_TSO_3); | 15283 | tg3_flag_set(tp, HW_TSO_3); |
15288 | else if (tg3_flag(tp, 5755_PLUS) || | 15284 | else if (tg3_flag(tp, 5755_PLUS) || |
15289 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | 15285 | tg3_asic_rev(tp) == ASIC_REV_5906) |
15290 | tg3_flag_set(tp, HW_TSO_2); | 15286 | tg3_flag_set(tp, HW_TSO_2); |
15291 | else if (tg3_flag(tp, 5750_PLUS)) { | 15287 | else if (tg3_flag(tp, 5750_PLUS)) { |
15292 | tg3_flag_set(tp, HW_TSO_1); | 15288 | tg3_flag_set(tp, HW_TSO_1); |
15293 | tg3_flag_set(tp, TSO_BUG); | 15289 | tg3_flag_set(tp, TSO_BUG); |
15294 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && | 15290 | if (tg3_asic_rev(tp) == ASIC_REV_5750 && |
15295 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | 15291 | tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2) |
15296 | tg3_flag_clear(tp, TSO_BUG); | 15292 | tg3_flag_clear(tp, TSO_BUG); |
15297 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | 15293 | } else if (tg3_asic_rev(tp) != ASIC_REV_5700 && |
15298 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | 15294 | tg3_asic_rev(tp) != ASIC_REV_5701 && |
15299 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | 15295 | tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { |
15300 | tg3_flag_set(tp, TSO_BUG); | 15296 | tg3_flag_set(tp, TSO_BUG); |
15301 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) | 15297 | if (tg3_asic_rev(tp) == ASIC_REV_5705) |
15302 | tp->fw_needed = FIRMWARE_TG3TSO5; | 15298 | tp->fw_needed = FIRMWARE_TG3TSO5; |
15303 | else | 15299 | else |
15304 | tp->fw_needed = FIRMWARE_TG3TSO; | 15300 | tp->fw_needed = FIRMWARE_TG3TSO; |
@@ -15320,22 +15316,22 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15320 | tp->fw_needed = NULL; | 15316 | tp->fw_needed = NULL; |
15321 | } | 15317 | } |
15322 | 15318 | ||
15323 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | 15319 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) |
15324 | tp->fw_needed = FIRMWARE_TG3; | 15320 | tp->fw_needed = FIRMWARE_TG3; |
15325 | 15321 | ||
15326 | tp->irq_max = 1; | 15322 | tp->irq_max = 1; |
15327 | 15323 | ||
15328 | if (tg3_flag(tp, 5750_PLUS)) { | 15324 | if (tg3_flag(tp, 5750_PLUS)) { |
15329 | tg3_flag_set(tp, SUPPORT_MSI); | 15325 | tg3_flag_set(tp, SUPPORT_MSI); |
15330 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || | 15326 | if (tg3_chip_rev(tp) == CHIPREV_5750_AX || |
15331 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | 15327 | tg3_chip_rev(tp) == CHIPREV_5750_BX || |
15332 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | 15328 | (tg3_asic_rev(tp) == ASIC_REV_5714 && |
15333 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | 15329 | tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 && |
15334 | tp->pdev_peer == tp->pdev)) | 15330 | tp->pdev_peer == tp->pdev)) |
15335 | tg3_flag_clear(tp, SUPPORT_MSI); | 15331 | tg3_flag_clear(tp, SUPPORT_MSI); |
15336 | 15332 | ||
15337 | if (tg3_flag(tp, 5755_PLUS) || | 15333 | if (tg3_flag(tp, 5755_PLUS) || |
15338 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 15334 | tg3_asic_rev(tp) == ASIC_REV_5906) { |
15339 | tg3_flag_set(tp, 1SHOT_MSI); | 15335 | tg3_flag_set(tp, 1SHOT_MSI); |
15340 | } | 15336 | } |
15341 | 15337 | ||
@@ -15351,26 +15347,26 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15351 | tp->rxq_max = TG3_RSS_MAX_NUM_QS; | 15347 | tp->rxq_max = TG3_RSS_MAX_NUM_QS; |
15352 | tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS); | 15348 | tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS); |
15353 | 15349 | ||
15354 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | 15350 | if (tg3_asic_rev(tp) == ASIC_REV_5719 || |
15355 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) | 15351 | tg3_asic_rev(tp) == ASIC_REV_5720) |
15356 | tp->txq_max = tp->irq_max - 1; | 15352 | tp->txq_max = tp->irq_max - 1; |
15357 | } | 15353 | } |
15358 | 15354 | ||
15359 | if (tg3_flag(tp, 5755_PLUS) || | 15355 | if (tg3_flag(tp, 5755_PLUS) || |
15360 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | 15356 | tg3_asic_rev(tp) == ASIC_REV_5906) |
15361 | tg3_flag_set(tp, SHORT_DMA_BUG); | 15357 | tg3_flag_set(tp, SHORT_DMA_BUG); |
15362 | 15358 | ||
15363 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) | 15359 | if (tg3_asic_rev(tp) == ASIC_REV_5719) |
15364 | tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; | 15360 | tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; |
15365 | 15361 | ||
15366 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 15362 | if (tg3_asic_rev(tp) == ASIC_REV_5717 || |
15367 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | 15363 | tg3_asic_rev(tp) == ASIC_REV_5719 || |
15368 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | 15364 | tg3_asic_rev(tp) == ASIC_REV_5720 || |
15369 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 15365 | tg3_asic_rev(tp) == ASIC_REV_5762) |
15370 | tg3_flag_set(tp, LRG_PROD_RING_CAP); | 15366 | tg3_flag_set(tp, LRG_PROD_RING_CAP); |
15371 | 15367 | ||
15372 | if (tg3_flag(tp, 57765_PLUS) && | 15368 | if (tg3_flag(tp, 57765_PLUS) && |
15373 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0) | 15369 | tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0) |
15374 | tg3_flag_set(tp, USE_JUMBO_BDFLAG); | 15370 | tg3_flag_set(tp, USE_JUMBO_BDFLAG); |
15375 | 15371 | ||
15376 | if (!tg3_flag(tp, 5705_PLUS) || | 15372 | if (!tg3_flag(tp, 5705_PLUS) || |
@@ -15388,20 +15384,19 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15388 | 15384 | ||
15389 | pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); | 15385 | pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); |
15390 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | 15386 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { |
15391 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | 15387 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
15392 | ASIC_REV_5906) { | ||
15393 | tg3_flag_clear(tp, HW_TSO_2); | 15388 | tg3_flag_clear(tp, HW_TSO_2); |
15394 | tg3_flag_clear(tp, TSO_CAPABLE); | 15389 | tg3_flag_clear(tp, TSO_CAPABLE); |
15395 | } | 15390 | } |
15396 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | 15391 | if (tg3_asic_rev(tp) == ASIC_REV_5784 || |
15397 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | 15392 | tg3_asic_rev(tp) == ASIC_REV_5761 || |
15398 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || | 15393 | tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 || |
15399 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | 15394 | tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1) |
15400 | tg3_flag_set(tp, CLKREQ_BUG); | 15395 | tg3_flag_set(tp, CLKREQ_BUG); |
15401 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { | 15396 | } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) { |
15402 | tg3_flag_set(tp, L1PLLPD_EN); | 15397 | tg3_flag_set(tp, L1PLLPD_EN); |
15403 | } | 15398 | } |
15404 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { | 15399 | } else if (tg3_asic_rev(tp) == ASIC_REV_5785) { |
15405 | /* BCM5785 devices are effectively PCIe devices, and should | 15400 | /* BCM5785 devices are effectively PCIe devices, and should |
15406 | * follow PCIe codepaths, but do not have a PCIe capabilities | 15401 | * follow PCIe codepaths, but do not have a PCIe capabilities |
15407 | * section. | 15402 | * section. |
@@ -15434,7 +15429,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15434 | &tp->pci_cacheline_sz); | 15429 | &tp->pci_cacheline_sz); |
15435 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | 15430 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
15436 | &tp->pci_lat_timer); | 15431 | &tp->pci_lat_timer); |
15437 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | 15432 | if (tg3_asic_rev(tp) == ASIC_REV_5703 && |
15438 | tp->pci_lat_timer < 64) { | 15433 | tp->pci_lat_timer < 64) { |
15439 | tp->pci_lat_timer = 64; | 15434 | tp->pci_lat_timer = 64; |
15440 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | 15435 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
@@ -15444,7 +15439,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15444 | /* Important! -- It is critical that the PCI-X hw workaround | 15439 | /* Important! -- It is critical that the PCI-X hw workaround |
15445 | * situation is decided before the first MMIO register access. | 15440 | * situation is decided before the first MMIO register access. |
15446 | */ | 15441 | */ |
15447 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { | 15442 | if (tg3_chip_rev(tp) == CHIPREV_5700_BX) { |
15448 | /* 5700 BX chips need to have their TX producer index | 15443 | /* 5700 BX chips need to have their TX producer index |
15449 | * mailboxes written twice to workaround a bug. | 15444 | * mailboxes written twice to workaround a bug. |
15450 | */ | 15445 | */ |
@@ -15486,7 +15481,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15486 | tg3_flag_set(tp, PCI_32BIT); | 15481 | tg3_flag_set(tp, PCI_32BIT); |
15487 | 15482 | ||
15488 | /* Chip-specific fixup from Broadcom driver */ | 15483 | /* Chip-specific fixup from Broadcom driver */ |
15489 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | 15484 | if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) && |
15490 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | 15485 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { |
15491 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | 15486 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; |
15492 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | 15487 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); |
@@ -15503,9 +15498,9 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15503 | /* Various workaround register access methods */ | 15498 | /* Various workaround register access methods */ |
15504 | if (tg3_flag(tp, PCIX_TARGET_HWBUG)) | 15499 | if (tg3_flag(tp, PCIX_TARGET_HWBUG)) |
15505 | tp->write32 = tg3_write_indirect_reg32; | 15500 | tp->write32 = tg3_write_indirect_reg32; |
15506 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || | 15501 | else if (tg3_asic_rev(tp) == ASIC_REV_5701 || |
15507 | (tg3_flag(tp, PCI_EXPRESS) && | 15502 | (tg3_flag(tp, PCI_EXPRESS) && |
15508 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { | 15503 | tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) { |
15509 | /* | 15504 | /* |
15510 | * Back to back register writes can cause problems on these | 15505 | * Back to back register writes can cause problems on these |
15511 | * chips, the workaround is to read back all reg writes | 15506 | * chips, the workaround is to read back all reg writes |
@@ -15537,7 +15532,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15537 | pci_cmd &= ~PCI_COMMAND_MEMORY; | 15532 | pci_cmd &= ~PCI_COMMAND_MEMORY; |
15538 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | 15533 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); |
15539 | } | 15534 | } |
15540 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 15535 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
15541 | tp->read32_mbox = tg3_read32_mbox_5906; | 15536 | tp->read32_mbox = tg3_read32_mbox_5906; |
15542 | tp->write32_mbox = tg3_write32_mbox_5906; | 15537 | tp->write32_mbox = tg3_write32_mbox_5906; |
15543 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | 15538 | tp->write32_tx_mbox = tg3_write32_mbox_5906; |
@@ -15546,8 +15541,8 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15546 | 15541 | ||
15547 | if (tp->write32 == tg3_write_indirect_reg32 || | 15542 | if (tp->write32 == tg3_write_indirect_reg32 || |
15548 | (tg3_flag(tp, PCIX_MODE) && | 15543 | (tg3_flag(tp, PCIX_MODE) && |
15549 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 15544 | (tg3_asic_rev(tp) == ASIC_REV_5700 || |
15550 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) | 15545 | tg3_asic_rev(tp) == ASIC_REV_5701))) |
15551 | tg3_flag_set(tp, SRAM_USE_CONFIG); | 15546 | tg3_flag_set(tp, SRAM_USE_CONFIG); |
15552 | 15547 | ||
15553 | /* The memory arbiter has to be enabled in order for SRAM accesses | 15548 | /* The memory arbiter has to be enabled in order for SRAM accesses |
@@ -15559,7 +15554,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15559 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | 15554 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
15560 | 15555 | ||
15561 | tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; | 15556 | tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; |
15562 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | 15557 | if (tg3_asic_rev(tp) == ASIC_REV_5704 || |
15563 | tg3_flag(tp, 5780_CLASS)) { | 15558 | tg3_flag(tp, 5780_CLASS)) { |
15564 | if (tg3_flag(tp, PCIX_MODE)) { | 15559 | if (tg3_flag(tp, PCIX_MODE)) { |
15565 | pci_read_config_dword(tp->pdev, | 15560 | pci_read_config_dword(tp->pdev, |
@@ -15567,14 +15562,14 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15567 | &val); | 15562 | &val); |
15568 | tp->pci_fn = val & 0x7; | 15563 | tp->pci_fn = val & 0x7; |
15569 | } | 15564 | } |
15570 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 15565 | } else if (tg3_asic_rev(tp) == ASIC_REV_5717 || |
15571 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | 15566 | tg3_asic_rev(tp) == ASIC_REV_5719 || |
15572 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) { | 15567 | tg3_asic_rev(tp) == ASIC_REV_5720) { |
15573 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); | 15568 | tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); |
15574 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG) | 15569 | if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG) |
15575 | val = tr32(TG3_CPMU_STATUS); | 15570 | val = tr32(TG3_CPMU_STATUS); |
15576 | 15571 | ||
15577 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | 15572 | if (tg3_asic_rev(tp) == ASIC_REV_5717) |
15578 | tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; | 15573 | tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; |
15579 | else | 15574 | else |
15580 | tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> | 15575 | tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> |
@@ -15621,18 +15616,18 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15621 | * It is also used as eeprom write protect on LOMs. | 15616 | * It is also used as eeprom write protect on LOMs. |
15622 | */ | 15617 | */ |
15623 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | 15618 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; |
15624 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 15619 | if (tg3_asic_rev(tp) == ASIC_REV_5700 || |
15625 | tg3_flag(tp, EEPROM_WRITE_PROT)) | 15620 | tg3_flag(tp, EEPROM_WRITE_PROT)) |
15626 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | 15621 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | |
15627 | GRC_LCLCTRL_GPIO_OUTPUT1); | 15622 | GRC_LCLCTRL_GPIO_OUTPUT1); |
15628 | /* Unused GPIO3 must be driven as output on 5752 because there | 15623 | /* Unused GPIO3 must be driven as output on 5752 because there |
15629 | * are no pull-up resistors on unused GPIO pins. | 15624 | * are no pull-up resistors on unused GPIO pins. |
15630 | */ | 15625 | */ |
15631 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | 15626 | else if (tg3_asic_rev(tp) == ASIC_REV_5752) |
15632 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | 15627 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; |
15633 | 15628 | ||
15634 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | 15629 | if (tg3_asic_rev(tp) == ASIC_REV_5755 || |
15635 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | 15630 | tg3_asic_rev(tp) == ASIC_REV_57780 || |
15636 | tg3_flag(tp, 57765_CLASS)) | 15631 | tg3_flag(tp, 57765_CLASS)) |
15637 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | 15632 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
15638 | 15633 | ||
@@ -15646,7 +15641,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15646 | GRC_LCLCTRL_GPIO_OUTPUT0; | 15641 | GRC_LCLCTRL_GPIO_OUTPUT0; |
15647 | } | 15642 | } |
15648 | 15643 | ||
15649 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 15644 | if (tg3_asic_rev(tp) == ASIC_REV_5762) |
15650 | tp->grc_local_ctrl |= | 15645 | tp->grc_local_ctrl |= |
15651 | tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL; | 15646 | tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL; |
15652 | 15647 | ||
@@ -15660,42 +15655,42 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15660 | tg3_flag_set(tp, JUMBO_RING_ENABLE); | 15655 | tg3_flag_set(tp, JUMBO_RING_ENABLE); |
15661 | 15656 | ||
15662 | /* Determine WakeOnLan speed to use. */ | 15657 | /* Determine WakeOnLan speed to use. */ |
15663 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 15658 | if (tg3_asic_rev(tp) == ASIC_REV_5700 || |
15664 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | 15659 | tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || |
15665 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | 15660 | tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || |
15666 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | 15661 | tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) { |
15667 | tg3_flag_clear(tp, WOL_SPEED_100MB); | 15662 | tg3_flag_clear(tp, WOL_SPEED_100MB); |
15668 | } else { | 15663 | } else { |
15669 | tg3_flag_set(tp, WOL_SPEED_100MB); | 15664 | tg3_flag_set(tp, WOL_SPEED_100MB); |
15670 | } | 15665 | } |
15671 | 15666 | ||
15672 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | 15667 | if (tg3_asic_rev(tp) == ASIC_REV_5906) |
15673 | tp->phy_flags |= TG3_PHYFLG_IS_FET; | 15668 | tp->phy_flags |= TG3_PHYFLG_IS_FET; |
15674 | 15669 | ||
15675 | /* A few boards don't want Ethernet@WireSpeed phy feature */ | 15670 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
15676 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 15671 | if (tg3_asic_rev(tp) == ASIC_REV_5700 || |
15677 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | 15672 | (tg3_asic_rev(tp) == ASIC_REV_5705 && |
15678 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && | 15673 | (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) && |
15679 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || | 15674 | (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) || |
15680 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || | 15675 | (tp->phy_flags & TG3_PHYFLG_IS_FET) || |
15681 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) | 15676 | (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) |
15682 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; | 15677 | tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; |
15683 | 15678 | ||
15684 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | 15679 | if (tg3_chip_rev(tp) == CHIPREV_5703_AX || |
15685 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | 15680 | tg3_chip_rev(tp) == CHIPREV_5704_AX) |
15686 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; | 15681 | tp->phy_flags |= TG3_PHYFLG_ADC_BUG; |
15687 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) | 15682 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) |
15688 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; | 15683 | tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; |
15689 | 15684 | ||
15690 | if (tg3_flag(tp, 5705_PLUS) && | 15685 | if (tg3_flag(tp, 5705_PLUS) && |
15691 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && | 15686 | !(tp->phy_flags & TG3_PHYFLG_IS_FET) && |
15692 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | 15687 | tg3_asic_rev(tp) != ASIC_REV_5785 && |
15693 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && | 15688 | tg3_asic_rev(tp) != ASIC_REV_57780 && |
15694 | !tg3_flag(tp, 57765_PLUS)) { | 15689 | !tg3_flag(tp, 57765_PLUS)) { |
15695 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | 15690 | if (tg3_asic_rev(tp) == ASIC_REV_5755 || |
15696 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | 15691 | tg3_asic_rev(tp) == ASIC_REV_5787 || |
15697 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | 15692 | tg3_asic_rev(tp) == ASIC_REV_5784 || |
15698 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | 15693 | tg3_asic_rev(tp) == ASIC_REV_5761) { |
15699 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && | 15694 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
15700 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | 15695 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) |
15701 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; | 15696 | tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; |
@@ -15705,8 +15700,8 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15705 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; | 15700 | tp->phy_flags |= TG3_PHYFLG_BER_BUG; |
15706 | } | 15701 | } |
15707 | 15702 | ||
15708 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | 15703 | if (tg3_asic_rev(tp) == ASIC_REV_5784 && |
15709 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | 15704 | tg3_chip_rev(tp) != CHIPREV_5784_AX) { |
15710 | tp->phy_otp = tg3_read_otp_phycfg(tp); | 15705 | tp->phy_otp = tg3_read_otp_phycfg(tp); |
15711 | if (tp->phy_otp == 0) | 15706 | if (tp->phy_otp == 0) |
15712 | tp->phy_otp = TG3_OTP_DEFAULT; | 15707 | tp->phy_otp = TG3_OTP_DEFAULT; |
@@ -15718,20 +15713,20 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15718 | tp->mi_mode = MAC_MI_MODE_BASE; | 15713 | tp->mi_mode = MAC_MI_MODE_BASE; |
15719 | 15714 | ||
15720 | tp->coalesce_mode = 0; | 15715 | tp->coalesce_mode = 0; |
15721 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && | 15716 | if (tg3_chip_rev(tp) != CHIPREV_5700_AX && |
15722 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | 15717 | tg3_chip_rev(tp) != CHIPREV_5700_BX) |
15723 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | 15718 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; |
15724 | 15719 | ||
15725 | /* Set these bits to enable statistics workaround. */ | 15720 | /* Set these bits to enable statistics workaround. */ |
15726 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 15721 | if (tg3_asic_rev(tp) == ASIC_REV_5717 || |
15727 | tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || | 15722 | tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || |
15728 | tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) { | 15723 | tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) { |
15729 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; | 15724 | tp->coalesce_mode |= HOSTCC_MODE_ATTN; |
15730 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; | 15725 | tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; |
15731 | } | 15726 | } |
15732 | 15727 | ||
15733 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | 15728 | if (tg3_asic_rev(tp) == ASIC_REV_5785 || |
15734 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | 15729 | tg3_asic_rev(tp) == ASIC_REV_57780) |
15735 | tg3_flag_set(tp, USE_PHYLIB); | 15730 | tg3_flag_set(tp, USE_PHYLIB); |
15736 | 15731 | ||
15737 | err = tg3_mdio_init(tp); | 15732 | err = tg3_mdio_init(tp); |
@@ -15740,8 +15735,8 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15740 | 15735 | ||
15741 | /* Initialize data/descriptor byte/word swapping. */ | 15736 | /* Initialize data/descriptor byte/word swapping. */ |
15742 | val = tr32(GRC_MODE); | 15737 | val = tr32(GRC_MODE); |
15743 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | 15738 | if (tg3_asic_rev(tp) == ASIC_REV_5720 || |
15744 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 15739 | tg3_asic_rev(tp) == ASIC_REV_5762) |
15745 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | | 15740 | val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA | |
15746 | GRC_MODE_WORD_SWAP_B2HRX_DATA | | 15741 | GRC_MODE_WORD_SWAP_B2HRX_DATA | |
15747 | GRC_MODE_B2HRX_ENABLE | | 15742 | GRC_MODE_B2HRX_ENABLE | |
@@ -15761,10 +15756,10 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15761 | &pci_state_reg); | 15756 | &pci_state_reg); |
15762 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | 15757 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && |
15763 | !tg3_flag(tp, PCIX_TARGET_HWBUG)) { | 15758 | !tg3_flag(tp, PCIX_TARGET_HWBUG)) { |
15764 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | 15759 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || |
15765 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | 15760 | tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || |
15766 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2 || | 15761 | tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 || |
15767 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B5) { | 15762 | tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) { |
15768 | void __iomem *sram_base; | 15763 | void __iomem *sram_base; |
15769 | 15764 | ||
15770 | /* Write some dummy words into the SRAM status block | 15765 | /* Write some dummy words into the SRAM status block |
@@ -15787,13 +15782,13 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15787 | grc_misc_cfg = tr32(GRC_MISC_CFG); | 15782 | grc_misc_cfg = tr32(GRC_MISC_CFG); |
15788 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | 15783 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; |
15789 | 15784 | ||
15790 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | 15785 | if (tg3_asic_rev(tp) == ASIC_REV_5705 && |
15791 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | 15786 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || |
15792 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | 15787 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) |
15793 | tg3_flag_set(tp, IS_5788); | 15788 | tg3_flag_set(tp, IS_5788); |
15794 | 15789 | ||
15795 | if (!tg3_flag(tp, IS_5788) && | 15790 | if (!tg3_flag(tp, IS_5788) && |
15796 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) | 15791 | tg3_asic_rev(tp) != ASIC_REV_5700) |
15797 | tg3_flag_set(tp, TAGGED_STATUS); | 15792 | tg3_flag_set(tp, TAGGED_STATUS); |
15798 | if (tg3_flag(tp, TAGGED_STATUS)) { | 15793 | if (tg3_flag(tp, TAGGED_STATUS)) { |
15799 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | | 15794 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | |
@@ -15826,7 +15821,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15826 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { | 15821 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
15827 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | 15822 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
15828 | } else { | 15823 | } else { |
15829 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | 15824 | if (tg3_asic_rev(tp) == ASIC_REV_5700) |
15830 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | 15825 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
15831 | else | 15826 | else |
15832 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; | 15827 | tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; |
@@ -15836,7 +15831,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15836 | * change bit implementation, so we must use the | 15831 | * change bit implementation, so we must use the |
15837 | * status register in those cases. | 15832 | * status register in those cases. |
15838 | */ | 15833 | */ |
15839 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | 15834 | if (tg3_asic_rev(tp) == ASIC_REV_5700) |
15840 | tg3_flag_set(tp, USE_LINKCHG_REG); | 15835 | tg3_flag_set(tp, USE_LINKCHG_REG); |
15841 | else | 15836 | else |
15842 | tg3_flag_clear(tp, USE_LINKCHG_REG); | 15837 | tg3_flag_clear(tp, USE_LINKCHG_REG); |
@@ -15846,7 +15841,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15846 | * upon subsystem IDs. | 15841 | * upon subsystem IDs. |
15847 | */ | 15842 | */ |
15848 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | 15843 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && |
15849 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && | 15844 | tg3_asic_rev(tp) == ASIC_REV_5701 && |
15850 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { | 15845 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { |
15851 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; | 15846 | tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; |
15852 | tg3_flag_set(tp, USE_LINKCHG_REG); | 15847 | tg3_flag_set(tp, USE_LINKCHG_REG); |
@@ -15860,7 +15855,7 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15860 | 15855 | ||
15861 | tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; | 15856 | tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; |
15862 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; | 15857 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
15863 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && | 15858 | if (tg3_asic_rev(tp) == ASIC_REV_5701 && |
15864 | tg3_flag(tp, PCIX_MODE)) { | 15859 | tg3_flag(tp, PCIX_MODE)) { |
15865 | tp->rx_offset = NET_SKB_PAD; | 15860 | tp->rx_offset = NET_SKB_PAD; |
15866 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | 15861 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
@@ -15877,9 +15872,9 @@ static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) | |||
15877 | /* Increment the rx prod index on the rx std ring by at most | 15872 | /* Increment the rx prod index on the rx std ring by at most |
15878 | * 8 for these chips to workaround hw errata. | 15873 | * 8 for these chips to workaround hw errata. |
15879 | */ | 15874 | */ |
15880 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | 15875 | if (tg3_asic_rev(tp) == ASIC_REV_5750 || |
15881 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | 15876 | tg3_asic_rev(tp) == ASIC_REV_5752 || |
15882 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | 15877 | tg3_asic_rev(tp) == ASIC_REV_5755) |
15883 | tp->rx_std_max_post = 8; | 15878 | tp->rx_std_max_post = 8; |
15884 | 15879 | ||
15885 | if (tg3_flag(tp, ASPM_WORKAROUND)) | 15880 | if (tg3_flag(tp, ASPM_WORKAROUND)) |
@@ -15934,7 +15929,7 @@ static int tg3_get_device_address(struct tg3 *tp) | |||
15934 | } | 15929 | } |
15935 | 15930 | ||
15936 | mac_offset = 0x7c; | 15931 | mac_offset = 0x7c; |
15937 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | 15932 | if (tg3_asic_rev(tp) == ASIC_REV_5704 || |
15938 | tg3_flag(tp, 5780_CLASS)) { | 15933 | tg3_flag(tp, 5780_CLASS)) { |
15939 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | 15934 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
15940 | mac_offset = 0xcc; | 15935 | mac_offset = 0xcc; |
@@ -15947,7 +15942,7 @@ static int tg3_get_device_address(struct tg3 *tp) | |||
15947 | mac_offset = 0xcc; | 15942 | mac_offset = 0xcc; |
15948 | if (tp->pci_fn > 1) | 15943 | if (tp->pci_fn > 1) |
15949 | mac_offset += 0x18c; | 15944 | mac_offset += 0x18c; |
15950 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | 15945 | } else if (tg3_asic_rev(tp) == ASIC_REV_5906) |
15951 | mac_offset = 0x10; | 15946 | mac_offset = 0x10; |
15952 | 15947 | ||
15953 | /* First try to get it from MAC address mailbox. */ | 15948 | /* First try to get it from MAC address mailbox. */ |
@@ -16015,8 +16010,8 @@ static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |||
16015 | /* On 5703 and later chips, the boundary bits have no | 16010 | /* On 5703 and later chips, the boundary bits have no |
16016 | * effect. | 16011 | * effect. |
16017 | */ | 16012 | */ |
16018 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | 16013 | if (tg3_asic_rev(tp) != ASIC_REV_5700 && |
16019 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | 16014 | tg3_asic_rev(tp) != ASIC_REV_5701 && |
16020 | !tg3_flag(tp, PCI_EXPRESS)) | 16015 | !tg3_flag(tp, PCI_EXPRESS)) |
16021 | goto out; | 16016 | goto out; |
16022 | 16017 | ||
@@ -16254,14 +16249,14 @@ static int tg3_test_dma(struct tg3 *tp) | |||
16254 | /* DMA read watermark not used on PCIE */ | 16249 | /* DMA read watermark not used on PCIE */ |
16255 | tp->dma_rwctrl |= 0x00180000; | 16250 | tp->dma_rwctrl |= 0x00180000; |
16256 | } else if (!tg3_flag(tp, PCIX_MODE)) { | 16251 | } else if (!tg3_flag(tp, PCIX_MODE)) { |
16257 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || | 16252 | if (tg3_asic_rev(tp) == ASIC_REV_5705 || |
16258 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | 16253 | tg3_asic_rev(tp) == ASIC_REV_5750) |
16259 | tp->dma_rwctrl |= 0x003f0000; | 16254 | tp->dma_rwctrl |= 0x003f0000; |
16260 | else | 16255 | else |
16261 | tp->dma_rwctrl |= 0x003f000f; | 16256 | tp->dma_rwctrl |= 0x003f000f; |
16262 | } else { | 16257 | } else { |
16263 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | 16258 | if (tg3_asic_rev(tp) == ASIC_REV_5703 || |
16264 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | 16259 | tg3_asic_rev(tp) == ASIC_REV_5704) { |
16265 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | 16260 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); |
16266 | u32 read_water = 0x7; | 16261 | u32 read_water = 0x7; |
16267 | 16262 | ||
@@ -16270,22 +16265,22 @@ static int tg3_test_dma(struct tg3 *tp) | |||
16270 | * better performance. | 16265 | * better performance. |
16271 | */ | 16266 | */ |
16272 | if (tg3_flag(tp, 40BIT_DMA_BUG) && | 16267 | if (tg3_flag(tp, 40BIT_DMA_BUG) && |
16273 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | 16268 | tg3_asic_rev(tp) == ASIC_REV_5704) |
16274 | tp->dma_rwctrl |= 0x8000; | 16269 | tp->dma_rwctrl |= 0x8000; |
16275 | else if (ccval == 0x6 || ccval == 0x7) | 16270 | else if (ccval == 0x6 || ccval == 0x7) |
16276 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; | 16271 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
16277 | 16272 | ||
16278 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) | 16273 | if (tg3_asic_rev(tp) == ASIC_REV_5703) |
16279 | read_water = 4; | 16274 | read_water = 4; |
16280 | /* Set bit 23 to enable PCIX hw bug fix */ | 16275 | /* Set bit 23 to enable PCIX hw bug fix */ |
16281 | tp->dma_rwctrl |= | 16276 | tp->dma_rwctrl |= |
16282 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | 16277 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | |
16283 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | 16278 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | |
16284 | (1 << 23); | 16279 | (1 << 23); |
16285 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { | 16280 | } else if (tg3_asic_rev(tp) == ASIC_REV_5780) { |
16286 | /* 5780 always in PCIX mode */ | 16281 | /* 5780 always in PCIX mode */ |
16287 | tp->dma_rwctrl |= 0x00144000; | 16282 | tp->dma_rwctrl |= 0x00144000; |
16288 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | 16283 | } else if (tg3_asic_rev(tp) == ASIC_REV_5714) { |
16289 | /* 5714 always in PCIX mode */ | 16284 | /* 5714 always in PCIX mode */ |
16290 | tp->dma_rwctrl |= 0x00148000; | 16285 | tp->dma_rwctrl |= 0x00148000; |
16291 | } else { | 16286 | } else { |
@@ -16295,12 +16290,12 @@ static int tg3_test_dma(struct tg3 *tp) | |||
16295 | if (tg3_flag(tp, ONE_DMA_AT_ONCE)) | 16290 | if (tg3_flag(tp, ONE_DMA_AT_ONCE)) |
16296 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; | 16291 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
16297 | 16292 | ||
16298 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | 16293 | if (tg3_asic_rev(tp) == ASIC_REV_5703 || |
16299 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | 16294 | tg3_asic_rev(tp) == ASIC_REV_5704) |
16300 | tp->dma_rwctrl &= 0xfffffff0; | 16295 | tp->dma_rwctrl &= 0xfffffff0; |
16301 | 16296 | ||
16302 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 16297 | if (tg3_asic_rev(tp) == ASIC_REV_5700 || |
16303 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | 16298 | tg3_asic_rev(tp) == ASIC_REV_5701) { |
16304 | /* Remove this if it causes problems for some boards. */ | 16299 | /* Remove this if it causes problems for some boards. */ |
16305 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | 16300 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; |
16306 | 16301 | ||
@@ -16324,8 +16319,8 @@ static int tg3_test_dma(struct tg3 *tp) | |||
16324 | tg3_switch_clocks(tp); | 16319 | tg3_switch_clocks(tp); |
16325 | #endif | 16320 | #endif |
16326 | 16321 | ||
16327 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | 16322 | if (tg3_asic_rev(tp) != ASIC_REV_5700 && |
16328 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | 16323 | tg3_asic_rev(tp) != ASIC_REV_5701) |
16329 | goto out; | 16324 | goto out; |
16330 | 16325 | ||
16331 | /* It is best to perform DMA test with maximum write burst size | 16326 | /* It is best to perform DMA test with maximum write burst size |
@@ -16444,7 +16439,7 @@ static void tg3_init_bufmgr_config(struct tg3 *tp) | |||
16444 | DEFAULT_MB_MACRX_LOW_WATER_5705; | 16439 | DEFAULT_MB_MACRX_LOW_WATER_5705; |
16445 | tp->bufmgr_config.mbuf_high_water = | 16440 | tp->bufmgr_config.mbuf_high_water = |
16446 | DEFAULT_MB_HIGH_WATER_5705; | 16441 | DEFAULT_MB_HIGH_WATER_5705; |
16447 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { | 16442 | if (tg3_asic_rev(tp) == ASIC_REV_5906) { |
16448 | tp->bufmgr_config.mbuf_mac_rx_low_water = | 16443 | tp->bufmgr_config.mbuf_mac_rx_low_water = |
16449 | DEFAULT_MB_MACRX_LOW_WATER_5906; | 16444 | DEFAULT_MB_MACRX_LOW_WATER_5906; |
16450 | tp->bufmgr_config.mbuf_high_water = | 16445 | tp->bufmgr_config.mbuf_high_water = |
@@ -16766,7 +16761,7 @@ static int tg3_init_one(struct pci_dev *pdev, | |||
16766 | /* 5700 B0 chips do not support checksumming correctly due | 16761 | /* 5700 B0 chips do not support checksumming correctly due |
16767 | * to hardware bugs. | 16762 | * to hardware bugs. |
16768 | */ | 16763 | */ |
16769 | if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) { | 16764 | if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) { |
16770 | features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; | 16765 | features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; |
16771 | 16766 | ||
16772 | if (tg3_flag(tp, 5755_PLUS)) | 16767 | if (tg3_flag(tp, 5755_PLUS)) |
@@ -16786,11 +16781,11 @@ static int tg3_init_one(struct pci_dev *pdev, | |||
16786 | if (features & NETIF_F_IPV6_CSUM) | 16781 | if (features & NETIF_F_IPV6_CSUM) |
16787 | features |= NETIF_F_TSO6; | 16782 | features |= NETIF_F_TSO6; |
16788 | if (tg3_flag(tp, HW_TSO_3) || | 16783 | if (tg3_flag(tp, HW_TSO_3) || |
16789 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | 16784 | tg3_asic_rev(tp) == ASIC_REV_5761 || |
16790 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | 16785 | (tg3_asic_rev(tp) == ASIC_REV_5784 && |
16791 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | 16786 | tg3_chip_rev(tp) != CHIPREV_5784_AX) || |
16792 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | 16787 | tg3_asic_rev(tp) == ASIC_REV_5785 || |
16793 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | 16788 | tg3_asic_rev(tp) == ASIC_REV_57780) |
16794 | features |= NETIF_F_TSO_ECN; | 16789 | features |= NETIF_F_TSO_ECN; |
16795 | } | 16790 | } |
16796 | 16791 | ||
@@ -16802,14 +16797,14 @@ static int tg3_init_one(struct pci_dev *pdev, | |||
16802 | * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY | 16797 | * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY |
16803 | * loopback for the remaining devices. | 16798 | * loopback for the remaining devices. |
16804 | */ | 16799 | */ |
16805 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 && | 16800 | if (tg3_asic_rev(tp) != ASIC_REV_5780 && |
16806 | !tg3_flag(tp, CPMU_PRESENT)) | 16801 | !tg3_flag(tp, CPMU_PRESENT)) |
16807 | /* Add the loopback capability */ | 16802 | /* Add the loopback capability */ |
16808 | features |= NETIF_F_LOOPBACK; | 16803 | features |= NETIF_F_LOOPBACK; |
16809 | 16804 | ||
16810 | dev->hw_features |= features; | 16805 | dev->hw_features |= features; |
16811 | 16806 | ||
16812 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && | 16807 | if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 && |
16813 | !tg3_flag(tp, TSO_CAPABLE) && | 16808 | !tg3_flag(tp, TSO_CAPABLE) && |
16814 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { | 16809 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { |
16815 | tg3_flag_set(tp, MAX_RXPEND_64); | 16810 | tg3_flag_set(tp, MAX_RXPEND_64); |
@@ -16888,9 +16883,9 @@ static int tg3_init_one(struct pci_dev *pdev, | |||
16888 | 16883 | ||
16889 | pci_set_drvdata(pdev, dev); | 16884 | pci_set_drvdata(pdev, dev); |
16890 | 16885 | ||
16891 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | 16886 | if (tg3_asic_rev(tp) == ASIC_REV_5719 || |
16892 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 || | 16887 | tg3_asic_rev(tp) == ASIC_REV_5720 || |
16893 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5762) | 16888 | tg3_asic_rev(tp) == ASIC_REV_5762) |
16894 | tg3_flag_set(tp, PTP_CAPABLE); | 16889 | tg3_flag_set(tp, PTP_CAPABLE); |
16895 | 16890 | ||
16896 | if (tg3_flag(tp, 5717_PLUS)) { | 16891 | if (tg3_flag(tp, 5717_PLUS)) { |
@@ -16910,7 +16905,7 @@ static int tg3_init_one(struct pci_dev *pdev, | |||
16910 | 16905 | ||
16911 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", | 16906 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
16912 | tp->board_part_number, | 16907 | tp->board_part_number, |
16913 | tp->pci_chip_rev_id, | 16908 | tg3_chip_rev_id(tp), |
16914 | tg3_bus_string(tp, str), | 16909 | tg3_bus_string(tp, str), |
16915 | dev->dev_addr); | 16910 | dev->dev_addr); |
16916 | 16911 | ||
diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h index 3e27f2efbfe0..8d7d4c2ab5d6 100644 --- a/drivers/net/ethernet/broadcom/tg3.h +++ b/drivers/net/ethernet/broadcom/tg3.h | |||
@@ -161,7 +161,7 @@ | |||
161 | #define CHIPREV_ID_5719_A0 0x05719000 | 161 | #define CHIPREV_ID_5719_A0 0x05719000 |
162 | #define CHIPREV_ID_5720_A0 0x05720000 | 162 | #define CHIPREV_ID_5720_A0 0x05720000 |
163 | #define CHIPREV_ID_5762_A0 0x05762000 | 163 | #define CHIPREV_ID_5762_A0 0x05762000 |
164 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) | 164 | |
165 | #define ASIC_REV_5700 0x07 | 165 | #define ASIC_REV_5700 0x07 |
166 | #define ASIC_REV_5701 0x00 | 166 | #define ASIC_REV_5701 0x00 |
167 | #define ASIC_REV_5703 0x01 | 167 | #define ASIC_REV_5703 0x01 |
@@ -185,7 +185,6 @@ | |||
185 | #define ASIC_REV_5720 0x5720 | 185 | #define ASIC_REV_5720 0x5720 |
186 | #define ASIC_REV_57766 0x57766 | 186 | #define ASIC_REV_57766 0x57766 |
187 | #define ASIC_REV_5762 0x5762 | 187 | #define ASIC_REV_5762 0x5762 |
188 | #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) | ||
189 | #define CHIPREV_5700_AX 0x70 | 188 | #define CHIPREV_5700_AX 0x70 |
190 | #define CHIPREV_5700_BX 0x71 | 189 | #define CHIPREV_5700_BX 0x71 |
191 | #define CHIPREV_5700_CX 0x72 | 190 | #define CHIPREV_5700_CX 0x72 |
@@ -198,7 +197,6 @@ | |||
198 | #define CHIPREV_5784_AX 0x57840 | 197 | #define CHIPREV_5784_AX 0x57840 |
199 | #define CHIPREV_5761_AX 0x57610 | 198 | #define CHIPREV_5761_AX 0x57610 |
200 | #define CHIPREV_57765_AX 0x577650 | 199 | #define CHIPREV_57765_AX 0x577650 |
201 | #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff) | ||
202 | #define METAL_REV_A0 0x00 | 200 | #define METAL_REV_A0 0x00 |
203 | #define METAL_REV_A1 0x01 | 201 | #define METAL_REV_A1 0x01 |
204 | #define METAL_REV_B0 0x00 | 202 | #define METAL_REV_B0 0x00 |
@@ -3357,4 +3355,18 @@ struct tg3 { | |||
3357 | bool link_up; | 3355 | bool link_up; |
3358 | }; | 3356 | }; |
3359 | 3357 | ||
3358 | /* Accessor macros for chip and asic attributes | ||
3359 | * | ||
3360 | * nb: Using static inlines equivalent to the accessor macros generates | ||
3361 | * larger object code with gcc 4.7. | ||
3362 | * Using statement expression macros to check tp with | ||
3363 | * typecheck(struct tg3 *, tp) also creates larger objects. | ||
3364 | */ | ||
3365 | #define tg3_chip_rev_id(tp) \ | ||
3366 | ((tp)->pci_chip_rev_id) | ||
3367 | #define tg3_asic_rev(tp) \ | ||
3368 | ((tp)->pci_chip_rev_id >> 12) | ||
3369 | #define tg3_chip_rev(tp) \ | ||
3370 | ((tp)->pci_chip_rev_id >> 8) | ||
3371 | |||
3360 | #endif /* !(_T3_H) */ | 3372 | #endif /* !(_T3_H) */ |