diff options
-rw-r--r-- | arch/arm/mach-pxa/mainstone.c | 19 | ||||
-rw-r--r-- | drivers/pcmcia/pxa2xx_mainstone.c | 18 |
2 files changed, 19 insertions, 18 deletions
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index b02c79c7e6a3..a4bc3483cbb3 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c | |||
@@ -444,6 +444,25 @@ static void __init mainstone_init(void) | |||
444 | */ | 444 | */ |
445 | pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD); | 445 | pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD); |
446 | 446 | ||
447 | GPSR(GPIO48_nPOE) = | ||
448 | GPIO_bit(GPIO48_nPOE) | | ||
449 | GPIO_bit(GPIO49_nPWE) | | ||
450 | GPIO_bit(GPIO50_nPIOR) | | ||
451 | GPIO_bit(GPIO51_nPIOW) | | ||
452 | GPIO_bit(GPIO85_nPCE_1) | | ||
453 | GPIO_bit(GPIO54_nPCE_2); | ||
454 | |||
455 | pxa_gpio_mode(GPIO48_nPOE_MD); | ||
456 | pxa_gpio_mode(GPIO49_nPWE_MD); | ||
457 | pxa_gpio_mode(GPIO50_nPIOR_MD); | ||
458 | pxa_gpio_mode(GPIO51_nPIOW_MD); | ||
459 | pxa_gpio_mode(GPIO85_nPCE_1_MD); | ||
460 | pxa_gpio_mode(GPIO54_nPCE_2_MD); | ||
461 | pxa_gpio_mode(GPIO79_pSKTSEL_MD); | ||
462 | pxa_gpio_mode(GPIO55_nPREG_MD); | ||
463 | pxa_gpio_mode(GPIO56_nPWAIT_MD); | ||
464 | pxa_gpio_mode(GPIO57_nIOIS16_MD); | ||
465 | |||
447 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 466 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
448 | 467 | ||
449 | /* reading Mainstone's "Virtual Configuration Register" | 468 | /* reading Mainstone's "Virtual Configuration Register" |
diff --git a/drivers/pcmcia/pxa2xx_mainstone.c b/drivers/pcmcia/pxa2xx_mainstone.c index 383107ba4bd3..36c671c5fb65 100644 --- a/drivers/pcmcia/pxa2xx_mainstone.c +++ b/drivers/pcmcia/pxa2xx_mainstone.c | |||
@@ -43,24 +43,6 @@ static int mst_pcmcia_hw_init(struct soc_pcmcia_socket *skt) | |||
43 | * Setup default state of GPIO outputs | 43 | * Setup default state of GPIO outputs |
44 | * before we enable them as outputs. | 44 | * before we enable them as outputs. |
45 | */ | 45 | */ |
46 | GPSR(GPIO48_nPOE) = | ||
47 | GPIO_bit(GPIO48_nPOE) | | ||
48 | GPIO_bit(GPIO49_nPWE) | | ||
49 | GPIO_bit(GPIO50_nPIOR) | | ||
50 | GPIO_bit(GPIO51_nPIOW) | | ||
51 | GPIO_bit(GPIO85_nPCE_1) | | ||
52 | GPIO_bit(GPIO54_nPCE_2); | ||
53 | |||
54 | pxa_gpio_mode(GPIO48_nPOE_MD); | ||
55 | pxa_gpio_mode(GPIO49_nPWE_MD); | ||
56 | pxa_gpio_mode(GPIO50_nPIOR_MD); | ||
57 | pxa_gpio_mode(GPIO51_nPIOW_MD); | ||
58 | pxa_gpio_mode(GPIO85_nPCE_1_MD); | ||
59 | pxa_gpio_mode(GPIO54_nPCE_2_MD); | ||
60 | pxa_gpio_mode(GPIO79_pSKTSEL_MD); | ||
61 | pxa_gpio_mode(GPIO55_nPREG_MD); | ||
62 | pxa_gpio_mode(GPIO56_nPWAIT_MD); | ||
63 | pxa_gpio_mode(GPIO57_nIOIS16_MD); | ||
64 | 46 | ||
65 | skt->irq = (skt->nr == 0) ? MAINSTONE_S0_IRQ : MAINSTONE_S1_IRQ; | 47 | skt->irq = (skt->nr == 0) ? MAINSTONE_S0_IRQ : MAINSTONE_S1_IRQ; |
66 | return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs)); | 48 | return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs)); |