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-rw-r--r--drivers/ata/Makefile2
-rw-r--r--drivers/ata/ahci.c2280
-rw-r--r--drivers/ata/ahci.h332
-rw-r--r--drivers/ata/libahci.c2091
4 files changed, 2425 insertions, 2280 deletions
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index fc936d4471d6..20c5251e7e41 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -1,7 +1,7 @@
1 1
2obj-$(CONFIG_ATA) += libata.o 2obj-$(CONFIG_ATA) += libata.o
3 3
4obj-$(CONFIG_SATA_AHCI) += ahci.o 4obj-$(CONFIG_SATA_AHCI) += ahci.o libahci.o
5obj-$(CONFIG_SATA_SVW) += sata_svw.o 5obj-$(CONFIG_SATA_SVW) += sata_svw.o
6obj-$(CONFIG_ATA_PIIX) += ata_piix.o 6obj-$(CONFIG_ATA_PIIX) += ata_piix.o
7obj-$(CONFIG_SATA_PROMISE) += sata_promise.o 7obj-$(CONFIG_SATA_PROMISE) += sata_promise.o
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index d5dc1238a88d..feaefb84ffa2 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -46,67 +46,13 @@
46#include <scsi/scsi_host.h> 46#include <scsi/scsi_host.h>
47#include <scsi/scsi_cmnd.h> 47#include <scsi/scsi_cmnd.h>
48#include <linux/libata.h> 48#include <linux/libata.h>
49#include "ahci.h"
49 50
50#define DRV_NAME "ahci" 51#define DRV_NAME "ahci"
51#define DRV_VERSION "3.0" 52#define DRV_VERSION "3.0"
52 53
53/* Enclosure Management Control */
54#define EM_CTRL_MSG_TYPE 0x000f0000
55
56/* Enclosure Management LED Message Type */
57#define EM_MSG_LED_HBA_PORT 0x0000000f
58#define EM_MSG_LED_PMP_SLOT 0x0000ff00
59#define EM_MSG_LED_VALUE 0xffff0000
60#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
61#define EM_MSG_LED_VALUE_OFF 0xfff80000
62#define EM_MSG_LED_VALUE_ON 0x00010000
63
64static int ahci_skip_host_reset;
65static int ahci_ignore_sss;
66
67module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
68MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
69
70module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
71MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
72
73static int ahci_enable_alpm(struct ata_port *ap,
74 enum link_pm policy);
75static void ahci_disable_alpm(struct ata_port *ap);
76static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
77static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
78 size_t size);
79static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
80 ssize_t size);
81
82enum { 54enum {
83 AHCI_PCI_BAR = 5, 55 AHCI_PCI_BAR = 5,
84 AHCI_MAX_PORTS = 32,
85 AHCI_MAX_SG = 168, /* hardware max is 64K */
86 AHCI_DMA_BOUNDARY = 0xffffffff,
87 AHCI_MAX_CMDS = 32,
88 AHCI_CMD_SZ = 32,
89 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
90 AHCI_RX_FIS_SZ = 256,
91 AHCI_CMD_TBL_CDB = 0x40,
92 AHCI_CMD_TBL_HDR_SZ = 0x80,
93 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
94 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
95 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
96 AHCI_RX_FIS_SZ,
97 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
98 AHCI_CMD_TBL_AR_SZ +
99 (AHCI_RX_FIS_SZ * 16),
100 AHCI_IRQ_ON_SG = (1 << 31),
101 AHCI_CMD_ATAPI = (1 << 5),
102 AHCI_CMD_WRITE = (1 << 6),
103 AHCI_CMD_PREFETCH = (1 << 7),
104 AHCI_CMD_RESET = (1 << 8),
105 AHCI_CMD_CLR_BUSY = (1 << 10),
106
107 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
108 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
109 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
110 56
111 board_ahci = 0, 57 board_ahci = 0,
112 board_ahci_vt8251 = 1, 58 board_ahci_vt8251 = 1,
@@ -118,332 +64,19 @@ enum {
118 board_ahci_nopmp = 7, 64 board_ahci_nopmp = 7,
119 board_ahci_yesncq = 8, 65 board_ahci_yesncq = 8,
120 board_ahci_nosntf = 9, 66 board_ahci_nosntf = 9,
121
122 /* global controller registers */
123 HOST_CAP = 0x00, /* host capabilities */
124 HOST_CTL = 0x04, /* global host control */
125 HOST_IRQ_STAT = 0x08, /* interrupt status */
126 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
127 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
128 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
129 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
130 HOST_CAP2 = 0x24, /* host capabilities, extended */
131
132 /* HOST_CTL bits */
133 HOST_RESET = (1 << 0), /* reset controller; self-clear */
134 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
135 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
136
137 /* HOST_CAP bits */
138 HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
139 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
140 HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
141 HOST_CAP_PART = (1 << 13), /* Partial state capable */
142 HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
143 HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
144 HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
145 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
146 HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
147 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
148 HOST_CAP_LED = (1 << 25), /* Supports activity LED */
149 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
150 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
151 HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
152 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
153 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
154 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
155
156 /* HOST_CAP2 bits */
157 HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
158 HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
159 HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
160
161 /* registers for each SATA port */
162 PORT_LST_ADDR = 0x00, /* command list DMA addr */
163 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
164 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
165 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
166 PORT_IRQ_STAT = 0x10, /* interrupt status */
167 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
168 PORT_CMD = 0x18, /* port command */
169 PORT_TFDATA = 0x20, /* taskfile data */
170 PORT_SIG = 0x24, /* device TF signature */
171 PORT_CMD_ISSUE = 0x38, /* command issue */
172 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
173 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
174 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
175 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
176 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
177 PORT_FBS = 0x40, /* FIS-based Switching */
178
179 /* PORT_IRQ_{STAT,MASK} bits */
180 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
181 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
182 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
183 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
184 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
185 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
186 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
187 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
188
189 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
190 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
191 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
192 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
193 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
194 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
195 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
196 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
197 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
198
199 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
200 PORT_IRQ_IF_ERR |
201 PORT_IRQ_CONNECT |
202 PORT_IRQ_PHYRDY |
203 PORT_IRQ_UNK_FIS |
204 PORT_IRQ_BAD_PMP,
205 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
206 PORT_IRQ_TF_ERR |
207 PORT_IRQ_HBUS_DATA_ERR,
208 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
209 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
210 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
211
212 /* PORT_CMD bits */
213 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
214 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
215 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
216 PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
217 PORT_CMD_PMP = (1 << 17), /* PMP attached */
218 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
219 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
220 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
221 PORT_CMD_CLO = (1 << 3), /* Command list override */
222 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
223 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
224 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
225
226 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
227 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
228 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
229 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
230
231 PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
232 PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
233 PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
234 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
235 PORT_FBS_SDE = (1 << 2), /* FBS single device error */
236 PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
237 PORT_FBS_EN = (1 << 0), /* Enable FBS */
238
239 /* hpriv->flags bits */
240 AHCI_HFLAG_NO_NCQ = (1 << 0),
241 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
242 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
243 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
244 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
245 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
246 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
247 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
248 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
249 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
250 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
251 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
252 link offline */
253 AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
254
255 /* ap->flags bits */
256
257 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
258 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
259 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
260 ATA_FLAG_IPM,
261
262 ICH_MAP = 0x90, /* ICH MAP register */
263
264 /* em constants */
265 EM_MAX_SLOTS = 8,
266 EM_MAX_RETRY = 5,
267
268 /* em_ctl bits */
269 EM_CTL_RST = (1 << 9), /* Reset */
270 EM_CTL_TM = (1 << 8), /* Transmit Message */
271 EM_CTL_ALHD = (1 << 26), /* Activity LED */
272};
273
274struct ahci_cmd_hdr {
275 __le32 opts;
276 __le32 status;
277 __le32 tbl_addr;
278 __le32 tbl_addr_hi;
279 __le32 reserved[4];
280};
281
282struct ahci_sg {
283 __le32 addr;
284 __le32 addr_hi;
285 __le32 reserved;
286 __le32 flags_size;
287};
288
289struct ahci_em_priv {
290 enum sw_activity blink_policy;
291 struct timer_list timer;
292 unsigned long saved_activity;
293 unsigned long activity;
294 unsigned long led_state;
295}; 67};
296 68
297struct ahci_host_priv {
298 void __iomem * mmio; /* bus-independant mem map */
299 unsigned int flags; /* AHCI_HFLAG_* */
300 u32 cap; /* cap to use */
301 u32 cap2; /* cap2 to use */
302 u32 port_map; /* port map to use */
303 u32 saved_cap; /* saved initial cap */
304 u32 saved_cap2; /* saved initial cap2 */
305 u32 saved_port_map; /* saved initial port_map */
306 u32 em_loc; /* enclosure management location */
307};
308
309struct ahci_port_priv {
310 struct ata_link *active_link;
311 struct ahci_cmd_hdr *cmd_slot;
312 dma_addr_t cmd_slot_dma;
313 void *cmd_tbl;
314 dma_addr_t cmd_tbl_dma;
315 void *rx_fis;
316 dma_addr_t rx_fis_dma;
317 /* for NCQ spurious interrupt analysis */
318 unsigned int ncq_saw_d2h:1;
319 unsigned int ncq_saw_dmas:1;
320 unsigned int ncq_saw_sdb:1;
321 u32 intr_mask; /* interrupts to enable */
322 bool fbs_supported; /* set iff FBS is supported */
323 bool fbs_enabled; /* set iff FBS is enabled */
324 int fbs_last_dev; /* save FBS.DEV of last FIS */
325 /* enclosure management info per PM slot */
326 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
327};
328
329static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
330static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
331static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 69static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
332static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
333static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
334static int ahci_port_start(struct ata_port *ap);
335static void ahci_port_stop(struct ata_port *ap);
336static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
337static void ahci_qc_prep(struct ata_queued_cmd *qc);
338static void ahci_freeze(struct ata_port *ap);
339static void ahci_thaw(struct ata_port *ap);
340static void ahci_enable_fbs(struct ata_port *ap);
341static void ahci_disable_fbs(struct ata_port *ap);
342static void ahci_pmp_attach(struct ata_port *ap);
343static void ahci_pmp_detach(struct ata_port *ap);
344static int ahci_softreset(struct ata_link *link, unsigned int *class,
345 unsigned long deadline);
346static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class, 70static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
347 unsigned long deadline); 71 unsigned long deadline);
348static int ahci_hardreset(struct ata_link *link, unsigned int *class,
349 unsigned long deadline);
350static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 72static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
351 unsigned long deadline); 73 unsigned long deadline);
352static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 74static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
353 unsigned long deadline); 75 unsigned long deadline);
354static void ahci_postreset(struct ata_link *link, unsigned int *class);
355static void ahci_error_handler(struct ata_port *ap);
356static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
357static int ahci_port_resume(struct ata_port *ap);
358static void ahci_dev_config(struct ata_device *dev);
359static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
360 u32 opts);
361#ifdef CONFIG_PM 76#ifdef CONFIG_PM
362static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
363static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); 77static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
364static int ahci_pci_device_resume(struct pci_dev *pdev); 78static int ahci_pci_device_resume(struct pci_dev *pdev);
365#endif 79#endif
366static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
367static ssize_t ahci_activity_store(struct ata_device *dev,
368 enum sw_activity val);
369static void ahci_init_sw_activity(struct ata_link *link);
370
371static ssize_t ahci_show_host_caps(struct device *dev,
372 struct device_attribute *attr, char *buf);
373static ssize_t ahci_show_host_cap2(struct device *dev,
374 struct device_attribute *attr, char *buf);
375static ssize_t ahci_show_host_version(struct device *dev,
376 struct device_attribute *attr, char *buf);
377static ssize_t ahci_show_port_cmd(struct device *dev,
378 struct device_attribute *attr, char *buf);
379
380static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
381static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
382static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
383static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
384
385static struct device_attribute *ahci_shost_attrs[] = {
386 &dev_attr_link_power_management_policy,
387 &dev_attr_em_message_type,
388 &dev_attr_em_message,
389 &dev_attr_ahci_host_caps,
390 &dev_attr_ahci_host_cap2,
391 &dev_attr_ahci_host_version,
392 &dev_attr_ahci_port_cmd,
393 NULL
394};
395
396static struct device_attribute *ahci_sdev_attrs[] = {
397 &dev_attr_sw_activity,
398 &dev_attr_unload_heads,
399 NULL
400};
401
402static struct scsi_host_template ahci_sht = {
403 ATA_NCQ_SHT(DRV_NAME),
404 .can_queue = AHCI_MAX_CMDS - 1,
405 .sg_tablesize = AHCI_MAX_SG,
406 .dma_boundary = AHCI_DMA_BOUNDARY,
407 .shost_attrs = ahci_shost_attrs,
408 .sdev_attrs = ahci_sdev_attrs,
409};
410
411static struct ata_port_operations ahci_ops = {
412 .inherits = &sata_pmp_port_ops,
413
414 .qc_defer = ahci_pmp_qc_defer,
415 .qc_prep = ahci_qc_prep,
416 .qc_issue = ahci_qc_issue,
417 .qc_fill_rtf = ahci_qc_fill_rtf,
418
419 .freeze = ahci_freeze,
420 .thaw = ahci_thaw,
421 .softreset = ahci_softreset,
422 .hardreset = ahci_hardreset,
423 .postreset = ahci_postreset,
424 .pmp_softreset = ahci_softreset,
425 .error_handler = ahci_error_handler,
426 .post_internal_cmd = ahci_post_internal_cmd,
427 .dev_config = ahci_dev_config,
428
429 .scr_read = ahci_scr_read,
430 .scr_write = ahci_scr_write,
431 .pmp_attach = ahci_pmp_attach,
432 .pmp_detach = ahci_pmp_detach,
433
434 .enable_pm = ahci_enable_alpm,
435 .disable_pm = ahci_disable_alpm,
436 .em_show = ahci_led_show,
437 .em_store = ahci_led_store,
438 .sw_activity_show = ahci_activity_show,
439 .sw_activity_store = ahci_activity_store,
440#ifdef CONFIG_PM
441 .port_suspend = ahci_port_suspend,
442 .port_resume = ahci_port_resume,
443#endif
444 .port_start = ahci_port_start,
445 .port_stop = ahci_port_stop,
446};
447 80
448static struct ata_port_operations ahci_vt8251_ops = { 81static struct ata_port_operations ahci_vt8251_ops = {
449 .inherits = &ahci_ops, 82 .inherits = &ahci_ops,
@@ -738,12 +371,6 @@ static struct pci_driver ahci_pci_driver = {
738#endif 371#endif
739}; 372};
740 373
741static int ahci_em_messages = 1;
742module_param(ahci_em_messages, int, 0444);
743/* add other LED protocol types when they become supported */
744MODULE_PARM_DESC(ahci_em_messages,
745 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
746
747#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE) 374#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
748static int marvell_enable; 375static int marvell_enable;
749#else 376#else
@@ -753,214 +380,6 @@ module_param(marvell_enable, int, 0644);
753MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); 380MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
754 381
755 382
756static inline int ahci_nr_ports(u32 cap)
757{
758 return (cap & 0x1f) + 1;
759}
760
761static inline void __iomem *__ahci_port_base(struct ata_host *host,
762 unsigned int port_no)
763{
764 struct ahci_host_priv *hpriv = host->private_data;
765 void __iomem *mmio = hpriv->mmio;
766
767 return mmio + 0x100 + (port_no * 0x80);
768}
769
770static inline void __iomem *ahci_port_base(struct ata_port *ap)
771{
772 return __ahci_port_base(ap->host, ap->port_no);
773}
774
775static void ahci_enable_ahci(void __iomem *mmio)
776{
777 int i;
778 u32 tmp;
779
780 /* turn on AHCI_EN */
781 tmp = readl(mmio + HOST_CTL);
782 if (tmp & HOST_AHCI_EN)
783 return;
784
785 /* Some controllers need AHCI_EN to be written multiple times.
786 * Try a few times before giving up.
787 */
788 for (i = 0; i < 5; i++) {
789 tmp |= HOST_AHCI_EN;
790 writel(tmp, mmio + HOST_CTL);
791 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
792 if (tmp & HOST_AHCI_EN)
793 return;
794 msleep(10);
795 }
796
797 WARN_ON(1);
798}
799
800static ssize_t ahci_show_host_caps(struct device *dev,
801 struct device_attribute *attr, char *buf)
802{
803 struct Scsi_Host *shost = class_to_shost(dev);
804 struct ata_port *ap = ata_shost_to_port(shost);
805 struct ahci_host_priv *hpriv = ap->host->private_data;
806
807 return sprintf(buf, "%x\n", hpriv->cap);
808}
809
810static ssize_t ahci_show_host_cap2(struct device *dev,
811 struct device_attribute *attr, char *buf)
812{
813 struct Scsi_Host *shost = class_to_shost(dev);
814 struct ata_port *ap = ata_shost_to_port(shost);
815 struct ahci_host_priv *hpriv = ap->host->private_data;
816
817 return sprintf(buf, "%x\n", hpriv->cap2);
818}
819
820static ssize_t ahci_show_host_version(struct device *dev,
821 struct device_attribute *attr, char *buf)
822{
823 struct Scsi_Host *shost = class_to_shost(dev);
824 struct ata_port *ap = ata_shost_to_port(shost);
825 struct ahci_host_priv *hpriv = ap->host->private_data;
826 void __iomem *mmio = hpriv->mmio;
827
828 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
829}
830
831static ssize_t ahci_show_port_cmd(struct device *dev,
832 struct device_attribute *attr, char *buf)
833{
834 struct Scsi_Host *shost = class_to_shost(dev);
835 struct ata_port *ap = ata_shost_to_port(shost);
836 void __iomem *port_mmio = ahci_port_base(ap);
837
838 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
839}
840
841/**
842 * ahci_save_initial_config - Save and fixup initial config values
843 * @dev: target AHCI device
844 * @hpriv: host private area to store config values
845 * @force_port_map: force port map to a specified value
846 * @mask_port_map: mask out particular bits from port map
847 *
848 * Some registers containing configuration info might be setup by
849 * BIOS and might be cleared on reset. This function saves the
850 * initial values of those registers into @hpriv such that they
851 * can be restored after controller reset.
852 *
853 * If inconsistent, config values are fixed up by this function.
854 *
855 * LOCKING:
856 * None.
857 */
858static void ahci_save_initial_config(struct device *dev,
859 struct ahci_host_priv *hpriv,
860 unsigned int force_port_map,
861 unsigned int mask_port_map)
862{
863 void __iomem *mmio = hpriv->mmio;
864 u32 cap, cap2, vers, port_map;
865 int i;
866
867 /* make sure AHCI mode is enabled before accessing CAP */
868 ahci_enable_ahci(mmio);
869
870 /* Values prefixed with saved_ are written back to host after
871 * reset. Values without are used for driver operation.
872 */
873 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
874 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
875
876 /* CAP2 register is only defined for AHCI 1.2 and later */
877 vers = readl(mmio + HOST_VERSION);
878 if ((vers >> 16) > 1 ||
879 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
880 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
881 else
882 hpriv->saved_cap2 = cap2 = 0;
883
884 /* some chips have errata preventing 64bit use */
885 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
886 dev_printk(KERN_INFO, dev,
887 "controller can't do 64bit DMA, forcing 32bit\n");
888 cap &= ~HOST_CAP_64;
889 }
890
891 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
892 dev_printk(KERN_INFO, dev,
893 "controller can't do NCQ, turning off CAP_NCQ\n");
894 cap &= ~HOST_CAP_NCQ;
895 }
896
897 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
898 dev_printk(KERN_INFO, dev,
899 "controller can do NCQ, turning on CAP_NCQ\n");
900 cap |= HOST_CAP_NCQ;
901 }
902
903 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
904 dev_printk(KERN_INFO, dev,
905 "controller can't do PMP, turning off CAP_PMP\n");
906 cap &= ~HOST_CAP_PMP;
907 }
908
909 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
910 dev_printk(KERN_INFO, dev,
911 "controller can't do SNTF, turning off CAP_SNTF\n");
912 cap &= ~HOST_CAP_SNTF;
913 }
914
915 if (force_port_map && port_map != force_port_map) {
916 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
917 port_map, force_port_map);
918 port_map = force_port_map;
919 }
920
921 if (mask_port_map) {
922 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
923 port_map,
924 port_map & mask_port_map);
925 port_map &= mask_port_map;
926 }
927
928 /* cross check port_map and cap.n_ports */
929 if (port_map) {
930 int map_ports = 0;
931
932 for (i = 0; i < AHCI_MAX_PORTS; i++)
933 if (port_map & (1 << i))
934 map_ports++;
935
936 /* If PI has more ports than n_ports, whine, clear
937 * port_map and let it be generated from n_ports.
938 */
939 if (map_ports > ahci_nr_ports(cap)) {
940 dev_printk(KERN_WARNING, dev,
941 "implemented port map (0x%x) contains more "
942 "ports than nr_ports (%u), using nr_ports\n",
943 port_map, ahci_nr_ports(cap));
944 port_map = 0;
945 }
946 }
947
948 /* fabricate port_map from cap.nr_ports */
949 if (!port_map) {
950 port_map = (1 << ahci_nr_ports(cap)) - 1;
951 dev_printk(KERN_WARNING, dev,
952 "forcing PORTS_IMPL to 0x%x\n", port_map);
953
954 /* write the fixed up value to the PI register */
955 hpriv->saved_port_map = port_map;
956 }
957
958 /* record values to use during operation */
959 hpriv->cap = cap;
960 hpriv->cap2 = cap2;
961 hpriv->port_map = port_map;
962}
963
964static void ahci_pci_save_initial_config(struct pci_dev *pdev, 383static void ahci_pci_save_initial_config(struct pci_dev *pdev,
965 struct ahci_host_priv *hpriv) 384 struct ahci_host_priv *hpriv)
966{ 385{
@@ -990,421 +409,6 @@ static void ahci_pci_save_initial_config(struct pci_dev *pdev,
990 mask_port_map); 409 mask_port_map);
991} 410}
992 411
993/**
994 * ahci_restore_initial_config - Restore initial config
995 * @host: target ATA host
996 *
997 * Restore initial config stored by ahci_save_initial_config().
998 *
999 * LOCKING:
1000 * None.
1001 */
1002static void ahci_restore_initial_config(struct ata_host *host)
1003{
1004 struct ahci_host_priv *hpriv = host->private_data;
1005 void __iomem *mmio = hpriv->mmio;
1006
1007 writel(hpriv->saved_cap, mmio + HOST_CAP);
1008 if (hpriv->saved_cap2)
1009 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
1010 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
1011 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1012}
1013
1014static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1015{
1016 static const int offset[] = {
1017 [SCR_STATUS] = PORT_SCR_STAT,
1018 [SCR_CONTROL] = PORT_SCR_CTL,
1019 [SCR_ERROR] = PORT_SCR_ERR,
1020 [SCR_ACTIVE] = PORT_SCR_ACT,
1021 [SCR_NOTIFICATION] = PORT_SCR_NTF,
1022 };
1023 struct ahci_host_priv *hpriv = ap->host->private_data;
1024
1025 if (sc_reg < ARRAY_SIZE(offset) &&
1026 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
1027 return offset[sc_reg];
1028 return 0;
1029}
1030
1031static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
1032{
1033 void __iomem *port_mmio = ahci_port_base(link->ap);
1034 int offset = ahci_scr_offset(link->ap, sc_reg);
1035
1036 if (offset) {
1037 *val = readl(port_mmio + offset);
1038 return 0;
1039 }
1040 return -EINVAL;
1041}
1042
1043static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
1044{
1045 void __iomem *port_mmio = ahci_port_base(link->ap);
1046 int offset = ahci_scr_offset(link->ap, sc_reg);
1047
1048 if (offset) {
1049 writel(val, port_mmio + offset);
1050 return 0;
1051 }
1052 return -EINVAL;
1053}
1054
1055static void ahci_start_engine(struct ata_port *ap)
1056{
1057 void __iomem *port_mmio = ahci_port_base(ap);
1058 u32 tmp;
1059
1060 /* start DMA */
1061 tmp = readl(port_mmio + PORT_CMD);
1062 tmp |= PORT_CMD_START;
1063 writel(tmp, port_mmio + PORT_CMD);
1064 readl(port_mmio + PORT_CMD); /* flush */
1065}
1066
1067static int ahci_stop_engine(struct ata_port *ap)
1068{
1069 void __iomem *port_mmio = ahci_port_base(ap);
1070 u32 tmp;
1071
1072 tmp = readl(port_mmio + PORT_CMD);
1073
1074 /* check if the HBA is idle */
1075 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
1076 return 0;
1077
1078 /* setting HBA to idle */
1079 tmp &= ~PORT_CMD_START;
1080 writel(tmp, port_mmio + PORT_CMD);
1081
1082 /* wait for engine to stop. This could be as long as 500 msec */
1083 tmp = ata_wait_register(port_mmio + PORT_CMD,
1084 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
1085 if (tmp & PORT_CMD_LIST_ON)
1086 return -EIO;
1087
1088 return 0;
1089}
1090
1091static void ahci_start_fis_rx(struct ata_port *ap)
1092{
1093 void __iomem *port_mmio = ahci_port_base(ap);
1094 struct ahci_host_priv *hpriv = ap->host->private_data;
1095 struct ahci_port_priv *pp = ap->private_data;
1096 u32 tmp;
1097
1098 /* set FIS registers */
1099 if (hpriv->cap & HOST_CAP_64)
1100 writel((pp->cmd_slot_dma >> 16) >> 16,
1101 port_mmio + PORT_LST_ADDR_HI);
1102 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
1103
1104 if (hpriv->cap & HOST_CAP_64)
1105 writel((pp->rx_fis_dma >> 16) >> 16,
1106 port_mmio + PORT_FIS_ADDR_HI);
1107 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
1108
1109 /* enable FIS reception */
1110 tmp = readl(port_mmio + PORT_CMD);
1111 tmp |= PORT_CMD_FIS_RX;
1112 writel(tmp, port_mmio + PORT_CMD);
1113
1114 /* flush */
1115 readl(port_mmio + PORT_CMD);
1116}
1117
1118static int ahci_stop_fis_rx(struct ata_port *ap)
1119{
1120 void __iomem *port_mmio = ahci_port_base(ap);
1121 u32 tmp;
1122
1123 /* disable FIS reception */
1124 tmp = readl(port_mmio + PORT_CMD);
1125 tmp &= ~PORT_CMD_FIS_RX;
1126 writel(tmp, port_mmio + PORT_CMD);
1127
1128 /* wait for completion, spec says 500ms, give it 1000 */
1129 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
1130 PORT_CMD_FIS_ON, 10, 1000);
1131 if (tmp & PORT_CMD_FIS_ON)
1132 return -EBUSY;
1133
1134 return 0;
1135}
1136
1137static void ahci_power_up(struct ata_port *ap)
1138{
1139 struct ahci_host_priv *hpriv = ap->host->private_data;
1140 void __iomem *port_mmio = ahci_port_base(ap);
1141 u32 cmd;
1142
1143 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1144
1145 /* spin up device */
1146 if (hpriv->cap & HOST_CAP_SSS) {
1147 cmd |= PORT_CMD_SPIN_UP;
1148 writel(cmd, port_mmio + PORT_CMD);
1149 }
1150
1151 /* wake up link */
1152 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
1153}
1154
1155static void ahci_disable_alpm(struct ata_port *ap)
1156{
1157 struct ahci_host_priv *hpriv = ap->host->private_data;
1158 void __iomem *port_mmio = ahci_port_base(ap);
1159 u32 cmd;
1160 struct ahci_port_priv *pp = ap->private_data;
1161
1162 /* IPM bits should be disabled by libata-core */
1163 /* get the existing command bits */
1164 cmd = readl(port_mmio + PORT_CMD);
1165
1166 /* disable ALPM and ASP */
1167 cmd &= ~PORT_CMD_ASP;
1168 cmd &= ~PORT_CMD_ALPE;
1169
1170 /* force the interface back to active */
1171 cmd |= PORT_CMD_ICC_ACTIVE;
1172
1173 /* write out new cmd value */
1174 writel(cmd, port_mmio + PORT_CMD);
1175 cmd = readl(port_mmio + PORT_CMD);
1176
1177 /* wait 10ms to be sure we've come out of any low power state */
1178 msleep(10);
1179
1180 /* clear out any PhyRdy stuff from interrupt status */
1181 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
1182
1183 /* go ahead and clean out PhyRdy Change from Serror too */
1184 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1185
1186 /*
1187 * Clear flag to indicate that we should ignore all PhyRdy
1188 * state changes
1189 */
1190 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1191
1192 /*
1193 * Enable interrupts on Phy Ready.
1194 */
1195 pp->intr_mask |= PORT_IRQ_PHYRDY;
1196 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1197
1198 /*
1199 * don't change the link pm policy - we can be called
1200 * just to turn of link pm temporarily
1201 */
1202}
1203
1204static int ahci_enable_alpm(struct ata_port *ap,
1205 enum link_pm policy)
1206{
1207 struct ahci_host_priv *hpriv = ap->host->private_data;
1208 void __iomem *port_mmio = ahci_port_base(ap);
1209 u32 cmd;
1210 struct ahci_port_priv *pp = ap->private_data;
1211 u32 asp;
1212
1213 /* Make sure the host is capable of link power management */
1214 if (!(hpriv->cap & HOST_CAP_ALPM))
1215 return -EINVAL;
1216
1217 switch (policy) {
1218 case MAX_PERFORMANCE:
1219 case NOT_AVAILABLE:
1220 /*
1221 * if we came here with NOT_AVAILABLE,
1222 * it just means this is the first time we
1223 * have tried to enable - default to max performance,
1224 * and let the user go to lower power modes on request.
1225 */
1226 ahci_disable_alpm(ap);
1227 return 0;
1228 case MIN_POWER:
1229 /* configure HBA to enter SLUMBER */
1230 asp = PORT_CMD_ASP;
1231 break;
1232 case MEDIUM_POWER:
1233 /* configure HBA to enter PARTIAL */
1234 asp = 0;
1235 break;
1236 default:
1237 return -EINVAL;
1238 }
1239
1240 /*
1241 * Disable interrupts on Phy Ready. This keeps us from
1242 * getting woken up due to spurious phy ready interrupts
1243 * TBD - Hot plug should be done via polling now, is
1244 * that even supported?
1245 */
1246 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1247 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1248
1249 /*
1250 * Set a flag to indicate that we should ignore all PhyRdy
1251 * state changes since these can happen now whenever we
1252 * change link state
1253 */
1254 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1255
1256 /* get the existing command bits */
1257 cmd = readl(port_mmio + PORT_CMD);
1258
1259 /*
1260 * Set ASP based on Policy
1261 */
1262 cmd |= asp;
1263
1264 /*
1265 * Setting this bit will instruct the HBA to aggressively
1266 * enter a lower power link state when it's appropriate and
1267 * based on the value set above for ASP
1268 */
1269 cmd |= PORT_CMD_ALPE;
1270
1271 /* write out new cmd value */
1272 writel(cmd, port_mmio + PORT_CMD);
1273 cmd = readl(port_mmio + PORT_CMD);
1274
1275 /* IPM bits should be set by libata-core */
1276 return 0;
1277}
1278
1279#ifdef CONFIG_PM
1280static void ahci_power_down(struct ata_port *ap)
1281{
1282 struct ahci_host_priv *hpriv = ap->host->private_data;
1283 void __iomem *port_mmio = ahci_port_base(ap);
1284 u32 cmd, scontrol;
1285
1286 if (!(hpriv->cap & HOST_CAP_SSS))
1287 return;
1288
1289 /* put device into listen mode, first set PxSCTL.DET to 0 */
1290 scontrol = readl(port_mmio + PORT_SCR_CTL);
1291 scontrol &= ~0xf;
1292 writel(scontrol, port_mmio + PORT_SCR_CTL);
1293
1294 /* then set PxCMD.SUD to 0 */
1295 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1296 cmd &= ~PORT_CMD_SPIN_UP;
1297 writel(cmd, port_mmio + PORT_CMD);
1298}
1299#endif
1300
1301static void ahci_start_port(struct ata_port *ap)
1302{
1303 struct ahci_port_priv *pp = ap->private_data;
1304 struct ata_link *link;
1305 struct ahci_em_priv *emp;
1306 ssize_t rc;
1307 int i;
1308
1309 /* enable FIS reception */
1310 ahci_start_fis_rx(ap);
1311
1312 /* enable DMA */
1313 ahci_start_engine(ap);
1314
1315 /* turn on LEDs */
1316 if (ap->flags & ATA_FLAG_EM) {
1317 ata_for_each_link(link, ap, EDGE) {
1318 emp = &pp->em_priv[link->pmp];
1319
1320 /* EM Transmit bit maybe busy during init */
1321 for (i = 0; i < EM_MAX_RETRY; i++) {
1322 rc = ahci_transmit_led_message(ap,
1323 emp->led_state,
1324 4);
1325 if (rc == -EBUSY)
1326 msleep(1);
1327 else
1328 break;
1329 }
1330 }
1331 }
1332
1333 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1334 ata_for_each_link(link, ap, EDGE)
1335 ahci_init_sw_activity(link);
1336
1337}
1338
1339static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1340{
1341 int rc;
1342
1343 /* disable DMA */
1344 rc = ahci_stop_engine(ap);
1345 if (rc) {
1346 *emsg = "failed to stop engine";
1347 return rc;
1348 }
1349
1350 /* disable FIS reception */
1351 rc = ahci_stop_fis_rx(ap);
1352 if (rc) {
1353 *emsg = "failed stop FIS RX";
1354 return rc;
1355 }
1356
1357 return 0;
1358}
1359
1360static int ahci_reset_controller(struct ata_host *host)
1361{
1362 struct ahci_host_priv *hpriv = host->private_data;
1363 void __iomem *mmio = hpriv->mmio;
1364 u32 tmp;
1365
1366 /* we must be in AHCI mode, before using anything
1367 * AHCI-specific, such as HOST_RESET.
1368 */
1369 ahci_enable_ahci(mmio);
1370
1371 /* global controller reset */
1372 if (!ahci_skip_host_reset) {
1373 tmp = readl(mmio + HOST_CTL);
1374 if ((tmp & HOST_RESET) == 0) {
1375 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1376 readl(mmio + HOST_CTL); /* flush */
1377 }
1378
1379 /*
1380 * to perform host reset, OS should set HOST_RESET
1381 * and poll until this bit is read to be "0".
1382 * reset must complete within 1 second, or
1383 * the hardware should be considered fried.
1384 */
1385 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1386 HOST_RESET, 10, 1000);
1387
1388 if (tmp & HOST_RESET) {
1389 dev_printk(KERN_ERR, host->dev,
1390 "controller reset failed (0x%x)\n", tmp);
1391 return -EIO;
1392 }
1393
1394 /* turn on AHCI mode */
1395 ahci_enable_ahci(mmio);
1396
1397 /* Some registers might be cleared on reset. Restore
1398 * initial values.
1399 */
1400 ahci_restore_initial_config(host);
1401 } else
1402 dev_printk(KERN_INFO, host->dev,
1403 "skipping global host reset\n");
1404
1405 return 0;
1406}
1407
1408static int ahci_pci_reset_controller(struct ata_host *host) 412static int ahci_pci_reset_controller(struct ata_host *host)
1409{ 413{
1410 struct pci_dev *pdev = to_pci_dev(host->dev); 414 struct pci_dev *pdev = to_pci_dev(host->dev);
@@ -1426,286 +430,6 @@ static int ahci_pci_reset_controller(struct ata_host *host)
1426 return 0; 430 return 0;
1427} 431}
1428 432
1429static void ahci_sw_activity(struct ata_link *link)
1430{
1431 struct ata_port *ap = link->ap;
1432 struct ahci_port_priv *pp = ap->private_data;
1433 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1434
1435 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1436 return;
1437
1438 emp->activity++;
1439 if (!timer_pending(&emp->timer))
1440 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1441}
1442
1443static void ahci_sw_activity_blink(unsigned long arg)
1444{
1445 struct ata_link *link = (struct ata_link *)arg;
1446 struct ata_port *ap = link->ap;
1447 struct ahci_port_priv *pp = ap->private_data;
1448 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1449 unsigned long led_message = emp->led_state;
1450 u32 activity_led_state;
1451 unsigned long flags;
1452
1453 led_message &= EM_MSG_LED_VALUE;
1454 led_message |= ap->port_no | (link->pmp << 8);
1455
1456 /* check to see if we've had activity. If so,
1457 * toggle state of LED and reset timer. If not,
1458 * turn LED to desired idle state.
1459 */
1460 spin_lock_irqsave(ap->lock, flags);
1461 if (emp->saved_activity != emp->activity) {
1462 emp->saved_activity = emp->activity;
1463 /* get the current LED state */
1464 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1465
1466 if (activity_led_state)
1467 activity_led_state = 0;
1468 else
1469 activity_led_state = 1;
1470
1471 /* clear old state */
1472 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1473
1474 /* toggle state */
1475 led_message |= (activity_led_state << 16);
1476 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1477 } else {
1478 /* switch to idle */
1479 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1480 if (emp->blink_policy == BLINK_OFF)
1481 led_message |= (1 << 16);
1482 }
1483 spin_unlock_irqrestore(ap->lock, flags);
1484 ahci_transmit_led_message(ap, led_message, 4);
1485}
1486
1487static void ahci_init_sw_activity(struct ata_link *link)
1488{
1489 struct ata_port *ap = link->ap;
1490 struct ahci_port_priv *pp = ap->private_data;
1491 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1492
1493 /* init activity stats, setup timer */
1494 emp->saved_activity = emp->activity = 0;
1495 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1496
1497 /* check our blink policy and set flag for link if it's enabled */
1498 if (emp->blink_policy)
1499 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1500}
1501
1502static int ahci_reset_em(struct ata_host *host)
1503{
1504 struct ahci_host_priv *hpriv = host->private_data;
1505 void __iomem *mmio = hpriv->mmio;
1506 u32 em_ctl;
1507
1508 em_ctl = readl(mmio + HOST_EM_CTL);
1509 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1510 return -EINVAL;
1511
1512 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1513 return 0;
1514}
1515
1516static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1517 ssize_t size)
1518{
1519 struct ahci_host_priv *hpriv = ap->host->private_data;
1520 struct ahci_port_priv *pp = ap->private_data;
1521 void __iomem *mmio = hpriv->mmio;
1522 u32 em_ctl;
1523 u32 message[] = {0, 0};
1524 unsigned long flags;
1525 int pmp;
1526 struct ahci_em_priv *emp;
1527
1528 /* get the slot number from the message */
1529 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1530 if (pmp < EM_MAX_SLOTS)
1531 emp = &pp->em_priv[pmp];
1532 else
1533 return -EINVAL;
1534
1535 spin_lock_irqsave(ap->lock, flags);
1536
1537 /*
1538 * if we are still busy transmitting a previous message,
1539 * do not allow
1540 */
1541 em_ctl = readl(mmio + HOST_EM_CTL);
1542 if (em_ctl & EM_CTL_TM) {
1543 spin_unlock_irqrestore(ap->lock, flags);
1544 return -EBUSY;
1545 }
1546
1547 /*
1548 * create message header - this is all zero except for
1549 * the message size, which is 4 bytes.
1550 */
1551 message[0] |= (4 << 8);
1552
1553 /* ignore 0:4 of byte zero, fill in port info yourself */
1554 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1555
1556 /* write message to EM_LOC */
1557 writel(message[0], mmio + hpriv->em_loc);
1558 writel(message[1], mmio + hpriv->em_loc+4);
1559
1560 /* save off new led state for port/slot */
1561 emp->led_state = state;
1562
1563 /*
1564 * tell hardware to transmit the message
1565 */
1566 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1567
1568 spin_unlock_irqrestore(ap->lock, flags);
1569 return size;
1570}
1571
1572static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1573{
1574 struct ahci_port_priv *pp = ap->private_data;
1575 struct ata_link *link;
1576 struct ahci_em_priv *emp;
1577 int rc = 0;
1578
1579 ata_for_each_link(link, ap, EDGE) {
1580 emp = &pp->em_priv[link->pmp];
1581 rc += sprintf(buf, "%lx\n", emp->led_state);
1582 }
1583 return rc;
1584}
1585
1586static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1587 size_t size)
1588{
1589 int state;
1590 int pmp;
1591 struct ahci_port_priv *pp = ap->private_data;
1592 struct ahci_em_priv *emp;
1593
1594 state = simple_strtoul(buf, NULL, 0);
1595
1596 /* get the slot number from the message */
1597 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1598 if (pmp < EM_MAX_SLOTS)
1599 emp = &pp->em_priv[pmp];
1600 else
1601 return -EINVAL;
1602
1603 /* mask off the activity bits if we are in sw_activity
1604 * mode, user should turn off sw_activity before setting
1605 * activity led through em_message
1606 */
1607 if (emp->blink_policy)
1608 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1609
1610 return ahci_transmit_led_message(ap, state, size);
1611}
1612
1613static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1614{
1615 struct ata_link *link = dev->link;
1616 struct ata_port *ap = link->ap;
1617 struct ahci_port_priv *pp = ap->private_data;
1618 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1619 u32 port_led_state = emp->led_state;
1620
1621 /* save the desired Activity LED behavior */
1622 if (val == OFF) {
1623 /* clear LFLAG */
1624 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1625
1626 /* set the LED to OFF */
1627 port_led_state &= EM_MSG_LED_VALUE_OFF;
1628 port_led_state |= (ap->port_no | (link->pmp << 8));
1629 ahci_transmit_led_message(ap, port_led_state, 4);
1630 } else {
1631 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1632 if (val == BLINK_OFF) {
1633 /* set LED to ON for idle */
1634 port_led_state &= EM_MSG_LED_VALUE_OFF;
1635 port_led_state |= (ap->port_no | (link->pmp << 8));
1636 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1637 ahci_transmit_led_message(ap, port_led_state, 4);
1638 }
1639 }
1640 emp->blink_policy = val;
1641 return 0;
1642}
1643
1644static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1645{
1646 struct ata_link *link = dev->link;
1647 struct ata_port *ap = link->ap;
1648 struct ahci_port_priv *pp = ap->private_data;
1649 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1650
1651 /* display the saved value of activity behavior for this
1652 * disk.
1653 */
1654 return sprintf(buf, "%d\n", emp->blink_policy);
1655}
1656
1657static void ahci_port_init(struct device *dev, struct ata_port *ap,
1658 int port_no, void __iomem *mmio,
1659 void __iomem *port_mmio)
1660{
1661 const char *emsg = NULL;
1662 int rc;
1663 u32 tmp;
1664
1665 /* make sure port is not active */
1666 rc = ahci_deinit_port(ap, &emsg);
1667 if (rc)
1668 dev_warn(dev, "%s (%d)\n", emsg, rc);
1669
1670 /* clear SError */
1671 tmp = readl(port_mmio + PORT_SCR_ERR);
1672 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1673 writel(tmp, port_mmio + PORT_SCR_ERR);
1674
1675 /* clear port IRQ */
1676 tmp = readl(port_mmio + PORT_IRQ_STAT);
1677 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1678 if (tmp)
1679 writel(tmp, port_mmio + PORT_IRQ_STAT);
1680
1681 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1682}
1683
1684static void ahci_init_controller(struct ata_host *host)
1685{
1686 struct ahci_host_priv *hpriv = host->private_data;
1687 void __iomem *mmio = hpriv->mmio;
1688 int i;
1689 void __iomem *port_mmio;
1690 u32 tmp;
1691
1692 for (i = 0; i < host->n_ports; i++) {
1693 struct ata_port *ap = host->ports[i];
1694
1695 port_mmio = ahci_port_base(ap);
1696 if (ata_port_is_dummy(ap))
1697 continue;
1698
1699 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1700 }
1701
1702 tmp = readl(mmio + HOST_CTL);
1703 VPRINTK("HOST_CTL 0x%x\n", tmp);
1704 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1705 tmp = readl(mmio + HOST_CTL);
1706 VPRINTK("HOST_CTL 0x%x\n", tmp);
1707}
1708
1709static void ahci_pci_init_controller(struct ata_host *host) 433static void ahci_pci_init_controller(struct ata_host *host)
1710{ 434{
1711 struct ahci_host_priv *hpriv = host->private_data; 435 struct ahci_host_priv *hpriv = host->private_data;
@@ -1733,205 +457,6 @@ static void ahci_pci_init_controller(struct ata_host *host)
1733 ahci_init_controller(host); 457 ahci_init_controller(host);
1734} 458}
1735 459
1736static void ahci_dev_config(struct ata_device *dev)
1737{
1738 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1739
1740 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1741 dev->max_sectors = 255;
1742 ata_dev_printk(dev, KERN_INFO,
1743 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1744 }
1745}
1746
1747static unsigned int ahci_dev_classify(struct ata_port *ap)
1748{
1749 void __iomem *port_mmio = ahci_port_base(ap);
1750 struct ata_taskfile tf;
1751 u32 tmp;
1752
1753 tmp = readl(port_mmio + PORT_SIG);
1754 tf.lbah = (tmp >> 24) & 0xff;
1755 tf.lbam = (tmp >> 16) & 0xff;
1756 tf.lbal = (tmp >> 8) & 0xff;
1757 tf.nsect = (tmp) & 0xff;
1758
1759 return ata_dev_classify(&tf);
1760}
1761
1762static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1763 u32 opts)
1764{
1765 dma_addr_t cmd_tbl_dma;
1766
1767 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1768
1769 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1770 pp->cmd_slot[tag].status = 0;
1771 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1772 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1773}
1774
1775static int ahci_kick_engine(struct ata_port *ap)
1776{
1777 void __iomem *port_mmio = ahci_port_base(ap);
1778 struct ahci_host_priv *hpriv = ap->host->private_data;
1779 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1780 u32 tmp;
1781 int busy, rc;
1782
1783 /* stop engine */
1784 rc = ahci_stop_engine(ap);
1785 if (rc)
1786 goto out_restart;
1787
1788 /* need to do CLO?
1789 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1790 */
1791 busy = status & (ATA_BUSY | ATA_DRQ);
1792 if (!busy && !sata_pmp_attached(ap)) {
1793 rc = 0;
1794 goto out_restart;
1795 }
1796
1797 if (!(hpriv->cap & HOST_CAP_CLO)) {
1798 rc = -EOPNOTSUPP;
1799 goto out_restart;
1800 }
1801
1802 /* perform CLO */
1803 tmp = readl(port_mmio + PORT_CMD);
1804 tmp |= PORT_CMD_CLO;
1805 writel(tmp, port_mmio + PORT_CMD);
1806
1807 rc = 0;
1808 tmp = ata_wait_register(port_mmio + PORT_CMD,
1809 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1810 if (tmp & PORT_CMD_CLO)
1811 rc = -EIO;
1812
1813 /* restart engine */
1814 out_restart:
1815 ahci_start_engine(ap);
1816 return rc;
1817}
1818
1819static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1820 struct ata_taskfile *tf, int is_cmd, u16 flags,
1821 unsigned long timeout_msec)
1822{
1823 const u32 cmd_fis_len = 5; /* five dwords */
1824 struct ahci_port_priv *pp = ap->private_data;
1825 void __iomem *port_mmio = ahci_port_base(ap);
1826 u8 *fis = pp->cmd_tbl;
1827 u32 tmp;
1828
1829 /* prep the command */
1830 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1831 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1832
1833 /* issue & wait */
1834 writel(1, port_mmio + PORT_CMD_ISSUE);
1835
1836 if (timeout_msec) {
1837 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1838 1, timeout_msec);
1839 if (tmp & 0x1) {
1840 ahci_kick_engine(ap);
1841 return -EBUSY;
1842 }
1843 } else
1844 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1845
1846 return 0;
1847}
1848
1849static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1850 int pmp, unsigned long deadline,
1851 int (*check_ready)(struct ata_link *link))
1852{
1853 struct ata_port *ap = link->ap;
1854 struct ahci_host_priv *hpriv = ap->host->private_data;
1855 const char *reason = NULL;
1856 unsigned long now, msecs;
1857 struct ata_taskfile tf;
1858 int rc;
1859
1860 DPRINTK("ENTER\n");
1861
1862 /* prepare for SRST (AHCI-1.1 10.4.1) */
1863 rc = ahci_kick_engine(ap);
1864 if (rc && rc != -EOPNOTSUPP)
1865 ata_link_printk(link, KERN_WARNING,
1866 "failed to reset engine (errno=%d)\n", rc);
1867
1868 ata_tf_init(link->device, &tf);
1869
1870 /* issue the first D2H Register FIS */
1871 msecs = 0;
1872 now = jiffies;
1873 if (time_after(now, deadline))
1874 msecs = jiffies_to_msecs(deadline - now);
1875
1876 tf.ctl |= ATA_SRST;
1877 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1878 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1879 rc = -EIO;
1880 reason = "1st FIS failed";
1881 goto fail;
1882 }
1883
1884 /* spec says at least 5us, but be generous and sleep for 1ms */
1885 msleep(1);
1886
1887 /* issue the second D2H Register FIS */
1888 tf.ctl &= ~ATA_SRST;
1889 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1890
1891 /* wait for link to become ready */
1892 rc = ata_wait_after_reset(link, deadline, check_ready);
1893 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1894 /*
1895 * Workaround for cases where link online status can't
1896 * be trusted. Treat device readiness timeout as link
1897 * offline.
1898 */
1899 ata_link_printk(link, KERN_INFO,
1900 "device not ready, treating as offline\n");
1901 *class = ATA_DEV_NONE;
1902 } else if (rc) {
1903 /* link occupied, -ENODEV too is an error */
1904 reason = "device not ready";
1905 goto fail;
1906 } else
1907 *class = ahci_dev_classify(ap);
1908
1909 DPRINTK("EXIT, class=%u\n", *class);
1910 return 0;
1911
1912 fail:
1913 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1914 return rc;
1915}
1916
1917static int ahci_check_ready(struct ata_link *link)
1918{
1919 void __iomem *port_mmio = ahci_port_base(link->ap);
1920 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1921
1922 return ata_check_ready(status);
1923}
1924
1925static int ahci_softreset(struct ata_link *link, unsigned int *class,
1926 unsigned long deadline)
1927{
1928 int pmp = sata_srst_pmp(link);
1929
1930 DPRINTK("ENTER\n");
1931
1932 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1933}
1934
1935static int ahci_sb600_check_ready(struct ata_link *link) 460static int ahci_sb600_check_ready(struct ata_link *link)
1936{ 461{
1937 void __iomem *port_mmio = ahci_port_base(link->ap); 462 void __iomem *port_mmio = ahci_port_base(link->ap);
@@ -1981,38 +506,6 @@ static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1981 return rc; 506 return rc;
1982} 507}
1983 508
1984static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1985 unsigned long deadline)
1986{
1987 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1988 struct ata_port *ap = link->ap;
1989 struct ahci_port_priv *pp = ap->private_data;
1990 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1991 struct ata_taskfile tf;
1992 bool online;
1993 int rc;
1994
1995 DPRINTK("ENTER\n");
1996
1997 ahci_stop_engine(ap);
1998
1999 /* clear D2H reception area to properly wait for D2H FIS */
2000 ata_tf_init(link->device, &tf);
2001 tf.command = 0x80;
2002 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
2003
2004 rc = sata_link_hardreset(link, timing, deadline, &online,
2005 ahci_check_ready);
2006
2007 ahci_start_engine(ap);
2008
2009 if (online)
2010 *class = ahci_dev_classify(ap);
2011
2012 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
2013 return rc;
2014}
2015
2016static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 509static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
2017 unsigned long deadline) 510 unsigned long deadline)
2018{ 511{
@@ -2081,601 +574,7 @@ static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
2081 return rc; 574 return rc;
2082} 575}
2083 576
2084static void ahci_postreset(struct ata_link *link, unsigned int *class)
2085{
2086 struct ata_port *ap = link->ap;
2087 void __iomem *port_mmio = ahci_port_base(ap);
2088 u32 new_tmp, tmp;
2089
2090 ata_std_postreset(link, class);
2091
2092 /* Make sure port's ATAPI bit is set appropriately */
2093 new_tmp = tmp = readl(port_mmio + PORT_CMD);
2094 if (*class == ATA_DEV_ATAPI)
2095 new_tmp |= PORT_CMD_ATAPI;
2096 else
2097 new_tmp &= ~PORT_CMD_ATAPI;
2098 if (new_tmp != tmp) {
2099 writel(new_tmp, port_mmio + PORT_CMD);
2100 readl(port_mmio + PORT_CMD); /* flush */
2101 }
2102}
2103
2104static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
2105{
2106 struct scatterlist *sg;
2107 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
2108 unsigned int si;
2109
2110 VPRINTK("ENTER\n");
2111
2112 /*
2113 * Next, the S/G list.
2114 */
2115 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2116 dma_addr_t addr = sg_dma_address(sg);
2117 u32 sg_len = sg_dma_len(sg);
2118
2119 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
2120 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
2121 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
2122 }
2123
2124 return si;
2125}
2126
2127static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
2128{
2129 struct ata_port *ap = qc->ap;
2130 struct ahci_port_priv *pp = ap->private_data;
2131
2132 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
2133 return ata_std_qc_defer(qc);
2134 else
2135 return sata_pmp_qc_defer_cmd_switch(qc);
2136}
2137
2138static void ahci_qc_prep(struct ata_queued_cmd *qc)
2139{
2140 struct ata_port *ap = qc->ap;
2141 struct ahci_port_priv *pp = ap->private_data;
2142 int is_atapi = ata_is_atapi(qc->tf.protocol);
2143 void *cmd_tbl;
2144 u32 opts;
2145 const u32 cmd_fis_len = 5; /* five dwords */
2146 unsigned int n_elem;
2147
2148 /*
2149 * Fill in command table information. First, the header,
2150 * a SATA Register - Host to Device command FIS.
2151 */
2152 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
2153
2154 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
2155 if (is_atapi) {
2156 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
2157 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
2158 }
2159
2160 n_elem = 0;
2161 if (qc->flags & ATA_QCFLAG_DMAMAP)
2162 n_elem = ahci_fill_sg(qc, cmd_tbl);
2163
2164 /*
2165 * Fill in command slot information.
2166 */
2167 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
2168 if (qc->tf.flags & ATA_TFLAG_WRITE)
2169 opts |= AHCI_CMD_WRITE;
2170 if (is_atapi)
2171 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
2172
2173 ahci_fill_cmd_slot(pp, qc->tag, opts);
2174}
2175
2176static void ahci_fbs_dec_intr(struct ata_port *ap)
2177{
2178 struct ahci_port_priv *pp = ap->private_data;
2179 void __iomem *port_mmio = ahci_port_base(ap);
2180 u32 fbs = readl(port_mmio + PORT_FBS);
2181 int retries = 3;
2182
2183 DPRINTK("ENTER\n");
2184 BUG_ON(!pp->fbs_enabled);
2185
2186 /* time to wait for DEC is not specified by AHCI spec,
2187 * add a retry loop for safety.
2188 */
2189 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
2190 fbs = readl(port_mmio + PORT_FBS);
2191 while ((fbs & PORT_FBS_DEC) && retries--) {
2192 udelay(1);
2193 fbs = readl(port_mmio + PORT_FBS);
2194 }
2195
2196 if (fbs & PORT_FBS_DEC)
2197 dev_printk(KERN_ERR, ap->host->dev,
2198 "failed to clear device error\n");
2199}
2200
2201static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
2202{
2203 struct ahci_host_priv *hpriv = ap->host->private_data;
2204 struct ahci_port_priv *pp = ap->private_data;
2205 struct ata_eh_info *host_ehi = &ap->link.eh_info;
2206 struct ata_link *link = NULL;
2207 struct ata_queued_cmd *active_qc;
2208 struct ata_eh_info *active_ehi;
2209 bool fbs_need_dec = false;
2210 u32 serror;
2211
2212 /* determine active link with error */
2213 if (pp->fbs_enabled) {
2214 void __iomem *port_mmio = ahci_port_base(ap);
2215 u32 fbs = readl(port_mmio + PORT_FBS);
2216 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
2217
2218 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
2219 ata_link_online(&ap->pmp_link[pmp])) {
2220 link = &ap->pmp_link[pmp];
2221 fbs_need_dec = true;
2222 }
2223
2224 } else
2225 ata_for_each_link(link, ap, EDGE)
2226 if (ata_link_active(link))
2227 break;
2228
2229 if (!link)
2230 link = &ap->link;
2231
2232 active_qc = ata_qc_from_tag(ap, link->active_tag);
2233 active_ehi = &link->eh_info;
2234
2235 /* record irq stat */
2236 ata_ehi_clear_desc(host_ehi);
2237 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
2238
2239 /* AHCI needs SError cleared; otherwise, it might lock up */
2240 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
2241 ahci_scr_write(&ap->link, SCR_ERROR, serror);
2242 host_ehi->serror |= serror;
2243
2244 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
2245 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
2246 irq_stat &= ~PORT_IRQ_IF_ERR;
2247
2248 if (irq_stat & PORT_IRQ_TF_ERR) {
2249 /* If qc is active, charge it; otherwise, the active
2250 * link. There's no active qc on NCQ errors. It will
2251 * be determined by EH by reading log page 10h.
2252 */
2253 if (active_qc)
2254 active_qc->err_mask |= AC_ERR_DEV;
2255 else
2256 active_ehi->err_mask |= AC_ERR_DEV;
2257
2258 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
2259 host_ehi->serror &= ~SERR_INTERNAL;
2260 }
2261
2262 if (irq_stat & PORT_IRQ_UNK_FIS) {
2263 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
2264
2265 active_ehi->err_mask |= AC_ERR_HSM;
2266 active_ehi->action |= ATA_EH_RESET;
2267 ata_ehi_push_desc(active_ehi,
2268 "unknown FIS %08x %08x %08x %08x" ,
2269 unk[0], unk[1], unk[2], unk[3]);
2270 }
2271
2272 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
2273 active_ehi->err_mask |= AC_ERR_HSM;
2274 active_ehi->action |= ATA_EH_RESET;
2275 ata_ehi_push_desc(active_ehi, "incorrect PMP");
2276 }
2277
2278 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
2279 host_ehi->err_mask |= AC_ERR_HOST_BUS;
2280 host_ehi->action |= ATA_EH_RESET;
2281 ata_ehi_push_desc(host_ehi, "host bus error");
2282 }
2283
2284 if (irq_stat & PORT_IRQ_IF_ERR) {
2285 if (fbs_need_dec)
2286 active_ehi->err_mask |= AC_ERR_DEV;
2287 else {
2288 host_ehi->err_mask |= AC_ERR_ATA_BUS;
2289 host_ehi->action |= ATA_EH_RESET;
2290 }
2291
2292 ata_ehi_push_desc(host_ehi, "interface fatal error");
2293 }
2294
2295 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
2296 ata_ehi_hotplugged(host_ehi);
2297 ata_ehi_push_desc(host_ehi, "%s",
2298 irq_stat & PORT_IRQ_CONNECT ?
2299 "connection status changed" : "PHY RDY changed");
2300 }
2301
2302 /* okay, let's hand over to EH */
2303
2304 if (irq_stat & PORT_IRQ_FREEZE)
2305 ata_port_freeze(ap);
2306 else if (fbs_need_dec) {
2307 ata_link_abort(link);
2308 ahci_fbs_dec_intr(ap);
2309 } else
2310 ata_port_abort(ap);
2311}
2312
2313static void ahci_port_intr(struct ata_port *ap)
2314{
2315 void __iomem *port_mmio = ahci_port_base(ap);
2316 struct ata_eh_info *ehi = &ap->link.eh_info;
2317 struct ahci_port_priv *pp = ap->private_data;
2318 struct ahci_host_priv *hpriv = ap->host->private_data;
2319 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
2320 u32 status, qc_active = 0;
2321 int rc;
2322
2323 status = readl(port_mmio + PORT_IRQ_STAT);
2324 writel(status, port_mmio + PORT_IRQ_STAT);
2325
2326 /* ignore BAD_PMP while resetting */
2327 if (unlikely(resetting))
2328 status &= ~PORT_IRQ_BAD_PMP;
2329
2330 /* If we are getting PhyRdy, this is
2331 * just a power state change, we should
2332 * clear out this, plus the PhyRdy/Comm
2333 * Wake bits from Serror
2334 */
2335 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2336 (status & PORT_IRQ_PHYRDY)) {
2337 status &= ~PORT_IRQ_PHYRDY;
2338 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
2339 }
2340
2341 if (unlikely(status & PORT_IRQ_ERROR)) {
2342 ahci_error_intr(ap, status);
2343 return;
2344 }
2345
2346 if (status & PORT_IRQ_SDB_FIS) {
2347 /* If SNotification is available, leave notification
2348 * handling to sata_async_notification(). If not,
2349 * emulate it by snooping SDB FIS RX area.
2350 *
2351 * Snooping FIS RX area is probably cheaper than
2352 * poking SNotification but some constrollers which
2353 * implement SNotification, ICH9 for example, don't
2354 * store AN SDB FIS into receive area.
2355 */
2356 if (hpriv->cap & HOST_CAP_SNTF)
2357 sata_async_notification(ap);
2358 else {
2359 /* If the 'N' bit in word 0 of the FIS is set,
2360 * we just received asynchronous notification.
2361 * Tell libata about it.
2362 *
2363 * Lack of SNotification should not appear in
2364 * ahci 1.2, so the workaround is unnecessary
2365 * when FBS is enabled.
2366 */
2367 if (pp->fbs_enabled)
2368 WARN_ON_ONCE(1);
2369 else {
2370 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2371 u32 f0 = le32_to_cpu(f[0]);
2372 if (f0 & (1 << 15))
2373 sata_async_notification(ap);
2374 }
2375 }
2376 }
2377
2378 /* pp->active_link is not reliable once FBS is enabled, both
2379 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
2380 * NCQ and non-NCQ commands may be in flight at the same time.
2381 */
2382 if (pp->fbs_enabled) {
2383 if (ap->qc_active) {
2384 qc_active = readl(port_mmio + PORT_SCR_ACT);
2385 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
2386 }
2387 } else {
2388 /* pp->active_link is valid iff any command is in flight */
2389 if (ap->qc_active && pp->active_link->sactive)
2390 qc_active = readl(port_mmio + PORT_SCR_ACT);
2391 else
2392 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2393 }
2394
2395 rc = ata_qc_complete_multiple(ap, qc_active);
2396
2397 /* while resetting, invalid completions are expected */
2398 if (unlikely(rc < 0 && !resetting)) {
2399 ehi->err_mask |= AC_ERR_HSM;
2400 ehi->action |= ATA_EH_RESET;
2401 ata_port_freeze(ap);
2402 }
2403}
2404
2405static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
2406{
2407 struct ata_host *host = dev_instance;
2408 struct ahci_host_priv *hpriv;
2409 unsigned int i, handled = 0;
2410 void __iomem *mmio;
2411 u32 irq_stat, irq_masked;
2412
2413 VPRINTK("ENTER\n");
2414
2415 hpriv = host->private_data;
2416 mmio = hpriv->mmio;
2417
2418 /* sigh. 0xffffffff is a valid return from h/w */
2419 irq_stat = readl(mmio + HOST_IRQ_STAT);
2420 if (!irq_stat)
2421 return IRQ_NONE;
2422
2423 irq_masked = irq_stat & hpriv->port_map;
2424
2425 spin_lock(&host->lock);
2426
2427 for (i = 0; i < host->n_ports; i++) {
2428 struct ata_port *ap;
2429
2430 if (!(irq_masked & (1 << i)))
2431 continue;
2432
2433 ap = host->ports[i];
2434 if (ap) {
2435 ahci_port_intr(ap);
2436 VPRINTK("port %u\n", i);
2437 } else {
2438 VPRINTK("port %u (no irq)\n", i);
2439 if (ata_ratelimit())
2440 dev_printk(KERN_WARNING, host->dev,
2441 "interrupt on disabled port %u\n", i);
2442 }
2443
2444 handled = 1;
2445 }
2446
2447 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2448 * it should be cleared after all the port events are cleared;
2449 * otherwise, it will raise a spurious interrupt after each
2450 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2451 * information.
2452 *
2453 * Also, use the unmasked value to clear interrupt as spurious
2454 * pending event on a dummy port might cause screaming IRQ.
2455 */
2456 writel(irq_stat, mmio + HOST_IRQ_STAT);
2457
2458 spin_unlock(&host->lock);
2459
2460 VPRINTK("EXIT\n");
2461
2462 return IRQ_RETVAL(handled);
2463}
2464
2465static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2466{
2467 struct ata_port *ap = qc->ap;
2468 void __iomem *port_mmio = ahci_port_base(ap);
2469 struct ahci_port_priv *pp = ap->private_data;
2470
2471 /* Keep track of the currently active link. It will be used
2472 * in completion path to determine whether NCQ phase is in
2473 * progress.
2474 */
2475 pp->active_link = qc->dev->link;
2476
2477 if (qc->tf.protocol == ATA_PROT_NCQ)
2478 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2479
2480 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2481 u32 fbs = readl(port_mmio + PORT_FBS);
2482 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2483 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2484 writel(fbs, port_mmio + PORT_FBS);
2485 pp->fbs_last_dev = qc->dev->link->pmp;
2486 }
2487
2488 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2489
2490 ahci_sw_activity(qc->dev->link);
2491
2492 return 0;
2493}
2494
2495static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2496{
2497 struct ahci_port_priv *pp = qc->ap->private_data;
2498 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2499
2500 if (pp->fbs_enabled)
2501 d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2502
2503 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2504 return true;
2505}
2506
2507static void ahci_freeze(struct ata_port *ap)
2508{
2509 void __iomem *port_mmio = ahci_port_base(ap);
2510
2511 /* turn IRQ off */
2512 writel(0, port_mmio + PORT_IRQ_MASK);
2513}
2514
2515static void ahci_thaw(struct ata_port *ap)
2516{
2517 struct ahci_host_priv *hpriv = ap->host->private_data;
2518 void __iomem *mmio = hpriv->mmio;
2519 void __iomem *port_mmio = ahci_port_base(ap);
2520 u32 tmp;
2521 struct ahci_port_priv *pp = ap->private_data;
2522
2523 /* clear IRQ */
2524 tmp = readl(port_mmio + PORT_IRQ_STAT);
2525 writel(tmp, port_mmio + PORT_IRQ_STAT);
2526 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2527
2528 /* turn IRQ back on */
2529 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2530}
2531
2532static void ahci_error_handler(struct ata_port *ap)
2533{
2534 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2535 /* restart engine */
2536 ahci_stop_engine(ap);
2537 ahci_start_engine(ap);
2538 }
2539
2540 sata_pmp_error_handler(ap);
2541}
2542
2543static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2544{
2545 struct ata_port *ap = qc->ap;
2546
2547 /* make DMA engine forget about the failed command */
2548 if (qc->flags & ATA_QCFLAG_FAILED)
2549 ahci_kick_engine(ap);
2550}
2551
2552static void ahci_enable_fbs(struct ata_port *ap)
2553{
2554 struct ahci_port_priv *pp = ap->private_data;
2555 void __iomem *port_mmio = ahci_port_base(ap);
2556 u32 fbs;
2557 int rc;
2558
2559 if (!pp->fbs_supported)
2560 return;
2561
2562 fbs = readl(port_mmio + PORT_FBS);
2563 if (fbs & PORT_FBS_EN) {
2564 pp->fbs_enabled = true;
2565 pp->fbs_last_dev = -1; /* initialization */
2566 return;
2567 }
2568
2569 rc = ahci_stop_engine(ap);
2570 if (rc)
2571 return;
2572
2573 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2574 fbs = readl(port_mmio + PORT_FBS);
2575 if (fbs & PORT_FBS_EN) {
2576 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
2577 pp->fbs_enabled = true;
2578 pp->fbs_last_dev = -1; /* initialization */
2579 } else
2580 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
2581
2582 ahci_start_engine(ap);
2583}
2584
2585static void ahci_disable_fbs(struct ata_port *ap)
2586{
2587 struct ahci_port_priv *pp = ap->private_data;
2588 void __iomem *port_mmio = ahci_port_base(ap);
2589 u32 fbs;
2590 int rc;
2591
2592 if (!pp->fbs_supported)
2593 return;
2594
2595 fbs = readl(port_mmio + PORT_FBS);
2596 if ((fbs & PORT_FBS_EN) == 0) {
2597 pp->fbs_enabled = false;
2598 return;
2599 }
2600
2601 rc = ahci_stop_engine(ap);
2602 if (rc)
2603 return;
2604
2605 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2606 fbs = readl(port_mmio + PORT_FBS);
2607 if (fbs & PORT_FBS_EN)
2608 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
2609 else {
2610 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
2611 pp->fbs_enabled = false;
2612 }
2613
2614 ahci_start_engine(ap);
2615}
2616
2617static void ahci_pmp_attach(struct ata_port *ap)
2618{
2619 void __iomem *port_mmio = ahci_port_base(ap);
2620 struct ahci_port_priv *pp = ap->private_data;
2621 u32 cmd;
2622
2623 cmd = readl(port_mmio + PORT_CMD);
2624 cmd |= PORT_CMD_PMP;
2625 writel(cmd, port_mmio + PORT_CMD);
2626
2627 ahci_enable_fbs(ap);
2628
2629 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2630 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2631}
2632
2633static void ahci_pmp_detach(struct ata_port *ap)
2634{
2635 void __iomem *port_mmio = ahci_port_base(ap);
2636 struct ahci_port_priv *pp = ap->private_data;
2637 u32 cmd;
2638
2639 ahci_disable_fbs(ap);
2640
2641 cmd = readl(port_mmio + PORT_CMD);
2642 cmd &= ~PORT_CMD_PMP;
2643 writel(cmd, port_mmio + PORT_CMD);
2644
2645 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2646 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2647}
2648
2649static int ahci_port_resume(struct ata_port *ap)
2650{
2651 ahci_power_up(ap);
2652 ahci_start_port(ap);
2653
2654 if (sata_pmp_attached(ap))
2655 ahci_pmp_attach(ap);
2656 else
2657 ahci_pmp_detach(ap);
2658
2659 return 0;
2660}
2661
2662#ifdef CONFIG_PM 577#ifdef CONFIG_PM
2663static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2664{
2665 const char *emsg = NULL;
2666 int rc;
2667
2668 rc = ahci_deinit_port(ap, &emsg);
2669 if (rc == 0)
2670 ahci_power_down(ap);
2671 else {
2672 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2673 ahci_start_port(ap);
2674 }
2675
2676 return rc;
2677}
2678
2679static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) 578static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2680{ 579{
2681 struct ata_host *host = dev_get_drvdata(&pdev->dev); 580 struct ata_host *host = dev_get_drvdata(&pdev->dev);
@@ -2727,92 +626,6 @@ static int ahci_pci_device_resume(struct pci_dev *pdev)
2727} 626}
2728#endif 627#endif
2729 628
2730static int ahci_port_start(struct ata_port *ap)
2731{
2732 struct ahci_host_priv *hpriv = ap->host->private_data;
2733 struct device *dev = ap->host->dev;
2734 struct ahci_port_priv *pp;
2735 void *mem;
2736 dma_addr_t mem_dma;
2737 size_t dma_sz, rx_fis_sz;
2738
2739 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2740 if (!pp)
2741 return -ENOMEM;
2742
2743 /* check FBS capability */
2744 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2745 void __iomem *port_mmio = ahci_port_base(ap);
2746 u32 cmd = readl(port_mmio + PORT_CMD);
2747 if (cmd & PORT_CMD_FBSCP)
2748 pp->fbs_supported = true;
2749 else
2750 dev_printk(KERN_WARNING, dev,
2751 "The port is not capable of FBS\n");
2752 }
2753
2754 if (pp->fbs_supported) {
2755 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2756 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2757 } else {
2758 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2759 rx_fis_sz = AHCI_RX_FIS_SZ;
2760 }
2761
2762 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2763 if (!mem)
2764 return -ENOMEM;
2765 memset(mem, 0, dma_sz);
2766
2767 /*
2768 * First item in chunk of DMA memory: 32-slot command table,
2769 * 32 bytes each in size
2770 */
2771 pp->cmd_slot = mem;
2772 pp->cmd_slot_dma = mem_dma;
2773
2774 mem += AHCI_CMD_SLOT_SZ;
2775 mem_dma += AHCI_CMD_SLOT_SZ;
2776
2777 /*
2778 * Second item: Received-FIS area
2779 */
2780 pp->rx_fis = mem;
2781 pp->rx_fis_dma = mem_dma;
2782
2783 mem += rx_fis_sz;
2784 mem_dma += rx_fis_sz;
2785
2786 /*
2787 * Third item: data area for storing a single command
2788 * and its scatter-gather table
2789 */
2790 pp->cmd_tbl = mem;
2791 pp->cmd_tbl_dma = mem_dma;
2792
2793 /*
2794 * Save off initial list of interrupts to be enabled.
2795 * This could be changed later
2796 */
2797 pp->intr_mask = DEF_PORT_IRQ;
2798
2799 ap->private_data = pp;
2800
2801 /* engage engines, captain */
2802 return ahci_port_resume(ap);
2803}
2804
2805static void ahci_port_stop(struct ata_port *ap)
2806{
2807 const char *emsg = NULL;
2808 int rc;
2809
2810 /* de-initialize port */
2811 rc = ahci_deinit_port(ap, &emsg);
2812 if (rc)
2813 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2814}
2815
2816static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) 629static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2817{ 630{
2818 int rc; 631 int rc;
@@ -2845,74 +658,6 @@ static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2845 return 0; 658 return 0;
2846} 659}
2847 660
2848static void ahci_print_info(struct ata_host *host, const char *scc_s)
2849{
2850 struct ahci_host_priv *hpriv = host->private_data;
2851 void __iomem *mmio = hpriv->mmio;
2852 u32 vers, cap, cap2, impl, speed;
2853 const char *speed_s;
2854
2855 vers = readl(mmio + HOST_VERSION);
2856 cap = hpriv->cap;
2857 cap2 = hpriv->cap2;
2858 impl = hpriv->port_map;
2859
2860 speed = (cap >> 20) & 0xf;
2861 if (speed == 1)
2862 speed_s = "1.5";
2863 else if (speed == 2)
2864 speed_s = "3";
2865 else if (speed == 3)
2866 speed_s = "6";
2867 else
2868 speed_s = "?";
2869
2870 dev_info(host->dev,
2871 "AHCI %02x%02x.%02x%02x "
2872 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2873 ,
2874
2875 (vers >> 24) & 0xff,
2876 (vers >> 16) & 0xff,
2877 (vers >> 8) & 0xff,
2878 vers & 0xff,
2879
2880 ((cap >> 8) & 0x1f) + 1,
2881 (cap & 0x1f) + 1,
2882 speed_s,
2883 impl,
2884 scc_s);
2885
2886 dev_info(host->dev,
2887 "flags: "
2888 "%s%s%s%s%s%s%s"
2889 "%s%s%s%s%s%s%s"
2890 "%s%s%s%s%s%s\n"
2891 ,
2892
2893 cap & HOST_CAP_64 ? "64bit " : "",
2894 cap & HOST_CAP_NCQ ? "ncq " : "",
2895 cap & HOST_CAP_SNTF ? "sntf " : "",
2896 cap & HOST_CAP_MPS ? "ilck " : "",
2897 cap & HOST_CAP_SSS ? "stag " : "",
2898 cap & HOST_CAP_ALPM ? "pm " : "",
2899 cap & HOST_CAP_LED ? "led " : "",
2900 cap & HOST_CAP_CLO ? "clo " : "",
2901 cap & HOST_CAP_ONLY ? "only " : "",
2902 cap & HOST_CAP_PMP ? "pmp " : "",
2903 cap & HOST_CAP_FBS ? "fbs " : "",
2904 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2905 cap & HOST_CAP_SSC ? "slum " : "",
2906 cap & HOST_CAP_PART ? "part " : "",
2907 cap & HOST_CAP_CCC ? "ccc " : "",
2908 cap & HOST_CAP_EMS ? "ems " : "",
2909 cap & HOST_CAP_SXS ? "sxs " : "",
2910 cap2 & HOST_CAP2_APST ? "apst " : "",
2911 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2912 cap2 & HOST_CAP2_BOH ? "boh " : ""
2913 );
2914}
2915
2916static void ahci_pci_print_info(struct ata_host *host) 661static void ahci_pci_print_info(struct ata_host *host)
2917{ 662{
2918 struct pci_dev *pdev = to_pci_dev(host->dev); 663 struct pci_dev *pdev = to_pci_dev(host->dev);
@@ -3270,29 +1015,6 @@ static inline void ahci_gtf_filter_workaround(struct ata_host *host)
3270{} 1015{}
3271#endif 1016#endif
3272 1017
3273static void ahci_set_em_messages(struct ahci_host_priv *hpriv,
3274 struct ata_port_info *pi)
3275{
3276 u8 messages;
3277 void __iomem *mmio = hpriv->mmio;
3278 u32 em_loc = readl(mmio + HOST_EM_LOC);
3279 u32 em_ctl = readl(mmio + HOST_EM_CTL);
3280
3281 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
3282 return;
3283
3284 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
3285
3286 /* we only support LED message type right now */
3287 if ((messages & 0x01) && (ahci_em_messages == 1)) {
3288 /* store em_loc */
3289 hpriv->em_loc = ((em_loc >> 16) * 4);
3290 pi->flags |= ATA_FLAG_EM;
3291 if (!(em_ctl & EM_CTL_ALHD))
3292 pi->flags |= ATA_FLAG_SW_ACTIVITY;
3293 }
3294}
3295
3296static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1018static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3297{ 1019{
3298 static int printed_version; 1020 static int printed_version;
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
new file mode 100644
index 000000000000..111a878d9188
--- /dev/null
+++ b/drivers/ata/ahci.h
@@ -0,0 +1,332 @@
1/*
2 * ahci.h - Common AHCI SATA definitions and declarations
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#ifndef _AHCI_H
36#define _AHCI_H
37
38#include <linux/libata.h>
39
40/* Enclosure Management Control */
41#define EM_CTRL_MSG_TYPE 0x000f0000
42
43/* Enclosure Management LED Message Type */
44#define EM_MSG_LED_HBA_PORT 0x0000000f
45#define EM_MSG_LED_PMP_SLOT 0x0000ff00
46#define EM_MSG_LED_VALUE 0xffff0000
47#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
48#define EM_MSG_LED_VALUE_OFF 0xfff80000
49#define EM_MSG_LED_VALUE_ON 0x00010000
50
51enum {
52 AHCI_MAX_PORTS = 32,
53 AHCI_MAX_SG = 168, /* hardware max is 64K */
54 AHCI_DMA_BOUNDARY = 0xffffffff,
55 AHCI_MAX_CMDS = 32,
56 AHCI_CMD_SZ = 32,
57 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
58 AHCI_RX_FIS_SZ = 256,
59 AHCI_CMD_TBL_CDB = 0x40,
60 AHCI_CMD_TBL_HDR_SZ = 0x80,
61 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
62 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
63 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
64 AHCI_RX_FIS_SZ,
65 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
66 AHCI_CMD_TBL_AR_SZ +
67 (AHCI_RX_FIS_SZ * 16),
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
74
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
78
79 /* global controller registers */
80 HOST_CAP = 0x00, /* host capabilities */
81 HOST_CTL = 0x04, /* global host control */
82 HOST_IRQ_STAT = 0x08, /* interrupt status */
83 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
84 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
85 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
86 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
87 HOST_CAP2 = 0x24, /* host capabilities, extended */
88
89 /* HOST_CTL bits */
90 HOST_RESET = (1 << 0), /* reset controller; self-clear */
91 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
92 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
93
94 /* HOST_CAP bits */
95 HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
96 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
97 HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
98 HOST_CAP_PART = (1 << 13), /* Partial state capable */
99 HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
100 HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
101 HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
102 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
103 HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
104 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
105 HOST_CAP_LED = (1 << 25), /* Supports activity LED */
106 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
107 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
108 HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
109 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
110 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
111 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
112
113 /* HOST_CAP2 bits */
114 HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
115 HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
116 HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
117
118 /* registers for each SATA port */
119 PORT_LST_ADDR = 0x00, /* command list DMA addr */
120 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
121 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
122 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
123 PORT_IRQ_STAT = 0x10, /* interrupt status */
124 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
125 PORT_CMD = 0x18, /* port command */
126 PORT_TFDATA = 0x20, /* taskfile data */
127 PORT_SIG = 0x24, /* device TF signature */
128 PORT_CMD_ISSUE = 0x38, /* command issue */
129 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
130 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
131 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
132 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
133 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
134 PORT_FBS = 0x40, /* FIS-based Switching */
135
136 /* PORT_IRQ_{STAT,MASK} bits */
137 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
138 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
139 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
140 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
141 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
142 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
143 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
144 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
145
146 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
147 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
148 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
149 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
150 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
151 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
152 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
153 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
154 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
155
156 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
157 PORT_IRQ_IF_ERR |
158 PORT_IRQ_CONNECT |
159 PORT_IRQ_PHYRDY |
160 PORT_IRQ_UNK_FIS |
161 PORT_IRQ_BAD_PMP,
162 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
163 PORT_IRQ_TF_ERR |
164 PORT_IRQ_HBUS_DATA_ERR,
165 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
166 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
167 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
168
169 /* PORT_CMD bits */
170 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
171 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
172 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
173 PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
174 PORT_CMD_PMP = (1 << 17), /* PMP attached */
175 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
176 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
177 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
178 PORT_CMD_CLO = (1 << 3), /* Command list override */
179 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
180 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
181 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
182
183 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
184 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
185 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
186 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
187
188 PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
189 PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
190 PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
191 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
192 PORT_FBS_SDE = (1 << 2), /* FBS single device error */
193 PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
194 PORT_FBS_EN = (1 << 0), /* Enable FBS */
195
196 /* hpriv->flags bits */
197 AHCI_HFLAG_NO_NCQ = (1 << 0),
198 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
199 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
200 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
201 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
202 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
203 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
204 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
205 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
206 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
207 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
208 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
209 link offline */
210 AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
211
212 /* ap->flags bits */
213
214 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
215 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
216 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
217 ATA_FLAG_IPM,
218
219 ICH_MAP = 0x90, /* ICH MAP register */
220
221 /* em constants */
222 EM_MAX_SLOTS = 8,
223 EM_MAX_RETRY = 5,
224
225 /* em_ctl bits */
226 EM_CTL_RST = (1 << 9), /* Reset */
227 EM_CTL_TM = (1 << 8), /* Transmit Message */
228 EM_CTL_ALHD = (1 << 26), /* Activity LED */
229};
230
231struct ahci_cmd_hdr {
232 __le32 opts;
233 __le32 status;
234 __le32 tbl_addr;
235 __le32 tbl_addr_hi;
236 __le32 reserved[4];
237};
238
239struct ahci_sg {
240 __le32 addr;
241 __le32 addr_hi;
242 __le32 reserved;
243 __le32 flags_size;
244};
245
246struct ahci_em_priv {
247 enum sw_activity blink_policy;
248 struct timer_list timer;
249 unsigned long saved_activity;
250 unsigned long activity;
251 unsigned long led_state;
252};
253
254struct ahci_port_priv {
255 struct ata_link *active_link;
256 struct ahci_cmd_hdr *cmd_slot;
257 dma_addr_t cmd_slot_dma;
258 void *cmd_tbl;
259 dma_addr_t cmd_tbl_dma;
260 void *rx_fis;
261 dma_addr_t rx_fis_dma;
262 /* for NCQ spurious interrupt analysis */
263 unsigned int ncq_saw_d2h:1;
264 unsigned int ncq_saw_dmas:1;
265 unsigned int ncq_saw_sdb:1;
266 u32 intr_mask; /* interrupts to enable */
267 bool fbs_supported; /* set iff FBS is supported */
268 bool fbs_enabled; /* set iff FBS is enabled */
269 int fbs_last_dev; /* save FBS.DEV of last FIS */
270 /* enclosure management info per PM slot */
271 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
272};
273
274struct ahci_host_priv {
275 void __iomem * mmio; /* bus-independant mem map */
276 unsigned int flags; /* AHCI_HFLAG_* */
277 u32 cap; /* cap to use */
278 u32 cap2; /* cap2 to use */
279 u32 port_map; /* port map to use */
280 u32 saved_cap; /* saved initial cap */
281 u32 saved_cap2; /* saved initial cap2 */
282 u32 saved_port_map; /* saved initial port_map */
283 u32 em_loc; /* enclosure management location */
284};
285
286extern int ahci_em_messages;
287extern int ahci_ignore_sss;
288
289extern struct scsi_host_template ahci_sht;
290extern struct ata_port_operations ahci_ops;
291
292void ahci_save_initial_config(struct device *dev,
293 struct ahci_host_priv *hpriv,
294 unsigned int force_port_map,
295 unsigned int mask_port_map);
296void ahci_init_controller(struct ata_host *host);
297int ahci_reset_controller(struct ata_host *host);
298
299int ahci_do_softreset(struct ata_link *link, unsigned int *class,
300 int pmp, unsigned long deadline,
301 int (*check_ready)(struct ata_link *link));
302
303int ahci_stop_engine(struct ata_port *ap);
304void ahci_start_engine(struct ata_port *ap);
305int ahci_check_ready(struct ata_link *link);
306int ahci_kick_engine(struct ata_port *ap);
307void ahci_set_em_messages(struct ahci_host_priv *hpriv,
308 struct ata_port_info *pi);
309int ahci_reset_em(struct ata_host *host);
310irqreturn_t ahci_interrupt(int irq, void *dev_instance);
311void ahci_print_info(struct ata_host *host, const char *scc_s);
312
313static inline void __iomem *__ahci_port_base(struct ata_host *host,
314 unsigned int port_no)
315{
316 struct ahci_host_priv *hpriv = host->private_data;
317 void __iomem *mmio = hpriv->mmio;
318
319 return mmio + 0x100 + (port_no * 0x80);
320}
321
322static inline void __iomem *ahci_port_base(struct ata_port *ap)
323{
324 return __ahci_port_base(ap->host, ap->port_no);
325}
326
327static inline int ahci_nr_ports(u32 cap)
328{
329 return (cap & 0x1f) + 1;
330}
331
332#endif /* _AHCI_H */
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
new file mode 100644
index 000000000000..38e1b4e9ecf4
--- /dev/null
+++ b/drivers/ata/libahci.c
@@ -0,0 +1,2091 @@
1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <scsi/scsi_host.h>
44#include <scsi/scsi_cmnd.h>
45#include <linux/libata.h>
46#include "ahci.h"
47
48static int ahci_skip_host_reset;
49int ahci_ignore_sss;
50EXPORT_SYMBOL_GPL(ahci_ignore_sss);
51
52module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
53MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
54
55module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
56MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
57
58static int ahci_enable_alpm(struct ata_port *ap,
59 enum link_pm policy);
60static void ahci_disable_alpm(struct ata_port *ap);
61static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
63 size_t size);
64static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
65 ssize_t size);
66
67
68
69static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
72static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73static int ahci_port_start(struct ata_port *ap);
74static void ahci_port_stop(struct ata_port *ap);
75static void ahci_qc_prep(struct ata_queued_cmd *qc);
76static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77static void ahci_freeze(struct ata_port *ap);
78static void ahci_thaw(struct ata_port *ap);
79static void ahci_enable_fbs(struct ata_port *ap);
80static void ahci_disable_fbs(struct ata_port *ap);
81static void ahci_pmp_attach(struct ata_port *ap);
82static void ahci_pmp_detach(struct ata_port *ap);
83static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87static void ahci_postreset(struct ata_link *link, unsigned int *class);
88static void ahci_error_handler(struct ata_port *ap);
89static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
90static int ahci_port_resume(struct ata_port *ap);
91static void ahci_dev_config(struct ata_device *dev);
92static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
93 u32 opts);
94#ifdef CONFIG_PM
95static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96#endif
97static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100static void ahci_init_sw_activity(struct ata_link *link);
101
102static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
110
111static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
112static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
113static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
114static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
115
116static struct device_attribute *ahci_shost_attrs[] = {
117 &dev_attr_link_power_management_policy,
118 &dev_attr_em_message_type,
119 &dev_attr_em_message,
120 &dev_attr_ahci_host_caps,
121 &dev_attr_ahci_host_cap2,
122 &dev_attr_ahci_host_version,
123 &dev_attr_ahci_port_cmd,
124 NULL
125};
126
127static struct device_attribute *ahci_sdev_attrs[] = {
128 &dev_attr_sw_activity,
129 &dev_attr_unload_heads,
130 NULL
131};
132
133struct scsi_host_template ahci_sht = {
134 ATA_NCQ_SHT("ahci"),
135 .can_queue = AHCI_MAX_CMDS - 1,
136 .sg_tablesize = AHCI_MAX_SG,
137 .dma_boundary = AHCI_DMA_BOUNDARY,
138 .shost_attrs = ahci_shost_attrs,
139 .sdev_attrs = ahci_sdev_attrs,
140};
141EXPORT_SYMBOL_GPL(ahci_sht);
142
143struct ata_port_operations ahci_ops = {
144 .inherits = &sata_pmp_port_ops,
145
146 .qc_defer = ahci_pmp_qc_defer,
147 .qc_prep = ahci_qc_prep,
148 .qc_issue = ahci_qc_issue,
149 .qc_fill_rtf = ahci_qc_fill_rtf,
150
151 .freeze = ahci_freeze,
152 .thaw = ahci_thaw,
153 .softreset = ahci_softreset,
154 .hardreset = ahci_hardreset,
155 .postreset = ahci_postreset,
156 .pmp_softreset = ahci_softreset,
157 .error_handler = ahci_error_handler,
158 .post_internal_cmd = ahci_post_internal_cmd,
159 .dev_config = ahci_dev_config,
160
161 .scr_read = ahci_scr_read,
162 .scr_write = ahci_scr_write,
163 .pmp_attach = ahci_pmp_attach,
164 .pmp_detach = ahci_pmp_detach,
165
166 .enable_pm = ahci_enable_alpm,
167 .disable_pm = ahci_disable_alpm,
168 .em_show = ahci_led_show,
169 .em_store = ahci_led_store,
170 .sw_activity_show = ahci_activity_show,
171 .sw_activity_store = ahci_activity_store,
172#ifdef CONFIG_PM
173 .port_suspend = ahci_port_suspend,
174 .port_resume = ahci_port_resume,
175#endif
176 .port_start = ahci_port_start,
177 .port_stop = ahci_port_stop,
178};
179EXPORT_SYMBOL_GPL(ahci_ops);
180
181int ahci_em_messages = 1;
182EXPORT_SYMBOL_GPL(ahci_em_messages);
183module_param(ahci_em_messages, int, 0444);
184/* add other LED protocol types when they become supported */
185MODULE_PARM_DESC(ahci_em_messages,
186 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
187
188static void ahci_enable_ahci(void __iomem *mmio)
189{
190 int i;
191 u32 tmp;
192
193 /* turn on AHCI_EN */
194 tmp = readl(mmio + HOST_CTL);
195 if (tmp & HOST_AHCI_EN)
196 return;
197
198 /* Some controllers need AHCI_EN to be written multiple times.
199 * Try a few times before giving up.
200 */
201 for (i = 0; i < 5; i++) {
202 tmp |= HOST_AHCI_EN;
203 writel(tmp, mmio + HOST_CTL);
204 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
205 if (tmp & HOST_AHCI_EN)
206 return;
207 msleep(10);
208 }
209
210 WARN_ON(1);
211}
212
213static ssize_t ahci_show_host_caps(struct device *dev,
214 struct device_attribute *attr, char *buf)
215{
216 struct Scsi_Host *shost = class_to_shost(dev);
217 struct ata_port *ap = ata_shost_to_port(shost);
218 struct ahci_host_priv *hpriv = ap->host->private_data;
219
220 return sprintf(buf, "%x\n", hpriv->cap);
221}
222
223static ssize_t ahci_show_host_cap2(struct device *dev,
224 struct device_attribute *attr, char *buf)
225{
226 struct Scsi_Host *shost = class_to_shost(dev);
227 struct ata_port *ap = ata_shost_to_port(shost);
228 struct ahci_host_priv *hpriv = ap->host->private_data;
229
230 return sprintf(buf, "%x\n", hpriv->cap2);
231}
232
233static ssize_t ahci_show_host_version(struct device *dev,
234 struct device_attribute *attr, char *buf)
235{
236 struct Scsi_Host *shost = class_to_shost(dev);
237 struct ata_port *ap = ata_shost_to_port(shost);
238 struct ahci_host_priv *hpriv = ap->host->private_data;
239 void __iomem *mmio = hpriv->mmio;
240
241 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
242}
243
244static ssize_t ahci_show_port_cmd(struct device *dev,
245 struct device_attribute *attr, char *buf)
246{
247 struct Scsi_Host *shost = class_to_shost(dev);
248 struct ata_port *ap = ata_shost_to_port(shost);
249 void __iomem *port_mmio = ahci_port_base(ap);
250
251 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
252}
253
254/**
255 * ahci_save_initial_config - Save and fixup initial config values
256 * @dev: target AHCI device
257 * @hpriv: host private area to store config values
258 * @force_port_map: force port map to a specified value
259 * @mask_port_map: mask out particular bits from port map
260 *
261 * Some registers containing configuration info might be setup by
262 * BIOS and might be cleared on reset. This function saves the
263 * initial values of those registers into @hpriv such that they
264 * can be restored after controller reset.
265 *
266 * If inconsistent, config values are fixed up by this function.
267 *
268 * LOCKING:
269 * None.
270 */
271void ahci_save_initial_config(struct device *dev,
272 struct ahci_host_priv *hpriv,
273 unsigned int force_port_map,
274 unsigned int mask_port_map)
275{
276 void __iomem *mmio = hpriv->mmio;
277 u32 cap, cap2, vers, port_map;
278 int i;
279
280 /* make sure AHCI mode is enabled before accessing CAP */
281 ahci_enable_ahci(mmio);
282
283 /* Values prefixed with saved_ are written back to host after
284 * reset. Values without are used for driver operation.
285 */
286 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
287 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
288
289 /* CAP2 register is only defined for AHCI 1.2 and later */
290 vers = readl(mmio + HOST_VERSION);
291 if ((vers >> 16) > 1 ||
292 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
293 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
294 else
295 hpriv->saved_cap2 = cap2 = 0;
296
297 /* some chips have errata preventing 64bit use */
298 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
299 dev_printk(KERN_INFO, dev,
300 "controller can't do 64bit DMA, forcing 32bit\n");
301 cap &= ~HOST_CAP_64;
302 }
303
304 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
305 dev_printk(KERN_INFO, dev,
306 "controller can't do NCQ, turning off CAP_NCQ\n");
307 cap &= ~HOST_CAP_NCQ;
308 }
309
310 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
311 dev_printk(KERN_INFO, dev,
312 "controller can do NCQ, turning on CAP_NCQ\n");
313 cap |= HOST_CAP_NCQ;
314 }
315
316 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
317 dev_printk(KERN_INFO, dev,
318 "controller can't do PMP, turning off CAP_PMP\n");
319 cap &= ~HOST_CAP_PMP;
320 }
321
322 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
323 dev_printk(KERN_INFO, dev,
324 "controller can't do SNTF, turning off CAP_SNTF\n");
325 cap &= ~HOST_CAP_SNTF;
326 }
327
328 if (force_port_map && port_map != force_port_map) {
329 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
330 port_map, force_port_map);
331 port_map = force_port_map;
332 }
333
334 if (mask_port_map) {
335 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
336 port_map,
337 port_map & mask_port_map);
338 port_map &= mask_port_map;
339 }
340
341 /* cross check port_map and cap.n_ports */
342 if (port_map) {
343 int map_ports = 0;
344
345 for (i = 0; i < AHCI_MAX_PORTS; i++)
346 if (port_map & (1 << i))
347 map_ports++;
348
349 /* If PI has more ports than n_ports, whine, clear
350 * port_map and let it be generated from n_ports.
351 */
352 if (map_ports > ahci_nr_ports(cap)) {
353 dev_printk(KERN_WARNING, dev,
354 "implemented port map (0x%x) contains more "
355 "ports than nr_ports (%u), using nr_ports\n",
356 port_map, ahci_nr_ports(cap));
357 port_map = 0;
358 }
359 }
360
361 /* fabricate port_map from cap.nr_ports */
362 if (!port_map) {
363 port_map = (1 << ahci_nr_ports(cap)) - 1;
364 dev_printk(KERN_WARNING, dev,
365 "forcing PORTS_IMPL to 0x%x\n", port_map);
366
367 /* write the fixed up value to the PI register */
368 hpriv->saved_port_map = port_map;
369 }
370
371 /* record values to use during operation */
372 hpriv->cap = cap;
373 hpriv->cap2 = cap2;
374 hpriv->port_map = port_map;
375}
376EXPORT_SYMBOL_GPL(ahci_save_initial_config);
377
378/**
379 * ahci_restore_initial_config - Restore initial config
380 * @host: target ATA host
381 *
382 * Restore initial config stored by ahci_save_initial_config().
383 *
384 * LOCKING:
385 * None.
386 */
387static void ahci_restore_initial_config(struct ata_host *host)
388{
389 struct ahci_host_priv *hpriv = host->private_data;
390 void __iomem *mmio = hpriv->mmio;
391
392 writel(hpriv->saved_cap, mmio + HOST_CAP);
393 if (hpriv->saved_cap2)
394 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
395 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
396 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
397}
398
399static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
400{
401 static const int offset[] = {
402 [SCR_STATUS] = PORT_SCR_STAT,
403 [SCR_CONTROL] = PORT_SCR_CTL,
404 [SCR_ERROR] = PORT_SCR_ERR,
405 [SCR_ACTIVE] = PORT_SCR_ACT,
406 [SCR_NOTIFICATION] = PORT_SCR_NTF,
407 };
408 struct ahci_host_priv *hpriv = ap->host->private_data;
409
410 if (sc_reg < ARRAY_SIZE(offset) &&
411 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
412 return offset[sc_reg];
413 return 0;
414}
415
416static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
417{
418 void __iomem *port_mmio = ahci_port_base(link->ap);
419 int offset = ahci_scr_offset(link->ap, sc_reg);
420
421 if (offset) {
422 *val = readl(port_mmio + offset);
423 return 0;
424 }
425 return -EINVAL;
426}
427
428static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
429{
430 void __iomem *port_mmio = ahci_port_base(link->ap);
431 int offset = ahci_scr_offset(link->ap, sc_reg);
432
433 if (offset) {
434 writel(val, port_mmio + offset);
435 return 0;
436 }
437 return -EINVAL;
438}
439
440void ahci_start_engine(struct ata_port *ap)
441{
442 void __iomem *port_mmio = ahci_port_base(ap);
443 u32 tmp;
444
445 /* start DMA */
446 tmp = readl(port_mmio + PORT_CMD);
447 tmp |= PORT_CMD_START;
448 writel(tmp, port_mmio + PORT_CMD);
449 readl(port_mmio + PORT_CMD); /* flush */
450}
451EXPORT_SYMBOL_GPL(ahci_start_engine);
452
453int ahci_stop_engine(struct ata_port *ap)
454{
455 void __iomem *port_mmio = ahci_port_base(ap);
456 u32 tmp;
457
458 tmp = readl(port_mmio + PORT_CMD);
459
460 /* check if the HBA is idle */
461 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
462 return 0;
463
464 /* setting HBA to idle */
465 tmp &= ~PORT_CMD_START;
466 writel(tmp, port_mmio + PORT_CMD);
467
468 /* wait for engine to stop. This could be as long as 500 msec */
469 tmp = ata_wait_register(port_mmio + PORT_CMD,
470 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
471 if (tmp & PORT_CMD_LIST_ON)
472 return -EIO;
473
474 return 0;
475}
476EXPORT_SYMBOL_GPL(ahci_stop_engine);
477
478static void ahci_start_fis_rx(struct ata_port *ap)
479{
480 void __iomem *port_mmio = ahci_port_base(ap);
481 struct ahci_host_priv *hpriv = ap->host->private_data;
482 struct ahci_port_priv *pp = ap->private_data;
483 u32 tmp;
484
485 /* set FIS registers */
486 if (hpriv->cap & HOST_CAP_64)
487 writel((pp->cmd_slot_dma >> 16) >> 16,
488 port_mmio + PORT_LST_ADDR_HI);
489 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
490
491 if (hpriv->cap & HOST_CAP_64)
492 writel((pp->rx_fis_dma >> 16) >> 16,
493 port_mmio + PORT_FIS_ADDR_HI);
494 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
495
496 /* enable FIS reception */
497 tmp = readl(port_mmio + PORT_CMD);
498 tmp |= PORT_CMD_FIS_RX;
499 writel(tmp, port_mmio + PORT_CMD);
500
501 /* flush */
502 readl(port_mmio + PORT_CMD);
503}
504
505static int ahci_stop_fis_rx(struct ata_port *ap)
506{
507 void __iomem *port_mmio = ahci_port_base(ap);
508 u32 tmp;
509
510 /* disable FIS reception */
511 tmp = readl(port_mmio + PORT_CMD);
512 tmp &= ~PORT_CMD_FIS_RX;
513 writel(tmp, port_mmio + PORT_CMD);
514
515 /* wait for completion, spec says 500ms, give it 1000 */
516 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
517 PORT_CMD_FIS_ON, 10, 1000);
518 if (tmp & PORT_CMD_FIS_ON)
519 return -EBUSY;
520
521 return 0;
522}
523
524static void ahci_power_up(struct ata_port *ap)
525{
526 struct ahci_host_priv *hpriv = ap->host->private_data;
527 void __iomem *port_mmio = ahci_port_base(ap);
528 u32 cmd;
529
530 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
531
532 /* spin up device */
533 if (hpriv->cap & HOST_CAP_SSS) {
534 cmd |= PORT_CMD_SPIN_UP;
535 writel(cmd, port_mmio + PORT_CMD);
536 }
537
538 /* wake up link */
539 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
540}
541
542static void ahci_disable_alpm(struct ata_port *ap)
543{
544 struct ahci_host_priv *hpriv = ap->host->private_data;
545 void __iomem *port_mmio = ahci_port_base(ap);
546 u32 cmd;
547 struct ahci_port_priv *pp = ap->private_data;
548
549 /* IPM bits should be disabled by libata-core */
550 /* get the existing command bits */
551 cmd = readl(port_mmio + PORT_CMD);
552
553 /* disable ALPM and ASP */
554 cmd &= ~PORT_CMD_ASP;
555 cmd &= ~PORT_CMD_ALPE;
556
557 /* force the interface back to active */
558 cmd |= PORT_CMD_ICC_ACTIVE;
559
560 /* write out new cmd value */
561 writel(cmd, port_mmio + PORT_CMD);
562 cmd = readl(port_mmio + PORT_CMD);
563
564 /* wait 10ms to be sure we've come out of any low power state */
565 msleep(10);
566
567 /* clear out any PhyRdy stuff from interrupt status */
568 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
569
570 /* go ahead and clean out PhyRdy Change from Serror too */
571 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
572
573 /*
574 * Clear flag to indicate that we should ignore all PhyRdy
575 * state changes
576 */
577 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
578
579 /*
580 * Enable interrupts on Phy Ready.
581 */
582 pp->intr_mask |= PORT_IRQ_PHYRDY;
583 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
584
585 /*
586 * don't change the link pm policy - we can be called
587 * just to turn of link pm temporarily
588 */
589}
590
591static int ahci_enable_alpm(struct ata_port *ap,
592 enum link_pm policy)
593{
594 struct ahci_host_priv *hpriv = ap->host->private_data;
595 void __iomem *port_mmio = ahci_port_base(ap);
596 u32 cmd;
597 struct ahci_port_priv *pp = ap->private_data;
598 u32 asp;
599
600 /* Make sure the host is capable of link power management */
601 if (!(hpriv->cap & HOST_CAP_ALPM))
602 return -EINVAL;
603
604 switch (policy) {
605 case MAX_PERFORMANCE:
606 case NOT_AVAILABLE:
607 /*
608 * if we came here with NOT_AVAILABLE,
609 * it just means this is the first time we
610 * have tried to enable - default to max performance,
611 * and let the user go to lower power modes on request.
612 */
613 ahci_disable_alpm(ap);
614 return 0;
615 case MIN_POWER:
616 /* configure HBA to enter SLUMBER */
617 asp = PORT_CMD_ASP;
618 break;
619 case MEDIUM_POWER:
620 /* configure HBA to enter PARTIAL */
621 asp = 0;
622 break;
623 default:
624 return -EINVAL;
625 }
626
627 /*
628 * Disable interrupts on Phy Ready. This keeps us from
629 * getting woken up due to spurious phy ready interrupts
630 * TBD - Hot plug should be done via polling now, is
631 * that even supported?
632 */
633 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
634 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
635
636 /*
637 * Set a flag to indicate that we should ignore all PhyRdy
638 * state changes since these can happen now whenever we
639 * change link state
640 */
641 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
642
643 /* get the existing command bits */
644 cmd = readl(port_mmio + PORT_CMD);
645
646 /*
647 * Set ASP based on Policy
648 */
649 cmd |= asp;
650
651 /*
652 * Setting this bit will instruct the HBA to aggressively
653 * enter a lower power link state when it's appropriate and
654 * based on the value set above for ASP
655 */
656 cmd |= PORT_CMD_ALPE;
657
658 /* write out new cmd value */
659 writel(cmd, port_mmio + PORT_CMD);
660 cmd = readl(port_mmio + PORT_CMD);
661
662 /* IPM bits should be set by libata-core */
663 return 0;
664}
665
666#ifdef CONFIG_PM
667static void ahci_power_down(struct ata_port *ap)
668{
669 struct ahci_host_priv *hpriv = ap->host->private_data;
670 void __iomem *port_mmio = ahci_port_base(ap);
671 u32 cmd, scontrol;
672
673 if (!(hpriv->cap & HOST_CAP_SSS))
674 return;
675
676 /* put device into listen mode, first set PxSCTL.DET to 0 */
677 scontrol = readl(port_mmio + PORT_SCR_CTL);
678 scontrol &= ~0xf;
679 writel(scontrol, port_mmio + PORT_SCR_CTL);
680
681 /* then set PxCMD.SUD to 0 */
682 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
683 cmd &= ~PORT_CMD_SPIN_UP;
684 writel(cmd, port_mmio + PORT_CMD);
685}
686#endif
687
688static void ahci_start_port(struct ata_port *ap)
689{
690 struct ahci_port_priv *pp = ap->private_data;
691 struct ata_link *link;
692 struct ahci_em_priv *emp;
693 ssize_t rc;
694 int i;
695
696 /* enable FIS reception */
697 ahci_start_fis_rx(ap);
698
699 /* enable DMA */
700 ahci_start_engine(ap);
701
702 /* turn on LEDs */
703 if (ap->flags & ATA_FLAG_EM) {
704 ata_for_each_link(link, ap, EDGE) {
705 emp = &pp->em_priv[link->pmp];
706
707 /* EM Transmit bit maybe busy during init */
708 for (i = 0; i < EM_MAX_RETRY; i++) {
709 rc = ahci_transmit_led_message(ap,
710 emp->led_state,
711 4);
712 if (rc == -EBUSY)
713 msleep(1);
714 else
715 break;
716 }
717 }
718 }
719
720 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
721 ata_for_each_link(link, ap, EDGE)
722 ahci_init_sw_activity(link);
723
724}
725
726static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
727{
728 int rc;
729
730 /* disable DMA */
731 rc = ahci_stop_engine(ap);
732 if (rc) {
733 *emsg = "failed to stop engine";
734 return rc;
735 }
736
737 /* disable FIS reception */
738 rc = ahci_stop_fis_rx(ap);
739 if (rc) {
740 *emsg = "failed stop FIS RX";
741 return rc;
742 }
743
744 return 0;
745}
746
747int ahci_reset_controller(struct ata_host *host)
748{
749 struct ahci_host_priv *hpriv = host->private_data;
750 void __iomem *mmio = hpriv->mmio;
751 u32 tmp;
752
753 /* we must be in AHCI mode, before using anything
754 * AHCI-specific, such as HOST_RESET.
755 */
756 ahci_enable_ahci(mmio);
757
758 /* global controller reset */
759 if (!ahci_skip_host_reset) {
760 tmp = readl(mmio + HOST_CTL);
761 if ((tmp & HOST_RESET) == 0) {
762 writel(tmp | HOST_RESET, mmio + HOST_CTL);
763 readl(mmio + HOST_CTL); /* flush */
764 }
765
766 /*
767 * to perform host reset, OS should set HOST_RESET
768 * and poll until this bit is read to be "0".
769 * reset must complete within 1 second, or
770 * the hardware should be considered fried.
771 */
772 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
773 HOST_RESET, 10, 1000);
774
775 if (tmp & HOST_RESET) {
776 dev_printk(KERN_ERR, host->dev,
777 "controller reset failed (0x%x)\n", tmp);
778 return -EIO;
779 }
780
781 /* turn on AHCI mode */
782 ahci_enable_ahci(mmio);
783
784 /* Some registers might be cleared on reset. Restore
785 * initial values.
786 */
787 ahci_restore_initial_config(host);
788 } else
789 dev_printk(KERN_INFO, host->dev,
790 "skipping global host reset\n");
791
792 return 0;
793}
794EXPORT_SYMBOL_GPL(ahci_reset_controller);
795
796static void ahci_sw_activity(struct ata_link *link)
797{
798 struct ata_port *ap = link->ap;
799 struct ahci_port_priv *pp = ap->private_data;
800 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
801
802 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
803 return;
804
805 emp->activity++;
806 if (!timer_pending(&emp->timer))
807 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
808}
809
810static void ahci_sw_activity_blink(unsigned long arg)
811{
812 struct ata_link *link = (struct ata_link *)arg;
813 struct ata_port *ap = link->ap;
814 struct ahci_port_priv *pp = ap->private_data;
815 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
816 unsigned long led_message = emp->led_state;
817 u32 activity_led_state;
818 unsigned long flags;
819
820 led_message &= EM_MSG_LED_VALUE;
821 led_message |= ap->port_no | (link->pmp << 8);
822
823 /* check to see if we've had activity. If so,
824 * toggle state of LED and reset timer. If not,
825 * turn LED to desired idle state.
826 */
827 spin_lock_irqsave(ap->lock, flags);
828 if (emp->saved_activity != emp->activity) {
829 emp->saved_activity = emp->activity;
830 /* get the current LED state */
831 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
832
833 if (activity_led_state)
834 activity_led_state = 0;
835 else
836 activity_led_state = 1;
837
838 /* clear old state */
839 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
840
841 /* toggle state */
842 led_message |= (activity_led_state << 16);
843 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
844 } else {
845 /* switch to idle */
846 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
847 if (emp->blink_policy == BLINK_OFF)
848 led_message |= (1 << 16);
849 }
850 spin_unlock_irqrestore(ap->lock, flags);
851 ahci_transmit_led_message(ap, led_message, 4);
852}
853
854static void ahci_init_sw_activity(struct ata_link *link)
855{
856 struct ata_port *ap = link->ap;
857 struct ahci_port_priv *pp = ap->private_data;
858 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
859
860 /* init activity stats, setup timer */
861 emp->saved_activity = emp->activity = 0;
862 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
863
864 /* check our blink policy and set flag for link if it's enabled */
865 if (emp->blink_policy)
866 link->flags |= ATA_LFLAG_SW_ACTIVITY;
867}
868
869int ahci_reset_em(struct ata_host *host)
870{
871 struct ahci_host_priv *hpriv = host->private_data;
872 void __iomem *mmio = hpriv->mmio;
873 u32 em_ctl;
874
875 em_ctl = readl(mmio + HOST_EM_CTL);
876 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
877 return -EINVAL;
878
879 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
880 return 0;
881}
882EXPORT_SYMBOL_GPL(ahci_reset_em);
883
884static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
885 ssize_t size)
886{
887 struct ahci_host_priv *hpriv = ap->host->private_data;
888 struct ahci_port_priv *pp = ap->private_data;
889 void __iomem *mmio = hpriv->mmio;
890 u32 em_ctl;
891 u32 message[] = {0, 0};
892 unsigned long flags;
893 int pmp;
894 struct ahci_em_priv *emp;
895
896 /* get the slot number from the message */
897 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
898 if (pmp < EM_MAX_SLOTS)
899 emp = &pp->em_priv[pmp];
900 else
901 return -EINVAL;
902
903 spin_lock_irqsave(ap->lock, flags);
904
905 /*
906 * if we are still busy transmitting a previous message,
907 * do not allow
908 */
909 em_ctl = readl(mmio + HOST_EM_CTL);
910 if (em_ctl & EM_CTL_TM) {
911 spin_unlock_irqrestore(ap->lock, flags);
912 return -EBUSY;
913 }
914
915 /*
916 * create message header - this is all zero except for
917 * the message size, which is 4 bytes.
918 */
919 message[0] |= (4 << 8);
920
921 /* ignore 0:4 of byte zero, fill in port info yourself */
922 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
923
924 /* write message to EM_LOC */
925 writel(message[0], mmio + hpriv->em_loc);
926 writel(message[1], mmio + hpriv->em_loc+4);
927
928 /* save off new led state for port/slot */
929 emp->led_state = state;
930
931 /*
932 * tell hardware to transmit the message
933 */
934 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
935
936 spin_unlock_irqrestore(ap->lock, flags);
937 return size;
938}
939
940static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
941{
942 struct ahci_port_priv *pp = ap->private_data;
943 struct ata_link *link;
944 struct ahci_em_priv *emp;
945 int rc = 0;
946
947 ata_for_each_link(link, ap, EDGE) {
948 emp = &pp->em_priv[link->pmp];
949 rc += sprintf(buf, "%lx\n", emp->led_state);
950 }
951 return rc;
952}
953
954static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
955 size_t size)
956{
957 int state;
958 int pmp;
959 struct ahci_port_priv *pp = ap->private_data;
960 struct ahci_em_priv *emp;
961
962 state = simple_strtoul(buf, NULL, 0);
963
964 /* get the slot number from the message */
965 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
966 if (pmp < EM_MAX_SLOTS)
967 emp = &pp->em_priv[pmp];
968 else
969 return -EINVAL;
970
971 /* mask off the activity bits if we are in sw_activity
972 * mode, user should turn off sw_activity before setting
973 * activity led through em_message
974 */
975 if (emp->blink_policy)
976 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
977
978 return ahci_transmit_led_message(ap, state, size);
979}
980
981static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
982{
983 struct ata_link *link = dev->link;
984 struct ata_port *ap = link->ap;
985 struct ahci_port_priv *pp = ap->private_data;
986 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
987 u32 port_led_state = emp->led_state;
988
989 /* save the desired Activity LED behavior */
990 if (val == OFF) {
991 /* clear LFLAG */
992 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
993
994 /* set the LED to OFF */
995 port_led_state &= EM_MSG_LED_VALUE_OFF;
996 port_led_state |= (ap->port_no | (link->pmp << 8));
997 ahci_transmit_led_message(ap, port_led_state, 4);
998 } else {
999 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1000 if (val == BLINK_OFF) {
1001 /* set LED to ON for idle */
1002 port_led_state &= EM_MSG_LED_VALUE_OFF;
1003 port_led_state |= (ap->port_no | (link->pmp << 8));
1004 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1005 ahci_transmit_led_message(ap, port_led_state, 4);
1006 }
1007 }
1008 emp->blink_policy = val;
1009 return 0;
1010}
1011
1012static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1013{
1014 struct ata_link *link = dev->link;
1015 struct ata_port *ap = link->ap;
1016 struct ahci_port_priv *pp = ap->private_data;
1017 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1018
1019 /* display the saved value of activity behavior for this
1020 * disk.
1021 */
1022 return sprintf(buf, "%d\n", emp->blink_policy);
1023}
1024
1025static void ahci_port_init(struct device *dev, struct ata_port *ap,
1026 int port_no, void __iomem *mmio,
1027 void __iomem *port_mmio)
1028{
1029 const char *emsg = NULL;
1030 int rc;
1031 u32 tmp;
1032
1033 /* make sure port is not active */
1034 rc = ahci_deinit_port(ap, &emsg);
1035 if (rc)
1036 dev_warn(dev, "%s (%d)\n", emsg, rc);
1037
1038 /* clear SError */
1039 tmp = readl(port_mmio + PORT_SCR_ERR);
1040 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1041 writel(tmp, port_mmio + PORT_SCR_ERR);
1042
1043 /* clear port IRQ */
1044 tmp = readl(port_mmio + PORT_IRQ_STAT);
1045 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1046 if (tmp)
1047 writel(tmp, port_mmio + PORT_IRQ_STAT);
1048
1049 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1050}
1051
1052void ahci_init_controller(struct ata_host *host)
1053{
1054 struct ahci_host_priv *hpriv = host->private_data;
1055 void __iomem *mmio = hpriv->mmio;
1056 int i;
1057 void __iomem *port_mmio;
1058 u32 tmp;
1059
1060 for (i = 0; i < host->n_ports; i++) {
1061 struct ata_port *ap = host->ports[i];
1062
1063 port_mmio = ahci_port_base(ap);
1064 if (ata_port_is_dummy(ap))
1065 continue;
1066
1067 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1068 }
1069
1070 tmp = readl(mmio + HOST_CTL);
1071 VPRINTK("HOST_CTL 0x%x\n", tmp);
1072 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1073 tmp = readl(mmio + HOST_CTL);
1074 VPRINTK("HOST_CTL 0x%x\n", tmp);
1075}
1076EXPORT_SYMBOL_GPL(ahci_init_controller);
1077
1078static void ahci_dev_config(struct ata_device *dev)
1079{
1080 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1081
1082 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1083 dev->max_sectors = 255;
1084 ata_dev_printk(dev, KERN_INFO,
1085 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1086 }
1087}
1088
1089static unsigned int ahci_dev_classify(struct ata_port *ap)
1090{
1091 void __iomem *port_mmio = ahci_port_base(ap);
1092 struct ata_taskfile tf;
1093 u32 tmp;
1094
1095 tmp = readl(port_mmio + PORT_SIG);
1096 tf.lbah = (tmp >> 24) & 0xff;
1097 tf.lbam = (tmp >> 16) & 0xff;
1098 tf.lbal = (tmp >> 8) & 0xff;
1099 tf.nsect = (tmp) & 0xff;
1100
1101 return ata_dev_classify(&tf);
1102}
1103
1104static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1105 u32 opts)
1106{
1107 dma_addr_t cmd_tbl_dma;
1108
1109 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1110
1111 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1112 pp->cmd_slot[tag].status = 0;
1113 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1114 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1115}
1116
1117int ahci_kick_engine(struct ata_port *ap)
1118{
1119 void __iomem *port_mmio = ahci_port_base(ap);
1120 struct ahci_host_priv *hpriv = ap->host->private_data;
1121 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1122 u32 tmp;
1123 int busy, rc;
1124
1125 /* stop engine */
1126 rc = ahci_stop_engine(ap);
1127 if (rc)
1128 goto out_restart;
1129
1130 /* need to do CLO?
1131 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1132 */
1133 busy = status & (ATA_BUSY | ATA_DRQ);
1134 if (!busy && !sata_pmp_attached(ap)) {
1135 rc = 0;
1136 goto out_restart;
1137 }
1138
1139 if (!(hpriv->cap & HOST_CAP_CLO)) {
1140 rc = -EOPNOTSUPP;
1141 goto out_restart;
1142 }
1143
1144 /* perform CLO */
1145 tmp = readl(port_mmio + PORT_CMD);
1146 tmp |= PORT_CMD_CLO;
1147 writel(tmp, port_mmio + PORT_CMD);
1148
1149 rc = 0;
1150 tmp = ata_wait_register(port_mmio + PORT_CMD,
1151 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1152 if (tmp & PORT_CMD_CLO)
1153 rc = -EIO;
1154
1155 /* restart engine */
1156 out_restart:
1157 ahci_start_engine(ap);
1158 return rc;
1159}
1160EXPORT_SYMBOL_GPL(ahci_kick_engine);
1161
1162static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1163 struct ata_taskfile *tf, int is_cmd, u16 flags,
1164 unsigned long timeout_msec)
1165{
1166 const u32 cmd_fis_len = 5; /* five dwords */
1167 struct ahci_port_priv *pp = ap->private_data;
1168 void __iomem *port_mmio = ahci_port_base(ap);
1169 u8 *fis = pp->cmd_tbl;
1170 u32 tmp;
1171
1172 /* prep the command */
1173 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1174 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1175
1176 /* issue & wait */
1177 writel(1, port_mmio + PORT_CMD_ISSUE);
1178
1179 if (timeout_msec) {
1180 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1181 1, timeout_msec);
1182 if (tmp & 0x1) {
1183 ahci_kick_engine(ap);
1184 return -EBUSY;
1185 }
1186 } else
1187 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1188
1189 return 0;
1190}
1191
1192int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1193 int pmp, unsigned long deadline,
1194 int (*check_ready)(struct ata_link *link))
1195{
1196 struct ata_port *ap = link->ap;
1197 struct ahci_host_priv *hpriv = ap->host->private_data;
1198 const char *reason = NULL;
1199 unsigned long now, msecs;
1200 struct ata_taskfile tf;
1201 int rc;
1202
1203 DPRINTK("ENTER\n");
1204
1205 /* prepare for SRST (AHCI-1.1 10.4.1) */
1206 rc = ahci_kick_engine(ap);
1207 if (rc && rc != -EOPNOTSUPP)
1208 ata_link_printk(link, KERN_WARNING,
1209 "failed to reset engine (errno=%d)\n", rc);
1210
1211 ata_tf_init(link->device, &tf);
1212
1213 /* issue the first D2H Register FIS */
1214 msecs = 0;
1215 now = jiffies;
1216 if (time_after(now, deadline))
1217 msecs = jiffies_to_msecs(deadline - now);
1218
1219 tf.ctl |= ATA_SRST;
1220 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1221 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1222 rc = -EIO;
1223 reason = "1st FIS failed";
1224 goto fail;
1225 }
1226
1227 /* spec says at least 5us, but be generous and sleep for 1ms */
1228 msleep(1);
1229
1230 /* issue the second D2H Register FIS */
1231 tf.ctl &= ~ATA_SRST;
1232 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1233
1234 /* wait for link to become ready */
1235 rc = ata_wait_after_reset(link, deadline, check_ready);
1236 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1237 /*
1238 * Workaround for cases where link online status can't
1239 * be trusted. Treat device readiness timeout as link
1240 * offline.
1241 */
1242 ata_link_printk(link, KERN_INFO,
1243 "device not ready, treating as offline\n");
1244 *class = ATA_DEV_NONE;
1245 } else if (rc) {
1246 /* link occupied, -ENODEV too is an error */
1247 reason = "device not ready";
1248 goto fail;
1249 } else
1250 *class = ahci_dev_classify(ap);
1251
1252 DPRINTK("EXIT, class=%u\n", *class);
1253 return 0;
1254
1255 fail:
1256 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1257 return rc;
1258}
1259
1260int ahci_check_ready(struct ata_link *link)
1261{
1262 void __iomem *port_mmio = ahci_port_base(link->ap);
1263 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1264
1265 return ata_check_ready(status);
1266}
1267EXPORT_SYMBOL_GPL(ahci_check_ready);
1268
1269static int ahci_softreset(struct ata_link *link, unsigned int *class,
1270 unsigned long deadline)
1271{
1272 int pmp = sata_srst_pmp(link);
1273
1274 DPRINTK("ENTER\n");
1275
1276 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1277}
1278EXPORT_SYMBOL_GPL(ahci_do_softreset);
1279
1280static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1281 unsigned long deadline)
1282{
1283 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1284 struct ata_port *ap = link->ap;
1285 struct ahci_port_priv *pp = ap->private_data;
1286 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1287 struct ata_taskfile tf;
1288 bool online;
1289 int rc;
1290
1291 DPRINTK("ENTER\n");
1292
1293 ahci_stop_engine(ap);
1294
1295 /* clear D2H reception area to properly wait for D2H FIS */
1296 ata_tf_init(link->device, &tf);
1297 tf.command = 0x80;
1298 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1299
1300 rc = sata_link_hardreset(link, timing, deadline, &online,
1301 ahci_check_ready);
1302
1303 ahci_start_engine(ap);
1304
1305 if (online)
1306 *class = ahci_dev_classify(ap);
1307
1308 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1309 return rc;
1310}
1311
1312static void ahci_postreset(struct ata_link *link, unsigned int *class)
1313{
1314 struct ata_port *ap = link->ap;
1315 void __iomem *port_mmio = ahci_port_base(ap);
1316 u32 new_tmp, tmp;
1317
1318 ata_std_postreset(link, class);
1319
1320 /* Make sure port's ATAPI bit is set appropriately */
1321 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1322 if (*class == ATA_DEV_ATAPI)
1323 new_tmp |= PORT_CMD_ATAPI;
1324 else
1325 new_tmp &= ~PORT_CMD_ATAPI;
1326 if (new_tmp != tmp) {
1327 writel(new_tmp, port_mmio + PORT_CMD);
1328 readl(port_mmio + PORT_CMD); /* flush */
1329 }
1330}
1331
1332static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1333{
1334 struct scatterlist *sg;
1335 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1336 unsigned int si;
1337
1338 VPRINTK("ENTER\n");
1339
1340 /*
1341 * Next, the S/G list.
1342 */
1343 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1344 dma_addr_t addr = sg_dma_address(sg);
1345 u32 sg_len = sg_dma_len(sg);
1346
1347 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1348 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1349 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1350 }
1351
1352 return si;
1353}
1354
1355static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1356{
1357 struct ata_port *ap = qc->ap;
1358 struct ahci_port_priv *pp = ap->private_data;
1359
1360 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1361 return ata_std_qc_defer(qc);
1362 else
1363 return sata_pmp_qc_defer_cmd_switch(qc);
1364}
1365
1366static void ahci_qc_prep(struct ata_queued_cmd *qc)
1367{
1368 struct ata_port *ap = qc->ap;
1369 struct ahci_port_priv *pp = ap->private_data;
1370 int is_atapi = ata_is_atapi(qc->tf.protocol);
1371 void *cmd_tbl;
1372 u32 opts;
1373 const u32 cmd_fis_len = 5; /* five dwords */
1374 unsigned int n_elem;
1375
1376 /*
1377 * Fill in command table information. First, the header,
1378 * a SATA Register - Host to Device command FIS.
1379 */
1380 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1381
1382 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1383 if (is_atapi) {
1384 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1385 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1386 }
1387
1388 n_elem = 0;
1389 if (qc->flags & ATA_QCFLAG_DMAMAP)
1390 n_elem = ahci_fill_sg(qc, cmd_tbl);
1391
1392 /*
1393 * Fill in command slot information.
1394 */
1395 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1396 if (qc->tf.flags & ATA_TFLAG_WRITE)
1397 opts |= AHCI_CMD_WRITE;
1398 if (is_atapi)
1399 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1400
1401 ahci_fill_cmd_slot(pp, qc->tag, opts);
1402}
1403
1404static void ahci_fbs_dec_intr(struct ata_port *ap)
1405{
1406 struct ahci_port_priv *pp = ap->private_data;
1407 void __iomem *port_mmio = ahci_port_base(ap);
1408 u32 fbs = readl(port_mmio + PORT_FBS);
1409 int retries = 3;
1410
1411 DPRINTK("ENTER\n");
1412 BUG_ON(!pp->fbs_enabled);
1413
1414 /* time to wait for DEC is not specified by AHCI spec,
1415 * add a retry loop for safety.
1416 */
1417 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1418 fbs = readl(port_mmio + PORT_FBS);
1419 while ((fbs & PORT_FBS_DEC) && retries--) {
1420 udelay(1);
1421 fbs = readl(port_mmio + PORT_FBS);
1422 }
1423
1424 if (fbs & PORT_FBS_DEC)
1425 dev_printk(KERN_ERR, ap->host->dev,
1426 "failed to clear device error\n");
1427}
1428
1429static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1430{
1431 struct ahci_host_priv *hpriv = ap->host->private_data;
1432 struct ahci_port_priv *pp = ap->private_data;
1433 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1434 struct ata_link *link = NULL;
1435 struct ata_queued_cmd *active_qc;
1436 struct ata_eh_info *active_ehi;
1437 bool fbs_need_dec = false;
1438 u32 serror;
1439
1440 /* determine active link with error */
1441 if (pp->fbs_enabled) {
1442 void __iomem *port_mmio = ahci_port_base(ap);
1443 u32 fbs = readl(port_mmio + PORT_FBS);
1444 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1445
1446 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
1447 ata_link_online(&ap->pmp_link[pmp])) {
1448 link = &ap->pmp_link[pmp];
1449 fbs_need_dec = true;
1450 }
1451
1452 } else
1453 ata_for_each_link(link, ap, EDGE)
1454 if (ata_link_active(link))
1455 break;
1456
1457 if (!link)
1458 link = &ap->link;
1459
1460 active_qc = ata_qc_from_tag(ap, link->active_tag);
1461 active_ehi = &link->eh_info;
1462
1463 /* record irq stat */
1464 ata_ehi_clear_desc(host_ehi);
1465 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1466
1467 /* AHCI needs SError cleared; otherwise, it might lock up */
1468 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1469 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1470 host_ehi->serror |= serror;
1471
1472 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1473 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1474 irq_stat &= ~PORT_IRQ_IF_ERR;
1475
1476 if (irq_stat & PORT_IRQ_TF_ERR) {
1477 /* If qc is active, charge it; otherwise, the active
1478 * link. There's no active qc on NCQ errors. It will
1479 * be determined by EH by reading log page 10h.
1480 */
1481 if (active_qc)
1482 active_qc->err_mask |= AC_ERR_DEV;
1483 else
1484 active_ehi->err_mask |= AC_ERR_DEV;
1485
1486 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1487 host_ehi->serror &= ~SERR_INTERNAL;
1488 }
1489
1490 if (irq_stat & PORT_IRQ_UNK_FIS) {
1491 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1492
1493 active_ehi->err_mask |= AC_ERR_HSM;
1494 active_ehi->action |= ATA_EH_RESET;
1495 ata_ehi_push_desc(active_ehi,
1496 "unknown FIS %08x %08x %08x %08x" ,
1497 unk[0], unk[1], unk[2], unk[3]);
1498 }
1499
1500 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1501 active_ehi->err_mask |= AC_ERR_HSM;
1502 active_ehi->action |= ATA_EH_RESET;
1503 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1504 }
1505
1506 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1507 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1508 host_ehi->action |= ATA_EH_RESET;
1509 ata_ehi_push_desc(host_ehi, "host bus error");
1510 }
1511
1512 if (irq_stat & PORT_IRQ_IF_ERR) {
1513 if (fbs_need_dec)
1514 active_ehi->err_mask |= AC_ERR_DEV;
1515 else {
1516 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1517 host_ehi->action |= ATA_EH_RESET;
1518 }
1519
1520 ata_ehi_push_desc(host_ehi, "interface fatal error");
1521 }
1522
1523 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1524 ata_ehi_hotplugged(host_ehi);
1525 ata_ehi_push_desc(host_ehi, "%s",
1526 irq_stat & PORT_IRQ_CONNECT ?
1527 "connection status changed" : "PHY RDY changed");
1528 }
1529
1530 /* okay, let's hand over to EH */
1531
1532 if (irq_stat & PORT_IRQ_FREEZE)
1533 ata_port_freeze(ap);
1534 else if (fbs_need_dec) {
1535 ata_link_abort(link);
1536 ahci_fbs_dec_intr(ap);
1537 } else
1538 ata_port_abort(ap);
1539}
1540
1541static void ahci_port_intr(struct ata_port *ap)
1542{
1543 void __iomem *port_mmio = ahci_port_base(ap);
1544 struct ata_eh_info *ehi = &ap->link.eh_info;
1545 struct ahci_port_priv *pp = ap->private_data;
1546 struct ahci_host_priv *hpriv = ap->host->private_data;
1547 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1548 u32 status, qc_active = 0;
1549 int rc;
1550
1551 status = readl(port_mmio + PORT_IRQ_STAT);
1552 writel(status, port_mmio + PORT_IRQ_STAT);
1553
1554 /* ignore BAD_PMP while resetting */
1555 if (unlikely(resetting))
1556 status &= ~PORT_IRQ_BAD_PMP;
1557
1558 /* If we are getting PhyRdy, this is
1559 * just a power state change, we should
1560 * clear out this, plus the PhyRdy/Comm
1561 * Wake bits from Serror
1562 */
1563 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1564 (status & PORT_IRQ_PHYRDY)) {
1565 status &= ~PORT_IRQ_PHYRDY;
1566 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1567 }
1568
1569 if (unlikely(status & PORT_IRQ_ERROR)) {
1570 ahci_error_intr(ap, status);
1571 return;
1572 }
1573
1574 if (status & PORT_IRQ_SDB_FIS) {
1575 /* If SNotification is available, leave notification
1576 * handling to sata_async_notification(). If not,
1577 * emulate it by snooping SDB FIS RX area.
1578 *
1579 * Snooping FIS RX area is probably cheaper than
1580 * poking SNotification but some constrollers which
1581 * implement SNotification, ICH9 for example, don't
1582 * store AN SDB FIS into receive area.
1583 */
1584 if (hpriv->cap & HOST_CAP_SNTF)
1585 sata_async_notification(ap);
1586 else {
1587 /* If the 'N' bit in word 0 of the FIS is set,
1588 * we just received asynchronous notification.
1589 * Tell libata about it.
1590 *
1591 * Lack of SNotification should not appear in
1592 * ahci 1.2, so the workaround is unnecessary
1593 * when FBS is enabled.
1594 */
1595 if (pp->fbs_enabled)
1596 WARN_ON_ONCE(1);
1597 else {
1598 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1599 u32 f0 = le32_to_cpu(f[0]);
1600 if (f0 & (1 << 15))
1601 sata_async_notification(ap);
1602 }
1603 }
1604 }
1605
1606 /* pp->active_link is not reliable once FBS is enabled, both
1607 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1608 * NCQ and non-NCQ commands may be in flight at the same time.
1609 */
1610 if (pp->fbs_enabled) {
1611 if (ap->qc_active) {
1612 qc_active = readl(port_mmio + PORT_SCR_ACT);
1613 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1614 }
1615 } else {
1616 /* pp->active_link is valid iff any command is in flight */
1617 if (ap->qc_active && pp->active_link->sactive)
1618 qc_active = readl(port_mmio + PORT_SCR_ACT);
1619 else
1620 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1621 }
1622
1623
1624 rc = ata_qc_complete_multiple(ap, qc_active);
1625
1626 /* while resetting, invalid completions are expected */
1627 if (unlikely(rc < 0 && !resetting)) {
1628 ehi->err_mask |= AC_ERR_HSM;
1629 ehi->action |= ATA_EH_RESET;
1630 ata_port_freeze(ap);
1631 }
1632}
1633
1634irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1635{
1636 struct ata_host *host = dev_instance;
1637 struct ahci_host_priv *hpriv;
1638 unsigned int i, handled = 0;
1639 void __iomem *mmio;
1640 u32 irq_stat, irq_masked;
1641
1642 VPRINTK("ENTER\n");
1643
1644 hpriv = host->private_data;
1645 mmio = hpriv->mmio;
1646
1647 /* sigh. 0xffffffff is a valid return from h/w */
1648 irq_stat = readl(mmio + HOST_IRQ_STAT);
1649 if (!irq_stat)
1650 return IRQ_NONE;
1651
1652 irq_masked = irq_stat & hpriv->port_map;
1653
1654 spin_lock(&host->lock);
1655
1656 for (i = 0; i < host->n_ports; i++) {
1657 struct ata_port *ap;
1658
1659 if (!(irq_masked & (1 << i)))
1660 continue;
1661
1662 ap = host->ports[i];
1663 if (ap) {
1664 ahci_port_intr(ap);
1665 VPRINTK("port %u\n", i);
1666 } else {
1667 VPRINTK("port %u (no irq)\n", i);
1668 if (ata_ratelimit())
1669 dev_printk(KERN_WARNING, host->dev,
1670 "interrupt on disabled port %u\n", i);
1671 }
1672
1673 handled = 1;
1674 }
1675
1676 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1677 * it should be cleared after all the port events are cleared;
1678 * otherwise, it will raise a spurious interrupt after each
1679 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1680 * information.
1681 *
1682 * Also, use the unmasked value to clear interrupt as spurious
1683 * pending event on a dummy port might cause screaming IRQ.
1684 */
1685 writel(irq_stat, mmio + HOST_IRQ_STAT);
1686
1687 spin_unlock(&host->lock);
1688
1689 VPRINTK("EXIT\n");
1690
1691 return IRQ_RETVAL(handled);
1692}
1693EXPORT_SYMBOL_GPL(ahci_interrupt);
1694
1695static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1696{
1697 struct ata_port *ap = qc->ap;
1698 void __iomem *port_mmio = ahci_port_base(ap);
1699 struct ahci_port_priv *pp = ap->private_data;
1700
1701 /* Keep track of the currently active link. It will be used
1702 * in completion path to determine whether NCQ phase is in
1703 * progress.
1704 */
1705 pp->active_link = qc->dev->link;
1706
1707 if (qc->tf.protocol == ATA_PROT_NCQ)
1708 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1709
1710 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1711 u32 fbs = readl(port_mmio + PORT_FBS);
1712 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1713 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1714 writel(fbs, port_mmio + PORT_FBS);
1715 pp->fbs_last_dev = qc->dev->link->pmp;
1716 }
1717
1718 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1719
1720 ahci_sw_activity(qc->dev->link);
1721
1722 return 0;
1723}
1724
1725static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1726{
1727 struct ahci_port_priv *pp = qc->ap->private_data;
1728 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1729
1730 if (pp->fbs_enabled)
1731 d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1732
1733 ata_tf_from_fis(d2h_fis, &qc->result_tf);
1734 return true;
1735}
1736
1737static void ahci_freeze(struct ata_port *ap)
1738{
1739 void __iomem *port_mmio = ahci_port_base(ap);
1740
1741 /* turn IRQ off */
1742 writel(0, port_mmio + PORT_IRQ_MASK);
1743}
1744
1745static void ahci_thaw(struct ata_port *ap)
1746{
1747 struct ahci_host_priv *hpriv = ap->host->private_data;
1748 void __iomem *mmio = hpriv->mmio;
1749 void __iomem *port_mmio = ahci_port_base(ap);
1750 u32 tmp;
1751 struct ahci_port_priv *pp = ap->private_data;
1752
1753 /* clear IRQ */
1754 tmp = readl(port_mmio + PORT_IRQ_STAT);
1755 writel(tmp, port_mmio + PORT_IRQ_STAT);
1756 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1757
1758 /* turn IRQ back on */
1759 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1760}
1761
1762static void ahci_error_handler(struct ata_port *ap)
1763{
1764 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1765 /* restart engine */
1766 ahci_stop_engine(ap);
1767 ahci_start_engine(ap);
1768 }
1769
1770 sata_pmp_error_handler(ap);
1771}
1772
1773static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1774{
1775 struct ata_port *ap = qc->ap;
1776
1777 /* make DMA engine forget about the failed command */
1778 if (qc->flags & ATA_QCFLAG_FAILED)
1779 ahci_kick_engine(ap);
1780}
1781
1782static void ahci_enable_fbs(struct ata_port *ap)
1783{
1784 struct ahci_port_priv *pp = ap->private_data;
1785 void __iomem *port_mmio = ahci_port_base(ap);
1786 u32 fbs;
1787 int rc;
1788
1789 if (!pp->fbs_supported)
1790 return;
1791
1792 fbs = readl(port_mmio + PORT_FBS);
1793 if (fbs & PORT_FBS_EN) {
1794 pp->fbs_enabled = true;
1795 pp->fbs_last_dev = -1; /* initialization */
1796 return;
1797 }
1798
1799 rc = ahci_stop_engine(ap);
1800 if (rc)
1801 return;
1802
1803 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
1804 fbs = readl(port_mmio + PORT_FBS);
1805 if (fbs & PORT_FBS_EN) {
1806 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
1807 pp->fbs_enabled = true;
1808 pp->fbs_last_dev = -1; /* initialization */
1809 } else
1810 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
1811
1812 ahci_start_engine(ap);
1813}
1814
1815static void ahci_disable_fbs(struct ata_port *ap)
1816{
1817 struct ahci_port_priv *pp = ap->private_data;
1818 void __iomem *port_mmio = ahci_port_base(ap);
1819 u32 fbs;
1820 int rc;
1821
1822 if (!pp->fbs_supported)
1823 return;
1824
1825 fbs = readl(port_mmio + PORT_FBS);
1826 if ((fbs & PORT_FBS_EN) == 0) {
1827 pp->fbs_enabled = false;
1828 return;
1829 }
1830
1831 rc = ahci_stop_engine(ap);
1832 if (rc)
1833 return;
1834
1835 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
1836 fbs = readl(port_mmio + PORT_FBS);
1837 if (fbs & PORT_FBS_EN)
1838 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
1839 else {
1840 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
1841 pp->fbs_enabled = false;
1842 }
1843
1844 ahci_start_engine(ap);
1845}
1846
1847static void ahci_pmp_attach(struct ata_port *ap)
1848{
1849 void __iomem *port_mmio = ahci_port_base(ap);
1850 struct ahci_port_priv *pp = ap->private_data;
1851 u32 cmd;
1852
1853 cmd = readl(port_mmio + PORT_CMD);
1854 cmd |= PORT_CMD_PMP;
1855 writel(cmd, port_mmio + PORT_CMD);
1856
1857 ahci_enable_fbs(ap);
1858
1859 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1860 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1861}
1862
1863static void ahci_pmp_detach(struct ata_port *ap)
1864{
1865 void __iomem *port_mmio = ahci_port_base(ap);
1866 struct ahci_port_priv *pp = ap->private_data;
1867 u32 cmd;
1868
1869 ahci_disable_fbs(ap);
1870
1871 cmd = readl(port_mmio + PORT_CMD);
1872 cmd &= ~PORT_CMD_PMP;
1873 writel(cmd, port_mmio + PORT_CMD);
1874
1875 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1876 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1877}
1878
1879static int ahci_port_resume(struct ata_port *ap)
1880{
1881 ahci_power_up(ap);
1882 ahci_start_port(ap);
1883
1884 if (sata_pmp_attached(ap))
1885 ahci_pmp_attach(ap);
1886 else
1887 ahci_pmp_detach(ap);
1888
1889 return 0;
1890}
1891
1892#ifdef CONFIG_PM
1893static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1894{
1895 const char *emsg = NULL;
1896 int rc;
1897
1898 rc = ahci_deinit_port(ap, &emsg);
1899 if (rc == 0)
1900 ahci_power_down(ap);
1901 else {
1902 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1903 ahci_start_port(ap);
1904 }
1905
1906 return rc;
1907}
1908#endif
1909
1910static int ahci_port_start(struct ata_port *ap)
1911{
1912 struct ahci_host_priv *hpriv = ap->host->private_data;
1913 struct device *dev = ap->host->dev;
1914 struct ahci_port_priv *pp;
1915 void *mem;
1916 dma_addr_t mem_dma;
1917 size_t dma_sz, rx_fis_sz;
1918
1919 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1920 if (!pp)
1921 return -ENOMEM;
1922
1923 /* check FBS capability */
1924 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
1925 void __iomem *port_mmio = ahci_port_base(ap);
1926 u32 cmd = readl(port_mmio + PORT_CMD);
1927 if (cmd & PORT_CMD_FBSCP)
1928 pp->fbs_supported = true;
1929 else
1930 dev_printk(KERN_WARNING, dev,
1931 "The port is not capable of FBS\n");
1932 }
1933
1934 if (pp->fbs_supported) {
1935 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
1936 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
1937 } else {
1938 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
1939 rx_fis_sz = AHCI_RX_FIS_SZ;
1940 }
1941
1942 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
1943 if (!mem)
1944 return -ENOMEM;
1945 memset(mem, 0, dma_sz);
1946
1947 /*
1948 * First item in chunk of DMA memory: 32-slot command table,
1949 * 32 bytes each in size
1950 */
1951 pp->cmd_slot = mem;
1952 pp->cmd_slot_dma = mem_dma;
1953
1954 mem += AHCI_CMD_SLOT_SZ;
1955 mem_dma += AHCI_CMD_SLOT_SZ;
1956
1957 /*
1958 * Second item: Received-FIS area
1959 */
1960 pp->rx_fis = mem;
1961 pp->rx_fis_dma = mem_dma;
1962
1963 mem += rx_fis_sz;
1964 mem_dma += rx_fis_sz;
1965
1966 /*
1967 * Third item: data area for storing a single command
1968 * and its scatter-gather table
1969 */
1970 pp->cmd_tbl = mem;
1971 pp->cmd_tbl_dma = mem_dma;
1972
1973 /*
1974 * Save off initial list of interrupts to be enabled.
1975 * This could be changed later
1976 */
1977 pp->intr_mask = DEF_PORT_IRQ;
1978
1979 ap->private_data = pp;
1980
1981 /* engage engines, captain */
1982 return ahci_port_resume(ap);
1983}
1984
1985static void ahci_port_stop(struct ata_port *ap)
1986{
1987 const char *emsg = NULL;
1988 int rc;
1989
1990 /* de-initialize port */
1991 rc = ahci_deinit_port(ap, &emsg);
1992 if (rc)
1993 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1994}
1995
1996void ahci_print_info(struct ata_host *host, const char *scc_s)
1997{
1998 struct ahci_host_priv *hpriv = host->private_data;
1999 void __iomem *mmio = hpriv->mmio;
2000 u32 vers, cap, cap2, impl, speed;
2001 const char *speed_s;
2002
2003 vers = readl(mmio + HOST_VERSION);
2004 cap = hpriv->cap;
2005 cap2 = hpriv->cap2;
2006 impl = hpriv->port_map;
2007
2008 speed = (cap >> 20) & 0xf;
2009 if (speed == 1)
2010 speed_s = "1.5";
2011 else if (speed == 2)
2012 speed_s = "3";
2013 else if (speed == 3)
2014 speed_s = "6";
2015 else
2016 speed_s = "?";
2017
2018 dev_info(host->dev,
2019 "AHCI %02x%02x.%02x%02x "
2020 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2021 ,
2022
2023 (vers >> 24) & 0xff,
2024 (vers >> 16) & 0xff,
2025 (vers >> 8) & 0xff,
2026 vers & 0xff,
2027
2028 ((cap >> 8) & 0x1f) + 1,
2029 (cap & 0x1f) + 1,
2030 speed_s,
2031 impl,
2032 scc_s);
2033
2034 dev_info(host->dev,
2035 "flags: "
2036 "%s%s%s%s%s%s%s"
2037 "%s%s%s%s%s%s%s"
2038 "%s%s%s%s%s%s\n"
2039 ,
2040
2041 cap & HOST_CAP_64 ? "64bit " : "",
2042 cap & HOST_CAP_NCQ ? "ncq " : "",
2043 cap & HOST_CAP_SNTF ? "sntf " : "",
2044 cap & HOST_CAP_MPS ? "ilck " : "",
2045 cap & HOST_CAP_SSS ? "stag " : "",
2046 cap & HOST_CAP_ALPM ? "pm " : "",
2047 cap & HOST_CAP_LED ? "led " : "",
2048 cap & HOST_CAP_CLO ? "clo " : "",
2049 cap & HOST_CAP_ONLY ? "only " : "",
2050 cap & HOST_CAP_PMP ? "pmp " : "",
2051 cap & HOST_CAP_FBS ? "fbs " : "",
2052 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2053 cap & HOST_CAP_SSC ? "slum " : "",
2054 cap & HOST_CAP_PART ? "part " : "",
2055 cap & HOST_CAP_CCC ? "ccc " : "",
2056 cap & HOST_CAP_EMS ? "ems " : "",
2057 cap & HOST_CAP_SXS ? "sxs " : "",
2058 cap2 & HOST_CAP2_APST ? "apst " : "",
2059 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2060 cap2 & HOST_CAP2_BOH ? "boh " : ""
2061 );
2062}
2063EXPORT_SYMBOL_GPL(ahci_print_info);
2064
2065void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2066 struct ata_port_info *pi)
2067{
2068 u8 messages;
2069 void __iomem *mmio = hpriv->mmio;
2070 u32 em_loc = readl(mmio + HOST_EM_LOC);
2071 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2072
2073 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2074 return;
2075
2076 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2077
2078 /* we only support LED message type right now */
2079 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2080 /* store em_loc */
2081 hpriv->em_loc = ((em_loc >> 16) * 4);
2082 pi->flags |= ATA_FLAG_EM;
2083 if (!(em_ctl & EM_CTL_ALHD))
2084 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2085 }
2086}
2087EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2088
2089MODULE_AUTHOR("Jeff Garzik");
2090MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2091MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 02:43:11 -0400