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-rw-r--r--MAINTAINERS2
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c52
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c59
3 files changed, 28 insertions, 85 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index a92c994ba935..86f9bb60d084 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2080,7 +2080,7 @@ F: include/drm/
2080 2080
2081INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets) 2081INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets)
2082M: Chris Wilson <chris@chris-wilson.co.uk> 2082M: Chris Wilson <chris@chris-wilson.co.uk>
2083L: intel-gfx@lists.freedesktop.org 2083L: intel-gfx@lists.freedesktop.org (subscribers-only)
2084L: dri-devel@lists.freedesktop.org 2084L: dri-devel@lists.freedesktop.org
2085T: git git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel.git 2085T: git git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel.git
2086S: Supported 2086S: Supported
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d9d81f94a4b8..a090acdf3bd5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -35,8 +35,7 @@
35#include <linux/swap.h> 35#include <linux/swap.h>
36#include <linux/pci.h> 36#include <linux/pci.h>
37 37
38static int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj, 38static void i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
39 struct intel_ring_buffer *pipelined);
40static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); 39static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); 40static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
42static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, 41static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
@@ -2552,10 +2551,7 @@ i915_gem_object_put_fence_reg(struct drm_i915_gem_object *obj,
2552 * before clearing the fence. 2551 * before clearing the fence.
2553 */ 2552 */
2554 if (obj->fenced_gpu_access) { 2553 if (obj->fenced_gpu_access) {
2555 ret = i915_gem_object_flush_gpu_write_domain(obj, NULL); 2554 i915_gem_object_flush_gpu_write_domain(obj);
2556 if (ret)
2557 return ret;
2558
2559 obj->fenced_gpu_access = false; 2555 obj->fenced_gpu_access = false;
2560 } 2556 }
2561 2557
@@ -2735,23 +2731,17 @@ i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2735} 2731}
2736 2732
2737/** Flushes any GPU write domain for the object if it's dirty. */ 2733/** Flushes any GPU write domain for the object if it's dirty. */
2738static int 2734static void
2739i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj, 2735i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2740 struct intel_ring_buffer *pipelined)
2741{ 2736{
2742 struct drm_device *dev = obj->base.dev; 2737 struct drm_device *dev = obj->base.dev;
2743 2738
2744 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) 2739 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2745 return 0; 2740 return;
2746 2741
2747 /* Queue the GPU write cache flushing we need. */ 2742 /* Queue the GPU write cache flushing we need. */
2748 i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain); 2743 i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain);
2749 BUG_ON(obj->base.write_domain); 2744 BUG_ON(obj->base.write_domain);
2750
2751 if (pipelined && pipelined == obj->ring)
2752 return 0;
2753
2754 return i915_gem_object_wait_rendering(obj, true);
2755} 2745}
2756 2746
2757/** Flushes the GTT write domain for the object if it's dirty. */ 2747/** Flushes the GTT write domain for the object if it's dirty. */
@@ -2812,18 +2802,13 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2812 if (obj->gtt_space == NULL) 2802 if (obj->gtt_space == NULL)
2813 return -EINVAL; 2803 return -EINVAL;
2814 2804
2815 ret = i915_gem_object_flush_gpu_write_domain(obj, NULL); 2805 i915_gem_object_flush_gpu_write_domain(obj);
2816 if (ret != 0) 2806 ret = i915_gem_object_wait_rendering(obj, true);
2807 if (ret)
2817 return ret; 2808 return ret;
2818 2809
2819 i915_gem_object_flush_cpu_write_domain(obj); 2810 i915_gem_object_flush_cpu_write_domain(obj);
2820 2811
2821 if (write) {
2822 ret = i915_gem_object_wait_rendering(obj, true);
2823 if (ret)
2824 return ret;
2825 }
2826
2827 old_write_domain = obj->base.write_domain; 2812 old_write_domain = obj->base.write_domain;
2828 old_read_domains = obj->base.read_domains; 2813 old_read_domains = obj->base.read_domains;
2829 2814
@@ -2860,9 +2845,7 @@ i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
2860 if (obj->gtt_space == NULL) 2845 if (obj->gtt_space == NULL)
2861 return -EINVAL; 2846 return -EINVAL;
2862 2847
2863 ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined); 2848 i915_gem_object_flush_gpu_write_domain(obj);
2864 if (ret)
2865 return ret;
2866 2849
2867 /* Currently, we are always called from an non-interruptible context. */ 2850 /* Currently, we are always called from an non-interruptible context. */
2868 if (!pipelined) { 2851 if (!pipelined) {
@@ -2909,8 +2892,9 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2909 uint32_t old_write_domain, old_read_domains; 2892 uint32_t old_write_domain, old_read_domains;
2910 int ret; 2893 int ret;
2911 2894
2912 ret = i915_gem_object_flush_gpu_write_domain(obj, false); 2895 i915_gem_object_flush_gpu_write_domain(obj);
2913 if (ret != 0) 2896 ret = i915_gem_object_wait_rendering(obj, true);
2897 if (ret)
2914 return ret; 2898 return ret;
2915 2899
2916 i915_gem_object_flush_gtt_write_domain(obj); 2900 i915_gem_object_flush_gtt_write_domain(obj);
@@ -2920,12 +2904,6 @@ i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2920 */ 2904 */
2921 i915_gem_object_set_to_full_cpu_read_domain(obj); 2905 i915_gem_object_set_to_full_cpu_read_domain(obj);
2922 2906
2923 if (write) {
2924 ret = i915_gem_object_wait_rendering(obj, true);
2925 if (ret)
2926 return ret;
2927 }
2928
2929 old_write_domain = obj->base.write_domain; 2907 old_write_domain = obj->base.write_domain;
2930 old_read_domains = obj->base.read_domains; 2908 old_read_domains = obj->base.read_domains;
2931 2909
@@ -3009,9 +2987,11 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
3009 if (offset == 0 && size == obj->base.size) 2987 if (offset == 0 && size == obj->base.size)
3010 return i915_gem_object_set_to_cpu_domain(obj, 0); 2988 return i915_gem_object_set_to_cpu_domain(obj, 0);
3011 2989
3012 ret = i915_gem_object_flush_gpu_write_domain(obj, false); 2990 i915_gem_object_flush_gpu_write_domain(obj);
3013 if (ret != 0) 2991 ret = i915_gem_object_wait_rendering(obj, true);
2992 if (ret)
3014 return ret; 2993 return ret;
2994
3015 i915_gem_object_flush_gtt_write_domain(obj); 2995 i915_gem_object_flush_gtt_write_domain(obj);
3016 2996
3017 /* If we're already fully in the CPU read domain, we're done. */ 2997 /* If we're already fully in the CPU read domain, we're done. */
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 843182528b79..d97e6cb52d34 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1296,55 +1296,14 @@ intel_sdvo_get_edid(struct drm_connector *connector)
1296 return drm_get_edid(connector, &sdvo->ddc); 1296 return drm_get_edid(connector, &sdvo->ddc);
1297} 1297}
1298 1298
1299static struct drm_connector *
1300intel_find_analog_connector(struct drm_device *dev)
1301{
1302 struct drm_connector *connector;
1303 struct intel_sdvo *encoder;
1304
1305 list_for_each_entry(encoder,
1306 &dev->mode_config.encoder_list,
1307 base.base.head) {
1308 if (encoder->base.type == INTEL_OUTPUT_ANALOG) {
1309 list_for_each_entry(connector,
1310 &dev->mode_config.connector_list,
1311 head) {
1312 if (&encoder->base ==
1313 intel_attached_encoder(connector))
1314 return connector;
1315 }
1316 }
1317 }
1318
1319 return NULL;
1320}
1321
1322static int
1323intel_analog_is_connected(struct drm_device *dev)
1324{
1325 struct drm_connector *analog_connector;
1326
1327 analog_connector = intel_find_analog_connector(dev);
1328 if (!analog_connector)
1329 return false;
1330
1331 if (analog_connector->funcs->detect(analog_connector, false) ==
1332 connector_status_disconnected)
1333 return false;
1334
1335 return true;
1336}
1337
1338/* Mac mini hack -- use the same DDC as the analog connector */ 1299/* Mac mini hack -- use the same DDC as the analog connector */
1339static struct edid * 1300static struct edid *
1340intel_sdvo_get_analog_edid(struct drm_connector *connector) 1301intel_sdvo_get_analog_edid(struct drm_connector *connector)
1341{ 1302{
1342 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1303 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1343 1304
1344 if (!intel_analog_is_connected(connector->dev)) 1305 return drm_get_edid(connector,
1345 return NULL; 1306 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
1346
1347 return drm_get_edid(connector, &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
1348} 1307}
1349 1308
1350enum drm_connector_status 1309enum drm_connector_status
@@ -1418,10 +1377,12 @@ intel_sdvo_detect(struct drm_connector *connector, bool force)
1418 if (!intel_sdvo_write_cmd(intel_sdvo, 1377 if (!intel_sdvo_write_cmd(intel_sdvo,
1419 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0)) 1378 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1420 return connector_status_unknown; 1379 return connector_status_unknown;
1421 if (intel_sdvo->is_tv) { 1380
1422 /* add 30ms delay when the output type is SDVO-TV */ 1381 /* add 30ms delay when the output type might be TV */
1382 if (intel_sdvo->caps.output_flags &
1383 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
1423 mdelay(30); 1384 mdelay(30);
1424 } 1385
1425 if (!intel_sdvo_read_response(intel_sdvo, &response, 2)) 1386 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1426 return connector_status_unknown; 1387 return connector_status_unknown;
1427 1388
@@ -1475,8 +1436,10 @@ static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1475 edid = intel_sdvo_get_analog_edid(connector); 1436 edid = intel_sdvo_get_analog_edid(connector);
1476 1437
1477 if (edid != NULL) { 1438 if (edid != NULL) {
1478 drm_mode_connector_update_edid_property(connector, edid); 1439 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1479 drm_add_edid_modes(connector, edid); 1440 drm_mode_connector_update_edid_property(connector, edid);
1441 drm_add_edid_modes(connector, edid);
1442 }
1480 connector->display_info.raw_edid = NULL; 1443 connector->display_info.raw_edid = NULL;
1481 kfree(edid); 1444 kfree(edid);
1482 } 1445 }