1 files changed, 168 insertions, 0 deletions
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index b6ad76ff6421..262a46fef5b7 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -51,6 +51,21 @@ static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
        return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
 }
+static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
+}
+static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
+}
+static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
+}
 static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 {
        return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
@@ -61,6 +76,11 @@ static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
        return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
 }
+static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
+}
 static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
 {
        return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
@@ -739,6 +759,154 @@ static struct clksrc_clk clksrcs[] = {
                .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
        }, {
                .clk            = {
+                        .name           = "sclk_csis",
+                        .id             = 0,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_csis",
+                        .id             = 1,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 28),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_cam",
+                        .id             = 0,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_cam",
+                        .id             = 1,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 20),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimc",
+                        .id             = 0,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimc",
+                        .id             = 1,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 4),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimc",
+                        .id             = 2,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 8),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimc",
+                        .id             = 3,
+                        .enable         = s5pv310_clksrc_mask_cam_ctrl,
+                        .ctrlbit        = (1 << 12),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimd",
+                        .id             = 0,
+                        .enable         = s5pv310_clksrc_mask_lcd0_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimd",
+                        .id             = 1,
+                        .enable         = s5pv310_clksrc_mask_lcd1_ctrl,
+                        .ctrlbit        = (1 << 0),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_sata",
+                        .id             = -1,
+                        .enable         = s5pv310_clksrc_mask_fsys_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &clkset_mout_corebus,
+                .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
+                .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_spi",
+                        .id             = 0,
+                        .enable         = s5pv310_clksrc_mask_peril1_ctrl,
+                        .ctrlbit        = (1 << 16),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_spi",
+                        .id             = 1,
+                        .enable         = s5pv310_clksrc_mask_peril1_ctrl,
+                        .ctrlbit        = (1 << 20),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_spi",
+                        .id             = 2,
+                        .enable         = s5pv310_clksrc_mask_peril1_ctrl,
+                        .ctrlbit        = (1 << 24),
+                },
+                .sources = &clkset_group,
+                .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+                .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
+                        .name           = "sclk_fimg2d",
+                        .id             = -1,
+                },
+                .sources = &clkset_mout_g2d,
+                .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
+                .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
+        }, {
+                .clk            = {
                        .name           = "sclk_mmc",
                        .id             = 0,
                        .parent         = &clk_dout_mmc0.clk,

diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c index b6ad76ff6421..262a46fef5b7 100644 --- a/arch/arm/mach-s5pv310/clock.c +++ b/arch/arm/mach-s5pv310/clock.c
@@ -51,6 +51,21 @@ static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
51	return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);	51	return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
52	}	52	}
53		53
		54	static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
		55	{
		56	return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
		57	}
		58
		59	static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
		60	{
		61	return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
		62	}
		63
		64	static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
		65	{
		66	return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
		67	}
		68
54	static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)	69	static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
55	{	70	{
56	return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);	71	return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
@@ -61,6 +76,11 @@ static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
61	return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);	76	return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
62	}	77	}
63		78
		79	static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
		80	{
		81	return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
		82	}
		83
64	static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)	84	static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
65	{	85	{
66	return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);	86	return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
@@ -739,6 +759,154 @@ static struct clksrc_clk clksrcs[] = {
739	.reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },	759	.reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
740	}, {	760	}, {
741	.clk = {	761	.clk = {
		762	.name = "sclk_csis",
		763	.id = 0,
		764	.enable = s5pv310_clksrc_mask_cam_ctrl,
		765	.ctrlbit = (1 << 24),
		766	},
		767	.sources = &clkset_group,
		768	.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
		769	.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
		770	}, {
		771	.clk = {
		772	.name = "sclk_csis",
		773	.id = 1,
		774	.enable = s5pv310_clksrc_mask_cam_ctrl,
		775	.ctrlbit = (1 << 28),
		776	},
		777	.sources = &clkset_group,
		778	.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
		779	.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
		780	}, {
		781	.clk = {
		782	.name = "sclk_cam",
		783	.id = 0,
		784	.enable = s5pv310_clksrc_mask_cam_ctrl,
		785	.ctrlbit = (1 << 16),
		786	},
		787	.sources = &clkset_group,
		788	.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
		789	.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
		790	}, {
		791	.clk = {
		792	.name = "sclk_cam",
		793	.id = 1,
		794	.enable = s5pv310_clksrc_mask_cam_ctrl,
		795	.ctrlbit = (1 << 20),
		796	},
		797	.sources = &clkset_group,
		798	.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
		799	.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
		800	}, {
		801	.clk = {
		802	.name = "sclk_fimc",
		803	.id = 0,
		804	.enable = s5pv310_clksrc_mask_cam_ctrl,
		805	.ctrlbit = (1 << 0),
		806	},
		807	.sources = &clkset_group,
		808	.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
		809	.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
		810	}, {
		811	.clk = {
		812	.name = "sclk_fimc",
		813	.id = 1,
		814	.enable = s5pv310_clksrc_mask_cam_ctrl,
		815	.ctrlbit = (1 << 4),
		816	},
		817	.sources = &clkset_group,
		818	.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
		819	.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
		820	}, {
		821	.clk = {
		822	.name = "sclk_fimc",
		823	.id = 2,
		824	.enable = s5pv310_clksrc_mask_cam_ctrl,
		825	.ctrlbit = (1 << 8),
		826	},
		827	.sources = &clkset_group,
		828	.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
		829	.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
		830	}, {
		831	.clk = {
		832	.name = "sclk_fimc",
		833	.id = 3,
		834	.enable = s5pv310_clksrc_mask_cam_ctrl,
		835	.ctrlbit = (1 << 12),
		836	},
		837	.sources = &clkset_group,
		838	.reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
		839	.reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
		840	}, {
		841	.clk = {
		842	.name = "sclk_fimd",
		843	.id = 0,
		844	.enable = s5pv310_clksrc_mask_lcd0_ctrl,
		845	.ctrlbit = (1 << 0),
		846	},
		847	.sources = &clkset_group,
		848	.reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
		849	.reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
		850	}, {
		851	.clk = {
		852	.name = "sclk_fimd",
		853	.id = 1,
		854	.enable = s5pv310_clksrc_mask_lcd1_ctrl,
		855	.ctrlbit = (1 << 0),
		856	},
		857	.sources = &clkset_group,
		858	.reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
		859	.reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
		860	}, {
		861	.clk = {
		862	.name = "sclk_sata",
		863	.id = -1,
		864	.enable = s5pv310_clksrc_mask_fsys_ctrl,
		865	.ctrlbit = (1 << 24),
		866	},
		867	.sources = &clkset_mout_corebus,
		868	.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
		869	.reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
		870	}, {
		871	.clk = {
		872	.name = "sclk_spi",
		873	.id = 0,
		874	.enable = s5pv310_clksrc_mask_peril1_ctrl,
		875	.ctrlbit = (1 << 16),
		876	},
		877	.sources = &clkset_group,
		878	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
		879	.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
		880	}, {
		881	.clk = {
		882	.name = "sclk_spi",
		883	.id = 1,
		884	.enable = s5pv310_clksrc_mask_peril1_ctrl,
		885	.ctrlbit = (1 << 20),
		886	},
		887	.sources = &clkset_group,
		888	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
		889	.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
		890	}, {
		891	.clk = {
		892	.name = "sclk_spi",
		893	.id = 2,
		894	.enable = s5pv310_clksrc_mask_peril1_ctrl,
		895	.ctrlbit = (1 << 24),
		896	},
		897	.sources = &clkset_group,
		898	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
		899	.reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
		900	}, {
		901	.clk = {
		902	.name = "sclk_fimg2d",
		903	.id = -1,
		904	},
		905	.sources = &clkset_mout_g2d,
		906	.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
		907	.reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
		908	}, {
		909	.clk = {
742	.name = "sclk_mmc",	910	.name = "sclk_mmc",
743	.id = 0,	911	.id = 0,
744	.parent = &clk_dout_mmc0.clk,	912	.parent = &clk_dout_mmc0.clk,