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-rw-r--r--arch/arm/mach-imx/clk-imx6q.c18
-rw-r--r--arch/arm/mach-imx/clk-pllv3.c9
-rw-r--r--arch/arm/mach-imx/clk.h3
3 files changed, 13 insertions, 17 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index d8049d3f9801..448476958e7f 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -198,15 +198,15 @@ int __init mx6q_clocks_init(void)
198 base = of_iomap(np, 0); 198 base = of_iomap(np, 0);
199 WARN_ON(!base); 199 WARN_ON(!base);
200 200
201 /* type name parent_name base gate_mask div_mask */ 201 /* type name parent_name base div_mask */
202 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x2000, 0x7f); 202 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
203 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x2000, 0x1); 203 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
204 clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x2000, 0x3); 204 clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
205 clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x2000, 0x7f); 205 clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
206 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x2000, 0x7f); 206 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
207 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x2000, 0x3); 207 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
208 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3); 208 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
209 clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x2000, 0x0); 209 clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
210 210
211 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6); 211 clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
212 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6); 212 clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index 59e74339ab08..d09bc3df9a7a 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -31,7 +31,6 @@
31 * @clk_hw: clock source 31 * @clk_hw: clock source
32 * @base: base address of PLL registers 32 * @base: base address of PLL registers
33 * @powerup_set: set POWER bit to power up the PLL 33 * @powerup_set: set POWER bit to power up the PLL
34 * @gate_mask: mask of gate bits
35 * @div_mask: mask of divider bits 34 * @div_mask: mask of divider bits
36 * 35 *
37 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3 36 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
@@ -41,7 +40,6 @@ struct clk_pllv3 {
41 struct clk_hw hw; 40 struct clk_hw hw;
42 void __iomem *base; 41 void __iomem *base;
43 bool powerup_set; 42 bool powerup_set;
44 u32 gate_mask;
45 u32 div_mask; 43 u32 div_mask;
46}; 44};
47 45
@@ -89,7 +87,7 @@ static int clk_pllv3_enable(struct clk_hw *hw)
89 u32 val; 87 u32 val;
90 88
91 val = readl_relaxed(pll->base); 89 val = readl_relaxed(pll->base);
92 val |= pll->gate_mask; 90 val |= BM_PLL_ENABLE;
93 writel_relaxed(val, pll->base); 91 writel_relaxed(val, pll->base);
94 92
95 return 0; 93 return 0;
@@ -101,7 +99,7 @@ static void clk_pllv3_disable(struct clk_hw *hw)
101 u32 val; 99 u32 val;
102 100
103 val = readl_relaxed(pll->base); 101 val = readl_relaxed(pll->base);
104 val &= ~pll->gate_mask; 102 val &= ~BM_PLL_ENABLE;
105 writel_relaxed(val, pll->base); 103 writel_relaxed(val, pll->base);
106} 104}
107 105
@@ -307,7 +305,7 @@ static const struct clk_ops clk_pllv3_mlb_ops = {
307 305
308struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 306struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
309 const char *parent_name, void __iomem *base, 307 const char *parent_name, void __iomem *base,
310 u32 gate_mask, u32 div_mask) 308 u32 div_mask)
311{ 309{
312 struct clk_pllv3 *pll; 310 struct clk_pllv3 *pll;
313 const struct clk_ops *ops; 311 const struct clk_ops *ops;
@@ -339,7 +337,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
339 ops = &clk_pllv3_ops; 337 ops = &clk_pllv3_ops;
340 } 338 }
341 pll->base = base; 339 pll->base = base;
342 pll->gate_mask = gate_mask;
343 pll->div_mask = div_mask; 340 pll->div_mask = div_mask;
344 341
345 init.name = name; 342 init.name = name;
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 5f2d8acca25f..9d1f3b99d1d3 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -22,8 +22,7 @@ enum imx_pllv3_type {
22}; 22};
23 23
24struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 24struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
25 const char *parent_name, void __iomem *base, u32 gate_mask, 25 const char *parent_name, void __iomem *base, u32 div_mask);
26 u32 div_mask);
27 26
28struct clk *clk_register_gate2(struct device *dev, const char *name, 27struct clk *clk_register_gate2(struct device *dev, const char *name,
29 const char *parent_name, unsigned long flags, 28 const char *parent_name, unsigned long flags,