116 files changed, 6069 insertions, 4804 deletions
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 4d175c751246..a57c1f216b21 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -35,6 +35,7 @@ parameter is applicable:
        APIC    APIC support is enabled.
        APM     Advanced Power Management support is enabled.
        AX25    Appropriate AX.25 support is enabled.
+        BLACKFIN Blackfin architecture is enabled.
        DRM     Direct Rendering Management support is enabled.
        EDD     BIOS Enhanced Disk Drive Services (EDD) is enabled
        EFI     EFI Partitioning (GPT) is enabled
@@ -550,7 +551,7 @@ and is between 256 and 4096 characters. It is defined in the file
        dtc3181e=       [HW,SCSI]
-        earlyprintk=    [X86-32,X86-64,SH]
+        earlyprintk=    [X86-32,X86-64,SH,BLACKFIN]
                        earlyprintk=vga
                        earlyprintk=serial[,ttySn[,baudrate]]
diff --git a/MAINTAINERS b/MAINTAINERS
index 0df29ce05e5a..22497de381da 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -718,34 +718,8 @@ M:	rpurdie@rpsys.net
 S:      Maintained
 BLACKFIN ARCHITECTURE
-P:      Aubrey Li
-M:      aubrey.li@analog.com
-P:      Bernd Schmidt
-M:      bernd.schmidt@analog.com
 P:      Bryan Wu
 M:      bryan.wu@analog.com
-P:      Grace Pan
-M:      grace.pan@analog.com
-P:      Marc Hoffman
-M:      marc.hoffman@analog.com
-P:      Michael Hennerich
-M:      michael.hennerich@analog.com
-P:      Mike Frysinger
-M:      michael.frysinger@analog.com
-P:      Jerry Zeng
-M:      jerry.zeng@analog.com
-P:      Jie Zhang
-M:      jie.zhang@analog.com
-P:      Robin Getz
-M:      robin.getz@analog.com
-P:      Roy Huang
-M:      roy.huang@analog.com
-P:      Sonic Zhang
-M:      sonic.zhang@analog.com
-P:      Vivi Li
-M:      vivi.li@analog.com
-P:      Yi Li
-M:      yi.li@analog.com
 L:      uclinux-dist-devel@blackfin.uclinux.org (subscribers-only)
 W:      http://blackfin.uclinux.org
 S:      Supported
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 017defaa525b..b24f4535ffe0 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -57,7 +57,7 @@ config GENERIC_TIME
        bool
        default n
-config GENERIC_CALIBRATE_DELAY
+config GENERIC_GPIO
        bool
        default y
@@ -323,7 +323,7 @@ config CMDLINE
          to the kernel, you may specify one here. As a minimum, you should specify
          the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
-comment "Board Setup"
+comment "Clock/PLL Setup"
 config CLKIN_HZ
        int "Crystal Frequency in Hz"
@@ -335,6 +335,118 @@ config CLKIN_HZ
        help
          The frequency of CLKIN crystal oscillator on the board in Hz.
+config BFIN_KERNEL_CLOCK
+        bool "Re-program Clocks while Kernel boots?"
+        default n
+        help
+          This option decides if kernel clocks are re-programed from the
+          bootloader settings. If the clocks are not set, the SDRAM settings
+          are also not changed, and the Bootloader does 100% of the hardware
+          configuration.
+config PLL_BYPASS
+        bool "Bypass PLL"
+        depends on BFIN_KERNEL_CLOCK
+        default n
+config CLKIN_HALF
+        bool "Half Clock In"
+        depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
+        default n
+        help
+          If this is set the clock will be divided by 2, before it goes to the PLL.
+config VCO_MULT
+        int "VCO Multiplier"
+        depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
+        range 1 64
+        default "22" if BFIN533_EZKIT
+        default "45" if BFIN533_STAMP
+        default "20" if BFIN537_STAMP
+        default "22" if BFIN533_BLUETECHNIX_CM
+        default "20" if BFIN537_BLUETECHNIX_CM
+        default "20" if BFIN561_BLUETECHNIX_CM
+        default "20" if BFIN561_EZKIT
+        help
+          This controls the frequency of the on-chip PLL. This can be between 1 and 64.
+          PLL Frequency = (Crystal Frequency) * (this setting)
+choice
+        prompt "Core Clock Divider"
+        depends on BFIN_KERNEL_CLOCK
+        default CCLK_DIV_1
+        help
+          This sets the frequency of the core. It can be 1, 2, 4 or 8
+          Core Frequency = (PLL frequency) / (this setting)
+config CCLK_DIV_1
+        bool "1"
+config CCLK_DIV_2
+        bool "2"
+config CCLK_DIV_4
+        bool "4"
+config CCLK_DIV_8
+        bool "8"
+endchoice
+config SCLK_DIV
+        int "System Clock Divider"
+        depends on BFIN_KERNEL_CLOCK
+        range 1 15
+        default 5 if BFIN533_EZKIT
+        default 5 if BFIN533_STAMP
+        default 4 if BFIN537_STAMP
+        default 5 if BFIN533_BLUETECHNIX_CM
+        default 4 if BFIN537_BLUETECHNIX_CM
+        default 4 if BFIN561_BLUETECHNIX_CM
+        default 5 if BFIN561_EZKIT
+        help
+          This sets the frequency of the system clock (including SDRAM or DDR).
+          This can be between 1 and 15
+          System Clock = (PLL frequency) / (this setting)
+#
+# Max & Min Speeds for various Chips
+#
+config MAX_VCO_HZ
+        int
+        default 600000000 if BF522
+        default 600000000 if BF525
+        default 600000000 if BF527
+        default 400000000 if BF531
+        default 400000000 if BF532
+        default 750000000 if BF533
+        default 500000000 if BF534
+        default 400000000 if BF536
+        default 600000000 if BF537
+        default 533000000 if BF538
+        default 533000000 if BF539
+        default 600000000 if BF542
+        default 533000000 if BF544
+        default 533000000 if BF549
+        default 600000000 if BF561
+config MIN_VCO_HZ
+        int
+        default 50000000
+config MAX_SCLK_HZ
+        int
+        default 133000000
+config MIN_SCLK_HZ
+        int
+        default 27000000
+comment "Kernel Timer/Scheduler"
+source kernel/Kconfig.hz
+comment "Memory Setup"
 config MEM_SIZE
        int "SDRAM Memory Size in MBytes"
        default  32 if BFIN533_EZKIT
@@ -364,15 +476,16 @@ config ENET_FLASH_PIN
 config BOOT_LOAD
        hex "Kernel load address for booting"
        default "0x1000"
+        range 0x1000 0x20000000
        help
          This option allows you to set the load address of the kernel.
          This can be useful if you are on a board which has a small amount
          of memory or you wish to reserve some memory at the beginning of
          the address space.
-          Note that you generally want to keep this value at or above 4k
+          Note that you need to keep this value above 4k (0x1000) as this
-          (0x1000) as this will allow the kernel to capture NULL pointer
+          memory region is used to capture NULL pointer references as well
-          references.
+          as some core kernel functions.
 comment "LED Status Indicators"
        depends on (BFIN533_STAMP || BFIN533_BLUETECHNIX_CM)
@@ -408,6 +521,52 @@ config BFIN_IDLE_LED_NUM
        help
          Select the LED (marked on the board) for you to blink.
+choice
+        prompt "Blackfin Exception Scratch Register"
+        default BFIN_SCRATCH_REG_RETN
+        help
+          Select the resource to reserve for the Exception handler:
+            - RETN: Non-Maskable Interrupt (NMI)
+            - RETE: Exception Return (JTAG/ICE)
+            - CYCLES: Performance counter
+          If you are unsure, please select "RETN".
+config BFIN_SCRATCH_REG_RETN
+        bool "RETN"
+        help
+          Use the RETN register in the Blackfin exception handler
+          as a stack scratch register.  This means you cannot
+          safely use NMI on the Blackfin while running Linux, but
+          you can debug the system with a JTAG ICE and use the
+          CYCLES performance registers.
+          If you are unsure, please select "RETN".
+config BFIN_SCRATCH_REG_RETE
+        bool "RETE"
+        help
+          Use the RETE register in the Blackfin exception handler
+          as a stack scratch register.  This means you cannot
+          safely use a JTAG ICE while debugging a Blackfin board,
+          but you can safely use the CYCLES performance registers
+          and the NMI.
+          If you are unsure, please select "RETN".
+config BFIN_SCRATCH_REG_CYCLES
+        bool "CYCLES"
+        help
+          Use the CYCLES register in the Blackfin exception handler
+          as a stack scratch register.  This means you cannot
+          safely use the CYCLES performance registers on a Blackfin
+          board at anytime, but you can debug the system with a JTAG
+          ICE and use the NMI.
+          If you are unsure, please select "RETN".
+endchoice
 #
 # Sorry - but you need to put the hex address here -
 #
@@ -448,10 +607,6 @@ endmenu
 menu "Blackfin Kernel Optimizations"
-comment "Timer Tick"
-source kernel/Kconfig.hz
 comment "Memory Optimizations"
 config I_ENTRY_L1
@@ -614,22 +769,22 @@ endchoice
 comment "Cache Support"
-config BLKFIN_CACHE
+config BFIN_ICACHE
        bool "Enable ICACHE"
-config BLKFIN_DCACHE
+config BFIN_DCACHE
        bool "Enable DCACHE"
-config BLKFIN_DCACHE_BANKA
+config BFIN_DCACHE_BANKA
        bool "Enable only 16k BankA DCACHE - BankB is SRAM"
-        depends on BLKFIN_DCACHE && !BF531
+        depends on BFIN_DCACHE && !BF531
        default n
-config BLKFIN_CACHE_LOCK
+config BFIN_ICACHE_LOCK
-        bool "Enable Cache Locking"
+        bool "Enable Instruction Cache Locking"
 choice
        prompt "Policy"
-        depends on BLKFIN_DCACHE
+        depends on BFIN_DCACHE
-        default BLKFIN_WB
+        default BFIN_WB
-config BLKFIN_WB
+config BFIN_WB
        bool "Write back"
        help
          Write Back Policy:
@@ -646,7 +801,7 @@ config BLKFIN_WB
          If you are unsure of the options and you want to be safe,
          then go with Write Through.
-config BLKFIN_WT
+config BFIN_WT
        bool "Write through"
        help
          Write Back Policy:
@@ -672,66 +827,9 @@ config L1_MAX_PIECE
          Set the max memory pieces for the L1 SRAM allocation algorithm.
          Min value is 16. Max value is 1024.
-menu "Clock Settings"
-config BFIN_KERNEL_CLOCK
-        bool "Re-program Clocks while Kernel boots?"
-        default n
-        help
-          This option decides if kernel clocks are re-programed from the
-          bootloader settings. If the clocks are not set, the SDRAM settings
-          are also not changed, and the Bootloader does 100% of the hardware
-          configuration.
-config VCO_MULT
-        int "VCO Multiplier"
-        depends on BFIN_KERNEL_CLOCK
-        default "22" if BFIN533_EZKIT
-        default "45" if BFIN533_STAMP
-        default "20" if BFIN537_STAMP
-        default "22" if BFIN533_BLUETECHNIX_CM
-        default "20" if BFIN537_BLUETECHNIX_CM
-        default "20" if BFIN561_BLUETECHNIX_CM
-        default "20" if BFIN561_EZKIT
-config CCLK_DIV
-        int "Core Clock Divider"
-        depends on BFIN_KERNEL_CLOCK
-        default 1 if BFIN533_EZKIT
-        default 1 if BFIN533_STAMP
-        default 1 if BFIN537_STAMP
-        default 1 if BFIN533_BLUETECHNIX_CM
-        default 1 if BFIN537_BLUETECHNIX_CM
-        default 1 if BFIN561_BLUETECHNIX_CM
-        default 1 if BFIN561_EZKIT
-config SCLK_DIV
-        int "System Clock Divider"
-        depends on BFIN_KERNEL_CLOCK
-        default 5 if BFIN533_EZKIT
-        default 5 if BFIN533_STAMP
-        default 4 if BFIN537_STAMP
-        default 5 if BFIN533_BLUETECHNIX_CM
-        default 4 if BFIN537_BLUETECHNIX_CM
-        default 4 if BFIN561_BLUETECHNIX_CM
-        default 5 if BFIN561_EZKIT
-config CLKIN_HALF
-        bool "Half ClockIn"
-        depends on BFIN_KERNEL_CLOCK
-        default n
-config PLL_BYPASS
-        bool "Bypass PLL"
-        depends on BFIN_KERNEL_CLOCK
-        default n
-endmenu
 comment "Asynchonous Memory Configuration"
-menu "EBIU_AMBCTL Global Control"
+menu "EBIU_AMGCTL Global Control"
 config C_AMCKEN
        bool "Enable CLKOUT"
        default y
@@ -941,24 +1039,6 @@ config DEBUG_ICACHE_CHECK
          also relocates the irq_panic() function to L1 memory, (which is
          un-cached).
-config DEBUG_KERNEL_START
-        bool "Debug Kernel Startup"
-        depends on DEBUG_KERNEL
-        help
-          Say Y here to put in an mini-execption handler before the kernel
-          replaces the bootloader exception handler. This will stop kernels
-          from dieing at startup with no visible error messages.
-config DEBUG_SERIAL_EARLY_INIT
-        bool "Initialize serial driver early"
-        default n
-        depends on SERIAL_BFIN
-        help
-          Say Y here if you want to get kernel output early when kernel
-          crashes before the normal console initialization. If this option
-          is enable, console output will always go to the ttyBF0, no matter
-          what kernel boot paramters you set.
 config DEBUG_HUNT_FOR_ZERO
        bool "Catch NULL pointer reads/writes"
        default y
@@ -973,8 +1053,89 @@ config DEBUG_HUNT_FOR_ZERO
          Enabling this option will take up an extra entry in CPLB table.
          Otherwise, there is no extra overhead.
+config DEBUG_BFIN_HWTRACE_ON
+        bool "Turn on Blackfin's Hardware Trace"
+        default y
+        help
+          All Blackfins include a Trace Unit which stores a history of the last
+          16 changes in program flow taken by the program sequencer. The history
+          allows the user to recreate the program sequencer’s recent path. This
+          can be handy when an application dies - we print out the execution
+          path of how it got to the offending instruction.
+          By turning this off, you may save a tiny amount of power.
+choice
+        prompt "Omit loop Tracing"
+        default DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
+        depends on DEBUG_BFIN_HWTRACE_ON
+        help
+          The trace buffer can be configured to omit recording of changes in
+          program flow that match either the last entry or one of the last
+          two entries. Omitting one of these entries from the record prevents
+          the trace buffer from overflowing because of any sort of loop (for, do
+          while, etc) in the program.
+          Because zero-overhead Hardware loops are not recorded in the trace buffer,
+          this feature can be used to prevent trace overflow from loops that
+          are nested four deep.
+config DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
+        bool "Trace all Loops"
+        help
+          The trace buffer records all changes of flow 
+config DEBUG_BFIN_HWTRACE_COMPRESSION_ONE
+        bool "Compress single-level loops"
+        help
+          The trace buffer does not record single loops - helpful if trace 
+          is spinning on a while or do loop.
+config DEBUG_BFIN_HWTRACE_COMPRESSION_TWO
+        bool "Compress two-level loops"
+        help
+          The trace buffer does not record loops two levels deep. Helpful if
+          the trace is spinning in a nested loop
+endchoice
+config DEBUG_BFIN_HWTRACE_COMPRESSION
+        int
+        depends on DEBUG_BFIN_HWTRACE_ON
+        default 0 if DEBUG_BFIN_HWTRACE_COMPRESSION_OFF
+        default 1 if DEBUG_BFIN_HWTRACE_COMPRESSION_ONE
+        default 2 if DEBUG_BFIN_HWTRACE_COMPRESSION_TWO
+config DEBUG_BFIN_HWTRACE_EXPAND
+        bool "Expand Trace Buffer greater than 16 entries"
+        depends on DEBUG_BFIN_HWTRACE_ON
+        default n
+        help
+          By selecting this option, every time the 16 hardware entries in
+          the Blackfin's HW Trace buffer are full, the kernel will move them
+          into a software buffer, for dumping when there is an issue. This 
+          has a great impact on performance, (an interrupt every 16 change of 
+          flows) and should normally be turned off, except in those nasty
+          debugging sessions
+config DEBUG_BFIN_HWTRACE_EXPAND_LEN
+        int "Size of Trace buffer (in power of 2k)"
+        range 0 4
+        depends on DEBUG_BFIN_HWTRACE_EXPAND
+        default 1
+        help
+          This sets the size of the software buffer that the trace information
+          is kept in.
+          0 for (2^0)  1k, or 256 entries,
+          1 for (2^1)  2k, or 512 entries,
+          2 for (2^2)  4k, or 1024 entries,
+          3 for (2^3)  8k, or 2048 entries,
+          4 for (2^4) 16k, or 4096 entries
 config DEBUG_BFIN_NO_KERN_HWTRACE
        bool "Trace user apps (turn off hwtrace in kernel)"
+        depends on DEBUG_BFIN_HWTRACE_ON
        default n
        help
          Some pieces of the kernel contain a lot of flow changes which can
@@ -985,6 +1146,20 @@ config DEBUG_BFIN_NO_KERN_HWTRACE
          Say Y here to disable hardware tracing in some known "jumpy" pieces
          of code so that the trace buffer will extend further back.
+config EARLY_PRINTK
+        bool "Early printk" 
+        default n
+        help
+          This option enables special console drivers which allow the kernel
+          to print messages very early in the bootup process.
+          This is useful for kernel debugging when your machine crashes very
+          early before the console code is initialized. After enabling this
+          feature, you must add "earlyprintk=serial,uart0,57600" to the
+          command line (bootargs). It is safe to say Y here in all cases, as
+          all of this lives in the init section and is thrown away after the
+          kernel boots completely.
 config DUAL_CORE_TEST_MODULE
        tristate "Dual Core Test Module"
        depends on (BF561)
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 1cf1ab28dc66..57f58d5cd47a 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21.5
+# Linux kernel version: 2.6.22.6
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -15,8 +15,9 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 # CONFIG_GENERIC_TIME is not set
-CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_IRQCHIP_DEMUX_GPIO=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -40,7 +41,9 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_TASKSTATS is not set
 # CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
 CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
 CONFIG_BLK_DEV_INITRD=y
@@ -58,15 +61,20 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
-CONFIG_BUDDY=y
 # CONFIG_NP2 is not set
 CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
 #
 # Loadable module support
@@ -184,19 +192,17 @@ CONFIG_WDTIMER=13
 # CONFIG_CMDLINE_BOOL is not set
 #
-# Board Setup
+# Clock/PLL Setup
 #
 CONFIG_CLKIN_HZ=27000000
-CONFIG_MEM_SIZE=32
+# CONFIG_BFIN_KERNEL_CLOCK is not set
-CONFIG_MEM_ADD_WIDTH=9
+CONFIG_MAX_VCO_HZ=750000000
-CONFIG_BOOT_LOAD=0x1000
+CONFIG_MIN_VCO_HZ=50000000
+CONFIG_MAX_SCLK_HZ=133000000
-#
+CONFIG_MIN_SCLK_HZ=27000000
-# Blackfin Kernel Optimizations
-#
 #
-# Timer Tick
+# Kernel Timer/Scheduler
 #
 # CONFIG_HZ_100 is not set
 CONFIG_HZ_250=y
@@ -205,6 +211,20 @@ CONFIG_HZ_250=y
 CONFIG_HZ=250
 #
+# Memory Setup
+#
+CONFIG_MEM_SIZE=32
+CONFIG_MEM_ADD_WIDTH=9
+CONFIG_BOOT_LOAD=0x1000
+CONFIG_BFIN_SCRATCH_REG_RETN=y
+# CONFIG_BFIN_SCRATCH_REG_RETE is not set
+# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
+#
+# Blackfin Kernel Optimizations
+#
+#
 # Memory Optimizations
 #
 CONFIG_I_ENTRY_L1=y
@@ -243,20 +263,15 @@ CONFIG_DMA_UNCACHED_1M=y
 #
 # Cache Support
 #
-CONFIG_BLKFIN_CACHE=y
+CONFIG_BFIN_ICACHE=y
-CONFIG_BLKFIN_DCACHE=y
+CONFIG_BFIN_DCACHE=y
-# CONFIG_BLKFIN_DCACHE_BANKA is not set
+# CONFIG_BFIN_DCACHE_BANKA is not set
-# CONFIG_BLKFIN_CACHE_LOCK is not set
+# CONFIG_BFIN_ICACHE_LOCK is not set
-# CONFIG_BLKFIN_WB is not set
+# CONFIG_BFIN_WB is not set
-CONFIG_BLKFIN_WT=y
+CONFIG_BFIN_WT=y
 CONFIG_L1_MAX_PIECE=16
 #
-# Clock Settings
-#
-# CONFIG_BFIN_KERNEL_CLOCK is not set
-#
 # Asynchonous Memory Configuration
 #
@@ -277,12 +292,13 @@ CONFIG_C_AMBEN_ALL=y
 CONFIG_BANK_0=0x7BB0
 CONFIG_BANK_1=0x7BB0
 CONFIG_BANK_2=0x7BB0
-CONFIG_BANK_3=0x99B3
+CONFIG_BANK_3=0xAAC3
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
 # CONFIG_PCI is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 #
 # PCCARD (PCMCIA/CardBus) support
@@ -290,10 +306,6 @@ CONFIG_BANK_3=0x99B3
 # CONFIG_PCCARD is not set
 #
-# PCI Hotplug Support
-#
-#
 # Executable file formats
 #
 CONFIG_BINFMT_ELF_FDPIC=y
@@ -327,7 +339,6 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -368,20 +379,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -448,7 +447,16 @@ CONFIG_IRTTY_SIR=m
 # FIR device drivers
 #
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
 #
 # Device Drivers
@@ -466,10 +474,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # Connector - unified userspace <-> kernelspace linker
 #
 # CONFIG_CONNECTOR is not set
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -513,7 +517,6 @@ CONFIG_MTD_MW320D=m
 CONFIG_MTD_RAM=y
 CONFIG_MTD_ROM=m
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 #
 # Mapping drivers for chip access
@@ -550,16 +553,13 @@ CONFIG_BFIN_FLASH_BANK_3=0x7BB0
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
 #
-# OneNAND Flash Device Drivers
+# UBI - Unsorted block images
 #
-# CONFIG_MTD_ONENAND is not set
+# CONFIG_MTD_UBI is not set
 #
 # Parallel port support
@@ -587,10 +587,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 #
 # Misc devices
 #
-#
-# ATA/ATAPI/MFM/RLL support
-#
 # CONFIG_IDE is not set
 #
@@ -599,10 +595,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
 # CONFIG_SCSI_NETLINK is not set
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
 #
@@ -611,19 +603,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_MD is not set
 #
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-#
-# IEEE 1394 (FireWire) support
-#
-#
-# I2O device support
-#
-#
 # Network device support
 #
 CONFIG_NETDEVICES=y
@@ -631,10 +610,6 @@ CONFIG_NETDEVICES=y
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-#
-# PHY device support
-#
 # CONFIG_PHYLIB is not set
 #
@@ -644,27 +619,15 @@ CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_SMC91X=y
 # CONFIG_SMSC911X is not set
+# CONFIG_DM9000 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
 #
-# Ethernet (1000 Mbit)
+# Wireless LAN
-#
-#
-# Ethernet (10000 Mbit)
-#
-#
-# Token Ring devices
-#
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-#
-# Wan interfaces
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -688,6 +651,7 @@ CONFIG_SMC91X=y
 #
 CONFIG_INPUT=m
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 #
 # Userland interfaces
@@ -704,6 +668,7 @@ CONFIG_INPUT_EVDEV=m
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
@@ -718,7 +683,7 @@ CONFIG_INPUT_EVDEV=m
 #
 # CONFIG_AD9960 is not set
 # CONFIG_SPI_ADC_BF533 is not set
-# CONFIG_BF5xx_PFLAGS is not set
+# CONFIG_BFIN_PFLAGS is not set
 # CONFIG_BF5xx_PPIFCD is not set
 # CONFIG_BF5xx_TIMERS is not set
 # CONFIG_BF5xx_PPI is not set
@@ -758,10 +723,6 @@ CONFIG_UNIX98_PTYS=y
 # IPMI
 #
 # CONFIG_IPMI_HANDLER is not set
-#
-# Watchdog Cards
-#
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
@@ -773,7 +734,6 @@ CONFIG_BFIN_WDT=y
 CONFIG_HW_RANDOM=y
 # CONFIG_GEN_RTC is not set
 CONFIG_BLACKFIN_DPMC=y
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
@@ -781,10 +741,6 @@ CONFIG_BLACKFIN_DPMC=y
 # TPM devices
 #
 # CONFIG_TCG_TPM is not set
-#
-# I2C support
-#
 # CONFIG_I2C is not set
 #
@@ -803,22 +759,22 @@ CONFIG_SPI_BFIN=y
 # SPI Protocol Masters
 #
 # CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
 #
 # Dallas's 1-wire bus
 #
 # CONFIG_W1 is not set
-#
-# Hardware Monitoring support
-#
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
 # CONFIG_SENSORS_ABITUGURU is not set
 # CONFIG_SENSORS_F71805F is not set
 # CONFIG_SENSORS_LM70 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627HF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
 #
@@ -830,16 +786,19 @@ CONFIG_HWMON=y
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
 #
-# Digital Video Broadcasting Devices
+# Graphics support
 #
-# CONFIG_DVB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 #
-# Graphics support
+# Display device support
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
 # CONFIG_FB is not set
 #
@@ -862,18 +821,17 @@ CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB is not set
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# Enable Host or Gadget support to see Inventra options
 #
 #
-# USB Gadget Support
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
-# CONFIG_USB_GADGET is not set
 #
-# MMC/SD Card support
+# USB Gadget Support
 #
-# CONFIG_SPI_MMC is not set
+# CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
 #
@@ -913,17 +871,29 @@ CONFIG_RTC_INTF_SYSFS=y
 CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+#
+# I2C RTC drivers
+#
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
 #
-# RTC drivers
+# Platform RTC drivers
 #
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_TEST is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
 # CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
 CONFIG_RTC_DRV_BFIN=y
 #
@@ -940,14 +910,6 @@ CONFIG_RTC_DRV_BFIN=y
 #
 #
-# Auxiliary Display support
-#
-#
-# Virtualization
-#
-#
 # PBX support
 #
 # CONFIG_PBX is not set
@@ -1047,6 +1009,7 @@ CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
+# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1124,14 +1087,20 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_SERIAL_EARLY_INIT is not set
+CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
+CONFIG_DEBUG_BFIN_HWTRACE_ON=y
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
+# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
@@ -1154,6 +1123,7 @@ CONFIG_SECURITY_CAPABILITIES=m
 CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
@@ -1161,3 +1131,4 @@ CONFIG_ZLIB_DEFLATE=m
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index 64b7f1b3b2af..306302baff06 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21.5
+# Linux kernel version: 2.6.22.6
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -15,8 +15,9 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 # CONFIG_GENERIC_TIME is not set
-CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_IRQCHIP_DEMUX_GPIO=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -40,7 +41,9 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_TASKSTATS is not set
 # CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
 CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
 CONFIG_BLK_DEV_INITRD=y
@@ -58,15 +61,20 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
-CONFIG_BUDDY=y
 # CONFIG_NP2 is not set
 CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
 #
 # Loadable module support
@@ -185,9 +193,27 @@ CONFIG_WDTIMER=13
 # CONFIG_CMDLINE_BOOL is not set
 #
-# Board Setup
+# Clock/PLL Setup
 #
 CONFIG_CLKIN_HZ=11059200
+# CONFIG_BFIN_KERNEL_CLOCK is not set
+CONFIG_MAX_VCO_HZ=750000000
+CONFIG_MIN_VCO_HZ=50000000
+CONFIG_MAX_SCLK_HZ=133000000
+CONFIG_MIN_SCLK_HZ=27000000
+#
+# Kernel Timer/Scheduler
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+#
+# Memory Setup
+#
 CONFIG_MEM_SIZE=128
 CONFIG_MEM_ADD_WIDTH=11
 CONFIG_ENET_FLASH_PIN=0
@@ -198,6 +224,9 @@ CONFIG_BOOT_LOAD=0x1000
 #
 # CONFIG_BFIN_ALIVE_LED is not set
 # CONFIG_BFIN_IDLE_LED is not set
+CONFIG_BFIN_SCRATCH_REG_RETN=y
+# CONFIG_BFIN_SCRATCH_REG_RETE is not set
+# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
 CONFIG_BFIN_ALIVE_LED_PORT=0xFFC00700
 CONFIG_BFIN_ALIVE_LED_DPORT=0xFFC00730
 CONFIG_BFIN_IDLE_LED_PORT=0xFFC00700
@@ -208,15 +237,6 @@ CONFIG_BFIN_IDLE_LED_DPORT=0xFFC00730
 #
 #
-# Timer Tick
-#
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-# CONFIG_HZ_300 is not set
-# CONFIG_HZ_1000 is not set
-CONFIG_HZ=250
-#
 # Memory Optimizations
 #
 CONFIG_I_ENTRY_L1=y
@@ -255,20 +275,15 @@ CONFIG_DMA_UNCACHED_1M=y
 #
 # Cache Support
 #
-CONFIG_BLKFIN_CACHE=y
+CONFIG_BFIN_ICACHE=y
-CONFIG_BLKFIN_DCACHE=y
+CONFIG_BFIN_DCACHE=y
-# CONFIG_BLKFIN_DCACHE_BANKA is not set
+# CONFIG_BFIN_DCACHE_BANKA is not set
-# CONFIG_BLKFIN_CACHE_LOCK is not set
+# CONFIG_BFIN_ICACHE_LOCK is not set
-# CONFIG_BLKFIN_WB is not set
+# CONFIG_BFIN_WB is not set
-CONFIG_BLKFIN_WT=y
+CONFIG_BFIN_WT=y
 CONFIG_L1_MAX_PIECE=16
 #
-# Clock Settings
-#
-# CONFIG_BFIN_KERNEL_CLOCK is not set
-#
 # Asynchonous Memory Configuration
 #
@@ -289,12 +304,13 @@ CONFIG_C_AMBEN_ALL=y
 CONFIG_BANK_0=0x7BB0
 CONFIG_BANK_1=0x7BB0
 CONFIG_BANK_2=0x7BB0
-CONFIG_BANK_3=0x99B3
+CONFIG_BANK_3=0xAAC3
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
 # CONFIG_PCI is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 #
 # PCCARD (PCMCIA/CardBus) support
@@ -302,10 +318,6 @@ CONFIG_BANK_3=0x99B3
 # CONFIG_PCCARD is not set
 #
-# PCI Hotplug Support
-#
-#
 # Executable file formats
 #
 CONFIG_BINFMT_ELF_FDPIC=y
@@ -339,7 +351,6 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -380,20 +391,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -460,7 +459,16 @@ CONFIG_IRTTY_SIR=m
 # FIR device drivers
 #
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
 #
 # Device Drivers
@@ -478,10 +486,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # Connector - unified userspace <-> kernelspace linker
 #
 # CONFIG_CONNECTOR is not set
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -525,7 +529,6 @@ CONFIG_MTD_MW320D=m
 CONFIG_MTD_RAM=y
 CONFIG_MTD_ROM=m
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 #
 # Mapping drivers for chip access
@@ -562,16 +565,13 @@ CONFIG_BFIN_FLASH_BANK_3=0x7BB0
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
 #
-# OneNAND Flash Device Drivers
+# UBI - Unsorted block images
 #
-# CONFIG_MTD_ONENAND is not set
+# CONFIG_MTD_UBI is not set
 #
 # Parallel port support
@@ -599,10 +599,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 #
 # Misc devices
 #
-#
-# ATA/ATAPI/MFM/RLL support
-#
 # CONFIG_IDE is not set
 #
@@ -611,10 +607,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
 # CONFIG_SCSI_NETLINK is not set
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
 #
@@ -623,19 +615,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_MD is not set
 #
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-#
-# IEEE 1394 (FireWire) support
-#
-#
-# I2O device support
-#
-#
 # Network device support
 #
 CONFIG_NETDEVICES=y
@@ -643,10 +622,6 @@ CONFIG_NETDEVICES=y
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-#
-# PHY device support
-#
 # CONFIG_PHYLIB is not set
 #
@@ -656,27 +631,15 @@ CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_SMC91X=y
 # CONFIG_SMSC911X is not set
+# CONFIG_DM9000 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
 #
-# Ethernet (1000 Mbit)
+# Wireless LAN
-#
-#
-# Ethernet (10000 Mbit)
-#
-#
-# Token Ring devices
-#
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-#
-# Wan interfaces
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -700,6 +663,7 @@ CONFIG_SMC91X=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 #
 # Userland interfaces
@@ -716,8 +680,14 @@ CONFIG_INPUT_EVDEV=m
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
 # CONFIG_INPUT_UINPUT is not set
 # CONFIG_BF53X_PFBUTTONS is not set
 CONFIG_TWI_KEYPAD=m
@@ -734,7 +704,7 @@ CONFIG_BFIN_TWIKEYPAD_IRQ_PFX=39
 #
 # CONFIG_AD9960 is not set
 # CONFIG_SPI_ADC_BF533 is not set
-# CONFIG_BF5xx_PFLAGS is not set
+# CONFIG_BFIN_PFLAGS is not set
 # CONFIG_BF5xx_PPIFCD is not set
 # CONFIG_BF5xx_TIMERS is not set
 # CONFIG_BF5xx_PPI is not set
@@ -777,10 +747,6 @@ CONFIG_UNIX98_PTYS=y
 # IPMI
 #
 # CONFIG_IPMI_HANDLER is not set
-#
-# Watchdog Cards
-#
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
@@ -792,7 +758,6 @@ CONFIG_BFIN_WDT=y
 CONFIG_HW_RANDOM=y
 # CONFIG_GEN_RTC is not set
 CONFIG_BLACKFIN_DPMC=y
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
@@ -800,11 +765,8 @@ CONFIG_BLACKFIN_DPMC=y
 # TPM devices
 #
 # CONFIG_TCG_TPM is not set
-#
-# I2C support
-#
 CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=m
 #
@@ -818,10 +780,11 @@ CONFIG_I2C_ALGOBIT=m
 # I2C Hardware Bus support
 #
 # CONFIG_I2C_BLACKFIN_GPIO is not set
+# CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
 # CONFIG_I2C_STUB is not set
-# CONFIG_I2C_PCA_ISA is not set
 #
 # Miscellaneous I2C Chip support
@@ -857,18 +820,16 @@ CONFIG_SPI_BFIN=y
 # SPI Protocol Masters
 #
 # CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
 #
 # Dallas's 1-wire bus
 #
 # CONFIG_W1 is not set
-#
-# Hardware Monitoring support
-#
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
 # CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_AD7418 is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
@@ -896,6 +857,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
@@ -920,22 +882,30 @@ CONFIG_HWMON=y
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
 #
-# Digital Video Broadcasting Devices
+# Graphics support
 #
-# CONFIG_DVB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 #
-# Graphics support
+# Display device support
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
 CONFIG_FB=m
 CONFIG_FIRMWARE_EDID=y
 # CONFIG_FB_DDC is not set
 CONFIG_FB_CFB_FILLRECT=m
 CONFIG_FB_CFB_COPYAREA=m
 CONFIG_FB_CFB_IMAGEBLIT=m
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -957,10 +927,6 @@ CONFIG_ADV7393_1XMEM=y
 # CONFIG_ADV7393_2XMEM is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
-#
-# Logo configuration
-#
 # CONFIG_LOGO is not set
 #
@@ -1001,7 +967,6 @@ CONFIG_SND_BLACKFIN_AD1836_TDM=y
 # CONFIG_SND_BLACKFIN_AD1836_I2S is not set
 CONFIG_SND_BLACKFIN_AD1836_MULSUB=y
 # CONFIG_SND_BLACKFIN_AD1836_5P1 is not set
-CONFIG_SND_BLACKFIN_AD1981B=m
 CONFIG_SND_BLACKFIN_SPORT=0
 CONFIG_SND_BLACKFIN_SPI_PFBIT=4
 CONFIG_SND_BFIN_AD73311=m
@@ -1009,11 +974,16 @@ CONFIG_SND_BFIN_SPORT=0
 CONFIG_SND_BFIN_AD73311_SE=4
 #
-# SoC audio support
+# System on Chip audio support
 #
 # CONFIG_SND_SOC is not set
 #
+# SoC Audio for the ADI Blackfin
+#
+# CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set
+#
 # Open Sound System
 #
 # CONFIG_SOUND_PRIME is not set
@@ -1033,18 +1003,17 @@ CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB is not set
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# Enable Host or Gadget support to see Inventra options
 #
 #
-# USB Gadget Support
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
-# CONFIG_USB_GADGET is not set
 #
-# MMC/SD Card support
+# USB Gadget Support
 #
-# CONFIG_SPI_MMC is not set
+# CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
 #
@@ -1084,44 +1053,50 @@ CONFIG_RTC_INTF_SYSFS=y
 CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 #
-# RTC drivers
+# I2C RTC drivers
 #
-# CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
 # CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+#
+# SPI RTC drivers
+#
 # CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_TEST is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-CONFIG_RTC_DRV_BFIN=y
 #
-# DMA Engine support
+# Platform RTC drivers
 #
-# CONFIG_DMA_ENGINE is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 #
-# DMA Clients
+# on-CPU RTC drivers
 #
+CONFIG_RTC_DRV_BFIN=y
 #
-# DMA Devices
+# DMA Engine support
 #
+# CONFIG_DMA_ENGINE is not set
 #
-# Auxiliary Display support
+# DMA Clients
 #
 #
-# Virtualization
+# DMA Devices
 #
 #
@@ -1224,6 +1199,7 @@ CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
+# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1301,14 +1277,20 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_SERIAL_EARLY_INIT is not set
+CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
+CONFIG_DEBUG_BFIN_HWTRACE_ON=y
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
+# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
@@ -1331,6 +1313,7 @@ CONFIG_SECURITY_CAPABILITIES=m
 CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
@@ -1338,3 +1321,4 @@ CONFIG_ZLIB_DEFLATE=m
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index ccf09dc09a18..828b604438eb 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21.5
+# Linux kernel version: 2.6.22.6
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -15,8 +15,9 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 # CONFIG_GENERIC_TIME is not set
-CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_IRQCHIP_DEMUX_GPIO=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -40,7 +41,9 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_TASKSTATS is not set
 # CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
 CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
 CONFIG_BLK_DEV_INITRD=y
@@ -58,15 +61,20 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
-CONFIG_BUDDY=y
 # CONFIG_NP2 is not set
 CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
 #
 # Loadable module support
@@ -148,13 +156,6 @@ CONFIG_IRQ_PLL_WAKEUP=7
 #
 #
-# PORT F/G Selection
-#
-CONFIG_BF537_PORT_F=y
-# CONFIG_BF537_PORT_G is not set
-# CONFIG_BF537_PORT_H is not set
-#
 # Interrupt Priority Assignment
 #
@@ -199,19 +200,17 @@ CONFIG_IRQ_WATCH=13
 # CONFIG_CMDLINE_BOOL is not set
 #
-# Board Setup
+# Clock/PLL Setup
 #
 CONFIG_CLKIN_HZ=25000000
-CONFIG_MEM_SIZE=64
+# CONFIG_BFIN_KERNEL_CLOCK is not set
-CONFIG_MEM_ADD_WIDTH=10
+CONFIG_MAX_VCO_HZ=600000000
-CONFIG_BOOT_LOAD=0x1000
+CONFIG_MIN_VCO_HZ=50000000
+CONFIG_MAX_SCLK_HZ=133000000
-#
+CONFIG_MIN_SCLK_HZ=27000000
-# Blackfin Kernel Optimizations
-#
 #
-# Timer Tick
+# Kernel Timer/Scheduler
 #
 # CONFIG_HZ_100 is not set
 CONFIG_HZ_250=y
@@ -220,6 +219,20 @@ CONFIG_HZ_250=y
 CONFIG_HZ=250
 #
+# Memory Setup
+#
+CONFIG_MEM_SIZE=64
+CONFIG_MEM_ADD_WIDTH=10
+CONFIG_BOOT_LOAD=0x1000
+CONFIG_BFIN_SCRATCH_REG_RETN=y
+# CONFIG_BFIN_SCRATCH_REG_RETE is not set
+# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
+#
+# Blackfin Kernel Optimizations
+#
+#
 # Memory Optimizations
 #
 CONFIG_I_ENTRY_L1=y
@@ -258,20 +271,15 @@ CONFIG_DMA_UNCACHED_1M=y
 #
 # Cache Support
 #
-CONFIG_BLKFIN_CACHE=y
+CONFIG_BFIN_ICACHE=y
-CONFIG_BLKFIN_DCACHE=y
+CONFIG_BFIN_DCACHE=y
-# CONFIG_BLKFIN_DCACHE_BANKA is not set
+# CONFIG_BFIN_DCACHE_BANKA is not set
-# CONFIG_BLKFIN_CACHE_LOCK is not set
+# CONFIG_BFIN_ICACHE_LOCK is not set
-# CONFIG_BLKFIN_WB is not set
+# CONFIG_BFIN_WB is not set
-CONFIG_BLKFIN_WT=y
+CONFIG_BFIN_WT=y
 CONFIG_L1_MAX_PIECE=16
 #
-# Clock Settings
-#
-# CONFIG_BFIN_KERNEL_CLOCK is not set
-#
 # Asynchonous Memory Configuration
 #
@@ -298,6 +306,7 @@ CONFIG_BANK_3=0x99B3
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
 # CONFIG_PCI is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 #
 # PCCARD (PCMCIA/CardBus) support
@@ -305,10 +314,6 @@ CONFIG_BANK_3=0x99B3
 # CONFIG_PCCARD is not set
 #
-# PCI Hotplug Support
-#
-#
 # Executable file formats
 #
 CONFIG_BINFMT_ELF_FDPIC=y
@@ -342,7 +347,6 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -383,20 +387,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -463,7 +455,16 @@ CONFIG_IRTTY_SIR=m
 # FIR device drivers
 #
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
 #
 # Device Drivers
@@ -481,10 +482,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # Connector - unified userspace <-> kernelspace linker
 #
 # CONFIG_CONNECTOR is not set
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -528,7 +525,6 @@ CONFIG_MTD_MW320D=m
 CONFIG_MTD_RAM=y
 CONFIG_MTD_ROM=m
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 #
 # Mapping drivers for chip access
@@ -565,13 +561,10 @@ CONFIG_BFIN_FLASH_BANK_3=0x7BB0
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-#
-# NAND Flash Device Drivers
-#
 CONFIG_MTD_NAND=m
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_BFIN=m
 CONFIG_BFIN_NAND_BASE=0x20212000
 CONFIG_BFIN_NAND_CLE=2
@@ -580,11 +573,13 @@ CONFIG_BFIN_NAND_READY=3
 CONFIG_MTD_NAND_IDS=m
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
 #
-# OneNAND Flash Device Drivers
+# UBI - Unsorted block images
 #
-# CONFIG_MTD_ONENAND is not set
+# CONFIG_MTD_UBI is not set
 #
 # Parallel port support
@@ -612,10 +607,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 #
 # Misc devices
 #
-#
-# ATA/ATAPI/MFM/RLL support
-#
 # CONFIG_IDE is not set
 #
@@ -624,10 +615,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
 # CONFIG_SCSI_NETLINK is not set
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
 #
@@ -636,19 +623,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_MD is not set
 #
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-#
-# IEEE 1394 (FireWire) support
-#
-#
-# I2O device support
-#
-#
 # Network device support
 #
 CONFIG_NETDEVICES=y
@@ -656,11 +630,20 @@ CONFIG_NETDEVICES=y
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+CONFIG_PHYLIB=y
 #
-# PHY device support
+# MII PHY device drivers
 #
-# CONFIG_PHYLIB is not set
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_FIXED_PHY is not set
 #
 # Ethernet (10 or 100Mbit)
@@ -674,27 +657,15 @@ CONFIG_BFIN_TX_DESC_NUM=10
 CONFIG_BFIN_RX_DESC_NUM=20
 # CONFIG_BFIN_MAC_RMII is not set
 # CONFIG_SMSC911X is not set
+# CONFIG_DM9000 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
 #
-# Ethernet (1000 Mbit)
+# Wireless LAN
-#
-#
-# Ethernet (10000 Mbit)
-#
-#
-# Token Ring devices
-#
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-#
-# Wan interfaces
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -718,6 +689,7 @@ CONFIG_BFIN_RX_DESC_NUM=20
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 #
 # Userland interfaces
@@ -734,8 +706,14 @@ CONFIG_INPUT_EVDEV=m
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
 # CONFIG_INPUT_UINPUT is not set
 # CONFIG_BF53X_PFBUTTONS is not set
 CONFIG_TWI_KEYPAD=m
@@ -752,7 +730,7 @@ CONFIG_BFIN_TWIKEYPAD_IRQ_PFX=72
 #
 # CONFIG_AD9960 is not set
 # CONFIG_SPI_ADC_BF533 is not set
-# CONFIG_BF5xx_PFLAGS is not set
+# CONFIG_BFIN_PFLAGS is not set
 # CONFIG_BF5xx_PPIFCD is not set
 # CONFIG_BF5xx_TIMERS is not set
 # CONFIG_BF5xx_PPI is not set
@@ -803,10 +781,6 @@ CONFIG_CAN_BLACKFIN=m
 # IPMI
 #
 # CONFIG_IPMI_HANDLER is not set
-#
-# Watchdog Cards
-#
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
@@ -818,7 +792,6 @@ CONFIG_BFIN_WDT=y
 CONFIG_HW_RANDOM=y
 # CONFIG_GEN_RTC is not set
 CONFIG_BLACKFIN_DPMC=y
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
@@ -826,11 +799,8 @@ CONFIG_BLACKFIN_DPMC=y
 # TPM devices
 #
 # CONFIG_TCG_TPM is not set
-#
-# I2C support
-#
 CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=m
 #
@@ -846,10 +816,11 @@ CONFIG_I2C_CHARDEV=m
 # CONFIG_I2C_BLACKFIN_GPIO is not set
 CONFIG_I2C_BLACKFIN_TWI=m
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
+# CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
 # CONFIG_I2C_STUB is not set
-# CONFIG_I2C_PCA_ISA is not set
 #
 # Miscellaneous I2C Chip support
@@ -885,18 +856,16 @@ CONFIG_SPI_BFIN=y
 # SPI Protocol Masters
 #
 # CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
 #
 # Dallas's 1-wire bus
 #
 # CONFIG_W1 is not set
-#
-# Hardware Monitoring support
-#
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
 # CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_AD7418 is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
@@ -924,6 +893,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
@@ -948,11 +918,8 @@ CONFIG_HWMON=y
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
-#
+CONFIG_DAB=y
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
 #
 # Graphics support
@@ -960,12 +927,23 @@ CONFIG_HWMON=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=m
 CONFIG_LCD_CLASS_DEVICE=m
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
 CONFIG_FB=m
 CONFIG_FIRMWARE_EDID=y
 # CONFIG_FB_DDC is not set
 CONFIG_FB_CFB_FILLRECT=m
 CONFIG_FB_CFB_COPYAREA=m
 CONFIG_FB_CFB_IMAGEBLIT=m
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -991,10 +969,6 @@ CONFIG_LQ035_SLAVE_ADDR=0x58
 # CONFIG_FB_BFIN_BGR is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
-#
-# Logo configuration
-#
 # CONFIG_LOGO is not set
 #
@@ -1035,7 +1009,6 @@ CONFIG_SND_BLACKFIN_AD1836_TDM=y
 # CONFIG_SND_BLACKFIN_AD1836_I2S is not set
 CONFIG_SND_BLACKFIN_AD1836_MULSUB=y
 # CONFIG_SND_BLACKFIN_AD1836_5P1 is not set
-CONFIG_SND_BLACKFIN_AD1981B=m
 CONFIG_SND_BLACKFIN_SPORT=0
 CONFIG_SND_BLACKFIN_SPI_PFBIT=4
 CONFIG_SND_BFIN_AD73311=m
@@ -1043,11 +1016,16 @@ CONFIG_SND_BFIN_SPORT=0
 CONFIG_SND_BFIN_AD73311_SE=4
 #
-# SoC audio support
+# System on Chip audio support
 #
 # CONFIG_SND_SOC is not set
 #
+# SoC Audio for the ADI Blackfin
+#
+# CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set
+#
 # Open Sound System
 #
 # CONFIG_SOUND_PRIME is not set
@@ -1067,18 +1045,17 @@ CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB is not set
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# Enable Host or Gadget support to see Inventra options
 #
 #
-# USB Gadget Support
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
-# CONFIG_USB_GADGET is not set
 #
-# MMC/SD Card support
+# USB Gadget Support
 #
-# CONFIG_SPI_MMC is not set
+# CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
 #
@@ -1118,44 +1095,50 @@ CONFIG_RTC_INTF_SYSFS=y
 CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 #
-# RTC drivers
+# I2C RTC drivers
 #
-# CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
 # CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+#
+# SPI RTC drivers
+#
 # CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_TEST is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-CONFIG_RTC_DRV_BFIN=y
 #
-# DMA Engine support
+# Platform RTC drivers
 #
-# CONFIG_DMA_ENGINE is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 #
-# DMA Clients
+# on-CPU RTC drivers
 #
+CONFIG_RTC_DRV_BFIN=y
 #
-# DMA Devices
+# DMA Engine support
 #
+# CONFIG_DMA_ENGINE is not set
 #
-# Auxiliary Display support
+# DMA Clients
 #
 #
-# Virtualization
+# DMA Devices
 #
 #
@@ -1258,6 +1241,7 @@ CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
+# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1335,14 +1319,20 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_SERIAL_EARLY_INIT is not set
+CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
+CONFIG_DEBUG_BFIN_HWTRACE_ON=y
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
+# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
@@ -1365,6 +1355,7 @@ CONFIG_SECURITY_CAPABILITIES=m
 CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
@@ -1372,3 +1363,4 @@ CONFIG_ZLIB_DEFLATE=m
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index ac8390fafa9c..e80f3d59c283 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21.5
+# Linux kernel version: 2.6.22.6
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -15,8 +15,9 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 # CONFIG_GENERIC_TIME is not set
-CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_IRQCHIP_DEMUX_GPIO=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -40,7 +41,9 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_TASKSTATS is not set
 # CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
 CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
 CONFIG_BLK_DEV_INITRD=y
@@ -51,7 +54,6 @@ CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
 CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
 # CONFIG_KALLSYMS_EXTRA_PASS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
@@ -59,14 +61,20 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
 # CONFIG_NP2 is not set
 CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
 #
 # Loadable module support
@@ -165,6 +173,7 @@ CONFIG_IRQ_UART1_TX=10
 #
 # BF548 Specific Configuration
 #
+# CONFIG_DEB_DMA_URGENT is not set
 #
 # Interrupt Priority Assignment
@@ -242,24 +251,35 @@ CONFIG_IRQ_PINT2=11
 CONFIG_IRQ_PINT3=11
 #
-# Board customizations
+# Pin Interrupt to Port Assignment
 #
-# CONFIG_CMDLINE_BOOL is not set
 #
-# Board Setup
+# Assignment
 #
-CONFIG_CLKIN_HZ=25000000
+CONFIG_PINTx_REASSIGN=y
-CONFIG_MEM_SIZE=64
+CONFIG_PINT0_ASSIGN=0x00000101
-CONFIG_MEM_ADD_WIDTH=10
+CONFIG_PINT1_ASSIGN=0x01010000
-CONFIG_BOOT_LOAD=0x1000
+CONFIG_PINT2_ASSIGN=0x07000101
+CONFIG_PINT3_ASSIGN=0x02020303
 #
-# Blackfin Kernel Optimizations
+# Board customizations
 #
+# CONFIG_CMDLINE_BOOL is not set
 #
-# Timer Tick
+# Clock/PLL Setup
+#
+CONFIG_CLKIN_HZ=25000000
+# CONFIG_BFIN_KERNEL_CLOCK is not set
+CONFIG_MAX_VCO_HZ=533000000
+CONFIG_MIN_VCO_HZ=50000000
+CONFIG_MAX_SCLK_HZ=133000000
+CONFIG_MIN_SCLK_HZ=27000000
+#
+# Kernel Timer/Scheduler
 #
 # CONFIG_HZ_100 is not set
 CONFIG_HZ_250=y
@@ -268,6 +288,20 @@ CONFIG_HZ_250=y
 CONFIG_HZ=250
 #
+# Memory Setup
+#
+CONFIG_MEM_SIZE=64
+CONFIG_MEM_ADD_WIDTH=10
+CONFIG_BOOT_LOAD=0x1000
+CONFIG_BFIN_SCRATCH_REG_RETN=y
+# CONFIG_BFIN_SCRATCH_REG_RETE is not set
+# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
+#
+# Blackfin Kernel Optimizations
+#
+#
 # Memory Optimizations
 #
 CONFIG_I_ENTRY_L1=y
@@ -275,12 +309,12 @@ CONFIG_EXCPT_IRQ_SYSC_L1=y
 CONFIG_DO_IRQ_L1=y
 CONFIG_CORE_TIMER_IRQ_L1=y
 CONFIG_IDLE_L1=y
-CONFIG_SCHEDULE_L1=y
+# CONFIG_SCHEDULE_L1 is not set
 CONFIG_ARITHMETIC_OPS_L1=y
 CONFIG_ACCESS_OK_L1=y
-CONFIG_MEMSET_L1=y
+# CONFIG_MEMSET_L1 is not set
-CONFIG_MEMCPY_L1=y
+# CONFIG_MEMCPY_L1 is not set
-CONFIG_SYS_BFIN_SPINLOCK_L1=y
+# CONFIG_SYS_BFIN_SPINLOCK_L1 is not set
 # CONFIG_IP_CHECKSUM_L1 is not set
 CONFIG_CACHELINE_ALIGNED_L1=y
 # CONFIG_SYSCALL_TAB_L1 is not set
@@ -306,20 +340,15 @@ CONFIG_DMA_UNCACHED_1M=y
 #
 # Cache Support
 #
-CONFIG_BLKFIN_CACHE=y
+CONFIG_BFIN_ICACHE=y
-CONFIG_BLKFIN_DCACHE=y
+CONFIG_BFIN_DCACHE=y
-# CONFIG_BLKFIN_DCACHE_BANKA is not set
+# CONFIG_BFIN_DCACHE_BANKA is not set
-# CONFIG_BLKFIN_CACHE_LOCK is not set
+# CONFIG_BFIN_ICACHE_LOCK is not set
-# CONFIG_BLKFIN_WB is not set
+# CONFIG_BFIN_WB is not set
-CONFIG_BLKFIN_WT=y
+CONFIG_BFIN_WT=y
 CONFIG_L1_MAX_PIECE=16
 #
-# Clock Settings
-#
-# CONFIG_BFIN_KERNEL_CLOCK is not set
-#
 # Asynchonous Memory Configuration
 #
@@ -327,7 +356,6 @@ CONFIG_L1_MAX_PIECE=16
 # EBIU_AMBCTL Global Control
 #
 CONFIG_C_AMCKEN=y
-CONFIG_C_CDPRIO=y
 # CONFIG_C_AMBEN is not set
 # CONFIG_C_AMBEN_B0 is not set
 # CONFIG_C_AMBEN_B0_B1 is not set
@@ -338,7 +366,7 @@ CONFIG_C_AMBEN_ALL=y
 # EBIU_AMBCTL Control
 #
 CONFIG_BANK_0=0x7BB0
-CONFIG_BANK_1=0x7BB0
+CONFIG_BANK_1=0x5554
 CONFIG_BANK_2=0x7BB0
 CONFIG_BANK_3=0x99B3
@@ -346,6 +374,7 @@ CONFIG_BANK_3=0x99B3
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
 # CONFIG_PCI is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 #
 # PCCARD (PCMCIA/CardBus) support
@@ -353,10 +382,6 @@ CONFIG_BANK_3=0x99B3
 # CONFIG_PCCARD is not set
 #
-# PCI Hotplug Support
-#
-#
 # Executable file formats
 #
 CONFIG_BINFMT_ELF_FDPIC=y
@@ -383,7 +408,6 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -424,20 +448,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -463,7 +475,16 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
 #
 # Device Drivers
@@ -475,29 +496,23 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 # CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 #
 # Connector - unified userspace <-> kernelspace linker
 #
 # CONFIG_CONNECTOR is not set
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
 #
 # User Modules And Translation Layers
 #
-# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
@@ -509,8 +524,10 @@ CONFIG_MTD_BLOCK=y
 #
 # RAM/ROM/Flash chip drivers
 #
-# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CFI=y
 # CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
 CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -521,22 +538,32 @@ CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+# CONFIG_MTD_MW320D is not set
+CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_RAM=y
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 #
 # Mapping drivers for chip access
 #
 CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x20000000
+CONFIG_MTD_PHYSMAP_LEN=0x400000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
 # CONFIG_MTD_BF5xx is not set
-CONFIG_MTD_UCLINUX=y
+# CONFIG_MTD_UCLINUX is not set
 # CONFIG_MTD_PLATRAM is not set
 #
 # Self-contained MTD device drivers
 #
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -548,16 +575,23 @@ CONFIG_MTD_UCLINUX=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_BFIN is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_BF5XX=y
+CONFIG_MTD_NAND_BF5XX_HWECC=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
 #
-# NAND Flash Device Drivers
+# UBI - Unsorted block images
-#
-# CONFIG_MTD_NAND is not set
-#
-# OneNAND Flash Device Drivers
 #
-# CONFIG_MTD_ONENAND is not set
+# CONFIG_MTD_UBI is not set
 #
 # Parallel port support
@@ -585,41 +619,61 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 #
 # Misc devices
 #
-#
-# ATA/ATAPI/MFM/RLL support
-#
 # CONFIG_IDE is not set
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
 #
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
+# SCSI support type (disk, tape, CD-ROM)
 #
-# CONFIG_ATA is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
 #
-# Multi-device support (RAID and LVM)
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
-# CONFIG_MD is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
 #
-# Fusion MPT device support
+# SCSI Transports
 #
-# CONFIG_FUSION is not set
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
 #
-# IEEE 1394 (FireWire) support
+# SCSI low-level drivers
 #
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+# CONFIG_PATA_PLATFORM is not set
+CONFIG_PATA_BF54X=y
+CONFIG_PATA_BF54X_DMA=y
 #
-# I2O device support
+# Multi-device support (RAID and LVM)
 #
+# CONFIG_MD is not set
 #
 # Network device support
@@ -629,10 +683,6 @@ CONFIG_NETDEVICES=y
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-#
-# PHY device support
-#
 # CONFIG_PHYLIB is not set
 #
@@ -641,28 +691,16 @@ CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 # CONFIG_SMC91X is not set
-# CONFIG_SMSC911X is not set
+CONFIG_SMSC911X=y
+# CONFIG_DM9000 is not set
-#
+CONFIG_NETDEV_1000=y
-# Ethernet (1000 Mbit)
+CONFIG_NETDEV_10000=y
-#
-#
-# Ethernet (10000 Mbit)
-#
 #
-# Token Ring devices
+# Wireless LAN
-#
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-#
-# Wan interfaces
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -686,6 +724,7 @@ CONFIG_MII=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 #
 # Userland interfaces
@@ -702,10 +741,17 @@ CONFIG_INPUT=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
 # CONFIG_INPUT_UINPUT is not set
 # CONFIG_BF53X_PFBUTTONS is not set
+# CONFIG_TWI_KEYPAD is not set
 #
 # Hardware I/O ports
@@ -718,12 +764,15 @@ CONFIG_INPUT_MISC=y
 #
 # CONFIG_AD9960 is not set
 # CONFIG_SPI_ADC_BF533 is not set
-# CONFIG_BF5xx_PFLAGS is not set
+# CONFIG_BFIN_PFLAGS is not set
 # CONFIG_BF5xx_PPIFCD is not set
 # CONFIG_BF5xx_TIMERS is not set
 # CONFIG_BF5xx_PPI is not set
 # CONFIG_BFIN_SPORT is not set
 # CONFIG_BFIN_TIMER_LATENCY is not set
+# CONFIG_TWI_LCD is not set
+# CONFIG_AD5304 is not set
+# CONFIG_BF5xx_TEA5764 is not set
 # CONFIG_BF5xx_FBDMA is not set
 # CONFIG_VT is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
@@ -760,14 +809,9 @@ CONFIG_UNIX98_PTYS=y
 # IPMI
 #
 # CONFIG_IPMI_HANDLER is not set
-#
-# Watchdog Cards
-#
 # CONFIG_WATCHDOG is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
@@ -775,32 +819,114 @@ CONFIG_HW_RANDOM=y
 # TPM devices
 #
 # CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
 #
-# I2C support
+# I2C Hardware Bus support
 #
-# CONFIG_I2C is not set
+# CONFIG_I2C_BLACKFIN_GPIO is not set
+CONFIG_I2C_BLACKFIN_TWI=y
+CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_AD5252 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCF8575 is not set
+# CONFIG_SENSORS_PCA9543 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
 #
 # SPI support
 #
-# CONFIG_SPI is not set
+CONFIG_SPI=y
-# CONFIG_SPI_MASTER is not set
+CONFIG_SPI_MASTER=y
 #
-# Dallas's 1-wire bus
+# SPI Master Controller Drivers
 #
-# CONFIG_W1 is not set
+CONFIG_SPI_BFIN=y
+# CONFIG_SPI_BITBANG is not set
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
 #
-# Hardware Monitoring support
+# Dallas's 1-wire bus
 #
+# CONFIG_W1 is not set
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
 # CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
 # CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
 #
@@ -812,16 +938,19 @@ CONFIG_HWMON=y
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
 #
-# Digital Video Broadcasting Devices
+# Graphics support
 #
-# CONFIG_DVB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 #
-# Graphics support
+# Display device support
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
 # CONFIG_FB is not set
 #
@@ -844,6 +973,10 @@ CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB is not set
 #
+# Enable Host or Gadget support to see Inventra options
+#
+#
 # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
@@ -851,11 +984,20 @@ CONFIG_USB_ARCH_HAS_HCD=y
 # USB Gadget Support
 #
 # CONFIG_USB_GADGET is not set
+CONFIG_MMC=m
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=m
 #
-# MMC/SD Card support
+# MMC/SD Host Controller Drivers
 #
-# CONFIG_MMC is not set
+CONFIG_SDH_BFIN=m
+# CONFIG_SPI_MMC is not set
 #
 # LED devices
@@ -894,15 +1036,37 @@ CONFIG_RTC_INTF_SYSFS=y
 CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 #
-# RTC drivers
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+#
+# Platform RTC drivers
 #
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_TEST is not set
 # CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
 CONFIG_RTC_DRV_BFIN=y
 #
@@ -919,14 +1083,6 @@ CONFIG_RTC_DRV_BFIN=y
 #
 #
-# Auxiliary Display support
-#
-#
-# Virtualization
-#
-#
 # PBX support
 #
 # CONFIG_PBX is not set
@@ -991,8 +1147,25 @@ CONFIG_RAMFS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_YAFFS_FS is not set
+CONFIG_YAFFS_FS=m
-# CONFIG_JFFS2_FS is not set
+CONFIG_YAFFS_YAFFS1=y
+# CONFIG_YAFFS_DOES_ECC is not set
+CONFIG_YAFFS_YAFFS2=y
+CONFIG_YAFFS_AUTO_YAFFS2=y
+# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set
+CONFIG_YAFFS_CHECKPOINT_RESERVED_BLOCKS=10
+# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set
+# CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set
+CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y
+CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_HPFS_FS is not set
@@ -1040,36 +1213,20 @@ CONFIG_MSDOS_PARTITION=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_MAGIC_SYSRQ=y
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_KERNEL is not set
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MMRS=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_LIST is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_FAULT_INJECTION is not set
-CONFIG_DEBUG_HWERR=y
-# CONFIG_DEBUG_ICACHE_CHECK is not set
-# CONFIG_DEBUG_KERNEL_START is not set
-# CONFIG_DEBUG_SERIAL_EARLY_INIT is not set
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
+CONFIG_DEBUG_BFIN_HWTRACE_ON=y
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
+# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
@@ -1092,9 +1249,12 @@ CONFIG_SECURITY_CAPABILITIES=y
 CONFIG_BITREVERSE=y
 # CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=m
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index 51c0b6f97798..85e647f87759 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21.5
+# Linux kernel version: 2.6.22.6
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -15,8 +15,9 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 # CONFIG_GENERIC_TIME is not set
-CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_IRQCHIP_DEMUX_GPIO=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -40,7 +41,9 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_TASKSTATS is not set
 # CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
 CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
 CONFIG_BLK_DEV_INITRD=y
@@ -58,15 +61,20 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
-CONFIG_BUDDY=y
 # CONFIG_NP2 is not set
 CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
 #
 # Loadable module support
@@ -229,19 +237,17 @@ CONFIG_IRQ_WDTIMER=13
 # CONFIG_CMDLINE_BOOL is not set
 #
-# Board Setup
+# Clock/PLL Setup
 #
 CONFIG_CLKIN_HZ=30000000
-CONFIG_MEM_SIZE=64
+# CONFIG_BFIN_KERNEL_CLOCK is not set
-CONFIG_MEM_ADD_WIDTH=9
+CONFIG_MAX_VCO_HZ=600000000
-CONFIG_BOOT_LOAD=0x1000
+CONFIG_MIN_VCO_HZ=50000000
+CONFIG_MAX_SCLK_HZ=133000000
-#
+CONFIG_MIN_SCLK_HZ=27000000
-# Blackfin Kernel Optimizations
-#
 #
-# Timer Tick
+# Kernel Timer/Scheduler
 #
 # CONFIG_HZ_100 is not set
 CONFIG_HZ_250=y
@@ -250,6 +256,20 @@ CONFIG_HZ_250=y
 CONFIG_HZ=250
 #
+# Memory Setup
+#
+CONFIG_MEM_SIZE=64
+CONFIG_MEM_ADD_WIDTH=9
+CONFIG_BOOT_LOAD=0x1000
+CONFIG_BFIN_SCRATCH_REG_RETN=y
+# CONFIG_BFIN_SCRATCH_REG_RETE is not set
+# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
+#
+# Blackfin Kernel Optimizations
+#
+#
 # Memory Optimizations
 #
 CONFIG_I_ENTRY_L1=y
@@ -288,20 +308,15 @@ CONFIG_DMA_UNCACHED_1M=y
 #
 # Cache Support
 #
-CONFIG_BLKFIN_CACHE=y
+CONFIG_BFIN_ICACHE=y
-CONFIG_BLKFIN_DCACHE=y
+CONFIG_BFIN_DCACHE=y
-# CONFIG_BLKFIN_DCACHE_BANKA is not set
+# CONFIG_BFIN_DCACHE_BANKA is not set
-# CONFIG_BLKFIN_CACHE_LOCK is not set
+# CONFIG_BFIN_ICACHE_LOCK is not set
-# CONFIG_BLKFIN_WB is not set
+# CONFIG_BFIN_WB is not set
-CONFIG_BLKFIN_WT=y
+CONFIG_BFIN_WT=y
 CONFIG_L1_MAX_PIECE=16
 #
-# Clock Settings
-#
-# CONFIG_BFIN_KERNEL_CLOCK is not set
-#
 # Asynchonous Memory Configuration
 #
@@ -326,12 +341,13 @@ CONFIG_C_AMBEN_ALL=y
 CONFIG_BANK_0=0x7BB0
 CONFIG_BANK_1=0x7BB0
 CONFIG_BANK_2=0x7BB0
-CONFIG_BANK_3=0x99B3
+CONFIG_BANK_3=0xAAC3
 #
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
 # CONFIG_PCI is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 #
 # PCCARD (PCMCIA/CardBus) support
@@ -339,10 +355,6 @@ CONFIG_BANK_3=0x99B3
 # CONFIG_PCCARD is not set
 #
-# PCI Hotplug Support
-#
-#
 # Executable file formats
 #
 CONFIG_BINFMT_ELF_FDPIC=y
@@ -364,7 +376,6 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -405,20 +416,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -485,7 +484,16 @@ CONFIG_IRTTY_SIR=m
 # FIR device drivers
 #
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
 #
 # Device Drivers
@@ -503,10 +511,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # Connector - unified userspace <-> kernelspace linker
 #
 # CONFIG_CONNECTOR is not set
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -550,7 +554,6 @@ CONFIG_MTD_MW320D=m
 CONFIG_MTD_RAM=y
 CONFIG_MTD_ROM=m
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 #
 # Mapping drivers for chip access
@@ -588,16 +591,13 @@ CONFIG_BFIN_FLASH_BANK_3=0x7BB0
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
 #
-# OneNAND Flash Device Drivers
+# UBI - Unsorted block images
 #
-# CONFIG_MTD_ONENAND is not set
+# CONFIG_MTD_UBI is not set
 #
 # Parallel port support
@@ -625,10 +625,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 #
 # Misc devices
 #
-#
-# ATA/ATAPI/MFM/RLL support
-#
 # CONFIG_IDE is not set
 #
@@ -637,10 +633,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
 # CONFIG_SCSI_NETLINK is not set
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
 #
@@ -649,19 +641,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_MD is not set
 #
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-#
-# IEEE 1394 (FireWire) support
-#
-#
-# I2O device support
-#
-#
 # Network device support
 #
 CONFIG_NETDEVICES=y
@@ -669,10 +648,6 @@ CONFIG_NETDEVICES=y
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-#
-# PHY device support
-#
 # CONFIG_PHYLIB is not set
 #
@@ -682,27 +657,15 @@ CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
 CONFIG_SMC91X=y
 # CONFIG_SMSC911X is not set
+# CONFIG_DM9000 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
 #
-# Ethernet (1000 Mbit)
+# Wireless LAN
-#
-#
-# Ethernet (10000 Mbit)
-#
-#
-# Token Ring devices
-#
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-#
-# Wan interfaces
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -726,6 +689,7 @@ CONFIG_SMC91X=y
 #
 CONFIG_INPUT=m
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 #
 # Userland interfaces
@@ -742,6 +706,7 @@ CONFIG_INPUT_EVDEV=m
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
@@ -756,7 +721,7 @@ CONFIG_INPUT_EVDEV=m
 #
 # CONFIG_AD9960 is not set
 # CONFIG_SPI_ADC_BF533 is not set
-# CONFIG_BF5xx_PFLAGS is not set
+# CONFIG_BFIN_PFLAGS is not set
 # CONFIG_BF5xx_PPIFCD is not set
 # CONFIG_BF5xx_TIMERS is not set
 # CONFIG_BF5xx_PPI is not set
@@ -796,10 +761,6 @@ CONFIG_UNIX98_PTYS=y
 # IPMI
 #
 # CONFIG_IPMI_HANDLER is not set
-#
-# Watchdog Cards
-#
 CONFIG_WATCHDOG=y
 # CONFIG_WATCHDOG_NOWAYOUT is not set
@@ -810,7 +771,6 @@ CONFIG_WATCHDOG=y
 CONFIG_BFIN_WDT=y
 CONFIG_HW_RANDOM=y
 # CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
@@ -818,10 +778,6 @@ CONFIG_HW_RANDOM=y
 # TPM devices
 #
 # CONFIG_TCG_TPM is not set
-#
-# I2C support
-#
 # CONFIG_I2C is not set
 #
@@ -840,22 +796,22 @@ CONFIG_SPI_BFIN=y
 # SPI Protocol Masters
 #
 # CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
 #
 # Dallas's 1-wire bus
 #
 # CONFIG_W1 is not set
-#
-# Hardware Monitoring support
-#
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
 # CONFIG_SENSORS_ABITUGURU is not set
 # CONFIG_SENSORS_F71805F is not set
 # CONFIG_SENSORS_LM70 is not set
 # CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
 # CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83627HF is not set
 # CONFIG_HWMON_DEBUG_CHIP is not set
 #
@@ -867,16 +823,19 @@ CONFIG_HWMON=y
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
 #
-# Digital Video Broadcasting Devices
+# Graphics support
 #
-# CONFIG_DVB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 #
-# Graphics support
+# Display device support
 #
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
 # CONFIG_FB is not set
 #
@@ -899,18 +858,17 @@ CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB is not set
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# Enable Host or Gadget support to see Inventra options
 #
 #
-# USB Gadget Support
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
-# CONFIG_USB_GADGET is not set
 #
-# MMC/SD Card support
+# USB Gadget Support
 #
-# CONFIG_SPI_MMC is not set
+# CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
 #
@@ -953,14 +911,6 @@ CONFIG_USB_ARCH_HAS_HCD=y
 #
 #
-# Auxiliary Display support
-#
-#
-# Virtualization
-#
-#
 # PBX support
 #
 # CONFIG_PBX is not set
@@ -1060,6 +1010,7 @@ CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
+# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1137,14 +1088,20 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_SERIAL_EARLY_INIT is not set
+CONFIG_DEBUG_MMRS=y
 CONFIG_DEBUG_HUNT_FOR_ZERO=y
+CONFIG_DEBUG_BFIN_HWTRACE_ON=y
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
+# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
+CONFIG_EARLY_PRINTK=y
 # CONFIG_DUAL_CORE_TEST_MODULE is not set
 CONFIG_CPLB_INFO=y
 CONFIG_ACCESS_CHECK=y
@@ -1168,6 +1125,7 @@ CONFIG_SECURITY_CAPABILITIES=m
 CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
@@ -1175,3 +1133,4 @@ CONFIG_ZLIB_DEFLATE=m
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/blackfin/configs/PNAV-10_defconfig b/arch/blackfin/configs/PNAV-10_defconfig
index 983ed181c896..15e36aaf2186 100644
--- a/arch/blackfin/configs/PNAV-10_defconfig
+++ b/arch/blackfin/configs/PNAV-10_defconfig
@@ -1,6 +1,6 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21.5
+# Linux kernel version: 2.6.22.6
 #
 # CONFIG_MMU is not set
 # CONFIG_FPU is not set
@@ -15,8 +15,9 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 # CONFIG_GENERIC_TIME is not set
-CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_GPIO=y
 CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_IRQCHIP_DEMUX_GPIO=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -41,6 +42,7 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
 # CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
 CONFIG_SYSFS_DEPRECATED=y
 # CONFIG_RELAY is not set
 # CONFIG_BLK_DEV_INITRD is not set
@@ -57,15 +59,20 @@ CONFIG_BUG=y
 CONFIG_ELF_CORE=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=9
-CONFIG_BUDDY=y
 # CONFIG_NP2 is not set
 CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
 CONFIG_RT_MUTEXES=y
 CONFIG_TINY_SHMEM=y
 CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
 #
 # Loadable module support
@@ -147,13 +154,6 @@ CONFIG_IRQ_PLL_WAKEUP=7
 #
 #
-# PORT F/G Selection
-#
-CONFIG_BF537_PORT_F=y
-# CONFIG_BF537_PORT_G is not set
-# CONFIG_BF537_PORT_H is not set
-#
 # Interrupt Priority Assignment
 #
@@ -198,19 +198,17 @@ CONFIG_IRQ_WATCH=13
 # CONFIG_CMDLINE_BOOL is not set
 #
-# Board Setup
+# Clock/PLL Setup
 #
 CONFIG_CLKIN_HZ=24576000
-CONFIG_MEM_SIZE=64
+# CONFIG_BFIN_KERNEL_CLOCK is not set
-CONFIG_MEM_ADD_WIDTH=10
+CONFIG_MAX_VCO_HZ=600000000
-CONFIG_BOOT_LOAD=0x1000
+CONFIG_MIN_VCO_HZ=50000000
+CONFIG_MAX_SCLK_HZ=133000000
-#
+CONFIG_MIN_SCLK_HZ=27000000
-# Blackfin Kernel Optimizations
-#
 #
-# Timer Tick
+# Kernel Timer/Scheduler
 #
 # CONFIG_HZ_100 is not set
 CONFIG_HZ_250=y
@@ -219,6 +217,20 @@ CONFIG_HZ_250=y
 CONFIG_HZ=250
 #
+# Memory Setup
+#
+CONFIG_MEM_SIZE=64
+CONFIG_MEM_ADD_WIDTH=10
+CONFIG_BOOT_LOAD=0x1000
+CONFIG_BFIN_SCRATCH_REG_RETN=y
+# CONFIG_BFIN_SCRATCH_REG_RETE is not set
+# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
+#
+# Blackfin Kernel Optimizations
+#
+#
 # Memory Optimizations
 #
 CONFIG_I_ENTRY_L1=y
@@ -257,20 +269,15 @@ CONFIG_DMA_UNCACHED_1M=y
 #
 # Cache Support
 #
-CONFIG_BLKFIN_CACHE=y
+CONFIG_BFIN_ICACHE=y
-CONFIG_BLKFIN_DCACHE=y
+CONFIG_BFIN_DCACHE=y
-# CONFIG_BLKFIN_DCACHE_BANKA is not set
+# CONFIG_BFIN_DCACHE_BANKA is not set
-# CONFIG_BLKFIN_CACHE_LOCK is not set
+# CONFIG_BFIN_ICACHE_LOCK is not set
-CONFIG_BLKFIN_WB=y
+CONFIG_BFIN_WB=y
-# CONFIG_BLKFIN_WT is not set
+# CONFIG_BFIN_WT is not set
 CONFIG_L1_MAX_PIECE=16
 #
-# Clock Settings
-#
-# CONFIG_BFIN_KERNEL_CLOCK is not set
-#
 # Asynchonous Memory Configuration
 #
@@ -297,6 +304,7 @@ CONFIG_BANK_3=0x99B3
 # Bus options (PCI, PCMCIA, EISA, MCA, ISA)
 #
 # CONFIG_PCI is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 #
 # PCCARD (PCMCIA/CardBus) support
@@ -304,10 +312,6 @@ CONFIG_BANK_3=0x99B3
 # CONFIG_PCCARD is not set
 #
-# PCI Hotplug Support
-#
-#
 # Executable file formats
 #
 CONFIG_BINFMT_ELF_FDPIC=y
@@ -334,7 +338,6 @@ CONFIG_NET=y
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
@@ -375,20 +378,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_NETLABEL is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_DCCP is not set
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
@@ -414,7 +405,16 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_HAMRADIO is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
 # CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
 #
 # Device Drivers
@@ -432,10 +432,6 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
 # Connector - unified userspace <-> kernelspace linker
 #
 # CONFIG_CONNECTOR is not set
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_CONCAT is not set
@@ -473,7 +469,6 @@ CONFIG_MTD_CFI_I2=y
 CONFIG_MTD_RAM=y
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 #
 # Mapping drivers for chip access
@@ -499,13 +494,10 @@ CONFIG_MTD_UCLINUX=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-#
-# NAND Flash Device Drivers
-#
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_BFIN=y
 CONFIG_BFIN_NAND_BASE=0x20100000
 CONFIG_BFIN_NAND_CLE=2
@@ -514,11 +506,13 @@ CONFIG_BFIN_NAND_READY=44
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
 #
-# OneNAND Flash Device Drivers
+# UBI - Unsorted block images
 #
-# CONFIG_MTD_ONENAND is not set
+# CONFIG_MTD_UBI is not set
 #
 # Parallel port support
@@ -546,10 +540,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 #
 # Misc devices
 #
-#
-# ATA/ATAPI/MFM/RLL support
-#
 # CONFIG_IDE is not set
 #
@@ -558,10 +548,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
 # CONFIG_SCSI_NETLINK is not set
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
 #
@@ -570,19 +556,6 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
 # CONFIG_MD is not set
 #
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-#
-# IEEE 1394 (FireWire) support
-#
-#
-# I2O device support
-#
-#
 # Network device support
 #
 CONFIG_NETDEVICES=y
@@ -590,11 +563,20 @@ CONFIG_NETDEVICES=y
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+CONFIG_PHYLIB=y
 #
-# PHY device support
+# MII PHY device drivers
 #
-# CONFIG_PHYLIB is not set
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_FIXED_PHY is not set
 #
 # Ethernet (10 or 100Mbit)
@@ -608,27 +590,15 @@ CONFIG_BFIN_TX_DESC_NUM=100
 CONFIG_BFIN_RX_DESC_NUM=100
 CONFIG_BFIN_MAC_RMII=y
 # CONFIG_SMSC911X is not set
+# CONFIG_DM9000 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
 #
-# Ethernet (1000 Mbit)
+# Wireless LAN
-#
-#
-# Ethernet (10000 Mbit)
-#
-#
-# Token Ring devices
-#
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-#
-# Wan interfaces
 #
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -652,6 +622,7 @@ CONFIG_BFIN_MAC_RMII=y
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
 #
 # Userland interfaces
@@ -670,6 +641,7 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_ADS7846 is not set
 CONFIG_TOUCHSCREEN_AD7877=y
@@ -681,7 +653,13 @@ CONFIG_TOUCHSCREEN_AD7877=y
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
 # CONFIG_TOUCHSCREEN_UCB1400 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
 CONFIG_INPUT_UINPUT=y
 # CONFIG_BF53X_PFBUTTONS is not set
 # CONFIG_TWI_KEYPAD is not set
@@ -697,7 +675,7 @@ CONFIG_INPUT_UINPUT=y
 #
 # CONFIG_AD9960 is not set
 # CONFIG_SPI_ADC_BF533 is not set
-# CONFIG_BF5xx_PFLAGS is not set
+# CONFIG_BFIN_PFLAGS is not set
 # CONFIG_BF5xx_PPIFCD is not set
 # CONFIG_BF5xx_TIMERS is not set
 # CONFIG_BF5xx_PPI is not set
@@ -749,14 +727,9 @@ CONFIG_CAN_BLACKFIN=m
 # IPMI
 #
 # CONFIG_IPMI_HANDLER is not set
-#
-# Watchdog Cards
-#
 # CONFIG_WATCHDOG is not set
 CONFIG_HW_RANDOM=y
 # CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
@@ -764,11 +737,8 @@ CONFIG_HW_RANDOM=y
 # TPM devices
 #
 # CONFIG_TCG_TPM is not set
-#
-# I2C support
-#
 CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 #
@@ -784,10 +754,11 @@ CONFIG_I2C_CHARDEV=y
 # CONFIG_I2C_BLACKFIN_GPIO is not set
 CONFIG_I2C_BLACKFIN_TWI=y
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=50
+# CONFIG_I2C_GPIO is not set
 # CONFIG_I2C_OCORES is not set
 # CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
 # CONFIG_I2C_STUB is not set
-# CONFIG_I2C_PCA_ISA is not set
 #
 # Miscellaneous I2C Chip support
@@ -823,18 +794,16 @@ CONFIG_SPI_BFIN=y
 # SPI Protocol Masters
 #
 # CONFIG_SPI_AT25 is not set
+# CONFIG_SPI_SPIDEV is not set
 #
 # Dallas's 1-wire bus
 #
 # CONFIG_W1 is not set
-#
-# Hardware Monitoring support
-#
 CONFIG_HWMON=y
 # CONFIG_HWMON_VID is not set
 # CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_AD7418 is not set
 # CONFIG_SENSORS_ADM1021 is not set
 # CONFIG_SENSORS_ADM1025 is not set
 # CONFIG_SENSORS_ADM1026 is not set
@@ -862,6 +831,7 @@ CONFIG_HWMON=y
 # CONFIG_SENSORS_LM90 is not set
 # CONFIG_SENSORS_LM92 is not set
 # CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
 # CONFIG_SENSORS_PC87360 is not set
 # CONFIG_SENSORS_PC87427 is not set
 # CONFIG_SENSORS_SMSC47M1 is not set
@@ -886,11 +856,8 @@ CONFIG_HWMON=y
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
-#
+CONFIG_DAB=y
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
 #
 # Graphics support
@@ -898,12 +865,23 @@ CONFIG_HWMON=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_LCD_CLASS_DEVICE=y
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_VGASTATE is not set
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 # CONFIG_FB_DDC is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
@@ -921,10 +899,6 @@ CONFIG_FB_BFIN_LANDSCAPE=y
 # CONFIG_FB_BFIN_BGR is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_VIRTUAL is not set
-#
-# Logo configuration
-#
 # CONFIG_LOGO is not set
 #
@@ -936,8 +910,6 @@ CONFIG_SOUND=y
 # Advanced Linux Sound Architecture
 #
 CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
 # CONFIG_SND_SEQUENCER is not set
 # CONFIG_SND_MIXER_OSS is not set
 # CONFIG_SND_PCM_OSS is not set
@@ -959,19 +931,23 @@ CONFIG_SND_PCM=m
 # ALSA Blackfin devices
 #
 # CONFIG_SND_BLACKFIN_AD1836 is not set
-CONFIG_SND_BLACKFIN_AD1981B=m
 # CONFIG_SND_BFIN_AD73311 is not set
 #
-# SoC audio support
+# System on Chip audio support
 #
 # CONFIG_SND_SOC is not set
 #
+# SoC Audio for the ADI Blackfin
+#
+# CONFIG_SND_BF5XX_HAVE_COLD_RESET is not set
+#
 # Open Sound System
 #
 CONFIG_SOUND_PRIME=y
-# CONFIG_OBSOLETE_OSS is not set
+# CONFIG_OSS_OBSOLETE is not set
 # CONFIG_SOUND_MSNDCLAS is not set
 # CONFIG_SOUND_MSNDPIN is not set
@@ -989,18 +965,17 @@ CONFIG_USB_ARCH_HAS_HCD=y
 # CONFIG_USB is not set
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# Enable Host or Gadget support to see Inventra options
 #
 #
-# USB Gadget Support
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
 #
-# CONFIG_USB_GADGET is not set
 #
-# MMC/SD Card support
+# USB Gadget Support
 #
-# CONFIG_SPI_MMC is not set
+# CONFIG_USB_GADGET is not set
 # CONFIG_MMC is not set
 #
@@ -1040,44 +1015,50 @@ CONFIG_RTC_INTF_SYSFS=y
 CONFIG_RTC_INTF_PROC=y
 CONFIG_RTC_INTF_DEV=y
 # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 #
-# RTC drivers
+# I2C RTC drivers
 #
-# CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
 # CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
 # CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+#
+# SPI RTC drivers
+#
 # CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_TEST is not set
 # CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-CONFIG_RTC_DRV_BFIN=y
 #
-# DMA Engine support
+# Platform RTC drivers
 #
-# CONFIG_DMA_ENGINE is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 #
-# DMA Clients
+# on-CPU RTC drivers
 #
+CONFIG_RTC_DRV_BFIN=y
 #
-# DMA Devices
+# DMA Engine support
 #
+# CONFIG_DMA_ENGINE is not set
 #
-# Auxiliary Display support
+# DMA Clients
 #
 #
-# Virtualization
+# DMA Devices
 #
 #
@@ -1176,6 +1157,7 @@ CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
+# CONFIG_SUNRPC_BIND34 is not set
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 CONFIG_SMB_FS=m
@@ -1256,11 +1238,17 @@ CONFIG_ENABLE_MUST_CHECK=y
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
 # CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_SERIAL_EARLY_INIT is not set
+# CONFIG_DEBUG_MMRS is not set
 # CONFIG_DEBUG_HUNT_FOR_ZERO is not set
+CONFIG_DEBUG_BFIN_HWTRACE_ON=y
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_OFF=y
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE is not set
+# CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_TWO is not set
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION=0
+# CONFIG_DEBUG_BFIN_HWTRACE_EXPAND is not set
 # CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
+# CONFIG_EARLY_PRINTK is not set
 # CONFIG_CPLB_INFO is not set
 # CONFIG_ACCESS_CHECK is not set
@@ -1283,9 +1271,11 @@ CONFIG_SECURITY_CAPABILITIES=y
 CONFIG_BITREVERSE=y
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index f429ebc3a961..8aeb6066b19b 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -7,11 +7,10 @@ extra-y := init_task.o vmlinux.lds
 obj-y := \
        entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
        sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \
-        fixed_code.o cplbinit.o cacheinit.o
+        fixed_code.o cplbinit.o cacheinit.o reboot.o bfin_gpio.o
-obj-$(CONFIG_BF53x)                  += bfin_gpio.o
-obj-$(CONFIG_BF561)                  += bfin_gpio.o
 obj-$(CONFIG_MODULES)                += module.o
 obj-$(CONFIG_BFIN_DMA_5XX)           += bfin_dma_5xx.o
 obj-$(CONFIG_DUAL_CORE_TEST_MODULE)  += dualcore_test.o
 obj-$(CONFIG_KGDB)                   += kgdb.o
+obj-$(CONFIG_EARLY_PRINTK)           += early_printk.o
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 7cf02f02a1db..e19164fb4cd1 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -73,6 +73,11 @@ static int __init blackfin_dma_init(void)
        /* Mark MEMDMA Channel 0 as requested since we're using it internally */
        dma_ch[CH_MEM_STREAM0_DEST].chan_status = DMA_CHANNEL_REQUESTED;
        dma_ch[CH_MEM_STREAM0_SRC].chan_status = DMA_CHANNEL_REQUESTED;
+#if defined(CONFIG_DEB_DMA_URGENT)
+        bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
+                         | DEB1_URGENT | DEB2_URGENT | DEB3_URGENT);
+#endif
        return 0;
 }
@@ -265,10 +270,23 @@ void set_dma_next_desc_addr(unsigned int channel, unsigned long addr)
        dma_ch[channel].regs->next_desc_ptr = addr;
        SSYNC();
-        pr_debug("set_dma_start_addr() : END\n");
+        pr_debug("set_dma_next_desc_addr() : END\n");
 }
 EXPORT_SYMBOL(set_dma_next_desc_addr);
+void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr)
+{
+        pr_debug("set_dma_curr_desc_addr() : BEGIN \n");
+        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
+               && channel < MAX_BLACKFIN_DMA_CHANNEL));
+        dma_ch[channel].regs->curr_desc_ptr = addr;
+        SSYNC();
+        pr_debug("set_dma_curr_desc_addr() : END\n");
+}
+EXPORT_SYMBOL(set_dma_curr_desc_addr);
 void set_dma_x_count(unsigned int channel, unsigned short x_count)
 {
        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
@@ -345,6 +363,16 @@ void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg)
 }
 EXPORT_SYMBOL(set_dma_sg);
+void set_dma_curr_addr(unsigned int channel, unsigned long addr)
+{
+        BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
+               && channel < MAX_BLACKFIN_DMA_CHANNEL));
+        dma_ch[channel].regs->curr_addr_ptr = addr;
+        SSYNC();
+}
+EXPORT_SYMBOL(set_dma_curr_addr);
 /*------------------------------------------------------------------------------
 *      Get the DMA status of a specific DMA channel from the system.
 *-----------------------------------------------------------------------------*/
@@ -408,6 +436,10 @@ static void *__dma_memcpy(void *dest, const void *src, size_t size)
                blackfin_dcache_flush_range((unsigned int)src,
                                            (unsigned int)(src + size));
+        if ((unsigned long)dest < memory_end)
+                blackfin_dcache_invalidate_range((unsigned int)dest,
+                                                 (unsigned int)(dest + size));
        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
        if ((unsigned long)src < (unsigned long)dest)
@@ -515,6 +547,8 @@ static void *__dma_memcpy(void *dest, const void *src, size_t size)
                }
        }
+        SSYNC();
        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
                ;
@@ -524,9 +558,6 @@ static void *__dma_memcpy(void *dest, const void *src, size_t size)
        bfin_write_MDMA_S0_CONFIG(0);
        bfin_write_MDMA_D0_CONFIG(0);
-        if ((unsigned long)dest < memory_end)
-                blackfin_dcache_invalidate_range((unsigned int)dest,
-                                                 (unsigned int)(dest + size));
        local_irq_restore(flags);
        return dest;
@@ -555,13 +586,14 @@ void *safe_dma_memcpy(void *dest, const void *src, size_t size)
 }
 EXPORT_SYMBOL(safe_dma_memcpy);
-void dma_outsb(void __iomem *addr, const void *buf, unsigned short len)
+void dma_outsb(unsigned long addr, const void *buf, unsigned short len)
 {
        unsigned long flags;
        local_irq_save(flags);
-        blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
+        blackfin_dcache_flush_range((unsigned int)buf,
+                         (unsigned int)(buf) + len);
        bfin_write_MDMA_D0_START_ADDR(addr);
        bfin_write_MDMA_D0_X_COUNT(len);
@@ -576,6 +608,8 @@ void dma_outsb(void __iomem *addr, const void *buf, unsigned short len)
        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
+        SSYNC();
        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -588,10 +622,13 @@ void dma_outsb(void __iomem *addr, const void *buf, unsigned short len)
 EXPORT_SYMBOL(dma_outsb);
-void dma_insb(const void __iomem *addr, void *buf, unsigned short len)
+void dma_insb(unsigned long addr, void *buf, unsigned short len)
 {
        unsigned long flags;
+        blackfin_dcache_invalidate_range((unsigned int)buf,
+                         (unsigned int)(buf) + len);
        local_irq_save(flags);
        bfin_write_MDMA_D0_START_ADDR(buf);
        bfin_write_MDMA_D0_X_COUNT(len);
@@ -606,7 +643,7 @@ void dma_insb(const void __iomem *addr, void *buf, unsigned short len)
        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
-        blackfin_dcache_invalidate_range((unsigned int)buf, (unsigned int)(buf) + len);
+        SSYNC();
        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
@@ -619,13 +656,14 @@ void dma_insb(const void __iomem *addr, void *buf, unsigned short len)
 }
 EXPORT_SYMBOL(dma_insb);
-void dma_outsw(void __iomem *addr, const void  *buf, unsigned short len)
+void dma_outsw(unsigned long addr, const void  *buf, unsigned short len)
 {
        unsigned long flags;
        local_irq_save(flags);
-        blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
+        blackfin_dcache_flush_range((unsigned int)buf,
+                         (unsigned int)(buf) + len * sizeof(short));
        bfin_write_MDMA_D0_START_ADDR(addr);
        bfin_write_MDMA_D0_X_COUNT(len);
@@ -640,6 +678,8 @@ void dma_outsw(void __iomem *addr, const void  *buf, unsigned short len)
        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
+        SSYNC();
        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -651,10 +691,13 @@ void dma_outsw(void __iomem *addr, const void  *buf, unsigned short len)
 }
 EXPORT_SYMBOL(dma_outsw);
-void dma_insw(const void __iomem *addr, void *buf, unsigned short len)
+void dma_insw(unsigned long addr, void *buf, unsigned short len)
 {
        unsigned long flags;
+        blackfin_dcache_invalidate_range((unsigned int)buf,
+                         (unsigned int)(buf) + len * sizeof(short));
        local_irq_save(flags);
        bfin_write_MDMA_D0_START_ADDR(buf);
@@ -670,7 +713,7 @@ void dma_insw(const void __iomem *addr, void *buf, unsigned short len)
        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
-        blackfin_dcache_invalidate_range((unsigned int)buf, (unsigned int)(buf) + len);
+        SSYNC();
        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
@@ -683,13 +726,14 @@ void dma_insw(const void __iomem *addr, void *buf, unsigned short len)
 }
 EXPORT_SYMBOL(dma_insw);
-void dma_outsl(void __iomem *addr, const void *buf, unsigned short len)
+void dma_outsl(unsigned long addr, const void *buf, unsigned short len)
 {
        unsigned long flags;
        local_irq_save(flags);
-        blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
+        blackfin_dcache_flush_range((unsigned int)buf,
+                         (unsigned int)(buf) + len * sizeof(long));
        bfin_write_MDMA_D0_START_ADDR(addr);
        bfin_write_MDMA_D0_X_COUNT(len);
@@ -704,6 +748,8 @@ void dma_outsl(void __iomem *addr, const void *buf, unsigned short len)
        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);
+        SSYNC();
        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -715,10 +761,13 @@ void dma_outsl(void __iomem *addr, const void *buf, unsigned short len)
 }
 EXPORT_SYMBOL(dma_outsl);
-void dma_insl(const void __iomem *addr, void *buf, unsigned short len)
+void dma_insl(unsigned long addr, void *buf, unsigned short len)
 {
        unsigned long flags;
+        blackfin_dcache_invalidate_range((unsigned int)buf,
+                         (unsigned int)(buf) + len * sizeof(long));
        local_irq_save(flags);
        bfin_write_MDMA_D0_START_ADDR(buf);
@@ -734,7 +783,7 @@ void dma_insl(const void __iomem *addr, void *buf, unsigned short len)
        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
        bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);
-        blackfin_dcache_invalidate_range((unsigned int)buf, (unsigned int)(buf) + len);
+        SSYNC();
        while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 5d488ef965ce..3fe0cd49e8db 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -7,7 +7,7 @@
 * Description:  GPIO Abstraction Layer
 *
 * Modified:
- *               Copyright 2006 Analog Devices Inc.
+ *               Copyright 2007 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
@@ -28,9 +28,9 @@
 */
 /*
-*  Number     BF537/6/4    BF561    BF533/2/1
+*  Number     BF537/6/4    BF561    BF533/2/1      BF549/8/4/2
 *
-*  GPIO_0       PF0         PF0        PF0
+*  GPIO_0       PF0         PF0        PF0         PA0...PJ13
 *  GPIO_1       PF1         PF1        PF1
 *  GPIO_2       PF2         PF2        PF2
 *  GPIO_3       PF3         PF3        PF3
@@ -80,6 +80,7 @@
 *  GPIO_47      PH15        PF47
 */
+#include <linux/delay.h>
 #include <linux/module.h>
 #include <linux/err.h>
 #include <asm/blackfin.h>
@@ -87,6 +88,36 @@
 #include <asm/portmux.h>
 #include <linux/irq.h>
+#if ANOMALY_05000311 || ANOMALY_05000323
+enum {
+        AWA_data = SYSCR,
+        AWA_data_clear = SYSCR,
+        AWA_data_set = SYSCR,
+        AWA_toggle = SYSCR,
+        AWA_maska = UART_SCR,
+        AWA_maska_clear = UART_SCR,
+        AWA_maska_set = UART_SCR,
+        AWA_maska_toggle = UART_SCR,
+        AWA_maskb = UART_GCTL,
+        AWA_maskb_clear = UART_GCTL,
+        AWA_maskb_set = UART_GCTL,
+        AWA_maskb_toggle = UART_GCTL,
+        AWA_dir = SPORT1_STAT,
+        AWA_polar = SPORT1_STAT,
+        AWA_edge = SPORT1_STAT,
+        AWA_both = SPORT1_STAT,
+#if ANOMALY_05000311
+        AWA_inen = TIMER_ENABLE,
+#elif ANOMALY_05000323
+        AWA_inen = DMA1_1_CONFIG,
+#endif
+};
+        /* Anomaly Workaround */
+#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
+#else
+#define AWA_DUMMY_READ(...)  do { } while (0)
+#endif
 #ifdef BF533_FAMILY
 static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
        (struct gpio_port_t *) FIO_FLAG_D,
@@ -116,11 +147,31 @@ static struct gpio_port_t *gpio_bankb[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
 };
 #endif
+#ifdef BF548_FAMILY
+static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
+        (struct gpio_port_t *)PORTA_FER,
+        (struct gpio_port_t *)PORTB_FER,
+        (struct gpio_port_t *)PORTC_FER,
+        (struct gpio_port_t *)PORTD_FER,
+        (struct gpio_port_t *)PORTE_FER,
+        (struct gpio_port_t *)PORTF_FER,
+        (struct gpio_port_t *)PORTG_FER,
+        (struct gpio_port_t *)PORTH_FER,
+        (struct gpio_port_t *)PORTI_FER,
+        (struct gpio_port_t *)PORTJ_FER,
+};
+#endif
 static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
 static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS + 16)];
-char *str_ident = NULL;
-#define RESOURCE_LABEL_SIZE 16
+#define MAX_RESOURCES           256
+#define RESOURCE_LABEL_SIZE     16
+struct str_ident {
+        char name[RESOURCE_LABEL_SIZE];
+} *str_ident;
 #ifdef CONFIG_PM
 static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
@@ -141,21 +192,32 @@ static unsigned int sic_iwr_irqs[gpio_bank(MAX_BLACKFIN_GPIOS)] = {IRQ_PROG0_INT
 #endif /* CONFIG_PM */
+#if defined(BF548_FAMILY)
+inline int check_gpio(unsigned short gpio)
+{
+        if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
+            || gpio == GPIO_PH14 || gpio == GPIO_PH15
+            || gpio == GPIO_PJ14 || gpio == GPIO_PJ15
+            || gpio > MAX_BLACKFIN_GPIOS)
+                return -EINVAL;
+        return 0;
+}
+#else
 inline int check_gpio(unsigned short gpio)
 {
        if (gpio >= MAX_BLACKFIN_GPIOS)
                return -EINVAL;
        return 0;
 }
+#endif
 static void set_label(unsigned short ident, const char *label)
 {
        if (label && str_ident) {
-                strncpy(str_ident + ident * RESOURCE_LABEL_SIZE, label,
+                strncpy(str_ident[ident].name, label,
                         RESOURCE_LABEL_SIZE);
-                str_ident[ident * RESOURCE_LABEL_SIZE +
+                str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
-                         RESOURCE_LABEL_SIZE - 1] = 0;
        }
 }
@@ -164,14 +226,13 @@ static char *get_label(unsigned short ident)
        if (!str_ident)
                return "UNKNOWN";
-        return (str_ident[ident * RESOURCE_LABEL_SIZE] ?
+        return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
-                (str_ident + ident * RESOURCE_LABEL_SIZE) : "UNKNOWN");
 }
 static int cmp_label(unsigned short ident, const char *label)
 {
        if (label && str_ident)
-                return strncmp(str_ident + ident * RESOURCE_LABEL_SIZE,
+                return strncmp(str_ident[ident].name,
                                 label, strlen(label));
        else
                return -EINVAL;
@@ -181,50 +242,84 @@ static int cmp_label(unsigned short ident, const char *label)
 static void port_setup(unsigned short gpio, unsigned short usage)
 {
        if (!check_gpio(gpio)) {
-                if (usage == GPIO_USAGE) {
+                if (usage == GPIO_USAGE)
                        *port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
-                } else
+                else
                        *port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
                SSYNC();
        }
 }
+#elif defined(BF548_FAMILY)
+static void port_setup(unsigned short gpio, unsigned short usage)
+{
+        if (usage == GPIO_USAGE)
+                gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
+        else
+                gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
+        SSYNC();
+}
 #else
 # define port_setup(...)  do { } while (0)
 #endif
 #ifdef BF537_FAMILY
+static struct {
-#define PMUX_LUT_RES            0
+        unsigned short res;
-#define PMUX_LUT_OFFSET         1
+        unsigned short offset;
-#define PMUX_LUT_ENTRIES        41
+} port_mux_lut[] = {
-#define PMUX_LUT_SIZE           2
+        {.res = P_PPI0_D13, .offset = 11},
+        {.res = P_PPI0_D14, .offset = 11},
-static unsigned short port_mux_lut[PMUX_LUT_ENTRIES][PMUX_LUT_SIZE] = {
+        {.res = P_PPI0_D15, .offset = 11},
-        {P_PPI0_D13, 11}, {P_PPI0_D14, 11}, {P_PPI0_D15, 11},
+        {.res = P_SPORT1_TFS, .offset = 11},
-        {P_SPORT1_TFS, 11}, {P_SPORT1_TSCLK, 11}, {P_SPORT1_DTPRI, 11},
+        {.res = P_SPORT1_TSCLK, .offset = 11},
-        {P_PPI0_D10, 10}, {P_PPI0_D11, 10}, {P_PPI0_D12, 10},
+        {.res = P_SPORT1_DTPRI, .offset = 11},
-        {P_SPORT1_RSCLK, 10}, {P_SPORT1_RFS, 10}, {P_SPORT1_DRPRI, 10},
+        {.res = P_PPI0_D10, .offset = 10},
-        {P_PPI0_D8, 9}, {P_PPI0_D9, 9}, {P_SPORT1_DRSEC, 9},
+        {.res = P_PPI0_D11, .offset = 10},
-        {P_SPORT1_DTSEC, 9}, {P_TMR2, 8}, {P_PPI0_FS3, 8}, {P_TMR3, 7},
+        {.res = P_PPI0_D12, .offset = 10},
-        {P_SPI0_SSEL4, 7}, {P_TMR4, 6}, {P_SPI0_SSEL5, 6}, {P_TMR5, 5},
+        {.res = P_SPORT1_RSCLK, .offset = 10},
-        {P_SPI0_SSEL6, 5}, {P_UART1_RX, 4}, {P_UART1_TX, 4}, {P_TMR6, 4},
+        {.res = P_SPORT1_RFS, .offset = 10},
-        {P_TMR7, 4}, {P_UART0_RX, 3}, {P_UART0_TX, 3}, {P_DMAR0, 3},
+        {.res = P_SPORT1_DRPRI, .offset = 10},
-        {P_DMAR1, 3}, {P_SPORT0_DTSEC, 1}, {P_SPORT0_DRSEC, 1},
+        {.res = P_PPI0_D8, .offset = 9},
-        {P_CAN0_RX, 1}, {P_CAN0_TX, 1}, {P_SPI0_SSEL7, 1},
+        {.res = P_PPI0_D9, .offset = 9},
-        {P_SPORT0_TFS, 0}, {P_SPORT0_DTPRI, 0}, {P_SPI0_SSEL2, 0},
+        {.res = P_SPORT1_DRSEC, .offset = 9},
-        {P_SPI0_SSEL3, 0}
+        {.res = P_SPORT1_DTSEC, .offset = 9},
+        {.res = P_TMR2, .offset = 8},
+        {.res = P_PPI0_FS3, .offset = 8},
+        {.res = P_TMR3, .offset = 7},
+        {.res = P_SPI0_SSEL4, .offset = 7},
+        {.res = P_TMR4, .offset = 6},
+        {.res = P_SPI0_SSEL5, .offset = 6},
+        {.res = P_TMR5, .offset = 5},
+        {.res = P_SPI0_SSEL6, .offset = 5},
+        {.res = P_UART1_RX, .offset = 4},
+        {.res = P_UART1_TX, .offset = 4},
+        {.res = P_TMR6, .offset = 4},
+        {.res = P_TMR7, .offset = 4},
+        {.res = P_UART0_RX, .offset = 3},
+        {.res = P_UART0_TX, .offset = 3},
+        {.res = P_DMAR0, .offset = 3},
+        {.res = P_DMAR1, .offset = 3},
+        {.res = P_SPORT0_DTSEC, .offset = 1},
+        {.res = P_SPORT0_DRSEC, .offset = 1},
+        {.res = P_CAN0_RX, .offset = 1},
+        {.res = P_CAN0_TX, .offset = 1},
+        {.res = P_SPI0_SSEL7, .offset = 1},
+        {.res = P_SPORT0_TFS, .offset = 0},
+        {.res = P_SPORT0_DTPRI, .offset = 0},
+        {.res = P_SPI0_SSEL2, .offset = 0},
+        {.res = P_SPI0_SSEL3, .offset = 0},
 };
 static void portmux_setup(unsigned short per, unsigned short function)
 {
-        u16 y, muxreg, offset;
+        u16 y, offset, muxreg;
-        for (y = 0; y < PMUX_LUT_ENTRIES; y++) {
+        for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
-                if (port_mux_lut[y][PMUX_LUT_RES] == per) {
+                if (port_mux_lut[y].res == per) {
                        /* SET PORTMUX REG */
-                        offset = port_mux_lut[y][PMUX_LUT_OFFSET];
+                        offset = port_mux_lut[y].offset;
                        muxreg = bfin_read_PORT_MUX();
                        if (offset != 1) {
@@ -238,18 +333,42 @@ static void portmux_setup(unsigned short per, unsigned short function)
                }
        }
 }
+#elif defined(BF548_FAMILY)
+inline void portmux_setup(unsigned short portno, unsigned short function)
+{
+        u32 pmux;
+        pmux = gpio_array[gpio_bank(portno)]->port_mux;
+        pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
+        pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
+        gpio_array[gpio_bank(portno)]->port_mux = pmux;
+}
+inline u16 get_portmux(unsigned short portno)
+{
+        u32 pmux;
+        pmux = gpio_array[gpio_bank(portno)]->port_mux;
+        return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
+}
 #else
 # define portmux_setup(...)  do { } while (0)
 #endif
+#ifndef BF548_FAMILY
 static void default_gpio(unsigned short gpio)
 {
        unsigned short bank, bitmask;
+        unsigned long flags;
        bank = gpio_bank(gpio);
        bitmask = gpio_bit(gpio);
+        local_irq_save(flags);
        gpio_bankb[bank]->maska_clear = bitmask;
        gpio_bankb[bank]->maskb_clear = bitmask;
        SSYNC();
@@ -258,24 +377,32 @@ static void default_gpio(unsigned short gpio)
        gpio_bankb[bank]->polar &= ~bitmask;
        gpio_bankb[bank]->both &= ~bitmask;
        gpio_bankb[bank]->edge &= ~bitmask;
+        AWA_DUMMY_READ(edge);
+        local_irq_restore(flags);
 }
+#else
+# define default_gpio(...)  do { } while (0)
+#endif
 static int __init bfin_gpio_init(void)
 {
+        str_ident = kcalloc(MAX_RESOURCES,
-        str_ident = kzalloc(RESOURCE_LABEL_SIZE * 256, GFP_KERNEL);
+                                 sizeof(struct str_ident), GFP_KERNEL);
-        if (!str_ident)
+        if (str_ident == NULL)
                return -ENOMEM;
+        memset(str_ident, 0, MAX_RESOURCES * sizeof(struct str_ident));
        printk(KERN_INFO "Blackfin GPIO Controller\n");
        return 0;
 }
 arch_initcall(bfin_gpio_init);
+#ifndef BF548_FAMILY
 /***********************************************************
 *
 * FUNCTIONS: Blackfin General Purpose Ports Access Functions
@@ -305,6 +432,7 @@ void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
                gpio_bankb[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
        else \
                gpio_bankb[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
+        AWA_DUMMY_READ(name); \
        local_irq_restore(flags); \
 } \
 EXPORT_SYMBOL(set_gpio_ ## name);
@@ -316,6 +444,22 @@ SET_GPIO(edge)
 SET_GPIO(both)
+#if ANOMALY_05000311 || ANOMALY_05000323
+#define SET_GPIO_SC(name) \
+void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
+{ \
+        unsigned long flags; \
+        BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))); \
+        local_irq_save(flags); \
+        if (arg) \
+                gpio_bankb[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
+        else \
+                gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
+        AWA_DUMMY_READ(name); \
+        local_irq_restore(flags); \
+} \
+EXPORT_SYMBOL(set_gpio_ ## name);
+#else
 #define SET_GPIO_SC(name) \
 void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
 { \
@@ -326,37 +470,20 @@ void set_gpio_ ## name(unsigned short gpio, unsigned short arg) \
                gpio_bankb[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
 } \
 EXPORT_SYMBOL(set_gpio_ ## name);
+#endif
 SET_GPIO_SC(maska)
 SET_GPIO_SC(maskb)
-#if defined(ANOMALY_05000311)
-void set_gpio_data(unsigned short gpio, unsigned short arg)
-{
-        unsigned long flags;
-        BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
-        local_irq_save(flags);
-        if (arg)
-                gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
-        else
-                gpio_bankb[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
-        bfin_read_CHIPID();
-        local_irq_restore(flags);
-}
-EXPORT_SYMBOL(set_gpio_data);
-#else
 SET_GPIO_SC(data)
-#endif
-#if defined(ANOMALY_05000311)
+#if ANOMALY_05000311 || ANOMALY_05000323
 void set_gpio_toggle(unsigned short gpio)
 {
        unsigned long flags;
        BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
        local_irq_save(flags);
        gpio_bankb[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
-        bfin_read_CHIPID();
+        AWA_DUMMY_READ(toggle);
        local_irq_restore(flags);
 }
 #else
@@ -371,13 +498,27 @@ EXPORT_SYMBOL(set_gpio_toggle);
 /*Set current PORT date (16-bit word)*/
+#if ANOMALY_05000311 || ANOMALY_05000323
 #define SET_GPIO_P(name) \
 void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \
 { \
+        unsigned long flags; \
+        local_irq_save(flags); \
        gpio_bankb[gpio_bank(gpio)]->name = arg; \
+        AWA_DUMMY_READ(name); \
+        local_irq_restore(flags); \
 } \
 EXPORT_SYMBOL(set_gpiop_ ## name);
+#else
+#define SET_GPIO_P(name) \
+void set_gpiop_ ## name(unsigned short gpio, unsigned short arg) \
+{ \
+        gpio_bankb[gpio_bank(gpio)]->name = arg; \
+} \
+EXPORT_SYMBOL(set_gpiop_ ## name);
+#endif
+SET_GPIO_P(data)
 SET_GPIO_P(dir)
 SET_GPIO_P(inen)
 SET_GPIO_P(polar)
@@ -387,31 +528,30 @@ SET_GPIO_P(maska)
 SET_GPIO_P(maskb)
-#if defined(ANOMALY_05000311)
-void set_gpiop_data(unsigned short gpio, unsigned short arg)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-        gpio_bankb[gpio_bank(gpio)]->data = arg;
-        bfin_read_CHIPID();
-        local_irq_restore(flags);
-}
-EXPORT_SYMBOL(set_gpiop_data);
-#else
-SET_GPIO_P(data)
-#endif
 /* Get a specific bit */
+#if ANOMALY_05000311 || ANOMALY_05000323
+#define GET_GPIO(name) \
+unsigned short get_gpio_ ## name(unsigned short gpio) \
+{ \
+        unsigned long flags; \
+        unsigned short ret; \
+        local_irq_save(flags); \
+        ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
+        AWA_DUMMY_READ(name); \
+        local_irq_restore(flags); \
+        return ret; \
+} \
+EXPORT_SYMBOL(get_gpio_ ## name);
+#else
 #define GET_GPIO(name) \
 unsigned short get_gpio_ ## name(unsigned short gpio) \
 { \
        return (0x01 & (gpio_bankb[gpio_bank(gpio)]->name >> gpio_sub_n(gpio))); \
 } \
 EXPORT_SYMBOL(get_gpio_ ## name);
+#endif
+GET_GPIO(data)
 GET_GPIO(dir)
 GET_GPIO(inen)
 GET_GPIO(polar)
@@ -420,33 +560,31 @@ GET_GPIO(both)
 GET_GPIO(maska)
 GET_GPIO(maskb)
-#if defined(ANOMALY_05000311)
-unsigned short get_gpio_data(unsigned short gpio)
-{
-        unsigned long flags;
-        unsigned short ret;
-        BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
-        local_irq_save(flags);
-        ret = 0x01 & (gpio_bankb[gpio_bank(gpio)]->data >> gpio_sub_n(gpio));
-        bfin_read_CHIPID();
-        local_irq_restore(flags);
-        return ret;
-}
-EXPORT_SYMBOL(get_gpio_data);
-#else
-GET_GPIO(data)
-#endif
 /*Get current PORT date (16-bit word)*/
+#if ANOMALY_05000311 || ANOMALY_05000323
+#define GET_GPIO_P(name) \
+unsigned short get_gpiop_ ## name(unsigned short gpio) \
+{ \
+        unsigned long flags; \
+        unsigned short ret; \
+        local_irq_save(flags); \
+        ret = (gpio_bankb[gpio_bank(gpio)]->name); \
+        AWA_DUMMY_READ(name); \
+        local_irq_restore(flags); \
+        return ret; \
+} \
+EXPORT_SYMBOL(get_gpiop_ ## name);
+#else
 #define GET_GPIO_P(name) \
 unsigned short get_gpiop_ ## name(unsigned short gpio) \
 { \
        return (gpio_bankb[gpio_bank(gpio)]->name);\
 } \
 EXPORT_SYMBOL(get_gpiop_ ## name);
+#endif
+GET_GPIO_P(data)
 GET_GPIO_P(dir)
 GET_GPIO_P(inen)
 GET_GPIO_P(polar)
@@ -455,21 +593,6 @@ GET_GPIO_P(both)
 GET_GPIO_P(maska)
 GET_GPIO_P(maskb)
-#if defined(ANOMALY_05000311)
-unsigned short get_gpiop_data(unsigned short gpio)
-{
-        unsigned long flags;
-        unsigned short ret;
-        local_irq_save(flags);
-        ret = gpio_bankb[gpio_bank(gpio)]->data;
-        bfin_read_CHIPID();
-        local_irq_restore(flags);
-        return ret;
-}
-EXPORT_SYMBOL(get_gpiop_data);
-#else
-GET_GPIO_P(data)
-#endif
 #ifdef CONFIG_PM
 /***********************************************************
@@ -593,6 +716,8 @@ u32 gpio_pm_setup(void)
                }
        }
+        AWA_DUMMY_READ(maskb_set);
        if (sic_iwr)
                return sic_iwr;
        else
@@ -624,12 +749,99 @@ void gpio_pm_restore(void)
                gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb;
        }
+        AWA_DUMMY_READ(maskb);
 }
 #endif
+#endif /* BF548_FAMILY */
+/***********************************************************
+*
+* FUNCTIONS:    Blackfin Peripheral Resource Allocation
+*               and PortMux Setup
+*
+* INPUTS/OUTPUTS:
+* per   Peripheral Identifier
+* label String
+*
+* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
+*
+* CAUTION:
+*************************************************************
+* MODIFICATION HISTORY :
+**************************************************************/
+#ifdef BF548_FAMILY
+int peripheral_request(unsigned short per, const char *label)
+{
+        unsigned long flags;
+        unsigned short ident = P_IDENT(per);
+        /*
+         * Don't cares are pins with only one dedicated function
+         */
+        if (per & P_DONTCARE)
+                return 0;
+        if (!(per & P_DEFINED))
+                return -ENODEV;
+        if (check_gpio(ident) < 0)
+                return -EINVAL;
+        local_irq_save(flags);
+        if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
+                printk(KERN_ERR
+                    "%s: Peripheral %d is already reserved as GPIO by %s !\n",
+                       __FUNCTION__, ident, get_label(ident));
+                dump_stack();
+                local_irq_restore(flags);
+                return -EBUSY;
+        }
+        if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
+                u16 funct = get_portmux(ident);
+        /*
+         * Pin functions like AMC address strobes my
+         * be requested and used by several drivers
+         */
+                if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
+                /*
+                 * Allow that the identical pin function can
+                 * be requested from the same driver twice
+                 */
+                if (cmp_label(ident, label) == 0)
+                        goto anyway;
+                        printk(KERN_ERR
+                               "%s: Peripheral %d function %d is already reserved by %s !\n",
+                               __FUNCTION__, ident, P_FUNCT2MUX(per), get_label(ident));
+                        dump_stack();
+                        local_irq_restore(flags);
+                        return -EBUSY;
+                }
+        }
+anyway:
+        reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
+        portmux_setup(ident, P_FUNCT2MUX(per));
+        port_setup(ident, PERIPHERAL_USAGE);
+        local_irq_restore(flags);
+        set_label(ident, label);
+        return 0;
+}
+EXPORT_SYMBOL(peripheral_request);
+#else
 int peripheral_request(unsigned short per, const char *label)
 {
@@ -680,7 +892,7 @@ int peripheral_request(unsigned short per, const char *label)
                        printk(KERN_ERR
                               "%s: Peripheral %d function %d is already"
-                               "reserved by %s !\n",
+                               " reserved by %s !\n",
                               __FUNCTION__, ident, P_FUNCT2MUX(per),
                                get_label(ident));
                        dump_stack();
@@ -691,8 +903,6 @@ int peripheral_request(unsigned short per, const char *label)
        }
 anyway:
        portmux_setup(per, P_FUNCT2MUX(per));
        port_setup(ident, PERIPHERAL_USAGE);
@@ -704,6 +914,7 @@ anyway:
        return 0;
 }
 EXPORT_SYMBOL(peripheral_request);
+#endif
 int peripheral_request_list(unsigned short per[], const char *label)
 {
@@ -711,9 +922,15 @@ int peripheral_request_list(unsigned short per[], const char *label)
        int ret;
        for (cnt = 0; per[cnt] != 0; cnt++) {
                ret = peripheral_request(per[cnt], label);
-                if (ret < 0)
-                        return ret;
+                if (ret < 0) {
+                        for ( ; cnt > 0; cnt--) {
+                                peripheral_free(per[cnt - 1]);
+                        }
+                return ret;
+                }
        }
        return 0;
@@ -748,6 +965,8 @@ void peripheral_free(unsigned short per)
        reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
+        set_label(ident, "free");
        local_irq_restore(flags);
 }
 EXPORT_SYMBOL(peripheral_free);
@@ -768,8 +987,8 @@ EXPORT_SYMBOL(peripheral_free_list);
 * FUNCTIONS: Blackfin GPIO Driver
 *
 * INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
+* gpio  PIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
+* label String
 *
 * DESCRIPTION: Blackfin GPIO Driver API
 *
@@ -787,17 +1006,39 @@ int gpio_request(unsigned short gpio, const char *label)
        local_irq_save(flags);
+        /*
+         * Allow that the identical GPIO can
+         * be requested from the same driver twice
+         * Do nothing and return -
+         */
+        if (cmp_label(gpio, label) == 0) {
+                local_irq_restore(flags);
+                return 0;
+        }
        if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
-                printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio);
+                printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved by %s !\n",
+                         gpio, get_label(gpio));
                dump_stack();
                local_irq_restore(flags);
                return -EBUSY;
        }
+        if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
+                printk(KERN_ERR
+                       "bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
+                       gpio, get_label(gpio));
+                dump_stack();
+                local_irq_restore(flags);
+                return -EBUSY;
+        }
        reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
        local_irq_restore(flags);
        port_setup(gpio, GPIO_USAGE);
+        set_label(gpio, label);
        return 0;
 }
@@ -823,10 +1064,57 @@ void gpio_free(unsigned short gpio)
        reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
+        set_label(gpio, "free");
        local_irq_restore(flags);
 }
 EXPORT_SYMBOL(gpio_free);
+#ifdef BF548_FAMILY
+void gpio_direction_input(unsigned short gpio)
+{
+        unsigned long flags;
+        BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
+        local_irq_save(flags);
+        gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
+        gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(gpio_direction_input);
+void gpio_direction_output(unsigned short gpio)
+{
+        unsigned long flags;
+        BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
+        local_irq_save(flags);
+        gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
+        gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
+        local_irq_restore(flags);
+}
+EXPORT_SYMBOL(gpio_direction_output);
+void gpio_set_value(unsigned short gpio, unsigned short arg)
+{
+        if (arg)
+                gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
+        else
+                gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
+}
+EXPORT_SYMBOL(gpio_set_value);
+unsigned short gpio_get_value(unsigned short gpio)
+{
+        return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
+}
+EXPORT_SYMBOL(gpio_get_value);
+#else
 void gpio_direction_input(unsigned short gpio)
 {
        unsigned long flags;
@@ -836,6 +1124,7 @@ void gpio_direction_input(unsigned short gpio)
        local_irq_save(flags);
        gpio_bankb[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
        gpio_bankb[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
+        AWA_DUMMY_READ(inen);
        local_irq_restore(flags);
 }
 EXPORT_SYMBOL(gpio_direction_input);
@@ -849,6 +1138,28 @@ void gpio_direction_output(unsigned short gpio)
        local_irq_save(flags);
        gpio_bankb[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
        gpio_bankb[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
+        AWA_DUMMY_READ(dir);
        local_irq_restore(flags);
 }
 EXPORT_SYMBOL(gpio_direction_output);
+/* If we are booting from SPI and our board lacks a strong enough pull up,
+ * the core can reset and execute the bootrom faster than the resistor can
+ * pull the signal logically high.  To work around this (common) error in
+ * board design, we explicitly set the pin back to GPIO mode, force /CS
+ * high, and wait for the electrons to do their thing.
+ *
+ * This function only makes sense to be called from reset code, but it
+ * lives here as we need to force all the GPIO states w/out going through
+ * BUG() checks and such.
+ */
+void bfin_gpio_reset_spi0_ssel1(void)
+{
+        u16 gpio = P_IDENT(P_SPI0_SSEL1);
+        port_setup(gpio, GPIO_USAGE);
+        gpio_bankb[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
+        udelay(1);
+}
+#endif /*BF548_FAMILY */
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
index 70455949cfd2..2198afe40f33 100644
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ b/arch/blackfin/kernel/bfin_ksyms.c
@@ -60,6 +60,7 @@ EXPORT_SYMBOL(csum_partial_copy);
 * their interface isn't gonna change any time soon now, so
 * it's OK to leave it out of version control.
 */
+EXPORT_SYMBOL(strcpy);
 EXPORT_SYMBOL(memcpy);
 EXPORT_SYMBOL(memset);
 EXPORT_SYMBOL(memcmp);
diff --git a/arch/blackfin/kernel/cacheinit.c b/arch/blackfin/kernel/cacheinit.c
index 4d41a40e8133..62cbba7364b0 100644
--- a/arch/blackfin/kernel/cacheinit.c
+++ b/arch/blackfin/kernel/cacheinit.c
@@ -21,9 +21,10 @@
 #include <asm/cacheflush.h>
 #include <asm/blackfin.h>
+#include <asm/cplb.h>
 #include <asm/cplbinit.h>
-#if defined(CONFIG_BLKFIN_CACHE)
+#if defined(CONFIG_BFIN_ICACHE)
 void bfin_icache_init(void)
 {
        unsigned long *table = icplb_table;
@@ -44,7 +45,7 @@ void bfin_icache_init(void)
 }
 #endif
-#if defined(CONFIG_BLKFIN_DCACHE)
+#if defined(CONFIG_BFIN_DCACHE)
 void bfin_dcache_init(void)
 {
        unsigned long *table = dcplb_table;
diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplbinit.c
index bbdb403fcb55..f2db6a5e2b5b 100644
--- a/arch/blackfin/kernel/cplbinit.c
+++ b/arch/blackfin/kernel/cplbinit.c
@@ -23,6 +23,7 @@
 #include <linux/module.h>
 #include <asm/blackfin.h>
+#include <asm/cplb.h>
 #include <asm/cplbinit.h>
 u_long icplb_table[MAX_CPLBS+1];
@@ -56,7 +57,7 @@ struct s_cplb {
        struct cplb_tab switch_d;
 };
-#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
+#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
 static struct cplb_desc cplb_data[] = {
        {
                .start = 0,
@@ -230,8 +231,8 @@ static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_en
                                cplb_data[i].psize,
                                cplb_data[i].i_conf);
        } else {
-#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
+#if defined(CONFIG_BFIN_ICACHE)
-                if (i == SDRAM_KERN) {
+                if (ANOMALY_05000263 && i == SDRAM_KERN) {
                        fill_cplbtab(t,
                                        cplb_data[i].start,
                                        cplb_data[i].end,
diff --git a/arch/blackfin/kernel/early_printk.c b/arch/blackfin/kernel/early_printk.c
new file mode 100644
index 000000000000..6ec518a81113
--- /dev/null
+++ b/arch/blackfin/kernel/early_printk.c
@@ -0,0 +1,214 @@
+/*
+ * File:         arch/blackfin/kernel/early_printk.c
+ * Based on:     arch/x86_64/kernel/early_printk.c
+ * Author:       Robin Getz <rgetz@blackfin.uclinux.org
+ *
+ * Created:      14Aug2007
+ * Description:  allow a console to be used for early printk
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/console.h>
+#include <linux/string.h>
+#include <asm/blackfin.h>
+#include <asm/irq_handler.h>
+#include <asm/early_printk.h>
+#ifdef CONFIG_SERIAL_BFIN
+extern struct console *bfin_earlyserial_init(unsigned int port,
+                                                unsigned int cflag);
+#endif
+static struct console *early_console;
+/* Default console */
+#define DEFAULT_PORT 0
+#define DEFAULT_CFLAG CS8|B57600
+/* Default console for early crashes */
+#define DEFAULT_EARLY_PORT "serial,uart0,57600"
+#ifdef CONFIG_SERIAL_CORE
+/* What should get here is "0,57600" */
+static struct console * __init earlyserial_init(char *buf)
+{
+        int baud, bit;
+        char parity;
+        unsigned int serial_port = DEFAULT_PORT;
+        unsigned int cflag = DEFAULT_CFLAG;
+        serial_port = simple_strtoul(buf, &buf, 10);
+        buf++;
+        cflag = 0;
+        baud = simple_strtoul(buf, &buf, 10);
+        switch (baud) {
+        case 1200:
+                cflag |= B1200;
+                break;
+        case 2400:
+                cflag |= B2400;
+                break;
+        case 4800:
+                cflag |= B4800;
+                break;
+        case 9600:
+                cflag |= B9600;
+                break;
+        case 19200:
+                cflag |= B19200;
+                break;
+        case 38400:
+                cflag |= B38400;
+                break;
+        case 115200:
+                cflag |= B115200;
+                break;
+        default:
+                cflag |= B57600;
+        }
+        parity = buf[0];
+        buf++;
+        switch (parity) {
+        case 'e':
+                cflag |= PARENB;
+                break;
+        case 'o':
+                cflag |= PARODD;
+                break;
+        }
+        bit = simple_strtoul(buf, &buf, 10);
+        switch (bit) {
+        case 5:
+                cflag |= CS5;
+                break;
+        case 6:
+                cflag |= CS5;
+                break;
+        case 7:
+                cflag |= CS5;
+                break;
+        default:
+                cflag |= CS8;
+        }
+#ifdef CONFIG_SERIAL_BFIN
+        return bfin_earlyserial_init(serial_port, cflag);
+#else
+        return NULL;
+#endif
+}
+#endif
+int __init setup_early_printk(char *buf)
+{
+        /* Crashing in here would be really bad, so check both the var
+           and the pointer before we start using it
+         */
+        if (!buf)
+                return 0;
+        if (!*buf)
+                return 0;
+        if (early_console != NULL)
+                return 0;
+#ifdef CONFIG_SERIAL_BFIN
+        /* Check for Blackfin Serial */
+        if (!strncmp(buf, "serial,uart", 11)) {
+                buf += 11;
+                early_console = earlyserial_init(buf);
+        }
+#endif
+#ifdef CONFIG_FB
+                /* TODO: add framebuffer console support */
+#endif
+        if (likely(early_console)) {
+                early_console->flags |= CON_BOOT;
+                register_console(early_console);
+                printk(KERN_INFO "early printk enabled on %s%d\n",
+                        early_console->name,
+                        early_console->index);
+        }
+        return 0;
+}
+/*
+ * Set up a temporary Event Vector Table, so if something bad happens before
+ * the kernel is fully started, it doesn't vector off into somewhere we don't
+ * know
+ */
+asmlinkage void __init init_early_exception_vectors(void)
+{
+        SSYNC();
+        /* cannot program in software:
+         * evt0 - emulation (jtag)
+         * evt1 - reset
+         */
+        bfin_write_EVT2(early_trap);
+        bfin_write_EVT3(early_trap);
+        bfin_write_EVT5(early_trap);
+        bfin_write_EVT6(early_trap);
+        bfin_write_EVT7(early_trap);
+        bfin_write_EVT8(early_trap);
+        bfin_write_EVT9(early_trap);
+        bfin_write_EVT10(early_trap);
+        bfin_write_EVT11(early_trap);
+        bfin_write_EVT12(early_trap);
+        bfin_write_EVT13(early_trap);
+        bfin_write_EVT14(early_trap);
+        bfin_write_EVT15(early_trap);
+        CSYNC();
+        /* Set all the return from interupt, exception, NMI to a known place
+         * so if we do a RETI, RETX or RETN by mistake - we go somewhere known
+         * Note - don't change RETS - we are in a subroutine, or
+         * RETE - since it might screw up if emulator is attached
+         */
+        asm("\tRETI = %0; RETX = %0; RETN = %0;\n"
+                : : "p"(early_trap));
+}
+asmlinkage void __init early_trap_c(struct pt_regs *fp, void *retaddr)
+{
+        /* This can happen before the uart is initialized, so initialize
+         * the UART now
+         */
+        if (likely(early_console == NULL))
+                setup_early_printk(DEFAULT_EARLY_PORT);
+        dump_bfin_regs(fp, retaddr);
+        dump_bfin_trace_buffer();
+        panic("Died early");
+}
+early_param("earlyprintk", setup_early_printk);
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 1fc001c7abda..73647c158774 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -34,6 +34,7 @@
 #include <linux/kallsyms.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <asm/trace.h>
 static unsigned long irq_err_count;
 static spinlock_t irq_controller_lock;
@@ -97,9 +98,8 @@ int show_interrupts(struct seq_file *p, void *v)
 */
 #ifdef CONFIG_DO_IRQ_L1
-asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)__attribute__((l1_text));
+__attribute__((l1_text))
 #endif
 asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
 {
        struct pt_regs *old_regs;
@@ -144,4 +144,12 @@ void __init init_IRQ(void)
        }
        init_arch_irq();
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
+        /* Now that evt_ivhw is set up, turn this on */
+        trace_buff_offset = 0;
+        bfin_write_TBUFCTL(BFIN_TRACE_ON);
+        printk(KERN_INFO "Hardware Trace expanded to %ik\n",
+          1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN);
+#endif
 }
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 6a7aefe48346..9124467651c4 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -134,31 +134,6 @@ void cpu_idle(void)
        }
 }
-void machine_restart(char *__unused)
-{
-#if defined(CONFIG_BLKFIN_CACHE)
-        bfin_write_IMEM_CONTROL(0x01);
-        SSYNC();
-#endif
-        bfin_reset();
-        /* Dont do anything till the reset occurs */
-        while (1) {
-                SSYNC();
-        }
-}
-void machine_halt(void)
-{
-        for (;;)
-                asm volatile ("idle");
-}
-void machine_power_off(void)
-{
-        for (;;)
-                asm volatile ("idle");
-}
 void show_regs(struct pt_regs *regs)
 {
        printk(KERN_NOTICE "\n");
@@ -420,7 +395,8 @@ void finish_atomic_sections (struct pt_regs *regs)
 #if defined(CONFIG_ACCESS_CHECK)
 int _access_ok(unsigned long addr, unsigned long size)
 {
+        if (size == 0)
+                return 1;
        if (addr > (addr + size))
                return 0;
        if (segment_eq(get_fs(), KERNEL_DS))
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index ed800c7456dd..64ce5fea8609 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -44,6 +44,7 @@
 #include <asm/processor.h>
 #include <asm/asm-offsets.h>
 #include <asm/dma.h>
+#include <asm/fixed_code.h>
 #define MAX_SHARED_LIBS 3
 #define TEXT_OFFSET 0
@@ -169,6 +170,9 @@ static inline int is_user_addr_valid(struct task_struct *child,
                    && start + len <= (unsigned long)sraml->addr + sraml->length)
                        return 0;
+        if (start >= FIXED_CODE_START && start + len <= FIXED_CODE_END)
+                return 0;
        return -EIO;
 }
@@ -215,9 +219,13 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                                copied = sizeof(tmp);
                        } else
 #endif
-                        copied =
+                        if (addr + add >= FIXED_CODE_START
-                            access_process_vm(child, addr + add, &tmp,
+                            && addr + add + sizeof(tmp) <= FIXED_CODE_END) {
-                                              sizeof(tmp), 0);
+                                memcpy(&tmp, (const void *)(addr + add), sizeof(tmp));
+                                copied = sizeof(tmp);
+                        } else
+                                copied = access_process_vm(child, addr + add, &tmp,
+                                                           sizeof(tmp), 0);
                        pr_debug("ptrace: copied size %d [0x%08lx]\n", copied, tmp);
                        if (copied != sizeof(tmp))
                                break;
@@ -281,9 +289,13 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                                copied = sizeof(data);
                        } else
 #endif
-                        copied =
+                        if (addr + add >= FIXED_CODE_START
-                            access_process_vm(child, addr + add, &data,
+                            && addr + add + sizeof(data) <= FIXED_CODE_END) {
-                                              sizeof(data), 1);
+                                memcpy((void *)(addr + add), &data, sizeof(data));
+                                copied = sizeof(data);
+                        } else
+                                copied = access_process_vm(child, addr + add, &data,
+                                                           sizeof(data), 1);
                        pr_debug("ptrace: copied size %d\n", copied);
                        if (copied != sizeof(data))
                                break;
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
new file mode 100644
index 000000000000..356078ec462b
--- /dev/null
+++ b/arch/blackfin/kernel/reboot.c
@@ -0,0 +1,78 @@
+/*
+ * arch/blackfin/kernel/reboot.c - handle shutdown/reboot
+ *
+ * Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#include <linux/interrupt.h>
+#include <asm/bfin-global.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+#if defined(BF537_FAMILY) || defined(BF533_FAMILY)
+#define SYSCR_VAL       0x0
+#elif defined(BF561_FAMILY)
+#define SYSCR_VAL       0x20
+#elif defined(BF548_FAMILY)
+#define SYSCR_VAL       0x10
+#endif
+/* A system soft reset makes external memory unusable
+ * so force this function into L1.
+ */
+__attribute__((l1_text))
+void bfin_reset(void)
+{
+        /* force BMODE and disable Core B (as needed) */
+        bfin_write_SYSCR(SYSCR_VAL);
+        /* we use asm ssync here because it's save and we save some L1 */
+        asm("ssync;");
+        while (1) {
+                /* initiate system soft reset with magic 0x7 */
+                bfin_write_SWRST(0x7);
+                asm("ssync;");
+                /* clear system soft reset */
+                bfin_write_SWRST(0);
+                asm("ssync;");
+                /* issue core reset */
+                asm("raise 1");
+        }
+}
+__attribute__((weak))
+void native_machine_restart(char *cmd)
+{
+}
+void machine_restart(char *cmd)
+{
+        native_machine_restart(cmd);
+        local_irq_disable();
+        bfin_reset();
+}
+__attribute__((weak))
+void native_machine_halt(void)
+{
+        idle_with_irq_disabled();
+}
+void machine_halt(void)
+{
+        native_machine_halt();
+}
+__attribute__((weak))
+void native_machine_power_off(void)
+{
+        idle_with_irq_disabled();
+}
+void machine_power_off(void)
+{
+        native_machine_power_off();
+}
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 88f221b89b33..8dcd76e87ed5 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -39,10 +39,12 @@
 #include <linux/cramfs_fs.h>
 #include <linux/romfs_fs.h>
+#include <asm/cplb.h>
 #include <asm/cacheflush.h>
 #include <asm/blackfin.h>
 #include <asm/cplbinit.h>
 #include <asm/fixed_code.h>
+#include <asm/early_printk.h>
 u16 _bfin_swrst;
@@ -66,21 +68,21 @@ char __initdata command_line[COMMAND_LINE_SIZE];
 void __init bf53x_cache_init(void)
 {
-#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
+#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
        generate_cpl_tables();
 #endif
-#ifdef CONFIG_BLKFIN_CACHE
+#ifdef CONFIG_BFIN_ICACHE
        bfin_icache_init();
        printk(KERN_INFO "Instruction Cache Enabled\n");
 #endif
-#ifdef CONFIG_BLKFIN_DCACHE
+#ifdef CONFIG_BFIN_DCACHE
        bfin_dcache_init();
        printk(KERN_INFO "Data Cache Enabled"
-# if defined CONFIG_BLKFIN_WB
+# if defined CONFIG_BFIN_WB
                " (write-back)"
-# elif defined CONFIG_BLKFIN_WT
+# elif defined CONFIG_BFIN_WT
                " (write-through)"
 # endif
                "\n");
@@ -156,8 +158,10 @@ static __init void parse_cmdline_early(char *cmdline_p)
                                                            1;
                                        }
                                }
+                        } else if (!memcmp(to, "earlyprintk=", 12)) {
+                                to += 12;
+                                setup_early_printk(to);
                        }
                }
                c = *(to++);
                if (!c)
@@ -176,22 +180,36 @@ void __init setup_arch(char **cmdline_p)
 #ifdef CONFIG_DUMMY_CONSOLE
        conswitchp = &dummy_con;
 #endif
+#if defined(CONFIG_CMDLINE_BOOL)
+        strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
+        command_line[sizeof(command_line) - 1] = 0;
+#endif
+        /* Keep a copy of command line */
+        *cmdline_p = &command_line[0];
+        memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
+        boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
+        /* setup memory defaults from the user config */
+        physical_mem_end = 0;
+        _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
+        parse_cmdline_early(&command_line[0]);
        cclk = get_cclk();
        sclk = get_sclk();
-#if !defined(CONFIG_BFIN_KERNEL_CLOCK) && defined(ANOMALY_05000273)
+#if !defined(CONFIG_BFIN_KERNEL_CLOCK)
-        if (cclk == sclk)
+        if (ANOMALY_05000273 && cclk == sclk)
                panic("ANOMALY 05000273, SCLK can not be same as CCLK");
 #endif
-#if defined(ANOMALY_05000266)
+#ifdef BF561_FAMILY
-        bfin_read_IMDMA_D0_IRQ_STATUS();
+        if (ANOMALY_05000266) {
-        bfin_read_IMDMA_D1_IRQ_STATUS();
+                bfin_read_IMDMA_D0_IRQ_STATUS();
-#endif
+                bfin_read_IMDMA_D1_IRQ_STATUS();
+        }
-#ifdef DEBUG_SERIAL_EARLY_INIT
-        bfin_console_init();    /* early console registration */
-        /* this give a chance to get printk() working before crash. */
 #endif
        printk(KERN_INFO "Hardware Trace ");
@@ -212,22 +230,6 @@ void __init setup_arch(char **cmdline_p)
        flash_probe();
 #endif
-#if defined(CONFIG_CMDLINE_BOOL)
-        strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
-        command_line[sizeof(command_line) - 1] = 0;
-#endif
-        /* Keep a copy of command line */
-        *cmdline_p = &command_line[0];
-        memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
-        boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
-        /* setup memory defaults from the user config */
-        physical_mem_end = 0;
-        _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
-        parse_cmdline_early(&command_line[0]);
        if (physical_mem_end == 0)
                physical_mem_end = _ramend;
@@ -260,7 +262,7 @@ void __init setup_arch(char **cmdline_p)
            && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1)
                mtd_size =
                    PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
-#  if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
+#  if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
        /* Due to a Hardware Anomaly we need to limit the size of usable
         * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
         * 05000263 - Hardware loop corrupted when taking an ICPLB exception
@@ -289,7 +291,7 @@ void __init setup_arch(char **cmdline_p)
        _ebss = memory_mtd_start;       /* define _ebss for compatible */
 #endif                          /* CONFIG_MTD_UCLINUX */
-#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
+#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
        /* Due to a Hardware Anomaly we need to limit the size of usable
         * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
         * 05000263 - Hardware loop corrupted when taking an ICPLB exception
@@ -334,13 +336,11 @@ void __init setup_arch(char **cmdline_p)
                       CPU, bfin_revid());
        printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
-        printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu Mhz System Clock\n",
+        printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
               cclk / 1000000,  sclk / 1000000);
-#if defined(ANOMALY_05000273)
+        if (ANOMALY_05000273 && (cclk >> 1) <= sclk)
-        if ((cclk >> 1) <= sclk)
                printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
-#endif
        printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
        printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
@@ -535,9 +535,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                seq_printf(m, "I-CACHE:\tOFF\n");
        if ((bfin_read_DMEM_CONTROL()) & (ENDCPLB | DMC_ENABLE))
                seq_printf(m, "D-CACHE:\tON"
-#if defined CONFIG_BLKFIN_WB
+#if defined CONFIG_BFIN_WB
                           " (write-back)"
-#elif defined CONFIG_BLKFIN_WT
+#elif defined CONFIG_BFIN_WT
                           " (write-through)"
 #endif
                           "\n");
@@ -566,15 +566,15 @@ static int show_cpuinfo(struct seq_file *m, void *v)
        }
-        seq_printf(m, "I-CACHE Size:\t%dKB\n", BLKFIN_ICACHESIZE / 1024);
+        seq_printf(m, "I-CACHE Size:\t%dKB\n", BFIN_ICACHESIZE / 1024);
        seq_printf(m, "D-CACHE Size:\t%dKB\n", dcache_size);
        seq_printf(m, "I-CACHE Setup:\t%d Sub-banks/%d Ways, %d Lines/Way\n",
-                   BLKFIN_ISUBBANKS, BLKFIN_IWAYS, BLKFIN_ILINES);
+                   BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
        seq_printf(m,
                   "D-CACHE Setup:\t%d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
-                   dsup_banks, BLKFIN_DSUBBANKS, BLKFIN_DWAYS,
+                   dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
-                   BLKFIN_DLINES);
+                   BFIN_DLINES);
-#ifdef CONFIG_BLKFIN_CACHE_LOCK
+#ifdef CONFIG_BFIN_ICACHE_LOCK
        switch (read_iloc()) {
        case WAY0_L:
                seq_printf(m, "Way0 Locked-Down\n");
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 792a8416fe10..8823e9ade584 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -51,10 +51,9 @@ void __init trap_init(void)
        CSYNC();
 }
-asmlinkage void trap_c(struct pt_regs *fp);
 int kstack_depth_to_print = 48;
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
 static int printk_address(unsigned long address)
 {
        struct vm_list_struct *vml;
@@ -131,10 +130,22 @@ static int printk_address(unsigned long address)
        /* we were unable to find this address anywhere */
        return printk("[<0x%p>]", (void *)address);
 }
+#endif
+asmlinkage void double_fault_c(struct pt_regs *fp)
+{
+        printk(KERN_EMERG "\n" KERN_EMERG "Double Fault\n");
+        dump_bfin_regs(fp, (void *)fp->retx);
+        panic("Double Fault - unrecoverable event\n");
+}
 asmlinkage void trap_c(struct pt_regs *fp)
 {
-        int j, sig = 0;
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
+        int j;
+#endif
+        int sig = 0;
        siginfo_t info;
        unsigned long trapnr = fp->seqstat & SEQSTAT_EXCAUSE;
@@ -391,10 +402,6 @@ asmlinkage void trap_c(struct pt_regs *fp)
                break;
        }
-        info.si_signo = sig;
-        info.si_errno = 0;
-        info.si_addr = (void *)fp->pc;
-        force_sig_info(sig, &info, current);
        if (sig != 0 && sig != SIGTRAP) {
                unsigned long stack;
                dump_bfin_regs(fp, (void *)fp->retx);
@@ -403,6 +410,10 @@ asmlinkage void trap_c(struct pt_regs *fp)
                if (current->mm == NULL)
                        panic("Kernel exception");
        }
+        info.si_signo = sig;
+        info.si_errno = 0;
+        info.si_addr = (void *)fp->pc;
+        force_sig_info(sig, &info, current);
        /* if the address that we are about to return to is not valid, set it
         * to a valid address, if we have a current application or panic
@@ -429,24 +440,56 @@ asmlinkage void trap_c(struct pt_regs *fp)
 /* Typical exception handling routines  */
+#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
 void dump_bfin_trace_buffer(void)
 {
-        int tflags;
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
+        int tflags, i = 0;
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
+        int j, index;
+#endif
        trace_buffer_save(tflags);
+        printk(KERN_EMERG "Hardware Trace:\n");
        if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
-                int i;
+                for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
-                printk(KERN_EMERG "Hardware Trace:\n");
+                        printk(KERN_EMERG "%4i Target : ", i);
-                for (i = 0; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
-                        printk(KERN_EMERG "%2i Target : ", i);
                        printk_address((unsigned long)bfin_read_TBUF());
-                        printk("\n" KERN_EMERG "   Source : ");
+                        printk("\n" KERN_EMERG "     Source : ");
                        printk_address((unsigned long)bfin_read_TBUF());
                        printk("\n");
                }
        }
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
+        if (trace_buff_offset)
+                index = trace_buff_offset/4 - 1;
+        else
+                index = EXPAND_LEN;
+        j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128;
+        while (j) {
+                printk(KERN_EMERG "%4i Target : ", i);
+                printk_address(software_trace_buff[index]);
+                index -= 1;
+                if (index < 0 )
+                        index = EXPAND_LEN;
+                printk("\n" KERN_EMERG "     Source : ");
+                printk_address(software_trace_buff[index]);
+                index -= 1;
+                if (index < 0)
+                        index = EXPAND_LEN;
+                printk("\n");
+                j--;
+                i++;
+        }
+#endif
        trace_buffer_restore(tflags);
+#endif
 }
 EXPORT_SYMBOL(dump_bfin_trace_buffer);
@@ -510,7 +553,9 @@ void show_stack(struct task_struct *task, unsigned long *stack)
 void dump_stack(void)
 {
        unsigned long stack;
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
        int tflags;
+#endif
        trace_buffer_save(tflags);
        dump_bfin_trace_buffer();
        show_stack(current, &stack);
@@ -559,8 +604,7 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
                unsigned short x = 0;
                for (; i < ((unsigned int)retaddr & 0xFFFFFFF0) + 32; i += 2) {
                        if (!(i & 0xF))
-                                printk(KERN_EMERG "\n" KERN_EMERG
+                                printk("\n" KERN_EMERG "0x%08x: ", i);
-                                        "0x%08x: ", i);
                        if (get_user(x, (unsigned short *)i))
                                break;
@@ -655,6 +699,42 @@ asmlinkage int sys_bfin_spinlock(int *spinlock)
        return ret;
 }
+int bfin_request_exception(unsigned int exception, void (*handler)(void))
+{
+        void (*curr_handler)(void);
+        if (exception > 0x3F)
+                return -EINVAL;
+        curr_handler = ex_table[exception];
+        if (curr_handler != ex_replaceable)
+                return -EBUSY;
+        ex_table[exception] = handler;
+        return 0;
+}
+EXPORT_SYMBOL(bfin_request_exception);
+int bfin_free_exception(unsigned int exception, void (*handler)(void))
+{
+        void (*curr_handler)(void);
+        if (exception > 0x3F)
+                return -EINVAL;
+        curr_handler = ex_table[exception];
+        if (curr_handler != handler)
+                return -EBUSY;
+        ex_table[exception] = ex_replaceable;
+        return 0;
+}
+EXPORT_SYMBOL(bfin_free_exception);
 void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
 {
        switch (cplb_panic) {
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index fb53780247bc..eec43674a465 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -49,7 +49,8 @@ SECTIONS
                TEXT_TEXT
                SCHED_TEXT
                LOCK_TEXT
-                *(.text.lock)
+                KPROBES_TEXT
+                *(.text.*)
                *(.fixup)
                . = ALIGN(16);
@@ -61,7 +62,7 @@ SECTIONS
                __etext = .;
        }
-        RODATA
+        RO_DATA(PAGE_SIZE)
        .data :
        {
@@ -72,50 +73,63 @@ SECTIONS
                __sdata = .;
                . = ALIGN(THREAD_SIZE);
                *(.data.init_task)
-                DATA_DATA
-                CONSTRUCTORS
                . = ALIGN(32);
                *(.data.cacheline_aligned)
+                DATA_DATA
+                *(.data.*)
+                CONSTRUCTORS
                . = ALIGN(THREAD_SIZE);
                __edata = .;
        }
        ___init_begin = .;
-        .init :
+        .init.text :
        {
                . = ALIGN(PAGE_SIZE);
                __sinittext = .;
                *(.init.text)
                __einittext = .;
+        }
+        .init.data :
+        {
+                . = ALIGN(16);
                *(.init.data)
+        }
+        .init.setup :
+        {
                . = ALIGN(16);
                ___setup_start = .;
                *(.init.setup)
                ___setup_end = .;
-                ___start___param = .;
+        }
-                *(__param)
+        .initcall.init :
-                ___stop___param = .;
+        {
                ___initcall_start = .;
                INITCALLS
                ___initcall_end = .;
+        }
+        .con_initcall.init :
+        {
                ___con_initcall_start = .;
                *(.con_initcall.init)
                ___con_initcall_end = .;
-                ___security_initcall_start = .;
+        }
-                *(.security_initcall.init)
+        SECURITY_INIT
-                ___security_initcall_end = .;
+        .init.ramfs :
+        {
                . = ALIGN(4);
                ___initramfs_start = .;
                *(.init.ramfs)
                ___initramfs_end = .;
-                . = ALIGN(4);
        }
        __l1_lma_start = .;
-        .text_l1 L1_CODE_START : AT(LOADADDR(.init) + SIZEOF(.init))
+        .text_l1 L1_CODE_START : AT(LOADADDR(.init.ramfs) + SIZEOF(.init.ramfs))
        {
                . = ALIGN(4);
                __stext_l1 = .;
@@ -164,13 +178,19 @@ SECTIONS
        {
                . = ALIGN(4);
                ___bss_start = .;
-                *(.bss)
+                *(.bss .bss.*)
                *(COMMON)
                . = ALIGN(4);
                ___bss_stop = .;
                __end = .;
        }
+        STABS_DEBUG
+        DWARF_DEBUG
+        NOTES
        /DISCARD/ :
        {
                *(.exit.text)
diff --git a/arch/blackfin/lib/memcmp.S b/arch/blackfin/lib/memcmp.S
index b88c5d2d1ebe..219fa2877c62 100644
--- a/arch/blackfin/lib/memcmp.S
+++ b/arch/blackfin/lib/memcmp.S
@@ -61,7 +61,7 @@ ENTRY(_memcmp)
        LSETUP (.Lquad_loop_s, .Lquad_loop_e) LC0=P1;
 .Lquad_loop_s:
-#ifdef ANOMALY_05000202
+#if ANOMALY_05000202
        R0 = [P0++];
        R1 = [I0++];
 #else
diff --git a/arch/blackfin/lib/memcpy.S b/arch/blackfin/lib/memcpy.S
index 14a5585bbd02..2e6336492b4b 100644
--- a/arch/blackfin/lib/memcpy.S
+++ b/arch/blackfin/lib/memcpy.S
@@ -98,7 +98,7 @@ ENTRY(_memcpy)
        R0 = R1;
        I1 = P1;
        R3 = [I1++];
-#ifdef ANOMALY_05000202
+#if ANOMALY_05000202
 .Lword_loops:
        [P0++] = R3;
 .Lword_loope:
diff --git a/arch/blackfin/lib/memmove.S b/arch/blackfin/lib/memmove.S
index 6ee6e206e77c..33f8653145b7 100644
--- a/arch/blackfin/lib/memmove.S
+++ b/arch/blackfin/lib/memmove.S
@@ -70,7 +70,7 @@ ENTRY(_memmove)
        R1 = [I0++];
        LSETUP (.Lquad_loops, .Lquad_loope) LC0=P1;
-#ifdef ANOMALY_05000202
+#if ANOMALY_05000202
 .Lquad_loops:
        [P0++] = R1;
 .Lquad_loope:
@@ -102,7 +102,7 @@ ENTRY(_memmove)
        R1 = B[P3--] (Z);
        CC = P2 == 0;
        IF CC JUMP .Lno_loop;
-#ifdef ANOMALY_05000245
+#if ANOMALY_05000245
        NOP;
        NOP;
 #endif
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index 4545f363e641..a57b52d207cd 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -34,7 +34,9 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/usb_isp1362.h>
+#include <linux/pata_platform.h>
 #include <linux/irq.h>
+#include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
 /*
@@ -93,7 +95,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80",       /* Name of spi_driver for this device */
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,               /* Framework bus number */
+                .bus_num = 0,               /* Framework bus number */
                .chip_select = 1,           /* Framework chip select. On STAMP537 it is SPISSEL1*/
                .platform_data = &bfin_spi_flash_data,
                .controller_data = &spi_flash_chip_info,
@@ -101,7 +103,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        }, {
                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,               /* Framework bus number */
+                .bus_num = 0,               /* Framework bus number */
                .chip_select = 2,           /* Framework chip select. */
                .platform_data = NULL,      /* No spi_driver specific config */
                .controller_data = &spi_adc_chip_info,
@@ -110,24 +112,40 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad1836-spi",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
 };
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CH_SPI,
+                .end   = CH_SPI,
+                .flags = IORESOURCE_IRQ,
+        }
+};
 /* SPI controller data */
-static struct bfin5xx_spi_master spi_bfin_master_info = {
+static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 8,
        .enable_dma = 1,  /* master has the ability to do dma transfer */
 };
-static struct platform_device spi_bfin_master_device = {
+static struct platform_device bfin_spi0_device = {
-        .name = "bfin-spi-master",
+        .name = "bfin-spi",
-        .id = 1, /* Bus number */
+        .id = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
        .dev = {
-                .platform_data = &spi_bfin_master_info, /* Passed to driver */
+                .platform_data = &bfin_spi0_info, /* Passed to driver */
        },
 };
 #endif  /* spi master and devices */
@@ -227,6 +245,43 @@ static struct platform_device isp1362_hcd_device = {
 };
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#define PATA_INT        38
+static struct pata_platform_info bfin_pata_platform_data = {
+        .ioport_shift = 2,
+        .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+};
+static struct resource bfin_pata_resources[] = {
+        {
+                .start = 0x2030C000,
+                .end = 0x2030C01F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = 0x2030D018,
+                .end = 0x2030D01B,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = PATA_INT,
+                .end = PATA_INT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_pata_device = {
+        .name = "pata_platform",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(bfin_pata_resources),
+        .resource = bfin_pata_resources,
+        .dev = {
+                .platform_data = &bfin_pata_platform_data,
+        }
+};
+#endif
 static struct platform_device *cm_bf533_devices[] __initdata = {
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
        &bfin_uart_device,
@@ -250,7 +305,11 @@ static struct platform_device *cm_bf533_devices[] __initdata = {
 #endif
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-        &spi_bfin_master_device,
+        &bfin_spi0_device,
+#endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        &bfin_pata_device,
 #endif
 };
@@ -261,6 +320,10 @@ static int __init cm_bf533_init(void)
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
+#endif
        return 0;
 }
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index 0000b8f1239c..5c1e35d3c012 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -35,7 +35,9 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/usb_isp1362.h>
+#include <linux/pata_platform.h>
 #include <linux/irq.h>
+#include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
 /*
@@ -50,6 +52,12 @@ static struct platform_device rtc_device = {
 };
 #endif
+#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+static struct platform_device bfin_fb_adv7393_device = {
+        .name = "bfin-adv7393",
+};
+#endif
 /*
 *  USB-LAN EzExtender board
 *  Driver needs to know address, irq and flag pin.
@@ -131,7 +139,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
                .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
                .platform_data = &bfin_spi_flash_data,
                .controller_data = &spi_flash_chip_info,
@@ -143,7 +151,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
                .chip_select = 1, /* Framework chip select. */
                .platform_data = NULL, /* No spi_driver specific config */
                .controller_data = &spi_adc_chip_info,
@@ -154,24 +162,40 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad1836-spi",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
 };
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CH_SPI,
+                .end   = CH_SPI,
+                .flags = IORESOURCE_IRQ,
+        }
+};
 /* SPI controller data */
-static struct bfin5xx_spi_master spi_bfin_master_info = {
+static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 8,
        .enable_dma = 1,  /* master has the ability to do dma transfer */
 };
-static struct platform_device spi_bfin_master_device = {
+static struct platform_device bfin_spi0_device = {
-        .name = "bfin-spi-master",
+        .name = "bfin-spi",
-        .id = 1, /* Bus number */
+        .id = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
        .dev = {
-                .platform_data = &spi_bfin_master_info, /* Passed to driver */
+                .platform_data = &bfin_spi0_info, /* Passed to driver */
        },
 };
 #endif  /* spi master and devices */
@@ -193,13 +217,54 @@ static struct platform_device bfin_uart_device = {
 };
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#define PATA_INT        55
+static struct pata_platform_info bfin_pata_platform_data = {
+        .ioport_shift = 1,
+        .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+};
+static struct resource bfin_pata_resources[] = {
+        {
+                .start = 0x20314020,
+                .end = 0x2031403F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = 0x2031401C,
+                .end = 0x2031401F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = PATA_INT,
+                .end = PATA_INT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_pata_device = {
+        .name = "pata_platform",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(bfin_pata_resources),
+        .resource = bfin_pata_resources,
+        .dev = {
+                .platform_data = &bfin_pata_platform_data,
+        }
+};
+#endif
 static struct platform_device *ezkit_devices[] __initdata = {
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
        &smc91x_device,
 #endif
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-        &spi_bfin_master_device,
+        &bfin_spi0_device,
+#endif
+#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+        &bfin_fb_adv7393_device,
 #endif
 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
@@ -209,6 +274,10 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
        &bfin_uart_device,
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        &bfin_pata_device,
+#endif
 };
 static int __init ezkit_init(void)
@@ -218,6 +287,10 @@ static int __init ezkit_init(void)
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
+#endif
        return 0;
 }
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index a9143c4cbdcd..8975e06ea158 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -37,8 +37,11 @@
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 #include <linux/usb_isp1362.h>
 #endif
+#include <linux/pata_platform.h>
 #include <linux/irq.h>
+#include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
+#include <asm/reboot.h>
 /*
 * Name the Board for the /proc/cpuinfo
@@ -77,6 +80,12 @@ static struct platform_device smc91x_device = {
 };
 #endif
+#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+static struct platform_device bfin_fb_adv7393_device = {
+        .name = "bfin-adv7393",
+};
+#endif
 #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
 static struct resource net2272_bfin_resources[] = {
        {
@@ -177,7 +186,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
                .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL2*/
                .platform_data = &bfin_spi_flash_data,
                .controller_data = &spi_flash_chip_info,
@@ -189,7 +198,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
                .chip_select = 1, /* Framework chip select. */
                .platform_data = NULL, /* No spi_driver specific config */
                .controller_data = &spi_adc_chip_info,
@@ -200,7 +209,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad1836-spi",
                .max_speed_hz = 31250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
                .controller_data = &ad1836_spi_chip_info,
        },
@@ -210,7 +219,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "spi_mmc_dummy",
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = 0,
                .platform_data = NULL,
                .controller_data = &spi_mmc_chip_info,
@@ -219,7 +228,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "spi_mmc",
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SPI_MMC_CS_CHAN,
                .platform_data = NULL,
                .controller_data = &spi_mmc_chip_info,
@@ -231,16 +240,16 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "fxs-spi",
                .max_speed_hz = 12500000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
-                .chip_select = 3,
+                .chip_select = 8 - CONFIG_J11_JUMPER,
                .controller_data = &spi_si3xxx_chip_info,
                .mode = SPI_MODE_3,
        },
        {
                .modalias = "fxo-spi",
                .max_speed_hz = 12500000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
-                .chip_select = 2,
+                .chip_select = 8 - CONFIG_J19_JUMPER,
                .controller_data = &spi_si3xxx_chip_info,
                .mode = SPI_MODE_3,
        },
@@ -250,7 +259,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad5304_spi",
                .max_speed_hz = 1000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = 2,
                .platform_data = NULL,
                .controller_data = &ad5304_chip_info,
@@ -259,17 +268,33 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CH_SPI,
+                .end   = CH_SPI,
+                .flags = IORESOURCE_IRQ,
+        }
+};
 /* SPI controller data */
-static struct bfin5xx_spi_master spi_bfin_master_info = {
+static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 8,
        .enable_dma = 1,  /* master has the ability to do dma transfer */
 };
-static struct platform_device spi_bfin_master_device = {
+static struct platform_device bfin_spi0_device = {
-        .name = "bfin-spi-master",
+        .name = "bfin-spi",
-        .id = 1, /* Bus number */
+        .id = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
        .dev = {
-                .platform_data = &spi_bfin_master_info, /* Passed to driver */
+                .platform_data = &bfin_spi0_info, /* Passed to driver */
        },
 };
 #endif  /* spi master and devices */
@@ -309,6 +334,43 @@ static struct platform_device bfin_sport1_uart_device = {
 };
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#define PATA_INT        55
+static struct pata_platform_info bfin_pata_platform_data = {
+        .ioport_shift = 1,
+        .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+};
+static struct resource bfin_pata_resources[] = {
+        {
+                .start = 0x20314020,
+                .end = 0x2031403F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = 0x2031401C,
+                .end = 0x2031401F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = PATA_INT,
+                .end = PATA_INT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_pata_device = {
+        .name = "pata_platform",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(bfin_pata_resources),
+        .resource = bfin_pata_resources,
+        .dev = {
+                .platform_data = &bfin_pata_platform_data,
+        }
+};
+#endif
 static struct platform_device *stamp_devices[] __initdata = {
 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
        &rtc_device,
@@ -318,12 +380,16 @@ static struct platform_device *stamp_devices[] __initdata = {
        &smc91x_device,
 #endif
+#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+        &bfin_fb_adv7393_device,
+#endif
 #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
        &net2272_bfin_device,
 #endif
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-        &spi_bfin_master_device,
+        &bfin_spi0_device,
 #endif
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
@@ -334,6 +400,10 @@ static struct platform_device *stamp_devices[] __initdata = {
        &bfin_sport0_uart_device,
        &bfin_sport1_uart_device,
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        &bfin_pata_device,
+#endif
 };
 static int __init stamp_init(void)
@@ -355,8 +425,23 @@ static int __init stamp_init(void)
 #endif
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-        return spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
+        spi_register_board_info(bfin_spi_board_info,
+                                ARRAY_SIZE(bfin_spi_board_info));
+#endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
 #endif
+        return 0;
 }
 arch_initcall(stamp_init);
+void native_machine_restart(char *cmd)
+{
+#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
+# define BIT_TO_SET (1 << CONFIG_ENET_FLASH_PIN)
+        bfin_write_FIO_INEN(~BIT_TO_SET);
+        bfin_write_FIO_DIR(BIT_TO_SET);
+        bfin_write_FIO_FLAG_C(BIT_TO_SET);
+#endif
+}
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 7dd0e9c3a936..1ded945a6fa0 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -32,11 +32,9 @@
 #include <asm/blackfin.h>
 #include <asm/trace.h>
 #if CONFIG_BFIN_KERNEL_CLOCK
+#include <asm/mach-common/clocks.h>
 #include <asm/mach/mem_init.h>
 #endif
-#if CONFIG_DEBUG_KERNEL_START
-#include <asm/mach-common/def_LPBlackfin.h>
-#endif
 .global __rambase
 .global __ramstart
@@ -52,10 +50,12 @@ __INIT
 ENTRY(__start)
        /* R0: argument of command line string, passed from uboot, save it */
        R7 = R0;
-        /* Set the SYSCFG register:
+        /* Enable Cycle Counter and Nesting Of Interrupts */
-         * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
+#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
-         */
+        R0 = SYSCFG_SNEN;
-        R0 = 0x36;
+#else
+        R0 = SYSCFG_SNEN | SYSCFG_CCEN;
+#endif
        SYSCFG = R0;
        R0 = 0;
@@ -97,40 +97,10 @@ ENTRY(__start)
        M2 = r0;
        M3 = r0;
-        trace_buffer_start(p0,r0);
+        trace_buffer_init(p0,r0);
        P0 = R1;
        R0 = R1;
-#if CONFIG_DEBUG_KERNEL_START
-/*
- * Set up a temporary Event Vector Table, so if something bad happens before
- * the kernel is fully started, it doesn't vector off into the bootloaders
- * table
- */
-        P0.l = lo(EVT2);
-        P0.h = hi(EVT2);
-        P1.l = lo(EVT15);
-        P1.h = hi(EVT15);
-        P2.l = debug_kernel_start_trap;
-        P2.h = debug_kernel_start_trap;
-        RTS = P2;
-        RTI = P2;
-        RTX = P2;
-        RTN = P2;
-        RTE = P2;
-.Lfill_temp_vector_table:
-        [P0++] = P2;    /* Core Event Vector Table */
-        CC = P0 == P1;
-        if !CC JUMP .Lfill_temp_vector_table
-        P0 = r0;
-        P1 = r0;
-        P2 = r0;
-#endif
        p0.h = hi(FIO_MASKA_C);
        p0.l = lo(FIO_MASKA_C);
        r0 = 0xFFFF(Z);
@@ -144,38 +114,38 @@ ENTRY(__start)
        ssync;
        /* Turn off the icache */
-        p0.l = (IMEM_CONTROL & 0xFFFF);
+        p0.l = LO(IMEM_CONTROL);
-        p0.h = (IMEM_CONTROL >> 16);
+        p0.h = HI(IMEM_CONTROL);
        R1 = [p0];
        R0 = ~ENICPLB;
        R0 = R0 & R1;
        /* Anomaly 05000125 */
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        CLI R2;
        SSYNC;
 #endif
        [p0] = R0;
        SSYNC;
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        STI R2;
 #endif
        /* Turn off the dcache */
-        p0.l = (DMEM_CONTROL & 0xFFFF);
+        p0.l = LO(DMEM_CONTROL);
-        p0.h = (DMEM_CONTROL >> 16);
+        p0.h = HI(DMEM_CONTROL);
        R1 = [p0];
        R0 = ~ENDCPLB;
        R0 = R0 & R1;
        /* Anomaly 05000125 */
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        CLI R2;
        SSYNC;
 #endif
        [p0] = R0;
        SSYNC;
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        STI R2;
 #endif
@@ -211,6 +181,12 @@ ENTRY(__start)
        fp = sp;
        usp = sp;
+#ifdef CONFIG_EARLY_PRINTK
+        SP += -12;
+        call _init_early_exception_vectors;
+        SP += 12;
+#endif
        /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
        call _bf53x_relocate_l1_mem;
 #if CONFIG_BFIN_KERNEL_CLOCK
@@ -264,7 +240,7 @@ ENTRY(__start)
        p0.l = .LWAIT_HERE;
        p0.h = .LWAIT_HERE;
        reti = p0;
-#if defined(ANOMALY_05000281)
+#if ANOMALY_05000281
        nop; nop; nop;
 #endif
        rti;
@@ -417,8 +393,8 @@ ENTRY(_start_dma_code)
        w[p0] = r0.l;
        ssync;
-        p0.l = (EBIU_SDBCTL & 0xFFFF);
+        p0.l = LO(EBIU_SDBCTL);
-        p0.h = (EBIU_SDBCTL >> 16);     /* SDRAM Memory Bank Control Register */
+        p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */
        r0 = mem_SDBCTL;
        w[p0] = r0.l;
        ssync;
@@ -456,276 +432,6 @@ ENTRY(_start_dma_code)
 ENDPROC(_start_dma_code)
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
-ENTRY(_bfin_reset)
-        /* No more interrupts to be handled*/
-        CLI R6;
-        SSYNC;
-#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
-        p0.h = hi(FIO_INEN);
-        p0.l = lo(FIO_INEN);
-        r0.l = ~(1 << CONFIG_ENET_FLASH_PIN);
-        w[p0] = r0.l;
-        p0.h = hi(FIO_DIR);
-        p0.l = lo(FIO_DIR);
-        r0.l = (1 << CONFIG_ENET_FLASH_PIN);
-        w[p0] = r0.l;
-        p0.h = hi(FIO_FLAG_C);
-        p0.l = lo(FIO_FLAG_C);
-        r0.l = (1 << CONFIG_ENET_FLASH_PIN);
-        w[p0] = r0.l;
-#endif
-        /* Clear the IMASK register */
-        p0.h = hi(IMASK);
-        p0.l = lo(IMASK);
-        r0 = 0x0;
-        [p0] = r0;
-        /* Clear the ILAT register */
-        p0.h = hi(ILAT);
-        p0.l = lo(ILAT);
-        r0 = [p0];
-        [p0] = r0;
-        SSYNC;
-        /* make sure SYSCR is set to use BMODE */
-        P0.h = hi(SYSCR);
-        P0.l = lo(SYSCR);
-        R0.l = 0x0;
-        W[P0] = R0.l;
-        SSYNC;
-        /* issue a system soft reset */
-        P1.h = hi(SWRST);
-        P1.l = lo(SWRST);
-        R1.l = 0x0007;
-        W[P1] = R1;
-        SSYNC;
-        /* clear system soft reset */
-        R0.l = 0x0000;
-        W[P0] = R0;
-        SSYNC;
-        /* issue core reset */
-        raise 1;
-        RTS;
-ENDPROC(_bfin_reset)
-#if CONFIG_DEBUG_KERNEL_START
-debug_kernel_start_trap:
-        /* Set up a temp stack in L1 - SDRAM might not be working  */
-        P0.L = lo(L1_DATA_A_START + 0x100);
-        P0.H = hi(L1_DATA_A_START + 0x100);
-        SP = P0;
-        /* Make sure the Clocks are the way I think they should be */
-        r0 = CONFIG_VCO_MULT & 63;       /* Load the VCO multiplier         */
-        r0 = r0 << 9;                    /* Shift it over,                  */
-        r1 = CLKIN_HALF;                 /* Do we need to divide CLKIN by 2?*/
-        r0 = r1 | r0;
-        r1 = PLL_BYPASS;                 /* Bypass the PLL?                 */
-        r1 = r1 << 8;                    /* Shift it over                   */
-        r0 = r1 | r0;                    /* add them all together           */
-        p0.h = hi(PLL_CTL);
-        p0.l = lo(PLL_CTL);              /* Load the address                */
-        cli r2;                          /* Disable interrupts              */
-        ssync;
-        w[p0] = r0.l;                    /* Set the value                   */
-        idle;                            /* Wait for the PLL to stablize    */
-        sti r2;                          /* Enable interrupts               */
-.Lcheck_again1:
-        p0.h = hi(PLL_STAT);
-        p0.l = lo(PLL_STAT);
-        R0 = W[P0](Z);
-        CC = BITTST(R0,5);
-        if ! CC jump .Lcheck_again1;
-        /* Configure SCLK & CCLK Dividers */
-        r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
-        p0.h = hi(PLL_DIV);
-        p0.l = lo(PLL_DIV);
-        w[p0] = r0.l;
-        ssync;
-        /* Make sure UART is enabled - you can never be sure */
-/*
- * Setup for console. Argument comes from the menuconfig
- */
-#ifdef CONFIG_BAUD_9600
-#define CONSOLE_BAUD_RATE       9600
-#elif CONFIG_BAUD_19200
-#define CONSOLE_BAUD_RATE       19200
-#elif CONFIG_BAUD_38400
-#define CONSOLE_BAUD_RATE       38400
-#elif CONFIG_BAUD_57600
-#define CONSOLE_BAUD_RATE       57600
-#elif CONFIG_BAUD_115200
-#define CONSOLE_BAUD_RATE       115200
-#endif
-        p0.h = hi(UART_GCTL);
-        p0.l = lo(UART_GCTL);
-        r0 = 0x00(Z);
-        w[p0] = r0.L;   /* To Turn off UART clocks */
-        ssync;
-        p0.h = hi(UART_LCR);
-        p0.l = lo(UART_LCR);
-        r0 = 0x83(Z);
-        w[p0] = r0.L;   /* To enable DLL writes */
-        ssync;
-        R1 = (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_SCLK_DIV) / (CONSOLE_BAUD_RATE * 16));
-        p0.h = hi(UART_DLL);
-        p0.l = lo(UART_DLL);
-        r0 = 0xFF(Z);
-        r0 = R1 & R0;
-        w[p0] = r0.L;
-        ssync;
-        p0.h = hi(UART_DLH);
-        p0.l = lo(UART_DLH);
-        r1 >>= 8 ;
-        w[p0] = r1.L;
-        ssync;
-        p0.h = hi(UART_GCTL);
-        p0.l = lo(UART_GCTL);
-        r0 = 0x0(Z);
-        w[p0] = r0.L;   /* To enable UART clock */
-        ssync;
-        p0.h = hi(UART_LCR);
-        p0.l = lo(UART_LCR);
-        r0 = 0x03(Z);
-        w[p0] = r0.L;   /* To Turn on UART */
-        ssync;
-        p0.h = hi(UART_GCTL);
-        p0.l = lo(UART_GCTL);
-        r0 = 0x01(Z);
-        w[p0] = r0.L;   /* To Turn on UART Clocks */
-        ssync;
-        P0.h = hi(UART_THR);
-        P0.l = lo(UART_THR);
-        P1.h = hi(UART_LSR);
-        P1.l = lo(UART_LSR);
-        R0.L = 'K';
-        call .Lwait_char;
-        R0.L='e';
-        call .Lwait_char;
-        R0.L='r';
-        call .Lwait_char;
-        R0.L='n'
-        call .Lwait_char;
-        R0.L='e'
-        call .Lwait_char;
-        R0.L='l';
-        call .Lwait_char;
-        R0.L=' ';
-        call .Lwait_char;
-        R0.L='c';
-        call .Lwait_char;
-        R0.L='r';
-        call .Lwait_char;
-        R0.L='a';
-        call .Lwait_char;
-        R0.L='s';
-        call .Lwait_char;
-        R0.L='h';
-        call .Lwait_char;
-        R0.L='\r';
-        call .Lwait_char;
-        R0.L='\n';
-        call .Lwait_char;
-        R0.L='S';
-        call .Lwait_char;
-        R0.L='E';
-        call .Lwait_char;
-        R0.L='Q'
-        call .Lwait_char;
-        R0.L='S'
-        call .Lwait_char;
-        R0.L='T';
-        call .Lwait_char;
-        R0.L='A';
-        call .Lwait_char;
-        R0.L='T';
-        call .Lwait_char;
-        R0.L='=';
-        call .Lwait_char;
-        R2 = SEQSTAT;
-        call .Ldump_reg;
-        R0.L=' ';
-        call .Lwait_char;
-        R0.L='R';
-        call .Lwait_char;
-        R0.L='E'
-        call .Lwait_char;
-        R0.L='T'
-        call .Lwait_char;
-        R0.L='X';
-        call .Lwait_char;
-        R0.L='=';
-        call .Lwait_char;
-        R2 = RETX;
-        call .Ldump_reg;
-        R0.L='\r';
-        call .Lwait_char;
-        R0.L='\n';
-        call .Lwait_char;
-.Ldebug_kernel_start_trap_done:
-        JUMP    .Ldebug_kernel_start_trap_done;
-.Ldump_reg:
-        R3 = 32;
-        R4 = 0x0F;
-        R5 = ':';  /* one past 9 */
-.Ldump_reg2:
-        R0 = R2;
-        R3 += -4;
-        R0 >>>= R3;
-        R0 = R0 & R4;
-        R0 += 0x30;
-        CC = R0 <= R5;
-        if CC JUMP .Ldump_reg1;
-        R0 += 7;
-.Ldump_reg1:
-        R1.l = W[P1];
-        CC = BITTST(R1, 5);
-        if !CC JUMP .Ldump_reg1;
-        W[P0] = r0;
-        CC = R3 == 0;
-        if !CC JUMP .Ldump_reg2
-        RTS;
-.Lwait_char:
-        R1.l = W[P1];
-        CC = BITTST(R1, 5);
-        if !CC JUMP .Lwait_char;
-        W[P0] = r0;
-        RTS;
-#endif  /* CONFIG_DEBUG_KERNEL_START  */
 .data
 /*
diff --git a/arch/blackfin/mach-bf537/Kconfig b/arch/blackfin/mach-bf537/Kconfig
index cc9ae38a4dda..e6648db09519 100644
--- a/arch/blackfin/mach-bf537/Kconfig
+++ b/arch/blackfin/mach-bf537/Kconfig
@@ -2,33 +2,6 @@ if (BF537 || BF534 || BF536)
 menu "BF537 Specific Configuration"
-comment "PORT F/G Selection"
-choice
-        prompt "Select BF537/6/4 default GPIO PFx PORTx"
-        help
-          Quick Hack for BF537/6/4 default GPIO PFx PORTF.
-config BF537_PORT_F
-        bool "Select BF537/6/4 default GPIO PFx PORTF"
-        depends on (BF537 || BF536 || BF534)
-        help
-          Quick Hack for BF537/6/4 default GPIO PFx PORTF.
-config BF537_PORT_G
-        bool "Select BF537/6/4 default GPIO PFx PORTG"
-        depends on (BF537 || BF536 || BF534)
-        help
-          Quick Hack for BF537/6/4 default GPIO PFx PORTG.
-config BF537_PORT_H
-        bool "Select BF537/6/4 default GPIO PFx PORTH"
-        depends on (BF537 || BF536 || BF534)
-        help
-          Quick Hack for BF537/6/4 default GPIO PFx PORTH
-          Use only when Blackfin EMAC support is not required.
-endchoice
 comment "Interrupt Priority Assignment"
 menu "Priority"
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c
index a8f947b72754..44dea05e1d03 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c
@@ -35,7 +35,9 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/usb_isp1362.h>
+#include <linux/pata_platform.h>
 #include <linux/irq.h>
+#include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
 /*
@@ -113,7 +115,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
                .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
                .platform_data = &bfin_spi_flash_data,
                .controller_data = &spi_flash_chip_info,
@@ -125,7 +127,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
                .chip_select = 1, /* Framework chip select. */
                .platform_data = NULL, /* No spi_driver specific config */
                .controller_data = &spi_adc_chip_info,
@@ -136,7 +138,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad1836-spi",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
                .controller_data = &ad1836_spi_chip_info,
        },
@@ -146,7 +148,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad9960-spi",
                .max_speed_hz = 10000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = 1,
                .controller_data = &ad9960_spi_chip_info,
        },
@@ -156,7 +158,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "spi_mmc_dummy",
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = 7,
                .platform_data = NULL,
                .controller_data = &spi_mmc_chip_info,
@@ -165,7 +167,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "spi_mmc",
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SPI_MMC_CS_CHAN,
                .platform_data = NULL,
                .controller_data = &spi_mmc_chip_info,
@@ -174,17 +176,33 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+                },
+        [1] = {
+                .start = CH_SPI,
+                .end   = CH_SPI,
+                .flags = IORESOURCE_IRQ,
+        }
+};
 /* SPI controller data */
-static struct bfin5xx_spi_master spi_bfin_master_info = {
+static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 8,
        .enable_dma = 1,  /* master has the ability to do dma transfer */
 };
-static struct platform_device spi_bfin_master_device = {
+static struct platform_device bfin_spi0_device = {
-        .name = "bfin-spi-master",
+        .name = "bfin-spi",
-        .id = 1, /* Bus number */
+        .id = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
        .dev = {
-                .platform_data = &spi_bfin_master_info, /* Passed to driver */
+                .platform_data = &bfin_spi0_info, /* Passed to driver */
        },
 };
 #endif  /* spi master and devices */
@@ -316,6 +334,43 @@ static struct platform_device bfin_mac_device = {
 };
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#define PATA_INT        64
+static struct pata_platform_info bfin_pata_platform_data = {
+        .ioport_shift = 2,
+        .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+};
+static struct resource bfin_pata_resources[] = {
+        {
+                .start = 0x2030C000,
+                .end = 0x2030C01F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = 0x2030D018,
+                .end = 0x2030D01B,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = PATA_INT,
+                .end = PATA_INT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_pata_device = {
+        .name = "pata_platform",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(bfin_pata_resources),
+        .resource = bfin_pata_resources,
+        .dev = {
+                .platform_data = &bfin_pata_platform_data,
+        }
+};
+#endif
 static struct platform_device *cm_bf537_devices[] __initdata = {
 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
        &rtc_device,
@@ -347,7 +402,11 @@ static struct platform_device *cm_bf537_devices[] __initdata = {
 #endif
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-        &spi_bfin_master_device,
+        &bfin_spi0_device,
+#endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        &bfin_pata_device,
 #endif
 };
@@ -358,6 +417,10 @@ static int __init cm_bf537_init(void)
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
+#endif
        return 0;
 }
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c
index 648d984e98d6..5e9d09eb8579 100644
--- a/arch/blackfin/mach-bf537/boards/generic_board.c
+++ b/arch/blackfin/mach-bf537/boards/generic_board.c
@@ -8,7 +8,7 @@
 *
 * Modified:
 *               Copyright 2005 National ICT Australia (NICTA)
- *               Copyright 2004-2006 Analog Devices Inc.
+ *               Copyright 2004-2007 Analog Devices Inc.
 *
 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
@@ -34,20 +34,74 @@
 #include <linux/mtd/partitions.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
+#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 #include <linux/usb_isp1362.h>
+#endif
+#include <linux/pata_platform.h>
 #include <linux/irq.h>
+#include <linux/interrupt.h>
 #include <linux/usb_sl811.h>
+#include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
+#include <asm/reboot.h>
+#include <linux/spi/ad7877.h>
 /*
 * Name the Board for the /proc/cpuinfo
 */
-char *bfin_board_name = "UNKNOWN BOARD";
+char *bfin_board_name = "GENERIC Board";
 /*
 *  Driver needs to know address, irq and flag pin.
 */
+#define ISP1761_BASE       0x203C0000
+#define ISP1761_IRQ        IRQ_PF7
+#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
+static struct resource bfin_isp1761_resources[] = {
+        [0] = {
+                .name   = "isp1761-regs",
+                .start  = ISP1761_BASE + 0x00000000,
+                .end    = ISP1761_BASE + 0x000fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = ISP1761_IRQ,
+                .end    = ISP1761_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_isp1761_device = {
+        .name           = "isp1761",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(bfin_isp1761_resources),
+        .resource       = bfin_isp1761_resources,
+};
+static struct platform_device *bfin_isp1761_devices[] = {
+        &bfin_isp1761_device,
+};
+int __init bfin_isp1761_init(void)
+{
+        unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
+        printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
+        set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
+        return platform_add_devices(bfin_isp1761_devices, num_devices);
+}
+void __exit bfin_isp1761_exit(void)
+{
+        platform_device_unregister(&bfin_isp1761_device);
+}
+arch_initcall(bfin_isp1761_init);
+#endif
 #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
 static struct resource bfin_pcmcia_cf_resources[] = {
        {
@@ -59,10 +113,6 @@ static struct resource bfin_pcmcia_cf_resources[] = {
                .end = 0x20311FFF,
                .flags = IORESOURCE_MEM,
        }, {
-                .start = IRQ_PROG_INTA,
-                .end = IRQ_PROG_INTA,
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        }, {
                .start = IRQ_PF4,
                .end = IRQ_PF4,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
@@ -96,14 +146,7 @@ static struct resource smc91x_resources[] = {
                .end = 0x20300300 + 16,
                .flags = IORESOURCE_MEM,
        }, {
-                .start = IRQ_PROG_INTB,
-                .end = IRQ_PROG_INTB,
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        }, {
-                /*
-                 *  denotes the flag pin and is used directly if
-                 *  CONFIG_IRQCHIP_DEMUX_GPIO is defined.
-                 */
                .start = IRQ_PF7,
                .end = IRQ_PF7,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -117,6 +160,28 @@ static struct platform_device smc91x_device = {
 };
 #endif
+#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+static struct resource dm9000_resources[] = {
+        [0] = {
+                .start  = 0x203FB800,
+                .end    = 0x203FB800 + 8,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_PF9,
+                .end    = IRQ_PF9,
+                .flags  = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
+        },
+};
+static struct platform_device dm9000_device = {
+        .name           = "dm9000",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm9000_resources),
+        .resource       = dm9000_resources,
+};
+#endif
 #if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
 static struct resource sl811_hcd_resources[] = {
        {
@@ -128,12 +193,8 @@ static struct resource sl811_hcd_resources[] = {
                .end = 0x20340004,
                .flags = IORESOURCE_MEM,
        }, {
-                .start = IRQ_PROG_INTA,
+                .start = CONFIG_USB_SL811_BFIN_IRQ,
-                .end = IRQ_PROG_INTA,
+                .end = CONFIG_USB_SL811_BFIN_IRQ,
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        }, {
-                .start = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO,
-                .end = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
        },
 };
@@ -141,21 +202,19 @@ static struct resource sl811_hcd_resources[] = {
 #if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
 void sl811_port_power(struct device *dev, int is_on)
 {
-        unsigned short mask = (1<<CONFIG_USB_SL811_BFIN_GPIO_VBUS);
+        gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
+        gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS);
-        bfin_write_PORT_FER(bfin_read_PORT_FER() & ~mask);
-        bfin_write_FIO_DIR(bfin_read_FIO_DIR() | mask);
        if (is_on)
-                bfin_write_FIO_FLAG_S(mask);
+                gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
        else
-                bfin_write_FIO_FLAG_C(mask);
+                gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
 }
 #endif
 static struct sl811_platform_data sl811_priv = {
        .potpg = 10,
-        .power = 250,           /* == 500mA */
+        .power = 250,       /* == 500mA */
 #if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
        .port_power = &sl811_port_power,
 #endif
@@ -170,7 +229,6 @@ static struct platform_device sl811_hcd_device = {
        .num_resources = ARRAY_SIZE(sl811_hcd_resources),
        .resource = sl811_hcd_resources,
 };
 #endif
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
@@ -184,13 +242,9 @@ static struct resource isp1362_hcd_resources[] = {
                .end = 0x20360004,
                .flags = IORESOURCE_MEM,
        }, {
-                .start = IRQ_PROG_INTA,
+                .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
-                .end = IRQ_PROG_INTA,
+                .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
-        }, {
-                .start = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO,
-                .end = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO,
-                .flags = IORESOURCE_IRQ,
        },
 };
@@ -246,7 +300,8 @@ static struct platform_device net2272_bfin_device = {
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
 /* all SPI peripherals info goes here */
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if defined(CONFIG_MTD_M25P80) \
+        || defined(CONFIG_MTD_M25P80_MODULE)
 static struct mtd_partition bfin_spi_flash_partitions[] = {
        {
                .name = "bootloader",
@@ -302,70 +357,198 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
 };
 #endif
+#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
+static struct bfin5xx_spi_chip spi_mmc_chip_info = {
+        .enable_dma = 1,
+        .bits_per_word = 8,
+};
+#endif
+#if defined(CONFIG_PBX)
+static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
+        .ctl_reg        = 0x4, /* send zero */
+        .enable_dma     = 0,
+        .bits_per_word  = 8,
+        .cs_change_per_word = 1,
+};
+#endif
+#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
+static struct bfin5xx_spi_chip ad5304_chip_info = {
+        .enable_dma = 0,
+        .bits_per_word = 16,
+};
+#endif
+#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
+        .enable_dma = 0,
+        .bits_per_word = 16,
+};
+static const struct ad7877_platform_data bfin_ad7877_ts_info = {
+        .model                  = 7877,
+        .vref_delay_usecs       = 50,   /* internal, no capacitor */
+        .x_plate_ohms           = 419,
+        .y_plate_ohms           = 486,
+        .pressure_max           = 1000,
+        .pressure_min           = 0,
+        .stopacq_polarity       = 1,
+        .first_conversion_delay = 3,
+        .acquisition_time       = 1,
+        .averaging              = 1,
+        .pen_down_acc_interval  = 1,
+};
+#endif
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
-#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
+#if defined(CONFIG_MTD_M25P80) \
+        || defined(CONFIG_MTD_M25P80_MODULE)
        {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
-                .chip_select = 2, /* Framework chip select. On STAMP537 it is SPISSEL1*/
+                .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
                .platform_data = &bfin_spi_flash_data,
                .controller_data = &spi_flash_chip_info,
                .mode = SPI_MODE_3,
        },
 #endif
-#if defined(CONFIG_SPI_ADC_BF533) || defined(CONFIG_SPI_ADC_BF533_MODULE)
+#if defined(CONFIG_SPI_ADC_BF533) \
+        || defined(CONFIG_SPI_ADC_BF533_MODULE)
        {
                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
                .chip_select = 1, /* Framework chip select. */
                .platform_data = NULL, /* No spi_driver specific config */
                .controller_data = &spi_adc_chip_info,
        },
 #endif
-#if defined(CONFIG_SND_BLACKFIN_AD1836) || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
+#if defined(CONFIG_SND_BLACKFIN_AD1836) \
+        || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
        {
                .modalias = "ad1836-spi",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
 #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
        {
                .modalias = "ad9960-spi",
                .max_speed_hz = 10000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = 1,
                .controller_data = &ad9960_spi_chip_info,
        },
 #endif
+#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
+        {
+                .modalias = "spi_mmc_dummy",
+                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 0,
+                .platform_data = NULL,
+                .controller_data = &spi_mmc_chip_info,
+                .mode = SPI_MODE_3,
+        },
+        {
+                .modalias = "spi_mmc",
+                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = CONFIG_SPI_MMC_CS_CHAN,
+                .platform_data = NULL,
+                .controller_data = &spi_mmc_chip_info,
+                .mode = SPI_MODE_3,
+        },
+#endif
+#if defined(CONFIG_PBX)
+        {
+                .modalias = "fxs-spi",
+                .max_speed_hz = 12500000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 8 - CONFIG_J11_JUMPER,
+                .controller_data = &spi_si3xxx_chip_info,
+                .mode = SPI_MODE_3,
+        },
+        {
+                .modalias = "fxo-spi",
+                .max_speed_hz = 12500000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 8 - CONFIG_J19_JUMPER,
+                .controller_data = &spi_si3xxx_chip_info,
+                .mode = SPI_MODE_3,
+        },
+#endif
+#if defined(CONFIG_AD5304) || defined(CONFIG_AD5304_MODULE)
+        {
+                .modalias = "ad5304_spi",
+                .max_speed_hz = 1250000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0,
+                .chip_select = 2,
+                .platform_data = NULL,
+                .controller_data = &ad5304_chip_info,
+                .mode = SPI_MODE_2,
+        },
+#endif
+#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+        {
+                .modalias               = "ad7877",
+                .platform_data          = &bfin_ad7877_ts_info,
+                .irq                    = IRQ_PF6,
+                .max_speed_hz   = 12500000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num        = 1,
+                .chip_select  = 1,
+                .controller_data = &spi_ad7877_chip_info,
+        },
+#endif
 };
 /* SPI controller data */
-static struct bfin5xx_spi_master spi_bfin_master_info = {
+static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 8,
        .enable_dma = 1,  /* master has the ability to do dma transfer */
 };
-static struct platform_device spi_bfin_master_device = {
+/* SPI (0) */
-        .name = "bfin-spi-master",
+static struct resource bfin_spi0_resource[] = {
-        .id = 1, /* Bus number */
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+                },
+        [1] = {
+                .start = CH_SPI,
+                .end   = CH_SPI,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_spi0_device = {
+        .name = "bfin-spi",
+        .id = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
        .dev = {
-                .platform_data = &spi_bfin_master_info, /* Passed to driver */
+                .platform_data = &bfin_spi0_info, /* Passed to driver */
        },
 };
 #endif  /* spi master and devices */
 #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
 static struct platform_device bfin_fb_device = {
-        .name = "bf537-fb",
+        .name = "bf537-lq035",
+};
+#endif
+#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+static struct platform_device bfin_fb_adv7393_device = {
+        .name = "bfin-adv7393",
 };
 #endif
@@ -390,15 +573,86 @@ static struct platform_device bfin_uart_device = {
 };
 #endif
-static struct platform_device *stamp_devices[] __initdata = {
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
-#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+static struct resource bfin_twi0_resource[] = {
-        &rtc_device,
+        [0] = {
+                .start = TWI0_REGBASE,
+                .end   = TWI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_TWI,
+                .end   = IRQ_TWI,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device i2c_bfin_twi_device = {
+        .name = "i2c-bfin-twi",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
+        .resource = bfin_twi0_resource,
+};
+#endif
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+static struct platform_device bfin_sport0_uart_device = {
+        .name = "bfin-sport-uart",
+        .id = 0,
+};
+static struct platform_device bfin_sport1_uart_device = {
+        .name = "bfin-sport-uart",
+        .id = 1,
+};
+#endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#define PATA_INT        55
+static struct pata_platform_info bfin_pata_platform_data = {
+        .ioport_shift = 1,
+        .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+};
+static struct resource bfin_pata_resources[] = {
+        {
+                .start = 0x20314020,
+                .end = 0x2031403F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = 0x2031401C,
+                .end = 0x2031401F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = PATA_INT,
+                .end = PATA_INT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_pata_device = {
+        .name = "pata_platform",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(bfin_pata_resources),
+        .resource = bfin_pata_resources,
+        .dev = {
+                .platform_data = &bfin_pata_platform_data,
+        }
+};
 #endif
+static struct platform_device *stamp_devices[] __initdata = {
 #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
        &bfin_pcmcia_cf_device,
 #endif
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+        &rtc_device,
+#endif
 #if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
        &sl811_hcd_device,
 #endif
@@ -411,6 +665,10 @@ static struct platform_device *stamp_devices[] __initdata = {
        &smc91x_device,
 #endif
+#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
+        &dm9000_device,
+#endif
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
        &bfin_mac_device,
 #endif
@@ -420,16 +678,33 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-        &spi_bfin_master_device,
+        &bfin_spi0_device,
 #endif
 #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
        &bfin_fb_device,
 #endif
+#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+        &bfin_fb_adv7393_device,
+#endif
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
        &bfin_uart_device,
 #endif
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+        &i2c_bfin_twi_device,
+#endif
+#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
+        &bfin_sport0_uart_device,
+        &bfin_sport1_uart_device,
+#endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        &bfin_pata_device,
+#endif
 };
 static int __init stamp_init(void)
@@ -437,9 +712,21 @@ static int __init stamp_init(void)
        printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
        platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
+        spi_register_board_info(bfin_spi_board_info,
+                                ARRAY_SIZE(bfin_spi_board_info));
+#endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
 #endif
        return 0;
 }
 arch_initcall(stamp_init);
+void native_machine_restart(char *cmd)
+{
+        /* workaround reboot hang when booting from SPI */
+        if ((bfin_read_SYSCR() & 0x7) == 0x3)
+                bfin_gpio_reset_spi0_ssel1();
+}
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 8806f1230f2d..20507e92a3a4 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -38,6 +38,7 @@
 #include <linux/usb_isp1362.h>
 #endif
 #include <linux/irq.h>
+#include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
 #include <linux/usb_sl811.h>
@@ -130,15 +131,13 @@ static struct resource sl811_hcd_resources[] = {
 #if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
 void sl811_port_power(struct device *dev, int is_on)
 {
-        unsigned short mask = (1 << CONFIG_USB_SL811_BFIN_GPIO_VBUS);
+        gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
+        gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS);
-        bfin_write_PORT_FER(bfin_read_PORT_FER() & ~mask);
-        bfin_write_FIO_DIR(bfin_read_FIO_DIR() | mask);
        if (is_on)
-                bfin_write_FIO_FLAG_S(mask);
+                gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
        else
-                bfin_write_FIO_FLAG_C(mask);
+                gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
 }
 #endif
@@ -323,7 +322,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
                .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
                .platform_data = &bfin_spi_flash_data,
                .controller_data = &spi_flash_chip_info,
@@ -336,7 +335,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
                .chip_select = 1, /* Framework chip select. */
                .platform_data = NULL, /* No spi_driver specific config */
                .controller_data = &spi_adc_chip_info,
@@ -348,7 +347,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad1836-spi",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
                .controller_data = &ad1836_spi_chip_info,
        },
@@ -357,7 +356,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad9960-spi",
                .max_speed_hz = 10000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = 1,
                .controller_data = &ad9960_spi_chip_info,
        },
@@ -366,7 +365,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "spi_mmc_dummy",
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = 7,
                .platform_data = NULL,
                .controller_data = &spi_mmc_chip_info,
@@ -375,7 +374,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "spi_mmc",
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SPI_MMC_CS_CHAN,
                .platform_data = NULL,
                .controller_data = &spi_mmc_chip_info,
@@ -396,24 +395,40 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 };
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+                },
+        [1] = {
+                .start = CH_SPI,
+                .end   = CH_SPI,
+                .flags = IORESOURCE_IRQ,
+        }
+};
 /* SPI controller data */
-static struct bfin5xx_spi_master spi_bfin_master_info = {
+static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 8,
        .enable_dma = 1,  /* master has the ability to do dma transfer */
 };
-static struct platform_device spi_bfin_master_device = {
+static struct platform_device bfin_spi0_device = {
-        .name = "bfin-spi-master",
+        .name = "bfin-spi",
-        .id = 1, /* Bus number */
+        .id = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
        .dev = {
-                .platform_data = &spi_bfin_master_info, /* Passed to driver */
+                .platform_data = &bfin_spi0_info, /* Passed to driver */
        },
 };
 #endif  /* spi master and devices */
 #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
 static struct platform_device bfin_fb_device = {
-        .name = "bf537-fb",
+        .name = "bf537-lq035",
 };
 #endif
@@ -469,7 +484,7 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-        &spi_bfin_master_device,
+        &bfin_spi0_device,
 #endif
 #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 9c43d7756510..47d7d4a0e73d 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -37,10 +37,13 @@
 #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
 #include <linux/usb_isp1362.h>
 #endif
+#include <linux/pata_platform.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/usb_sl811.h>
+#include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
+#include <asm/reboot.h>
 #include <linux/spi/ad7877.h>
 /*
@@ -199,15 +202,13 @@ static struct resource sl811_hcd_resources[] = {
 #if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
 void sl811_port_power(struct device *dev, int is_on)
 {
-        unsigned short mask = (1 << CONFIG_USB_SL811_BFIN_GPIO_VBUS);
+        gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
+        gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS);
-        bfin_write_PORT_FER(bfin_read_PORT_FER() & ~mask);
-        bfin_write_FIO_DIR(bfin_read_FIO_DIR() | mask);
        if (is_on)
-                bfin_write_FIO_FLAG_S(mask);
+                gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 1);
        else
-                bfin_write_FIO_FLAG_C(mask);
+                gpio_set_value(CONFIG_USB_SL811_BFIN_GPIO_VBUS, 0);
 }
 #endif
@@ -407,7 +408,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
                .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
                .platform_data = &bfin_spi_flash_data,
                .controller_data = &spi_flash_chip_info,
@@ -420,7 +421,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
                .chip_select = 1, /* Framework chip select. */
                .platform_data = NULL, /* No spi_driver specific config */
                .controller_data = &spi_adc_chip_info,
@@ -432,7 +433,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad1836-spi",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
                .controller_data = &ad1836_spi_chip_info,
        },
@@ -441,7 +442,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad9960-spi",
                .max_speed_hz = 10000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = 1,
                .controller_data = &ad9960_spi_chip_info,
        },
@@ -450,7 +451,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "spi_mmc_dummy",
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = 0,
                .platform_data = NULL,
                .controller_data = &spi_mmc_chip_info,
@@ -459,7 +460,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "spi_mmc",
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SPI_MMC_CS_CHAN,
                .platform_data = NULL,
                .controller_data = &spi_mmc_chip_info,
@@ -470,16 +471,16 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "fxs-spi",
                .max_speed_hz = 12500000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
-                .chip_select = 3,
+                .chip_select = 8 - CONFIG_J11_JUMPER,
                .controller_data = &spi_si3xxx_chip_info,
                .mode = SPI_MODE_3,
        },
        {
                .modalias = "fxo-spi",
                .max_speed_hz = 12500000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
-                .chip_select = 2,
+                .chip_select = 8 - CONFIG_J19_JUMPER,
                .controller_data = &spi_si3xxx_chip_info,
                .mode = SPI_MODE_3,
        },
@@ -488,7 +489,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad5304_spi",
                .max_speed_hz = 1250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = 2,
                .platform_data = NULL,
                .controller_data = &ad5304_chip_info,
@@ -509,23 +510,45 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 };
 /* SPI controller data */
-static struct bfin5xx_spi_master spi_bfin_master_info = {
+static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 8,
        .enable_dma = 1,  /* master has the ability to do dma transfer */
 };
-static struct platform_device spi_bfin_master_device = {
+/* SPI (0) */
-        .name = "bfin-spi-master",
+static struct resource bfin_spi0_resource[] = {
-        .id = 1, /* Bus number */
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+                },
+        [1] = {
+                .start = CH_SPI,
+                .end   = CH_SPI,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_spi0_device = {
+        .name = "bfin-spi",
+        .id = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
        .dev = {
-                .platform_data = &spi_bfin_master_info, /* Passed to driver */
+                .platform_data = &bfin_spi0_info, /* Passed to driver */
        },
 };
 #endif  /* spi master and devices */
 #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
 static struct platform_device bfin_fb_device = {
-        .name = "bf537-fb",
+        .name = "bf537-lq035",
+};
+#endif
+#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+static struct platform_device bfin_fb_adv7393_device = {
+        .name = "bfin-adv7393",
 };
 #endif
@@ -551,9 +574,24 @@ static struct platform_device bfin_uart_device = {
 #endif
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static struct resource bfin_twi0_resource[] = {
+        [0] = {
+                .start = TWI0_REGBASE,
+                .end   = TWI0_REGBASE,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_TWI,
+                .end   = IRQ_TWI,
+                .flags = IORESOURCE_IRQ,
+        },
+};
 static struct platform_device i2c_bfin_twi_device = {
        .name = "i2c-bfin-twi",
        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
+        .resource = bfin_twi0_resource,
 };
 #endif
@@ -569,6 +607,43 @@ static struct platform_device bfin_sport1_uart_device = {
 };
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#define PATA_INT        55
+static struct pata_platform_info bfin_pata_platform_data = {
+        .ioport_shift = 1,
+        .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+};
+static struct resource bfin_pata_resources[] = {
+        {
+                .start = 0x20314020,
+                .end = 0x2031403F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = 0x2031401C,
+                .end = 0x2031401F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = PATA_INT,
+                .end = PATA_INT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_pata_device = {
+        .name = "pata_platform",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(bfin_pata_resources),
+        .resource = bfin_pata_resources,
+        .dev = {
+                .platform_data = &bfin_pata_platform_data,
+        }
+};
+#endif
 static struct platform_device *stamp_devices[] __initdata = {
 #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
        &bfin_pcmcia_cf_device,
@@ -603,13 +678,17 @@ static struct platform_device *stamp_devices[] __initdata = {
 #endif
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-        &spi_bfin_master_device,
+        &bfin_spi0_device,
 #endif
 #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
        &bfin_fb_device,
 #endif
+#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
+        &bfin_fb_adv7393_device,
+#endif
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
        &bfin_uart_device,
 #endif
@@ -622,6 +701,10 @@ static struct platform_device *stamp_devices[] __initdata = {
        &bfin_sport0_uart_device,
        &bfin_sport1_uart_device,
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        &bfin_pata_device,
+#endif
 };
 static int __init stamp_init(void)
@@ -632,7 +715,18 @@ static int __init stamp_init(void)
        spi_register_board_info(bfin_spi_board_info,
                                ARRAY_SIZE(bfin_spi_board_info));
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
+#endif
        return 0;
 }
 arch_initcall(stamp_init);
+void native_machine_restart(char *cmd)
+{
+        /* workaround reboot hang when booting from SPI */
+        if ((bfin_read_SYSCR() & 0x7) == 0x3)
+                bfin_gpio_reset_spi0_ssel1();
+}
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 429c8a1019da..3014fe8dd155 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -33,6 +33,7 @@
 #include <asm/trace.h>
 #if CONFIG_BFIN_KERNEL_CLOCK
+#include <asm/mach-common/clocks.h>
 #include <asm/mach/mem_init.h>
 #endif
@@ -50,10 +51,12 @@ __INIT
 ENTRY(__start)
        /* R0: argument of command line string, passed from uboot, save it */
        R7 = R0;
-        /* Set the SYSCFG register:
+        /* Enable Cycle Counter and Nesting Of Interrupts */
-         * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
+#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
-         */
+        R0 = SYSCFG_SNEN;
-        R0 = 0x36;
+#else
+        R0 = SYSCFG_SNEN | SYSCFG_CCEN;
+#endif
        SYSCFG = R0;
        R0 = 0;
@@ -95,43 +98,43 @@ ENTRY(__start)
        M2 = r0;
        M3 = r0;
-        trace_buffer_start(p0,r0);
+        trace_buffer_init(p0,r0);
        P0 = R1;
        R0 = R1;
        /* Turn off the icache */
-        p0.l = (IMEM_CONTROL & 0xFFFF);
+        p0.l = LO(IMEM_CONTROL);
-        p0.h = (IMEM_CONTROL >> 16);
+        p0.h = HI(IMEM_CONTROL);
        R1 = [p0];
        R0 = ~ENICPLB;
        R0 = R0 & R1;
        /* Anomaly 05000125 */
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        CLI R2;
        SSYNC;
 #endif
        [p0] = R0;
        SSYNC;
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        STI R2;
 #endif
        /* Turn off the dcache */
-        p0.l = (DMEM_CONTROL & 0xFFFF);
+        p0.l = LO(DMEM_CONTROL);
-        p0.h = (DMEM_CONTROL >> 16);
+        p0.h = HI(DMEM_CONTROL);
        R1 = [p0];
        R0 = ~ENDCPLB;
        R0 = R0 & R1;
        /* Anomaly 05000125 */
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        CLI R2;
        SSYNC;
 #endif
        [p0] = R0;
        SSYNC;
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        STI R2;
 #endif
@@ -141,12 +144,12 @@ ENTRY(__start)
         */
        p0.h = hi(BFIN_PORT_MUX);
        p0.l = lo(BFIN_PORT_MUX);
-#ifdef ANOMALY_05000212
+#if ANOMALY_05000212
        R0.L = W[P0]; /* Read */
        SSYNC;
 #endif
        R0 = (PGDE_UART | PFTE_UART)(Z);
-#ifdef ANOMALY_05000212
+#if ANOMALY_05000212
        W[P0] = R0.L; /* Write */
        SSYNC;
 #endif
@@ -155,12 +158,12 @@ ENTRY(__start)
        p0.h = hi(PORTF_FER);
        p0.l = lo(PORTF_FER);
-#ifdef ANOMALY_05000212
+#if ANOMALY_05000212
        R0.L = W[P0]; /* Read */
        SSYNC;
 #endif
        R0 = 0x000F(Z);
-#ifdef ANOMALY_05000212
+#if ANOMALY_05000212
        W[P0] = R0.L; /* Write */
        SSYNC;
 #endif
@@ -221,6 +224,12 @@ ENTRY(__start)
        fp = sp;
        usp = sp;
+#ifdef CONFIG_EARLY_PRINTK
+        SP += -12;
+        call _init_early_exception_vectors;
+        SP += 12;
+#endif
        /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
        call _bf53x_relocate_l1_mem;
 #if CONFIG_BFIN_KERNEL_CLOCK
@@ -274,7 +283,7 @@ ENTRY(__start)
        p0.l = .LWAIT_HERE;
        p0.h = .LWAIT_HERE;
        reti = p0;
-#if defined(ANOMALY_05000281)
+#if ANOMALY_05000281
        nop; nop; nop;
 #endif
        rti;
@@ -436,8 +445,8 @@ ENTRY(_start_dma_code)
        w[p0] = r0.l;
        ssync;
-        p0.l = (EBIU_SDBCTL & 0xFFFF);
+        p0.l = LO(EBIU_SDBCTL);
-        p0.h = (EBIU_SDBCTL >> 16);     /* SDRAM Memory Bank Control Register */
+        p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */
        r0 = mem_SDBCTL;
        w[p0] = r0.l;
        ssync;
@@ -475,85 +484,6 @@ ENTRY(_start_dma_code)
 ENDPROC(_start_dma_code)
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
-ENTRY(_bfin_reset)
-        /* No more interrupts to be handled*/
-        CLI R6;
-        SSYNC;
-#if defined(CONFIG_MTD_M25P80)
-        /*
-         * The following code fix the SPI flash reboot issue,
-         * /CS signal of the chip which is using PF10 return to GPIO mode
-         */
-        p0.h = hi(PORTF_FER);
-        p0.l = lo(PORTF_FER);
-        r0.l = 0x0000;
-        w[p0] = r0.l;
-        SSYNC;
-        /* /CS return to high */
-        p0.h = hi(PORTFIO);
-        p0.l = lo(PORTFIO);
-        r0.l = 0xFFFF;
-        w[p0] = r0.l;
-        SSYNC;
-        /* Delay some time, This is necessary */
-        r1.h = 0;
-        r1.l = 0x400;
-        p1   = r1;
-        lsetup (.L_delay_lab1, .L_delay_lab1_end) lc1 = p1;
-.L_delay_lab1:
-        r0.h = 0;
-        r0.l = 0x8000;
-        p0   = r0;
-        lsetup (.L_delay_lab0, .L_delay_lab0_end) lc0 = p0;
-.L_delay_lab0:
-        nop;
-.L_delay_lab0_end:
-        nop;
-.L_delay_lab1_end:
-        nop;
-#endif
-        /* Clear the IMASK register */
-        p0.h = hi(IMASK);
-        p0.l = lo(IMASK);
-        r0 = 0x0;
-        [p0] = r0;
-        /* Clear the ILAT register */
-        p0.h = hi(ILAT);
-        p0.l = lo(ILAT);
-        r0 = [p0];
-        [p0] = r0;
-        SSYNC;
-        /* make sure SYSCR is set to use BMODE */
-        P0.h = hi(SYSCR);
-        P0.l = lo(SYSCR);
-        R0.l = 0x0;
-        W[P0] = R0.l;
-        SSYNC;
-        /* issue a system soft reset */
-        P1.h = hi(SWRST);
-        P1.l = lo(SWRST);
-        R1.l = 0x0007;
-        W[P1] = R1;
-        SSYNC;
-        /* clear system soft reset */
-        R0.l = 0x0000;
-        W[P0] = R0;
-        SSYNC;
-        /* issue core reset */
-        raise 1;
-        RTS;
-ENDPROC(_bfin_reset)
 .data
 /*
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
index e78b03d56c7c..08d8dc83701c 100644
--- a/arch/blackfin/mach-bf548/Kconfig
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -2,6 +2,13 @@ if (BF54x)
 menu "BF548 Specific Configuration"
+config DEB_DMA_URGENT
+        bool "DMA has priority over core for ext. accesses"
+        depends on BF54x
+        default n
+        help
+          Treat any DEB1, DEB2 and DEB3 request as Urgent
 comment "Interrupt Priority Assignment"
 menu "Priority"
@@ -282,7 +289,7 @@ menu "Assignment"
 config PINTx_REASSIGN
        bool "Reprogram PINT Assignment"
-        default n
+        default y
        help
          The interrupt assignment registers controls the pin-to-interrupt
          assignment in a byte-wide manner. Each option allows you to select
@@ -303,7 +310,7 @@ config PINT1_ASSIGN
 config PINT2_ASSIGN
        hex "PINT2_ASSIGN"
        depends on PINTx_REASSIGN
-        default 0x00000101
+        default 0x07000101
 config PINT3_ASSIGN
        hex "PINT3_ASSIGN"
        depends on PINTx_REASSIGN
diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile
index 060ad78ebf1d..7e7c9c8ac5b2 100644
--- a/arch/blackfin/mach-bf548/Makefile
+++ b/arch/blackfin/mach-bf548/Makefile
@@ -4,6 +4,6 @@
 extra-y := head.o
-obj-y := ints-priority.o dma.o gpio.o
+obj-y := ints-priority.o dma.o
 obj-$(CONFIG_CPU_FREQ)   += cpu.o
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 96ad95fab1a8..2c47db494f7d 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -35,9 +35,16 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/irq.h>
-#include <linux/irq.h>
 #include <linux/interrupt.h>
+#include <linux/usb/musb.h>
 #include <asm/bfin5xx_spi.h>
+#include <asm/cplb.h>
+#include <asm/dma.h>
+#include <asm/gpio.h>
+#include <asm/nand.h>
+#include <asm/mach/bf54x_keys.h>
+#include <linux/input.h>
+#include <linux/spi/ad7877.h>
 /*
 * Name the Board for the /proc/cpuinfo
@@ -48,6 +55,88 @@ char *bfin_board_name = "ADSP-BF548-EZKIT";
 *  Driver needs to know address, irq and flag pin.
 */
+#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
+#include <asm/mach/bf54x-lq043.h>
+static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
+        .width =        480,
+        .height =       272,
+        .xres =         {480, 480, 480},
+        .yres =         {272, 272, 272},
+        .bpp =          {24, 24, 24},
+        .disp =         GPIO_PE3,
+};
+static struct resource bf54x_lq043_resources[] = {
+        {
+                .start = IRQ_EPPI0_ERR,
+                .end = IRQ_EPPI0_ERR,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bf54x_lq043_device = {
+        .name           = "bf54x-lq043",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(bf54x_lq043_resources),
+        .resource       = bf54x_lq043_resources,
+        .dev            = {
+                .platform_data = &bf54x_lq043_data,
+        },
+};
+#endif
+#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
+static int bf548_keymap[] = {
+        KEYVAL(0, 0, KEY_ENTER),
+        KEYVAL(0, 1, KEY_HELP),
+        KEYVAL(0, 2, KEY_0),
+        KEYVAL(0, 3, KEY_BACKSPACE),
+        KEYVAL(1, 0, KEY_TAB),
+        KEYVAL(1, 1, KEY_9),
+        KEYVAL(1, 2, KEY_8),
+        KEYVAL(1, 3, KEY_7),
+        KEYVAL(2, 0, KEY_DOWN),
+        KEYVAL(2, 1, KEY_6),
+        KEYVAL(2, 2, KEY_5),
+        KEYVAL(2, 3, KEY_4),
+        KEYVAL(3, 0, KEY_UP),
+        KEYVAL(3, 1, KEY_3),
+        KEYVAL(3, 2, KEY_2),
+        KEYVAL(3, 3, KEY_1),
+};
+static struct bfin_kpad_platform_data bf54x_kpad_data = {
+        .rows                   = 4,
+        .cols                   = 4,
+        .keymap                 = bf548_keymap,
+        .keymapsize             = ARRAY_SIZE(bf548_keymap),
+        .repeat                 = 0,
+        .debounce_time          = 5000, /* ns (5ms) */
+        .coldrive_time          = 1000, /* ns (1ms) */
+        .keyup_test_interval    = 50, /* ms (50ms) */
+};
+static struct resource bf54x_kpad_resources[] = {
+        {
+                .start = IRQ_KEY,
+                .end = IRQ_KEY,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bf54x_kpad_device = {
+        .name           = "bf54x-keys",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(bf54x_kpad_resources),
+        .resource       = bf54x_kpad_resources,
+        .dev            = {
+                .platform_data = &bf54x_kpad_data,
+        },
+};
+#endif
 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
 static struct platform_device rtc_device = {
        .name = "rtc-bfin",
@@ -94,6 +183,344 @@ static struct platform_device bfin_uart_device = {
 };
 #endif
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+static struct resource smsc911x_resources[] = {
+        {
+                .name = "smsc911x-memory",
+                .start = 0x24000000,
+                .end = 0x24000000 + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_PE8,
+                .end = IRQ_PE8,
+                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+        },
+};
+static struct platform_device smsc911x_device = {
+        .name = "smsc911x",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(smsc911x_resources),
+        .resource = smsc911x_resources,
+};
+#endif
+#if defined(CONFIG_USB_BF54x_HCD) || defined(CONFIG_USB_BF54x_HCD_MODULE)
+static struct resource bf54x_hcd_resources[] = {
+        {
+                .start = 0xFFC03C00,
+                .end = 0xFFC040FF,
+                .flags = IORESOURCE_MEM,
+        },
+};
+static struct platform_device bf54x_hcd = {
+        .name = "bf54x-hcd",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bf54x_hcd_resources),
+        .resource = bf54x_hcd_resources,
+};
+#endif
+#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+static struct resource musb_resources[] = {
+        [0] = {
+                .start  = 0xFFC03C00,
+                .end    = 0xFFC040FF,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = { /* general IRQ */
+                .start  = IRQ_USB_INT0,
+                .end    = IRQ_USB_INT0,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+        },
+        [2] = { /* DMA IRQ */
+                .start  = IRQ_USB_DMA,
+                .end    = IRQ_USB_DMA,
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+        },
+};
+static struct musb_hdrc_platform_data musb_plat = {
+#ifdef CONFIG_USB_MUSB_OTG
+        .mode           = MUSB_OTG,
+#elif CONFIG_USB_MUSB_HDRC_HCD
+        .mode           = MUSB_HOST,
+#elif CONFIG_USB_GADGET_MUSB_HDRC
+        .mode           = MUSB_PERIPHERAL,
+#endif
+        .multipoint     = 1,
+};
+static u64 musb_dmamask = ~(u32)0;
+static struct platform_device musb_device = {
+        .name           = "musb_hdrc",
+        .id             = 0,
+        .dev = {
+                .dma_mask               = &musb_dmamask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &musb_plat,
+        },
+        .num_resources  = ARRAY_SIZE(musb_resources),
+        .resource       = musb_resources,
+};
+#endif
+#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
+static struct resource bfin_atapi_resources[] = {
+        {
+                .start = 0xFFC03800,
+                .end = 0xFFC0386F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_ATAPI_ERR,
+                .end = IRQ_ATAPI_ERR,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_atapi_device = {
+        .name = "pata-bf54x",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(bfin_atapi_resources),
+        .resource = bfin_atapi_resources,
+};
+#endif
+#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+static struct mtd_partition partition_info[] = {
+        {
+                .name = "Linux Kernel",
+                .offset = 0,
+                .size = 4 * SIZE_1M,
+        },
+        {
+                .name = "File System",
+                .offset = 4 * SIZE_1M,
+                .size = (256 - 4) * SIZE_1M,
+        },
+};
+static struct bf5xx_nand_platform bf5xx_nand_platform = {
+        .page_size = NFC_PG_SIZE_256,
+        .data_width = NFC_NWIDTH_8,
+        .partitions = partition_info,
+        .nr_partitions = ARRAY_SIZE(partition_info),
+        .rd_dly = 3,
+        .wr_dly = 3,
+};
+static struct resource bf5xx_nand_resources[] = {
+        {
+                .start = 0xFFC03B00,
+                .end = 0xFFC03B4F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = CH_NFC,
+                .end = CH_NFC,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bf5xx_nand_device = {
+        .name = "bf5xx-nand",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
+        .resource = bf5xx_nand_resources,
+        .dev = {
+                .platform_data = &bf5xx_nand_platform,
+        },
+};
+#endif
+#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN)
+static struct platform_device bf54x_sdh_device = {
+        .name = "bfin-sdh",
+        .id = 0,
+};
+#endif
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+/* all SPI peripherals info goes here */
+#if defined(CONFIG_MTD_M25P80) \
+        || defined(CONFIG_MTD_M25P80_MODULE)
+/* SPI flash chip (m25p16) */
+static struct mtd_partition bfin_spi_flash_partitions[] = {
+        {
+                .name = "bootloader",
+                .size = 0x00040000,
+                .offset = 0,
+                .mask_flags = MTD_CAP_ROM
+        }, {
+                .name = "linux kernel",
+                .size = 0x1c0000,
+                .offset = 0x40000
+        }
+};
+static struct flash_platform_data bfin_spi_flash_data = {
+        .name = "m25p80",
+        .parts = bfin_spi_flash_partitions,
+        .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
+        .type = "m25p16",
+};
+static struct bfin5xx_spi_chip spi_flash_chip_info = {
+        .enable_dma = 0,         /* use dma transfer with this chip*/
+        .bits_per_word = 8,
+        .cs_change_per_word = 0,
+};
+#endif
+#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
+        .cs_change_per_word = 1,
+        .enable_dma = 0,
+        .bits_per_word = 16,
+};
+static const struct ad7877_platform_data bfin_ad7877_ts_info = {
+        .model                  = 7877,
+        .vref_delay_usecs       = 50,   /* internal, no capacitor */
+        .x_plate_ohms           = 419,
+        .y_plate_ohms           = 486,
+        .pressure_max           = 1000,
+        .pressure_min           = 0,
+        .stopacq_polarity       = 1,
+        .first_conversion_delay = 3,
+        .acquisition_time       = 1,
+        .averaging              = 1,
+        .pen_down_acc_interval  = 1,
+};
+#endif
+static struct spi_board_info bf54x_spi_board_info[] __initdata = {
+#if defined(CONFIG_MTD_M25P80) \
+        || defined(CONFIG_MTD_M25P80_MODULE)
+        {
+                /* the modalias must be the same as spi device driver name */
+                .modalias = "m25p80", /* Name of spi_driver for this device */
+                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
+                .bus_num = 0, /* Framework bus number */
+                .chip_select = 1, /* SPI_SSEL1*/
+                .platform_data = &bfin_spi_flash_data,
+                .controller_data = &spi_flash_chip_info,
+                .mode = SPI_MODE_3,
+        },
+#endif
+#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
+{
+        .modalias               = "ad7877",
+        .platform_data          = &bfin_ad7877_ts_info,
+        .irq                    = IRQ_PJ11,
+        .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
+        .bus_num                = 0,
+        .chip_select            = 2,
+        .controller_data = &spi_ad7877_chip_info,
+},
+#endif
+};
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CH_SPI0,
+                .end   = CH_SPI0,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+/* SPI (1) */
+static struct resource bfin_spi1_resource[] = {
+        [0] = {
+                .start = SPI1_REGBASE,
+                .end   = SPI1_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CH_SPI1,
+                .end   = CH_SPI1,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+/* SPI controller data */
+static struct bfin5xx_spi_master bf54x_spi_master_info = {
+        .num_chipselect = 8,
+        .enable_dma = 1,  /* master has the ability to do dma transfer */
+};
+static struct platform_device bf54x_spi_master0 = {
+        .name = "bfin-spi",
+        .id = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
+        .dev = {
+                .platform_data = &bf54x_spi_master_info, /* Passed to driver */
+                },
+};
+static struct platform_device bf54x_spi_master1 = {
+        .name = "bfin-spi",
+        .id = 1, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi1_resource),
+        .resource = bfin_spi1_resource,
+        .dev = {
+                .platform_data = &bf54x_spi_master_info, /* Passed to driver */
+                },
+};
+#endif  /* spi master and devices */
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static struct resource bfin_twi0_resource[] = {
+        [0] = {
+                .start = TWI0_REGBASE,
+                .end   = TWI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_TWI0,
+                .end   = IRQ_TWI0,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device i2c_bfin_twi0_device = {
+        .name = "i2c-bfin-twi",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
+        .resource = bfin_twi0_resource,
+};
+static struct resource bfin_twi1_resource[] = {
+        [0] = {
+                .start = TWI1_REGBASE,
+                .end   = TWI1_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_TWI1,
+                .end   = IRQ_TWI1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device i2c_bfin_twi1_device = {
+        .name = "i2c-bfin-twi",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(bfin_twi1_resource),
+        .resource = bfin_twi1_resource,
+};
+#endif
 static struct platform_device *ezkit_devices[] __initdata = {
 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
        &rtc_device,
@@ -102,12 +529,60 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
        &bfin_uart_device,
 #endif
+#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
+        &bf54x_lq043_device,
+#endif
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+        &smsc911x_device,
+#endif
+#if defined(CONFIG_USB_BF54x_HCD) || defined(CONFIG_USB_BF54x_HCD_MODULE)
+        &bf54x_hcd,
+#endif
+#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
+        &musb_device,
+#endif
+#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
+        &bfin_atapi_device,
+#endif
+#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
+        &bf5xx_nand_device,
+#endif
+#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN)
+        &bf54x_sdh_device,
+#endif
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+        &bf54x_spi_master0,
+/*      &bf54x_spi_master1,*/
+#endif
+#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
+        &bf54x_kpad_device,
+#endif
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+        &i2c_bfin_twi0_device,
+        &i2c_bfin_twi1_device,
+#endif
 };
 static int __init stamp_init(void)
 {
        printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
        platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+        spi_register_board_info(bf54x_spi_board_info,
+                        ARRAY_SIZE(bf54x_spi_board_info));
+#endif
        return 0;
 }
diff --git a/arch/blackfin/mach-bf548/gpio.c b/arch/blackfin/mach-bf548/gpio.c
deleted file mode 100644
index 0da5f0003b8c..000000000000
--- a/arch/blackfin/mach-bf548/gpio.c
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * File:         arch/blackfin/mach-bf548/gpio.c
- * Based on:
- * Author:       Michael Hennerich (hennerich@blackfin.uclinux.org)
- *
- * Created:
- * Description:  GPIO Abstraction Layer
- *
- * Modified:
- *               Copyright 2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/module.h>
-#include <linux/err.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-#include <linux/irq.h>
-static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
-        (struct gpio_port_t *)PORTA_FER,
-        (struct gpio_port_t *)PORTB_FER,
-        (struct gpio_port_t *)PORTC_FER,
-        (struct gpio_port_t *)PORTD_FER,
-        (struct gpio_port_t *)PORTE_FER,
-        (struct gpio_port_t *)PORTF_FER,
-        (struct gpio_port_t *)PORTG_FER,
-        (struct gpio_port_t *)PORTH_FER,
-        (struct gpio_port_t *)PORTI_FER,
-        (struct gpio_port_t *)PORTJ_FER,
-};
-static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
-static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
-inline int check_gpio(unsigned short gpio)
-{
-        if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
-            || gpio == GPIO_PH14 || gpio == GPIO_PH15
-            || gpio == GPIO_PJ14 || gpio == GPIO_PJ15
-            || gpio > MAX_BLACKFIN_GPIOS)
-                return -EINVAL;
-        return 0;
-}
-inline void portmux_setup(unsigned short portno, unsigned short function)
-{
-        u32 pmux;
-        pmux = gpio_array[gpio_bank(portno)]->port_mux;
-        pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
-        pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
-        gpio_array[gpio_bank(portno)]->port_mux = pmux;
-}
-inline u16 get_portmux(unsigned short portno)
-{
-        u32 pmux;
-        pmux = gpio_array[gpio_bank(portno)]->port_mux;
-        return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
-}
-static void port_setup(unsigned short gpio, unsigned short usage)
-{
-        if (usage == GPIO_USAGE) {
-                if (gpio_array[gpio_bank(gpio)]->port_fer & gpio_bit(gpio))
-                        printk(KERN_WARNING
-                               "bfin-gpio: Possible Conflict with Peripheral "
-                               "usage and GPIO %d detected!\n", gpio);
-                gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
-        } else
-                gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
-        SSYNC();
-}
-static int __init bfin_gpio_init(void)
-{
-        printk(KERN_INFO "Blackfin GPIO Controller\n");
-        return 0;
-}
-arch_initcall(bfin_gpio_init);
-int peripheral_request(unsigned short per, const char *label)
-{
-        unsigned long flags;
-        unsigned short ident = P_IDENT(per);
-        if (!(per & P_DEFINED))
-                return -ENODEV;
-        if (check_gpio(ident) < 0)
-                return -EINVAL;
-        local_irq_save(flags);
-        if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
-                printk(KERN_ERR
-                       "%s: Peripheral %d is already reserved as GPIO!\n",
-                       __FUNCTION__, per);
-                dump_stack();
-                local_irq_restore(flags);
-                return -EBUSY;
-        }
-        if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
-                u16 funct = get_portmux(ident);
-                if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
-                        printk(KERN_ERR
-                               "%s: Peripheral %d is already reserved!\n",
-                               __FUNCTION__, per);
-                        dump_stack();
-                        local_irq_restore(flags);
-                        return -EBUSY;
-                }
-        }
-        reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
-        portmux_setup(ident, P_FUNCT2MUX(per));
-        port_setup(ident, PERIPHERAL_USAGE);
-        local_irq_restore(flags);
-        return 0;
-}
-EXPORT_SYMBOL(peripheral_request);
-int peripheral_request_list(unsigned short per[], const char *label)
-{
-        u16 cnt;
-        int ret;
-        for (cnt = 0; per[cnt] != 0; cnt++) {
-                ret = peripheral_request(per[cnt], label);
-                if (ret < 0)
-                        return ret;
-        }
-        return 0;
-}
-EXPORT_SYMBOL(peripheral_request_list);
-void peripheral_free(unsigned short per)
-{
-        unsigned long flags;
-        unsigned short ident = P_IDENT(per);
-        if (!(per & P_DEFINED))
-                return;
-        if (check_gpio(ident) < 0)
-                return;
-        local_irq_save(flags);
-        if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
-                printk(KERN_ERR "bfin-gpio: Peripheral %d wasn't reserved!\n", per);
-                dump_stack();
-                local_irq_restore(flags);
-                return;
-        }
-        if (!(per & P_MAYSHARE)) {
-                port_setup(ident, GPIO_USAGE);
-        }
-        reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
-        local_irq_restore(flags);
-}
-EXPORT_SYMBOL(peripheral_free);
-void peripheral_free_list(unsigned short per[])
-{
-        u16 cnt;
-        for (cnt = 0; per[cnt] != 0; cnt++) {
-                peripheral_free(per[cnt]);
-        }
-}
-EXPORT_SYMBOL(peripheral_free_list);
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-int gpio_request(unsigned short gpio, const char *label)
-{
-        unsigned long flags;
-        if (check_gpio(gpio) < 0)
-                return -EINVAL;
-        local_irq_save(flags);
-        if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
-                printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio);
-                dump_stack();
-                local_irq_restore(flags);
-                return -EBUSY;
-        }
-        if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
-                printk(KERN_ERR
-                       "bfin-gpio: GPIO %d is already reserved as Peripheral!\n", gpio);
-                dump_stack();
-                local_irq_restore(flags);
-                return -EBUSY;
-        }
-        reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
-        local_irq_restore(flags);
-        port_setup(gpio, GPIO_USAGE);
-        return 0;
-}
-EXPORT_SYMBOL(gpio_request);
-void gpio_free(unsigned short gpio)
-{
-        unsigned long flags;
-        if (check_gpio(gpio) < 0)
-                return;
-        local_irq_save(flags);
-        if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
-                printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
-                dump_stack();
-                local_irq_restore(flags);
-                return;
-        }
-        reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
-        local_irq_restore(flags);
-}
-EXPORT_SYMBOL(gpio_free);
-void gpio_direction_input(unsigned short gpio)
-{
-        unsigned long flags;
-        BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
-        local_irq_save(flags);
-        gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
-        gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
-        local_irq_restore(flags);
-}
-EXPORT_SYMBOL(gpio_direction_input);
-void gpio_direction_output(unsigned short gpio)
-{
-        unsigned long flags;
-        BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
-        local_irq_save(flags);
-        gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
-        gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
-        local_irq_restore(flags);
-}
-EXPORT_SYMBOL(gpio_direction_output);
-void gpio_set_value(unsigned short gpio, unsigned short arg)
-{
-        if (arg)
-                gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
-        else
-                gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
-}
-EXPORT_SYMBOL(gpio_set_value);
-unsigned short gpio_get_value(unsigned short gpio)
-{
-        return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
-}
-EXPORT_SYMBOL(gpio_get_value);
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
index 06751ae8b857..3071c243d426 100644
--- a/arch/blackfin/mach-bf548/head.S
+++ b/arch/blackfin/mach-bf548/head.S
@@ -31,6 +31,7 @@
 #include <asm/blackfin.h>
 #include <asm/trace.h>
 #if CONFIG_BFIN_KERNEL_CLOCK
+#include <asm/mach-common/clocks.h>
 #include <asm/mach/mem_init.h>
 #endif
@@ -49,9 +50,13 @@ ENTRY(__start)
 ENTRY(__stext)
        /* R0: argument of command line string, passed from uboot, save it */
        R7 = R0;
-        /* Set the SYSCFG register */
+        /* Enable Cycle Counter and Nesting Of Interrupts */
-        R0 = 0x36;
+#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
-        SYSCFG = R0;   /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
+        R0 = SYSCFG_SNEN;
+#else
+        R0 = SYSCFG_SNEN | SYSCFG_CCEN;
+#endif
+        SYSCFG = R0;
        R0 = 0;
        /* Clear Out All the data and pointer  Registers*/
@@ -92,13 +97,13 @@ ENTRY(__stext)
        M2 = r0;
        M3 = r0;
-        trace_buffer_start(p0,r0);
+        trace_buffer_init(p0,r0);
        P0 = R1;
        R0 = R1;
        /* Turn off the icache */
-        p0.l = (IMEM_CONTROL & 0xFFFF);
+        p0.l = LO(IMEM_CONTROL);
-        p0.h = (IMEM_CONTROL >> 16);
+        p0.h = HI(IMEM_CONTROL);
        R1 = [p0];
        R0 = ~ENICPLB;
        R0 = R0 & R1;
@@ -106,8 +111,8 @@ ENTRY(__stext)
        SSYNC;
        /* Turn off the dcache */
-        p0.l = (DMEM_CONTROL & 0xFFFF);
+        p0.l = LO(DMEM_CONTROL);
-        p0.h = (DMEM_CONTROL >> 16);
+        p0.h = HI(DMEM_CONTROL);
        R1 = [p0];
        R0 = ~ENDCPLB;
        R0 = R0 & R1;
@@ -120,6 +125,12 @@ ENTRY(__stext)
        FP = SP;
        USP = SP;
+#ifdef CONFIG_EARLY_PRINTK
+        SP += -12;
+        call _init_early_exception_vectors;
+        SP += 12;
+#endif
        /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
        call _bf53x_relocate_l1_mem;
 #if CONFIG_BFIN_KERNEL_CLOCK
@@ -172,7 +183,7 @@ ENTRY(__stext)
        p0.l = .LWAIT_HERE;
        p0.h = .LWAIT_HERE;
        reti = p0;
-#if defined (ANOMALY_05000281)
+#if ANOMALY_05000281
        nop;
        nop;
        nop;
@@ -335,8 +346,8 @@ ENTRY(_start_dma_code)
        w[p0] = r0.l;
        ssync;
-        p0.l = (EBIU_SDBCTL & 0xFFFF);
+        p0.l = LO(EBIU_SDBCTL);
-        p0.h = (EBIU_SDBCTL >> 16);     /* SDRAM Memory Bank Control Register */
+        p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */
        r0 = mem_SDBCTL;
        w[p0] = r0.l;
        ssync;
@@ -373,129 +384,6 @@ ENTRY(_start_dma_code)
        RTS;
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
-ENTRY(_bfin_reset)
-        /* No more interrupts to be handled*/
-        CLI R6;
-        SSYNC;
-#if defined(CONFIG_MTD_M25P80)
-/*
- * The following code fix the SPI flash reboot issue,
- * /CS signal of the chip which is using PF10 return to GPIO mode
- */
-        p0.h = hi(PORTF_FER);
-        p0.l = lo(PORTF_FER);
-        r0.l = 0x0000;
-        w[p0] = r0.l;
-        SSYNC;
-/* /CS return to high */
-        p0.h = hi(PORTFIO);
-        p0.l = lo(PORTFIO);
-        r0.l = 0xFFFF;
-        w[p0] = r0.l;
-        SSYNC;
-/* Delay some time, This is necessary */
-        r1.h = 0;
-        r1.l = 0x400;
-        p1   = r1;
-        lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1;
-_delay_lab1:
-        r0.h = 0;
-        r0.l = 0x8000;
-        p0   = r0;
-        lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0;
-_delay_lab0:
-        nop;
-_delay_lab0_end:
-        nop;
-_delay_lab1_end:
-        nop;
-#endif
-        /* Clear the bits 13-15 in SWRST if they werent cleared */
-        p0.h = hi(SWRST);
-        p0.l = lo(SWRST);
-        csync;
-        r0.l = w[p0];
-        /* Clear the IMASK register */
-        p0.h = hi(IMASK);
-        p0.l = lo(IMASK);
-        r0 = 0x0;
-        [p0] = r0;
-        /* Clear the ILAT register */
-        p0.h = hi(ILAT);
-        p0.l = lo(ILAT);
-        r0 = [p0];
-        [p0] = r0;
-        SSYNC;
-        /* Disable the WDOG TIMER */
-        p0.h = hi(WDOG_CTL);
-        p0.l = lo(WDOG_CTL);
-        r0.l = 0xAD6;
-        w[p0] = r0.l;
-        SSYNC;
-        /* Clear the sticky bit incase it is already set */
-        p0.h = hi(WDOG_CTL);
-        p0.l = lo(WDOG_CTL);
-        r0.l = 0x8AD6;
-        w[p0] = r0.l;
-        SSYNC;
-        /* Program the count value */
-        R0.l = 0x100;
-        R0.h = 0x0;
-        P0.h = hi(WDOG_CNT);
-        P0.l = lo(WDOG_CNT);
-        [P0] = R0;
-        SSYNC;
-        /* Program WDOG_STAT if necessary */
-        P0.h = hi(WDOG_CTL);
-        P0.l = lo(WDOG_CTL);
-        R0 = W[P0](Z);
-        CC = BITTST(R0,1);
-        if !CC JUMP .LWRITESTAT;
-        CC = BITTST(R0,2);
-        if !CC JUMP .LWRITESTAT;
-        JUMP .LSKIP_WRITE;
-.LWRITESTAT:
-        /* When watch dog timer is enabled,
-         * a write to STAT will load the contents of CNT to STAT
-         */
-        R0 = 0x0000(z);
-        P0.h = hi(WDOG_STAT);
-        P0.l = lo(WDOG_STAT)
-        [P0] = R0;
-        SSYNC;
-.LSKIP_WRITE:
-        /* Enable the reset event */
-        P0.h = hi(WDOG_CTL);
-        P0.l = lo(WDOG_CTL);
-        R0 = W[P0](Z);
-        BITCLR(R0,1);
-        BITCLR(R0,2);
-        W[P0] = R0.L;
-        SSYNC;
-        NOP;
-        /* Enable the wdog counter */
-        R0 = W[P0](Z);
-        BITCLR(R0,4);
-        W[P0] = R0.L;
-        SSYNC;
-        IDLE;
-        RTS;
 .data
 /*
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 5b2b544529a1..cd827a1b6ba1 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -34,7 +34,9 @@
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/usb_isp1362.h>
+#include <linux/pata_platform.h>
 #include <linux/irq.h>
+#include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
 /*
@@ -112,7 +114,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                /* the modalias must be the same as spi device driver name */
                .modalias = "m25p80", /* Name of spi_driver for this device */
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
                .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
                .platform_data = &bfin_spi_flash_data,
                .controller_data = &spi_flash_chip_info,
@@ -124,7 +126,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
                .max_speed_hz = 6250000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1, /* Framework bus number */
+                .bus_num = 0, /* Framework bus number */
                .chip_select = 1, /* Framework chip select. */
                .platform_data = NULL, /* No spi_driver specific config */
                .controller_data = &spi_adc_chip_info,
@@ -135,7 +137,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad1836-spi",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
                .controller_data = &ad1836_spi_chip_info,
        },
@@ -144,7 +146,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad9960-spi",
                .max_speed_hz = 10000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = 1,
                .controller_data = &ad9960_spi_chip_info,
        },
@@ -153,7 +155,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "spi_mmc",
                .max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SPI_MMC_CS_CHAN,
                .platform_data = NULL,
                .controller_data = &spi_mmc_chip_info,
@@ -162,17 +164,33 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #endif
 };
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CH_SPI,
+                .end   = CH_SPI,
+                .flags = IORESOURCE_IRQ,
+        }
+};
 /* SPI controller data */
-static struct bfin5xx_spi_master spi_bfin_master_info = {
+static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 8,
        .enable_dma = 1,  /* master has the ability to do dma transfer */
 };
-static struct platform_device spi_bfin_master_device = {
+static struct platform_device bfin_spi0_device = {
-        .name = "bfin-spi-master",
+        .name = "bfin-spi",
-        .id = 1, /* Bus number */
+        .id = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
        .dev = {
-                .platform_data = &spi_bfin_master_info, /* Passed to driver */
+                .platform_data = &bfin_spi0_info, /* Passed to driver */
        },
 };
 #endif  /* spi master and devices */
@@ -256,6 +274,43 @@ static struct platform_device bfin_uart_device = {
 };
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#define PATA_INT        119
+static struct pata_platform_info bfin_pata_platform_data = {
+        .ioport_shift = 2,
+        .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+};
+static struct resource bfin_pata_resources[] = {
+        {
+                .start = 0x2400C000,
+                .end = 0x2400C001F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = 0x2400D018,
+                .end = 0x2400D01B,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = PATA_INT,
+                .end = PATA_INT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_pata_device = {
+        .name = "pata_platform",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(bfin_pata_resources),
+        .resource = bfin_pata_resources,
+        .dev = {
+                .platform_data = &bfin_pata_platform_data,
+        }
+};
+#endif
 static struct platform_device *cm_bf561_devices[] __initdata = {
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
@@ -271,9 +326,12 @@ static struct platform_device *cm_bf561_devices[] __initdata = {
 #endif
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-        &spi_bfin_master_device,
+        &bfin_spi0_device,
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        &bfin_pata_device,
+#endif
 };
 static int __init cm_bf561_init(void)
@@ -283,6 +341,10 @@ static int __init cm_bf561_init(void)
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
+#endif
        return 0;
 }
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 724191da20a2..57e14edca8b1 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -32,6 +32,8 @@
 #include <linux/spi/spi.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
+#include <linux/pata_platform.h>
+#include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
 /*
@@ -140,17 +142,33 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
 #endif
 #endif
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CH_SPI,
+                .end   = CH_SPI,
+                .flags = IORESOURCE_IRQ,
+        }
+};
 /* SPI controller data */
-static struct bfin5xx_spi_master spi_bfin_master_info = {
+static struct bfin5xx_spi_master bfin_spi0_info = {
        .num_chipselect = 8,
        .enable_dma = 1,  /* master has the ability to do dma transfer */
 };
-static struct platform_device spi_bfin_master_device = {
+static struct platform_device bfin_spi0_device = {
-        .name = "bfin-spi-master",
+        .name = "bfin-spi",
-        .id = 1, /* Bus number */
+        .id = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource = bfin_spi0_resource,
        .dev = {
-                .platform_data = &spi_bfin_master_info, /* Passed to driver */
+                .platform_data = &bfin_spi0_info, /* Passed to driver */
        },
 };
@@ -160,23 +178,63 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
        {
                .modalias = "ad1836-spi",
                .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
+                .bus_num = 0,
                .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
                .controller_data = &ad1836_spi_chip_info,
        },
 #endif
 };
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+#define PATA_INT        55
+static struct pata_platform_info bfin_pata_platform_data = {
+        .ioport_shift = 1,
+        .irq_type = IRQF_TRIGGER_HIGH | IRQF_DISABLED,
+};
+static struct resource bfin_pata_resources[] = {
+        {
+                .start = 0x20314020,
+                .end = 0x2031403F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = 0x2031401C,
+                .end = 0x2031401F,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = PATA_INT,
+                .end = PATA_INT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device bfin_pata_device = {
+        .name = "pata_platform",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(bfin_pata_resources),
+        .resource = bfin_pata_resources,
+        .dev = {
+                .platform_data = &bfin_pata_platform_data,
+        }
+};
+#endif
 static struct platform_device *ezkit_devices[] __initdata = {
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
        &smc91x_device,
 #endif
 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-        &spi_bfin_master_device,
+        &bfin_spi0_device,
 #endif
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
        &bfin_uart_device,
 #endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        &bfin_pata_device,
+#endif
 };
 static int __init ezkit_init(void)
@@ -194,7 +252,15 @@ static int __init ezkit_init(void)
        SSYNC();
 #endif
-        return spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+        spi_register_board_info(bfin_spi_board_info,
+                                ARRAY_SIZE(bfin_spi_board_info));
+#endif
+#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
+        irq_desc[PATA_INT].status |= IRQ_NOAUTOEN;
+#endif
+        return 0;
 }
 arch_initcall(ezkit_init);
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 38650a628980..96a3d456fb6d 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -33,6 +33,7 @@
 #include <asm/trace.h>
 #if CONFIG_BFIN_KERNEL_CLOCK
+#include <asm/mach-common/clocks.h>
 #include <asm/mach/mem_init.h>
 #endif
@@ -50,10 +51,12 @@ __INIT
 ENTRY(__start)
        /* R0: argument of command line string, passed from uboot, save it */
        R7 = R0;
-        /* Set the SYSCFG register:
+        /* Enable Cycle Counter and Nesting Of Interrupts */
-         * Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
+#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
-         */
+        R0 = SYSCFG_SNEN;
-        R0 = 0x36;
+#else
+        R0 = SYSCFG_SNEN | SYSCFG_CCEN;
+#endif
        SYSCFG = R0;
        R0 = 0;
@@ -95,43 +98,42 @@ ENTRY(__start)
        M2 = r0;
        M3 = r0;
-        trace_buffer_start(p0,r0);
+        trace_buffer_init(p0,r0);
        P0 = R1;
        R0 = R1;
        /* Turn off the icache */
-        p0.l = (IMEM_CONTROL & 0xFFFF);
+        p0.l = LO(IMEM_CONTROL);
-        p0.h = (IMEM_CONTROL >> 16);
+        p0.h = HI(IMEM_CONTROL);
        R1 = [p0];
        R0 = ~ENICPLB;
        R0 = R0 & R1;
-        /* Anomaly 05000125 */
+#if ANOMALY_05000125
-#ifdef ANOMALY_05000125
        CLI R2;
        SSYNC;
 #endif
        [p0] = R0;
        SSYNC;
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        STI R2;
 #endif
        /* Turn off the dcache */
-        p0.l = (DMEM_CONTROL & 0xFFFF);
+        p0.l = LO(DMEM_CONTROL);
-        p0.h = (DMEM_CONTROL >> 16);
+        p0.h = HI(DMEM_CONTROL);
        R1 = [p0];
        R0 = ~ENDCPLB;
        R0 = R0 & R1;
        /* Anomaly 05000125 */
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        CLI R2;
        SSYNC;
 #endif
        [p0] = R0;
        SSYNC;
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
        STI R2;
 #endif
@@ -167,6 +169,12 @@ ENTRY(__start)
        fp = sp;
        usp = sp;
+#ifdef CONFIG_EARLY_PRINTK
+        SP += -12;
+        call _init_early_exception_vectors;
+        SP += 12;
+#endif
        /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
        call _bf53x_relocate_l1_mem;
 #if CONFIG_BFIN_KERNEL_CLOCK
@@ -220,7 +228,7 @@ ENTRY(__start)
        p0.l = .LWAIT_HERE;
        p0.h = .LWAIT_HERE;
        reti = p0;
-#if defined(ANOMALY_05000281)
+#if ANOMALY_05000281
        nop; nop; nop;
 #endif
        rti;
@@ -372,8 +380,8 @@ ENTRY(_start_dma_code)
        w[p0] = r0.l;
        ssync;
-        p0.l = (EBIU_SDBCTL & 0xFFFF);
+        p0.l = LO(EBIU_SDBCTL);
-        p0.h = (EBIU_SDBCTL >> 16);     /* SDRAM Memory Bank Control Register */
+        p0.h = HI(EBIU_SDBCTL);     /* SDRAM Memory Bank Control Register */
        r0 = mem_SDBCTL;
        w[p0] = r0.l;
        ssync;
@@ -404,66 +412,6 @@ ENTRY(_start_dma_code)
 ENDPROC(_start_dma_code)
 #endif /* CONFIG_BFIN_KERNEL_CLOCK */
-ENTRY(_bfin_reset)
-        /* No more interrupts to be handled*/
-        CLI R6;
-        SSYNC;
-#if defined(CONFIG_BFIN_SHARED_FLASH_ENET)
-        p0.h = hi(FIO_INEN);
-        p0.l = lo(FIO_INEN);
-        r0.l = ~(PF1 | PF0);
-        w[p0] = r0.l;
-        p0.h = hi(FIO_DIR);
-        p0.l = lo(FIO_DIR);
-        r0.l = (PF1 | PF0);
-        w[p0] = r0.l;
-        p0.h = hi(FIO_FLAG_C);
-        p0.l = lo(FIO_FLAG_C);
-        r0.l = (PF1 | PF0);
-        w[p0] = r0.l;
-#endif
-        /* Clear the IMASK register */
-        p0.h = hi(IMASK);
-        p0.l = lo(IMASK);
-        r0 = 0x0;
-        [p0] = r0;
-        /* Clear the ILAT register */
-        p0.h = hi(ILAT);
-        p0.l = lo(ILAT);
-        r0 = [p0];
-        [p0] = r0;
-        SSYNC;
-        /* make sure SYSCR is set to use BMODE */
-        P0.h = hi(SYSCR);
-        P0.l = lo(SYSCR);
-        R0.l = 0x20;            /* on BF561, disable core b */
-        W[P0] = R0.l;
-        SSYNC;
-        /* issue a system soft reset */
-        P1.h = hi(SWRST);
-        P1.l = lo(SWRST);
-        R1.l = 0x0007;
-        W[P1] = R1;
-        SSYNC;
-        /* clear system soft reset */
-        R0.l = 0x0000;
-        W[P0] = R0;
-        SSYNC;
-        /* issue core reset */
-        raise 1;
-        RTS;
-ENDPROC(_bfin_reset)
 .data
 /*
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index 0279ede70392..4d7733dfd5de 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -4,7 +4,7 @@
 obj-y := \
        cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \
-        interrupt.o lock.o irqpanic.o
+        interrupt.o lock.o irqpanic.o arch_checks.o
 obj-$(CONFIG_CPLB_INFO)          += cplbinfo.o
 obj-$(CONFIG_BFIN_SINGLE_CORE)   += ints-priority-sc.o
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
new file mode 100644
index 000000000000..2f6ce397780f
--- /dev/null
+++ b/arch/blackfin/mach-common/arch_checks.c
@@ -0,0 +1,60 @@
+/*
+ * File:         arch/blackfin/mach-common/arch_checks.c
+ * Based on:
+ * Author:       Robin Getz <rgetz@blackfin.uclinux.org>
+ *
+ * Created:      25Jul07
+ * Description:  Do some checking to make sure things are OK
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <asm/mach/anomaly.h>
+#include <asm/mach-common/clocks.h>
+#ifdef CONFIG_BFIN_KERNEL_CLOCK
+# if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ)
+#  error "VCO selected is more than maximum value. Please change the VCO multipler"
+# endif
+# if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ)
+# error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
+# endif
+# if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ)
+# error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
+# endif
+# if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ)
+# error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK"
+# endif
+# if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
+# error "Please select sclk less than cclk"
+# endif
+#endif /* CONFIG_BFIN_KERNEL_CLOCK */
+#if (CONFIG_MEM_SIZE % 4)
+#error "SDRAM mem size must be multible of 4MB"
+#endif
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index 7063795eb7c0..0521b1588204 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -79,8 +79,8 @@ ENTRY(_icache_invalidate)
 ENTRY(_invalidate_entire_icache)
        [--SP] = ( R7:5);
-        P0.L = (IMEM_CONTROL & 0xFFFF);
+        P0.L = LO(IMEM_CONTROL);
-        P0.H = (IMEM_CONTROL >> 16);
+        P0.H = HI(IMEM_CONTROL);
        R7 = [P0];
        /* Clear the IMC bit , All valid bits in the instruction
@@ -197,8 +197,8 @@ ENTRY(_invalidate_entire_dcache)
 ENTRY(_dcache_invalidate)
        [--SP] = ( R7:6);
-        P0.L = (DMEM_CONTROL & 0xFFFF);
+        P0.L = LO(DMEM_CONTROL);
-        P0.H = (DMEM_CONTROL >> 16);
+        P0.H = HI(DMEM_CONTROL);
        R7 = [P0];
        /* Clear the DMC[1:0] bits, All valid bits in the data
diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S
index 5be6b975ae4a..22fada0c1cb3 100644
--- a/arch/blackfin/mach-common/cacheinit.S
+++ b/arch/blackfin/mach-common/cacheinit.S
@@ -38,13 +38,13 @@
 .text
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
-#if defined(CONFIG_BLKFIN_CACHE)
+#if defined(CONFIG_BFIN_ICACHE)
 ENTRY(_bfin_write_IMEM_CONTROL)
        /* Enable Instruction Cache */
-        P0.l = (IMEM_CONTROL & 0xFFFF);
+        P0.l = LO(IMEM_CONTROL);
-        P0.h = (IMEM_CONTROL >> 16);
+        P0.h = HI(IMEM_CONTROL);
        /* Anomaly 05000125 */
        CLI R1;
@@ -58,10 +58,10 @@ ENTRY(_bfin_write_IMEM_CONTROL)
 ENDPROC(_bfin_write_IMEM_CONTROL)
 #endif
-#if defined(CONFIG_BLKFIN_DCACHE)
+#if defined(CONFIG_BFIN_DCACHE)
 ENTRY(_bfin_write_DMEM_CONTROL)
-        P0.l = (DMEM_CONTROL & 0xFFFF);
+        P0.l = LO(DMEM_CONTROL);
-        P0.h = (DMEM_CONTROL >> 16);
+        P0.h = HI(DMEM_CONTROL);
        CLI R1;
        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
diff --git a/arch/blackfin/mach-common/cplbhdlr.S b/arch/blackfin/mach-common/cplbhdlr.S
index 2f3c72c23997..2788532de72b 100644
--- a/arch/blackfin/mach-common/cplbhdlr.S
+++ b/arch/blackfin/mach-common/cplbhdlr.S
@@ -69,14 +69,14 @@ ENTRY(__cplb_hdr)
 .Lis_icplb_miss:
-#if defined(CONFIG_BLKFIN_CACHE) || defined(CONFIG_BLKFIN_DCACHE)
+#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
-# if defined(CONFIG_BLKFIN_CACHE) && !defined(CONFIG_BLKFIN_DCACHE)
+# if defined(CONFIG_BFIN_ICACHE) && !defined(CONFIG_BFIN_DCACHE)
        R1 = CPLB_ENABLE_ICACHE;
 # endif
-# if !defined(CONFIG_BLKFIN_CACHE) && defined(CONFIG_BLKFIN_DCACHE)
+# if !defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
        R1 = CPLB_ENABLE_DCACHE;
 # endif
-# if defined(CONFIG_BLKFIN_CACHE) && defined(CONFIG_BLKFIN_DCACHE)
+# if defined(CONFIG_BFIN_ICACHE) && defined(CONFIG_BFIN_DCACHE)
        R1 = CPLB_ENABLE_DCACHE | CPLB_ENABLE_ICACHE;
 # endif
 #else
diff --git a/arch/blackfin/mach-common/cplbmgr.S b/arch/blackfin/mach-common/cplbmgr.S
index e4b47e09cf13..946703ef48ff 100644
--- a/arch/blackfin/mach-common/cplbmgr.S
+++ b/arch/blackfin/mach-common/cplbmgr.S
@@ -75,15 +75,15 @@ ENTRY(_cplb_mgr)
        * from the configuration table.
        */
-        P4.L = (ICPLB_FAULT_ADDR & 0xFFFF);
+        P4.L = LO(ICPLB_FAULT_ADDR);
-        P4.H = (ICPLB_FAULT_ADDR >> 16);
+        P4.H = HI(ICPLB_FAULT_ADDR);
        P1 = 16;
        P5.L = _page_size_table;
        P5.H = _page_size_table;
-        P0.L = (ICPLB_DATA0 & 0xFFFF);
+        P0.L = LO(ICPLB_DATA0);
-        P0.H = (ICPLB_DATA0 >> 16);
+        P0.H = HI(ICPLB_DATA0);
        R4 = [P4];              /* Get faulting address*/
        R6 = 64;                /* Advance past the fault address, which*/
        R6 = R6 + R4;           /* we'll use if we find a match*/
@@ -117,13 +117,13 @@ ENTRY(_cplb_mgr)
        I0 = R4;                /* Fault address we'll search for*/
        /* set up pointers */
-        P0.L = (ICPLB_DATA0 & 0xFFFF);
+        P0.L = LO(ICPLB_DATA0);
-        P0.H = (ICPLB_DATA0 >> 16);
+        P0.H = HI(ICPLB_DATA0);
        /* The replacement procedure for ICPLBs */
-        P4.L = (IMEM_CONTROL & 0xFFFF);
+        P4.L = LO(IMEM_CONTROL);
-        P4.H = (IMEM_CONTROL >> 16);
+        P4.H = HI(IMEM_CONTROL);
        /* disable cplbs */
        R5 = [P4];              /* Control Register*/
@@ -243,8 +243,8 @@ ENTRY(_cplb_mgr)
         * last entry of the table.
         */
-        P1.L = (ICPLB_DATA15 & 0xFFFF);         /* ICPLB_DATA15 */
+        P1.L = LO(ICPLB_DATA15);                /* ICPLB_DATA15 */
-        P1.H = (ICPLB_DATA15 >> 16);
+        P1.H = HI(ICPLB_DATA15);
        [P1] = R2;
        [P1-0x100] = R4;
 #ifdef  CONFIG_CPLB_INFO
@@ -292,10 +292,10 @@ ENTRY(_cplb_mgr)
         * pending writes associated with the CPLB.
         */
-        P4.L = (DCPLB_STATUS & 0xFFFF);
+        P4.L = LO(DCPLB_STATUS);
-        P4.H = (DCPLB_STATUS >> 16);
+        P4.H = HI(DCPLB_STATUS);
-        P3.L = (DCPLB_DATA0 & 0xFFFF);
+        P3.L = LO(DCPLB_DATA0);
-        P3.H = (DCPLB_DATA0 >> 16);
+        P3.H = HI(DCPLB_DATA0);
        R5 = [P4];
        /* A protection violation can be caused by more than just writes
@@ -355,11 +355,11 @@ ENTRY(_cplb_mgr)
         * config table, that covers the faulting address.
         */
-        P1.L = (DCPLB_DATA15 & 0xFFFF);
+        P1.L = LO(DCPLB_DATA15);
-        P1.H = (DCPLB_DATA15 >> 16);
+        P1.H = HI(DCPLB_DATA15);
-        P4.L = (DCPLB_FAULT_ADDR & 0xFFFF);
+        P4.L = LO(DCPLB_FAULT_ADDR);
-        P4.H = (DCPLB_FAULT_ADDR >> 16);
+        P4.H = HI(DCPLB_FAULT_ADDR);
        R4 = [P4];
        I0 = R4;
@@ -368,8 +368,8 @@ ENTRY(_cplb_mgr)
        R6 = R1;        /* Save for later*/
        /* Turn off CPLBs while we work.*/
-        P4.L = (DMEM_CONTROL & 0xFFFF);
+        P4.L = LO(DMEM_CONTROL);
-        P4.H = (DMEM_CONTROL >> 16);
+        P4.H = HI(DMEM_CONTROL);
        R5 = [P4];
        BITCLR(R5,ENDCPLB_P);
        CLI R0;
@@ -384,8 +384,8 @@ ENTRY(_cplb_mgr)
         * are no good.
         */
-        I1.L = (DCPLB_DATA0 & 0xFFFF);
+        I1.L = LO(DCPLB_DATA0);
-        I1.H = (DCPLB_DATA0 >> 16);
+        I1.H = HI(DCPLB_DATA0);
        P1 = 2;
        P2 = 16;
        I2.L = _dcplb_preference;
@@ -405,7 +405,7 @@ ENTRY(_cplb_mgr)
        P3.L = _page_size_table; /* retrieve end address */
        P3.H = _page_size_table; /* retrieve end address */
        R3 = 0x1002;            /* 16th - position, 2 bits -length */
-#ifdef ANOMALY_05000209
+#if ANOMALY_05000209
        nop;                    /* Anomaly 05000209 */
 #endif
        R7 = EXTRACT(R1,R3.l);
@@ -475,8 +475,8 @@ ENTRY(_cplb_mgr)
         * one space closer to the start.
         */
-        R1.L = (DCPLB_DATA16 & 0xFFFF);         /* DCPLB_DATA15 + 4 */
+        R1.L = LO(DCPLB_DATA16);                /* DCPLB_DATA15 + 4 */
-        R1.H = (DCPLB_DATA16 >> 16);
+        R1.H = HI(DCPLB_DATA16);
        R0 = P0;
        /* If the victim happens to be in DCPLB15,
@@ -549,8 +549,8 @@ ENTRY(_cplb_mgr)
         * if necessary.
         */
-        P1.L = (DCPLB_DATA15 & 0xFFFF);
+        P1.L = LO(DCPLB_DATA15);
-        P1.H = (DCPLB_DATA15 >> 16);
+        P1.H = HI(DCPLB_DATA15);
        /* If the DCPLB has cache bits set, but caching hasn't
         * been enabled, then we want to mask off the cache-in-L1
@@ -565,7 +565,7 @@ ENTRY(_cplb_mgr)
         * cost of first-write exceptions to mark the page as dirty.
         */
-#ifdef CONFIG_BLKFIN_WT
+#ifdef CONFIG_BFIN_WT
        BITSET(R6, 14);         /* Set WT*/
 #endif
diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S
index 97cdcd6a00d4..39fbc2861107 100644
--- a/arch/blackfin/mach-common/dpmc.S
+++ b/arch/blackfin/mach-common/dpmc.S
@@ -39,8 +39,8 @@ ENTRY(_unmask_wdog_wakeup_evt)
        P0.H = hi(SICA_IWR1);
        P0.L = lo(SICA_IWR1);
 #else
-        P0.h = (SIC_IWR >> 16);
+        P0.h = HI(SIC_IWR);
-        P0.l = (SIC_IWR & 0xFFFF);
+        P0.l = LO(SIC_IWR);
 #endif
        R7 = [P0];
 #if defined(CONFIG_BF561)
@@ -60,11 +60,11 @@ ENTRY(_unmask_wdog_wakeup_evt)
         */
        R7 = 0x0000(z);
 #if defined(CONFIG_BF561)
-        P0.h = (WDOGA_STAT >> 16);
+        P0.h = HI(WDOGA_STAT);
-        P0.l = (WDOGA_STAT & 0xFFFF);
+        P0.l = LO(WDOGA_STAT);
 #else
-        P0.h = (WDOG_STAT >> 16);
+        P0.h = HI(WDOG_STAT);
-        P0.l = (WDOG_STAT & 0xFFFF);
+        P0.l = LO(WDOG_STAT);
 #endif
        [P0] = R7;
        SSYNC;
@@ -73,21 +73,21 @@ ENTRY(_unmask_wdog_wakeup_evt)
 ENTRY(_program_wdog_timer)
        [--SP] = ( R7:0, P5:0 );
 #if defined(CONFIG_BF561)
-        P0.h = (WDOGA_CNT >> 16);
+        P0.h = HI(WDOGA_CNT);
-        P0.l = (WDOGA_CNT & 0xFFFF);
+        P0.l = LO(WDOGA_CNT);
 #else
-        P0.h = (WDOG_CNT >> 16);
+        P0.h = HI(WDOG_CNT);
-        P0.l = (WDOG_CNT & 0xFFFF);
+        P0.l = LO(WDOG_CNT);
 #endif
        [P0] = R0;
        SSYNC;
 #if defined(CONFIG_BF561)
-        P0.h = (WDOGA_CTL >> 16);
+        P0.h = HI(WDOGA_CTL);
-        P0.l = (WDOGA_CTL & 0xFFFF);
+        P0.l = LO(WDOGA_CTL);
 #else
-        P0.h = (WDOG_CTL >> 16);
+        P0.h = HI(WDOG_CTL);
-        P0.l = (WDOG_CTL & 0xFFFF);
+        P0.l = LO(WDOG_CTL);
 #endif
        R7 = W[P0](Z);
        CC = BITTST(R7,1);
@@ -97,11 +97,11 @@ ENTRY(_program_wdog_timer)
 .LSKIP_WRITE_TO_STAT:
 #if defined(CONFIG_BF561)
-        P0.h = (WDOGA_CTL >> 16);
+        P0.h = HI(WDOGA_CTL);
-            P0.l = (WDOGA_CTL & 0xFFFF);
+        P0.l = LO(WDOGA_CTL);
 #else
-        P0.h = (WDOG_CTL >> 16);
+        P0.h = HI(WDOG_CTL);
-            P0.l = (WDOG_CTL & 0xFFFF);
+        P0.l = LO(WDOG_CTL);
 #endif
        R7 = W[P0](Z);
        BITCLR(R7,1);   /* Enable GP event */
@@ -122,11 +122,11 @@ ENTRY(_clear_wdog_wakeup_evt)
        [--SP] = ( R7:0, P5:0 );
 #if defined(CONFIG_BF561)
-        P0.h = (WDOGA_CTL >> 16);
+        P0.h = HI(WDOGA_CTL);
-        P0.l = (WDOGA_CTL & 0xFFFF);
+        P0.l = LO(WDOGA_CTL);
 #else
-        P0.h = (WDOG_CTL >> 16);
+        P0.h = HI(WDOG_CTL);
-        P0.l = (WDOG_CTL & 0xFFFF);
+        P0.l = LO(WDOG_CTL);
 #endif
        R7 = 0x0AD6(Z);
        W[P0] = R7.L;
@@ -149,11 +149,11 @@ ENTRY(_clear_wdog_wakeup_evt)
 ENTRY(_disable_wdog_timer)
        [--SP] = ( R7:0, P5:0 );
 #if defined(CONFIG_BF561)
-        P0.h = (WDOGA_CTL >> 16);
+        P0.h = HI(WDOGA_CTL);
-        P0.l = (WDOGA_CTL & 0xFFFF);
+        P0.l = LO(WDOGA_CTL);
 #else
-        P0.h = (WDOG_CTL >> 16);
+        P0.h = HI(WDOG_CTL);
-        P0.l = (WDOG_CTL & 0xFFFF);
+        P0.l = LO(WDOG_CTL);
 #endif
        R7 = 0xAD6(Z);
        W[P0] = R7.L;
@@ -300,7 +300,7 @@ ENTRY(_sleep_deeper)
        P0.H = hi(PLL_CTL);
        P0.L = lo(PLL_CTL);
        R5 = W[P0](z);
-        R0.L = (MIN_VC/CONFIG_CLKIN_HZ) << 9;
+        R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
        W[P0] = R0.l;
        SSYNC;
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 960458808344..e3ad5802868a 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -29,21 +29,7 @@
 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
-/*
+/* NOTE: This code handles signal-recognition, which happens every time
- * 25-Dec-2004 - LG Soft India
- *      1. Fix in return_from_int, to make sure any pending
- *      system call in ILAT for this process to get
- *      executed, otherwise in case context switch happens,
- *      system call of first process (i.e in ILAT) will be
- *      carried forward to the switched process.
- *      2. Removed Constant references for the following
- *              a.  IPEND
- *              b.  EXCAUSE mask
- *              c.  PAGE Mask
- */
-/*
- * NOTE: This code handles signal-recognition, which happens every time
 * after a timer-interrupt and after each system call.
 */
@@ -58,6 +44,23 @@
 #include <asm/mach-common/context.S>
+#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
+# define EX_SCRATCH_REG RETN
+#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE)
+# define EX_SCRATCH_REG RETE
+#else
+# define EX_SCRATCH_REG CYCLES
+#endif
+#if ANOMALY_05000281
+ENTRY(_safe_speculative_execution)
+        NOP;
+        NOP;
+        NOP;
+        jump _safe_speculative_execution;
+ENDPROC(_safe_speculative_execution)
+#endif
 #ifdef CONFIG_EXCPT_IRQ_SYSC_L1
 .section .l1.text
 #else
@@ -69,7 +72,7 @@
 * patch up CPLB misses on the kernel stack.
 */
 ENTRY(_ex_dcplb)
-#if defined(ANOMALY_05000261)
+#if ANOMALY_05000261
        /*
         * Work around an anomaly: if we see a new DCPLB fault, return
         * without doing anything.  Then, if we get the same fault again,
@@ -93,7 +96,7 @@ ENTRY(_ex_icplb)
        call __cplb_hdr;
        DEBUG_START_HWTRACE(p5, r7)
        RESTORE_ALL_SYS
-        SP = RETN;
+        SP = EX_SCRATCH_REG;
        rtx;
 ENDPROC(_ex_icplb)
@@ -102,7 +105,7 @@ ENTRY(_ex_syscall)
        (R7:6,P5:4) = [sp++];
        ASTAT = [sp++];
        raise 15;               /* invoked by TRAP #0, for sys call */
-        sp = retn;
+        sp = EX_SCRATCH_REG;
        rtx
 ENDPROC(_ex_syscall)
@@ -135,9 +138,9 @@ ENTRY(_ex_single_step)
        cc = r6 == r7;
        if !cc jump _ex_trap_c;
-_return_from_exception:
+ENTRY(_return_from_exception)
        DEBUG_START_HWTRACE(p5, r7)
-#ifdef ANOMALY_05000257
+#if ANOMALY_05000257
        R7=LC0;
        LC0=R7;
        R7=LC1;
@@ -145,7 +148,7 @@ _return_from_exception:
 #endif
        (R7:6,P5:4) = [sp++];
        ASTAT = [sp++];
-        sp = retn;
+        sp = EX_SCRATCH_REG;
        rtx;
 ENDPROC(_ex_soft_bp)
@@ -163,7 +166,17 @@ ENTRY(_handle_bad_cplb)
        [--sp] = ASTAT;
        [--sp] = (R7:6, P5:4);
+ENTRY(_ex_replaceable)
+        nop;
 ENTRY(_ex_trap_c)
+        /* Make sure we are not in a double fault */
+        p4.l = lo(IPEND);
+        p4.h = hi(IPEND);
+        r7 = [p4];
+        CC = BITTST (r7, 5);
+        if CC jump _double_fault;
        /* Call C code (trap_c) to handle the exception, which most
         * likely involves sending a signal to the current process.
         * To avoid double faults, lower our priority to IRQ5 first.
@@ -204,11 +217,57 @@ ENTRY(_ex_trap_c)
        DEBUG_START_HWTRACE(p5, r7)
        (R7:6,P5:4) = [sp++];
        ASTAT = [sp++];
-        SP = RETN;
+        SP = EX_SCRATCH_REG;
        raise 5;
        rtx;
 ENDPROC(_ex_trap_c)
+/* We just realized we got an exception, while we were processing a different
+ * exception. This is a unrecoverable event, so crash
+ */
+ENTRY(_double_fault)
+        /* Turn caches & protection off, to ensure we don't get any more
+         * double exceptions
+         */
+        P4.L = LO(IMEM_CONTROL);
+        P4.H = HI(IMEM_CONTROL);
+        R5 = [P4];              /* Control Register*/
+        BITCLR(R5,ENICPLB_P);
+        SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
+        .align 8;
+        [P4] = R5;
+        SSYNC;
+        P4.L = LO(DMEM_CONTROL);
+        P4.H = HI(DMEM_CONTROL);
+        R5 = [P4];
+        BITCLR(R5,ENDCPLB_P);
+        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
+        .align 8;
+        [P4] = R5;
+        SSYNC;
+        /* Fix up the stack */
+        (R7:6,P5:4) = [sp++];
+        ASTAT = [sp++];
+        SP = EX_SCRATCH_REG;
+        /* We should be out of the exception stack, and back down into
+         * kernel or user space stack
+         */
+        SAVE_ALL_SYS
+        r0 = sp;        /* stack frame pt_regs pointer argument ==> r0 */
+        SP += -12;
+        call _double_fault_c;
+        SP += 12;
+.L_double_fault_panic:
+        JUMP .L_double_fault_panic
+ENDPROC(_double_fault)
 ENTRY(_exception_to_level5)
        SAVE_ALL_SYS
@@ -279,7 +338,7 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
         * covered by a CPLB.  Switch to an exception stack; use RETN as a
         * scratch register (for want of a better option).
         */
-        retn = sp;
+        EX_SCRATCH_REG = sp;
        sp.l = _exception_stack_top;
        sp.h = _exception_stack_top;
        /* Try to deal with syscalls quickly.  */
@@ -290,8 +349,8 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
        r6.l = lo(SEQSTAT_EXCAUSE);
        r6.h = hi(SEQSTAT_EXCAUSE);
        r7 = r7 & r6;
-        p5.h = _extable;
+        p5.h = _ex_table;
-        p5.l = _extable;
+        p5.l = _ex_table;
        p4 = r7;
        p5 = p5 + (p4 << 2);
        p4 = [p5];
@@ -634,9 +693,9 @@ ENTRY(_return_from_int)
        p1.h = _schedule_and_signal_from_int;
        [p0] = p1;
        csync;
-#if defined(ANOMALY_05000281)
+#if ANOMALY_05000281
-        r0.l = lo(CONFIG_BOOT_LOAD);
+        r0.l = _safe_speculative_execution;
-        r0.h = hi(CONFIG_BOOT_LOAD);
+        r0.h = _safe_speculative_execution;
        reti = r0;
 #endif
        r0 = 0x801f (z);
@@ -648,9 +707,9 @@ ENTRY(_return_from_int)
 ENDPROC(_return_from_int)
 ENTRY(_lower_to_irq14)
-#if defined(ANOMALY_05000281)
+#if ANOMALY_05000281
-        r0.l = lo(CONFIG_BOOT_LOAD);
+        r0.l = _safe_speculative_execution;
-        r0.h = hi(CONFIG_BOOT_LOAD);
+        r0.h = _safe_speculative_execution;
        reti = r0;
 #endif
        r0 = 0x401f;
@@ -731,6 +790,114 @@ ENTRY(_init_exception_buff)
        rts;
 ENDPROC(_init_exception_buff)
+/* We handle this 100% in exception space - to reduce overhead
+ * Only potiential problem is if the software buffer gets swapped out of the
+ * CPLB table - then double fault. - so we don't let this happen in other places
+ */
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
+ENTRY(_ex_trace_buff_full)
+        [--sp] = P3;
+        [--sp] = P2;
+        [--sp] = LC0;
+        [--sp] = LT0;
+        [--sp] = LB0;
+        P5.L = _trace_buff_offset;
+        P5.H = _trace_buff_offset;
+        P3 = [P5];              /* trace_buff_offset */
+        P5.L = lo(TBUFSTAT);
+        P5.H = hi(TBUFSTAT);
+        R7 = [P5];
+        R7 <<= 1;               /* double, since we need to read twice */
+        LC0 = R7;
+        R7 <<= 2;               /* need to shift over again,
+                                 * to get the number of bytes */
+        P5.L = lo(TBUF);
+        P5.H = hi(TBUF);
+        R6 = ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*1024) - 1;
+        P2 = R7;
+        P3 = P3 + P2;
+        R7 = P3;
+        R7 = R7 & R6;
+        P3 = R7;
+        P2.L = _trace_buff_offset;
+        P2.H = _trace_buff_offset;
+        [P2] = P3;
+        P2.L = _software_trace_buff;
+        P2.H = _software_trace_buff;
+        LSETUP (.Lstart, .Lend) LC0;
+.Lstart:
+        R7 = [P5];      /* read TBUF */
+        P4 = P3 + P2;
+        [P4] = R7;
+        P3 += -4;
+        R7 = P3;
+        R7 = R7 & R6;
+.Lend:
+        P3 = R7;
+        LB0 = [sp++];
+        LT0 = [sp++];
+        LC0 = [sp++];
+        P2 = [sp++];
+        P3 = [sp++];
+        jump _return_from_exception;
+ENDPROC(_ex_trace_buff_full)
+#if CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN == 4
+.data
+#else
+.section .l1.data.B
+#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN */
+ENTRY(_trace_buff_offset)
+        .long 0;
+ALIGN
+ENTRY(_software_trace_buff)
+        .rept ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN)*256);
+        .long 0
+        .endr
+#endif /* CONFIG_DEBUG_BFIN_HWTRACE_EXPAND */
+#if CONFIG_EARLY_PRINTK
+.section .init.text
+ENTRY(_early_trap)
+        SAVE_ALL_SYS
+        trace_buffer_stop(p0,r0);
+        /* Turn caches off, to ensure we don't get double exceptions */
+        P4.L = LO(IMEM_CONTROL);
+        P4.H = HI(IMEM_CONTROL);
+        R5 = [P4];              /* Control Register*/
+        BITCLR(R5,ENICPLB_P);
+        CLI R1;
+        SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
+        .align 8;
+        [P4] = R5;
+        SSYNC;
+        P4.L = LO(DMEM_CONTROL);
+        P4.H = HI(DMEM_CONTROL);
+        R5 = [P4];
+        BITCLR(R5,ENDCPLB_P);
+        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
+        .align 8;
+        [P4] = R5;
+        SSYNC;
+        STI R1;
+        r0 = sp;        /* stack frame pt_regs pointer argument ==> r0 */
+        r1 = RETX;
+        SP += -12;
+        call _early_trap_c;
+        SP += 12;
+ENDPROC(_early_trap)
+#endif /* CONFIG_EARLY_PRINTK */
 /*
 * Put these in the kernel data section - that should always be covered by
 * a CPLB. This is needed to ensure we don't get double fault conditions
@@ -741,30 +908,33 @@ ENDPROC(_init_exception_buff)
 #else
 .data
 #endif
-ALIGN
+ENTRY(_ex_table)
-_extable:
        /* entry for each EXCAUSE[5:0]
         * This table must be in sync with the table in ./kernel/traps.c
         * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined
         */
-        .long _ex_syscall;      /* 0x00 - User Defined - Linux Syscall */
+        .long _ex_syscall       /* 0x00 - User Defined - Linux Syscall */
        .long _ex_soft_bp       /* 0x01 - User Defined - Software breakpoint */
-        .long _ex_trap_c        /* 0x02 - User Defined */
+        .long _ex_replaceable   /* 0x02 - User Defined */
        .long _ex_trap_c        /* 0x03 - User Defined - userspace stack overflow */
-        .long _ex_trap_c        /* 0x04 - User Defined */
+        .long _ex_replaceable   /* 0x04 - User Defined */
-        .long _ex_trap_c        /* 0x05 - User Defined */
+        .long _ex_replaceable   /* 0x05 - User Defined */
-        .long _ex_trap_c        /* 0x06 - User Defined */
+        .long _ex_replaceable   /* 0x06 - User Defined */
-        .long _ex_trap_c        /* 0x07 - User Defined */
+        .long _ex_replaceable   /* 0x07 - User Defined */
-        .long _ex_trap_c        /* 0x08 - User Defined */
+        .long _ex_replaceable   /* 0x08 - User Defined */
-        .long _ex_trap_c        /* 0x09 - User Defined */
+        .long _ex_replaceable   /* 0x09 - User Defined */
-        .long _ex_trap_c        /* 0x0A - User Defined */
+        .long _ex_replaceable   /* 0x0A - User Defined */
-        .long _ex_trap_c        /* 0x0B - User Defined */
+        .long _ex_replaceable   /* 0x0B - User Defined */
-        .long _ex_trap_c        /* 0x0C - User Defined */
+        .long _ex_replaceable   /* 0x0C - User Defined */
-        .long _ex_trap_c        /* 0x0D - User Defined */
+        .long _ex_replaceable   /* 0x0D - User Defined */
-        .long _ex_trap_c        /* 0x0E - User Defined */
+        .long _ex_replaceable   /* 0x0E - User Defined */
-        .long _ex_trap_c        /* 0x0F - User Defined */
+        .long _ex_replaceable   /* 0x0F - User Defined */
        .long _ex_single_step   /* 0x10 - HW Single step */
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
+        .long _ex_trace_buff_full /* 0x11 - Trace Buffer Full */
+#else
        .long _ex_trap_c        /* 0x11 - Trace Buffer Full */
+#endif
        .long _ex_trap_c        /* 0x12 - Reserved */
        .long _ex_trap_c        /* 0x13 - Reserved */
        .long _ex_trap_c        /* 0x14 - Reserved */
@@ -812,8 +982,8 @@ _extable:
        .long _ex_trap_c        /* 0x3D - Reserved */
        .long _ex_trap_c        /* 0x3E - Reserved */
        .long _ex_trap_c        /* 0x3F - Reserved */
+END(_ex_table)
-ALIGN
 ENTRY(_sys_call_table)
        .long _sys_restart_syscall      /* 0 */
        .long _sys_exit
@@ -1184,7 +1354,7 @@ _exception_stack:
        .endr
 _exception_stack_top:
-#if defined(ANOMALY_05000261)
+#if ANOMALY_05000261
 /* Used by the assembly entry point to work around an anomaly.  */
 _last_cplb_fault_retx:
        .long 0;
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 203e20709163..c6b32fe0f6e9 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -46,30 +46,6 @@
 .align 4        /* just in case */
-/*
- * initial interrupt handlers
- */
-#ifndef CONFIG_KGDB
-        /* interrupt routine for emulation - 0 */
-        /* Currently used only if GDB stub is not in - invalid */
-        /* gdb-stub set the evt itself */
-        /* save registers for post-mortem only */
-ENTRY(_evt_emulation)
-        SAVE_ALL_SYS
-#ifdef CONFIG_FRAME_POINTER
-        fp = 0;
-#endif
-        r0 = IRQ_EMU;
-        r1 = sp;
-        SP += -12;
-        call _irq_panic;
-        SP += 12;
-        /* - GDB stub fills this in by itself (if defined) */
-        rte;
-ENDPROC(_evt_emulation)
-#endif
 /* Common interrupt entry code.  First we do CLI, then push
 * RETI, to keep interrupts disabled, but to allow this state to be changed
 * by local_bh_enable.
@@ -140,7 +116,7 @@ __common_int_entry:
        fp = 0;
 #endif
-#if defined (ANOMALY_05000283) || defined (ANOMALY_05000315)
+#if ANOMALY_05000283 || ANOMALY_05000315
        cc = r7 == r7;
        p5.h = 0xffc0;
        p5.l = 0x0014;
@@ -163,7 +139,7 @@ ENTRY(_evt_ivhw)
 #ifdef CONFIG_FRAME_POINTER
        fp = 0;
 #endif
-#ifdef  ANOMALY_05000283
+#if ANOMALY_05000283
        cc = r7 == r7;
        p5.h = 0xffc0;
        p5.l = 0x0014;
@@ -201,27 +177,15 @@ ENTRY(_evt_ivhw)
        jump .Lcommon_restore_context;
 #endif
-/* interrupt routine for evt2 - 2.  This is NMI.  */
+/* Interrupt routine for evt2 (NMI).
-ENTRY(_evt_evt2)
+ * We don't actually use this, so just return.
-        SAVE_CONTEXT
+ * For inner circle type details, please see:
-#ifdef CONFIG_FRAME_POINTER
+ * http://docs.blackfin.uclinux.org/doku.php?id=linux:nmi
-        fp = 0;
+ */
-#endif
+ENTRY(_evt_nmi)
-#ifdef  ANOMALY_05000283
+.weak _evt_nmi
-        cc = r7 == r7;
-        p5.h = 0xffc0;
-        p5.l = 0x0014;
-        if cc jump 1f;
-        r7.l = W[p5];
-1:
-#endif
-        r0 = IRQ_NMI;
-        r1 =  sp;
-        SP += -12;
-        call _asm_do_IRQ;
-        SP += 12;
-        RESTORE_CONTEXT
        rtn;
+ENDPROC(_evt_nmi)
 /* interrupt routine for core timer - 6 */
 ENTRY(_evt_timer)
diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c
index 660f881b620a..2db3546fc874 100644
--- a/arch/blackfin/mach-common/ints-priority-dc.c
+++ b/arch/blackfin/mach-common/ints-priority-dc.c
@@ -221,7 +221,7 @@ static unsigned int bf561_gpio_irq_startup(unsigned int irq)
        if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
-                ret = gpio_request(gpionr, NULL);
+                ret = gpio_request(gpionr, "IRQ");
                if (ret)
                        return ret;
@@ -261,7 +261,7 @@ static int bf561_gpio_irq_type(unsigned int irq, unsigned int type)
                if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
-                        ret = gpio_request(gpionr, NULL);
+                        ret = gpio_request(gpionr, "IRQ");
                        if (ret)
                                return ret;
@@ -362,10 +362,11 @@ void __init init_exception_vectors(void)
 {
        SSYNC();
-#ifndef CONFIG_KGDB
+        /* cannot program in software:
-        bfin_write_EVT0(evt_emulation);
+         * evt0 - emulation (jtag)
-#endif
+         * evt1 - reset
-        bfin_write_EVT2(evt_evt2);
+         */
+        bfin_write_EVT2(evt_nmi);
        bfin_write_EVT3(trap);
        bfin_write_EVT5(evt_ivhw);
        bfin_write_EVT6(evt_timer);
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c
index 4708023fe716..d3b7672b2b94 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority-sc.c
@@ -343,7 +343,7 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
        u16 gpionr = irq - IRQ_PF0;
        if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
-                ret = gpio_request(gpionr, NULL);
+                ret = gpio_request(gpionr, "IRQ");
                if (ret)
                        return ret;
        }
@@ -377,7 +377,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
                    IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
                if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
-                        ret = gpio_request(gpionr, NULL);
+                        ret = gpio_request(gpionr, "IRQ");
                        if (ret)
                                return ret;
                }
@@ -587,7 +587,7 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
        }
        if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
-                ret = gpio_request(gpionr, NULL);
+                ret = gpio_request(gpionr, "IRQ");
                if (ret)
                        return ret;
        }
@@ -627,7 +627,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
                    IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
                if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
-                        ret = gpio_request(gpionr, NULL);
+                        ret = gpio_request(gpionr, "IRQ");
                        if (ret)
                                return ret;
                }
@@ -721,10 +721,11 @@ void __init init_exception_vectors(void)
 {
        SSYNC();
-#ifndef CONFIG_KGDB
+        /* cannot program in software:
-        bfin_write_EVT0(evt_emulation);
+         * evt0 - emulation (jtag)
-#endif
+         * evt1 - reset
-        bfin_write_EVT2(evt_evt2);
+         */
+        bfin_write_EVT2(evt_nmi);
        bfin_write_EVT3(trap);
        bfin_write_EVT5(evt_ivhw);
        bfin_write_EVT6(evt_timer);
diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S
index 386ac8dda076..28b87fe9ce3c 100644
--- a/arch/blackfin/mach-common/lock.S
+++ b/arch/blackfin/mach-common/lock.S
@@ -33,7 +33,7 @@
 .text
-#ifdef CONFIG_BLKFIN_CACHE_LOCK
+#ifdef CONFIG_BFIN_ICACHE_LOCK
 /* When you come here, it is assumed that
 * R0 - Which way to be locked
@@ -43,12 +43,12 @@ ENTRY(_cache_grab_lock)
        [--SP]=( R7:0,P5:0 );
-        P1.H = (IMEM_CONTROL >> 16);
+        P1.H = HI(IMEM_CONTROL);
-        P1.L = (IMEM_CONTROL & 0xFFFF);
+        P1.L = LO(IMEM_CONTROL);
-        P5.H = (ICPLB_ADDR0 >> 16);
+        P5.H = HI(ICPLB_ADDR0);
-        P5.L = (ICPLB_ADDR0 & 0xFFFF);
+        P5.L = LO(ICPLB_ADDR0);
-        P4.H = (ICPLB_DATA0 >> 16);
+        P4.H = HI(ICPLB_DATA0);
-        P4.L = (ICPLB_DATA0 & 0xFFFF);
+        P4.L = LO(ICPLB_DATA0);
        R7 = R0;
        /* If the code of interest already resides in the cache
@@ -167,8 +167,8 @@ ENTRY(_cache_lock)
        [--SP]=( R7:0,P5:0 );
-        P1.H = (IMEM_CONTROL >> 16);
+        P1.H = HI(IMEM_CONTROL);
-        P1.L = (IMEM_CONTROL & 0xFFFF);
+        P1.L = LO(IMEM_CONTROL);
        /* Disable the Interrupts*/
        CLI R3;
@@ -189,14 +189,14 @@ ENTRY(_cache_lock)
        RTS;
 ENDPROC(_cache_lock)
-#endif  /* BLKFIN_CACHE_LOCK */
+#endif  /* BFIN_ICACHE_LOCK */
 /* Return the ILOC bits of IMEM_CONTROL
 */
 ENTRY(_read_iloc)
-        P1.H = (IMEM_CONTROL >> 16);
+        P1.H = HI(IMEM_CONTROL);
-        P1.L = (IMEM_CONTROL & 0xFFFF);
+        P1.L = LO(IMEM_CONTROL);
        R1 = 0xF;
        R0 = [P1];
        R0 = R0 >> 3;
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 68459cc052a1..e97ea8fc8dc4 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -53,7 +53,7 @@ static unsigned long empty_bad_page;
 unsigned long empty_zero_page;
-void __init show_mem(void)
+void show_mem(void)
 {
        unsigned long i;
        int free = 0, total = 0, reserved = 0, shared = 0;
diff --git a/arch/blackfin/oprofile/op_blackfin.h b/arch/blackfin/oprofile/op_blackfin.h
index f88f446c814f..05dd08c9d154 100644
--- a/arch/blackfin/oprofile/op_blackfin.h
+++ b/arch/blackfin/oprofile/op_blackfin.h
@@ -68,7 +68,7 @@ static inline unsigned int ctr_read(void)
        unsigned int tmp;
        tmp = bfin_read_PFCTL();
-        __builtin_bfin_csync();
+        CSYNC();
        return tmp;
 }
@@ -76,21 +76,21 @@ static inline unsigned int ctr_read(void)
 static inline void ctr_write(unsigned int val)
 {
        bfin_write_PFCTL(val);
-        __builtin_bfin_csync();
+        CSYNC();
 }
 static inline void count_read(unsigned int *count)
 {
        count[0] = bfin_read_PFCNTR0();
        count[1] = bfin_read_PFCNTR1();
-        __builtin_bfin_csync();
+        CSYNC();
 }
 static inline void count_write(unsigned int *count)
 {
        bfin_write_PFCNTR0(count[0]);
        bfin_write_PFCNTR1(count[1]);
-        __builtin_bfin_csync();
+        CSYNC();
 }
 extern int pm_overflow_handler(int irq, struct pt_regs *regs);
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c
index 66c92bc36f3d..6f475b609864 100644
--- a/drivers/serial/bfin_5xx.c
+++ b/drivers/serial/bfin_5xx.c
@@ -86,10 +86,8 @@ static void bfin_serial_stop_tx(struct uart_port *port)
 {
        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
-#ifdef CONFIG_BF54x
        while (!(UART_GET_LSR(uart) & TEMT))
                continue;
-#endif
 #ifdef CONFIG_SERIAL_BFIN_DMA
        disable_dma(uart->tx_dma_channel);
@@ -128,8 +126,8 @@ static void bfin_serial_start_tx(struct uart_port *port)
        ier = UART_GET_IER(uart);
        ier |= ETBEI;
        UART_PUT_IER(uart, ier);
-        bfin_serial_tx_chars(uart);
 #endif
+        bfin_serial_tx_chars(uart);
 #endif
 }
@@ -139,18 +137,21 @@ static void bfin_serial_start_tx(struct uart_port *port)
 static void bfin_serial_stop_rx(struct uart_port *port)
 {
        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+#ifdef  CONFIG_KGDB_UART
+        if (uart->port.line != CONFIG_KGDB_UART_PORT) {
+#endif
 #ifdef CONFIG_BF54x
        UART_CLEAR_IER(uart, ERBFI);
 #else
        unsigned short ier;
        ier = UART_GET_IER(uart);
-#ifdef  CONFIG_KGDB_UART
-        if (uart->port.line != CONFIG_KGDB_UART_PORT)
-#endif
        ier &= ~ERBFI;
        UART_PUT_IER(uart, ier);
 #endif
+#ifdef  CONFIG_KGDB_UART
+        }
+#endif
 }
 /*
@@ -173,12 +174,15 @@ void kgdb_put_debug_char(int chr)
                uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
        
        while (!(UART_GET_LSR(uart) & THRE)) {
-                __builtin_bfin_ssync();
+                SSYNC();
        }
+#ifndef CONFIG_BF54x
        UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
-        __builtin_bfin_ssync();
+        SSYNC();
+#endif
        UART_PUT_CHAR(uart, (unsigned char)chr);
-        __builtin_bfin_ssync();
+        SSYNC();
 }
 int kgdb_get_debug_char(void)
@@ -192,12 +196,14 @@ int kgdb_get_debug_char(void)
                uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
        
        while(!(UART_GET_LSR(uart) & DR)) {
-                __builtin_bfin_ssync();
+                SSYNC();
        }
+#ifndef CONFIG_BF54x
        UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
-        __builtin_bfin_ssync();
+        SSYNC();
+#endif
        chr = UART_GET_CHAR(uart);
-        __builtin_bfin_ssync();
+        SSYNC();
        return chr;
 }
@@ -225,12 +231,10 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
 {
        struct tty_struct *tty = uart->port.info->tty;
        unsigned int status, ch, flg;
+        static int in_break = 0;
 #ifdef CONFIG_KGDB_UART
        struct pt_regs *regs = get_irq_regs();
 #endif
-#ifdef BF533_FAMILY
-        static int in_break = 0;
-#endif
        status = UART_GET_LSR(uart);
        ch = UART_GET_CHAR(uart);
@@ -256,29 +260,30 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
                }
        }
 #endif
- 
-#ifdef BF533_FAMILY
+        if (ANOMALY_05000230) {
-        /* The BF533 family of processors have a nice misbehavior where
+                /* The BF533 family of processors have a nice misbehavior where
-         * they continuously generate characters for a "single" break.
+                 * they continuously generate characters for a "single" break.
-         * We have to basically ignore this flood until the "next" valid
+                 * We have to basically ignore this flood until the "next" valid
-         * character comes across.  All other Blackfin families operate
+                 * character comes across.  All other Blackfin families operate
-         * properly though.
+                 * properly though.
-         */
+                 * Note: While Anomaly 05000230 does not directly address this,
-        if (in_break) {
+                 *       the changes that went in for it also fixed this issue.
-                if (ch != 0) {
+                 */
-                        in_break = 0;
+                if (in_break) {
-                        ch = UART_GET_CHAR(uart);
+                        if (ch != 0) {
-                        if (bfin_revid() < 5)
+                                in_break = 0;
+                                ch = UART_GET_CHAR(uart);
+                                if (bfin_revid() < 5)
+                                        return;
+                        } else
                                return;
-                } else
+                }
-                        return;
        }
-#endif
        if (status & BI) {
-#ifdef BF533_FAMILY
+                if (ANOMALY_05000230)
-                in_break = 1;
+                        in_break = 1;
-#endif
                uart->port.icount.brk++;
                if (uart_handle_break(&uart->port))
                        goto ignore_char;
@@ -697,17 +702,19 @@ static int bfin_serial_startup(struct uart_port *port)
        uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
        add_timer(&(uart->rx_dma_timer));
 #else
+        if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
+             "BFIN_UART_RX", uart)) {
 # ifdef CONFIG_KGDB_UART
-        if (uart->port.line != CONFIG_KGDB_UART_PORT && request_irq
+                if (uart->port.line != CONFIG_KGDB_UART_PORT) {
-# else
-        if (request_irq
 # endif
-            (uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
-             "BFIN_UART_RX", uart)) {
                printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
                return -EBUSY;
+# ifdef CONFIG_KGDB_UART
+                }
+# endif
        }
        if (request_irq
            (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
             "BFIN_UART_TX", uart)) {
@@ -962,30 +969,6 @@ static void __init bfin_serial_init_ports(void)
 }
 #ifdef CONFIG_SERIAL_BFIN_CONSOLE
-static void bfin_serial_console_putchar(struct uart_port *port, int ch)
-{
-        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
-        while (!(UART_GET_LSR(uart) & THRE))
-                barrier();
-        UART_PUT_CHAR(uart, ch);
-        SSYNC();
-}
-/*
- * Interrupts are disabled on entering
- */
-static void
-bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
-{
-        struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
-        int flags = 0;
-        spin_lock_irqsave(&uart->port.lock, flags);
-        uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
-        spin_unlock_irqrestore(&uart->port.lock, flags);
-}
 /*
 * If the port was already initialised (eg, by a boot loader),
 * try to determine the current setup.
@@ -1038,19 +1021,25 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
        }
        pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __FUNCTION__, *baud, *parity, *bits);
 }
+#endif
+#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
+static struct uart_driver bfin_serial_reg;
 static int __init
 bfin_serial_console_setup(struct console *co, char *options)
 {
        struct bfin_serial_port *uart;
+# ifdef CONFIG_SERIAL_BFIN_CONSOLE
        int baud = 57600;
        int bits = 8;
        int parity = 'n';
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+#  ifdef CONFIG_SERIAL_BFIN_CTSRTS
        int flow = 'r';
-#else
+#  else
        int flow = 'n';
-#endif
+#  endif
+# endif
        /*
         * Check whether an invalid uart number has been specified, and
@@ -1061,15 +1050,45 @@ bfin_serial_console_setup(struct console *co, char *options)
                co->index = 0;
        uart = &bfin_serial_ports[co->index];
+# ifdef CONFIG_SERIAL_BFIN_CONSOLE
        if (options)
                uart_parse_options(options, &baud, &parity, &bits, &flow);
        else
                bfin_serial_console_get_options(uart, &baud, &parity, &bits);
        return uart_set_options(&uart->port, co, baud, parity, bits, flow);
+# else
+        return 0;
+# endif
+}
+#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
+                                 defined (CONFIG_EARLY_PRINTK) */
+#ifdef CONFIG_SERIAL_BFIN_CONSOLE
+static void bfin_serial_console_putchar(struct uart_port *port, int ch)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+        while (!(UART_GET_LSR(uart) & THRE))
+                barrier();
+        UART_PUT_CHAR(uart, ch);
+        SSYNC();
+}
+/*
+ * Interrupts are disabled on entering
+ */
+static void
+bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
+{
+        struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
+        int flags = 0;
+        spin_lock_irqsave(&uart->port.lock, flags);
+        uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
+        spin_unlock_irqrestore(&uart->port.lock, flags);
 }
-static struct uart_driver bfin_serial_reg;
 static struct console bfin_serial_console = {
        .name           = BFIN_SERIAL_NAME,
        .write          = bfin_serial_console_write,
@@ -1095,7 +1114,64 @@ console_initcall(bfin_serial_rs_console_init);
 #define BFIN_SERIAL_CONSOLE     &bfin_serial_console
 #else
 #define BFIN_SERIAL_CONSOLE     NULL
-#endif
+#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
+#ifdef CONFIG_EARLY_PRINTK
+static __init void early_serial_putc(struct uart_port *port, int ch)
+{
+        unsigned timeout = 0xffff;
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+        while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
+                cpu_relax();
+        UART_PUT_CHAR(uart, ch);
+}
+static __init void early_serial_write(struct console *con, const char *s,
+                                        unsigned int n)
+{
+        struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
+        unsigned int i;
+        for (i = 0; i < n; i++, s++) {
+                if (*s == '\n')
+                        early_serial_putc(&uart->port, '\r');
+                early_serial_putc(&uart->port, *s);
+        }
+}
+static struct __init console bfin_early_serial_console = {
+        .name = "early_BFuart",
+        .write = early_serial_write,
+        .device = uart_console_device,
+        .flags = CON_PRINTBUFFER,
+        .setup = bfin_serial_console_setup,
+        .index = -1,
+        .data  = &bfin_serial_reg,
+};
+struct console __init *bfin_earlyserial_init(unsigned int port,
+                                                unsigned int cflag)
+{
+        struct bfin_serial_port *uart;
+        struct ktermios t;
+        if (port == -1 || port >= nr_ports)
+                port = 0;
+        bfin_serial_init_ports();
+        bfin_early_serial_console.index = port;
+        uart = &bfin_serial_ports[port];
+        t.c_cflag = cflag;
+        t.c_iflag = 0;
+        t.c_oflag = 0;
+        t.c_lflag = ICANON;
+        t.c_line = port;
+        bfin_serial_set_termios(&uart->port, &t, &t);
+        return &bfin_early_serial_console;
+}
+#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
 static struct uart_driver bfin_serial_reg = {
        .owner                  = THIS_MODULE,
@@ -1182,7 +1258,7 @@ static int __init bfin_serial_init(void)
        int ret;
 #ifdef CONFIG_KGDB_UART
        struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
-        struct termios t;
+        struct ktermios t;
 #endif
        pr_info("Serial: Blackfin serial driver\n");
@@ -1199,11 +1275,15 @@ static int __init bfin_serial_init(void)
        }
 #ifdef CONFIG_KGDB_UART
        if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) {
-                request_irq(uart->port.irq, bfin_serial_int,
+                request_irq(uart->port.irq, bfin_serial_rx_int,
                        IRQF_DISABLED, "BFIN_UART_RX", uart);
                pr_info("Request irq for kgdb uart port\n");
+#ifdef CONFIG_BF54x
+                UART_SET_IER(uart, ERBFI);
+#else
                UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
-                __builtin_bfin_ssync();
+#endif
+                SSYNC();
                t.c_cflag = CS8|B57600;
                t.c_iflag = 0;
                t.c_oflag = 0;
diff --git a/include/asm-blackfin/bfin5xx_spi.h b/include/asm-blackfin/bfin5xx_spi.h
index 95c1c952e7c1..f617d8765451 100644
--- a/include/asm-blackfin/bfin5xx_spi.h
+++ b/include/asm-blackfin/bfin5xx_spi.h
@@ -21,8 +21,6 @@
 #ifndef _SPI_CHANNEL_H_
 #define _SPI_CHANNEL_H_
-#define SPI0_REGBASE       0xffc00500
 #define SPI_READ              0
 #define SPI_WRITE             1
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
index 25b934b7f829..984b74f0a2ec 100644
--- a/include/asm-blackfin/blackfin.h
+++ b/include/asm-blackfin/blackfin.h
@@ -11,78 +11,57 @@
 #define HI(con32) (((con32) >> 16) & 0xFFFF)
 #define hi(con32) (((con32) >> 16) & 0xFFFF)
-#include <asm/mach/blackfin.h>
+#include <asm/mach/anomaly.h>
-#include <asm/bfin-global.h>
 #ifndef __ASSEMBLY__
 /* SSYNC implementation for C file */
-#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+static inline void SSYNC(void)
-static inline void SSYNC (void)
-{
-        int _tmp;
-        __asm__ __volatile__ ("cli %0;\n\t"
-                        "nop;nop;\n\t"
-                        "ssync;\n\t"
-                        "sti %0;\n\t"
-                        :"=d"(_tmp):);
-}
-#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
-static inline void SSYNC (void)
 {
        int _tmp;
-        __asm__ __volatile__ ("cli %0;\n\t"
+        if (ANOMALY_05000312)
-                        "ssync;\n\t"
+                __asm__ __volatile__(
-                        "sti %0;\n\t"
+                        "cli %0;"
-                        :"=d"(_tmp):);
+                        "nop;"
+                        "nop;"
+                        "ssync;"
+                        "sti %0;"
+                        : "=d" (_tmp)
+                );
+        else if (ANOMALY_05000244)
+                __asm__ __volatile__(
+                        "nop;"
+                        "nop;"
+                        "nop;"
+                        "ssync;"
+                );
+        else
+                __asm__ __volatile__("ssync;");
 }
-#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
-static inline void SSYNC (void)
-{
-        __asm__ __volatile__ ("nop; nop; nop;\n\t"
-                        "ssync;\n\t"
-                        ::);
-}
-#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
-static inline void SSYNC (void)
-{
-        __asm__ __volatile__ ("ssync;\n\t");
-}
-#endif
 /* CSYNC implementation for C file */
-#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+static inline void CSYNC(void)
-static inline void CSYNC (void)
-{
-        int _tmp;
-        __asm__ __volatile__ ("cli %0;\n\t"
-                        "nop;nop;\n\t"
-                        "csync;\n\t"
-                        "sti %0;\n\t"
-                        :"=d"(_tmp):);
-}
-#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
-static inline void CSYNC (void)
 {
        int _tmp;
-        __asm__ __volatile__ ("cli %0;\n\t"
+        if (ANOMALY_05000312)
-                        "csync;\n\t"
+                __asm__ __volatile__(
-                        "sti %0;\n\t"
+                        "cli %0;"
-                        :"=d"(_tmp):);
+                        "nop;"
-}
+                        "nop;"
-#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+                        "csync;"
-static inline void CSYNC (void)
+                        "sti %0;"
-{
+                        : "=d" (_tmp)
-        __asm__ __volatile__ ("nop; nop; nop;\n\t"
+                );
-                        "ssync;\n\t"
+        else if (ANOMALY_05000244)
-                        ::);
+                __asm__ __volatile__(
+                        "nop;"
+                        "nop;"
+                        "nop;"
+                        "csync;"
+                );
+        else
+                __asm__ __volatile__("csync;");
 }
-#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
-static inline void CSYNC (void)
-{
-        __asm__ __volatile__ ("csync;\n\t");
-}
-#endif
 #else  /* __ASSEMBLY__ */
@@ -91,19 +70,15 @@ static inline void CSYNC (void)
 #define ssync(x) SSYNC(x)
 #define csync(x) CSYNC(x)
-#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+#if ANOMALY_05000312
 #define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
 #define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
-#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
+#elif ANOMALY_05000244
-#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
-#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
-#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
 #define SSYNC(scratch) nop; nop; nop; SSYNC;
 #define CSYNC(scratch) nop; nop; nop; CSYNC;
-#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
+#else
 #define SSYNC(scratch) SSYNC;
 #define CSYNC(scratch) CSYNC;
@@ -111,4 +86,7 @@ static inline void CSYNC (void)
 #endif /* __ASSEMBLY__ */
+#include <asm/mach/blackfin.h>
+#include <asm/bfin-global.h>
 #endif                          /* _BLACKFIN_H_ */
diff --git a/include/asm-blackfin/cacheflush.h b/include/asm-blackfin/cacheflush.h
index e5e000de3c36..d81a77545a04 100644
--- a/include/asm-blackfin/cacheflush.h
+++ b/include/asm-blackfin/cacheflush.h
@@ -48,9 +48,9 @@ extern void blackfin_dflush_page(void *);
 static inline void flush_icache_range(unsigned start, unsigned end)
 {
-#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_CACHE)
+#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE)
-# if defined(CONFIG_BLKFIN_WT)
+# if defined(CONFIG_BFIN_WT)
        blackfin_icache_flush_range((start), (end));
 # else
        blackfin_icache_dcache_flush_range((start), (end));
@@ -58,10 +58,10 @@ static inline void flush_icache_range(unsigned start, unsigned end)
 #else
-# if defined(CONFIG_BLKFIN_CACHE)
+# if defined(CONFIG_BFIN_ICACHE)
        blackfin_icache_flush_range((start), (end));
 # endif
-# if defined(CONFIG_BLKFIN_DCACHE)
+# if defined(CONFIG_BFIN_DCACHE)
        blackfin_dcache_flush_range((start), (end));
 # endif
@@ -74,12 +74,12 @@ do { memcpy(dst, src, len); \
 } while (0)
 #define copy_from_user_page(vma, page, vaddr, dst, src, len)    memcpy(dst, src, len)
-#if defined(CONFIG_BLKFIN_DCACHE)
+#if defined(CONFIG_BFIN_DCACHE)
 # define invalidate_dcache_range(start,end)     blackfin_dcache_invalidate_range((start), (end))
 #else
 # define invalidate_dcache_range(start,end)     do { } while (0)
 #endif
-#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_WB)
+#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB)
 # define flush_dcache_range(start,end)          blackfin_dcache_flush_range((start), (end))
 # define flush_dcache_page(page)                        blackfin_dflush_page(page_address(page))
 #else
@@ -87,4 +87,4 @@ do { memcpy(dst, src, len); \
 # define flush_dcache_page(page)                        do { } while (0)
 #endif
-#endif                          /* _BLACKFIN_CACHEFLUSH_H */
+#endif                          /* _BLACKFIN_ICACHEFLUSH_H */
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
index e0dd56bfa4c7..06828d77a58f 100644
--- a/include/asm-blackfin/cplb.h
+++ b/include/asm-blackfin/cplb.h
@@ -1,17 +1,100 @@
-/************************************************************************
+/*
+ * File:         include/asm-blackfin/cplb.h
+ * Based on:     include/asm-blackfin/mach-bf537/bf537.h
+ * Author:       Robin Getz <rgetz@blackfin.uclinux.org>
 *
- * cplb.h
+ * Created:      2000
+ * Description:  Common CPLB definitions for CPLB init
 *
- * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
 *
- ************************************************************************/
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
-/* Defines necessary for cplb initialisation routines. */
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
 #ifndef _CPLB_H
 #define _CPLB_H
-# include <asm/blackfin.h>
+#include <asm/blackfin.h>
+#include <asm/mach/anomaly.h>
+#define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
+#define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
+#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
+/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
+#if ANOMALY_05000158
+#define ANOMALY_05000158_WORKAROUND             0x200
+#else
+#define ANOMALY_05000158_WORKAROUND             0x0
+#endif
+#define CPLB_COMMON     (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#ifdef CONFIG_BFIN_WB         /*Write Back Policy */
+#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_COMMON)
+#else                           /*Write Through */
+#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_COMMON)
+#endif
+#define L1_DMEMORY       (CPLB_LOCK | CPLB_COMMON)
+#define L2_MEMORY        (CPLB_COMMON)
+#define SDRAM_DNON_CHBL  (CPLB_COMMON)
+#define SDRAM_EBIU       (CPLB_COMMON)
+#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
+#define SIZE_1K 0x00000400      /* 1K */
+#define SIZE_4K 0x00001000      /* 4K */
+#define SIZE_1M 0x00100000      /* 1M */
+#define SIZE_4M 0x00400000      /* 4M */
+#define MAX_CPLBS (16 * 2)
+#define ASYNC_MEMORY_CPLB_COVERAGE      ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
+                                 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
+/*
+* Number of required data CPLB switchtable entries
+* MEMSIZE / 4 (we mostly install 4M page size CPLBs
+* approx 16 for smaller 1MB page size CPLBs for allignment purposes
+* 1 for L1 Data Memory
+* possibly 1 for L2 Data Memory
+* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
+* 1 for ASYNC Memory
+*/
+#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \
+                                 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)
+/*
+* Number of required instruction CPLB switchtable entries
+* MEMSIZE / 4 (we mostly install 4M page size CPLBs
+* approx 12 for smaller 1MB page size CPLBs for allignment purposes
+* 1 for L1 Instruction Memory
+* possibly 1 for L2 Instruction Memory
+* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
+*/
+#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
 #define CPLB_ENABLE_ICACHE_P    0
 #define CPLB_ENABLE_DCACHE_P    1
@@ -39,8 +122,6 @@
 #define CPLB_DEF_CACHE          CPLB_L1_CHBL | CPLB_WT
 #define CPLB_CACHE_ENABLED      CPLB_L1_CHBL | CPLB_DIRTY
-#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
 #define CPLB_I_PAGE_MGMT        CPLB_LOCK | CPLB_VALID
 #define CPLB_D_PAGE_MGMT        CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
 #define CPLB_DNOCACHE           CPLB_ALL_ACCESS | CPLB_VALID
diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h
index be0d913e5516..b42a531e7a1b 100644
--- a/include/asm-blackfin/dma.h
+++ b/include/asm-blackfin/dma.h
@@ -152,6 +152,7 @@ struct dma_channel {
 /* functions to set register mode */
 void set_dma_start_addr(unsigned int channel, unsigned long addr);
 void set_dma_next_desc_addr(unsigned int channel, unsigned long addr);
+void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr);
 void set_dma_x_count(unsigned int channel, unsigned short x_count);
 void set_dma_x_modify(unsigned int channel, short x_modify);
 void set_dma_y_count(unsigned int channel, unsigned short y_count);
@@ -159,6 +160,7 @@ void set_dma_y_modify(unsigned int channel, short y_modify);
 void set_dma_config(unsigned int channel, unsigned short config);
 unsigned short set_bfin_dma_config(char direction, char flow_mode,
                                   char intr_mode, char dma_mode, char width);
+void set_dma_curr_addr(unsigned int channel, unsigned long addr);
 /* get curr status for polling */
 unsigned short get_dma_curr_irqstat(unsigned int channel);
diff --git a/include/asm-blackfin/early_printk.h b/include/asm-blackfin/early_printk.h
new file mode 100644
index 000000000000..110f1c1f845c
--- /dev/null
+++ b/include/asm-blackfin/early_printk.h
@@ -0,0 +1,28 @@
+/*
+ * File:         include/asm-blackfin/early_printk.h
+ * Author:       Robin Getz <rgetz@blackfin.uclinux.org
+ *
+ * Created:      14Aug2007
+ * Description:  function prototpyes for early printk
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifdef CONFIG_EARLY_PRINTK
+extern int setup_early_printk(char *);
+#else
+#define setup_early_printk(fmt) do { } while (0)
+#endif /* CONFIG_EARLY_PRINTK */
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index 7480cfa7e2d6..dd203cd93796 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -144,6 +144,24 @@
 #ifdef BF533_FAMILY
 #define MAX_BLACKFIN_GPIOS 16
+#define GPIO_PF0        0
+#define GPIO_PF1        1
+#define GPIO_PF2        2
+#define GPIO_PF3        3
+#define GPIO_PF4        4
+#define GPIO_PF5        5
+#define GPIO_PF6        6
+#define GPIO_PF7        7
+#define GPIO_PF8        8
+#define GPIO_PF9        9
+#define GPIO_PF10       10
+#define GPIO_PF11       11
+#define GPIO_PF12       12
+#define GPIO_PF13       13
+#define GPIO_PF14       14
+#define GPIO_PF15       15
 #endif
 #ifdef BF537_FAMILY
@@ -421,6 +439,19 @@ unsigned short gpio_get_value(unsigned short gpio);
 void gpio_direction_input(unsigned short gpio);
 void gpio_direction_output(unsigned short gpio);
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
+#include <asm/irq.h>
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return (gpio + GPIO_IRQ_BASE);
+}
+static inline int irq_to_gpio(unsigned irq)
+{
+        return (irq - GPIO_IRQ_BASE);
+}
 #endif /* __ASSEMBLY__ */
 #endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index 142cb333db29..525179bf43d7 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -115,21 +115,21 @@ static inline unsigned int readl(const volatile void __iomem *addr)
 #ifndef __ASSEMBLY__
-extern void outsb(void __iomem *port, const void *addr, unsigned short count);
+extern void outsb(unsigned long port, const void *addr, unsigned long count);
-extern void outsw(void __iomem *port, const void *addr, unsigned short count);
+extern void outsw(unsigned long port, const void *addr, unsigned long count);
-extern void outsl(void __iomem *port, const void *addr, unsigned short count);
+extern void outsl(unsigned long port, const void *addr, unsigned long count);
-extern void insb(const void __iomem *port, void *addr, unsigned short count);
+extern void insb(unsigned long port, void *addr, unsigned long count);
-extern void insw(const void __iomem *port, void *addr, unsigned short count);
+extern void insw(unsigned long port, void *addr, unsigned long count);
-extern void insl(const void __iomem *port, void *addr, unsigned short count);
+extern void insl(unsigned long port, void *addr, unsigned long count);
-extern void dma_outsb(void __iomem *port, const void *addr, unsigned short count);
+extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
-extern void dma_outsw(void __iomem *port, const void *addr, unsigned short count);
+extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
-extern void dma_outsl(void __iomem *port, const void *addr, unsigned short count);
+extern void dma_outsl(unsigned long port, const void *addr, unsigned short count);
-extern void dma_insb(const void __iomem *port, void *addr, unsigned short count);
+extern void dma_insb(unsigned long port, void *addr, unsigned short count);
-extern void dma_insw(const void __iomem *port, void *addr, unsigned short count);
+extern void dma_insw(unsigned long port, void *addr, unsigned short count);
-extern void dma_insl(const void __iomem *port, void *addr, unsigned short count);
+extern void dma_insl(unsigned long port, void *addr, unsigned short count);
 /*
 * Map some physical address range into the kernel address space.
diff --git a/include/asm-blackfin/ioctls.h b/include/asm-blackfin/ioctls.h
index 8356204151db..895e3173165d 100644
--- a/include/asm-blackfin/ioctls.h
+++ b/include/asm-blackfin/ioctls.h
@@ -47,8 +47,13 @@
 #define TIOCSBRK        0x5427  /* BSD compatibility */
 #define TIOCCBRK        0x5428  /* BSD compatibility */
 #define TIOCGSID        0x5429  /* Return the session ID of FD */
-#define TIOCGPTN        _IOR('T',0x30, unsigned int)    /* Get Pty Number (of pty-mux device) */
+#define TCGETS2         _IOR('T', 0x2A, struct termios2)
-#define TIOCSPTLCK      _IOW('T',0x31, int)     /* Lock/unlock Pty */
+#define TCSETS2         _IOW('T', 0x2B, struct termios2)
+#define TCSETSW2        _IOW('T', 0x2C, struct termios2)
+#define TCSETSF2        _IOW('T', 0x2D, struct termios2)
+/* Get Pty Number (of pty-mux device) */
+#define TIOCGPTN        _IOR('T', 0x30, unsigned int)
+#define TIOCSPTLCK      _IOW('T', 0x31, int)    /* Lock/unlock Pty */
 #define FIONCLEX        0x5450  /* these numbers need to be adjusted. */
 #define FIOCLEX         0x5451
diff --git a/include/asm-blackfin/irq_handler.h b/include/asm-blackfin/irq_handler.h
index d830f0a49a1c..139b5208f9d8 100644
--- a/include/asm-blackfin/irq_handler.h
+++ b/include/asm-blackfin/irq_handler.h
@@ -1,13 +1,15 @@
 #ifndef _IRQ_HANDLER_H
 #define _IRQ_HANDLER_H
+#include <linux/types.h>
+#include <linux/linkage.h>
 /* BASE LEVEL interrupt handler routines */
-asmlinkage void evt_emulation(void);
 asmlinkage void evt_exception(void);
 asmlinkage void trap(void);
 asmlinkage void evt_ivhw(void);
 asmlinkage void evt_timer(void);
-asmlinkage void evt_evt2(void);
+asmlinkage void evt_nmi(void);
 asmlinkage void evt_evt7(void);
 asmlinkage void evt_evt8(void);
 asmlinkage void evt_evt9(void);
@@ -18,5 +20,14 @@ asmlinkage void evt_evt13(void);
 asmlinkage void evt_soft_int1(void);
 asmlinkage void evt_system_call(void);
 asmlinkage void init_exception_buff(void);
+asmlinkage void trap_c(struct pt_regs *fp);
+asmlinkage void ex_replaceable(void);
+asmlinkage void early_trap(void);
+extern void *ex_table[];
+extern void return_from_exception(void);
+extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
+extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
 #endif
diff --git a/include/asm-blackfin/kgdb.h b/include/asm-blackfin/kgdb.h
index 532bd9052004..0f73847fd6bc 100644
--- a/include/asm-blackfin/kgdb.h
+++ b/include/asm-blackfin/kgdb.h
@@ -179,5 +179,6 @@ enum regnames {
 #define STATDA1         0x80
 extern void kgdb_print(const char *fmt, ...);
+extern void init_kgdb_uart(void);
 #endif
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h
new file mode 100644
index 000000000000..991db986cd4b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/anomaly.h
@@ -0,0 +1,41 @@
+/*
+ * File: include/asm-blackfin/mach-bf527/anomaly.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+/* This file shoule be up to date with:
+ *  - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List
+ */
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
+#define ANOMALY_05000074 (1)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (1)
+/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
+#define ANOMALY_05000301 (1)
+/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (1)
+/* Incorrect Access of OTP_STATUS During otp_write() Function */
+#define ANOMALY_05000328 (1)
+/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
+#define ANOMALY_05000337 (1)
+/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */
+#define ANOMALY_05000342 (1)
+/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
+#define ANOMALY_05000347 (1)
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000323 (0)
+#endif
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h
index 0b2fb5036ed0..b1ff67db01f8 100644
--- a/include/asm-blackfin/mach-bf527/defBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h
@@ -102,6 +102,7 @@
 /* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
+#define SPI0_REGBASE                    0xFFC00500
 #define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
 #define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
 #define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
@@ -480,6 +481,7 @@
 /* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+#define TWI0_REGBASE                    0xFFC01400
 #define TWI_CLKDIV                      0xFFC01400      /* Serial Clock Divider Register                        */
 #define TWI_CONTROL                     0xFFC01404      /* TWI Control Register                                         */
 #define TWI_SLAVE_CTL           0xFFC01408      /* Slave Mode Control Register                          */
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
index 7302f290b93d..f36ff5af1b91 100644
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -1,247 +1,259 @@
 /*
- * File:         include/asm-blackfin/mach-bf533/anomaly.h
+ * File: include/asm-blackfin/mach-bf533/anomaly.h
- * Based on:
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
- * Author:
 *
- * Created:
+ * Copyright (C) 2004-2007 Analog Devices Inc.
- * Description:
+ * Licensed under the GPL-2 or later.
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */
 /* This file shoule be up to date with:
- *  - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List
+ *  - Revision X,  March 23, 2007; ADSP-BF533 Blackfin Processor Anomaly List
- *  - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List
+ *  - Revision AB, March 23, 2007; ADSP-BF532 Blackfin Processor Anomaly List
- *  - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List
+ *  - Revision W,  March 23, 2007; ADSP-BF531 Blackfin Processor Anomaly List
 */
 #ifndef _MACH_ANOMALY_H_
 #define _MACH_ANOMALY_H_
 /* We do not support 0.1 or 0.2 silicon - sorry */
-#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2))
+#if __SILICON_REVISION__ < 3
-#error Kernel will not work on BF533 Version 0.1 or 0.2
+# error Kernel will not work on BF533 silicon version 0.0, 0.1, or 0.2
 #endif
-/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
+#if defined(__ADSPBF531__)
-#if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) \
+# define ANOMALY_BF531 1
-                || defined(CONFIG_BF_REV_0_3))
+#else
-#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
+# define ANOMALY_BF531 0
-                            slot1 and store of a P register in slot 2 is not
+#endif
-                            supported */
+#if defined(__ADSPBF532__)
-#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
+# define ANOMALY_BF532 1
-                            every corresponding match */
+#else
-#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
+# define ANOMALY_BF532 0
-                            Channel DMA stops */
+#endif
-#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
+#if defined(__ADSPBF533__)
-                            registers. */
+# define ANOMALY_BF533 1
-#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
+#else
-                            upper bits*/
+# define ANOMALY_BF533 0
-#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
+#endif
-#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
-                            syncs */
-#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
-                            functional */
-#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
-                            state */
-#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
-#define ANOMALY_05000272 /* Certain data cache write through modes fail for
-                            VDDint <=0.9V */
-#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
-#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
-                            an edge is detected may clear interrupt */
-#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
-                            DMA system instability */
-#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
-                            not restored */
-#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
-                            control */
-#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
-                            killed in a particular stage*/
-#define ANOMALY_05000311 /* Erroneous flag pin operations under specific
-                            sequences */
-#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
-                            registers are interrupted */
-#define ANOMALY_05000313 /* PPI Is Level-Sensitive on First Transfer  */
-#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously On
-                          *  Next System MMR Access */
-#define ANOMALY_05000319 /* Internal Voltage Regulator Values of 1.05V, 1.10V
-                          *  and 1.15V Not Allowed for LQFP Packages */
-#endif /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
-/* These issues only occur on 0.3 or 0.4 BF533 */
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
-#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
+#define ANOMALY_05000074 (1)
-#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
+/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-                            updated at the same time. */
+#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
+/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
-                            Cache Fill can be corrupted after or during
+#define ANOMALY_05000105 (1)
-                            Instruction DMA if certain core stalls exist */
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
+#define ANOMALY_05000119 (1)
-                            Purpose TX or RX modes */
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
+#define ANOMALY_05000122 (1)
-                            preceding memory read */
+/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
-#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
+#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
-                            inactive channels in certain conditions */
+/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
+#define ANOMALY_05000166 (1)
-                            situation */
+/* Turning Serial Ports on with External Frame Syncs */
-#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
+#define ANOMALY_05000167 (1)
-#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
+/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
+#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-                            data*/
+/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
+#define ANOMALY_05000180 (1)
-                            Differences in certain Conditions */
+/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
+#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
-#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
+/* False Protection Exceptions */
-                            hardware reset */
+#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
-#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
+/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-                            IDLE around a Change of Control causes
+#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
-                            unpredictable results */
+/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
+#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
-                            shadow of a conditional branch */
+/* Failing MMR Accesses When Stalled by Preceding Memory Read */
-#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
+#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-                            errors */
+/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
+#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
+/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-                            interrupt not functional */
+#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
-#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
+/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
-                            loops may cause the instruction fetch unit to
+#define ANOMALY_05000201 (__SILICON_REVISION__ < 4)
-                            malfunction */
+/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
+#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-                            the ICPLB Data registers differ */
+/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
+#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
-#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
+/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
-#define ANOMALY_05000262 /* Stores to data cache may be lost */
+#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
-#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
+/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
+#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
-                            instruction will cause an infinite stall in the
+/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-                            second to last instruction in a hardware loop */
+#define ANOMALY_05000208 (1)
-#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
+/* Speed Path in Computational Unit Affects Certain Instructions */
-                            SPORT external receive and transmit clocks. */
+#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
-#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
+/* UART TX Interrupt Masked Erroneously */
-                            internal voltage regulator (VDDint) to increase. */
+#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
+/* NMI Event at Boot Time Results in Unpredictable State */
-                            internal voltage regulator (VDDint) to decrease */
+#define ANOMALY_05000219 (1)
-#endif /* issues only occur on 0.3 or 0.4 BF533 */
+/* Incorrect Pulse-Width of UART Start Bit */
+#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
+/* Scratchpad Memory Bank Reads May Return Incorrect Data */
+#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
+/* SPI Slave Boot Mode Modifies Registers from Reset Value */
+#define ANOMALY_05000229 (1)
+/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
+#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
+/* UART STB Bit Incorrectly Affects Receiver Setting */
+#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
+/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
+#define ANOMALY_05000233 (__SILICON_REVISION__ < 4)
+/* Incorrect Revision Number in DSPID Register */
+#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
+/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
+#define ANOMALY_05000242 (__SILICON_REVISION__ < 4)
+/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
+#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
+/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* Data CPLBs Should Prevent Spurious Hardware Errors */
+#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
+/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
+#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
+/* Maximum External Clock Speed for Timers */
+#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
+#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
+/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
+#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
+/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
+#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
+/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
+#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
+/* ICPLB_STATUS MMR Register May Be Corrupted */
+#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
+/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
+#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
+/* Stores To Data Cache May Be Lost */
+#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
+/* Hardware Loop Corrupted When Taking an ICPLB Exception */
+#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
+/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
+#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
+#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
+#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
+/* Spontaneous Reset of Internal Voltage Regulator */
+#define ANOMALY_05000271 (__SILICON_REVISION__ < 4)
+/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
+#define ANOMALY_05000272 (1)
+/* Writes to Synchronous SDRAM Memory May Be Lost */
+#define ANOMALY_05000273 (1)
+/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
+#define ANOMALY_05000276 (1)
+/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
+#define ANOMALY_05000277 (1)
+/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
+#define ANOMALY_05000278 (1)
+/* False Hardware Error Exception When ISR Context Is Not Restored */
+#define ANOMALY_05000281 (1)
+/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
+#define ANOMALY_05000282 (1)
+/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
+#define ANOMALY_05000283 (1)
+/* SPORTs May Receive Bad Data If FIFOs Fill Up */
+#define ANOMALY_05000288 (1)
+/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
+#define ANOMALY_05000301 (1)
+/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
+#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
+/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
+#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
+/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
+#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
+#define ANOMALY_05000311 (1)
+/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (1)
+/* PPI Is Level-Sensitive on First Transfer */
+#define ANOMALY_05000313 (1)
+/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
+#define ANOMALY_05000315 (1)
+/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
+#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
-/* These issues are only on 0.4 silicon */
+/* These anomalies have been "phased" out of analog.com anomaly sheets and are
-#if (defined(CONFIG_BF_REV_0_4))
+ * here to show running on older silicon just isn't feasible.
-#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
+ */
-#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
-                            (TDM) */
-#endif /* issues are only on 0.4 silicon */
-/* These issues are only on 0.3 silicon */
+/* Watchpoints (Hardware Breakpoints) are not supported */
-#if defined(CONFIG_BF_REV_0_3)
+#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
-#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
+/* Reserved bits in SYSCFG register not set at power on */
-                            External Frame Syncs */
+#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
-#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
+/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
-                            Instruction or Data Fetches, or by Fetches at the
+#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-                            boundary of reserved memory space */
+/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */
-#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
+#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
-                            when polarity setting is changed */
+/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
+#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
-                            corruption */
+/* Erroneous exception when enabling cache */
-#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
+#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-                            fix */
+/* SPI clock polarity and phase bits incorrect during booting */
-#define ANOMALY_05000201 /* Receive frame sync not ignored during active
+#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
-                            frames in sport MCM */
+/* DMEM_CONTROL is not set on Reset */
-#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
+#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
-                            stopping */
+/* SPI boot will not complete if there is a zero fill block in the loader file */
-#if defined(CONFIG_BF533)
+#define ANOMALY_05000138 (__SILICON_REVISION__ < 3)
-#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
+/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-                            allocate cache lines on reads only mode */
+#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-#endif /* CONFIG_BF533 */
+/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
+#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
+/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-                            instructions */
+#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
+/* A read from external memory may return a wrong value with data cache enabled */
-                            Sync Transmit Mode */
+#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
-#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
+/* DMA and TESTSET conflict when both are accessing external memory */
-#endif /* only on 0.3 silicon */
+#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
+/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
+#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
+/* MDMA may lose the first few words of a descriptor chain */
+#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
+/* The source MDMA descriptor may stop with a DMA Error */
+#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
+/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */
+#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
+/* Frame Delay in SPORT Multichannel Mode */
+#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
+/* SPORT TFS signal is active in Multi-channel mode outside of valid channels */
+#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
+/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
+#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
+/* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
+/* SPORT transmit data is not gated by external frame sync in certain conditions */
+#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
+/* SDRAM auto-refresh and subsequent Power Ups */
+#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
+/* DATA CPLB page miss can result in lost write-through cache data writes */
+#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
+/* DMA vs Core accesses to external memory */
+#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
+/* Cache Fill Buffer Data lost */
+#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
+/* Overlapping Sequencer and Memory Stalls */
+#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
+/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
+#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
+/* Disabling the PPI resets the PPI configuration registers */
+#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
+/* PPI TX Mode with 2 External Frame Syncs */
+#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
+/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
+#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
+/* In PPI Transmit Modes with External Frame Syncs POLC */
+#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
+/* Internal Voltage Regulator may not start up */
+#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
-#if defined(CONFIG_BF_REV_0_2)
+/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000067 /* Watchpoints (Hardware Breakpoints) are not
+#define ANOMALY_05000266 (0)
-                          *  supported */
+#define ANOMALY_05000323 (0)
-#define ANOMALY_05000109 /* Reserved bits in SYSCFG register not set at
-                          *  power on */
-#define ANOMALY_05000116 /* Trace Buffers may record discontinuities into
-                          *  emulation mode and/or exception, NMI, reset
-                          *  handlers */
-#define ANOMALY_05000123 /* DTEST_COMMAND initiated memory access may be
-                          *  incorrect if data cache or DMA is active */
-#define ANOMALY_05000124 /* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1,
-                          *  or 1:1 */
-#define ANOMALY_05000125 /* Erroneous exception when enabling cache */
-#define ANOMALY_05000126 /* SPI clock polarity and phase bits incorrect
-                          *  during booting */
-#define ANOMALY_05000137 /* DMEM_CONTROL is not set on Reset */
-#define ANOMALY_05000138 /* SPI boot will not complete if there is a zero fill
-                          * block in the loader file */
-#define ANOMALY_05000140 /* Allowing the SPORT RX FIFO to fill will cause an
-                          *  overflow */
-#define ANOMALY_05000141 /* An Infinite Stall occurs with a particular sequence
-                          *  of consecutive dual dag events */
-#define ANOMALY_05000142 /* Interrupts may be lost when a programmable input
-                          *  flag is configured to be edge sensitive */
-#define ANOMALY_05000143 /* A read from external memory may return a wrong
-                          *  value with data cache enabled */
-#define ANOMALY_05000144 /* DMA and TESTSET conflict when both are accessing
-                          *  external memory */
-#define ANOMALY_05000145 /* In PWM_OUT mode, you must enable the PPI block to
-                          *  generate a waveform from PPI_CLK */
-#define ANOMALY_05000146 /* MDMA may lose the first few words of a descriptor
-                          *  chain */
-#define ANOMALY_05000147 /* The source MDMA descriptor may stop with a DMA
-                          *  Error */
-#define ANOMALY_05000148 /* When booting from a 16-bit asynchronous memory
-                          *  device, the upper 8-bits of each word must be
-                          *  0x00 */
-#define ANOMALY_05000153 /* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000154 /* SPORT TFS signal is active in Multi-channel mode
-                          *  outside of valid channels */
-#define ANOMALY_05000155 /* Timer1 can not be used for PWMOUT mode when a
-                          *  certain PPI mode is in use */
-#define ANOMALY_05000157 /* A killed 32-bit System MMR write will lead to
-                          *  the next system MMR access thinking it should be
-                          *  32-bit. */
-#define ANOMALY_05000163 /* SPORT transmit data is not gated by external frame
-                          *  sync in certain conditions */
-#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
-#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost
-                          *  write-through cache data writes */
-#define ANOMALY_05000173 /* DMA vs Core accesses to external memory */
-#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
-#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
-                          *  accumulator saturation */
-#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
-                          *  registers */
-#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000191 /* PPI does not invert the Driving PPICLK edge in
-                          *  Transmit Modes */
-#define ANOMALY_05000192 /* In PPI Transmit Modes with External Frame Syncs
-                          *  POLC */
-#define ANOMALY_05000206 /* Internal Voltage Regulator may not start up */
 #endif
-#endif /*  _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf533/bf533.h b/include/asm-blackfin/mach-bf533/bf533.h
index 185fc1284858..12a416931991 100644
--- a/include/asm-blackfin/mach-bf533/bf533.h
+++ b/include/asm-blackfin/mach-bf533/bf533.h
@@ -52,12 +52,12 @@
 /***************************/
-#define BLKFIN_DSUBBANKS        4
+#define BFIN_DSUBBANKS  4
-#define BLKFIN_DWAYS            2
+#define BFIN_DWAYS              2
-#define BLKFIN_DLINES           64
+#define BFIN_DLINES             64
-#define BLKFIN_ISUBBANKS        4
+#define BFIN_ISUBBANKS  4
-#define BLKFIN_IWAYS            4
+#define BFIN_IWAYS              4
-#define BLKFIN_ILINES           32
+#define BFIN_ILINES             32
 #define WAY0_L                  0x1
 #define WAY1_L                  0x2
@@ -141,97 +141,6 @@
 #define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
-#define MAX_VC  650000000
-#define MIN_VC  50000000
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-/********************************PLL Settings **************************************/
-#if (CONFIG_VCO_MULT < 0)
-#error "VCO Multiplier is less than 0. Please select a different value"
-#endif
-#if (CONFIG_VCO_MULT == 0)
-#error "VCO Multiplier should be greater than 0. Please select a different value"
-#endif
-#if (CONFIG_VCO_MULT > 64)
-#error "VCO Multiplier is more than 64. Please select a different value"
-#endif
-#ifndef CONFIG_CLKIN_HALF
-#define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
-#else
-#define CONFIG_VCO_HZ   ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
-#endif
-#ifndef CONFIG_PLL_BYPASS
-#define CONFIG_CCLK_HZ  (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
-#define CONFIG_SCLK_HZ  (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
-#else
-#define CONFIG_CCLK_HZ  CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ  CONFIG_CLKIN_HZ
-#endif
-#if (CONFIG_SCLK_DIV < 1)
-#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
-#endif
-#if (CONFIG_SCLK_DIV > 15)
-#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
-#endif
-#if (CONFIG_CCLK_DIV != 1)
-#if (CONFIG_CCLK_DIV != 2)
-#if (CONFIG_CCLK_DIV != 4)
-#if (CONFIG_CCLK_DIV != 8)
-#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
-#endif
-#endif
-#endif
-#endif
-#if (CONFIG_VCO_HZ > MAX_VC)
-#error "VCO selected is more than maximum value. Please change the VCO multipler"
-#endif
-#if (CONFIG_SCLK_HZ > 133000000)
-#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
-#endif
-#if (CONFIG_SCLK_HZ < 27000000)
-#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
-#endif
-#if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ)
-#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
-#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
-#error "Please select sclk less than cclk"
-#endif
-#endif
-#endif
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
-#endif
-#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
-#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
-#endif
-#endif                          /* CONFIG_BFIN_KERNEL_CLOCK */
 #ifdef CONFIG_BF533
 #define CPU "BF533"
 #define CPUID 0x027a5000
@@ -249,58 +158,4 @@
 #define CPUID 0x0
 #endif
-#if (CONFIG_MEM_SIZE % 4)
-#error "SDRAM mem size must be multible of 4MB"
-#endif
-#define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
-#define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
-#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
-/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
-#define ANOMALY_05000158_WORKAROUND             0x200
-#ifdef CONFIG_BLKFIN_WB         /*Write Back Policy */
-#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_DIRTY \
-                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#else                           /*Write Through */
-#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_DIRTY \
-                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#endif
-#define L1_DMEMORY       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
-#define SDRAM_DNON_CHBL  (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
-#define SDRAM_EBIU       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
-#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
-#define SIZE_1K 0x00000400      /* 1K */
-#define SIZE_4K 0x00001000      /* 4K */
-#define SIZE_1M 0x00100000      /* 1M */
-#define SIZE_4M 0x00400000      /* 4M */
-#define MAX_CPLBS (16 * 2)
-/*
-* Number of required data CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 16 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Data Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-* 1 for ASYNC Memory
-*/
-#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
-/*
-* Number of required instruction CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 12 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Instruction Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-*/
-#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
 #endif                          /* __MACH_BF533_H__  */
diff --git a/include/asm-blackfin/mach-bf533/blackfin.h b/include/asm-blackfin/mach-bf533/blackfin.h
index e4384491e972..f3b240abf170 100644
--- a/include/asm-blackfin/mach-bf533/blackfin.h
+++ b/include/asm-blackfin/mach-bf533/blackfin.h
@@ -38,7 +38,7 @@
 #include "defBF532.h"
 #include "anomaly.h"
-#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
+#if !defined(__ASSEMBLY__)
 #include "cdefBF532.h"
 #endif
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h
index 74f967b235e2..c803e14b529c 100644
--- a/include/asm-blackfin/mach-bf533/cdefBF532.h
+++ b/include/asm-blackfin/mach-bf533/cdefBF532.h
@@ -30,11 +30,9 @@
 #ifndef _CDEF_BF532_H
 #define _CDEF_BF532_H
-/*
-#if !defined(__ADSPLPBLACKFIN__)
+#include <asm/blackfin.h>
-#warning cdefBF532.h should only be included for 532 compatible chips.
-#endif
-*/
 /*include all Core registers and bit definitions*/
 #include "defBF532.h"
@@ -65,7 +63,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
        bfin_write32(SIC_IWR, IWR_ENABLE(0));
        bfin_write16(VR_CTL, val);
-        __builtin_bfin_ssync();
+        SSYNC();
        local_irq_save(flags);
        asm("IDLE;");
@@ -132,10 +130,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
 #define bfin_read_FIO_DIR()                  bfin_read16(FIO_DIR)
 #define bfin_write_FIO_DIR(val)              bfin_write16(FIO_DIR,val)
-#define bfin_read_FIO_FLAG_C()               bfin_read16(FIO_FLAG_C)
-#define bfin_write_FIO_FLAG_C(val)           bfin_write16(FIO_FLAG_C,val)
-#define bfin_read_FIO_FLAG_S()               bfin_read16(FIO_FLAG_S)
-#define bfin_write_FIO_FLAG_S(val)           bfin_write16(FIO_FLAG_S,val)
 #define bfin_read_FIO_MASKA_C()              bfin_read16(FIO_MASKA_C)
 #define bfin_write_FIO_MASKA_C(val)          bfin_write16(FIO_MASKA_C,val)
 #define bfin_read_FIO_MASKA_S()              bfin_read16(FIO_MASKA_S)
@@ -152,10 +146,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_write_FIO_BOTH(val)             bfin_write16(FIO_BOTH,val)
 #define bfin_read_FIO_INEN()                 bfin_read16(FIO_INEN)
 #define bfin_write_FIO_INEN(val)             bfin_write16(FIO_INEN,val)
-#define bfin_read_FIO_FLAG_D()               bfin_read16(FIO_FLAG_D)
-#define bfin_write_FIO_FLAG_D(val)           bfin_write16(FIO_FLAG_D,val)
-#define bfin_read_FIO_FLAG_T()               bfin_read16(FIO_FLAG_T)
-#define bfin_write_FIO_FLAG_T(val)           bfin_write16(FIO_FLAG_T,val)
 #define bfin_read_FIO_MASKA_D()              bfin_read16(FIO_MASKA_D)
 #define bfin_write_FIO_MASKA_D(val)          bfin_write16(FIO_MASKA_D,val)
 #define bfin_read_FIO_MASKA_T()              bfin_read16(FIO_MASKA_T)
@@ -165,6 +155,50 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
 #define bfin_read_FIO_MASKB_T()              bfin_read16(FIO_MASKB_T)
 #define bfin_write_FIO_MASKB_T(val)          bfin_write16(FIO_MASKB_T,val)
+#if ANOMALY_05000311
+#define BFIN_WRITE_FIO_FLAG(name) \
+static __inline__ void bfin_write_FIO_FLAG_ ## name (unsigned short val)\
+{\
+        unsigned long flags;\
+        local_irq_save(flags);\
+        bfin_write16(FIO_FLAG_ ## name,val);\
+        bfin_read_CHIPID();\
+        local_irq_restore(flags);\
+}
+BFIN_WRITE_FIO_FLAG(D)
+BFIN_WRITE_FIO_FLAG(C)
+BFIN_WRITE_FIO_FLAG(S)
+BFIN_WRITE_FIO_FLAG(T)
+#define BFIN_READ_FIO_FLAG(name) \
+static __inline__ unsigned short bfin_read_FIO_FLAG_ ## name (void)\
+{\
+        unsigned long flags;\
+        unsigned short ret;\
+        local_irq_save(flags);\
+        ret = bfin_read16(FIO_FLAG_ ## name);\
+        bfin_read_CHIPID();\
+        local_irq_restore(flags);\
+        return ret;\
+}
+BFIN_READ_FIO_FLAG(D)
+BFIN_READ_FIO_FLAG(C)
+BFIN_READ_FIO_FLAG(S)
+BFIN_READ_FIO_FLAG(T)
+#else
+#define bfin_write_FIO_FLAG_D(val)           bfin_write16(FIO_FLAG_D,val)
+#define bfin_write_FIO_FLAG_C(val)           bfin_write16(FIO_FLAG_C,val)
+#define bfin_write_FIO_FLAG_S(val)           bfin_write16(FIO_FLAG_S,val)
+#define bfin_write_FIO_FLAG_T(val)           bfin_write16(FIO_FLAG_T,val)
+#define bfin_read_FIO_FLAG_T()               bfin_read16(FIO_FLAG_T)
+#define bfin_read_FIO_FLAG_C()               bfin_read16(FIO_FLAG_C)
+#define bfin_read_FIO_FLAG_S()               bfin_read16(FIO_FLAG_S)
+#define bfin_read_FIO_FLAG_D()               bfin_read16(FIO_FLAG_D)
+#endif
 /* DMA Controller */
 #define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 6a3cf93f8b57..37134aaf9954 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -104,6 +104,7 @@
 #define UART_GCTL                        0xFFC00424     /* Global Control Register */
 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI0_REGBASE                    0xFFC00500
 #define SPI_CTL                         0xFFC00500      /* SPI Control Register */
 #define SPI_FLG                         0xFFC00504      /* SPI Flag register */
 #define SPI_STAT                        0xFFC00508      /* SPI Status register */
@@ -928,7 +929,7 @@
 #define GM                     0x00000008       /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
 #define PSSE                   0x00000010       /* Enable (=1) Slave-Select input for Master. */
 #define EMISO                  0x00000020       /* Enable (=1) MISO pin as an output. */
-#define SPI_LEN                0x00000100       /* Word length (0 => 8 bits, 1 => 16 bits) */
+#define SIZE                   0x00000100       /* Word length (0 => 8 bits, 1 => 16 bits) */
 #define LSBF                   0x00000200       /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
 #define CPHA                   0x00000400       /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
 #define CPOL                   0x00000800       /* Clock polarity (0 => active-high, 1 => active-low) */
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
index 9879e68e315c..452fb825d891 100644
--- a/include/asm-blackfin/mach-bf533/irq.h
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -128,6 +128,8 @@ Core        Emulation               **
 #define IRQ_PF14                47
 #define IRQ_PF15                48
+#define GPIO_IRQ_BASE           IRQ_PF0
 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS         (IRQ_PF15+1)
 #else
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
index e84baa3e939d..94d8c4062eb7 100644
--- a/include/asm-blackfin/mach-bf533/mem_map.h
+++ b/include/asm-blackfin/mach-bf533/mem_map.h
@@ -51,10 +51,10 @@
 /* Level 1 Memory */
-#ifdef CONFIG_BLKFIN_CACHE
+#ifdef CONFIG_BFIN_ICACHE
-#define BLKFIN_ICACHESIZE       (16*1024)
+#define BFIN_ICACHESIZE (16*1024)
 #else
-#define BLKFIN_ICACHESIZE       (0*1024)
+#define BFIN_ICACHESIZE (0*1024)
 #endif
 /* Memory Map for ADSP-BF533 processors */
@@ -64,35 +64,35 @@
 #define L1_DATA_A_START     0xFF800000
 #define L1_DATA_B_START     0xFF900000
-#ifdef CONFIG_BLKFIN_CACHE
+#ifdef CONFIG_BFIN_ICACHE
 #define L1_CODE_LENGTH      (0x14000 - 0x4000)
 #else
 #define L1_CODE_LENGTH      0x14000
 #endif
-#ifdef CONFIG_BLKFIN_DCACHE
+#ifdef CONFIG_BFIN_DCACHE
-#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#ifdef CONFIG_BFIN_DCACHE_BANKA
 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 #define L1_DATA_B_LENGTH      0x8000
-#define BLKFIN_DCACHESIZE       (16*1024)
+#define BFIN_DCACHESIZE (16*1024)
-#define BLKFIN_DSUPBANKS        1
+#define BFIN_DSUPBANKS  1
 #else
 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BLKFIN_DCACHESIZE       (32*1024)
+#define BFIN_DCACHESIZE (32*1024)
-#define BLKFIN_DSUPBANKS        2
+#define BFIN_DSUPBANKS  2
 #endif
 #else
 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      0x8000
 #define L1_DATA_B_LENGTH      0x8000
-#define BLKFIN_DCACHESIZE       (0*1024)
+#define BFIN_DCACHESIZE (0*1024)
-#define BLKFIN_DSUPBANKS        0
+#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BLKFIN_DCACHE*/
+#endif /*CONFIG_BFIN_DCACHE*/
 #endif
 /* Memory Map for ADSP-BF532 processors */
@@ -102,36 +102,36 @@
 #define L1_DATA_A_START     0xFF804000
 #define L1_DATA_B_START     0xFF904000
-#ifdef CONFIG_BLKFIN_CACHE
+#ifdef CONFIG_BFIN_ICACHE
 #define L1_CODE_LENGTH      (0xC000 - 0x4000)
 #else
 #define L1_CODE_LENGTH      0xC000
 #endif
-#ifdef CONFIG_BLKFIN_DCACHE
+#ifdef CONFIG_BFIN_DCACHE
-#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#ifdef CONFIG_BFIN_DCACHE_BANKA
 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
 #define L1_DATA_B_LENGTH      0x4000
-#define BLKFIN_DCACHESIZE       (16*1024)
+#define BFIN_DCACHESIZE (16*1024)
-#define BLKFIN_DSUPBANKS        1
+#define BFIN_DSUPBANKS  1
 #else
 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
 #define L1_DATA_B_LENGTH      (0x4000 - 0x4000)
-#define BLKFIN_DCACHESIZE       (32*1024)
+#define BFIN_DCACHESIZE (32*1024)
-#define BLKFIN_DSUPBANKS        2
+#define BFIN_DSUPBANKS  2
 #endif
 #else
 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      0x4000
 #define L1_DATA_B_LENGTH      0x4000
-#define BLKFIN_DCACHESIZE       (0*1024)
+#define BFIN_DCACHESIZE (0*1024)
-#define BLKFIN_DSUPBANKS        0
+#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BLKFIN_DCACHE*/
+#endif /*CONFIG_BFIN_DCACHE*/
 #endif
 /* Memory Map for ADSP-BF531 processors */
@@ -144,16 +144,16 @@
 #define L1_DATA_B_LENGTH      0x0000
-#ifdef CONFIG_BLKFIN_DCACHE
+#ifdef CONFIG_BFIN_DCACHE
 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB  | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
-#define BLKFIN_DCACHESIZE       (16*1024)
+#define BFIN_DCACHESIZE (16*1024)
-#define BLKFIN_DSUPBANKS        1
+#define BFIN_DSUPBANKS  1
 #else
 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB  | PORT_PREF0)
 #define L1_DATA_A_LENGTH      0x4000
-#define BLKFIN_DCACHESIZE       (0*1024)
+#define BFIN_DCACHESIZE (0*1024)
-#define BLKFIN_DSUPBANKS        0
+#define BFIN_DSUPBANKS  0
 #endif
 #endif
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 4453e614c3b1..2b66ecf489f7 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -1,139 +1,144 @@
 /*
- * File:         include/asm-blackfin/mach-bf537/anomaly.h
+ * File: include/asm-blackfin/mach-bf537/anomaly.h
- * Based on:
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
 *
- * This program is distributed in the hope that it will be useful,
+ * Copyright (C) 2004-2007 Analog Devices Inc.
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * Licensed under the GPL-2 or later.
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */
 /* This file shoule be up to date with:
- *  - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List
+ *  - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List
- *  - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List
+ *  - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List
- *  - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List
+ *  - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List
 */
 #ifndef _MACH_ANOMALY_H_
 #define _MACH_ANOMALY_H_
 /* We do not support 0.1 silicon - sorry */
-#if (defined(CONFIG_BF_REV_0_1))
+#if __SILICON_REVISION__ < 2
-#error Kernel will not work on BF537/6/4 Version 0.1
+# error Kernel will not work on BF537 silicon version 0.0 or 0.1
 #endif
-#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2))
+#if defined(__ADSPBF534__)
-#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
+# define ANOMALY_BF534 1
-                            slot1 and store of a P register in slot 2 is not
+#else
-                            supported */
+# define ANOMALY_BF534 0
-#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
-                            Channel DMA stops */
-#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
-                            registers. */
-#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
-                            upper bits*/
-#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
-                            syncs */
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
-#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
-                            Changed */
-#endif
-#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
-                            SPORT external receive and transmit clocks. */
-#define ANOMALY_05000272 /* Certain data cache write through modes fail for
-                            VDDint <=0.9V */
-#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
-#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
-                            an edge is detected may clear interrupt */
-#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
-                            not restored */
-#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
-                            control */
-#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
-                            killed in a particular stage*/
-#define ANOMALY_05000310 /* False hardware errors caused by fetches at the
-                          *  boundary of reserved memory */
-#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
-                            registers are interrupted */
-#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */
-#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not
-                          *  received properly */
 #endif
+#if defined(__ADSPBF536__)
-#if defined(CONFIG_BF_REV_0_2)
+# define ANOMALY_BF536 1
-#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
+#else
-                            IDLE around a Change of Control causes
+# define ANOMALY_BF536 0
-                            unpredictable results */
-#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
-                            (TDM) */
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
-#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
 #endif
-#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
+#if defined(__ADSPBF537__)
-#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
+# define ANOMALY_BF537 1
-                            interrupt not functional */
+#else
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+# define ANOMALY_BF537 0
-#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
 #endif
-#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
-                            loops may cause the instruction fetch unit to
-                            malfunction */
-#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
-                            the ICPLB Data registers differ */
-#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
-#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
-#define ANOMALY_05000262 /* Stores to data cache may be lost */
-#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
-#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
-                            instruction will cause an infinite stall in the
-                            second to last instruction in a hardware loop */
-#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
-                            and non-zero DEB_TRAFFIC_PERIOD value */
-#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
-                            internal voltage regulator (VDDint) to decrease */
-#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
-                            an edge is detected may clear interrupt */
-#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
-                            DMA system instability */
-#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
-                            Atmel Dataflash devices */
-#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context
-                          *  is not restored */
-#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
-                          *  control */
-#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When
-                          *  Killed in a Particular Stage */
-#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment
-                          *  (Not Available On Older Silicon) */
-#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
-#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously
-                          *  On Next System MMR Access */
-#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex
-                          *  mode */
-#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with
-                          *  status No Carrier */
-#endif  /* CONFIG_BF_REV_0_2 */
-#endif /* _MACH_ANOMALY_H_ */
+/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
+#define ANOMALY_05000074 (1)
+/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */
+#define ANOMALY_05000119 (1)
+/* Rx.H cannot be used to access 16-bit System MMR registers */
+#define ANOMALY_05000122 (1)
+/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
+/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
+#define ANOMALY_05000180 (1)
+/* Instruction Cache Is Not Functional */
+#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
+/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
+#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
+/* Spurious Hardware Error from an access in the shadow of a conditional branch */
+#define ANOMALY_05000245 (1)
+/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
+#define ANOMALY_05000247 (1)
+/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */
+#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
+/* EMAC Tx DMA error after an early frame abort */
+#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
+/* Maximum external clock speed for Timers */
+#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */
+#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
+/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */
+#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
+/* EMAC MDIO input latched on wrong MDC edge */
+#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
+/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */
+#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
+/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */
+#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
+/* ICPLB_STATUS MMR register may be corrupted */
+#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
+/* DCPLB_FAULT_ADDR MMR register may be corrupted */
+#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
+/* Stores to data cache may be lost */
+#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
+/* Hardware loop corrupted when taking an ICPLB exception */
+#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
+/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */
+#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
+/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */
+#define ANOMALY_05000265 (1)
+/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
+#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
+/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */
+#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
+/* Certain data cache write through modes fail for VDDint <=0.9V */
+#define ANOMALY_05000272 (1)
+/* Writes to Synchronous SDRAM memory may be lost */
+#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
+/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
+/* Disabling Peripherals with DMA running may cause DMA system instability */
+#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
+/* SPI Master boot mode does not work well with Atmel Data flash devices */
+#define ANOMALY_05000280 (1)
+/* False Hardware Error Exception when ISR context is not restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
+/* Memory DMA corruption with 32-bit data and traffic control */
+#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
+/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
+#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
+/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
+#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
+/* SPORTs may receive bad data if FIFOs fill up */
+#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
+/* Memory to memory DMA source/destination descriptors must be in same memory space */
+#define ANOMALY_05000301 (1)
+/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
+#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
+/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
+#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
+/* SCKELOW Bit Does Not Maintain State Through Hibernate */
+#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
+/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
+#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
+/* False hardware errors caused by fetches at the boundary of reserved memory */
+#define ANOMALY_05000310 (1)
+/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */
+#define ANOMALY_05000312 (1)
+/* PPI is level sensitive on first transfer */
+#define ANOMALY_05000313 (1)
+/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
+#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
+/* EMAC RMII mode: collisions occur in Full Duplex mode */
+#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
+/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
+#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
+/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
+#define ANOMALY_05000322 (1)
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000125 (0)
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000266 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000323 (0)
+#endif
diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h
index b8924cd7730c..cfe2a221112e 100644
--- a/include/asm-blackfin/mach-bf537/bf537.h
+++ b/include/asm-blackfin/mach-bf537/bf537.h
@@ -62,12 +62,12 @@
 /***************************/
-#define BLKFIN_DSUBBANKS        4
+#define BFIN_DSUBBANKS  4
-#define BLKFIN_DWAYS            2
+#define BFIN_DWAYS              2
-#define BLKFIN_DLINES           64
+#define BFIN_DLINES             64
-#define BLKFIN_ISUBBANKS        4
+#define BFIN_ISUBBANKS  4
-#define BLKFIN_IWAYS            4
+#define BFIN_IWAYS              4
-#define BLKFIN_ILINES           32
+#define BFIN_ILINES             32
 #define WAY0_L                  0x1
 #define WAY1_L                  0x2
@@ -121,97 +121,6 @@
 #define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
-#define MAX_VC  650000000
-#define MIN_VC  50000000
-/********************************PLL Settings **************************************/
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-#if (CONFIG_VCO_MULT < 0)
-#error "VCO Multiplier is less than 0. Please select a different value"
-#endif
-#if (CONFIG_VCO_MULT == 0)
-#error "VCO Multiplier should be greater than 0. Please select a different value"
-#endif
-#if (CONFIG_VCO_MULT > 64)
-#error "VCO Multiplier is more than 64. Please select a different value"
-#endif
-#ifndef CONFIG_CLKIN_HALF
-#define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
-#else
-#define CONFIG_VCO_HZ   ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
-#endif
-#ifndef CONFIG_PLL_BYPASS
-#define CONFIG_CCLK_HZ  (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
-#define CONFIG_SCLK_HZ  (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
-#else
-#define CONFIG_CCLK_HZ  CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ  CONFIG_CLKIN_HZ
-#endif
-#if (CONFIG_SCLK_DIV < 1)
-#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
-#endif
-#if (CONFIG_SCLK_DIV > 15)
-#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
-#endif
-#if (CONFIG_CCLK_DIV != 1)
-#if (CONFIG_CCLK_DIV != 2)
-#if (CONFIG_CCLK_DIV != 4)
-#if (CONFIG_CCLK_DIV != 8)
-#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
-#endif
-#endif
-#endif
-#endif
-#if (CONFIG_VCO_HZ > MAX_VC)
-#error "VCO selected is more than maximum value. Please change the VCO multipler"
-#endif
-#if (CONFIG_SCLK_HZ > 133000000)
-#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
-#endif
-#if (CONFIG_SCLK_HZ < 27000000)
-#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
-#endif
-#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
-#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
-#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
-#error "Please select sclk less than cclk"
-#endif
-#endif
-#endif
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
-#endif
-#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
-#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
-#endif
-#endif                          /* CONFIG_BFIN_KERNEL_CLOCK */
 #ifdef CONFIG_BF537
 #define CPU "BF537"
 #define CPUID 0x027c8000
@@ -229,59 +138,4 @@
 #define CPUID 0x0
 #endif
-#if (CONFIG_MEM_SIZE % 4)
-#error "SDRAM mem size must be multible of 4MB"
-#endif
-#define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
-#define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
-#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
-/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
-#define ANOMALY_05000158_WORKAROUND             0x200
-#ifdef CONFIG_BLKFIN_WB         /*Write Back Policy */
-#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_DIRTY \
-                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#else                           /*Write Through */
-#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
-                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
-#endif
-#define L1_DMEMORY       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
-#define SDRAM_DNON_CHBL  (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
-#define SDRAM_EBIU       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
-#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
-#define SIZE_1K 0x00000400      /* 1K */
-#define SIZE_4K 0x00001000      /* 4K */
-#define SIZE_1M 0x00100000      /* 1M */
-#define SIZE_4M 0x00400000      /* 4M */
-#define MAX_CPLBS (16 * 2)
-/*
-* Number of required data CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 16 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Data Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-* 1 for ASYNC Memory
-*/
-#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
-/*
-* Number of required instruction CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 12 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Instruction Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-*/
-#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
 #endif                          /* __MACH_BF537_H__  */
diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h
index bbd97051ec9c..53fcfa3408d0 100644
--- a/include/asm-blackfin/mach-bf537/blackfin.h
+++ b/include/asm-blackfin/mach-bf537/blackfin.h
@@ -43,7 +43,7 @@
 #include "defBF537.h"
 #endif
-#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
+#if !defined(__ASSEMBLY__)
 #include "cdefBF534.h"
 /* UART 0*/
@@ -143,284 +143,6 @@
 #define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
 #define STOPCK_OFF STOPCK
-/* FIO USE PORT F*/
-#ifdef CONFIG_BF537_PORT_F
-#define bfin_read_PORT_FER() bfin_read_PORTF_FER()
-#define bfin_write_PORT_FER(val) bfin_write_PORTF_FER(val)
-#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO()
-#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val)
-#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR()
-#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val)
-#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET()
-#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val)
-#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE()
-#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val)
-#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA()
-#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val)
-#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR()
-#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val)
-#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET()
-#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val)
-#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE()
-#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val)
-#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB()
-#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val)
-#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR()
-#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val)
-#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET()
-#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val)
-#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE()
-#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val)
-#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR()
-#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val)
-#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR()
-#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val)
-#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE()
-#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val)
-#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH()
-#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val)
-#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN()
-#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val)
-#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO()
-#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val)
-#define FIO_FLAG_D              PORTFIO
-#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR()
-#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val)
-#define FIO_FLAG_C              PORTFIO_CLEAR
-#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET()
-#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val)
-#define FIO_FLAG_S              PORTFIO_SET
-#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE()
-#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val)
-#define FIO_FLAG_T              PORTFIO_TOGGLE
-#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA()
-#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val)
-#define FIO_MASKA_D         PORTFIO_MASKA
-#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR()
-#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val)
-#define FIO_MASKA_C     PORTFIO_MASKA_CLEAR
-#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET()
-#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val)
-#define FIO_MASKA_S     PORTFIO_MASKA_SET
-#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE()
-#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val)
-#define FIO_MASKA_T     PORTFIO_MASKA_TOGGLE
-#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB()
-#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val)
-#define FIO_MASKB_D     PORTFIO_MASKB
-#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR()
-#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val)
-#define FIO_MASKB_C     PORTFIO_MASKB_CLEAR
-#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET()
-#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val)
-#define FIO_MASKB_S     PORTFIO_MASKB_SET
-#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE()
-#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val)
-#define FIO_MASKB_T     PORTFIO_MASKB_TOGGLE
-#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR()
-#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val)
-#define FIO_DIR             PORTFIO_DIR
-#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR()
-#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val)
-#define FIO_POLAR               PORTFIO_POLAR
-#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE()
-#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val)
-#define FIO_EDGE                PORTFIO_EDGE
-#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH()
-#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val)
-#define FIO_BOTH                PORTFIO_BOTH
-#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN()
-#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val)
-#define FIO_INEN                PORTFIO_INEN
-#endif
-/* FIO USE PORT G*/
-#ifdef CONFIG_BF537_PORT_G
-#define bfin_read_PORT_FER() bfin_read_PORTG_FER()
-#define bfin_write_PORT_FER(val) bfin_write_PORTG_FER(val)
-#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO()
-#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val)
-#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR()
-#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val)
-#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET()
-#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val)
-#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE()
-#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val)
-#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA()
-#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val)
-#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR()
-#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val)
-#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET()
-#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val)
-#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE()
-#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val)
-#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB()
-#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val)
-#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR()
-#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val)
-#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET()
-#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val)
-#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE()
-#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val)
-#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR()
-#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val)
-#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR()
-#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val)
-#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE()
-#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val)
-#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH()
-#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val)
-#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN()
-#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val)
-#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO()
-#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val)
-#define FIO_FLAG_D              PORTGIO
-#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR()
-#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val)
-#define FIO_FLAG_C              PORTGIO_CLEAR
-#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET()
-#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val)
-#define FIO_FLAG_S              PORTGIO_SET
-#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE()
-#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val)
-#define FIO_FLAG_T              PORTGIO_TOGGLE
-#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA()
-#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val)
-#define FIO_MASKA_D         PORTGIO_MASKA
-#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR()
-#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val)
-#define FIO_MASKA_C         PORTGIO_MASKA_CLEAR
-#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET()
-#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val)
-#define FIO_MASKA_S         PORTGIO_MASKA_SET
-#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE()
-#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val)
-#define FIO_MASKA_T         PORTGIO_MASKA_TOGGLE
-#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB()
-#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val)
-#define FIO_MASKB_D         PORTGIO_MASKB
-#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR()
-#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val)
-#define FIO_MASKB_C         PORTGIO_MASKB_CLEAR
-#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET()
-#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val)
-#define FIO_MASKB_S         PORTGIO_MASKB_SET
-#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE()
-#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val)
-#define FIO_MASKB_T         PORTGIO_MASKB_TOGGLE
-#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR()
-#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val)
-#define FIO_DIR             PORTGIO_DIR
-#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR()
-#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val)
-#define FIO_POLAR               PORTGIO_POLAR
-#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE()
-#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val)
-#define FIO_EDGE                PORTGIO_EDGE
-#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH()
-#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val)
-#define FIO_BOTH                PORTGIO_BOTH
-#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN()
-#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val)
-#define FIO_INEN                PORTGIO_INEN
-#endif
-/* FIO USE PORT H*/
-#ifdef CONFIG_BF537_PORT_H
-#define bfin_read_PORT_FER() bfin_read_PORTH_FER()
-#define bfin_write_PORT_FER(val) bfin_write_PORTH_FER(val)
-#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO()
-#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val)
-#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR()
-#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val)
-#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET()
-#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val)
-#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE()
-#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val)
-#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA()
-#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val)
-#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR()
-#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val)
-#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET()
-#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val)
-#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE()
-#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val)
-#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB()
-#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val)
-#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR()
-#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val)
-#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET()
-#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val)
-#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE()
-#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val)
-#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR()
-#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val)
-#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR()
-#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val)
-#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE()
-#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val)
-#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH()
-#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val)
-#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN()
-#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val)
-#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO()
-#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val)
-#define FIO_FLAG_D              PORTHIO
-#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR()
-#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val)
-#define FIO_FLAG_C              PORTHIO_CLEAR
-#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET()
-#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val)
-#define FIO_FLAG_S              PORTHIO_SET
-#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE()
-#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val)
-#define FIO_FLAG_T              PORTHIO_TOGGLE
-#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA()
-#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val)
-#define FIO_MASKA_D         PORTHIO_MASKA
-#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR()
-#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val)
-#define FIO_MASKA_C         PORTHIO_MASKA_CLEAR
-#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET()
-#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val)
-#define FIO_MASKA_S         PORTHIO_MASKA_SET
-#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE()
-#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val)
-#define FIO_MASKA_T         PORTHIO_MASKA_TOGGLE
-#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB()
-#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val)
-#define FIO_MASKB_D         PORTHIO_MASKB
-#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR()
-#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val)
-#define FIO_MASKB_C         PORTHIO_MASKB_CLEAR
-#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET()
-#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val)
-#define FIO_MASKB_S         PORTHIO_MASKB_SET
-#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE()
-#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val)
-#define FIO_MASKB_T         PORTHIO_MASKB_TOGGLE
-#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR()
-#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val)
-#define FIO_DIR             PORTHIO_DIR
-#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR()
-#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val)
-#define FIO_POLAR               PORTHIO_POLAR
-#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE()
-#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val)
-#define FIO_EDGE                PORTHIO_EDGE
-#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH()
-#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val)
-#define FIO_BOTH                PORTHIO_BOTH
-#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN()
-#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val)
-#define FIO_INEN                PORTHIO_INEN
-#endif
 /* PLL_DIV Masks                                                                                                        */
 #define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
 #define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
index 84e58fa73dce..78227bc855df 100644
--- a/include/asm-blackfin/mach-bf537/cdefBF534.h
+++ b/include/asm-blackfin/mach-bf537/cdefBF534.h
@@ -32,6 +32,8 @@
 #ifndef _CDEF_BF534_H
 #define _CDEF_BF534_H
+#include <asm/blackfin.h>
 /* Include all Core registers and bit definitions                                                                       */
 #include "defBF534.h"
@@ -57,7 +59,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
        bfin_write32(SIC_IWR, IWR_ENABLE(0));
        bfin_write16(VR_CTL, val);
-        __builtin_bfin_ssync();
+        SSYNC();
        local_irq_save(flags);
        asm("IDLE;");
diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h
index 1859f2fee5a7..d0d80d3152ba 100644
--- a/include/asm-blackfin/mach-bf537/defBF534.h
+++ b/include/asm-blackfin/mach-bf537/defBF534.h
@@ -86,6 +86,7 @@
 #define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
 /* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
+#define SPI0_REGBASE                    0xFFC00500
 #define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
 #define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
 #define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
@@ -456,6 +457,7 @@
 #define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
 /* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+#define TWI0_REGBASE                    0xFFC01400
 #define TWI_CLKDIV                      0xFFC01400      /* Serial Clock Divider Register                        */
 #define TWI_CONTROL                     0xFFC01404      /* TWI Control Register                                         */
 #define TWI_SLAVE_CTL           0xFFC01408      /* Slave Mode Control Register                          */
@@ -1165,7 +1167,7 @@
 #define GM                      0x0008  /* Get More (When RDBR Full, Overwrite/Discard*)        */
 #define PSSE            0x0010  /* Slave-Select Input Enable                                            */
 #define EMISO           0x0020  /* Enable MISO As Output                                                        */
-#define SPI_SIZE        0x0100  /* Size of Words (16/8* Bits)                                           */
+#define SIZE            0x0100  /* Size of Words (16/8* Bits)                                           */
 #define LSBF            0x0200  /* LSB First                                                                            */
 #define CPHA            0x0400  /* Clock Phase                                                                          */
 #define CPOL            0x0800  /* Clock Polarity                                                                       */
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
index 8af2a832ef6b..36c44bc1a917 100644
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -160,6 +160,8 @@ Core        Emulation               **
 #define IRQ_PH14        96
 #define IRQ_PH15        97
+#define GPIO_IRQ_BASE   IRQ_PF0
 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS     (IRQ_PH15+1)
 #else
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
index 2a808c1202bf..18759e38eaae 100644
--- a/include/asm-blackfin/mach-bf537/mem_map.h
+++ b/include/asm-blackfin/mach-bf537/mem_map.h
@@ -52,10 +52,10 @@
 /* Memory Map for ADSP-BF537 processors */
-#ifdef CONFIG_BLKFIN_CACHE
+#ifdef CONFIG_BFIN_ICACHE
-#define BLKFIN_ICACHESIZE       (16*1024)
+#define BFIN_ICACHESIZE (16*1024)
 #else
-#define BLKFIN_ICACHESIZE       (0*1024)
+#define BFIN_ICACHESIZE (0*1024)
 #endif
@@ -66,29 +66,29 @@
 #define L1_CODE_LENGTH      0xC000
-#ifdef CONFIG_BLKFIN_DCACHE
+#ifdef CONFIG_BFIN_DCACHE
-#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#ifdef CONFIG_BFIN_DCACHE_BANKA
 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 #define L1_DATA_B_LENGTH      0x8000
-#define BLKFIN_DCACHESIZE       (16*1024)
+#define BFIN_DCACHESIZE (16*1024)
-#define BLKFIN_DSUPBANKS        1
+#define BFIN_DSUPBANKS  1
 #else
 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BLKFIN_DCACHESIZE       (32*1024)
+#define BFIN_DCACHESIZE (32*1024)
-#define BLKFIN_DSUPBANKS        2
+#define BFIN_DSUPBANKS  2
 #endif
 #else
 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      0x8000
 #define L1_DATA_B_LENGTH      0x8000
-#define BLKFIN_DCACHESIZE       (0*1024)
+#define BFIN_DCACHESIZE (0*1024)
-#define BLKFIN_DSUPBANKS        0
+#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BLKFIN_DCACHE*/
+#endif /*CONFIG_BFIN_DCACHE*/
 #endif /*CONFIG_BF537*/
@@ -102,30 +102,30 @@
 #define L1_CODE_LENGTH      0xC000
-#ifdef CONFIG_BLKFIN_DCACHE
+#ifdef CONFIG_BFIN_DCACHE
-#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#ifdef CONFIG_BFIN_DCACHE_BANKA
 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
 #define L1_DATA_B_LENGTH      0x4000
-#define BLKFIN_DCACHESIZE       (16*1024)
+#define BFIN_DCACHESIZE (16*1024)
-#define BLKFIN_DSUPBANKS        1
+#define BFIN_DSUPBANKS  1
 #else
 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
 #define L1_DATA_B_LENGTH      (0x4000 - 0x4000)
-#define BLKFIN_DCACHESIZE       (32*1024)
+#define BFIN_DCACHESIZE (32*1024)
-#define BLKFIN_DSUPBANKS        2
+#define BFIN_DSUPBANKS  2
 #endif
 #else
 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      0x4000
 #define L1_DATA_B_LENGTH      0x4000
-#define BLKFIN_DCACHESIZE       (0*1024)
+#define BFIN_DCACHESIZE (0*1024)
-#define BLKFIN_DSUPBANKS        0
+#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BLKFIN_DCACHE*/
+#endif /*CONFIG_BFIN_DCACHE*/
 #endif
@@ -138,30 +138,30 @@
 #define L1_CODE_LENGTH      0xC000
-#ifdef CONFIG_BLKFIN_DCACHE
+#ifdef CONFIG_BFIN_DCACHE
-#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#ifdef CONFIG_BFIN_DCACHE_BANKA
 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 #define L1_DATA_B_LENGTH      0x8000
-#define BLKFIN_DCACHESIZE       (16*1024)
+#define BFIN_DCACHESIZE (16*1024)
-#define BLKFIN_DSUPBANKS        1
+#define BFIN_DSUPBANKS  1
 #else
 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BLKFIN_DCACHESIZE       (32*1024)
+#define BFIN_DCACHESIZE (32*1024)
-#define BLKFIN_DSUPBANKS        2
+#define BFIN_DSUPBANKS  2
 #endif
 #else
 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      0x8000
 #define L1_DATA_B_LENGTH      0x8000
-#define BLKFIN_DCACHESIZE       (0*1024)
+#define BFIN_DCACHESIZE (0*1024)
-#define BLKFIN_DSUPBANKS        0
+#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BLKFIN_DCACHE*/
+#endif /*CONFIG_BFIN_DCACHE*/
 #endif
diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h
index ae6c53b28452..5a3f7d3bf73d 100644
--- a/include/asm-blackfin/mach-bf537/portmux.h
+++ b/include/asm-blackfin/mach-bf537/portmux.h
@@ -99,7 +99,7 @@
 #define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
 #define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
 #define P_SPORT0_TFS    (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
-#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
+#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
 #define P_CAN0_RX       (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
 #define P_CAN0_TX       (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
 #define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
index aca1d4ba145c..c5b63759cdee 100644
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -1,74 +1,85 @@
 /*
- * File:         include/asm-blackfin/mach-bf548/anomaly.h
+ * File: include/asm-blackfin/mach-bf548/anomaly.h
- * Based on:
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
- * This program is free software; you can redistribute it and/or modify
+ * Copyright (C) 2004-2007 Analog Devices Inc.
- * it under the terms of the GNU General Public License as published by
+ * Licensed under the GPL-2 or later.
- * the Free Software Foundation; either version 2, or (at your option)
+ */
- * any later version.
- *
+/* This file shoule be up to date with:
- * This program is distributed in the hope that it will be useful,
+ *  - Revision C, July 16, 2007; ADSP-BF549 Silicon Anomaly List
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */
 #ifndef _MACH_ANOMALY_H_
 #define _MACH_ANOMALY_H_
-#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
-                            slot1 and store of a P register in slot 2 is not
-                            supported */
-#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
-                            Channel DMA stops */
-#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
-                            registers. */
-#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the
-                            Shadow of a Conditional Branch */
-#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
-                            interrupt not functional */
-#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
-                            SPORT external receive and transmit clocks. */
-#define ANOMALY_05000272 /* Certain data cache write through modes fail for
-                            VDDint <=0.9V */
-#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
-                            not restored */
-#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
-                            Boundary of Reserved Memory */
-#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and
-                            LC Registers Are Interrupted */
-#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */
-#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to
-                            the USB FIFO Simultaneously */
-#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write()
-                            function */
-#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional
-                            */
-#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */
-#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM
-                            Skew */
-#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration
-                            of Host DMA Port */
-#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent
-                            Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#endif /* _MACH_ANOMALY_H_ */
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
+#define ANOMALY_05000074 (1)
+/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
+#define ANOMALY_05000119 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (1)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (1)
+/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
+#define ANOMALY_05000272 (1)
+/* False Hardware Error Exception when ISR context is not restored */
+#define ANOMALY_05000281 (1)
+/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
+#define ANOMALY_05000304 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (1)
+/* TWI Slave Boot Mode Is Not Functional */
+#define ANOMALY_05000324 (1)
+/* External FIFO Boot Mode Is Not Functional */
+#define ANOMALY_05000325 (1)
+/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
+#define ANOMALY_05000327 (1)
+/* Incorrect Access of OTP_STATUS During otp_write() Function */
+#define ANOMALY_05000328 (1)
+/* Synchronous Burst Flash Boot Mode Is Not Functional */
+#define ANOMALY_05000329 (1)
+/* Host DMA Boot Mode Is Not Functional */
+#define ANOMALY_05000330 (1)
+/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
+#define ANOMALY_05000334 (1)
+/* Inadequate Rotary Debounce Logic Duration */
+#define ANOMALY_05000335 (1)
+/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
+#define ANOMALY_05000336 (1)
+/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
+#define ANOMALY_05000337 (1)
+/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
+#define ANOMALY_05000338 (1)
+/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
+#define ANOMALY_05000340 (1)
+/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
+#define ANOMALY_05000344 (1)
+/* USB Calibration Value Is Not Intialized */
+#define ANOMALY_05000346 (1)
+/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
+#define ANOMALY_05000347 (1)
+/* Data Lost when Core Reads SDH Data FIFO */
+#define ANOMALY_05000349 (1)
+/* PLL Status Register Is Inaccurate */
+#define ANOMALY_05000351 (1)
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000125 (0)
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000244 (0)
+#define ANOMALY_05000261 (0)
+#define ANOMALY_05000263 (0)
+#define ANOMALY_05000266 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000323 (0)
+#endif
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
index 9498313a2cb7..7e6d349beb08 100644
--- a/include/asm-blackfin/mach-bf548/bf548.h
+++ b/include/asm-blackfin/mach-bf548/bf548.h
@@ -52,12 +52,12 @@
 /***************************/
-#define BLKFIN_DSUBBANKS        4
+#define BFIN_DSUBBANKS  4
-#define BLKFIN_DWAYS            2
+#define BFIN_DWAYS              2
-#define BLKFIN_DLINES           64
+#define BFIN_DLINES             64
-#define BLKFIN_ISUBBANKS        4
+#define BFIN_ISUBBANKS  4
-#define BLKFIN_IWAYS            4
+#define BFIN_IWAYS              4
-#define BLKFIN_ILINES           32
+#define BFIN_ILINES             32
 #define WAY0_L                  0x1
 #define WAY1_L                  0x2
@@ -106,93 +106,6 @@
 #define AMGCTLVAL       (V_AMBEN | V_AMCKEN)
-#define MAX_VC  650000000
-#define MIN_VC  50000000
-/********************************PLL Settings **************************************/
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-#if (CONFIG_VCO_MULT < 0)
-#error "VCO Multiplier is less than 0. Please select a different value"
-#endif
-#if (CONFIG_VCO_MULT == 0)
-#error "VCO Multiplier should be greater than 0. Please select a different value"
-#endif
-#if (CONFIG_VCO_MULT > 64)
-#error "VCO Multiplier is more than 64. Please select a different value"
-#endif
-#ifndef CONFIG_CLKIN_HALF
-#define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
-#else
-#define CONFIG_VCO_HZ   ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
-#endif
-#ifndef CONFIG_PLL_BYPASS
-#define CONFIG_CCLK_HZ  (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
-#define CONFIG_SCLK_HZ  (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
-#else
-#define CONFIG_CCLK_HZ  CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ  CONFIG_CLKIN_HZ
-#endif
-#if (CONFIG_SCLK_DIV < 1)
-#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
-#endif
-#if (CONFIG_SCLK_DIV > 15)
-#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
-#endif
-#if (CONFIG_CCLK_DIV != 1)
-#if (CONFIG_CCLK_DIV != 2)
-#if (CONFIG_CCLK_DIV != 4)
-#if (CONFIG_CCLK_DIV != 8)
-#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
-#endif
-#endif
-#endif
-#endif
-#if (CONFIG_VCO_HZ > MAX_VC)
-#error "VCO selected is more than maximum value. Please change the VCO multipler"
-#endif
-#if (CONFIG_SCLK_HZ > 133000000)
-#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
-#endif
-#if (CONFIG_SCLK_HZ < 27000000)
-#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
-#endif
-#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
-#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
-#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
-#error "Please select sclk less than cclk"
-#endif
-#endif
-#endif
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
-#endif
-#endif  /* CONFIG_BFIN_KERNEL_CLOCK */
 #ifdef CONFIG_BF542
 #define CPU "BF542"
 #define CPUID 0x027c8000
@@ -213,59 +126,4 @@
 #define CPUID 0x0
 #endif
-#if (CONFIG_MEM_SIZE % 4)
-#error "SDRAM mem size must be multible of 4MB"
-#endif
-#define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
-#define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
-#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
-/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
-#define ANOMALY_05000158_WORKAROUND             0x200
-#ifdef CONFIG_BLKFIN_WB         /*Write Back Policy */
-#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_DIRTY \
-                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#else                           /*Write Through */
-#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
-                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
-#endif
-#define L1_DMEMORY       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
-#define SDRAM_DNON_CHBL  (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
-#define SDRAM_EBIU       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
-#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
-#define SIZE_1K 0x00000400      /* 1K */
-#define SIZE_4K 0x00001000      /* 4K */
-#define SIZE_1M 0x00100000      /* 1M */
-#define SIZE_4M 0x00400000      /* 4M */
-#define MAX_CPLBS (16 * 2)
-/*
-* Number of required data CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 16 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Data Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-* 1 for ASYNC Memory
-*/
-#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
-/*
-* Number of required instruction CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 12 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Instruction Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-*/
-#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
 #endif  /* __MACH_BF48_H__  */
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index 2f4afc90db11..f21a1620e6bd 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -1,5 +1,6 @@
 #include <linux/serial.h>
 #include <asm/dma.h>
+#include <asm/portmux.h>
 #define NR_PORTS                4
@@ -143,50 +144,48 @@ struct bfin_serial_res bfin_serial_resource[] = {
 int nr_ports = ARRAY_SIZE(bfin_serial_resource);
+#define DRIVER_NAME "bfin-uart"
 static void bfin_serial_hw_init(struct bfin_serial_port *uart)
 {
 #ifdef CONFIG_SERIAL_BFIN_UART0
-        /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */
+        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER());
+        peripheral_request(P_UART0_RX, DRIVER_NAME);
-        bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX());
 #endif
 #ifdef CONFIG_SERIAL_BFIN_UART1
-        /* Enable UART1 RX and TX on pin 0 & 1 of PORT H */
+        peripheral_request(P_UART1_TX, DRIVER_NAME);
-        bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER());
+        peripheral_request(P_UART1_RX, DRIVER_NAME);
-        bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX());
 #ifdef CONFIG_BFIN_UART1_CTSRTS
-        /* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */
+        peripheral_request(P_UART1_RTS, DRIVER_NAME);
-        bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER());
+        peripheral_request(P_UART1_CTS DRIVER_NAME);
-        bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX());
 #endif
 #endif
 #ifdef CONFIG_SERIAL_BFIN_UART2
-        /* Enable UART2 RX and TX on pin 4 & 5 of PORT B */
+        peripheral_request(P_UART2_TX, DRIVER_NAME);
-        bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER());
+        peripheral_request(P_UART2_RX, DRIVER_NAME);
-        bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX());
 #endif
 #ifdef CONFIG_SERIAL_BFIN_UART3
-        /* Enable UART3 RX and TX on pin 6 & 7 of PORT B */
+        peripheral_request(P_UART3_TX, DRIVER_NAME);
-        bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER());
+        peripheral_request(P_UART3_RX, DRIVER_NAME);
-        bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX());
 #ifdef CONFIG_BFIN_UART3_CTSRTS
-        /* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */
+        peripheral_request(P_UART3_RTS, DRIVER_NAME);
-        bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER());
+        peripheral_request(P_UART3_CTS DRIVER_NAME);
-        bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX());
 #endif
 #endif
        SSYNC();
 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
        if (uart->cts_pin >= 0) {
-                gpio_request(uart->cts_pin, NULL);
+                gpio_request(uart->cts_pin, DRIVER_NAME);
                gpio_direction_input(uart->cts_pin);
        }
        if (uart->rts_pin >= 0) {
-                gpio_request(uart->rts_pin, NULL);
+                gpio_request(uart->rts_pin, DRIVER_NAME);
                gpio_direction_output(uart->rts_pin);
        }
 #endif
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
index 791218fe7d94..19e84dd4c99c 100644
--- a/include/asm-blackfin/mach-bf548/blackfin.h
+++ b/include/asm-blackfin/mach-bf548/blackfin.h
@@ -54,7 +54,7 @@
 #include "defBF549.h"
 #endif
-#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
+#if !defined(__ASSEMBLY__)
 #ifdef CONFIG_BF542
 #include "cdefBF542.h"
 #endif
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index cdf29e75ea59..aefab3f618c1 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -31,6 +31,8 @@
 #ifndef _CDEF_BF54X_H
 #define _CDEF_BF54X_H
+#include <asm/blackfin.h>
 #include "defBF54x_base.h"
 #include <asm/system.h>
@@ -60,7 +62,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
        bfin_write32(SIC_IWR2, 0);
        bfin_write16(VR_CTL, val);
-        __builtin_bfin_ssync();
+        SSYNC();
        local_irq_save(flags);
        asm("IDLE;");
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
index dd955dcd39b8..760307e34b9e 100644
--- a/include/asm-blackfin/mach-bf548/defBF544.h
+++ b/include/asm-blackfin/mach-bf548/defBF544.h
@@ -81,6 +81,7 @@
 /* Two Wire Interface Registers (TWI1) */
+#define                     TWI1_REGBASE  0xffc02200
 #define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
 #define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
 #define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index 8d4214e0807c..70af33c963b0 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -120,6 +120,7 @@
 /* Two Wire Interface Registers (TWI1) */
+#define                     TWI1_REGBASE  0xffc02200
 #define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
 #define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
 #define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
@@ -139,6 +140,7 @@
 /* SPI2  Registers */
+#define                     SPI2_REGBASE  0xffc02400
 #define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
 #define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
 #define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h
index c2f4734da48d..50b3fe55ef0c 100644
--- a/include/asm-blackfin/mach-bf548/defBF549.h
+++ b/include/asm-blackfin/mach-bf548/defBF549.h
@@ -121,6 +121,7 @@
 /* Two Wire Interface Registers (TWI1) */
+#define                     TWI1_REGBASE  0xffc02200
 #define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
 #define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
 #define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
@@ -140,6 +141,7 @@
 /* SPI2  Registers */
+#define                     SPI2_REGBASE  0xffc02400
 #define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
 #define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
 #define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 895ddd40a838..e2632db74baa 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -109,6 +109,7 @@
 /* SPI0 Registers */
+#define                     SPI0_REGBASE  0xffc00500
 #define                         SPI0_CTL  0xffc00500   /* SPI0 Control Register */
 #define                         SPI0_FLG  0xffc00504   /* SPI0 Flag Register */
 #define                        SPI0_STAT  0xffc00508   /* SPI0 Status Register */
@@ -121,6 +122,7 @@
 /* Two Wire Interface Registers (TWI0) */
+#define                     TWI0_REGBASE  0xffc00700
 #define                      TWI0_CLKDIV  0xffc00700   /* Clock Divider Register */
 #define                     TWI0_CONTROL  0xffc00704   /* TWI Control Register */
 #define                  TWI0_SLAVE_CTRL  0xffc00708   /* TWI Slave Mode Control Register */
@@ -978,6 +980,7 @@
 /* SPI1 Registers */
+#define                     SPI1_REGBASE  0xffc02300
 #define                         SPI1_CTL  0xffc02300   /* SPI1 Control Register */
 #define                         SPI1_FLG  0xffc02304   /* SPI1 Flag Register */
 #define                        SPI1_STAT  0xffc02308   /* SPI1 Status Register */
diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h
index dbf66bcabe35..cb8b0f15c9a6 100644
--- a/include/asm-blackfin/mach-bf548/gpio.h
+++ b/include/asm-blackfin/mach-bf548/gpio.h
@@ -209,8 +209,3 @@ struct gpio_port_t {
        unsigned short dummy7;
        unsigned int port_mux;
 };
-int gpio_request(unsigned short gpio, const char *label);
-void peripheral_free(unsigned short per);
-int peripheral_request_list(unsigned short per[], const char *label);
-void peripheral_free_list(unsigned short per[]);
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index e548d3cd81e3..3b08cf9bd6f3 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -55,287 +55,288 @@ Events         (highest priority)  EMU         0
 /* The ABSTRACT IRQ definitions */
 /** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU         0       /* Emulation */
+#define IRQ_EMU                 0       /* Emulation */
-#define IRQ_RST         1       /* reset */
+#define IRQ_RST                 1       /* reset */
-#define IRQ_NMI         2       /* Non Maskable */
+#define IRQ_NMI                 2       /* Non Maskable */
-#define IRQ_EVX         3       /* Exception */
+#define IRQ_EVX                 3       /* Exception */
-#define IRQ_UNUSED      4       /* - unused interrupt*/
+#define IRQ_UNUSED              4       /* - unused interrupt*/
-#define IRQ_HWERR       5       /* Hardware Error */
+#define IRQ_HWERR               5       /* Hardware Error */
-#define IRQ_CORETMR     6       /* Core timer */
+#define IRQ_CORETMR             6       /* Core timer */
-#define BFIN_IRQ(x)     ((x) + 7)
+#define BFIN_IRQ(x)             ((x) + 7)
-#define IRQ_PLL_WAKEUP  BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
+#define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
-#define IRQ_DMAC0_ERR   BFIN_IRQ(1)     /* DMAC0 Status Interrupt */
+#define IRQ_DMAC0_ERROR         BFIN_IRQ(1)     /* DMAC0 Status Interrupt */
-#define IRQ_EPPI0_ERR   BFIN_IRQ(2)     /* EPPI0 Error Interrupt */
+#define IRQ_EPPI0_ERROR         BFIN_IRQ(2)     /* EPPI0 Error Interrupt */
-#define IRQ_SPORT0_ERR  BFIN_IRQ(3)     /* SPORT0 Error Interrupt */
+#define IRQ_SPORT0_ERROR        BFIN_IRQ(3)     /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERR  BFIN_IRQ(4)     /* SPORT1 Error Interrupt */
+#define IRQ_SPORT1_ERROR        BFIN_IRQ(4)     /* SPORT1 Error Interrupt */
-#define IRQ_SPI0_ERR    BFIN_IRQ(5)     /* SPI0 Status(Error) Interrupt */
+#define IRQ_SPI0_ERROR          BFIN_IRQ(5)     /* SPI0 Status(Error) Interrupt */
-#define IRQ_UART0_ERR   BFIN_IRQ(6)     /* UART0 Status(Error) Interrupt */
+#define IRQ_UART0_ERROR         BFIN_IRQ(6)     /* UART0 Status(Error) Interrupt */
-#define IRQ_RTC         BFIN_IRQ(7)     /* RTC Interrupt */
+#define IRQ_RTC                 BFIN_IRQ(7)     /* RTC Interrupt */
-#define IRQ_EPPI0       BFIN_IRQ(8)     /* EPPI0 Interrupt (DMA12) */
+#define IRQ_EPPI0               BFIN_IRQ(8)     /* EPPI0 Interrupt (DMA12) */
-#define IRQ_SPORT0_RX   BFIN_IRQ(9)     /* SPORT0 RX Interrupt (DMA0) */
+#define IRQ_SPORT0_RX           BFIN_IRQ(9)     /* SPORT0 RX Interrupt (DMA0) */
-#define IRQ_SPORT0_TX   BFIN_IRQ(10)    /* SPORT0 TX Interrupt (DMA1) */
+#define IRQ_SPORT0_TX           BFIN_IRQ(10)    /* SPORT0 TX Interrupt (DMA1) */
-#define IRQ_SPORT1_RX   BFIN_IRQ(11)    /* SPORT1 RX Interrupt (DMA2) */
+#define IRQ_SPORT1_RX           BFIN_IRQ(11)    /* SPORT1 RX Interrupt (DMA2) */
-#define IRQ_SPORT1_TX   BFIN_IRQ(12)    /* SPORT1 TX Interrupt (DMA3) */
+#define IRQ_SPORT1_TX           BFIN_IRQ(12)    /* SPORT1 TX Interrupt (DMA3) */
-#define IRQ_SPI0        BFIN_IRQ(13)    /* SPI0 Interrupt (DMA4) */
+#define IRQ_SPI0                BFIN_IRQ(13)    /* SPI0 Interrupt (DMA4) */
-#define IRQ_UART0_RX    BFIN_IRQ(14)    /* UART0 RX Interrupt (DMA6) */
+#define IRQ_UART0_RX            BFIN_IRQ(14)    /* UART0 RX Interrupt (DMA6) */
-#define IRQ_UART0_TX    BFIN_IRQ(15)    /* UART0 TX Interrupt (DMA7) */
+#define IRQ_UART0_TX            BFIN_IRQ(15)    /* UART0 TX Interrupt (DMA7) */
-#define IRQ_TIMER8      BFIN_IRQ(16)    /* TIMER 8 Interrupt */
+#define IRQ_TIMER8              BFIN_IRQ(16)    /* TIMER 8 Interrupt */
-#define IRQ_TIMER9      BFIN_IRQ(17)    /* TIMER 9 Interrupt */
+#define IRQ_TIMER9              BFIN_IRQ(17)    /* TIMER 9 Interrupt */
-#define IRQ_TIMER10     BFIN_IRQ(18)    /* TIMER 10 Interrupt */
+#define IRQ_TIMER10             BFIN_IRQ(18)    /* TIMER 10 Interrupt */
-#define IRQ_PINT0       BFIN_IRQ(19)    /* PINT0 Interrupt */
+#define IRQ_PINT0               BFIN_IRQ(19)    /* PINT0 Interrupt */
-#define IRQ_PINT1       BFIN_IRQ(20)    /* PINT1 Interrupt */
+#define IRQ_PINT1               BFIN_IRQ(20)    /* PINT1 Interrupt */
-#define IRQ_MDMAS0      BFIN_IRQ(21)    /* MDMA Stream 0 Interrupt */
+#define IRQ_MDMAS0              BFIN_IRQ(21)    /* MDMA Stream 0 Interrupt */
-#define IRQ_MDMAS1      BFIN_IRQ(22)    /* MDMA Stream 1 Interrupt */
+#define IRQ_MDMAS1              BFIN_IRQ(22)    /* MDMA Stream 1 Interrupt */
-#define IRQ_WATCHDOG    BFIN_IRQ(23)    /* Watchdog Interrupt */
+#define IRQ_WATCHDOG            BFIN_IRQ(23)    /* Watchdog Interrupt */
-#define IRQ_DMAC1_ERR   BFIN_IRQ(24)    /* DMAC1 Status (Error) Interrupt */
+#define IRQ_DMAC1_ERROR         BFIN_IRQ(24)    /* DMAC1 Status (Error) Interrupt */
-#define IRQ_SPORT2_ERR  BFIN_IRQ(25)    /* SPORT2 Error Interrupt */
+#define IRQ_SPORT2_ERROR        BFIN_IRQ(25)    /* SPORT2 Error Interrupt */
-#define IRQ_SPORT3_ERR  BFIN_IRQ(26)    /* SPORT3 Error Interrupt */
+#define IRQ_SPORT3_ERROR        BFIN_IRQ(26)    /* SPORT3 Error Interrupt */
-#define IRQ_MXVR_DATA   BFIN_IRQ(27)    /* MXVR Data Interrupt */
+#define IRQ_MXVR_DATA           BFIN_IRQ(27)    /* MXVR Data Interrupt */
-#define IRQ_SPI1_ERR    BFIN_IRQ(28)    /* SPI1 Status (Error) Interrupt */
+#define IRQ_SPI1_ERROR          BFIN_IRQ(28)    /* SPI1 Status (Error) Interrupt */
-#define IRQ_SPI2_ERR    BFIN_IRQ(29)    /* SPI2 Status (Error) Interrupt */
+#define IRQ_SPI2_ERROR          BFIN_IRQ(29)    /* SPI2 Status (Error) Interrupt */
-#define IRQ_UART1_ERR   BFIN_IRQ(30)    /* UART1 Status (Error) Interrupt */
+#define IRQ_UART1_ERROR         BFIN_IRQ(30)    /* UART1 Status (Error) Interrupt */
-#define IRQ_UART2_ERR   BFIN_IRQ(31)    /* UART2 Status (Error) Interrupt */
+#define IRQ_UART2_ERROR         BFIN_IRQ(31)    /* UART2 Status (Error) Interrupt */
-#define IRQ_CAN0_ERR    BFIN_IRQ(32)    /* CAN0 Status (Error) Interrupt */
+#define IRQ_CAN0_ERROR          BFIN_IRQ(32)    /* CAN0 Status (Error) Interrupt */
-#define IRQ_SPORT2_RX   BFIN_IRQ(33)    /* SPORT2 RX (DMA18) Interrupt */
+#define IRQ_SPORT2_RX           BFIN_IRQ(33)    /* SPORT2 RX (DMA18) Interrupt */
-#define IRQ_SPORT2_TX   BFIN_IRQ(34)    /* SPORT2 TX (DMA19) Interrupt */
+#define IRQ_SPORT2_TX           BFIN_IRQ(34)    /* SPORT2 TX (DMA19) Interrupt */
-#define IRQ_SPORT3_RX   BFIN_IRQ(35)    /* SPORT3 RX (DMA20) Interrupt */
+#define IRQ_SPORT3_RX           BFIN_IRQ(35)    /* SPORT3 RX (DMA20) Interrupt */
-#define IRQ_SPORT3_TX   BFIN_IRQ(36)    /* SPORT3 TX (DMA21) Interrupt */
+#define IRQ_SPORT3_TX           BFIN_IRQ(36)    /* SPORT3 TX (DMA21) Interrupt */
-#define IRQ_EPPI1       BFIN_IRQ(37)    /* EPP1 (DMA13) Interrupt */
+#define IRQ_EPPI1               BFIN_IRQ(37)    /* EPP1 (DMA13) Interrupt */
-#define IRQ_EPPI2       BFIN_IRQ(38)    /* EPP2 (DMA14) Interrupt */
+#define IRQ_EPPI2               BFIN_IRQ(38)    /* EPP2 (DMA14) Interrupt */
-#define IRQ_SPI1        BFIN_IRQ(39)    /* SPI1 (DMA5) Interrupt */
+#define IRQ_SPI1                BFIN_IRQ(39)    /* SPI1 (DMA5) Interrupt */
-#define IRQ_SPI2        BFIN_IRQ(40)    /* SPI2 (DMA23) Interrupt */
+#define IRQ_SPI2                BFIN_IRQ(40)    /* SPI2 (DMA23) Interrupt */
-#define IRQ_UART1_RX    BFIN_IRQ(41)    /* UART1 RX (DMA8) Interrupt */
+#define IRQ_UART1_RX            BFIN_IRQ(41)    /* UART1 RX (DMA8) Interrupt */
-#define IRQ_UART1_TX    BFIN_IRQ(42)    /* UART1 TX (DMA9) Interrupt */
+#define IRQ_UART1_TX            BFIN_IRQ(42)    /* UART1 TX (DMA9) Interrupt */
-#define IRQ_ATAPI_RX    BFIN_IRQ(43)    /* ATAPI RX (DMA10) Interrupt */
+#define IRQ_ATAPI_RX            BFIN_IRQ(43)    /* ATAPI RX (DMA10) Interrupt */
-#define IRQ_ATAPI_TX    BFIN_IRQ(44)    /* ATAPI TX (DMA11) Interrupt */
+#define IRQ_ATAPI_TX            BFIN_IRQ(44)    /* ATAPI TX (DMA11) Interrupt */
-#define IRQ_TWI0        BFIN_IRQ(45)    /* TWI0 Interrupt */
+#define IRQ_TWI0                BFIN_IRQ(45)    /* TWI0 Interrupt */
-#define IRQ_TWI1        BFIN_IRQ(46)    /* TWI1 Interrupt */
+#define IRQ_TWI1                BFIN_IRQ(46)    /* TWI1 Interrupt */
-#define IRQ_TWI         IRQ_TWI0        /* TWI Interrupt */
+#define IRQ_CAN0_RX             BFIN_IRQ(47)    /* CAN0 Receive Interrupt */
-#define IRQ_CAN0_RX     BFIN_IRQ(47)    /* CAN0 Receive Interrupt */
+#define IRQ_CAN0_TX             BFIN_IRQ(48)    /* CAN0 Transmit Interrupt */
-#define IRQ_CAN0_TX     BFIN_IRQ(48)    /* CAN0 Transmit Interrupt */
+#define IRQ_MDMAS2              BFIN_IRQ(49)    /* MDMA Stream 2 Interrupt */
-#define IRQ_MDMAS2      BFIN_IRQ(49)    /* MDMA Stream 2 Interrupt */
+#define IRQ_MDMAS3              BFIN_IRQ(50)    /* MDMA Stream 3 Interrupt */
-#define IRQ_MDMAS3      BFIN_IRQ(50)    /* MDMA Stream 3 Interrupt */
+#define IRQ_MXVR_ERROR          BFIN_IRQ(51)    /* MXVR Status (Error) Interrupt */
-#define IRQ_MXVR_ERR    BFIN_IRQ(51)    /* MXVR Status (Error) Interrupt */
+#define IRQ_MXVR_MSG            BFIN_IRQ(52)    /* MXVR Message Interrupt */
-#define IRQ_MXVR_MSG    BFIN_IRQ(52)    /* MXVR Message Interrupt */
+#define IRQ_MXVR_PKT            BFIN_IRQ(53)    /* MXVR Packet Interrupt */
-#define IRQ_MXVR_PKT    BFIN_IRQ(53)    /* MXVR Packet Interrupt */
+#define IRQ_EPP1_ERROR          BFIN_IRQ(54)    /* EPPI1 Error Interrupt */
-#define IRQ_EPP1_ERR    BFIN_IRQ(54)    /* EPPI1 Error Interrupt */
+#define IRQ_EPP2_ERROR          BFIN_IRQ(55)    /* EPPI2 Error Interrupt */
-#define IRQ_EPP2_ERR    BFIN_IRQ(55)    /* EPPI2 Error Interrupt */
+#define IRQ_UART3_ERROR         BFIN_IRQ(56)    /* UART3 Status (Error) Interrupt */
-#define IRQ_UART3_ERR   BFIN_IRQ(56)    /* UART3 Status (Error) Interrupt */
+#define IRQ_HOST_ERROR          BFIN_IRQ(57)    /* HOST Status (Error) Interrupt */
-#define IRQ_HOST_ERR    BFIN_IRQ(57)    /* HOST Status (Error) Interrupt */
+#define IRQ_PIXC_ERROR          BFIN_IRQ(59)    /* PIXC Status (Error) Interrupt */
-#define IRQ_PIXC_ERR    BFIN_IRQ(59)    /* PIXC Status (Error) Interrupt */
+#define IRQ_NFC_ERROR           BFIN_IRQ(60)    /* NFC Error Interrupt */
-#define IRQ_NFC_ERR     BFIN_IRQ(60)    /* NFC Error Interrupt */
+#define IRQ_ATAPI_ERROR         BFIN_IRQ(61)    /* ATAPI Error Interrupt */
-#define IRQ_ATAPI_ERR   BFIN_IRQ(61)    /* ATAPI Error Interrupt */
+#define IRQ_CAN1_ERROR          BFIN_IRQ(62)    /* CAN1 Status (Error) Interrupt */
-#define IRQ_CAN1_ERR    BFIN_IRQ(62)    /* CAN1 Status (Error) Interrupt */
+#define IRQ_HS_DMA_ERROR        BFIN_IRQ(63)    /* Handshake DMA Status Interrupt */
-#define IRQ_HS_DMA_ERR  BFIN_IRQ(63)    /* Handshake DMA Status Interrupt */
+#define IRQ_PIXC_IN0            BFIN_IRQ(64)    /* PIXC IN0 (DMA15) Interrupt */
-#define IRQ_PIXC_IN0    BFIN_IRQ(64)    /* PIXC IN0 (DMA15) Interrupt */
+#define IRQ_PIXC_IN1            BFIN_IRQ(65)    /* PIXC IN1 (DMA16) Interrupt */
-#define IRQ_PIXC_IN1    BFIN_IRQ(65)    /* PIXC IN1 (DMA16) Interrupt */
+#define IRQ_PIXC_OUT            BFIN_IRQ(66)    /* PIXC OUT (DMA17) Interrupt */
-#define IRQ_PIXC_OUT    BFIN_IRQ(66)    /* PIXC OUT (DMA17) Interrupt */
+#define IRQ_SDH                 BFIN_IRQ(67)    /* SDH/NFC (DMA22) Interrupt */
-#define IRQ_SDH         BFIN_IRQ(67)    /* SDH/NFC (DMA22) Interrupt */
+#define IRQ_CNT                 BFIN_IRQ(68)    /* CNT Interrupt */
-#define IRQ_CNT         BFIN_IRQ(68)    /* CNT Interrupt */
+#define IRQ_KEY                 BFIN_IRQ(69)    /* KEY Interrupt */
-#define IRQ_KEY         BFIN_IRQ(69)    /* KEY Interrupt */
+#define IRQ_CAN1_RX             BFIN_IRQ(70)    /* CAN1 RX Interrupt */
-#define IRQ_CAN1_RX     BFIN_IRQ(70)    /* CAN1 RX Interrupt */
+#define IRQ_CAN1_TX             BFIN_IRQ(71)    /* CAN1 TX Interrupt */
-#define IRQ_CAN1_TX     BFIN_IRQ(71)    /* CAN1 TX Interrupt */
+#define IRQ_SDH_MASK0           BFIN_IRQ(72)    /* SDH Mask 0 Interrupt */
-#define IRQ_SDH_MASK0   BFIN_IRQ(72)    /* SDH Mask 0 Interrupt */
+#define IRQ_SDH_MASK1           BFIN_IRQ(73)    /* SDH Mask 1 Interrupt */
-#define IRQ_SDH_MASK1   BFIN_IRQ(73)    /* SDH Mask 1 Interrupt */
+#define IRQ_USB_INT0            BFIN_IRQ(75)    /* USB INT0 Interrupt */
-#define IRQ_USB_INT0    BFIN_IRQ(75)    /* USB INT0 Interrupt */
+#define IRQ_USB_INT1            BFIN_IRQ(76)    /* USB INT1 Interrupt */
-#define IRQ_USB_INT1    BFIN_IRQ(76)    /* USB INT1 Interrupt */
+#define IRQ_USB_INT2            BFIN_IRQ(77)    /* USB INT2 Interrupt */
-#define IRQ_USB_INT2    BFIN_IRQ(77)    /* USB INT2 Interrupt */
+#define IRQ_USB_DMA             BFIN_IRQ(78)    /* USB DMA Interrupt */
-#define IRQ_USB_DMA     BFIN_IRQ(78)    /* USB DMA Interrupt */
+#define IRQ_OPTSEC              BFIN_IRQ(79)    /* OTPSEC Interrupt */
-#define IRQ_OPTSEC      BFIN_IRQ(79)    /* OTPSEC Interrupt */
+#define IRQ_TIMER0              BFIN_IRQ(86)    /* Timer 0 Interrupt */
-#define IRQ_TIMER0      BFIN_IRQ(86)    /* Timer 0 Interrupt */
+#define IRQ_TIMER1              BFIN_IRQ(87)    /* Timer 1 Interrupt */
-#define IRQ_TIMER1      BFIN_IRQ(87)    /* Timer 1 Interrupt */
+#define IRQ_TIMER2              BFIN_IRQ(88)    /* Timer 2 Interrupt */
-#define IRQ_TIMER2      BFIN_IRQ(88)    /* Timer 2 Interrupt */
+#define IRQ_TIMER3              BFIN_IRQ(89)    /* Timer 3 Interrupt */
-#define IRQ_TIMER3      BFIN_IRQ(89)    /* Timer 3 Interrupt */
+#define IRQ_TIMER4              BFIN_IRQ(90)    /* Timer 4 Interrupt */
-#define IRQ_TIMER4      BFIN_IRQ(90)    /* Timer 4 Interrupt */
+#define IRQ_TIMER5              BFIN_IRQ(91)    /* Timer 5 Interrupt */
-#define IRQ_TIMER5      BFIN_IRQ(91)    /* Timer 5 Interrupt */
+#define IRQ_TIMER6              BFIN_IRQ(92)    /* Timer 6 Interrupt */
-#define IRQ_TIMER6      BFIN_IRQ(92)    /* Timer 6 Interrupt */
+#define IRQ_TIMER7              BFIN_IRQ(93)    /* Timer 7 Interrupt */
-#define IRQ_TIMER7      BFIN_IRQ(93)    /* Timer 7 Interrupt */
+#define IRQ_PINT2               BFIN_IRQ(94)    /* PINT2 Interrupt */
-#define IRQ_PINT2       BFIN_IRQ(94)    /* PINT2 Interrupt */
+#define IRQ_PINT3               BFIN_IRQ(95)    /* PINT3 Interrupt */
-#define IRQ_PINT3       BFIN_IRQ(95)    /* PINT3 Interrupt */
+#define SYS_IRQS                IRQ_PINT3
-#define SYS_IRQS        IRQ_PINT3
+#define BFIN_PA_IRQ(x)          ((x) + SYS_IRQS + 1)
-#define BFIN_PA_IRQ(x)  ((x) + SYS_IRQS + 1)
+#define IRQ_PA0                 BFIN_PA_IRQ(0)
-#define IRQ_PA0         BFIN_PA_IRQ(0)
+#define IRQ_PA1                 BFIN_PA_IRQ(1)
-#define IRQ_PA1         BFIN_PA_IRQ(1)
+#define IRQ_PA2                 BFIN_PA_IRQ(2)
-#define IRQ_PA2         BFIN_PA_IRQ(2)
+#define IRQ_PA3                 BFIN_PA_IRQ(3)
-#define IRQ_PA3         BFIN_PA_IRQ(3)
+#define IRQ_PA4                 BFIN_PA_IRQ(4)
-#define IRQ_PA4         BFIN_PA_IRQ(4)
+#define IRQ_PA5                 BFIN_PA_IRQ(5)
-#define IRQ_PA5         BFIN_PA_IRQ(5)
+#define IRQ_PA6                 BFIN_PA_IRQ(6)
-#define IRQ_PA6         BFIN_PA_IRQ(6)
+#define IRQ_PA7                 BFIN_PA_IRQ(7)
-#define IRQ_PA7         BFIN_PA_IRQ(7)
+#define IRQ_PA8                 BFIN_PA_IRQ(8)
-#define IRQ_PA8         BFIN_PA_IRQ(8)
+#define IRQ_PA9                 BFIN_PA_IRQ(9)
-#define IRQ_PA9         BFIN_PA_IRQ(9)
+#define IRQ_PA10                BFIN_PA_IRQ(10)
-#define IRQ_PA10        BFIN_PA_IRQ(10)
+#define IRQ_PA11                BFIN_PA_IRQ(11)
-#define IRQ_PA11        BFIN_PA_IRQ(11)
+#define IRQ_PA12                BFIN_PA_IRQ(12)
-#define IRQ_PA12        BFIN_PA_IRQ(12)
+#define IRQ_PA13                BFIN_PA_IRQ(13)
-#define IRQ_PA13        BFIN_PA_IRQ(13)
+#define IRQ_PA14                BFIN_PA_IRQ(14)
-#define IRQ_PA14        BFIN_PA_IRQ(14)
+#define IRQ_PA15                BFIN_PA_IRQ(15)
-#define IRQ_PA15        BFIN_PA_IRQ(15)
+#define BFIN_PB_IRQ(x)          ((x) + IRQ_PA15 + 1)
-#define BFIN_PB_IRQ(x)  ((x) + IRQ_PA15 + 1)
+#define IRQ_PB0                 BFIN_PB_IRQ(0)
-#define IRQ_PB0         BFIN_PB_IRQ(0)
+#define IRQ_PB1                 BFIN_PB_IRQ(1)
-#define IRQ_PB1         BFIN_PB_IRQ(1)
+#define IRQ_PB2                 BFIN_PB_IRQ(2)
-#define IRQ_PB2         BFIN_PB_IRQ(2)
+#define IRQ_PB3                 BFIN_PB_IRQ(3)
-#define IRQ_PB3         BFIN_PB_IRQ(3)
+#define IRQ_PB4                 BFIN_PB_IRQ(4)
-#define IRQ_PB4         BFIN_PB_IRQ(4)
+#define IRQ_PB5                 BFIN_PB_IRQ(5)
-#define IRQ_PB5         BFIN_PB_IRQ(5)
+#define IRQ_PB6                 BFIN_PB_IRQ(6)
-#define IRQ_PB6         BFIN_PB_IRQ(6)
+#define IRQ_PB7                 BFIN_PB_IRQ(7)
-#define IRQ_PB7         BFIN_PB_IRQ(7)
+#define IRQ_PB8                 BFIN_PB_IRQ(8)
-#define IRQ_PB8         BFIN_PB_IRQ(8)
+#define IRQ_PB9                 BFIN_PB_IRQ(9)
-#define IRQ_PB9         BFIN_PB_IRQ(9)
+#define IRQ_PB10                BFIN_PB_IRQ(10)
-#define IRQ_PB10        BFIN_PB_IRQ(10)
+#define IRQ_PB11                BFIN_PB_IRQ(11)
-#define IRQ_PB11        BFIN_PB_IRQ(11)
+#define IRQ_PB12                BFIN_PB_IRQ(12)
-#define IRQ_PB12        BFIN_PB_IRQ(12)
+#define IRQ_PB13                BFIN_PB_IRQ(13)
-#define IRQ_PB13        BFIN_PB_IRQ(13)
+#define IRQ_PB14                BFIN_PB_IRQ(14)
-#define IRQ_PB14        BFIN_PB_IRQ(14)
+#define IRQ_PB15                BFIN_PB_IRQ(15)         /* N/A */
-#define IRQ_PB15        BFIN_PB_IRQ(15)         /* N/A */
+#define BFIN_PC_IRQ(x)          ((x) + IRQ_PB15 + 1)
-#define BFIN_PC_IRQ(x)  ((x) + IRQ_PB15 + 1)
+#define IRQ_PC0                 BFIN_PC_IRQ(0)
-#define IRQ_PC0         BFIN_PC_IRQ(0)
+#define IRQ_PC1                 BFIN_PC_IRQ(1)
-#define IRQ_PC1         BFIN_PC_IRQ(1)
+#define IRQ_PC2                 BFIN_PC_IRQ(2)
-#define IRQ_PC2         BFIN_PC_IRQ(2)
+#define IRQ_PC3                 BFIN_PC_IRQ(3)
-#define IRQ_PC3         BFIN_PC_IRQ(3)
+#define IRQ_PC4                 BFIN_PC_IRQ(4)
-#define IRQ_PC4         BFIN_PC_IRQ(4)
+#define IRQ_PC5                 BFIN_PC_IRQ(5)
-#define IRQ_PC5         BFIN_PC_IRQ(5)
+#define IRQ_PC6                 BFIN_PC_IRQ(6)
-#define IRQ_PC6         BFIN_PC_IRQ(6)
+#define IRQ_PC7                 BFIN_PC_IRQ(7)
-#define IRQ_PC7         BFIN_PC_IRQ(7)
+#define IRQ_PC8                 BFIN_PC_IRQ(8)
-#define IRQ_PC8         BFIN_PC_IRQ(8)
+#define IRQ_PC9                 BFIN_PC_IRQ(9)
-#define IRQ_PC9         BFIN_PC_IRQ(9)
+#define IRQ_PC10                BFIN_PC_IRQ(10)
-#define IRQ_PC10        BFIN_PC_IRQ(10)
+#define IRQ_PC11                BFIN_PC_IRQ(11)
-#define IRQ_PC11        BFIN_PC_IRQ(11)
+#define IRQ_PC12                BFIN_PC_IRQ(12)
-#define IRQ_PC12        BFIN_PC_IRQ(12)
+#define IRQ_PC13                BFIN_PC_IRQ(13)
-#define IRQ_PC13        BFIN_PC_IRQ(13)
+#define IRQ_PC14                BFIN_PC_IRQ(14)         /* N/A */
-#define IRQ_PC14        BFIN_PC_IRQ(14)         /* N/A */
+#define IRQ_PC15                BFIN_PC_IRQ(15)         /* N/A */
-#define IRQ_PC15        BFIN_PC_IRQ(15)         /* N/A */
+#define BFIN_PD_IRQ(x)          ((x) + IRQ_PC15 + 1)
-#define BFIN_PD_IRQ(x)  ((x) + IRQ_PC15 + 1)
+#define IRQ_PD0                 BFIN_PD_IRQ(0)
-#define IRQ_PD0         BFIN_PD_IRQ(0)
+#define IRQ_PD1                 BFIN_PD_IRQ(1)
-#define IRQ_PD1         BFIN_PD_IRQ(1)
+#define IRQ_PD2                 BFIN_PD_IRQ(2)
-#define IRQ_PD2         BFIN_PD_IRQ(2)
+#define IRQ_PD3                 BFIN_PD_IRQ(3)
-#define IRQ_PD3         BFIN_PD_IRQ(3)
+#define IRQ_PD4                 BFIN_PD_IRQ(4)
-#define IRQ_PD4         BFIN_PD_IRQ(4)
+#define IRQ_PD5                 BFIN_PD_IRQ(5)
-#define IRQ_PD5         BFIN_PD_IRQ(5)
+#define IRQ_PD6                 BFIN_PD_IRQ(6)
-#define IRQ_PD6         BFIN_PD_IRQ(6)
+#define IRQ_PD7                 BFIN_PD_IRQ(7)
-#define IRQ_PD7         BFIN_PD_IRQ(7)
+#define IRQ_PD8                 BFIN_PD_IRQ(8)
-#define IRQ_PD8         BFIN_PD_IRQ(8)
+#define IRQ_PD9                 BFIN_PD_IRQ(9)
-#define IRQ_PD9         BFIN_PD_IRQ(9)
+#define IRQ_PD10                BFIN_PD_IRQ(10)
-#define IRQ_PD10        BFIN_PD_IRQ(10)
+#define IRQ_PD11                BFIN_PD_IRQ(11)
-#define IRQ_PD11        BFIN_PD_IRQ(11)
+#define IRQ_PD12                BFIN_PD_IRQ(12)
-#define IRQ_PD12        BFIN_PD_IRQ(12)
+#define IRQ_PD13                BFIN_PD_IRQ(13)
-#define IRQ_PD13        BFIN_PD_IRQ(13)
+#define IRQ_PD14                BFIN_PD_IRQ(14)
-#define IRQ_PD14        BFIN_PD_IRQ(14)
+#define IRQ_PD15                BFIN_PD_IRQ(15)
-#define IRQ_PD15        BFIN_PD_IRQ(15)
+#define BFIN_PE_IRQ(x)          ((x) + IRQ_PD15 + 1)
-#define BFIN_PE_IRQ(x)  ((x) + IRQ_PD15 + 1)
+#define IRQ_PE0                 BFIN_PE_IRQ(0)
-#define IRQ_PE0         BFIN_PE_IRQ(0)
+#define IRQ_PE1                 BFIN_PE_IRQ(1)
-#define IRQ_PE1         BFIN_PE_IRQ(1)
+#define IRQ_PE2                 BFIN_PE_IRQ(2)
-#define IRQ_PE2         BFIN_PE_IRQ(2)
+#define IRQ_PE3                 BFIN_PE_IRQ(3)
-#define IRQ_PE3         BFIN_PE_IRQ(3)
+#define IRQ_PE4                 BFIN_PE_IRQ(4)
-#define IRQ_PE4         BFIN_PE_IRQ(4)
+#define IRQ_PE5                 BFIN_PE_IRQ(5)
-#define IRQ_PE5         BFIN_PE_IRQ(5)
+#define IRQ_PE6                 BFIN_PE_IRQ(6)
-#define IRQ_PE6         BFIN_PE_IRQ(6)
+#define IRQ_PE7                 BFIN_PE_IRQ(7)
-#define IRQ_PE7         BFIN_PE_IRQ(7)
+#define IRQ_PE8                 BFIN_PE_IRQ(8)
-#define IRQ_PE8         BFIN_PE_IRQ(8)
+#define IRQ_PE9                 BFIN_PE_IRQ(9)
-#define IRQ_PE9         BFIN_PE_IRQ(9)
+#define IRQ_PE10                BFIN_PE_IRQ(10)
-#define IRQ_PE10        BFIN_PE_IRQ(10)
+#define IRQ_PE11                BFIN_PE_IRQ(11)
-#define IRQ_PE11        BFIN_PE_IRQ(11)
+#define IRQ_PE12                BFIN_PE_IRQ(12)
-#define IRQ_PE12        BFIN_PE_IRQ(12)
+#define IRQ_PE13                BFIN_PE_IRQ(13)
-#define IRQ_PE13        BFIN_PE_IRQ(13)
+#define IRQ_PE14                BFIN_PE_IRQ(14)
-#define IRQ_PE14        BFIN_PE_IRQ(14)
+#define IRQ_PE15                BFIN_PE_IRQ(15)
-#define IRQ_PE15        BFIN_PE_IRQ(15)
+#define BFIN_PF_IRQ(x)          ((x) + IRQ_PE15 + 1)
-#define BFIN_PF_IRQ(x)  ((x) + IRQ_PE15 + 1)
+#define IRQ_PF0                 BFIN_PF_IRQ(0)
-#define IRQ_PF0         BFIN_PF_IRQ(0)
+#define IRQ_PF1                 BFIN_PF_IRQ(1)
-#define IRQ_PF1         BFIN_PF_IRQ(1)
+#define IRQ_PF2                 BFIN_PF_IRQ(2)
-#define IRQ_PF2         BFIN_PF_IRQ(2)
+#define IRQ_PF3                 BFIN_PF_IRQ(3)
-#define IRQ_PF3         BFIN_PF_IRQ(3)
+#define IRQ_PF4                 BFIN_PF_IRQ(4)
-#define IRQ_PF4         BFIN_PF_IRQ(4)
+#define IRQ_PF5                 BFIN_PF_IRQ(5)
-#define IRQ_PF5         BFIN_PF_IRQ(5)
+#define IRQ_PF6                 BFIN_PF_IRQ(6)
-#define IRQ_PF6         BFIN_PF_IRQ(6)
+#define IRQ_PF7                 BFIN_PF_IRQ(7)
-#define IRQ_PF7         BFIN_PF_IRQ(7)
+#define IRQ_PF8                 BFIN_PF_IRQ(8)
-#define IRQ_PF8         BFIN_PF_IRQ(8)
+#define IRQ_PF9                 BFIN_PF_IRQ(9)
-#define IRQ_PF9         BFIN_PF_IRQ(9)
+#define IRQ_PF10                BFIN_PF_IRQ(10)
-#define IRQ_PF10        BFIN_PF_IRQ(10)
+#define IRQ_PF11                BFIN_PF_IRQ(11)
-#define IRQ_PF11        BFIN_PF_IRQ(11)
+#define IRQ_PF12                BFIN_PF_IRQ(12)
-#define IRQ_PF12        BFIN_PF_IRQ(12)
+#define IRQ_PF13                BFIN_PF_IRQ(13)
-#define IRQ_PF13        BFIN_PF_IRQ(13)
+#define IRQ_PF14                BFIN_PF_IRQ(14)
-#define IRQ_PF14        BFIN_PF_IRQ(14)
+#define IRQ_PF15                BFIN_PF_IRQ(15)
-#define IRQ_PF15        BFIN_PF_IRQ(15)
+#define BFIN_PG_IRQ(x)          ((x) + IRQ_PF15 + 1)
-#define BFIN_PG_IRQ(x)  ((x) + IRQ_PF15 + 1)
+#define IRQ_PG0                 BFIN_PG_IRQ(0)
-#define IRQ_PG0         BFIN_PG_IRQ(0)
+#define IRQ_PG1                 BFIN_PG_IRQ(1)
-#define IRQ_PG1         BFIN_PG_IRQ(1)
+#define IRQ_PG2                 BFIN_PG_IRQ(2)
-#define IRQ_PG2         BFIN_PG_IRQ(2)
+#define IRQ_PG3                 BFIN_PG_IRQ(3)
-#define IRQ_PG3         BFIN_PG_IRQ(3)
+#define IRQ_PG4                 BFIN_PG_IRQ(4)
-#define IRQ_PG4         BFIN_PG_IRQ(4)
+#define IRQ_PG5                 BFIN_PG_IRQ(5)
-#define IRQ_PG5         BFIN_PG_IRQ(5)
+#define IRQ_PG6                 BFIN_PG_IRQ(6)
-#define IRQ_PG6         BFIN_PG_IRQ(6)
+#define IRQ_PG7                 BFIN_PG_IRQ(7)
-#define IRQ_PG7         BFIN_PG_IRQ(7)
+#define IRQ_PG8                 BFIN_PG_IRQ(8)
-#define IRQ_PG8         BFIN_PG_IRQ(8)
+#define IRQ_PG9                 BFIN_PG_IRQ(9)
-#define IRQ_PG9         BFIN_PG_IRQ(9)
+#define IRQ_PG10                BFIN_PG_IRQ(10)
-#define IRQ_PG10        BFIN_PG_IRQ(10)
+#define IRQ_PG11                BFIN_PG_IRQ(11)
-#define IRQ_PG11        BFIN_PG_IRQ(11)
+#define IRQ_PG12                BFIN_PG_IRQ(12)
-#define IRQ_PG12        BFIN_PG_IRQ(12)
+#define IRQ_PG13                BFIN_PG_IRQ(13)
-#define IRQ_PG13        BFIN_PG_IRQ(13)
+#define IRQ_PG14                BFIN_PG_IRQ(14)
-#define IRQ_PG14        BFIN_PG_IRQ(14)
+#define IRQ_PG15                BFIN_PG_IRQ(15)
-#define IRQ_PG15        BFIN_PG_IRQ(15)
+#define BFIN_PH_IRQ(x)          ((x) + IRQ_PG15 + 1)
-#define BFIN_PH_IRQ(x)  ((x) + IRQ_PG15 + 1)
+#define IRQ_PH0                 BFIN_PH_IRQ(0)
-#define IRQ_PH0         BFIN_PH_IRQ(0)
+#define IRQ_PH1                 BFIN_PH_IRQ(1)
-#define IRQ_PH1         BFIN_PH_IRQ(1)
+#define IRQ_PH2                 BFIN_PH_IRQ(2)
-#define IRQ_PH2         BFIN_PH_IRQ(2)
+#define IRQ_PH3                 BFIN_PH_IRQ(3)
-#define IRQ_PH3         BFIN_PH_IRQ(3)
+#define IRQ_PH4                 BFIN_PH_IRQ(4)
-#define IRQ_PH4         BFIN_PH_IRQ(4)
+#define IRQ_PH5                 BFIN_PH_IRQ(5)
-#define IRQ_PH5         BFIN_PH_IRQ(5)
+#define IRQ_PH6                 BFIN_PH_IRQ(6)
-#define IRQ_PH6         BFIN_PH_IRQ(6)
+#define IRQ_PH7                 BFIN_PH_IRQ(7)
-#define IRQ_PH7         BFIN_PH_IRQ(7)
+#define IRQ_PH8                 BFIN_PH_IRQ(8)
-#define IRQ_PH8         BFIN_PH_IRQ(8)
+#define IRQ_PH9                 BFIN_PH_IRQ(9)
-#define IRQ_PH9         BFIN_PH_IRQ(9)
+#define IRQ_PH10                BFIN_PH_IRQ(10)
-#define IRQ_PH10        BFIN_PH_IRQ(10)
+#define IRQ_PH11                BFIN_PH_IRQ(11)
-#define IRQ_PH11        BFIN_PH_IRQ(11)
+#define IRQ_PH12                BFIN_PH_IRQ(12)
-#define IRQ_PH12        BFIN_PH_IRQ(12)
+#define IRQ_PH13                BFIN_PH_IRQ(13)
-#define IRQ_PH13        BFIN_PH_IRQ(13)
+#define IRQ_PH14                BFIN_PH_IRQ(14)         /* N/A */
-#define IRQ_PH14        BFIN_PH_IRQ(14)         /* N/A */
+#define IRQ_PH15                BFIN_PH_IRQ(15)         /* N/A */
-#define IRQ_PH15        BFIN_PH_IRQ(15)         /* N/A */
+#define BFIN_PI_IRQ(x)          ((x) + IRQ_PH15 + 1)
-#define BFIN_PI_IRQ(x)  ((x) + IRQ_PH15 + 1)
+#define IRQ_PI0                 BFIN_PI_IRQ(0)
-#define IRQ_PI0         BFIN_PI_IRQ(0)
+#define IRQ_PI1                 BFIN_PI_IRQ(1)
-#define IRQ_PI1         BFIN_PI_IRQ(1)
+#define IRQ_PI2                 BFIN_PI_IRQ(2)
-#define IRQ_PI2         BFIN_PI_IRQ(2)
+#define IRQ_PI3                 BFIN_PI_IRQ(3)
-#define IRQ_PI3         BFIN_PI_IRQ(3)
+#define IRQ_PI4                 BFIN_PI_IRQ(4)
-#define IRQ_PI4         BFIN_PI_IRQ(4)
+#define IRQ_PI5                 BFIN_PI_IRQ(5)
-#define IRQ_PI5         BFIN_PI_IRQ(5)
+#define IRQ_PI6                 BFIN_PI_IRQ(6)
-#define IRQ_PI6         BFIN_PI_IRQ(6)
+#define IRQ_PI7                 BFIN_PI_IRQ(7)
-#define IRQ_PI7         BFIN_PI_IRQ(7)
+#define IRQ_PI8                 BFIN_PI_IRQ(8)
-#define IRQ_PI8         BFIN_PI_IRQ(8)
+#define IRQ_PI9                 BFIN_PI_IRQ(9)
-#define IRQ_PI9         BFIN_PI_IRQ(9)
+#define IRQ_PI10                BFIN_PI_IRQ(10)
-#define IRQ_PI10        BFIN_PI_IRQ(10)
+#define IRQ_PI11                BFIN_PI_IRQ(11)
-#define IRQ_PI11        BFIN_PI_IRQ(11)
+#define IRQ_PI12                BFIN_PI_IRQ(12)
-#define IRQ_PI12        BFIN_PI_IRQ(12)
+#define IRQ_PI13                BFIN_PI_IRQ(13)
-#define IRQ_PI13        BFIN_PI_IRQ(13)
+#define IRQ_PI14                BFIN_PI_IRQ(14)
-#define IRQ_PI14        BFIN_PI_IRQ(14)
+#define IRQ_PI15                BFIN_PI_IRQ(15)
-#define IRQ_PI15        BFIN_PI_IRQ(15)
+#define BFIN_PJ_IRQ(x)          ((x) + IRQ_PI15 + 1)
-#define BFIN_PJ_IRQ(x)  ((x) + IRQ_PI15 + 1)
+#define IRQ_PJ0                 BFIN_PJ_IRQ(0)
-#define IRQ_PJ0         BFIN_PJ_IRQ(0)
+#define IRQ_PJ1                 BFIN_PJ_IRQ(1)
-#define IRQ_PJ1         BFIN_PJ_IRQ(1)
+#define IRQ_PJ2                 BFIN_PJ_IRQ(2)
-#define IRQ_PJ2         BFIN_PJ_IRQ(2)
+#define IRQ_PJ3                 BFIN_PJ_IRQ(3)
-#define IRQ_PJ3         BFIN_PJ_IRQ(3)
+#define IRQ_PJ4                 BFIN_PJ_IRQ(4)
-#define IRQ_PJ4         BFIN_PJ_IRQ(4)
+#define IRQ_PJ5                 BFIN_PJ_IRQ(5)
-#define IRQ_PJ5         BFIN_PJ_IRQ(5)
+#define IRQ_PJ6                 BFIN_PJ_IRQ(6)
-#define IRQ_PJ6         BFIN_PJ_IRQ(6)
+#define IRQ_PJ7                 BFIN_PJ_IRQ(7)
-#define IRQ_PJ7         BFIN_PJ_IRQ(7)
+#define IRQ_PJ8                 BFIN_PJ_IRQ(8)
-#define IRQ_PJ8         BFIN_PJ_IRQ(8)
+#define IRQ_PJ9                 BFIN_PJ_IRQ(9)
-#define IRQ_PJ9         BFIN_PJ_IRQ(9)
+#define IRQ_PJ10                BFIN_PJ_IRQ(10)
-#define IRQ_PJ10        BFIN_PJ_IRQ(10)
+#define IRQ_PJ11                BFIN_PJ_IRQ(11)
-#define IRQ_PJ11        BFIN_PJ_IRQ(11)
+#define IRQ_PJ12                BFIN_PJ_IRQ(12)
-#define IRQ_PJ12        BFIN_PJ_IRQ(12)
+#define IRQ_PJ13                BFIN_PJ_IRQ(13)
-#define IRQ_PJ13        BFIN_PJ_IRQ(13)
+#define IRQ_PJ14                BFIN_PJ_IRQ(14)         /* N/A */
-#define IRQ_PJ14        BFIN_PJ_IRQ(14)         /* N/A */
+#define IRQ_PJ15                BFIN_PJ_IRQ(15)         /* N/A */
-#define IRQ_PJ15        BFIN_PJ_IRQ(15)         /* N/A */
+#define GPIO_IRQ_BASE   IRQ_PA0
 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS     (IRQ_PJ15+1)
@@ -343,6 +344,34 @@ Events         (highest priority)  EMU         0
 #define NR_IRQS     (SYS_IRQS+1)
 #endif
+/* For compatibility reasons with existing code */
+#define IRQ_DMAC0_ERR           IRQ_DMAC0_ERROR
+#define IRQ_EPPI0_ERR           IRQ_EPPI0_ERROR
+#define IRQ_SPORT0_ERR          IRQ_SPORT0_ERROR
+#define IRQ_SPORT1_ERR          IRQ_SPORT1_ERROR
+#define IRQ_SPI0_ERR            IRQ_SPI0_ERROR
+#define IRQ_UART0_ERR           IRQ_UART0_ERROR
+#define IRQ_DMAC1_ERR           IRQ_DMAC1_ERROR
+#define IRQ_SPORT2_ERR          IRQ_SPORT2_ERROR
+#define IRQ_SPORT3_ERR          IRQ_SPORT3_ERROR
+#define IRQ_SPI1_ERR            IRQ_SPI1_ERROR
+#define IRQ_SPI2_ERR            IRQ_SPI2_ERROR
+#define IRQ_UART1_ERR           IRQ_UART1_ERROR
+#define IRQ_UART2_ERR           IRQ_UART2_ERROR
+#define IRQ_CAN0_ERR            IRQ_CAN0_ERROR
+#define IRQ_MXVR_ERR            IRQ_MXVR_ERROR
+#define IRQ_EPP1_ERR            IRQ_EPP1_ERROR
+#define IRQ_EPP2_ERR            IRQ_EPP2_ERROR
+#define IRQ_UART3_ERR           IRQ_UART3_ERROR
+#define IRQ_HOST_ERR            IRQ_HOST_ERROR
+#define IRQ_PIXC_ERR            IRQ_PIXC_ERROR
+#define IRQ_NFC_ERR             IRQ_NFC_ERROR
+#define IRQ_ATAPI_ERR           IRQ_ATAPI_ERROR
+#define IRQ_CAN1_ERR            IRQ_CAN1_ERROR
+#define IRQ_HS_DMA_ERR          IRQ_HS_DMA_ERROR
 #define IVG7            7
 #define IVG8            8
 #define IVG9            9
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
index 72d80e8a6e81..ec1597e31831 100644
--- a/include/asm-blackfin/mach-bf548/mem_map.h
+++ b/include/asm-blackfin/mach-bf548/mem_map.h
@@ -51,10 +51,10 @@
 /* Level 1 Memory */
 /* Memory Map for ADSP-BF548 processors */
-#ifdef CONFIG_BLKFIN_ICACHE
+#ifdef CONFIG_BFIN_ICACHE
-#define BLKFIN_ICACHESIZE       (16*1024)
+#define BFIN_ICACHESIZE (16*1024)
 #else
-#define BLKFIN_ICACHESIZE       (0*1024)
+#define BFIN_ICACHESIZE (0*1024)
 #endif
 #define L1_CODE_START       0xFFA00000
@@ -63,29 +63,29 @@
 #define L1_CODE_LENGTH      0xC000
-#ifdef CONFIG_BLKFIN_DCACHE
+#ifdef CONFIG_BFIN_DCACHE
-#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#ifdef CONFIG_BFIN_DCACHE_BANKA
 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 #define L1_DATA_B_LENGTH      0x8000
-#define BLKFIN_DCACHESIZE       (16*1024)
+#define BFIN_DCACHESIZE (16*1024)
-#define BLKFIN_DSUPBANKS        1
+#define BFIN_DSUPBANKS  1
 #else
 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BLKFIN_DCACHESIZE       (32*1024)
+#define BFIN_DCACHESIZE (32*1024)
-#define BLKFIN_DSUPBANKS        2
+#define BFIN_DSUPBANKS  2
 #endif
 #else
 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      0x8000
 #define L1_DATA_B_LENGTH      0x8000
-#define BLKFIN_DCACHESIZE       (0*1024)
+#define BFIN_DCACHESIZE (0*1024)
-#define BLKFIN_DSUPBANKS        0
+#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BLKFIN_DCACHE*/
+#endif /*CONFIG_BFIN_DCACHE*/
 /* Scratch Pad Memory */
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index f5b32d66517d..bed956456884 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -1,184 +1,256 @@
 /*
- * File:         include/asm-blackfin/mach-bf561/anomaly.h
+ * File: include/asm-blackfin/mach-bf561/anomaly.h
- * Based on:
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
 *
- * This program is free software; you can redistribute it and/or modify
+ * Copyright (C) 2004-2007 Analog Devices Inc.
- * it under the terms of the GNU General Public License as published by
+ * Licensed under the GPL-2 or later.
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */
 /* This file shoule be up to date with:
- *  - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List
+ *  - Revision N, March 28, 2007; ADSP-BF561 Silicon Anomaly List
 */
 #ifndef _MACH_ANOMALY_H_
 #define _MACH_ANOMALY_H_
-/* We do not support 0.1 or 0.4 silicon - sorry */
+/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
-#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4))
+#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
-#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4
+# error Kernel will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
 #endif
-/* Issues that are common to 0.5 and  0.3 silicon */
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
-#if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3))
+#define ANOMALY_05000074 (1)
-#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
+/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-                            slot1 and store of a P register in slot 2 is not
+#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-                            supported */
+/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */
-#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
+#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-                            updated at the same time. */
+/* Testset instructions restricted to 32-bit aligned memory locations */
-#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned
+#define ANOMALY_05000120 (1)
-                            memory locations */
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR
+#define ANOMALY_05000122 (1)
-                            registers */
+/* Erroneous exception when enabling cache */
-#define ANOMALY_05000127 /* Signbits instruction not functional under certain
+#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-                            conditions */
+/* Signbits instruction not functional under certain conditions */
-#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */
+#define ANOMALY_05000127 (1)
-#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
+/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
-                            upper bits */
+#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
-#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
+/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
-#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
+#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
-                            syncs */
+/* Stall in multi-unit DMA operations */
-#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz
+#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
-                            and higher devices */
+/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */
+#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */
+/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
+#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-                            functional */
+/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
+#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-                            shadow of a conditional branch */
+/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop
+#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-                            may cause bad instruction fetches */
+/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
+#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-                            external SPORT TX and RX clocks */
+/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */
+#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal
+/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-                            voltage regulator (VDDint) to increase */
+#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal
+/* IMDMA S1/D1 channel may stall */
-                            voltage regulator (VDDint) to decrease */
+#define ANOMALY_05000149 (1)
-#define ANOMALY_05000272 /* Certain data cache write through modes fail for
+/* DMA engine may lose data due to incorrect handshaking */
-                            VDDint <=0.9V */
+#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
-#define ANOMALY_05000274 /* Data cache write back to external synchronous memory
+/* DMA stalls when all three controllers read data from the same source */
-                            may be lost */
+#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
-#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */
+/* Execution stall when executing in L2 and doing external accesses */
-#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
+#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
-                            registers are interrupted */
+/* Frame Delay in SPORT Multichannel Mode */
+#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
+/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
+#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
+/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
+#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
+/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
+/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
+#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
+/* A read from external memory may return a wrong value with data cache enabled */
+#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
+/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
+#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
+/* DMEM_CONTROL<12> is not set on Reset */
+#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
+/* SPORT transmit data is not gated by external frame sync in certain conditions */
+#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
+/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
+#define ANOMALY_05000166 (1)
+/* Turning Serial Ports on with External Frame Syncs */
+#define ANOMALY_05000167 (1)
+/* SDRAM auto-refresh and subsequent Power Ups */
+#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
+/* DATA CPLB page miss can result in lost write-through cache data writes */
+#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
+/* Boot-ROM code modifies SICA_IWRx wakeup registers */
+#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
+/* DSPID register values incorrect */
+#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
+/* DMA vs Core accesses to external memory */
+#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
+/* Cache Fill Buffer Data lost */
+#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
+/* Overlapping Sequencer and Memory Stalls */
+#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
+/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
+#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
+/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
+#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
+/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
+#define ANOMALY_05000180 (1)
+/* Disabling the PPI resets the PPI configuration registers */
+#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
+/* IMDMA does not operate to full speed for 600MHz and higher devices */
+#define ANOMALY_05000182 (1)
+/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */
+#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
+/* PPI TX Mode with 2 External Frame Syncs */
+#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
+/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */
+#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
+/* IMDMA Corrupted Data after a Halt */
+#define ANOMALY_05000187 (1)
+/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
+#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
+/* False Protection Exceptions */
+#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
+/* PPI not functional at core voltage < 1Volt */
+#define ANOMALY_05000190 (1)
+/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
+#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
+/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
+#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
+/* Restarting SPORT in Specific Modes May Cause Data Corruption */
+#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
+/* Failing MMR Accesses When Stalled by Preceding Memory Read */
+#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
+/* Current DMA Address Shows Wrong Value During Carry Fix */
+#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
+/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
+#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
+/* Possible Infinite Stall with Specific Dual-DAG Situation */
+#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
+/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
+#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
+/* Specific sequence that can cause DMA error or DMA stopping */
+#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
+/* Recovery from "Brown-Out" Condition */
+#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
+/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
+#define ANOMALY_05000208 (1)
+/* Speed Path in Computational Unit Affects Certain Instructions */
+#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
+/* UART TX Interrupt Masked Erroneously */
+#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
+/* NMI Event at Boot Time Results in Unpredictable State */
+#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
+/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
+#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
+/* Incorrect Pulse-Width of UART Start Bit */
+#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
+/* Scratchpad Memory Bank Reads May Return Incorrect Data */
+#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
+/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
+#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
+/* UART STB Bit Incorrectly Affects Receiver Setting */
+#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
+/* SPORT data transmit lines are incorrectly driven in multichannel mode */
+#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
+/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
+#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
+/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
+#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
+/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
+/* TESTSET operation forces stall on the other core */
+#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
+/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
+#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
+/* Exception Not Generated for MMR Accesses in Reserved Region */
+#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
+/* Maximum External Clock Speed for Timers */
+#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
+#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
+/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
+#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
+/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
+#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
+/* ICPLB_STATUS MMR Register May Be Corrupted */
+#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
+/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
+#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
+/* Stores To Data Cache May Be Lost */
+#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
+/* Hardware Loop Corrupted When Taking an ICPLB Exception */
+#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
+/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
+#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
+/* IMDMA destination IRQ status must be read prior to using IMDMA */
+#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
+/* IMDMA may corrupt data under certain conditions */
+#define ANOMALY_05000267 (1)
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
+#define ANOMALY_05000269 (1)
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
+#define ANOMALY_05000270 (1)
+/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
+#define ANOMALY_05000272 (1)
+/* Data cache write back to external synchronous memory may be lost */
+#define ANOMALY_05000274 (1)
+/* PPI Timing and Sampling Information Updates */
+#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
+/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
+#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
+/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
+#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
+/* False Hardware Error Exception When ISR Context Is Not Restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
+/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
+#define ANOMALY_05000283 (1)
+/* A read will receive incorrect data under certain conditions */
+#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
+/* SPORTs May Receive Bad Data If FIFOs Fill Up */
+#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
+/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
+#define ANOMALY_05000301 (1)
+/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
+#define ANOMALY_05000302 (1)
+/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
+#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
+/* SCKELOW Bit Does Not Maintain State Through Hibernate */
+#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (1)
+/* PPI Is Level-Sensitive on First Transfer */
+#define ANOMALY_05000313 (1)
+/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
+#define ANOMALY_05000315 (1)
+/* PF2 Output Remains Asserted After SPI Master Boot */
+#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
+/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */
+#define ANOMALY_05000323 (1)
+/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */
+#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
+/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */
+#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
+/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */
+#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
+/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
+#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
-#endif /*  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000311 (0)
-#if  (defined(CONFIG_BF_REV_0_5))
-#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT
-                            mode with external clock */
-#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to
-                            using IMDMA */
 #endif
-#if  (defined(CONFIG_BF_REV_0_3))
-#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input)
-                            Mode with 0 Frame Syncs */
-#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
-#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through
-                            cache data writes */
-#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */
-#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
-#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
-                            accumulator saturation */
-#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
-                            Purpose TX or RX modes */
-#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
-                            registers */
-#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with
-                            External Frame Syncs */
-#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits
-                            (not a meaningful mode) */
-#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer
-                            Placement in Memory */
-#define ANOMALY_05000189 /* False Protection Exception */
-#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
-                            when polarity setting is changed */
-#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data
-                            corruption */
-#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding
-                            memory read */
-#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
-                            fix */
-#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
-                            inactive channels in certain conditions */
-#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG
-                            situation */
-#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
-                            allocate cache lines on reads only mode */
-#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA
-                            stopping */
-#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
-#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
-                            instructions */
-#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
-#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
-                            state */
-#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and
-                            Non-Cached On-Chip L2 Memory */
-#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
-#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
-                            data */
-#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
-                            Differences in certain Conditions */
-#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
-#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in
-                            multichannel mode */
-#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
-                            hardware reset */
-#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of
-                            Control causes failures */
-#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */
-#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
-                            (TDM) mode in certain conditions */
-#define ANOMALY_05000251 /* Exception not generated for MMR accesses in
-                            reserved region */
-#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
-#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12
-                            of the ICPLB Data registers differ */
-#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
-#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
-#define ANOMALY_05000262 /* Stores to data cache may be lost */
-#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB
-                            exception */
-#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second
-                            to last instruction in hardware loop */
-#define ANOMALY_05000276 /* Timing requirements change for External Frame
-                            Sync PPI Modes with non-zero PPI_DELAY */
-#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
-                            DMA system instability */
-#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
-                            not restored */
-#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed
-                            in a particular stage */
-#define ANOMALY_05000287 /* A read will receive incorrect data under certain
-                            conditions */
-#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
-#endif
-#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
index 96a5d3a47e45..17e1d5dcef02 100644
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -73,13 +73,13 @@
 */
-#define BLKFIN_ISUBBANKS        4
+#define BFIN_ISUBBANKS  4
-#define BLKFIN_IWAYS            4
+#define BFIN_IWAYS              4
-#define BLKFIN_ILINES           32
+#define BFIN_ILINES             32
-#define BLKFIN_DSUBBANKS        4
+#define BFIN_DSUBBANKS  4
-#define BLKFIN_DWAYS            2
+#define BFIN_DWAYS              2
-#define BLKFIN_DLINES           64
+#define BFIN_DLINES             64
 #define WAY0_L                  0x1
 #define WAY1_L                  0x2
@@ -230,93 +230,6 @@
 #define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
-#define MAX_VC  600000000
-#define MIN_VC  50000000
-/******************************* PLL Settings ********************************/
-#ifdef CONFIG_BFIN_KERNEL_CLOCK
-#if (CONFIG_VCO_MULT < 0)
-#error "VCO Multiplier is less than 0. Please select a different value"
-#endif
-#if (CONFIG_VCO_MULT == 0)
-#error "VCO Multiplier should be greater than 0. Please select a different value"
-#endif
-#ifndef CONFIG_CLKIN_HALF
-#define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
-#else
-#define CONFIG_VCO_HZ   ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
-#endif
-#ifndef CONFIG_PLL_BYPASS
-#define CONFIG_CCLK_HZ  (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
-#define CONFIG_SCLK_HZ  (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
-#else
-#define CONFIG_CCLK_HZ  CONFIG_CLKIN_HZ
-#define CONFIG_SCLK_HZ  CONFIG_CLKIN_HZ
-#endif
-#if (CONFIG_SCLK_DIV < 1)
-#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
-#endif
-#if (CONFIG_SCLK_DIV > 15)
-#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
-#endif
-#if (CONFIG_CCLK_DIV != 1)
-#if (CONFIG_CCLK_DIV != 2)
-#if (CONFIG_CCLK_DIV != 4)
-#if (CONFIG_CCLK_DIV != 8)
-#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
-#endif
-#endif
-#endif
-#endif
-#if (CONFIG_VCO_HZ > MAX_VC)
-#error "VCO selected is more than maximum value. Please change the VCO multipler"
-#endif
-#if (CONFIG_SCLK_HZ > 133000000)
-#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
-#endif
-#if (CONFIG_SCLK_HZ < 27000000)
-#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
-#endif
-#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
-#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
-#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
-#error "Please select sclk less than cclk"
-#endif
-#endif
-#endif
-#if (CONFIG_CCLK_DIV == 1)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
-#endif
-#if (CONFIG_CCLK_DIV == 2)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
-#endif
-#if (CONFIG_CCLK_DIV == 4)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
-#endif
-#if (CONFIG_CCLK_DIV == 8)
-#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
-#endif
-#ifndef CONFIG_CCLK_ACT_DIV
-#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
-#endif
-#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
-#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
-#endif
-#endif                          /* CONFIG_BFIN_KERNEL_CLOCK */
 #ifdef CONFIG_BF561
 #define CPU "BF561"
 #define CPUID 0x027bb000
@@ -326,83 +239,4 @@
 #define CPUID 0x0
 #endif
-#if (CONFIG_MEM_SIZE % 4)
-#error "SDRAM memory size must be a multiple of 4MB!"
-#endif
-#define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
-#define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
-#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
-/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
-#define ANOMALY_05000158_WORKAROUND             0x200
-#ifdef CONFIG_BLKFIN_WB         /*Write Back Policy */
-#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_DIRTY \
-                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#else                           /*Write Through */
-#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \
-                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#endif
-#define L1_DMEMORY       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
-#define SDRAM_DNON_CHBL  (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
-#define SDRAM_EBIU       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
-#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
-#define L2_MEMORY       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
-#define SIZE_1K 0x00000400      /* 1K */
-#define SIZE_4K 0x00001000      /* 4K */
-#define SIZE_1M 0x00100000      /* 1M */
-#define SIZE_4M 0x00400000      /* 4M */
-#define MAX_CPLBS (16 * 2)
-/*
-* Number of required data CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 16 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Data Memory
-* 1 for L2 Data Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-* 64 for ASYNC Memory
-*/
-#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 + 64) * 2)
-/*
-* Number of required instruction CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 12 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Instruction Memory
-* 1 for L2 Instruction Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-*/
-#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
-#if 0                           /* comment by mhfan */
-/* Event Vector Table Address */
-#define EVT_EMULATION_ADDR      0xffe02000
-#define EVT_RESET_ADDR          0xffe02004
-#define EVT_NMI_ADDR            0xffe02008
-#define EVT_EXCEPTION_ADDR      0xffe0200c
-#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
-#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
-#define EVT_TIMER_ADDR          0xffe02018
-#define EVT_IVG7_ADDR           0xffe0201c
-#define EVT_IVG8_ADDR           0xffe02020
-#define EVT_IVG9_ADDR           0xffe02024
-#define EVT_IVG10_ADDR          0xffe02028
-#define EVT_IVG11_ADDR          0xffe0202c
-#define EVT_IVG12_ADDR          0xffe02030
-#define EVT_IVG13_ADDR          0xffe02034
-#define EVT_IVG14_ADDR          0xffe02038
-#define EVT_IVG15_ADDR          0xffe0203c
-#define EVT_OVERRIDE_ADDR       0xffe02100
-#endif                          /* comment by mhfan */
 #endif                          /* __MACH_BF561_H__  */
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h
index 2537c845e8b0..562aee39895c 100644
--- a/include/asm-blackfin/mach-bf561/blackfin.h
+++ b/include/asm-blackfin/mach-bf561/blackfin.h
@@ -38,7 +38,7 @@
 #include "defBF561.h"
 #include "anomaly.h"
-#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
+#if !defined(__ASSEMBLY__)
 #include "cdefBF561.h"
 #endif
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index 73d4d65249cd..d667816486c0 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -31,11 +31,8 @@
 #ifndef _CDEF_BF561_H
 #define _CDEF_BF561_H
-/*
+#include <asm/blackfin.h>
-#if !defined(__ADSPBF561__)
-#warning cdefBF561.h should only be included for BF561 chip.
-#endif
-*/
 /* include all Core registers and bit definitions */
 #include "defBF561.h"
@@ -67,7 +64,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
        bfin_write32(SICA_IWR1, 0);
        bfin_write16(VR_CTL, val);
-        __builtin_bfin_ssync();
+        SSYNC();
        local_irq_save(flags);
        asm("IDLE;");
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 0f2dc6e6335b..bf7dc4e00065 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -120,6 +120,7 @@
 #define UART_GCTL               0xFFC00424      /* Global Control Register */
 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI0_REGBASE                    0xFFC00500
 #define SPI_CTL                         0xFFC00500      /* SPI Control Register */
 #define SPI_FLG                         0xFFC00504      /* SPI Flag register */
 #define SPI_STAT                        0xFFC00508      /* SPI Status register */
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
index a753ce720d74..12789927db3d 100644
--- a/include/asm-blackfin/mach-bf561/irq.h
+++ b/include/asm-blackfin/mach-bf561/irq.h
@@ -289,6 +289,8 @@
 #define IRQ_PF46                119
 #define IRQ_PF47                120
+#define GPIO_IRQ_BASE           IRQ_PF0
 #ifdef CONFIG_IRQCHIP_DEMUX_GPIO
 #define NR_IRQS                 (IRQ_PF47 + 1)
 #else
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h
index ebac9a8d838d..f7ac09cf2c3d 100644
--- a/include/asm-blackfin/mach-bf561/mem_map.h
+++ b/include/asm-blackfin/mach-bf561/mem_map.h
@@ -21,10 +21,10 @@
 /* Level 1 Memory */
-#ifdef CONFIG_BLKFIN_CACHE
+#ifdef CONFIG_BFIN_ICACHE
-#define BLKFIN_ICACHESIZE       (16*1024)
+#define BFIN_ICACHESIZE (16*1024)
 #else
-#define BLKFIN_ICACHESIZE       (0*1024)
+#define BFIN_ICACHESIZE (0*1024)
 #endif
 /* Memory Map for ADSP-BF561 processors */
@@ -36,29 +36,29 @@
 #define L1_CODE_LENGTH      0x4000
-#ifdef CONFIG_BLKFIN_DCACHE
+#ifdef CONFIG_BFIN_DCACHE
-#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#ifdef CONFIG_BFIN_DCACHE_BANKA
 #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 #define L1_DATA_B_LENGTH      0x8000
-#define BLKFIN_DCACHESIZE       (16*1024)
+#define BFIN_DCACHESIZE (16*1024)
-#define BLKFIN_DSUPBANKS        1
+#define BFIN_DSUPBANKS  1
 #else
 #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
 #define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BLKFIN_DCACHESIZE       (32*1024)
+#define BFIN_DCACHESIZE (32*1024)
-#define BLKFIN_DSUPBANKS        2
+#define BFIN_DSUPBANKS  2
 #endif
 #else
 #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
 #define L1_DATA_A_LENGTH      0x8000
 #define L1_DATA_B_LENGTH      0x8000
-#define BLKFIN_DCACHESIZE       (0*1024)
+#define BFIN_DCACHESIZE (0*1024)
-#define BLKFIN_DSUPBANKS        0
+#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BLKFIN_DCACHE*/
+#endif /*CONFIG_BFIN_DCACHE*/
 #endif
 /* Level 2 Memory */
diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h
index 10d11d5ffe23..132ad31665e3 100644
--- a/include/asm-blackfin/mach-bf561/portmux.h
+++ b/include/asm-blackfin/mach-bf561/portmux.h
@@ -81,7 +81,7 @@
 #define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PF1))
 #define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PF0))
 #define P_SPI0_MOSI     (P_DONTCARE)
-#define P_SPI0_MIS0     (P_DONTCARE)
+#define P_SPI0_MISO     (P_DONTCARE)
 #define P_SPI0_SCK      (P_DONTCARE)
 #endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
index 94ed381e5606..ede210eca4ec 100644
--- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -39,7 +39,7 @@
 #define bfin_read_SRAM_BASE_ADDRESS()        bfin_read32(SRAM_BASE_ADDRESS)
 #define bfin_write_SRAM_BASE_ADDRESS(val)    bfin_write32(SRAM_BASE_ADDRESS,val)
 #define bfin_read_DMEM_CONTROL()             bfin_read32(DMEM_CONTROL)
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
 extern void bfin_write_DMEM_CONTROL(unsigned int val);
 #else
 #define bfin_write_DMEM_CONTROL(val)         bfin_write32(DMEM_CONTROL,val)
@@ -129,7 +129,7 @@ extern void bfin_write_DMEM_CONTROL(unsigned int val);
 #define DTEST_DATA3            0xFFE0040C
 */
 #define bfin_read_IMEM_CONTROL()             bfin_read32(IMEM_CONTROL)
-#ifdef ANOMALY_05000125
+#if ANOMALY_05000125
 extern void bfin_write_IMEM_CONTROL(unsigned int val);
 #else
 #define bfin_write_IMEM_CONTROL(val)         bfin_write32(IMEM_CONTROL,val)
diff --git a/include/asm-blackfin/mach-common/clocks.h b/include/asm-blackfin/mach-common/clocks.h
new file mode 100644
index 000000000000..033bba92d61c
--- /dev/null
+++ b/include/asm-blackfin/mach-common/clocks.h
@@ -0,0 +1,70 @@
+/*
+ * File:         include/asm-blackfin/mach-common/clocks.h
+ * Based on:     include/asm-blackfin/mach-bf537/bf537.h
+ * Author:       Robin Getz <rgetz@blackfin.uclinux.org>
+ *
+ * Created:      25Jul07
+ * Description:  Common Clock definitions for various kernel files
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#ifndef _BFIN_CLOCKS_H
+#define _BFIN_CLOCKS_H
+#ifdef CONFIG_CCLK_DIV_1
+# define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
+# define CONFIG_CCLK_DIV 1
+#endif
+#ifdef CONFIG_CCLK_DIV_2
+# define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
+# define CONFIG_CCLK_DIV 2
+#endif
+#ifdef CONFIG_CCLK_DIV_4
+# define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
+# define CONFIG_CCLK_DIV 4
+#endif
+#ifdef CONFIG_CCLK_DIV_8
+# define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
+# define CONFIG_CCLK_DIV 8
+#endif
+#ifndef CONFIG_PLL_BYPASS
+# ifndef CONFIG_CLKIN_HALF
+#  define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
+# else
+#  define CONFIG_VCO_HZ   ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
+# endif
+# define CONFIG_CCLK_HZ  (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
+# define CONFIG_SCLK_HZ  (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
+#else
+# define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ)
+# define CONFIG_CCLK_HZ  (CONFIG_CLKIN_HZ)
+# define CONFIG_SCLK_HZ  (CONFIG_CLKIN_HZ)
+# define CONFIG_VCO_MULT 0
+#endif
+#endif
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
index be1ece8c0c27..c1d8c4a78fcf 100644
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -33,81 +33,77 @@
 #include <asm/mach/anomaly.h>
-/*#if !defined(__ADSPLPBLACKFIN__)
-#warning def_LPBlackfin.h should only be included for 532 compatible chips.
-#endif
-*/
 #define MK_BMSK_(x) (1<<x)
-#if defined(ANOMALY_05000198)
+#ifndef __ASSEMBLY__
-#define bfin_read8(addr) ({ unsigned char __v; \
-                __asm__ __volatile__ ("NOP;\n\t" \
-                        "%0 = b[%1] (z);\n\t" \
-                        : "=d"(__v) : "a"(addr)); \
-                __v; })
-#define bfin_read16(addr) ({ unsigned __v; \
-                       __asm__ __volatile__ ("NOP;\n\t"\
-                                                                "%0 = w[%1] (z);\n\t"\
-  : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
-#define bfin_read32(addr) ({ unsigned __v; \
-                      __asm__ __volatile__ ("NOP;\n\t"\
-                                            "%0 = [%1];\n\t"\
-  : "=d"(__v) : "a"(addr)); __v; })
-#define bfin_write8(addr, val) ({ \
-                __asm__ __volatile__ ("NOP;\n\t" \
-                        "b[%0] = %1;\n\t" \
-                        : : "a"(addr), "d"(val) : "memory");})
-#define bfin_write16(addr,val) ({\
+#include <linux/types.h>
-                      __asm__ __volatile__ ("NOP;\n\t"\
-                                            "w[%0] = %1;\n\t"\
-  : : "a"(addr) , "d"(val) : "memory");})
-#define bfin_write32(addr,val) ({\
-                      __asm__ __volatile__ ("NOP;\n\t"\
-                                            "[%0] = %1;\n\t"\
-  : : "a"(addr) , "d"(val) : "memory");})
+#if ANOMALY_05000198
+# define NOP_PAD_ANOMALY_05000198 "nop;"
 #else
+# define NOP_PAD_ANOMALY_05000198
-#define bfin_read8(addr) ({ unsigned char __v; \
-                __asm__ __volatile__ ( \
-                        "%0 = b[%1] (z);\n\t" \
-                        :"=d"(__v) : "a"(addr)); \
-                __v; })
-#define bfin_read16(addr) ({ unsigned __v; \
-                       __asm__ __volatile__ (\
-                                                                "%0 = w[%1] (z);\n\t"\
-  : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
-#define bfin_read32(addr) ({ unsigned __v; \
-                      __asm__ __volatile__ (\
-                                            "%0 = [%1];\n\t"\
-  : "=d"(__v) : "a"(addr)); __v; })
-#define bfin_write8(addr, val) ({ \
-                __asm__ __volatile__ ( \
-                        "b[%0] = %1; \n\t" \
-                        ::"a"(addr), "d"(val) : "memory");})
-#define bfin_write16(addr,val) ({\
-                      __asm__ __volatile__ (\
-                                            "w[%0] = %1;\n\t"\
-  : : "a"(addr) , "d"(val) : "memory");})
-#define bfin_write32(addr,val) ({\
-                      __asm__ __volatile__ (\
-                                            "[%0] = %1;\n\t"\
-  : : "a"(addr) , "d"(val) : "memory");})
 #endif
+#define bfin_read8(addr) ({ \
+        uint8_t __v; \
+        __asm__ __volatile__( \
+                NOP_PAD_ANOMALY_05000198 \
+                "%0 = b[%1] (z);" \
+                : "=d" (__v) \
+                : "a" (addr) \
+        ); \
+        __v; })
+#define bfin_read16(addr) ({ \
+        uint16_t __v; \
+        __asm__ __volatile__( \
+                NOP_PAD_ANOMALY_05000198 \
+                "%0 = w[%1] (z);" \
+                : "=d" (__v) \
+                : "a" (addr) \
+        ); \
+        __v; })
+#define bfin_read32(addr) ({ \
+        uint32_t __v; \
+        __asm__ __volatile__( \
+                NOP_PAD_ANOMALY_05000198 \
+                "%0 = [%1];" \
+                : "=d" (__v) \
+                : "a" (addr) \
+        ); \
+        __v; })
+#define bfin_write8(addr, val) \
+        __asm__ __volatile__( \
+                NOP_PAD_ANOMALY_05000198 \
+                "b[%0] = %1;" \
+                : \
+                : "a" (addr), "d" (val) \
+                : "memory" \
+        )
+#define bfin_write16(addr, val) \
+        __asm__ __volatile__( \
+                NOP_PAD_ANOMALY_05000198 \
+                "w[%0] = %1;" \
+                : \
+                : "a" (addr), "d" (val) \
+                : "memory" \
+        )
+#define bfin_write32(addr, val) \
+        __asm__ __volatile__( \
+                NOP_PAD_ANOMALY_05000198 \
+                "[%0] = %1;" \
+                : \
+                : "a" (addr), "d" (val) \
+                : "memory" \
+        )
+#endif /* __ASSEMBLY__ */
 /**************************************************
 * System Register Bits
 **************************************************/
@@ -643,6 +639,7 @@
 #define CPLB_USER_RD       0x00000004   /* 0=no read access, 1=read access
                                         * allowed (user mode)
                                         */
 #define PAGE_SIZE_1KB      0x00000000   /* 1 KB page size */
 #define PAGE_SIZE_4KB      0x00010000   /* 4 KB page size */
 #define PAGE_SIZE_1MB      0x00020000   /* 1 MB page size */
@@ -675,6 +672,8 @@
                                         */
 #define CPLB_WT            0x00004000   /* 0=write-back, 1=write-through */
+#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
 /* TBUFCTL Masks */
 #define TBUFPWR            0x0001
 #define TBUFEN             0x0002
diff --git a/include/asm-blackfin/pgtable.h b/include/asm-blackfin/pgtable.h
index 5a8f9e431c40..b11b114689c0 100644
--- a/include/asm-blackfin/pgtable.h
+++ b/include/asm-blackfin/pgtable.h
@@ -4,7 +4,7 @@
 #include <asm-generic/4level-fixup.h>
 #include <asm/page.h>
-#include <asm/cplb.h>
+#include <asm/mach-common/def_LPBlackfin.h>
 typedef pte_t *pte_addr_t;
 /*
diff --git a/include/asm-blackfin/reboot.h b/include/asm-blackfin/reboot.h
new file mode 100644
index 000000000000..6d448b5f5985
--- /dev/null
+++ b/include/asm-blackfin/reboot.h
@@ -0,0 +1,20 @@
+/*
+ * include/asm-blackfin/reboot.h - shutdown/reboot header
+ *
+ * Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+#ifndef __ASM_REBOOT_H__
+#define __ASM_REBOOT_H__
+/* optional board specific hooks */
+extern void native_machine_restart(char *cmd);
+extern void native_machine_halt(void);
+extern void native_machine_power_off(void);
+/* common reboot workarounds */
+extern void bfin_gpio_reset_spi0_ssel1(void);
+#endif
diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h
index 5e5f1a0566c0..2b3d47d0bbb6 100644
--- a/include/asm-blackfin/system.h
+++ b/include/asm-blackfin/system.h
@@ -36,6 +36,7 @@
 #include <linux/linkage.h>
 #include <linux/compiler.h>
+#include <asm/mach/anomaly.h>
 /*
 * Interrupt configuring macros.
@@ -43,53 +44,60 @@
 extern unsigned long irq_flags;
-#define local_irq_enable() do {         \
+#define local_irq_enable() \
-        __asm__ __volatile__ (          \
+        __asm__ __volatile__( \
-                "sti %0;"               \
+                "sti %0;" \
-                ::"d"(irq_flags));      \
+                : \
-} while (0)
+                : "d" (irq_flags) \
+        )
-#define local_irq_disable() do {        \
+#define local_irq_disable() \
-        int _tmp_dummy;                 \
+        do { \
-        __asm__ __volatile__ (          \
+                int __tmp_dummy; \
-                "cli %0;"               \
+                __asm__ __volatile__( \
-                :"=d" (_tmp_dummy):);   \
+                        "cli %0;" \
-} while (0)
+                        : "=d" (__tmp_dummy) \
+                ); \
+        } while (0)
-#if defined(ANOMALY_05000244) && defined (CONFIG_BLKFIN_CACHE)
+#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
-#define idle_with_irq_disabled() do {   \
+# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
-        __asm__ __volatile__ (          \
-                "nop; nop;\n"           \
-                ".align 8;\n"           \
-                "sti %0; idle;\n"       \
-                ::"d" (irq_flags));     \
-} while (0)
 #else
-#define idle_with_irq_disabled() do {   \
+# define NOP_PAD_ANOMALY_05000244
-        __asm__ __volatile__ (          \
-                ".align 8;\n"           \
-                "sti %0; idle;\n"       \
-                ::"d" (irq_flags));     \
-} while (0)
 #endif
+#define idle_with_irq_disabled() \
+        __asm__ __volatile__( \
+                NOP_PAD_ANOMALY_05000244 \
+                ".align 8;" \
+                "sti %0;" \
+                "idle;" \
+                : \
+                : "d" (irq_flags) \
+        )
 #ifdef CONFIG_DEBUG_HWERR
-#define __save_and_cli(x) do {                  \
+# define __save_and_cli(x) \
-        __asm__ __volatile__ (                  \
+        __asm__ __volatile__( \
-                "cli %0;\n\tsti %1;"            \
+                "cli %0;" \
-                :"=&d"(x): "d" (0x3F));         \
+                "sti %1;" \
-} while (0)
+                : "=&d" (x) \
+                : "d" (0x3F) \
+        )
 #else
-#define __save_and_cli(x) do {          \
+# define __save_and_cli(x) \
-        __asm__ __volatile__ (          \
+        __asm__ __volatile__( \
-                "cli %0;"               \
+                "cli %0;" \
-                :"=&d"(x):);            \
+                : "=&d" (x) \
-} while (0)
+        )
 #endif
-#define local_save_flags(x) asm volatile ("cli %0;"     \
+#define local_save_flags(x) \
-                                          "sti %0;"     \
+        __asm__ __volatile__( \
-                                          :"=d"(x):);
+                "cli %0;" \
+                "sti %0;" \
+                : "=d" (x) \
+        )
 #ifdef CONFIG_DEBUG_HWERR
 #define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0)
@@ -97,10 +105,11 @@ extern unsigned long irq_flags;
 #define irqs_enabled_from_flags(x) ((x) != 0x1f)
 #endif
-#define local_irq_restore(x) do {                       \
+#define local_irq_restore(x) \
-        if (irqs_enabled_from_flags(x))                 \
+        do { \
-                local_irq_enable ();                    \
+                if (irqs_enabled_from_flags(x)) \
-} while (0)
+                        local_irq_enable(); \
+        } while (0)
 /* For spinlocks etc */
 #define local_irq_save(x) __save_and_cli(x)
diff --git a/include/asm-blackfin/termbits.h b/include/asm-blackfin/termbits.h
index 4eac38de8ce1..f37feb7cf895 100644
--- a/include/asm-blackfin/termbits.h
+++ b/include/asm-blackfin/termbits.h
@@ -140,6 +140,7 @@ struct ktermios {
 #define HUPCL   0002000
 #define CLOCAL  0004000
 #define CBAUDEX 0010000
+#define BOTHER  0010000
 #define    B57600 0010001
 #define   B115200 0010002
 #define   B230400 0010003
@@ -155,10 +156,12 @@ struct ktermios {
 #define  B3000000 0010015
 #define  B3500000 0010016
 #define  B4000000 0010017
-#define CIBAUD    002003600000  /* input baud rate (not used) */
+#define CIBAUD    002003600000  /* input baud rate */
 #define CMSPAR    010000000000  /* mark or space (stick) parity */
 #define CRTSCTS   020000000000  /* flow control */
+#define IBSHIFT 16      /* Shift from CBAUD to CIBAUD */
 /* c_lflag bits */
 #define ISIG    0000001
 #define ICANON  0000002
diff --git a/include/asm-blackfin/termios.h b/include/asm-blackfin/termios.h
index 5c41478a51c6..e31fe859650b 100644
--- a/include/asm-blackfin/termios.h
+++ b/include/asm-blackfin/termios.h
@@ -98,8 +98,14 @@ struct termio {
        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
 })
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define user_termios_to_kernel_termios(k, u) \
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
+        copy_from_user(k, u, sizeof(struct termios2))
+#define kernel_termios_to_user_termios(u, k) \
+        copy_to_user(u, k, sizeof(struct termios2))
+#define user_termios_to_kernel_termios_1(k, u) \
+        copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios_1(u, k) \
+        copy_to_user(u, k, sizeof(struct termios))
 #endif                          /* __KERNEL__ */
diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h
index 9c2474c9a589..6313aace9d59 100644
--- a/include/asm-blackfin/trace.h
+++ b/include/asm-blackfin/trace.h
@@ -6,23 +6,46 @@
 #ifndef _BLACKFIN_TRACE_
 #define _BLACKFIN_TRACE_
+/* Normally, we use ON, but you can't turn on software expansion until
+ * interrupts subsystem is ready
+ */
+#define BFIN_TRACE_INIT ((CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION << 4) | 0x03)
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
+#define BFIN_TRACE_ON   (BFIN_TRACE_INIT | (CONFIG_DEBUG_BFIN_HWTRACE_EXPAND << 2))
+#else
+#define BFIN_TRACE_ON   (BFIN_TRACE_INIT)
+#endif
 #ifndef __ASSEMBLY__
+extern unsigned long trace_buff_offset;
+extern unsigned long software_trace_buff[];
 /* Trace Macros for C files */
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
 #define trace_buffer_save(x) \
-        do { \
+        do { \
-                (x) = bfin_read_TBUFCTL(); \
+                (x) = bfin_read_TBUFCTL(); \
-                bfin_write_TBUFCTL((x) & ~TBUFEN); \
+                bfin_write_TBUFCTL((x) & ~TBUFEN); \
-        } while (0)
+        } while (0)
 #define trace_buffer_restore(x) \
-        do { \
+        do { \
-                bfin_write_TBUFCTL((x));        \
+                bfin_write_TBUFCTL((x));        \
-        } while (0)
+        } while (0)
+#else /* DEBUG_BFIN_HWTRACE_ON */
+#define trace_buffer_save(x)
+#define trace_buffer_restore(x)
+#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
 #else
 /* Trace Macros for Assembly files */
+#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
 #define TRACE_BUFFER_START(preg, dreg) trace_buffer_start(preg, dreg)
 #define TRACE_BUFFER_STOP(preg, dreg)  trace_buffer_stop(preg, dreg)
@@ -32,12 +55,26 @@
        dreg = 0x1;                     \
        [preg] = dreg;
-#define trace_buffer_start(preg, dreg) \
+#define trace_buffer_start(preg, dreg)  \
        preg.L = LO(TBUFCTL);           \
        preg.H = HI(TBUFCTL);           \
-        dreg = 0x13;                    \
+        dreg = BFIN_TRACE_ON;           \
+        [preg] = dreg;
+#define trace_buffer_init(preg, dreg) \
+        preg.L = LO(TBUFCTL);         \
+        preg.H = HI(TBUFCTL);         \
+        dreg = BFIN_TRACE_INIT;       \
        [preg] = dreg;
+#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
+#define trace_buffer_stop(preg, dreg)
+#define trace_buffer_start(preg, dreg)
+#define trace_buffer_init(preg, dreg)
+#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
 #ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
 # define DEBUG_START_HWTRACE(preg, dreg) trace_buffer_start(preg, dreg)
 # define DEBUG_STOP_HWTRACE(preg, dreg) trace_buffer_stop(preg, dreg)