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-rw-r--r--drivers/gpu/drm/i915/i915_irq.c4
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c14
2 files changed, 14 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c5266355973b..4a457521d76e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1889,13 +1889,13 @@ static int ivybridge_irq_postinstall(struct drm_device *dev)
1889 DE_PIPEA_VBLANK_IVB); 1889 DE_PIPEA_VBLANK_IVB);
1890 POSTING_READ(DEIER); 1890 POSTING_READ(DEIER);
1891 1891
1892 dev_priv->gt_irq_mask = ~0; 1892 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1893 1893
1894 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1894 I915_WRITE(GTIIR, I915_READ(GTIIR));
1895 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1895 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1896 1896
1897 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT | 1897 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1898 GEN6_BLITTER_USER_INTERRUPT; 1898 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
1899 I915_WRITE(GTIER, render_irqs); 1899 I915_WRITE(GTIER, render_irqs);
1900 POSTING_READ(GTIER); 1900 POSTING_READ(GTIER);
1901 1901
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1df1694835a1..89a5e7f89d7a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -427,6 +427,9 @@ static int init_render_ring(struct intel_ring_buffer *ring)
427 if (INTEL_INFO(dev)->gen >= 6) 427 if (INTEL_INFO(dev)->gen >= 6)
428 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); 428 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
429 429
430 if (IS_IVYBRIDGE(dev))
431 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
432
430 return ret; 433 return ret;
431} 434}
432 435
@@ -814,7 +817,11 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
814 817
815 spin_lock_irqsave(&dev_priv->irq_lock, flags); 818 spin_lock_irqsave(&dev_priv->irq_lock, flags);
816 if (ring->irq_refcount++ == 0) { 819 if (ring->irq_refcount++ == 0) {
817 I915_WRITE_IMR(ring, ~ring->irq_enable_mask); 820 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
821 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
822 GEN6_RENDER_L3_PARITY_ERROR));
823 else
824 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
818 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; 825 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
819 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 826 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
820 POSTING_READ(GTIMR); 827 POSTING_READ(GTIMR);
@@ -833,7 +840,10 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
833 840
834 spin_lock_irqsave(&dev_priv->irq_lock, flags); 841 spin_lock_irqsave(&dev_priv->irq_lock, flags);
835 if (--ring->irq_refcount == 0) { 842 if (--ring->irq_refcount == 0) {
836 I915_WRITE_IMR(ring, ~0); 843 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
844 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
845 else
846 I915_WRITE_IMR(ring, ~0);
837 dev_priv->gt_irq_mask |= ring->irq_enable_mask; 847 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
838 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 848 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
839 POSTING_READ(GTIMR); 849 POSTING_READ(GTIMR);