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-rw-r--r--drivers/ide/ide-generic.c9
-rw-r--r--drivers/ide/legacy/ide-cs.c41
-rw-r--r--drivers/ide/pci/opti621.c221
-rw-r--r--drivers/ide/ppc/pmac.c60
-rw-r--r--drivers/macintosh/mediabay.c3
5 files changed, 101 insertions, 233 deletions
diff --git a/drivers/ide/ide-generic.c b/drivers/ide/ide-generic.c
index 9134488ac043..2d92214096ab 100644
--- a/drivers/ide/ide-generic.c
+++ b/drivers/ide/ide-generic.c
@@ -22,6 +22,10 @@
22 22
23#define DRV_NAME "ide_generic" 23#define DRV_NAME "ide_generic"
24 24
25static int probe_mask = 0x03;
26module_param(probe_mask, int, 0);
27MODULE_PARM_DESC(probe_mask, "probe mask for legacy ISA IDE ports");
28
25static ssize_t store_add(struct class *cls, const char *buf, size_t n) 29static ssize_t store_add(struct class *cls, const char *buf, size_t n)
26{ 30{
27 ide_hwif_t *hwif; 31 ide_hwif_t *hwif;
@@ -89,6 +93,9 @@ static int __init ide_generic_init(void)
89 u8 idx[MAX_HWIFS]; 93 u8 idx[MAX_HWIFS];
90 int i; 94 int i;
91 95
96 printk(KERN_INFO DRV_NAME ": please use \"probe_mask=0x3f\" module "
97 "parameter for probing all legacy ISA IDE ports\n");
98
92 for (i = 0; i < MAX_HWIFS; i++) { 99 for (i = 0; i < MAX_HWIFS; i++) {
93 ide_hwif_t *hwif; 100 ide_hwif_t *hwif;
94 unsigned long io_addr = ide_default_io_base(i); 101 unsigned long io_addr = ide_default_io_base(i);
@@ -96,7 +103,7 @@ static int __init ide_generic_init(void)
96 103
97 idx[i] = 0xff; 104 idx[i] = 0xff;
98 105
99 if (io_addr) { 106 if ((probe_mask & (1 << i)) && io_addr) {
100 if (!request_region(io_addr, 8, DRV_NAME)) { 107 if (!request_region(io_addr, 8, DRV_NAME)) {
101 printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX " 108 printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX "
102 "not free.\n", 109 "not free.\n",
diff --git a/drivers/ide/legacy/ide-cs.c b/drivers/ide/legacy/ide-cs.c
index aa2ea3deac85..f633b6b3c7f3 100644
--- a/drivers/ide/legacy/ide-cs.c
+++ b/drivers/ide/legacy/ide-cs.c
@@ -135,13 +135,17 @@ static void ide_detach(struct pcmcia_device *link)
135{ 135{
136 ide_info_t *info = link->priv; 136 ide_info_t *info = link->priv;
137 ide_hwif_t *hwif = info->hwif; 137 ide_hwif_t *hwif = info->hwif;
138 unsigned long data_addr, ctl_addr;
138 139
139 DEBUG(0, "ide_detach(0x%p)\n", link); 140 DEBUG(0, "ide_detach(0x%p)\n", link);
140 141
142 data_addr = hwif->io_ports.data_addr;
143 ctl_addr = hwif->io_ports.ctl_addr;
144
141 ide_release(link); 145 ide_release(link);
142 146
143 release_region(hwif->io_ports.ctl_addr, 1); 147 release_region(ctl_addr, 1);
144 release_region(hwif->io_ports.data_addr, 8); 148 release_region(data_addr, 8);
145 149
146 kfree(info); 150 kfree(info);
147} /* ide_detach */ 151} /* ide_detach */
@@ -194,6 +198,16 @@ static ide_hwif_t *idecs_register(unsigned long io, unsigned long ctl,
194 if (hwif->present) 198 if (hwif->present)
195 return hwif; 199 return hwif;
196 200
201 /* retry registration in case device is still spinning up */
202 for (i = 0; i < 10; i++) {
203 msleep(100);
204 ide_port_scan(hwif);
205 if (hwif->present)
206 return hwif;
207 }
208
209 return hwif;
210
197out_release: 211out_release:
198 release_region(ctl, 1); 212 release_region(ctl, 1);
199 release_region(io, 8); 213 release_region(io, 8);
@@ -222,7 +236,7 @@ static int ide_config(struct pcmcia_device *link)
222 cistpl_cftable_entry_t dflt; 236 cistpl_cftable_entry_t dflt;
223 } *stk = NULL; 237 } *stk = NULL;
224 cistpl_cftable_entry_t *cfg; 238 cistpl_cftable_entry_t *cfg;
225 int i, pass, last_ret = 0, last_fn = 0, is_kme = 0; 239 int pass, last_ret = 0, last_fn = 0, is_kme = 0;
226 unsigned long io_base, ctl_base; 240 unsigned long io_base, ctl_base;
227 ide_hwif_t *hwif; 241 ide_hwif_t *hwif;
228 242
@@ -319,30 +333,15 @@ static int ide_config(struct pcmcia_device *link)
319 if (is_kme) 333 if (is_kme)
320 outb(0x81, ctl_base+1); 334 outb(0x81, ctl_base+1);
321 335
322 /* retry registration in case device is still spinning up */ 336 hwif = idecs_register(io_base, ctl_base, link->irq.AssignedIRQ, link);
323 for (i = 0; i < 10; i++) { 337 if (hwif == NULL && link->io.NumPorts1 == 0x20) {
324 hwif = idecs_register(io_base, ctl_base, link->irq.AssignedIRQ, link);
325 if (hwif)
326 break;
327 if (link->io.NumPorts1 == 0x20) {
328 outb(0x02, ctl_base + 0x10); 338 outb(0x02, ctl_base + 0x10);
329 hwif = idecs_register(io_base + 0x10, ctl_base + 0x10, 339 hwif = idecs_register(io_base + 0x10, ctl_base + 0x10,
330 link->irq.AssignedIRQ, link); 340 link->irq.AssignedIRQ, link);
331 if (hwif) {
332 io_base += 0x10;
333 ctl_base += 0x10;
334 break;
335 }
336 }
337 msleep(100);
338 } 341 }
339 342
340 if (hwif == NULL) { 343 if (hwif == NULL)
341 printk(KERN_NOTICE "ide-cs: ide_register() at 0x%3lx & 0x%3lx"
342 ", irq %u failed\n", io_base, ctl_base,
343 link->irq.AssignedIRQ);
344 goto failed; 344 goto failed;
345 }
346 345
347 info->ndev = 1; 346 info->ndev = 1;
348 sprintf(info->node.dev_name, "hd%c", 'a' + hwif->index * 2); 347 sprintf(info->node.dev_name, "hd%c", 'a' + hwif->index * 2);
diff --git a/drivers/ide/pci/opti621.c b/drivers/ide/pci/opti621.c
index 6e99080497bf..725c80508d90 100644
--- a/drivers/ide/pci/opti621.c
+++ b/drivers/ide/pci/opti621.c
@@ -81,8 +81,6 @@
81 * 0.5 doesn't work. 81 * 0.5 doesn't work.
82 */ 82 */
83 83
84#define OPTI621_DEBUG /* define for debug messages */
85
86#include <linux/types.h> 84#include <linux/types.h>
87#include <linux/module.h> 85#include <linux/module.h>
88#include <linux/kernel.h> 86#include <linux/kernel.h>
@@ -92,28 +90,6 @@
92 90
93#include <asm/io.h> 91#include <asm/io.h>
94 92
95//#define OPTI621_MAX_PIO 3
96/* In fact, I do not have any PIO 4 drive
97 * (address: 25 ns, data: 70 ns, recovery: 35 ns),
98 * but OPTi 82C621 is programmable and it can do (minimal values):
99 * on 40MHz PCI bus (pulse 25 ns):
100 * address: 25 ns, data: 25 ns, recovery: 50 ns;
101 * on 20MHz PCI bus (pulse 50 ns):
102 * address: 50 ns, data: 50 ns, recovery: 100 ns.
103 */
104
105/* #define READ_PREFETCH 0 */
106/* Uncomment for disable read prefetch.
107 * There is some readprefetch capatibility in hdparm,
108 * but when I type hdparm -P 1 /dev/hda, I got errors
109 * and till reset drive is inaccessible.
110 * This (hw) read prefetch is safe on my drive.
111 */
112
113#ifndef READ_PREFETCH
114#define READ_PREFETCH 0x40 /* read prefetch is enabled */
115#endif /* else read prefetch is disabled */
116
117#define READ_REG 0 /* index of Read cycle timing register */ 93#define READ_REG 0 /* index of Read cycle timing register */
118#define WRITE_REG 1 /* index of Write cycle timing register */ 94#define WRITE_REG 1 /* index of Write cycle timing register */
119#define CNTRL_REG 3 /* index of Control register */ 95#define CNTRL_REG 3 /* index of Control register */
@@ -122,51 +98,8 @@
122 98
123static int reg_base; 99static int reg_base;
124 100
125#define PIO_NOT_EXIST 254
126#define PIO_DONT_KNOW 255
127
128static DEFINE_SPINLOCK(opti621_lock); 101static DEFINE_SPINLOCK(opti621_lock);
129 102
130/* there are stored pio numbers from other calls of opti621_set_pio_mode */
131static void compute_pios(ide_drive_t *drive, const u8 pio)
132/* Store values into drive->drive_data
133 * second_contr - 0 for primary controller, 1 for secondary
134 * slave_drive - 0 -> pio is for master, 1 -> pio is for slave
135 * pio - PIO mode for selected drive (for other we don't know)
136 */
137{
138 int d;
139 ide_hwif_t *hwif = HWIF(drive);
140
141 drive->drive_data = pio;
142
143 for (d = 0; d < 2; ++d) {
144 drive = &hwif->drives[d];
145 if (drive->present) {
146 if (drive->drive_data == PIO_DONT_KNOW)
147 drive->drive_data = ide_get_best_pio_mode(drive, 255, 3);
148#ifdef OPTI621_DEBUG
149 printk("%s: Selected PIO mode %d\n",
150 drive->name, drive->drive_data);
151#endif
152 } else {
153 drive->drive_data = PIO_NOT_EXIST;
154 }
155 }
156}
157
158static int cmpt_clk(int time, int bus_speed)
159/* Returns (rounded up) time in clocks for time in ns,
160 * with bus_speed in MHz.
161 * Example: bus_speed = 40 MHz, time = 80 ns
162 * 1000/40 = 25 ns (clk value),
163 * 80/25 = 3.2, rounded up to 4 (I hope ;-)).
164 * Use idebus=xx to select right frequency.
165 */
166{
167 return ((time*bus_speed+999)/1000);
168}
169
170/* Write value to register reg, base of register 103/* Write value to register reg, base of register
171 * is at reg_base (0x1f0 primary, 0x170 secondary, 104 * is at reg_base (0x1f0 primary, 0x170 secondary,
172 * if not changed by PCI configuration). 105 * if not changed by PCI configuration).
@@ -199,83 +132,29 @@ static u8 read_reg(int reg)
199 return ret; 132 return ret;
200} 133}
201 134
202typedef struct pio_clocks_s {
203 int address_time; /* Address setup (clocks) */
204 int data_time; /* Active/data pulse (clocks) */
205 int recovery_time; /* Recovery time (clocks) */
206} pio_clocks_t;
207
208static void compute_clocks(int pio, pio_clocks_t *clks)
209{
210 if (pio != PIO_NOT_EXIST) {
211 int adr_setup, data_pls;
212 int bus_speed = ide_pci_clk ? ide_pci_clk : system_bus_clock();
213
214 adr_setup = ide_pio_timings[pio].setup_time;
215 data_pls = ide_pio_timings[pio].active_time;
216 clks->address_time = cmpt_clk(adr_setup, bus_speed);
217 clks->data_time = cmpt_clk(data_pls, bus_speed);
218 clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time
219 - adr_setup-data_pls, bus_speed);
220 if (clks->address_time < 1)
221 clks->address_time = 1;
222 if (clks->address_time > 4)
223 clks->address_time = 4;
224 if (clks->data_time < 1)
225 clks->data_time = 1;
226 if (clks->data_time > 16)
227 clks->data_time = 16;
228 if (clks->recovery_time < 2)
229 clks->recovery_time = 2;
230 if (clks->recovery_time > 17)
231 clks->recovery_time = 17;
232 } else {
233 clks->address_time = 1;
234 clks->data_time = 1;
235 clks->recovery_time = 2;
236 /* minimal values */
237 }
238}
239
240static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio) 135static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
241{ 136{
242 /* primary and secondary drives share some registers, 137 ide_hwif_t *hwif = drive->hwif;
243 * so we have to program both drives 138 ide_drive_t *pair = ide_get_paired_drive(drive);
244 */
245 unsigned long flags; 139 unsigned long flags;
246 u8 pio1 = 0, pio2 = 0; 140 u8 tim, misc, addr_pio = pio, clk;
247 pio_clocks_t first, second; 141
248 int ax, drdy; 142 /* DRDY is default 2 (by OPTi Databook) */
249 u8 cycle1, cycle2, misc; 143 static const u8 addr_timings[2][5] = {
250 ide_hwif_t *hwif = HWIF(drive); 144 { 0x20, 0x10, 0x00, 0x00, 0x00 }, /* 33 MHz */
251 145 { 0x10, 0x10, 0x00, 0x00, 0x00 }, /* 25 MHz */
252 /* sets drive->drive_data for both drives */ 146 };
253 compute_pios(drive, pio); 147 static const u8 data_rec_timings[2][5] = {
254 pio1 = hwif->drives[0].drive_data; 148 { 0x5b, 0x45, 0x32, 0x21, 0x20 }, /* 33 MHz */
255 pio2 = hwif->drives[1].drive_data; 149 { 0x48, 0x34, 0x21, 0x10, 0x10 } /* 25 MHz */
256 150 };
257 compute_clocks(pio1, &first); 151
258 compute_clocks(pio2, &second); 152 drive->drive_data = XFER_PIO_0 + pio;
259 153
260 /* ax = max(a1,a2) */ 154 if (pair->present) {
261 ax = (first.address_time < second.address_time) ? second.address_time : first.address_time; 155 if (pair->drive_data && pair->drive_data < drive->drive_data)
262 156 addr_pio = pair->drive_data - XFER_PIO_0;
263 drdy = 2; /* DRDY is default 2 (by OPTi Databook) */ 157 }
264
265 cycle1 = ((first.data_time-1)<<4) | (first.recovery_time-2);
266 cycle2 = ((second.data_time-1)<<4) | (second.recovery_time-2);
267 misc = READ_PREFETCH | ((ax-1)<<4) | ((drdy-2)<<1);
268
269#ifdef OPTI621_DEBUG
270 printk("%s: master: address: %d, data: %d, "
271 "recovery: %d, drdy: %d [clk]\n",
272 hwif->name, ax, first.data_time,
273 first.recovery_time, drdy);
274 printk("%s: slave: address: %d, data: %d, "
275 "recovery: %d, drdy: %d [clk]\n",
276 hwif->name, ax, second.data_time,
277 second.recovery_time, drdy);
278#endif
279 158
280 spin_lock_irqsave(&opti621_lock, flags); 159 spin_lock_irqsave(&opti621_lock, flags);
281 160
@@ -289,24 +168,21 @@ static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
289 (void)inb(reg_base + CNTRL_REG); 168 (void)inb(reg_base + CNTRL_REG);
290 /* if reads 0xc0, no interface exist? */ 169 /* if reads 0xc0, no interface exist? */
291 read_reg(CNTRL_REG); 170 read_reg(CNTRL_REG);
292 /* read version, probably 0 */
293 read_reg(STRAP_REG);
294 171
295 /* program primary drive */ 172 /* check CLK speed */
296 /* select Index-0 for Register-A */ 173 clk = read_reg(STRAP_REG) & 1;
297 write_reg(0, MISC_REG); 174
298 /* set read cycle timings */ 175 printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33);
299 write_reg(cycle1, READ_REG);
300 /* set write cycle timings */
301 write_reg(cycle1, WRITE_REG);
302 176
303 /* program secondary drive */ 177 tim = data_rec_timings[clk][pio];
304 /* select Index-1 for Register-B */ 178 misc = addr_timings[clk][addr_pio];
305 write_reg(1, MISC_REG); 179
180 /* select Index-0/1 for Register-A/B */
181 write_reg(drive->select.b.unit, MISC_REG);
306 /* set read cycle timings */ 182 /* set read cycle timings */
307 write_reg(cycle2, READ_REG); 183 write_reg(tim, READ_REG);
308 /* set write cycle timings */ 184 /* set write cycle timings */
309 write_reg(cycle2, WRITE_REG); 185 write_reg(tim, WRITE_REG);
310 186
311 /* use Register-A for drive 0 */ 187 /* use Register-A for drive 0 */
312 /* use Register-B for drive 1 */ 188 /* use Register-B for drive 1 */
@@ -319,45 +195,26 @@ static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
319 spin_unlock_irqrestore(&opti621_lock, flags); 195 spin_unlock_irqrestore(&opti621_lock, flags);
320} 196}
321 197
322static void __devinit opti621_port_init_devs(ide_hwif_t *hwif)
323{
324 hwif->drives[0].drive_data = PIO_DONT_KNOW;
325 hwif->drives[1].drive_data = PIO_DONT_KNOW;
326}
327
328static const struct ide_port_ops opti621_port_ops = { 198static const struct ide_port_ops opti621_port_ops = {
329 .port_init_devs = opti621_port_init_devs,
330 .set_pio_mode = opti621_set_pio_mode, 199 .set_pio_mode = opti621_set_pio_mode,
331}; 200};
332 201
333static const struct ide_port_info opti621_chipsets[] __devinitdata = { 202static const struct ide_port_info opti621_chipset __devinitdata = {
334 { /* 0 */ 203 .name = "OPTI621/X",
335 .name = "OPTI621", 204 .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
336 .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} }, 205 .port_ops = &opti621_port_ops,
337 .port_ops = &opti621_port_ops, 206 .host_flags = IDE_HFLAG_NO_DMA,
338 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, 207 .pio_mask = ATA_PIO4,
339 .pio_mask = ATA_PIO3,
340 .swdma_mask = ATA_SWDMA2,
341 .mwdma_mask = ATA_MWDMA2,
342 }, { /* 1 */
343 .name = "OPTI621X",
344 .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
345 .port_ops = &opti621_port_ops,
346 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
347 .pio_mask = ATA_PIO3,
348 .swdma_mask = ATA_SWDMA2,
349 .mwdma_mask = ATA_MWDMA2,
350 }
351}; 208};
352 209
353static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id) 210static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
354{ 211{
355 return ide_setup_pci_device(dev, &opti621_chipsets[id->driver_data]); 212 return ide_setup_pci_device(dev, &opti621_chipset);
356} 213}
357 214
358static const struct pci_device_id opti621_pci_tbl[] = { 215static const struct pci_device_id opti621_pci_tbl[] = {
359 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 }, 216 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
360 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 }, 217 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 0 },
361 { 0, }, 218 { 0, },
362}; 219};
363MODULE_DEVICE_TABLE(pci, opti621_pci_tbl); 220MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);
diff --git a/drivers/ide/ppc/pmac.c b/drivers/ide/ppc/pmac.c
index 48aa019127bc..ba2d58727964 100644
--- a/drivers/ide/ppc/pmac.c
+++ b/drivers/ide/ppc/pmac.c
@@ -59,7 +59,6 @@ typedef struct pmac_ide_hwif {
59 int irq; 59 int irq;
60 int kind; 60 int kind;
61 int aapl_bus_id; 61 int aapl_bus_id;
62 unsigned cable_80 : 1;
63 unsigned mediabay : 1; 62 unsigned mediabay : 1;
64 unsigned broken_dma : 1; 63 unsigned broken_dma : 1;
65 unsigned broken_dma_warn : 1; 64 unsigned broken_dma_warn : 1;
@@ -918,10 +917,40 @@ pmac_ide_do_resume(ide_hwif_t *hwif)
918 return 0; 917 return 0;
919} 918}
920 919
920static u8 pmac_ide_cable_detect(ide_hwif_t *hwif)
921{
922 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)ide_get_hwifdata(hwif);
923 struct device_node *np = pmif->node;
924 const char *cable = of_get_property(np, "cable-type", NULL);
925
926 /* Get cable type from device-tree. */
927 if (cable && !strncmp(cable, "80-", 3))
928 return ATA_CBL_PATA80;
929
930 /*
931 * G5's seem to have incorrect cable type in device-tree.
932 * Let's assume they have a 80 conductor cable, this seem
933 * to be always the case unless the user mucked around.
934 */
935 if (of_device_is_compatible(np, "K2-UATA") ||
936 of_device_is_compatible(np, "shasta-ata"))
937 return ATA_CBL_PATA80;
938
939 return ATA_CBL_PATA40;
940}
941
921static const struct ide_port_ops pmac_ide_ata6_port_ops = { 942static const struct ide_port_ops pmac_ide_ata6_port_ops = {
922 .set_pio_mode = pmac_ide_set_pio_mode, 943 .set_pio_mode = pmac_ide_set_pio_mode,
923 .set_dma_mode = pmac_ide_set_dma_mode, 944 .set_dma_mode = pmac_ide_set_dma_mode,
924 .selectproc = pmac_ide_kauai_selectproc, 945 .selectproc = pmac_ide_kauai_selectproc,
946 .cable_detect = pmac_ide_cable_detect,
947};
948
949static const struct ide_port_ops pmac_ide_ata4_port_ops = {
950 .set_pio_mode = pmac_ide_set_pio_mode,
951 .set_dma_mode = pmac_ide_set_dma_mode,
952 .selectproc = pmac_ide_selectproc,
953 .cable_detect = pmac_ide_cable_detect,
925}; 954};
926 955
927static const struct ide_port_ops pmac_ide_port_ops = { 956static const struct ide_port_ops pmac_ide_port_ops = {
@@ -949,10 +978,7 @@ static const struct ide_port_info pmac_port_info = {
949 978
950/* 979/*
951 * Setup, register & probe an IDE channel driven by this driver, this is 980 * Setup, register & probe an IDE channel driven by this driver, this is
952 * called by one of the 2 probe functions (macio or PCI). Note that a channel 981 * called by one of the 2 probe functions (macio or PCI).
953 * that ends up beeing free of any device is not kept around by this driver
954 * (it is kept in 2.4). This introduce an interface numbering change on some
955 * rare machines unfortunately, but it's better this way.
956 */ 982 */
957static int __devinit 983static int __devinit
958pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw) 984pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
@@ -962,7 +988,6 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
962 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; 988 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
963 struct ide_port_info d = pmac_port_info; 989 struct ide_port_info d = pmac_port_info;
964 990
965 pmif->cable_80 = 0;
966 pmif->broken_dma = pmif->broken_dma_warn = 0; 991 pmif->broken_dma = pmif->broken_dma_warn = 0;
967 if (of_device_is_compatible(np, "shasta-ata")) { 992 if (of_device_is_compatible(np, "shasta-ata")) {
968 pmif->kind = controller_sh_ata6; 993 pmif->kind = controller_sh_ata6;
@@ -979,6 +1004,7 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
979 } else if (of_device_is_compatible(np, "keylargo-ata")) { 1004 } else if (of_device_is_compatible(np, "keylargo-ata")) {
980 if (strcmp(np->name, "ata-4") == 0) { 1005 if (strcmp(np->name, "ata-4") == 0) {
981 pmif->kind = controller_kl_ata4; 1006 pmif->kind = controller_kl_ata4;
1007 d.port_ops = &pmac_ide_ata4_port_ops;
982 d.udma_mask = ATA_UDMA4; 1008 d.udma_mask = ATA_UDMA4;
983 } else 1009 } else
984 pmif->kind = controller_kl_ata3; 1010 pmif->kind = controller_kl_ata3;
@@ -992,22 +1018,6 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
992 bidp = of_get_property(np, "AAPL,bus-id", NULL); 1018 bidp = of_get_property(np, "AAPL,bus-id", NULL);
993 pmif->aapl_bus_id = bidp ? *bidp : 0; 1019 pmif->aapl_bus_id = bidp ? *bidp : 0;
994 1020
995 /* Get cable type from device-tree */
996 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
997 || pmif->kind == controller_k2_ata6
998 || pmif->kind == controller_sh_ata6) {
999 const char* cable = of_get_property(np, "cable-type", NULL);
1000 if (cable && !strncmp(cable, "80-", 3))
1001 pmif->cable_80 = 1;
1002 }
1003 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1004 * they have a 80 conductor cable, this seem to be always the case unless
1005 * the user mucked around
1006 */
1007 if (of_device_is_compatible(np, "K2-UATA") ||
1008 of_device_is_compatible(np, "shasta-ata"))
1009 pmif->cable_80 = 1;
1010
1011 /* On Kauai-type controllers, we make sure the FCR is correct */ 1021 /* On Kauai-type controllers, we make sure the FCR is correct */
1012 if (pmif->kauai_fcr) 1022 if (pmif->kauai_fcr)
1013 writel(KAUAI_FCR_UATA_MAGIC | 1023 writel(KAUAI_FCR_UATA_MAGIC |
@@ -1053,7 +1063,6 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
1053 1063
1054 hwif->hwif_data = pmif; 1064 hwif->hwif_data = pmif;
1055 ide_init_port_hw(hwif, hw); 1065 ide_init_port_hw(hwif, hw);
1056 hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
1057 1066
1058 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n", 1067 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1059 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id, 1068 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
@@ -1070,11 +1079,6 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw)
1070 } 1079 }
1071 } 1080 }
1072 1081
1073#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1074 if (pmif->cable_80 == 0)
1075 d.udma_mask &= ATA_UDMA2;
1076#endif
1077
1078 idx[0] = hwif->index; 1082 idx[0] = hwif->index;
1079 1083
1080 ide_device_add(idx, &d); 1084 ide_device_add(idx, &d);
diff --git a/drivers/macintosh/mediabay.c b/drivers/macintosh/mediabay.c
index 82add26cc665..c34bdf852e32 100644
--- a/drivers/macintosh/mediabay.c
+++ b/drivers/macintosh/mediabay.c
@@ -556,7 +556,8 @@ static void media_bay_step(int i)
556 printk("mediabay %d, registering IDE...\n", i); 556 printk("mediabay %d, registering IDE...\n", i);
557 pmu_suspend(); 557 pmu_suspend();
558 ide_port_scan(bay->cd_port); 558 ide_port_scan(bay->cd_port);
559 bay->cd_index = bay->cd_port->index; 559 if (bay->cd_port->present)
560 bay->cd_index = bay->cd_port->index;
560 pmu_resume(); 561 pmu_resume();
561 } 562 }
562 if (bay->cd_index == -1) { 563 if (bay->cd_index == -1) {