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-rw-r--r--arch/blackfin/Kconfig61
-rw-r--r--arch/blackfin/Kconfig.debug11
-rw-r--r--arch/blackfin/include/asm/bfin-global.h6
-rw-r--r--arch/blackfin/include/asm/bug.h7
-rw-r--r--arch/blackfin/include/asm/cache.h2
-rw-r--r--arch/blackfin/include/asm/gpio.h22
-rw-r--r--arch/blackfin/include/asm/pgtable.h3
-rw-r--r--arch/blackfin/include/asm/pseudo_instructions.h18
-rw-r--r--arch/blackfin/include/asm/string.h113
-rw-r--r--arch/blackfin/include/asm/tlbflush.h1
-rw-r--r--arch/blackfin/include/asm/trace.h7
-rw-r--r--arch/blackfin/kernel/Makefile5
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c131
-rw-r--r--arch/blackfin/kernel/bfin_ksyms.c12
-rw-r--r--arch/blackfin/kernel/dumpstack.c174
-rw-r--r--arch/blackfin/kernel/exception.c45
-rw-r--r--arch/blackfin/kernel/kgdb.c2
-rw-r--r--arch/blackfin/kernel/pseudodbg.c191
-rw-r--r--arch/blackfin/kernel/setup.c4
-rw-r--r--arch/blackfin/kernel/sys_bfin.c23
-rw-r--r--arch/blackfin/kernel/trace.c981
-rw-r--r--arch/blackfin/kernel/traps.c900
-rw-r--r--arch/blackfin/lib/memset.S1
-rw-r--r--arch/blackfin/lib/strcmp.S43
-rw-r--r--arch/blackfin/lib/strcmp.c19
-rw-r--r--arch/blackfin/lib/strcpy.S35
-rw-r--r--arch/blackfin/lib/strcpy.c19
-rw-r--r--arch/blackfin/lib/strncmp.S52
-rw-r--r--arch/blackfin/lib/strncmp.c18
-rw-r--r--arch/blackfin/lib/strncpy.S85
-rw-r--r--arch/blackfin/lib/strncpy.c19
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c4
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c4
-rw-r--r--arch/blackfin/mach-bf527/boards/ezkit.c4
-rw-r--r--arch/blackfin/mach-bf537/boards/minotaur.c3
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h622
-rw-r--r--arch/blackfin/mach-bf537/include/mach/irq.h2
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h621
-rw-r--r--arch/blackfin/mach-bf548/boards/cm_bf548.c4
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c4
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h671
-rw-r--r--arch/blackfin/mach-bf561/boards/acvilon.c3
-rw-r--r--arch/blackfin/mach-common/ints-priority.c42
-rw-r--r--arch/blackfin/mach-common/pm.c24
-rw-r--r--arch/blackfin/mach-common/smp.c4
-rw-r--r--arch/blackfin/mm/init.c60
-rw-r--r--arch/blackfin/mm/isram-driver.c94
-rw-r--r--arch/blackfin/mm/sram-alloc.c3
48 files changed, 1938 insertions, 3241 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index c078849df7f9..f66294b4f9d2 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -348,7 +348,7 @@ config MEM_MT48LC16M16A2TG_75
348 348
349config MEM_MT48LC32M8A2_75 349config MEM_MT48LC32M8A2_75
350 bool 350 bool
351 depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) 351 depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
352 default y 352 default y
353 353
354config MEM_MT48LC8M32B2B5_7 354config MEM_MT48LC8M32B2B5_7
@@ -361,11 +361,6 @@ config MEM_MT48LC32M16A2TG_75
361 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP) 361 depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
362 default y 362 default y
363 363
364config MEM_MT48LC32M8A2_75
365 bool
366 depends on (BFIN518F_EZBRD)
367 default y
368
369config MEM_MT48H32M16LFCJ_75 364config MEM_MT48H32M16LFCJ_75
370 bool 365 bool
371 depends on (BFIN526_EZBRD) 366 depends on (BFIN526_EZBRD)
@@ -791,6 +786,34 @@ config MEMCPY_L1
791 If enabled, the memcpy function is linked 786 If enabled, the memcpy function is linked
792 into L1 instruction memory. (less latency) 787 into L1 instruction memory. (less latency)
793 788
789config STRCMP_L1
790 bool "locate strcmp function in L1 Memory"
791 default y
792 help
793 If enabled, the strcmp function is linked
794 into L1 instruction memory (less latency).
795
796config STRNCMP_L1
797 bool "locate strncmp function in L1 Memory"
798 default y
799 help
800 If enabled, the strncmp function is linked
801 into L1 instruction memory (less latency).
802
803config STRCPY_L1
804 bool "locate strcpy function in L1 Memory"
805 default y
806 help
807 If enabled, the strcpy function is linked
808 into L1 instruction memory (less latency).
809
810config STRNCPY_L1
811 bool "locate strncpy function in L1 Memory"
812 default y
813 help
814 If enabled, the strncpy function is linked
815 into L1 instruction memory (less latency).
816
794config SYS_BFIN_SPINLOCK_L1 817config SYS_BFIN_SPINLOCK_L1
795 bool "Locate sys_bfin_spinlock function in L1 Memory" 818 bool "Locate sys_bfin_spinlock function in L1 Memory"
796 default y 819 default y
@@ -1187,32 +1210,6 @@ config PM_BFIN_SLEEP
1187 If unsure, select "Sleep Deeper". 1210 If unsure, select "Sleep Deeper".
1188endchoice 1211endchoice
1189 1212
1190config PM_WAKEUP_BY_GPIO
1191 bool "Allow Wakeup from Standby by GPIO"
1192 depends on PM && !BF54x
1193
1194config PM_WAKEUP_GPIO_NUMBER
1195 int "GPIO number"
1196 range 0 47
1197 depends on PM_WAKEUP_BY_GPIO
1198 default 2
1199
1200choice
1201 prompt "GPIO Polarity"
1202 depends on PM_WAKEUP_BY_GPIO
1203 default PM_WAKEUP_GPIO_POLAR_H
1204config PM_WAKEUP_GPIO_POLAR_H
1205 bool "Active High"
1206config PM_WAKEUP_GPIO_POLAR_L
1207 bool "Active Low"
1208config PM_WAKEUP_GPIO_POLAR_EDGE_F
1209 bool "Falling EDGE"
1210config PM_WAKEUP_GPIO_POLAR_EDGE_R
1211 bool "Rising EDGE"
1212config PM_WAKEUP_GPIO_POLAR_EDGE_B
1213 bool "Both EDGE"
1214endchoice
1215
1216comment "Possible Suspend Mem / Hibernate Wake-Up Sources" 1213comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1217 depends on PM 1214 depends on PM
1218 1215
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index aec89a5280b2..d1825cb24768 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -238,7 +238,7 @@ config EARLY_PRINTK
238config NMI_WATCHDOG 238config NMI_WATCHDOG
239 bool "Enable NMI watchdog to help debugging lockup on SMP" 239 bool "Enable NMI watchdog to help debugging lockup on SMP"
240 default n 240 default n
241 depends on (SMP && !BFIN_SCRATCH_REG_RETN) 241 depends on SMP
242 help 242 help
243 If any CPU in the system does not execute the period local timer 243 If any CPU in the system does not execute the period local timer
244 interrupt for more than 5 seconds, then the NMI handler dumps debug 244 interrupt for more than 5 seconds, then the NMI handler dumps debug
@@ -264,4 +264,13 @@ config BFIN_ISRAM_SELF_TEST
264 help 264 help
265 Run some self tests of the isram driver code at boot. 265 Run some self tests of the isram driver code at boot.
266 266
267config BFIN_PSEUDODBG_INSNS
268 bool "Support pseudo debug instructions"
269 default n
270 help
271 This option allows the kernel to emulate some pseudo instructions which
272 allow simulator test cases to be run under Linux with no changes.
273
274 Most people should say N here.
275
267endmenu 276endmenu
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index e6485c305ea6..121cc04d877d 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -39,9 +39,15 @@ extern unsigned long sclk_to_usecs(unsigned long sclk);
39extern unsigned long usecs_to_sclk(unsigned long usecs); 39extern unsigned long usecs_to_sclk(unsigned long usecs);
40 40
41struct pt_regs; 41struct pt_regs;
42#if defined(CONFIG_DEBUG_VERBOSE)
42extern void dump_bfin_process(struct pt_regs *regs); 43extern void dump_bfin_process(struct pt_regs *regs);
43extern void dump_bfin_mem(struct pt_regs *regs); 44extern void dump_bfin_mem(struct pt_regs *regs);
44extern void dump_bfin_trace_buffer(void); 45extern void dump_bfin_trace_buffer(void);
46#else
47#define dump_bfin_process(regs)
48#define dump_bfin_mem(regs)
49#define dump_bfin_trace_buffer()
50#endif
45 51
46/* init functions only */ 52/* init functions only */
47extern int init_arch_irq(void); 53extern int init_arch_irq(void);
diff --git a/arch/blackfin/include/asm/bug.h b/arch/blackfin/include/asm/bug.h
index 75f6dc336d46..8d9b1eba89c4 100644
--- a/arch/blackfin/include/asm/bug.h
+++ b/arch/blackfin/include/asm/bug.h
@@ -9,7 +9,12 @@
9 9
10#ifdef CONFIG_BUG 10#ifdef CONFIG_BUG
11 11
12#define BFIN_BUG_OPCODE 0xefcd 12/*
13 * This can be any undefined 16-bit opcode, meaning
14 * ((opcode & 0xc000) != 0xc000)
15 * Anything from 0x0001 to 0x000A (inclusive) will work
16 */
17#define BFIN_BUG_OPCODE 0x0001
13 18
14#ifdef CONFIG_DEBUG_BUGVERBOSE 19#ifdef CONFIG_DEBUG_BUGVERBOSE
15 20
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
index 8542bc31f63c..93f6c634fdf4 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -15,6 +15,8 @@
15#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 15#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
16#define SMP_CACHE_BYTES L1_CACHE_BYTES 16#define SMP_CACHE_BYTES L1_CACHE_BYTES
17 17
18#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
19
18#ifdef CONFIG_SMP 20#ifdef CONFIG_SMP
19#define __cacheline_aligned 21#define __cacheline_aligned
20#else 22#else
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 91bd2d7b9d55..01b19d0cf509 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -167,23 +167,23 @@ int bfin_special_gpio_request(unsigned gpio, const char *label);
167#endif 167#endif
168 168
169#ifdef CONFIG_PM 169#ifdef CONFIG_PM
170int bfin_pm_standby_ctrl(unsigned ctrl);
170 171
171unsigned int bfin_pm_standby_setup(void); 172static inline int bfin_pm_standby_setup(void)
172void bfin_pm_standby_restore(void); 173{
174 return bfin_pm_standby_ctrl(1);
175}
176
177static inline void bfin_pm_standby_restore(void)
178{
179 bfin_pm_standby_ctrl(0);
180}
173 181
174void bfin_gpio_pm_hibernate_restore(void); 182void bfin_gpio_pm_hibernate_restore(void);
175void bfin_gpio_pm_hibernate_suspend(void); 183void bfin_gpio_pm_hibernate_suspend(void);
176 184
177#ifndef CONFIG_BF54x 185#ifndef CONFIG_BF54x
178#define PM_WAKE_RISING 0x1 186int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
179#define PM_WAKE_FALLING 0x2
180#define PM_WAKE_HIGH 0x4
181#define PM_WAKE_LOW 0x8
182#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING)
183#define PM_WAKE_IGNORE 0xF0
184
185int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
186void gpio_pm_wakeup_free(unsigned gpio);
187 187
188struct gpio_port_s { 188struct gpio_port_s {
189 unsigned short data; 189 unsigned short data;
diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h
index 821c699c2238..dcca3e6d6e80 100644
--- a/arch/blackfin/include/asm/pgtable.h
+++ b/arch/blackfin/include/asm/pgtable.h
@@ -80,7 +80,8 @@ PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
80 * ZERO_PAGE is a global shared page that is always zero: used 80 * ZERO_PAGE is a global shared page that is always zero: used
81 * for zero-mapped memory areas etc.. 81 * for zero-mapped memory areas etc..
82 */ 82 */
83#define ZERO_PAGE(vaddr) (virt_to_page(0)) 83#define ZERO_PAGE(vaddr) virt_to_page(empty_zero_page)
84extern char empty_zero_page[];
84 85
85extern unsigned int kobjsize(const void *objp); 86extern unsigned int kobjsize(const void *objp);
86 87
diff --git a/arch/blackfin/include/asm/pseudo_instructions.h b/arch/blackfin/include/asm/pseudo_instructions.h
new file mode 100644
index 000000000000..b00adfa08169
--- /dev/null
+++ b/arch/blackfin/include/asm/pseudo_instructions.h
@@ -0,0 +1,18 @@
1/*
2 * header file for pseudo instructions
3 *
4 * Copyright 2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef _BLACKFIN_PSEUDO_
10#define _BLACKFIN_PSEUDO_
11
12#include <linux/types.h>
13#include <asm/ptrace.h>
14
15extern bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode);
16extern bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode);
17
18#endif
diff --git a/arch/blackfin/include/asm/string.h b/arch/blackfin/include/asm/string.h
index d7f0ccb418c3..423c099aa988 100644
--- a/arch/blackfin/include/asm/string.h
+++ b/arch/blackfin/include/asm/string.h
@@ -12,121 +12,16 @@
12#ifdef __KERNEL__ /* only set these up for kernel code */ 12#ifdef __KERNEL__ /* only set these up for kernel code */
13 13
14#define __HAVE_ARCH_STRCPY 14#define __HAVE_ARCH_STRCPY
15extern inline char *strcpy(char *dest, const char *src) 15extern char *strcpy(char *dest, const char *src);
16{
17 char *xdest = dest;
18 char temp = 0;
19
20 __asm__ __volatile__ (
21 "1:"
22 "%2 = B [%1++] (Z);"
23 "B [%0++] = %2;"
24 "CC = %2;"
25 "if cc jump 1b (bp);"
26 : "+&a" (dest), "+&a" (src), "=&d" (temp)
27 :
28 : "memory", "CC");
29
30 return xdest;
31}
32 16
33#define __HAVE_ARCH_STRNCPY 17#define __HAVE_ARCH_STRNCPY
34extern inline char *strncpy(char *dest, const char *src, size_t n) 18extern char *strncpy(char *dest, const char *src, size_t n);
35{
36 char *xdest = dest;
37 char temp = 0;
38
39 if (n == 0)
40 return xdest;
41
42 __asm__ __volatile__ (
43 "1:"
44 "%3 = B [%1++] (Z);"
45 "B [%0++] = %3;"
46 "CC = %3;"
47 "if ! cc jump 2f;"
48 "%2 += -1;"
49 "CC = %2 == 0;"
50 "if ! cc jump 1b (bp);"
51 "jump 4f;"
52 "2:"
53 /* if src is shorter than n, we need to null pad bytes now */
54 "%3 = 0;"
55 "3:"
56 "%2 += -1;"
57 "CC = %2 == 0;"
58 "if cc jump 4f;"
59 "B [%0++] = %3;"
60 "jump 3b;"
61 "4:"
62 : "+&a" (dest), "+&a" (src), "+&da" (n), "=&d" (temp)
63 :
64 : "memory", "CC");
65
66 return xdest;
67}
68 19
69#define __HAVE_ARCH_STRCMP 20#define __HAVE_ARCH_STRCMP
70extern inline int strcmp(const char *cs, const char *ct) 21extern int strcmp(const char *cs, const char *ct);
71{
72 /* need to use int's here so the char's in the assembly don't get
73 * sign extended incorrectly when we don't want them to be
74 */
75 int __res1, __res2;
76
77 __asm__ __volatile__ (
78 "1:"
79 "%2 = B[%0++] (Z);" /* get *cs */
80 "%3 = B[%1++] (Z);" /* get *ct */
81 "CC = %2 == %3;" /* compare a byte */
82 "if ! cc jump 2f;" /* not equal, break out */
83 "CC = %2;" /* at end of cs? */
84 "if cc jump 1b (bp);" /* no, keep going */
85 "jump.s 3f;" /* strings are equal */
86 "2:"
87 "%2 = %2 - %3;" /* *cs - *ct */
88 "3:"
89 : "+&a" (cs), "+&a" (ct), "=&d" (__res1), "=&d" (__res2)
90 :
91 : "memory", "CC");
92
93 return __res1;
94}
95 22
96#define __HAVE_ARCH_STRNCMP 23#define __HAVE_ARCH_STRNCMP
97extern inline int strncmp(const char *cs, const char *ct, size_t count) 24extern int strncmp(const char *cs, const char *ct, size_t count);
98{
99 /* need to use int's here so the char's in the assembly don't get
100 * sign extended incorrectly when we don't want them to be
101 */
102 int __res1, __res2;
103
104 if (!count)
105 return 0;
106
107 __asm__ __volatile__ (
108 "1:"
109 "%3 = B[%0++] (Z);" /* get *cs */
110 "%4 = B[%1++] (Z);" /* get *ct */
111 "CC = %3 == %4;" /* compare a byte */
112 "if ! cc jump 3f;" /* not equal, break out */
113 "CC = %3;" /* at end of cs? */
114 "if ! cc jump 4f;" /* yes, all done */
115 "%2 += -1;" /* no, adjust count */
116 "CC = %2 == 0;"
117 "if ! cc jump 1b;" /* more to do, keep going */
118 "2:"
119 "%3 = 0;" /* strings are equal */
120 "jump.s 4f;"
121 "3:"
122 "%3 = %3 - %4;" /* *cs - *ct */
123 "4:"
124 : "+&a" (cs), "+&a" (ct), "+&da" (count), "=&d" (__res1), "=&d" (__res2)
125 :
126 : "memory", "CC");
127
128 return __res1;
129}
130 25
131#define __HAVE_ARCH_MEMSET 26#define __HAVE_ARCH_MEMSET
132extern void *memset(void *s, int c, size_t count); 27extern void *memset(void *s, int c, size_t count);
diff --git a/arch/blackfin/include/asm/tlbflush.h b/arch/blackfin/include/asm/tlbflush.h
index f1a06c006ed0..7c368682c0a3 100644
--- a/arch/blackfin/include/asm/tlbflush.h
+++ b/arch/blackfin/include/asm/tlbflush.h
@@ -1 +1,2 @@
1#include <asm-generic/tlbflush.h> 1#include <asm-generic/tlbflush.h>
2#define flush_tlb_kernel_range(s, e) do { } while (0)
diff --git a/arch/blackfin/include/asm/trace.h b/arch/blackfin/include/asm/trace.h
index dc0aa55ae773..33589a29b8d8 100644
--- a/arch/blackfin/include/asm/trace.h
+++ b/arch/blackfin/include/asm/trace.h
@@ -23,6 +23,13 @@
23#ifndef __ASSEMBLY__ 23#ifndef __ASSEMBLY__
24extern unsigned long trace_buff_offset; 24extern unsigned long trace_buff_offset;
25extern unsigned long software_trace_buff[]; 25extern unsigned long software_trace_buff[];
26#if defined(CONFIG_DEBUG_VERBOSE)
27extern void decode_address(char *buf, unsigned long address);
28extern bool get_instruction(unsigned int *val, unsigned short *address);
29#else
30static inline void decode_address(char *buf, unsigned long address) { }
31static inline bool get_instruction(unsigned int *val, unsigned short *address) { return false; }
32#endif
26 33
27/* Trace Macros for C files */ 34/* Trace Macros for C files */
28 35
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 346a421f1562..30d0d1f01dc7 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -7,7 +7,8 @@ extra-y := init_task.o vmlinux.lds
7obj-y := \ 7obj-y := \
8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ 8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
9 sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \ 9 sys_bfin.o traps.o irqchip.o dma-mapping.o flat.o \
10 fixed_code.o reboot.o bfin_gpio.o bfin_dma_5xx.o 10 fixed_code.o reboot.o bfin_gpio.o bfin_dma_5xx.o \
11 exception.o dumpstack.o
11 12
12ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y) 13ifeq ($(CONFIG_GENERIC_CLOCKEVENTS),y)
13 obj-y += time-ts.o 14 obj-y += time-ts.o
@@ -29,6 +30,8 @@ obj-$(CONFIG_NMI_WATCHDOG) += nmi.o
29obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 30obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
30obj-$(CONFIG_EARLY_PRINTK) += shadow_console.o 31obj-$(CONFIG_EARLY_PRINTK) += shadow_console.o
31obj-$(CONFIG_STACKTRACE) += stacktrace.o 32obj-$(CONFIG_STACKTRACE) += stacktrace.o
33obj-$(CONFIG_DEBUG_VERBOSE) += trace.o
34obj-$(CONFIG_BFIN_PSEUDODBG_INSNS) += pseudodbg.o
32 35
33# the kgdb test puts code into L2 and without linker 36# the kgdb test puts code into L2 and without linker
34# relaxation, we need to force long calls to/from it 37# relaxation, we need to force long calls to/from it
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index e35e20f00d9b..42833ee2b308 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -475,9 +475,7 @@ GET_GPIO_P(maskb)
475 475
476 476
477#ifdef CONFIG_PM 477#ifdef CONFIG_PM
478
479static unsigned short wakeup_map[GPIO_BANK_NUM]; 478static unsigned short wakeup_map[GPIO_BANK_NUM];
480static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
481 479
482static const unsigned int sic_iwr_irqs[] = { 480static const unsigned int sic_iwr_irqs[] = {
483#if defined(BF533_FAMILY) 481#if defined(BF533_FAMILY)
@@ -514,112 +512,26 @@ static const unsigned int sic_iwr_irqs[] = {
514************************************************************* 512*************************************************************
515* MODIFICATION HISTORY : 513* MODIFICATION HISTORY :
516**************************************************************/ 514**************************************************************/
517int gpio_pm_wakeup_request(unsigned gpio, unsigned char type) 515int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl)
518{
519 unsigned long flags;
520
521 if ((check_gpio(gpio) < 0) || !type)
522 return -EINVAL;
523
524 local_irq_save_hw(flags);
525 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
526 wakeup_flags_map[gpio] = type;
527 local_irq_restore_hw(flags);
528
529 return 0;
530}
531EXPORT_SYMBOL(gpio_pm_wakeup_request);
532
533void gpio_pm_wakeup_free(unsigned gpio)
534{ 516{
535 unsigned long flags; 517 unsigned long flags;
536 518
537 if (check_gpio(gpio) < 0) 519 if (check_gpio(gpio) < 0)
538 return; 520 return -EINVAL;
539 521
540 local_irq_save_hw(flags); 522 local_irq_save_hw(flags);
541 523 if (ctrl)
542 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); 524 wakeup_map[gpio_bank(gpio)] |= gpio_bit(gpio);
543
544 local_irq_restore_hw(flags);
545}
546EXPORT_SYMBOL(gpio_pm_wakeup_free);
547
548static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
549{
550 port_setup(gpio, GPIO_USAGE);
551 set_gpio_dir(gpio, 0);
552 set_gpio_inen(gpio, 1);
553
554 if (type & (PM_WAKE_RISING | PM_WAKE_FALLING))
555 set_gpio_edge(gpio, 1);
556 else
557 set_gpio_edge(gpio, 0);
558
559 if ((type & (PM_WAKE_BOTH_EDGES)) == (PM_WAKE_BOTH_EDGES))
560 set_gpio_both(gpio, 1);
561 else 525 else
562 set_gpio_both(gpio, 0); 526 wakeup_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
563
564 if ((type & (PM_WAKE_FALLING | PM_WAKE_LOW)))
565 set_gpio_polar(gpio, 1);
566 else
567 set_gpio_polar(gpio, 0);
568 527
569 SSYNC(); 528 set_gpio_maskb(gpio, ctrl);
570 529 local_irq_restore_hw(flags);
571 return 0;
572}
573
574u32 bfin_pm_standby_setup(void)
575{
576 u16 bank, mask, i, gpio;
577
578 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
579 mask = wakeup_map[gpio_bank(i)];
580 bank = gpio_bank(i);
581
582 gpio_bank_saved[bank].maskb = gpio_array[bank]->maskb;
583 gpio_array[bank]->maskb = 0;
584
585 if (mask) {
586#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x)
587 gpio_bank_saved[bank].fer = *port_fer[bank];
588#endif
589 gpio_bank_saved[bank].inen = gpio_array[bank]->inen;
590 gpio_bank_saved[bank].polar = gpio_array[bank]->polar;
591 gpio_bank_saved[bank].dir = gpio_array[bank]->dir;
592 gpio_bank_saved[bank].edge = gpio_array[bank]->edge;
593 gpio_bank_saved[bank].both = gpio_array[bank]->both;
594 gpio_bank_saved[bank].reserved =
595 reserved_gpio_map[bank];
596
597 gpio = i;
598
599 while (mask) {
600 if ((mask & 1) && (wakeup_flags_map[gpio] !=
601 PM_WAKE_IGNORE)) {
602 reserved_gpio_map[gpio_bank(gpio)] |=
603 gpio_bit(gpio);
604 bfin_gpio_wakeup_type(gpio,
605 wakeup_flags_map[gpio]);
606 set_gpio_data(gpio, 0); /*Clear*/
607 }
608 gpio++;
609 mask >>= 1;
610 }
611
612 bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
613 gpio_array[bank]->maskb_set = wakeup_map[gpio_bank(i)];
614 }
615 }
616
617 AWA_DUMMY_READ(maskb_set);
618 530
619 return 0; 531 return 0;
620} 532}
621 533
622void bfin_pm_standby_restore(void) 534int bfin_pm_standby_ctrl(unsigned ctrl)
623{ 535{
624 u16 bank, mask, i; 536 u16 bank, mask, i;
625 537
@@ -627,24 +539,10 @@ void bfin_pm_standby_restore(void)
627 mask = wakeup_map[gpio_bank(i)]; 539 mask = wakeup_map[gpio_bank(i)];
628 bank = gpio_bank(i); 540 bank = gpio_bank(i);
629 541
630 if (mask) { 542 if (mask)
631#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) 543 bfin_internal_set_wake(sic_iwr_irqs[bank], ctrl);
632 *port_fer[bank] = gpio_bank_saved[bank].fer;
633#endif
634 gpio_array[bank]->inen = gpio_bank_saved[bank].inen;
635 gpio_array[bank]->dir = gpio_bank_saved[bank].dir;
636 gpio_array[bank]->polar = gpio_bank_saved[bank].polar;
637 gpio_array[bank]->edge = gpio_bank_saved[bank].edge;
638 gpio_array[bank]->both = gpio_bank_saved[bank].both;
639
640 reserved_gpio_map[bank] =
641 gpio_bank_saved[bank].reserved;
642 bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
643 }
644
645 gpio_array[bank]->maskb = gpio_bank_saved[bank].maskb;
646 } 544 }
647 AWA_DUMMY_READ(maskb); 545 return 0;
648} 546}
649 547
650void bfin_gpio_pm_hibernate_suspend(void) 548void bfin_gpio_pm_hibernate_suspend(void)
@@ -708,16 +606,11 @@ void bfin_gpio_pm_hibernate_restore(void)
708#else /* CONFIG_BF54x */ 606#else /* CONFIG_BF54x */
709#ifdef CONFIG_PM 607#ifdef CONFIG_PM
710 608
711u32 bfin_pm_standby_setup(void) 609int bfin_pm_standby_ctrl(unsigned ctrl)
712{ 610{
713 return 0; 611 return 0;
714} 612}
715 613
716void bfin_pm_standby_restore(void)
717{
718
719}
720
721void bfin_gpio_pm_hibernate_suspend(void) 614void bfin_gpio_pm_hibernate_suspend(void)
722{ 615{
723 int i, bank; 616 int i, bank;
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
index ed8392c117ea..2c264b51566a 100644
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ b/arch/blackfin/kernel/bfin_ksyms.c
@@ -33,6 +33,18 @@ EXPORT_SYMBOL(memmove);
33EXPORT_SYMBOL(memchr); 33EXPORT_SYMBOL(memchr);
34 34
35/* 35/*
36 * Because string functions are both inline and exported functions and
37 * folder arch/blackfin/lib is configured as a library path in Makefile,
38 * symbols exported in folder lib is not linked into built-in.o but
39 * inlined only. In order to export string symbols to kernel module
40 * properly, they should be exported here.
41 */
42EXPORT_SYMBOL(strcpy);
43EXPORT_SYMBOL(strncpy);
44EXPORT_SYMBOL(strcmp);
45EXPORT_SYMBOL(strncmp);
46
47/*
36 * libgcc functions - functions that are used internally by the 48 * libgcc functions - functions that are used internally by the
37 * compiler... (prototypes are not correct though, but that 49 * compiler... (prototypes are not correct though, but that
38 * doesn't really matter since they're not versioned). 50 * doesn't really matter since they're not versioned).
diff --git a/arch/blackfin/kernel/dumpstack.c b/arch/blackfin/kernel/dumpstack.c
new file mode 100644
index 000000000000..5cfbaa298211
--- /dev/null
+++ b/arch/blackfin/kernel/dumpstack.c
@@ -0,0 +1,174 @@
1/* Provide basic stack dumping functions
2 *
3 * Copyright 2004-2009 Analog Devices Inc.
4 *
5 * Licensed under the GPL-2 or later
6 */
7
8#include <linux/kernel.h>
9#include <linux/thread_info.h>
10#include <linux/mm.h>
11#include <linux/uaccess.h>
12#include <linux/module.h>
13#include <asm/trace.h>
14
15/*
16 * Checks to see if the address pointed to is either a
17 * 16-bit CALL instruction, or a 32-bit CALL instruction
18 */
19static bool is_bfin_call(unsigned short *addr)
20{
21 unsigned int opcode;
22
23 if (!get_instruction(&opcode, addr))
24 return false;
25
26 if ((opcode >= 0x0060 && opcode <= 0x0067) ||
27 (opcode >= 0x0070 && opcode <= 0x0077) ||
28 (opcode >= 0xE3000000 && opcode <= 0xE3FFFFFF))
29 return true;
30
31 return false;
32
33}
34
35void show_stack(struct task_struct *task, unsigned long *stack)
36{
37#ifdef CONFIG_PRINTK
38 unsigned int *addr, *endstack, *fp = 0, *frame;
39 unsigned short *ins_addr;
40 char buf[150];
41 unsigned int i, j, ret_addr, frame_no = 0;
42
43 /*
44 * If we have been passed a specific stack, use that one otherwise
45 * if we have been passed a task structure, use that, otherwise
46 * use the stack of where the variable "stack" exists
47 */
48
49 if (stack == NULL) {
50 if (task) {
51 /* We know this is a kernel stack, so this is the start/end */
52 stack = (unsigned long *)task->thread.ksp;
53 endstack = (unsigned int *)(((unsigned int)(stack) & ~(THREAD_SIZE - 1)) + THREAD_SIZE);
54 } else {
55 /* print out the existing stack info */
56 stack = (unsigned long *)&stack;
57 endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
58 }
59 } else
60 endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
61
62 printk(KERN_NOTICE "Stack info:\n");
63 decode_address(buf, (unsigned int)stack);
64 printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf);
65
66 if (!access_ok(VERIFY_READ, stack, (unsigned int)endstack - (unsigned int)stack)) {
67 printk(KERN_NOTICE "Invalid stack pointer\n");
68 return;
69 }
70
71 /* First thing is to look for a frame pointer */
72 for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) {
73 if (*addr & 0x1)
74 continue;
75 ins_addr = (unsigned short *)*addr;
76 ins_addr--;
77 if (is_bfin_call(ins_addr))
78 fp = addr - 1;
79
80 if (fp) {
81 /* Let's check to see if it is a frame pointer */
82 while (fp >= (addr - 1) && fp < endstack
83 && fp && ((unsigned int) fp & 0x3) == 0)
84 fp = (unsigned int *)*fp;
85 if (fp == 0 || fp == endstack) {
86 fp = addr - 1;
87 break;
88 }
89 fp = 0;
90 }
91 }
92 if (fp) {
93 frame = fp;
94 printk(KERN_NOTICE " FP: (0x%p)\n", fp);
95 } else
96 frame = 0;
97
98 /*
99 * Now that we think we know where things are, we
100 * walk the stack again, this time printing things out
101 * incase there is no frame pointer, we still look for
102 * valid return addresses
103 */
104
105 /* First time print out data, next time, print out symbols */
106 for (j = 0; j <= 1; j++) {
107 if (j)
108 printk(KERN_NOTICE "Return addresses in stack:\n");
109 else
110 printk(KERN_NOTICE " Memory from 0x%08lx to %p", ((long unsigned int)stack & ~0xF), endstack);
111
112 fp = frame;
113 frame_no = 0;
114
115 for (addr = (unsigned int *)((unsigned int)stack & ~0xF), i = 0;
116 addr < endstack; addr++, i++) {
117
118 ret_addr = 0;
119 if (!j && i % 8 == 0)
120 printk(KERN_NOTICE "%p:", addr);
121
122 /* if it is an odd address, or zero, just skip it */
123 if (*addr & 0x1 || !*addr)
124 goto print;
125
126 ins_addr = (unsigned short *)*addr;
127
128 /* Go back one instruction, and see if it is a CALL */
129 ins_addr--;
130 ret_addr = is_bfin_call(ins_addr);
131 print:
132 if (!j && stack == (unsigned long *)addr)
133 printk("[%08x]", *addr);
134 else if (ret_addr)
135 if (j) {
136 decode_address(buf, (unsigned int)*addr);
137 if (frame == addr) {
138 printk(KERN_NOTICE " frame %2i : %s\n", frame_no, buf);
139 continue;
140 }
141 printk(KERN_NOTICE " address : %s\n", buf);
142 } else
143 printk("<%08x>", *addr);
144 else if (fp == addr) {
145 if (j)
146 frame = addr+1;
147 else
148 printk("(%08x)", *addr);
149
150 fp = (unsigned int *)*addr;
151 frame_no++;
152
153 } else if (!j)
154 printk(" %08x ", *addr);
155 }
156 if (!j)
157 printk("\n");
158 }
159#endif
160}
161EXPORT_SYMBOL(show_stack);
162
163void dump_stack(void)
164{
165 unsigned long stack;
166#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
167 int tflags;
168#endif
169 trace_buffer_save(tflags);
170 dump_bfin_trace_buffer();
171 show_stack(current, &stack);
172 trace_buffer_restore(tflags);
173}
174EXPORT_SYMBOL(dump_stack);
diff --git a/arch/blackfin/kernel/exception.c b/arch/blackfin/kernel/exception.c
new file mode 100644
index 000000000000..9208b5fd5186
--- /dev/null
+++ b/arch/blackfin/kernel/exception.c
@@ -0,0 +1,45 @@
1/* Basic functions for adding/removing custom exception handlers
2 *
3 * Copyright 2004-2009 Analog Devices Inc.
4 *
5 * Licensed under the GPL-2 or later
6 */
7
8#include <linux/module.h>
9#include <asm/irq_handler.h>
10
11int bfin_request_exception(unsigned int exception, void (*handler)(void))
12{
13 void (*curr_handler)(void);
14
15 if (exception > 0x3F)
16 return -EINVAL;
17
18 curr_handler = ex_table[exception];
19
20 if (curr_handler != ex_replaceable)
21 return -EBUSY;
22
23 ex_table[exception] = handler;
24
25 return 0;
26}
27EXPORT_SYMBOL(bfin_request_exception);
28
29int bfin_free_exception(unsigned int exception, void (*handler)(void))
30{
31 void (*curr_handler)(void);
32
33 if (exception > 0x3F)
34 return -EINVAL;
35
36 curr_handler = ex_table[exception];
37
38 if (curr_handler != handler)
39 return -EBUSY;
40
41 ex_table[exception] = ex_replaceable;
42
43 return 0;
44}
45EXPORT_SYMBOL(bfin_free_exception);
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
index 7367aea4ae59..08bc44ea6883 100644
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@@ -66,7 +66,7 @@ void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
66 gdb_regs[BFIN_RETN] = regs->retn; 66 gdb_regs[BFIN_RETN] = regs->retn;
67 gdb_regs[BFIN_RETE] = regs->rete; 67 gdb_regs[BFIN_RETE] = regs->rete;
68 gdb_regs[BFIN_PC] = regs->pc; 68 gdb_regs[BFIN_PC] = regs->pc;
69 gdb_regs[BFIN_CC] = 0; 69 gdb_regs[BFIN_CC] = (regs->astat >> 5) & 1;
70 gdb_regs[BFIN_EXTRA1] = 0; 70 gdb_regs[BFIN_EXTRA1] = 0;
71 gdb_regs[BFIN_EXTRA2] = 0; 71 gdb_regs[BFIN_EXTRA2] = 0;
72 gdb_regs[BFIN_EXTRA3] = 0; 72 gdb_regs[BFIN_EXTRA3] = 0;
diff --git a/arch/blackfin/kernel/pseudodbg.c b/arch/blackfin/kernel/pseudodbg.c
new file mode 100644
index 000000000000..db85bc94334e
--- /dev/null
+++ b/arch/blackfin/kernel/pseudodbg.c
@@ -0,0 +1,191 @@
1/* The fake debug assert instructions
2 *
3 * Copyright 2010 Analog Devices Inc.
4 *
5 * Licensed under the GPL-2 or later
6 */
7
8#include <linux/types.h>
9#include <linux/kernel.h>
10#include <linux/ptrace.h>
11
12const char * const greg_names[] = {
13 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
14 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP",
15 "I0", "I1", "I2", "I3", "M0", "M1", "M2", "M3",
16 "B0", "B1", "B2", "B3", "L0", "L1", "L2", "L3",
17 "A0.X", "A0.W", "A1.X", "A1.W", "<res>", "<res>", "ASTAT", "RETS",
18 "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>", "<res>",
19 "LC0", "LT0", "LB0", "LC1", "LT1", "LB1", "CYCLES", "CYCLES2",
20 "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", "RETE", "EMUDAT",
21};
22
23static const char *get_allreg_name(int grp, int reg)
24{
25 return greg_names[(grp << 3) | reg];
26}
27
28/*
29 * Unfortunately, the pt_regs structure is not laid out the same way as the
30 * hardware register file, so we need to do some fix ups.
31 *
32 * CYCLES is not stored in the pt_regs structure - so, we just read it from
33 * the hardware.
34 *
35 * Don't support:
36 * - All reserved registers
37 * - All in group 7 are (supervisors only)
38 */
39
40static bool fix_up_reg(struct pt_regs *fp, long *value, int grp, int reg)
41{
42 long *val = &fp->r0;
43 unsigned long tmp;
44
45 /* Only do Dregs and Pregs for now */
46 if (grp == 5 ||
47 (grp == 4 && (reg == 4 || reg == 5)) ||
48 (grp == 7))
49 return false;
50
51 if (grp == 0 || (grp == 1 && reg < 6))
52 val -= (reg + 8 * grp);
53 else if (grp == 1 && reg == 6)
54 val = &fp->usp;
55 else if (grp == 1 && reg == 7)
56 val = &fp->fp;
57 else if (grp == 2) {
58 val = &fp->i0;
59 val -= reg;
60 } else if (grp == 3 && reg >= 4) {
61 val = &fp->l0;
62 val -= (reg - 4);
63 } else if (grp == 3 && reg < 4) {
64 val = &fp->b0;
65 val -= reg;
66 } else if (grp == 4 && reg < 4) {
67 val = &fp->a0x;
68 val -= reg;
69 } else if (grp == 4 && reg == 6)
70 val = &fp->astat;
71 else if (grp == 4 && reg == 7)
72 val = &fp->rets;
73 else if (grp == 6 && reg < 6) {
74 val = &fp->lc0;
75 val -= reg;
76 } else if (grp == 6 && reg == 6) {
77 __asm__ __volatile__("%0 = cycles;\n" : "=d"(tmp));
78 val = &tmp;
79 } else if (grp == 6 && reg == 7) {
80 __asm__ __volatile__("%0 = cycles2;\n" : "=d"(tmp));
81 val = &tmp;
82 }
83
84 *value = *val;
85 return true;
86
87}
88
89#define PseudoDbg_Assert_opcode 0xf0000000
90#define PseudoDbg_Assert_expected_bits 0
91#define PseudoDbg_Assert_expected_mask 0xffff
92#define PseudoDbg_Assert_regtest_bits 16
93#define PseudoDbg_Assert_regtest_mask 0x7
94#define PseudoDbg_Assert_grp_bits 19
95#define PseudoDbg_Assert_grp_mask 0x7
96#define PseudoDbg_Assert_dbgop_bits 22
97#define PseudoDbg_Assert_dbgop_mask 0x3
98#define PseudoDbg_Assert_dontcare_bits 24
99#define PseudoDbg_Assert_dontcare_mask 0x7
100#define PseudoDbg_Assert_code_bits 27
101#define PseudoDbg_Assert_code_mask 0x1f
102
103/*
104 * DBGA - debug assert
105 */
106bool execute_pseudodbg_assert(struct pt_regs *fp, unsigned int opcode)
107{
108 int expected = ((opcode >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
109 int dbgop = ((opcode >> (PseudoDbg_Assert_dbgop_bits)) & PseudoDbg_Assert_dbgop_mask);
110 int grp = ((opcode >> (PseudoDbg_Assert_grp_bits)) & PseudoDbg_Assert_grp_mask);
111 int regtest = ((opcode >> (PseudoDbg_Assert_regtest_bits)) & PseudoDbg_Assert_regtest_mask);
112 long value;
113
114 if ((opcode & 0xFF000000) != PseudoDbg_Assert_opcode)
115 return false;
116
117 if (!fix_up_reg(fp, &value, grp, regtest))
118 return false;
119
120 if (dbgop == 0 || dbgop == 2) {
121 /* DBGA ( regs_lo , uimm16 ) */
122 /* DBGAL ( regs , uimm16 ) */
123 if (expected != (value & 0xFFFF)) {
124 pr_notice("DBGA (%s.L,0x%x) failure, got 0x%x\n",
125 get_allreg_name(grp, regtest),
126 expected, (unsigned int)(value & 0xFFFF));
127 return false;
128 }
129
130 } else if (dbgop == 1 || dbgop == 3) {
131 /* DBGA ( regs_hi , uimm16 ) */
132 /* DBGAH ( regs , uimm16 ) */
133 if (expected != ((value >> 16) & 0xFFFF)) {
134 pr_notice("DBGA (%s.H,0x%x) failure, got 0x%x\n",
135 get_allreg_name(grp, regtest),
136 expected, (unsigned int)((value >> 16) & 0xFFFF));
137 return false;
138 }
139 }
140
141 fp->pc += 4;
142 return true;
143}
144
145#define PseudoDbg_opcode 0xf8000000
146#define PseudoDbg_reg_bits 0
147#define PseudoDbg_reg_mask 0x7
148#define PseudoDbg_grp_bits 3
149#define PseudoDbg_grp_mask 0x7
150#define PseudoDbg_fn_bits 6
151#define PseudoDbg_fn_mask 0x3
152#define PseudoDbg_code_bits 8
153#define PseudoDbg_code_mask 0xff
154
155/*
156 * DBG - debug (dump a register value out)
157 */
158bool execute_pseudodbg(struct pt_regs *fp, unsigned int opcode)
159{
160 int grp, fn, reg;
161 long value, value1;
162
163 if ((opcode & 0xFF000000) != PseudoDbg_opcode)
164 return false;
165
166 opcode >>= 16;
167 grp = ((opcode >> PseudoDbg_grp_bits) & PseudoDbg_reg_mask);
168 fn = ((opcode >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
169 reg = ((opcode >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
170
171 if (fn == 3 && (reg == 0 || reg == 1)) {
172 if (!fix_up_reg(fp, &value, 4, 2 * reg))
173 return false;
174 if (!fix_up_reg(fp, &value1, 4, 2 * reg + 1))
175 return false;
176
177 pr_notice("DBG A%i = %02lx%08lx\n", reg, value & 0xFF, value1);
178 fp->pc += 2;
179 return true;
180
181 } else if (fn == 0) {
182 if (!fix_up_reg(fp, &value, grp, reg))
183 return false;
184
185 pr_notice("DBG %s = %08lx\n", get_allreg_name(grp, reg), value);
186 fp->pc += 2;
187 return true;
188 }
189
190 return false;
191}
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 8e2efceb364b..d37a397f43f5 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Copyright 2004-2010 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later. 4 * Licensed under the GPL-2 or later.
5 */ 5 */
@@ -925,7 +925,7 @@ void __init setup_arch(char **cmdline_p)
925 else if (_bfin_swrst & RESET_SOFTWARE) 925 else if (_bfin_swrst & RESET_SOFTWARE)
926 printk(KERN_NOTICE "Reset caused by Software reset\n"); 926 printk(KERN_NOTICE "Reset caused by Software reset\n");
927 927
928 printk(KERN_INFO "Blackfin support (C) 2004-2009 Analog Devices, Inc.\n"); 928 printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
929 if (bfin_compiled_revid() == 0xffff) 929 if (bfin_compiled_revid() == 0xffff)
930 printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid()); 930 printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
931 else if (bfin_compiled_revid() == -1) 931 else if (bfin_compiled_revid() == -1)
diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c
index 2e7f8e10bf87..bdc1e2f0da32 100644
--- a/arch/blackfin/kernel/sys_bfin.c
+++ b/arch/blackfin/kernel/sys_bfin.c
@@ -47,3 +47,26 @@ unsigned long get_fb_unmapped_area(struct file *filp, unsigned long orig_addr,
47} 47}
48EXPORT_SYMBOL(get_fb_unmapped_area); 48EXPORT_SYMBOL(get_fb_unmapped_area);
49#endif 49#endif
50
51/* Needed for legacy userspace atomic emulation */
52static DEFINE_SPINLOCK(bfin_spinlock_lock);
53
54#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1
55__attribute__((l1_text))
56#endif
57asmlinkage int sys_bfin_spinlock(int *p)
58{
59 int ret, tmp = 0;
60
61 spin_lock(&bfin_spinlock_lock); /* This would also hold kernel preemption. */
62 ret = get_user(tmp, p);
63 if (likely(ret == 0)) {
64 if (unlikely(tmp))
65 ret = 1;
66 else
67 put_user(1, p);
68 }
69 spin_unlock(&bfin_spinlock_lock);
70
71 return ret;
72}
diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c
new file mode 100644
index 000000000000..59fcdf6b0138
--- /dev/null
+++ b/arch/blackfin/kernel/trace.c
@@ -0,0 +1,981 @@
1/* provide some functions which dump the trace buffer, in a nice way for people
2 * to read it, and understand what is going on
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later
7 */
8
9#include <linux/kernel.h>
10#include <linux/hardirq.h>
11#include <linux/thread_info.h>
12#include <linux/mm.h>
13#include <linux/uaccess.h>
14#include <linux/module.h>
15#include <linux/kallsyms.h>
16#include <linux/err.h>
17#include <linux/fs.h>
18#include <asm/dma.h>
19#include <asm/trace.h>
20#include <asm/fixed_code.h>
21#include <asm/traps.h>
22#include <asm/irq_handler.h>
23
24void decode_address(char *buf, unsigned long address)
25{
26 struct task_struct *p;
27 struct mm_struct *mm;
28 unsigned long flags, offset;
29 unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
30 struct rb_node *n;
31
32#ifdef CONFIG_KALLSYMS
33 unsigned long symsize;
34 const char *symname;
35 char *modname;
36 char *delim = ":";
37 char namebuf[128];
38#endif
39
40 buf += sprintf(buf, "<0x%08lx> ", address);
41
42#ifdef CONFIG_KALLSYMS
43 /* look up the address and see if we are in kernel space */
44 symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf);
45
46 if (symname) {
47 /* yeah! kernel space! */
48 if (!modname)
49 modname = delim = "";
50 sprintf(buf, "{ %s%s%s%s + 0x%lx }",
51 delim, modname, delim, symname,
52 (unsigned long)offset);
53 return;
54 }
55#endif
56
57 if (address >= FIXED_CODE_START && address < FIXED_CODE_END) {
58 /* Problem in fixed code section? */
59 strcat(buf, "/* Maybe fixed code section */");
60 return;
61
62 } else if (address < CONFIG_BOOT_LOAD) {
63 /* Problem somewhere before the kernel start address */
64 strcat(buf, "/* Maybe null pointer? */");
65 return;
66
67 } else if (address >= COREMMR_BASE) {
68 strcat(buf, "/* core mmrs */");
69 return;
70
71 } else if (address >= SYSMMR_BASE) {
72 strcat(buf, "/* system mmrs */");
73 return;
74
75 } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) {
76 strcat(buf, "/* on-chip L1 ROM */");
77 return;
78
79 } else if (address >= L1_SCRATCH_START && address < L1_SCRATCH_START + L1_SCRATCH_LENGTH) {
80 strcat(buf, "/* on-chip scratchpad */");
81 return;
82
83 } else if (address >= physical_mem_end && address < ASYNC_BANK0_BASE) {
84 strcat(buf, "/* unconnected memory */");
85 return;
86
87 } else if (address >= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE && address < BOOT_ROM_START) {
88 strcat(buf, "/* reserved memory */");
89 return;
90
91 } else if (address >= L1_DATA_A_START && address < L1_DATA_A_START + L1_DATA_A_LENGTH) {
92 strcat(buf, "/* on-chip Data Bank A */");
93 return;
94
95 } else if (address >= L1_DATA_B_START && address < L1_DATA_B_START + L1_DATA_B_LENGTH) {
96 strcat(buf, "/* on-chip Data Bank B */");
97 return;
98 }
99
100 /*
101 * Don't walk any of the vmas if we are oopsing, it has been known
102 * to cause problems - corrupt vmas (kernel crashes) cause double faults
103 */
104 if (oops_in_progress) {
105 strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
106 return;
107 }
108
109 /* looks like we're off in user-land, so let's walk all the
110 * mappings of all our processes and see if we can't be a whee
111 * bit more specific
112 */
113 write_lock_irqsave(&tasklist_lock, flags);
114 for_each_process(p) {
115 mm = (in_atomic ? p->mm : get_task_mm(p));
116 if (!mm)
117 continue;
118
119 if (!down_read_trylock(&mm->mmap_sem)) {
120 if (!in_atomic)
121 mmput(mm);
122 continue;
123 }
124
125 for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
126 struct vm_area_struct *vma;
127
128 vma = rb_entry(n, struct vm_area_struct, vm_rb);
129
130 if (address >= vma->vm_start && address < vma->vm_end) {
131 char _tmpbuf[256];
132 char *name = p->comm;
133 struct file *file = vma->vm_file;
134
135 if (file) {
136 char *d_name = d_path(&file->f_path, _tmpbuf,
137 sizeof(_tmpbuf));
138 if (!IS_ERR(d_name))
139 name = d_name;
140 }
141
142 /* FLAT does not have its text aligned to the start of
143 * the map while FDPIC ELF does ...
144 */
145
146 /* before we can check flat/fdpic, we need to
147 * make sure current is valid
148 */
149 if ((unsigned long)current >= FIXED_CODE_START &&
150 !((unsigned long)current & 0x3)) {
151 if (current->mm &&
152 (address > current->mm->start_code) &&
153 (address < current->mm->end_code))
154 offset = address - current->mm->start_code;
155 else
156 offset = (address - vma->vm_start) +
157 (vma->vm_pgoff << PAGE_SHIFT);
158
159 sprintf(buf, "[ %s + 0x%lx ]", name, offset);
160 } else
161 sprintf(buf, "[ %s vma:0x%lx-0x%lx]",
162 name, vma->vm_start, vma->vm_end);
163
164 up_read(&mm->mmap_sem);
165 if (!in_atomic)
166 mmput(mm);
167
168 if (buf[0] == '\0')
169 sprintf(buf, "[ %s ] dynamic memory", name);
170
171 goto done;
172 }
173 }
174
175 up_read(&mm->mmap_sem);
176 if (!in_atomic)
177 mmput(mm);
178 }
179
180 /*
181 * we were unable to find this address anywhere,
182 * or some MMs were skipped because they were in use.
183 */
184 sprintf(buf, "/* kernel dynamic memory */");
185
186done:
187 write_unlock_irqrestore(&tasklist_lock, flags);
188}
189
190#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
191
192/*
193 * Similar to get_user, do some address checking, then dereference
194 * Return true on success, false on bad address
195 */
196bool get_mem16(unsigned short *val, unsigned short *address)
197{
198 unsigned long addr = (unsigned long)address;
199
200 /* Check for odd addresses */
201 if (addr & 0x1)
202 return false;
203
204 switch (bfin_mem_access_type(addr, 2)) {
205 case BFIN_MEM_ACCESS_CORE:
206 case BFIN_MEM_ACCESS_CORE_ONLY:
207 *val = *address;
208 return true;
209 case BFIN_MEM_ACCESS_DMA:
210 dma_memcpy(val, address, 2);
211 return true;
212 case BFIN_MEM_ACCESS_ITEST:
213 isram_memcpy(val, address, 2);
214 return true;
215 default: /* invalid access */
216 return false;
217 }
218}
219
220bool get_instruction(unsigned int *val, unsigned short *address)
221{
222 unsigned long addr = (unsigned long)address;
223 unsigned short opcode0, opcode1;
224
225 /* Check for odd addresses */
226 if (addr & 0x1)
227 return false;
228
229 /* MMR region will never have instructions */
230 if (addr >= SYSMMR_BASE)
231 return false;
232
233 /* Scratchpad will never have instructions */
234 if (addr >= L1_SCRATCH_START && addr < L1_SCRATCH_START + L1_SCRATCH_LENGTH)
235 return false;
236
237 /* Data banks will never have instructions */
238 if (addr >= BOOT_ROM_START + BOOT_ROM_LENGTH && addr < L1_CODE_START)
239 return false;
240
241 if (!get_mem16(&opcode0, address))
242 return false;
243
244 /* was this a 32-bit instruction? If so, get the next 16 bits */
245 if ((opcode0 & 0xc000) == 0xc000) {
246 if (!get_mem16(&opcode1, address + 1))
247 return false;
248 *val = (opcode0 << 16) + opcode1;
249 } else
250 *val = opcode0;
251
252 return true;
253}
254
255#if defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
256/*
257 * decode the instruction if we are printing out the trace, as it
258 * makes things easier to follow, without running it through objdump
259 * Decode the change of flow, and the common load/store instructions
260 * which are the main cause for faults, and discontinuities in the trace
261 * buffer.
262 */
263
264#define ProgCtrl_opcode 0x0000
265#define ProgCtrl_poprnd_bits 0
266#define ProgCtrl_poprnd_mask 0xf
267#define ProgCtrl_prgfunc_bits 4
268#define ProgCtrl_prgfunc_mask 0xf
269#define ProgCtrl_code_bits 8
270#define ProgCtrl_code_mask 0xff
271
272static void decode_ProgCtrl_0(unsigned int opcode)
273{
274 int poprnd = ((opcode >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
275 int prgfunc = ((opcode >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
276
277 if (prgfunc == 0 && poprnd == 0)
278 pr_cont("NOP");
279 else if (prgfunc == 1 && poprnd == 0)
280 pr_cont("RTS");
281 else if (prgfunc == 1 && poprnd == 1)
282 pr_cont("RTI");
283 else if (prgfunc == 1 && poprnd == 2)
284 pr_cont("RTX");
285 else if (prgfunc == 1 && poprnd == 3)
286 pr_cont("RTN");
287 else if (prgfunc == 1 && poprnd == 4)
288 pr_cont("RTE");
289 else if (prgfunc == 2 && poprnd == 0)
290 pr_cont("IDLE");
291 else if (prgfunc == 2 && poprnd == 3)
292 pr_cont("CSYNC");
293 else if (prgfunc == 2 && poprnd == 4)
294 pr_cont("SSYNC");
295 else if (prgfunc == 2 && poprnd == 5)
296 pr_cont("EMUEXCPT");
297 else if (prgfunc == 3)
298 pr_cont("CLI R%i", poprnd);
299 else if (prgfunc == 4)
300 pr_cont("STI R%i", poprnd);
301 else if (prgfunc == 5)
302 pr_cont("JUMP (P%i)", poprnd);
303 else if (prgfunc == 6)
304 pr_cont("CALL (P%i)", poprnd);
305 else if (prgfunc == 7)
306 pr_cont("CALL (PC + P%i)", poprnd);
307 else if (prgfunc == 8)
308 pr_cont("JUMP (PC + P%i", poprnd);
309 else if (prgfunc == 9)
310 pr_cont("RAISE %i", poprnd);
311 else if (prgfunc == 10)
312 pr_cont("EXCPT %i", poprnd);
313 else
314 pr_cont("0x%04x", opcode);
315
316}
317
318#define BRCC_opcode 0x1000
319#define BRCC_offset_bits 0
320#define BRCC_offset_mask 0x3ff
321#define BRCC_B_bits 10
322#define BRCC_B_mask 0x1
323#define BRCC_T_bits 11
324#define BRCC_T_mask 0x1
325#define BRCC_code_bits 12
326#define BRCC_code_mask 0xf
327
328static void decode_BRCC_0(unsigned int opcode)
329{
330 int B = ((opcode >> BRCC_B_bits) & BRCC_B_mask);
331 int T = ((opcode >> BRCC_T_bits) & BRCC_T_mask);
332
333 pr_cont("IF %sCC JUMP pcrel %s", T ? "" : "!", B ? "(BP)" : "");
334}
335
336#define CALLa_opcode 0xe2000000
337#define CALLa_addr_bits 0
338#define CALLa_addr_mask 0xffffff
339#define CALLa_S_bits 24
340#define CALLa_S_mask 0x1
341#define CALLa_code_bits 25
342#define CALLa_code_mask 0x7f
343
344static void decode_CALLa_0(unsigned int opcode)
345{
346 int S = ((opcode >> (CALLa_S_bits - 16)) & CALLa_S_mask);
347
348 if (S)
349 pr_cont("CALL pcrel");
350 else
351 pr_cont("JUMP.L");
352}
353
354#define LoopSetup_opcode 0xe0800000
355#define LoopSetup_eoffset_bits 0
356#define LoopSetup_eoffset_mask 0x3ff
357#define LoopSetup_dontcare_bits 10
358#define LoopSetup_dontcare_mask 0x3
359#define LoopSetup_reg_bits 12
360#define LoopSetup_reg_mask 0xf
361#define LoopSetup_soffset_bits 16
362#define LoopSetup_soffset_mask 0xf
363#define LoopSetup_c_bits 20
364#define LoopSetup_c_mask 0x1
365#define LoopSetup_rop_bits 21
366#define LoopSetup_rop_mask 0x3
367#define LoopSetup_code_bits 23
368#define LoopSetup_code_mask 0x1ff
369
370static void decode_LoopSetup_0(unsigned int opcode)
371{
372 int c = ((opcode >> LoopSetup_c_bits) & LoopSetup_c_mask);
373 int reg = ((opcode >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
374 int rop = ((opcode >> LoopSetup_rop_bits) & LoopSetup_rop_mask);
375
376 pr_cont("LSETUP <> LC%i", c);
377 if ((rop & 1) == 1)
378 pr_cont("= P%i", reg);
379 if ((rop & 2) == 2)
380 pr_cont(" >> 0x1");
381}
382
383#define DspLDST_opcode 0x9c00
384#define DspLDST_reg_bits 0
385#define DspLDST_reg_mask 0x7
386#define DspLDST_i_bits 3
387#define DspLDST_i_mask 0x3
388#define DspLDST_m_bits 5
389#define DspLDST_m_mask 0x3
390#define DspLDST_aop_bits 7
391#define DspLDST_aop_mask 0x3
392#define DspLDST_W_bits 9
393#define DspLDST_W_mask 0x1
394#define DspLDST_code_bits 10
395#define DspLDST_code_mask 0x3f
396
397static void decode_dspLDST_0(unsigned int opcode)
398{
399 int i = ((opcode >> DspLDST_i_bits) & DspLDST_i_mask);
400 int m = ((opcode >> DspLDST_m_bits) & DspLDST_m_mask);
401 int W = ((opcode >> DspLDST_W_bits) & DspLDST_W_mask);
402 int aop = ((opcode >> DspLDST_aop_bits) & DspLDST_aop_mask);
403 int reg = ((opcode >> DspLDST_reg_bits) & DspLDST_reg_mask);
404
405 if (W == 0) {
406 pr_cont("R%i", reg);
407 switch (m) {
408 case 0:
409 pr_cont(" = ");
410 break;
411 case 1:
412 pr_cont(".L = ");
413 break;
414 case 2:
415 pr_cont(".W = ");
416 break;
417 }
418 }
419
420 pr_cont("[ I%i", i);
421
422 switch (aop) {
423 case 0:
424 pr_cont("++ ]");
425 break;
426 case 1:
427 pr_cont("-- ]");
428 break;
429 }
430
431 if (W == 1) {
432 pr_cont(" = R%i", reg);
433 switch (m) {
434 case 1:
435 pr_cont(".L = ");
436 break;
437 case 2:
438 pr_cont(".W = ");
439 break;
440 }
441 }
442}
443
444#define LDST_opcode 0x9000
445#define LDST_reg_bits 0
446#define LDST_reg_mask 0x7
447#define LDST_ptr_bits 3
448#define LDST_ptr_mask 0x7
449#define LDST_Z_bits 6
450#define LDST_Z_mask 0x1
451#define LDST_aop_bits 7
452#define LDST_aop_mask 0x3
453#define LDST_W_bits 9
454#define LDST_W_mask 0x1
455#define LDST_sz_bits 10
456#define LDST_sz_mask 0x3
457#define LDST_code_bits 12
458#define LDST_code_mask 0xf
459
460static void decode_LDST_0(unsigned int opcode)
461{
462 int Z = ((opcode >> LDST_Z_bits) & LDST_Z_mask);
463 int W = ((opcode >> LDST_W_bits) & LDST_W_mask);
464 int sz = ((opcode >> LDST_sz_bits) & LDST_sz_mask);
465 int aop = ((opcode >> LDST_aop_bits) & LDST_aop_mask);
466 int reg = ((opcode >> LDST_reg_bits) & LDST_reg_mask);
467 int ptr = ((opcode >> LDST_ptr_bits) & LDST_ptr_mask);
468
469 if (W == 0)
470 pr_cont("%s%i = ", (sz == 0 && Z == 1) ? "P" : "R", reg);
471
472 switch (sz) {
473 case 1:
474 pr_cont("W");
475 break;
476 case 2:
477 pr_cont("B");
478 break;
479 }
480
481 pr_cont("[P%i", ptr);
482
483 switch (aop) {
484 case 0:
485 pr_cont("++");
486 break;
487 case 1:
488 pr_cont("--");
489 break;
490 }
491 pr_cont("]");
492
493 if (W == 1)
494 pr_cont(" = %s%i ", (sz == 0 && Z == 1) ? "P" : "R", reg);
495
496 if (sz) {
497 if (Z)
498 pr_cont(" (X)");
499 else
500 pr_cont(" (Z)");
501 }
502}
503
504#define LDSTii_opcode 0xa000
505#define LDSTii_reg_bit 0
506#define LDSTii_reg_mask 0x7
507#define LDSTii_ptr_bit 3
508#define LDSTii_ptr_mask 0x7
509#define LDSTii_offset_bit 6
510#define LDSTii_offset_mask 0xf
511#define LDSTii_op_bit 10
512#define LDSTii_op_mask 0x3
513#define LDSTii_W_bit 12
514#define LDSTii_W_mask 0x1
515#define LDSTii_code_bit 13
516#define LDSTii_code_mask 0x7
517
518static void decode_LDSTii_0(unsigned int opcode)
519{
520 int reg = ((opcode >> LDSTii_reg_bit) & LDSTii_reg_mask);
521 int ptr = ((opcode >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
522 int offset = ((opcode >> LDSTii_offset_bit) & LDSTii_offset_mask);
523 int op = ((opcode >> LDSTii_op_bit) & LDSTii_op_mask);
524 int W = ((opcode >> LDSTii_W_bit) & LDSTii_W_mask);
525
526 if (W == 0) {
527 pr_cont("%s%i = %s[P%i + %i]", op == 3 ? "R" : "P", reg,
528 op == 1 || op == 2 ? "" : "W", ptr, offset);
529 if (op == 2)
530 pr_cont("(Z)");
531 if (op == 3)
532 pr_cont("(X)");
533 } else {
534 pr_cont("%s[P%i + %i] = %s%i", op == 0 ? "" : "W", ptr,
535 offset, op == 3 ? "P" : "R", reg);
536 }
537}
538
539#define LDSTidxI_opcode 0xe4000000
540#define LDSTidxI_offset_bits 0
541#define LDSTidxI_offset_mask 0xffff
542#define LDSTidxI_reg_bits 16
543#define LDSTidxI_reg_mask 0x7
544#define LDSTidxI_ptr_bits 19
545#define LDSTidxI_ptr_mask 0x7
546#define LDSTidxI_sz_bits 22
547#define LDSTidxI_sz_mask 0x3
548#define LDSTidxI_Z_bits 24
549#define LDSTidxI_Z_mask 0x1
550#define LDSTidxI_W_bits 25
551#define LDSTidxI_W_mask 0x1
552#define LDSTidxI_code_bits 26
553#define LDSTidxI_code_mask 0x3f
554
555static void decode_LDSTidxI_0(unsigned int opcode)
556{
557 int Z = ((opcode >> LDSTidxI_Z_bits) & LDSTidxI_Z_mask);
558 int W = ((opcode >> LDSTidxI_W_bits) & LDSTidxI_W_mask);
559 int sz = ((opcode >> LDSTidxI_sz_bits) & LDSTidxI_sz_mask);
560 int reg = ((opcode >> LDSTidxI_reg_bits) & LDSTidxI_reg_mask);
561 int ptr = ((opcode >> LDSTidxI_ptr_bits) & LDSTidxI_ptr_mask);
562 int offset = ((opcode >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
563
564 if (W == 0)
565 pr_cont("%s%i = ", sz == 0 && Z == 1 ? "P" : "R", reg);
566
567 if (sz == 1)
568 pr_cont("W");
569 if (sz == 2)
570 pr_cont("B");
571
572 pr_cont("[P%i + %s0x%x]", ptr, offset & 0x20 ? "-" : "",
573 (offset & 0x1f) << 2);
574
575 if (W == 0 && sz != 0) {
576 if (Z)
577 pr_cont("(X)");
578 else
579 pr_cont("(Z)");
580 }
581
582 if (W == 1)
583 pr_cont("= %s%i", (sz == 0 && Z == 1) ? "P" : "R", reg);
584
585}
586
587static void decode_opcode(unsigned int opcode)
588{
589#ifdef CONFIG_BUG
590 if (opcode == BFIN_BUG_OPCODE)
591 pr_cont("BUG");
592 else
593#endif
594 if ((opcode & 0xffffff00) == ProgCtrl_opcode)
595 decode_ProgCtrl_0(opcode);
596 else if ((opcode & 0xfffff000) == BRCC_opcode)
597 decode_BRCC_0(opcode);
598 else if ((opcode & 0xfffff000) == 0x2000)
599 pr_cont("JUMP.S");
600 else if ((opcode & 0xfe000000) == CALLa_opcode)
601 decode_CALLa_0(opcode);
602 else if ((opcode & 0xff8000C0) == LoopSetup_opcode)
603 decode_LoopSetup_0(opcode);
604 else if ((opcode & 0xfffffc00) == DspLDST_opcode)
605 decode_dspLDST_0(opcode);
606 else if ((opcode & 0xfffff000) == LDST_opcode)
607 decode_LDST_0(opcode);
608 else if ((opcode & 0xffffe000) == LDSTii_opcode)
609 decode_LDSTii_0(opcode);
610 else if ((opcode & 0xfc000000) == LDSTidxI_opcode)
611 decode_LDSTidxI_0(opcode);
612 else if (opcode & 0xffff0000)
613 pr_cont("0x%08x", opcode);
614 else
615 pr_cont("0x%04x", opcode);
616}
617
618#define BIT_MULTI_INS 0x08000000
619static void decode_instruction(unsigned short *address)
620{
621 unsigned int opcode;
622
623 if (!get_instruction(&opcode, address))
624 return;
625
626 decode_opcode(opcode);
627
628 /* If things are a 32-bit instruction, it has the possibility of being
629 * a multi-issue instruction (a 32-bit, and 2 16 bit instrucitions)
630 * This test collidates with the unlink instruction, so disallow that
631 */
632 if ((opcode & 0xc0000000) == 0xc0000000 &&
633 (opcode & BIT_MULTI_INS) &&
634 (opcode & 0xe8000000) != 0xe8000000) {
635 pr_cont(" || ");
636 if (!get_instruction(&opcode, address + 2))
637 return;
638 decode_opcode(opcode);
639 pr_cont(" || ");
640 if (!get_instruction(&opcode, address + 3))
641 return;
642 decode_opcode(opcode);
643 }
644}
645#endif
646
647void dump_bfin_trace_buffer(void)
648{
649#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
650 int tflags, i = 0, fault = 0;
651 char buf[150];
652 unsigned short *addr;
653 unsigned int cpu = raw_smp_processor_id();
654#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
655 int j, index;
656#endif
657
658 trace_buffer_save(tflags);
659
660 pr_notice("Hardware Trace:\n");
661
662#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
663 pr_notice("WARNING: Expanded trace turned on - can not trace exceptions\n");
664#endif
665
666 if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
667 for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
668 addr = (unsigned short *)bfin_read_TBUF();
669 decode_address(buf, (unsigned long)addr);
670 pr_notice("%4i Target : %s\n", i, buf);
671 /* Normally, the faulting instruction doesn't go into
672 * the trace buffer, (since it doesn't commit), so
673 * we print out the fault address here
674 */
675 if (!fault && addr == ((unsigned short *)evt_ivhw)) {
676 addr = (unsigned short *)bfin_read_TBUF();
677 decode_address(buf, (unsigned long)addr);
678 pr_notice(" FAULT : %s ", buf);
679 decode_instruction(addr);
680 pr_cont("\n");
681 fault = 1;
682 continue;
683 }
684 if (!fault && addr == (unsigned short *)trap &&
685 (cpu_pda[cpu].seqstat & SEQSTAT_EXCAUSE) > VEC_EXCPT15) {
686 decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
687 pr_notice(" FAULT : %s ", buf);
688 decode_instruction((unsigned short *)cpu_pda[cpu].icplb_fault_addr);
689 pr_cont("\n");
690 fault = 1;
691 }
692 addr = (unsigned short *)bfin_read_TBUF();
693 decode_address(buf, (unsigned long)addr);
694 pr_notice(" Source : %s ", buf);
695 decode_instruction(addr);
696 pr_cont("\n");
697 }
698 }
699
700#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
701 if (trace_buff_offset)
702 index = trace_buff_offset / 4;
703 else
704 index = EXPAND_LEN;
705
706 j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128;
707 while (j) {
708 decode_address(buf, software_trace_buff[index]);
709 pr_notice("%4i Target : %s\n", i, buf);
710 index -= 1;
711 if (index < 0)
712 index = EXPAND_LEN;
713 decode_address(buf, software_trace_buff[index]);
714 pr_notice(" Source : %s ", buf);
715 decode_instruction((unsigned short *)software_trace_buff[index]);
716 pr_cont("\n");
717 index -= 1;
718 if (index < 0)
719 index = EXPAND_LEN;
720 j--;
721 i++;
722 }
723#endif
724
725 trace_buffer_restore(tflags);
726#endif
727}
728EXPORT_SYMBOL(dump_bfin_trace_buffer);
729
730void dump_bfin_process(struct pt_regs *fp)
731{
732 /* We should be able to look at fp->ipend, but we don't push it on the
733 * stack all the time, so do this until we fix that */
734 unsigned int context = bfin_read_IPEND();
735
736 if (oops_in_progress)
737 pr_emerg("Kernel OOPS in progress\n");
738
739 if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
740 pr_notice("HW Error context\n");
741 else if (context & 0x0020)
742 pr_notice("Deferred Exception context\n");
743 else if (context & 0x3FC0)
744 pr_notice("Interrupt context\n");
745 else if (context & 0x4000)
746 pr_notice("Deferred Interrupt context\n");
747 else if (context & 0x8000)
748 pr_notice("Kernel process context\n");
749
750 /* Because we are crashing, and pointers could be bad, we check things
751 * pretty closely before we use them
752 */
753 if ((unsigned long)current >= FIXED_CODE_START &&
754 !((unsigned long)current & 0x3) && current->pid) {
755 pr_notice("CURRENT PROCESS:\n");
756 if (current->comm >= (char *)FIXED_CODE_START)
757 pr_notice("COMM=%s PID=%d",
758 current->comm, current->pid);
759 else
760 pr_notice("COMM= invalid");
761
762 pr_cont(" CPU=%d\n", current_thread_info()->cpu);
763 if (!((unsigned long)current->mm & 0x3) &&
764 (unsigned long)current->mm >= FIXED_CODE_START) {
765 pr_notice("TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n",
766 (void *)current->mm->start_code,
767 (void *)current->mm->end_code,
768 (void *)current->mm->start_data,
769 (void *)current->mm->end_data);
770 pr_notice(" BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n",
771 (void *)current->mm->end_data,
772 (void *)current->mm->brk,
773 (void *)current->mm->start_stack);
774 } else
775 pr_notice("invalid mm\n");
776 } else
777 pr_notice("No Valid process in current context\n");
778}
779
780void dump_bfin_mem(struct pt_regs *fp)
781{
782 unsigned short *addr, *erraddr, val = 0, err = 0;
783 char sti = 0, buf[6];
784
785 erraddr = (void *)fp->pc;
786
787 pr_notice("return address: [0x%p]; contents of:", erraddr);
788
789 for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
790 addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
791 addr++) {
792 if (!((unsigned long)addr & 0xF))
793 pr_notice("0x%p: ", addr);
794
795 if (!get_mem16(&val, addr)) {
796 val = 0;
797 sprintf(buf, "????");
798 } else
799 sprintf(buf, "%04x", val);
800
801 if (addr == erraddr) {
802 pr_cont("[%s]", buf);
803 err = val;
804 } else
805 pr_cont(" %s ", buf);
806
807 /* Do any previous instructions turn on interrupts? */
808 if (addr <= erraddr && /* in the past */
809 ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */
810 val == 0x017b)) /* [SP++] = RETI */
811 sti = 1;
812 }
813
814 pr_cont("\n");
815
816 /* Hardware error interrupts can be deferred */
817 if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
818 oops_in_progress)){
819 pr_notice("Looks like this was a deferred error - sorry\n");
820#ifndef CONFIG_DEBUG_HWERR
821 pr_notice("The remaining message may be meaningless\n");
822 pr_notice("You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n");
823#else
824 /* If we are handling only one peripheral interrupt
825 * and current mm and pid are valid, and the last error
826 * was in that user space process's text area
827 * print it out - because that is where the problem exists
828 */
829 if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) &&
830 (current->pid && current->mm)) {
831 /* And the last RETI points to the current userspace context */
832 if ((fp + 1)->pc >= current->mm->start_code &&
833 (fp + 1)->pc <= current->mm->end_code) {
834 pr_notice("It might be better to look around here :\n");
835 pr_notice("-------------------------------------------\n");
836 show_regs(fp + 1);
837 pr_notice("-------------------------------------------\n");
838 }
839 }
840#endif
841 }
842}
843
844void show_regs(struct pt_regs *fp)
845{
846 char buf[150];
847 struct irqaction *action;
848 unsigned int i;
849 unsigned long flags = 0;
850 unsigned int cpu = raw_smp_processor_id();
851 unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
852
853 pr_notice("\n");
854 if (CPUID != bfin_cpuid())
855 pr_notice("Compiled for cpu family 0x%04x (Rev %d), "
856 "but running on:0x%04x (Rev %d)\n",
857 CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());
858
859 pr_notice("ADSP-%s-0.%d",
860 CPU, bfin_compiled_revid());
861
862 if (bfin_compiled_revid() != bfin_revid())
863 pr_cont("(Detected 0.%d)", bfin_revid());
864
865 pr_cont(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
866 get_cclk()/1000000, get_sclk()/1000000,
867#ifdef CONFIG_MPU
868 "mpu on"
869#else
870 "mpu off"
871#endif
872 );
873
874 pr_notice("%s", linux_banner);
875
876 pr_notice("\nSEQUENCER STATUS:\t\t%s\n", print_tainted());
877 pr_notice(" SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n",
878 (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg);
879 if (fp->ipend & EVT_IRPTEN)
880 pr_notice(" Global Interrupts Disabled (IPEND[4])\n");
881 if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 |
882 EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR)))
883 pr_notice(" Peripheral interrupts masked off\n");
884 if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14)))
885 pr_notice(" Kernel interrupts masked off\n");
886 if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
887 pr_notice(" HWERRCAUSE: 0x%lx\n",
888 (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
889#ifdef EBIU_ERRMST
890 /* If the error was from the EBIU, print it out */
891 if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
892 pr_notice(" EBIU Error Reason : 0x%04x\n",
893 bfin_read_EBIU_ERRMST());
894 pr_notice(" EBIU Error Address : 0x%08x\n",
895 bfin_read_EBIU_ERRADD());
896 }
897#endif
898 }
899 pr_notice(" EXCAUSE : 0x%lx\n",
900 fp->seqstat & SEQSTAT_EXCAUSE);
901 for (i = 2; i <= 15 ; i++) {
902 if (fp->ipend & (1 << i)) {
903 if (i != 4) {
904 decode_address(buf, bfin_read32(EVT0 + 4*i));
905 pr_notice(" physical IVG%i asserted : %s\n", i, buf);
906 } else
907 pr_notice(" interrupts disabled\n");
908 }
909 }
910
911 /* if no interrupts are going off, don't print this out */
912 if (fp->ipend & ~0x3F) {
913 for (i = 0; i < (NR_IRQS - 1); i++) {
914 if (!in_atomic)
915 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
916
917 action = irq_desc[i].action;
918 if (!action)
919 goto unlock;
920
921 decode_address(buf, (unsigned int)action->handler);
922 pr_notice(" logical irq %3d mapped : %s", i, buf);
923 for (action = action->next; action; action = action->next) {
924 decode_address(buf, (unsigned int)action->handler);
925 pr_cont(", %s", buf);
926 }
927 pr_cont("\n");
928unlock:
929 if (!in_atomic)
930 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
931 }
932 }
933
934 decode_address(buf, fp->rete);
935 pr_notice(" RETE: %s\n", buf);
936 decode_address(buf, fp->retn);
937 pr_notice(" RETN: %s\n", buf);
938 decode_address(buf, fp->retx);
939 pr_notice(" RETX: %s\n", buf);
940 decode_address(buf, fp->rets);
941 pr_notice(" RETS: %s\n", buf);
942 decode_address(buf, fp->pc);
943 pr_notice(" PC : %s\n", buf);
944
945 if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
946 (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
947 decode_address(buf, cpu_pda[cpu].dcplb_fault_addr);
948 pr_notice("DCPLB_FAULT_ADDR: %s\n", buf);
949 decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
950 pr_notice("ICPLB_FAULT_ADDR: %s\n", buf);
951 }
952
953 pr_notice("PROCESSOR STATE:\n");
954 pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
955 fp->r0, fp->r1, fp->r2, fp->r3);
956 pr_notice(" R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
957 fp->r4, fp->r5, fp->r6, fp->r7);
958 pr_notice(" P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
959 fp->p0, fp->p1, fp->p2, fp->p3);
960 pr_notice(" P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
961 fp->p4, fp->p5, fp->fp, (long)fp);
962 pr_notice(" LB0: %08lx LT0: %08lx LC0: %08lx\n",
963 fp->lb0, fp->lt0, fp->lc0);
964 pr_notice(" LB1: %08lx LT1: %08lx LC1: %08lx\n",
965 fp->lb1, fp->lt1, fp->lc1);
966 pr_notice(" B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
967 fp->b0, fp->l0, fp->m0, fp->i0);
968 pr_notice(" B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
969 fp->b1, fp->l1, fp->m1, fp->i1);
970 pr_notice(" B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
971 fp->b2, fp->l2, fp->m2, fp->i2);
972 pr_notice(" B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
973 fp->b3, fp->l3, fp->m3, fp->i3);
974 pr_notice("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
975 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
976
977 pr_notice("USP : %08lx ASTAT: %08lx\n",
978 rdusp(), fp->astat);
979
980 pr_notice("\n");
981}
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index ba70c4bc2699..59c1df75e4de 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -1,25 +1,22 @@
1/* 1/*
2 * Copyright 2004-2009 Analog Devices Inc. 2 * Main exception handling logic.
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
3 * 5 *
4 * Licensed under the GPL-2 or later 6 * Licensed under the GPL-2 or later
5 */ 7 */
6 8
7#include <linux/bug.h> 9#include <linux/bug.h>
8#include <linux/uaccess.h> 10#include <linux/uaccess.h>
9#include <linux/interrupt.h>
10#include <linux/module.h> 11#include <linux/module.h>
11#include <linux/kallsyms.h>
12#include <linux/fs.h>
13#include <linux/rbtree.h>
14#include <asm/traps.h> 12#include <asm/traps.h>
15#include <asm/cacheflush.h>
16#include <asm/cplb.h> 13#include <asm/cplb.h>
17#include <asm/dma.h>
18#include <asm/blackfin.h> 14#include <asm/blackfin.h>
19#include <asm/irq_handler.h> 15#include <asm/irq_handler.h>
20#include <linux/irq.h> 16#include <linux/irq.h>
21#include <asm/trace.h> 17#include <asm/trace.h>
22#include <asm/fixed_code.h> 18#include <asm/fixed_code.h>
19#include <asm/pseudo_instructions.h>
23 20
24#ifdef CONFIG_KGDB 21#ifdef CONFIG_KGDB
25# include <linux/kgdb.h> 22# include <linux/kgdb.h>
@@ -62,194 +59,6 @@ void __init trap_init(void)
62 CSYNC(); 59 CSYNC();
63} 60}
64 61
65static void decode_address(char *buf, unsigned long address)
66{
67#ifdef CONFIG_DEBUG_VERBOSE
68 struct task_struct *p;
69 struct mm_struct *mm;
70 unsigned long flags, offset;
71 unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
72 struct rb_node *n;
73
74#ifdef CONFIG_KALLSYMS
75 unsigned long symsize;
76 const char *symname;
77 char *modname;
78 char *delim = ":";
79 char namebuf[128];
80#endif
81
82 buf += sprintf(buf, "<0x%08lx> ", address);
83
84#ifdef CONFIG_KALLSYMS
85 /* look up the address and see if we are in kernel space */
86 symname = kallsyms_lookup(address, &symsize, &offset, &modname, namebuf);
87
88 if (symname) {
89 /* yeah! kernel space! */
90 if (!modname)
91 modname = delim = "";
92 sprintf(buf, "{ %s%s%s%s + 0x%lx }",
93 delim, modname, delim, symname,
94 (unsigned long)offset);
95 return;
96 }
97#endif
98
99 if (address >= FIXED_CODE_START && address < FIXED_CODE_END) {
100 /* Problem in fixed code section? */
101 strcat(buf, "/* Maybe fixed code section */");
102 return;
103
104 } else if (address < CONFIG_BOOT_LOAD) {
105 /* Problem somewhere before the kernel start address */
106 strcat(buf, "/* Maybe null pointer? */");
107 return;
108
109 } else if (address >= COREMMR_BASE) {
110 strcat(buf, "/* core mmrs */");
111 return;
112
113 } else if (address >= SYSMMR_BASE) {
114 strcat(buf, "/* system mmrs */");
115 return;
116
117 } else if (address >= L1_ROM_START && address < L1_ROM_START + L1_ROM_LENGTH) {
118 strcat(buf, "/* on-chip L1 ROM */");
119 return;
120 }
121
122 /*
123 * Don't walk any of the vmas if we are oopsing, it has been known
124 * to cause problems - corrupt vmas (kernel crashes) cause double faults
125 */
126 if (oops_in_progress) {
127 strcat(buf, "/* kernel dynamic memory (maybe user-space) */");
128 return;
129 }
130
131 /* looks like we're off in user-land, so let's walk all the
132 * mappings of all our processes and see if we can't be a whee
133 * bit more specific
134 */
135 write_lock_irqsave(&tasklist_lock, flags);
136 for_each_process(p) {
137 mm = (in_atomic ? p->mm : get_task_mm(p));
138 if (!mm)
139 continue;
140
141 if (!down_read_trylock(&mm->mmap_sem)) {
142 if (!in_atomic)
143 mmput(mm);
144 continue;
145 }
146
147 for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
148 struct vm_area_struct *vma;
149
150 vma = rb_entry(n, struct vm_area_struct, vm_rb);
151
152 if (address >= vma->vm_start && address < vma->vm_end) {
153 char _tmpbuf[256];
154 char *name = p->comm;
155 struct file *file = vma->vm_file;
156
157 if (file) {
158 char *d_name = d_path(&file->f_path, _tmpbuf,
159 sizeof(_tmpbuf));
160 if (!IS_ERR(d_name))
161 name = d_name;
162 }
163
164 /* FLAT does not have its text aligned to the start of
165 * the map while FDPIC ELF does ...
166 */
167
168 /* before we can check flat/fdpic, we need to
169 * make sure current is valid
170 */
171 if ((unsigned long)current >= FIXED_CODE_START &&
172 !((unsigned long)current & 0x3)) {
173 if (current->mm &&
174 (address > current->mm->start_code) &&
175 (address < current->mm->end_code))
176 offset = address - current->mm->start_code;
177 else
178 offset = (address - vma->vm_start) +
179 (vma->vm_pgoff << PAGE_SHIFT);
180
181 sprintf(buf, "[ %s + 0x%lx ]", name, offset);
182 } else
183 sprintf(buf, "[ %s vma:0x%lx-0x%lx]",
184 name, vma->vm_start, vma->vm_end);
185
186 up_read(&mm->mmap_sem);
187 if (!in_atomic)
188 mmput(mm);
189
190 if (buf[0] == '\0')
191 sprintf(buf, "[ %s ] dynamic memory", name);
192
193 goto done;
194 }
195 }
196
197 up_read(&mm->mmap_sem);
198 if (!in_atomic)
199 mmput(mm);
200 }
201
202 /*
203 * we were unable to find this address anywhere,
204 * or some MMs were skipped because they were in use.
205 */
206 sprintf(buf, "/* kernel dynamic memory */");
207
208done:
209 write_unlock_irqrestore(&tasklist_lock, flags);
210#else
211 sprintf(buf, " ");
212#endif
213}
214
215asmlinkage void double_fault_c(struct pt_regs *fp)
216{
217#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
218 int j;
219 trace_buffer_save(j);
220#endif
221
222 console_verbose();
223 oops_in_progress = 1;
224#ifdef CONFIG_DEBUG_VERBOSE
225 printk(KERN_EMERG "Double Fault\n");
226#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
227 if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) {
228 unsigned int cpu = raw_smp_processor_id();
229 char buf[150];
230 decode_address(buf, cpu_pda[cpu].retx_doublefault);
231 printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n",
232 (unsigned int)cpu_pda[cpu].seqstat_doublefault & SEQSTAT_EXCAUSE, buf);
233 decode_address(buf, cpu_pda[cpu].dcplb_doublefault_addr);
234 printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf);
235 decode_address(buf, cpu_pda[cpu].icplb_doublefault_addr);
236 printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf);
237
238 decode_address(buf, fp->retx);
239 printk(KERN_NOTICE "The instruction at %s caused a double exception\n", buf);
240 } else
241#endif
242 {
243 dump_bfin_process(fp);
244 dump_bfin_mem(fp);
245 show_regs(fp);
246 dump_bfin_trace_buffer();
247 }
248#endif
249 panic("Double Fault - unrecoverable event");
250
251}
252
253static int kernel_mode_regs(struct pt_regs *regs) 62static int kernel_mode_regs(struct pt_regs *regs)
254{ 63{
255 return regs->ipend & 0xffc0; 64 return regs->ipend & 0xffc0;
@@ -260,6 +69,9 @@ asmlinkage notrace void trap_c(struct pt_regs *fp)
260#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON 69#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
261 int j; 70 int j;
262#endif 71#endif
72#ifdef CONFIG_BFIN_PSEUDODBG_INSNS
73 int opcode;
74#endif
263 unsigned int cpu = raw_smp_processor_id(); 75 unsigned int cpu = raw_smp_processor_id();
264 const char *strerror = NULL; 76 const char *strerror = NULL;
265 int sig = 0; 77 int sig = 0;
@@ -392,6 +204,19 @@ asmlinkage notrace void trap_c(struct pt_regs *fp)
392 } 204 }
393 } 205 }
394#endif 206#endif
207#ifdef CONFIG_BFIN_PSEUDODBG_INSNS
208 /*
209 * Support for the fake instructions, if the instruction fails,
210 * then just execute a illegal opcode failure (like normal).
211 * Don't support these instructions inside the kernel
212 */
213 if (!kernel_mode_regs(fp) && get_instruction(&opcode, (unsigned short *)fp->pc)) {
214 if (execute_pseudodbg_assert(fp, opcode))
215 goto traps_done;
216 if (execute_pseudodbg(fp, opcode))
217 goto traps_done;
218 }
219#endif
395 info.si_code = ILL_ILLOPC; 220 info.si_code = ILL_ILLOPC;
396 sig = SIGILL; 221 sig = SIGILL;
397 strerror = KERN_NOTICE EXC_0x21(KERN_NOTICE); 222 strerror = KERN_NOTICE EXC_0x21(KERN_NOTICE);
@@ -672,659 +497,44 @@ asmlinkage notrace void trap_c(struct pt_regs *fp)
672 trace_buffer_restore(j); 497 trace_buffer_restore(j);
673} 498}
674 499
675/* Typical exception handling routines */ 500asmlinkage void double_fault_c(struct pt_regs *fp)
676
677#define EXPAND_LEN ((1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 256 - 1)
678
679/*
680 * Similar to get_user, do some address checking, then dereference
681 * Return true on success, false on bad address
682 */
683static bool get_instruction(unsigned short *val, unsigned short *address)
684{
685 unsigned long addr = (unsigned long)address;
686
687 /* Check for odd addresses */
688 if (addr & 0x1)
689 return false;
690
691 /* MMR region will never have instructions */
692 if (addr >= SYSMMR_BASE)
693 return false;
694
695 switch (bfin_mem_access_type(addr, 2)) {
696 case BFIN_MEM_ACCESS_CORE:
697 case BFIN_MEM_ACCESS_CORE_ONLY:
698 *val = *address;
699 return true;
700 case BFIN_MEM_ACCESS_DMA:
701 dma_memcpy(val, address, 2);
702 return true;
703 case BFIN_MEM_ACCESS_ITEST:
704 isram_memcpy(val, address, 2);
705 return true;
706 default: /* invalid access */
707 return false;
708 }
709}
710
711/*
712 * decode the instruction if we are printing out the trace, as it
713 * makes things easier to follow, without running it through objdump
714 * These are the normal instructions which cause change of flow, which
715 * would be at the source of the trace buffer
716 */
717#if defined(CONFIG_DEBUG_VERBOSE) && defined(CONFIG_DEBUG_BFIN_HWTRACE_ON)
718static void decode_instruction(unsigned short *address)
719{
720 unsigned short opcode;
721
722 if (get_instruction(&opcode, address)) {
723 if (opcode == 0x0010)
724 verbose_printk("RTS");
725 else if (opcode == 0x0011)
726 verbose_printk("RTI");
727 else if (opcode == 0x0012)
728 verbose_printk("RTX");
729 else if (opcode == 0x0013)
730 verbose_printk("RTN");
731 else if (opcode == 0x0014)
732 verbose_printk("RTE");
733 else if (opcode == 0x0025)
734 verbose_printk("EMUEXCPT");
735 else if (opcode >= 0x0040 && opcode <= 0x0047)
736 verbose_printk("STI R%i", opcode & 7);
737 else if (opcode >= 0x0050 && opcode <= 0x0057)
738 verbose_printk("JUMP (P%i)", opcode & 7);
739 else if (opcode >= 0x0060 && opcode <= 0x0067)
740 verbose_printk("CALL (P%i)", opcode & 7);
741 else if (opcode >= 0x0070 && opcode <= 0x0077)
742 verbose_printk("CALL (PC+P%i)", opcode & 7);
743 else if (opcode >= 0x0080 && opcode <= 0x0087)
744 verbose_printk("JUMP (PC+P%i)", opcode & 7);
745 else if (opcode >= 0x0090 && opcode <= 0x009F)
746 verbose_printk("RAISE 0x%x", opcode & 0xF);
747 else if (opcode >= 0x00A0 && opcode <= 0x00AF)
748 verbose_printk("EXCPT 0x%x", opcode & 0xF);
749 else if ((opcode >= 0x1000 && opcode <= 0x13FF) || (opcode >= 0x1800 && opcode <= 0x1BFF))
750 verbose_printk("IF !CC JUMP");
751 else if ((opcode >= 0x1400 && opcode <= 0x17ff) || (opcode >= 0x1c00 && opcode <= 0x1fff))
752 verbose_printk("IF CC JUMP");
753 else if (opcode >= 0x2000 && opcode <= 0x2fff)
754 verbose_printk("JUMP.S");
755 else if (opcode >= 0xe080 && opcode <= 0xe0ff)
756 verbose_printk("LSETUP");
757 else if (opcode >= 0xe200 && opcode <= 0xe2ff)
758 verbose_printk("JUMP.L");
759 else if (opcode >= 0xe300 && opcode <= 0xe3ff)
760 verbose_printk("CALL pcrel");
761 else
762 verbose_printk("0x%04x", opcode);
763 }
764
765}
766#endif
767
768void dump_bfin_trace_buffer(void)
769{
770#ifdef CONFIG_DEBUG_VERBOSE
771#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
772 int tflags, i = 0;
773 char buf[150];
774 unsigned short *addr;
775#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
776 int j, index;
777#endif
778
779 trace_buffer_save(tflags);
780
781 printk(KERN_NOTICE "Hardware Trace:\n");
782
783#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
784 printk(KERN_NOTICE "WARNING: Expanded trace turned on - can not trace exceptions\n");
785#endif
786
787 if (likely(bfin_read_TBUFSTAT() & TBUFCNT)) {
788 for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
789 decode_address(buf, (unsigned long)bfin_read_TBUF());
790 printk(KERN_NOTICE "%4i Target : %s\n", i, buf);
791 addr = (unsigned short *)bfin_read_TBUF();
792 decode_address(buf, (unsigned long)addr);
793 printk(KERN_NOTICE " Source : %s ", buf);
794 decode_instruction(addr);
795 printk("\n");
796 }
797 }
798
799#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
800 if (trace_buff_offset)
801 index = trace_buff_offset / 4;
802 else
803 index = EXPAND_LEN;
804
805 j = (1 << CONFIG_DEBUG_BFIN_HWTRACE_EXPAND_LEN) * 128;
806 while (j) {
807 decode_address(buf, software_trace_buff[index]);
808 printk(KERN_NOTICE "%4i Target : %s\n", i, buf);
809 index -= 1;
810 if (index < 0 )
811 index = EXPAND_LEN;
812 decode_address(buf, software_trace_buff[index]);
813 printk(KERN_NOTICE " Source : %s ", buf);
814 decode_instruction((unsigned short *)software_trace_buff[index]);
815 printk("\n");
816 index -= 1;
817 if (index < 0)
818 index = EXPAND_LEN;
819 j--;
820 i++;
821 }
822#endif
823
824 trace_buffer_restore(tflags);
825#endif
826#endif
827}
828EXPORT_SYMBOL(dump_bfin_trace_buffer);
829
830#ifdef CONFIG_BUG
831int is_valid_bugaddr(unsigned long addr)
832{
833 unsigned short opcode;
834
835 if (!get_instruction(&opcode, (unsigned short *)addr))
836 return 0;
837
838 return opcode == BFIN_BUG_OPCODE;
839}
840#endif
841
842/*
843 * Checks to see if the address pointed to is either a
844 * 16-bit CALL instruction, or a 32-bit CALL instruction
845 */
846static bool is_bfin_call(unsigned short *addr)
847{
848 unsigned short opcode = 0, *ins_addr;
849 ins_addr = (unsigned short *)addr;
850
851 if (!get_instruction(&opcode, ins_addr))
852 return false;
853
854 if ((opcode >= 0x0060 && opcode <= 0x0067) ||
855 (opcode >= 0x0070 && opcode <= 0x0077))
856 return true;
857
858 ins_addr--;
859 if (!get_instruction(&opcode, ins_addr))
860 return false;
861
862 if (opcode >= 0xE300 && opcode <= 0xE3FF)
863 return true;
864
865 return false;
866
867}
868
869void show_stack(struct task_struct *task, unsigned long *stack)
870{
871#ifdef CONFIG_PRINTK
872 unsigned int *addr, *endstack, *fp = 0, *frame;
873 unsigned short *ins_addr;
874 char buf[150];
875 unsigned int i, j, ret_addr, frame_no = 0;
876
877 /*
878 * If we have been passed a specific stack, use that one otherwise
879 * if we have been passed a task structure, use that, otherwise
880 * use the stack of where the variable "stack" exists
881 */
882
883 if (stack == NULL) {
884 if (task) {
885 /* We know this is a kernel stack, so this is the start/end */
886 stack = (unsigned long *)task->thread.ksp;
887 endstack = (unsigned int *)(((unsigned int)(stack) & ~(THREAD_SIZE - 1)) + THREAD_SIZE);
888 } else {
889 /* print out the existing stack info */
890 stack = (unsigned long *)&stack;
891 endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
892 }
893 } else
894 endstack = (unsigned int *)PAGE_ALIGN((unsigned int)stack);
895
896 printk(KERN_NOTICE "Stack info:\n");
897 decode_address(buf, (unsigned int)stack);
898 printk(KERN_NOTICE " SP: [0x%p] %s\n", stack, buf);
899
900 if (!access_ok(VERIFY_READ, stack, (unsigned int)endstack - (unsigned int)stack)) {
901 printk(KERN_NOTICE "Invalid stack pointer\n");
902 return;
903 }
904
905 /* First thing is to look for a frame pointer */
906 for (addr = (unsigned int *)((unsigned int)stack & ~0xF); addr < endstack; addr++) {
907 if (*addr & 0x1)
908 continue;
909 ins_addr = (unsigned short *)*addr;
910 ins_addr--;
911 if (is_bfin_call(ins_addr))
912 fp = addr - 1;
913
914 if (fp) {
915 /* Let's check to see if it is a frame pointer */
916 while (fp >= (addr - 1) && fp < endstack
917 && fp && ((unsigned int) fp & 0x3) == 0)
918 fp = (unsigned int *)*fp;
919 if (fp == 0 || fp == endstack) {
920 fp = addr - 1;
921 break;
922 }
923 fp = 0;
924 }
925 }
926 if (fp) {
927 frame = fp;
928 printk(KERN_NOTICE " FP: (0x%p)\n", fp);
929 } else
930 frame = 0;
931
932 /*
933 * Now that we think we know where things are, we
934 * walk the stack again, this time printing things out
935 * incase there is no frame pointer, we still look for
936 * valid return addresses
937 */
938
939 /* First time print out data, next time, print out symbols */
940 for (j = 0; j <= 1; j++) {
941 if (j)
942 printk(KERN_NOTICE "Return addresses in stack:\n");
943 else
944 printk(KERN_NOTICE " Memory from 0x%08lx to %p", ((long unsigned int)stack & ~0xF), endstack);
945
946 fp = frame;
947 frame_no = 0;
948
949 for (addr = (unsigned int *)((unsigned int)stack & ~0xF), i = 0;
950 addr < endstack; addr++, i++) {
951
952 ret_addr = 0;
953 if (!j && i % 8 == 0)
954 printk(KERN_NOTICE "%p:",addr);
955
956 /* if it is an odd address, or zero, just skip it */
957 if (*addr & 0x1 || !*addr)
958 goto print;
959
960 ins_addr = (unsigned short *)*addr;
961
962 /* Go back one instruction, and see if it is a CALL */
963 ins_addr--;
964 ret_addr = is_bfin_call(ins_addr);
965 print:
966 if (!j && stack == (unsigned long *)addr)
967 printk("[%08x]", *addr);
968 else if (ret_addr)
969 if (j) {
970 decode_address(buf, (unsigned int)*addr);
971 if (frame == addr) {
972 printk(KERN_NOTICE " frame %2i : %s\n", frame_no, buf);
973 continue;
974 }
975 printk(KERN_NOTICE " address : %s\n", buf);
976 } else
977 printk("<%08x>", *addr);
978 else if (fp == addr) {
979 if (j)
980 frame = addr+1;
981 else
982 printk("(%08x)", *addr);
983
984 fp = (unsigned int *)*addr;
985 frame_no++;
986
987 } else if (!j)
988 printk(" %08x ", *addr);
989 }
990 if (!j)
991 printk("\n");
992 }
993#endif
994}
995EXPORT_SYMBOL(show_stack);
996
997void dump_stack(void)
998{ 501{
999 unsigned long stack;
1000#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON 502#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
1001 int tflags; 503 int j;
504 trace_buffer_save(j);
1002#endif 505#endif
1003 trace_buffer_save(tflags);
1004 dump_bfin_trace_buffer();
1005 show_stack(current, &stack);
1006 trace_buffer_restore(tflags);
1007}
1008EXPORT_SYMBOL(dump_stack);
1009 506
1010void dump_bfin_process(struct pt_regs *fp) 507 console_verbose();
1011{ 508 oops_in_progress = 1;
1012#ifdef CONFIG_DEBUG_VERBOSE 509#ifdef CONFIG_DEBUG_VERBOSE
1013 /* We should be able to look at fp->ipend, but we don't push it on the 510 printk(KERN_EMERG "Double Fault\n");
1014 * stack all the time, so do this until we fix that */ 511#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
1015 unsigned int context = bfin_read_IPEND(); 512 if (((long)fp->seqstat & SEQSTAT_EXCAUSE) == VEC_UNCOV) {
1016 513 unsigned int cpu = raw_smp_processor_id();
1017 if (oops_in_progress) 514 char buf[150];
1018 verbose_printk(KERN_EMERG "Kernel OOPS in progress\n"); 515 decode_address(buf, cpu_pda[cpu].retx_doublefault);
1019 516 printk(KERN_EMERG "While handling exception (EXCAUSE = 0x%x) at %s:\n",
1020 if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) 517 (unsigned int)cpu_pda[cpu].seqstat_doublefault & SEQSTAT_EXCAUSE, buf);
1021 verbose_printk(KERN_NOTICE "HW Error context\n"); 518 decode_address(buf, cpu_pda[cpu].dcplb_doublefault_addr);
1022 else if (context & 0x0020) 519 printk(KERN_NOTICE " DCPLB_FAULT_ADDR: %s\n", buf);
1023 verbose_printk(KERN_NOTICE "Deferred Exception context\n"); 520 decode_address(buf, cpu_pda[cpu].icplb_doublefault_addr);
1024 else if (context & 0x3FC0) 521 printk(KERN_NOTICE " ICPLB_FAULT_ADDR: %s\n", buf);
1025 verbose_printk(KERN_NOTICE "Interrupt context\n");
1026 else if (context & 0x4000)
1027 verbose_printk(KERN_NOTICE "Deferred Interrupt context\n");
1028 else if (context & 0x8000)
1029 verbose_printk(KERN_NOTICE "Kernel process context\n");
1030
1031 /* Because we are crashing, and pointers could be bad, we check things
1032 * pretty closely before we use them
1033 */
1034 if ((unsigned long)current >= FIXED_CODE_START &&
1035 !((unsigned long)current & 0x3) && current->pid) {
1036 verbose_printk(KERN_NOTICE "CURRENT PROCESS:\n");
1037 if (current->comm >= (char *)FIXED_CODE_START)
1038 verbose_printk(KERN_NOTICE "COMM=%s PID=%d",
1039 current->comm, current->pid);
1040 else
1041 verbose_printk(KERN_NOTICE "COMM= invalid");
1042 522
1043 printk(KERN_CONT " CPU=%d\n", current_thread_info()->cpu); 523 decode_address(buf, fp->retx);
1044 if (!((unsigned long)current->mm & 0x3) && (unsigned long)current->mm >= FIXED_CODE_START) 524 printk(KERN_NOTICE "The instruction at %s caused a double exception\n", buf);
1045 verbose_printk(KERN_NOTICE
1046 "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n"
1047 " BSS = 0x%p-0x%p USER-STACK = 0x%p\n\n",
1048 (void *)current->mm->start_code,
1049 (void *)current->mm->end_code,
1050 (void *)current->mm->start_data,
1051 (void *)current->mm->end_data,
1052 (void *)current->mm->end_data,
1053 (void *)current->mm->brk,
1054 (void *)current->mm->start_stack);
1055 else
1056 verbose_printk(KERN_NOTICE "invalid mm\n");
1057 } else 525 } else
1058 verbose_printk(KERN_NOTICE
1059 "No Valid process in current context\n");
1060#endif
1061}
1062
1063void dump_bfin_mem(struct pt_regs *fp)
1064{
1065#ifdef CONFIG_DEBUG_VERBOSE
1066 unsigned short *addr, *erraddr, val = 0, err = 0;
1067 char sti = 0, buf[6];
1068
1069 erraddr = (void *)fp->pc;
1070
1071 verbose_printk(KERN_NOTICE "return address: [0x%p]; contents of:", erraddr);
1072
1073 for (addr = (unsigned short *)((unsigned long)erraddr & ~0xF) - 0x10;
1074 addr < (unsigned short *)((unsigned long)erraddr & ~0xF) + 0x10;
1075 addr++) {
1076 if (!((unsigned long)addr & 0xF))
1077 verbose_printk(KERN_NOTICE "0x%p: ", addr);
1078
1079 if (!get_instruction(&val, addr)) {
1080 val = 0;
1081 sprintf(buf, "????");
1082 } else
1083 sprintf(buf, "%04x", val);
1084
1085 if (addr == erraddr) {
1086 verbose_printk("[%s]", buf);
1087 err = val;
1088 } else
1089 verbose_printk(" %s ", buf);
1090
1091 /* Do any previous instructions turn on interrupts? */
1092 if (addr <= erraddr && /* in the past */
1093 ((val >= 0x0040 && val <= 0x0047) || /* STI instruction */
1094 val == 0x017b)) /* [SP++] = RETI */
1095 sti = 1;
1096 }
1097
1098 verbose_printk("\n");
1099
1100 /* Hardware error interrupts can be deferred */
1101 if (unlikely(sti && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR &&
1102 oops_in_progress)){
1103 verbose_printk(KERN_NOTICE "Looks like this was a deferred error - sorry\n");
1104#ifndef CONFIG_DEBUG_HWERR
1105 verbose_printk(KERN_NOTICE
1106"The remaining message may be meaningless\n"
1107"You should enable CONFIG_DEBUG_HWERR to get a better idea where it came from\n");
1108#else
1109 /* If we are handling only one peripheral interrupt
1110 * and current mm and pid are valid, and the last error
1111 * was in that user space process's text area
1112 * print it out - because that is where the problem exists
1113 */
1114 if ((!(((fp)->ipend & ~0x30) & (((fp)->ipend & ~0x30) - 1))) &&
1115 (current->pid && current->mm)) {
1116 /* And the last RETI points to the current userspace context */
1117 if ((fp + 1)->pc >= current->mm->start_code &&
1118 (fp + 1)->pc <= current->mm->end_code) {
1119 verbose_printk(KERN_NOTICE "It might be better to look around here :\n");
1120 verbose_printk(KERN_NOTICE "-------------------------------------------\n");
1121 show_regs(fp + 1);
1122 verbose_printk(KERN_NOTICE "-------------------------------------------\n");
1123 }
1124 }
1125#endif
1126 }
1127#endif
1128}
1129
1130void show_regs(struct pt_regs *fp)
1131{
1132#ifdef CONFIG_DEBUG_VERBOSE
1133 char buf [150];
1134 struct irqaction *action;
1135 unsigned int i;
1136 unsigned long flags = 0;
1137 unsigned int cpu = raw_smp_processor_id();
1138 unsigned char in_atomic = (bfin_read_IPEND() & 0x10) || in_atomic();
1139
1140 verbose_printk(KERN_NOTICE "\n");
1141 if (CPUID != bfin_cpuid())
1142 verbose_printk(KERN_NOTICE "Compiled for cpu family 0x%04x (Rev %d), "
1143 "but running on:0x%04x (Rev %d)\n",
1144 CPUID, bfin_compiled_revid(), bfin_cpuid(), bfin_revid());
1145
1146 verbose_printk(KERN_NOTICE "ADSP-%s-0.%d",
1147 CPU, bfin_compiled_revid());
1148
1149 if (bfin_compiled_revid() != bfin_revid())
1150 verbose_printk("(Detected 0.%d)", bfin_revid());
1151
1152 verbose_printk(" %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n",
1153 get_cclk()/1000000, get_sclk()/1000000,
1154#ifdef CONFIG_MPU
1155 "mpu on"
1156#else
1157 "mpu off"
1158#endif
1159 );
1160
1161 verbose_printk(KERN_NOTICE "%s", linux_banner);
1162
1163 verbose_printk(KERN_NOTICE "\nSEQUENCER STATUS:\t\t%s\n", print_tainted());
1164 verbose_printk(KERN_NOTICE " SEQSTAT: %08lx IPEND: %04lx IMASK: %04lx SYSCFG: %04lx\n",
1165 (long)fp->seqstat, fp->ipend, cpu_pda[raw_smp_processor_id()].ex_imask, fp->syscfg);
1166 if (fp->ipend & EVT_IRPTEN)
1167 verbose_printk(KERN_NOTICE " Global Interrupts Disabled (IPEND[4])\n");
1168 if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG13 | EVT_IVG12 | EVT_IVG11 |
1169 EVT_IVG10 | EVT_IVG9 | EVT_IVG8 | EVT_IVG7 | EVT_IVTMR)))
1170 verbose_printk(KERN_NOTICE " Peripheral interrupts masked off\n");
1171 if (!(cpu_pda[raw_smp_processor_id()].ex_imask & (EVT_IVG15 | EVT_IVG14)))
1172 verbose_printk(KERN_NOTICE " Kernel interrupts masked off\n");
1173 if ((fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR) {
1174 verbose_printk(KERN_NOTICE " HWERRCAUSE: 0x%lx\n",
1175 (fp->seqstat & SEQSTAT_HWERRCAUSE) >> 14);
1176#ifdef EBIU_ERRMST
1177 /* If the error was from the EBIU, print it out */
1178 if (bfin_read_EBIU_ERRMST() & CORE_ERROR) {
1179 verbose_printk(KERN_NOTICE " EBIU Error Reason : 0x%04x\n",
1180 bfin_read_EBIU_ERRMST());
1181 verbose_printk(KERN_NOTICE " EBIU Error Address : 0x%08x\n",
1182 bfin_read_EBIU_ERRADD());
1183 }
1184#endif 526#endif
527 {
528 dump_bfin_process(fp);
529 dump_bfin_mem(fp);
530 show_regs(fp);
531 dump_bfin_trace_buffer();
1185 } 532 }
1186 verbose_printk(KERN_NOTICE " EXCAUSE : 0x%lx\n",
1187 fp->seqstat & SEQSTAT_EXCAUSE);
1188 for (i = 2; i <= 15 ; i++) {
1189 if (fp->ipend & (1 << i)) {
1190 if (i != 4) {
1191 decode_address(buf, bfin_read32(EVT0 + 4*i));
1192 verbose_printk(KERN_NOTICE " physical IVG%i asserted : %s\n", i, buf);
1193 } else
1194 verbose_printk(KERN_NOTICE " interrupts disabled\n");
1195 }
1196 }
1197
1198 /* if no interrupts are going off, don't print this out */
1199 if (fp->ipend & ~0x3F) {
1200 for (i = 0; i < (NR_IRQS - 1); i++) {
1201 if (!in_atomic)
1202 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
1203
1204 action = irq_desc[i].action;
1205 if (!action)
1206 goto unlock;
1207
1208 decode_address(buf, (unsigned int)action->handler);
1209 verbose_printk(KERN_NOTICE " logical irq %3d mapped : %s", i, buf);
1210 for (action = action->next; action; action = action->next) {
1211 decode_address(buf, (unsigned int)action->handler);
1212 verbose_printk(", %s", buf);
1213 }
1214 verbose_printk("\n");
1215unlock:
1216 if (!in_atomic)
1217 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
1218 }
1219 }
1220
1221 decode_address(buf, fp->rete);
1222 verbose_printk(KERN_NOTICE " RETE: %s\n", buf);
1223 decode_address(buf, fp->retn);
1224 verbose_printk(KERN_NOTICE " RETN: %s\n", buf);
1225 decode_address(buf, fp->retx);
1226 verbose_printk(KERN_NOTICE " RETX: %s\n", buf);
1227 decode_address(buf, fp->rets);
1228 verbose_printk(KERN_NOTICE " RETS: %s\n", buf);
1229 decode_address(buf, fp->pc);
1230 verbose_printk(KERN_NOTICE " PC : %s\n", buf);
1231
1232 if (((long)fp->seqstat & SEQSTAT_EXCAUSE) &&
1233 (((long)fp->seqstat & SEQSTAT_EXCAUSE) != VEC_HWERR)) {
1234 decode_address(buf, cpu_pda[cpu].dcplb_fault_addr);
1235 verbose_printk(KERN_NOTICE "DCPLB_FAULT_ADDR: %s\n", buf);
1236 decode_address(buf, cpu_pda[cpu].icplb_fault_addr);
1237 verbose_printk(KERN_NOTICE "ICPLB_FAULT_ADDR: %s\n", buf);
1238 }
1239
1240 verbose_printk(KERN_NOTICE "PROCESSOR STATE:\n");
1241 verbose_printk(KERN_NOTICE " R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n",
1242 fp->r0, fp->r1, fp->r2, fp->r3);
1243 verbose_printk(KERN_NOTICE " R4 : %08lx R5 : %08lx R6 : %08lx R7 : %08lx\n",
1244 fp->r4, fp->r5, fp->r6, fp->r7);
1245 verbose_printk(KERN_NOTICE " P0 : %08lx P1 : %08lx P2 : %08lx P3 : %08lx\n",
1246 fp->p0, fp->p1, fp->p2, fp->p3);
1247 verbose_printk(KERN_NOTICE " P4 : %08lx P5 : %08lx FP : %08lx SP : %08lx\n",
1248 fp->p4, fp->p5, fp->fp, (long)fp);
1249 verbose_printk(KERN_NOTICE " LB0: %08lx LT0: %08lx LC0: %08lx\n",
1250 fp->lb0, fp->lt0, fp->lc0);
1251 verbose_printk(KERN_NOTICE " LB1: %08lx LT1: %08lx LC1: %08lx\n",
1252 fp->lb1, fp->lt1, fp->lc1);
1253 verbose_printk(KERN_NOTICE " B0 : %08lx L0 : %08lx M0 : %08lx I0 : %08lx\n",
1254 fp->b0, fp->l0, fp->m0, fp->i0);
1255 verbose_printk(KERN_NOTICE " B1 : %08lx L1 : %08lx M1 : %08lx I1 : %08lx\n",
1256 fp->b1, fp->l1, fp->m1, fp->i1);
1257 verbose_printk(KERN_NOTICE " B2 : %08lx L2 : %08lx M2 : %08lx I2 : %08lx\n",
1258 fp->b2, fp->l2, fp->m2, fp->i2);
1259 verbose_printk(KERN_NOTICE " B3 : %08lx L3 : %08lx M3 : %08lx I3 : %08lx\n",
1260 fp->b3, fp->l3, fp->m3, fp->i3);
1261 verbose_printk(KERN_NOTICE "A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
1262 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
1263
1264 verbose_printk(KERN_NOTICE "USP : %08lx ASTAT: %08lx\n",
1265 rdusp(), fp->astat);
1266
1267 verbose_printk(KERN_NOTICE "\n");
1268#endif 533#endif
1269} 534 panic("Double Fault - unrecoverable event");
1270
1271#ifdef CONFIG_SYS_BFIN_SPINLOCK_L1
1272asmlinkage int sys_bfin_spinlock(int *spinlock)__attribute__((l1_text));
1273#endif
1274
1275static DEFINE_SPINLOCK(bfin_spinlock_lock);
1276
1277asmlinkage int sys_bfin_spinlock(int *p)
1278{
1279 int ret, tmp = 0;
1280
1281 spin_lock(&bfin_spinlock_lock); /* This would also hold kernel preemption. */
1282 ret = get_user(tmp, p);
1283 if (likely(ret == 0)) {
1284 if (unlikely(tmp))
1285 ret = 1;
1286 else
1287 put_user(1, p);
1288 }
1289 spin_unlock(&bfin_spinlock_lock);
1290 return ret;
1291}
1292
1293int bfin_request_exception(unsigned int exception, void (*handler)(void))
1294{
1295 void (*curr_handler)(void);
1296
1297 if (exception > 0x3F)
1298 return -EINVAL;
1299
1300 curr_handler = ex_table[exception];
1301
1302 if (curr_handler != ex_replaceable)
1303 return -EBUSY;
1304
1305 ex_table[exception] = handler;
1306 535
1307 return 0;
1308} 536}
1309EXPORT_SYMBOL(bfin_request_exception);
1310
1311int bfin_free_exception(unsigned int exception, void (*handler)(void))
1312{
1313 void (*curr_handler)(void);
1314
1315 if (exception > 0x3F)
1316 return -EINVAL;
1317
1318 curr_handler = ex_table[exception];
1319 537
1320 if (curr_handler != handler)
1321 return -EBUSY;
1322
1323 ex_table[exception] = ex_replaceable;
1324
1325 return 0;
1326}
1327EXPORT_SYMBOL(bfin_free_exception);
1328 538
1329void panic_cplb_error(int cplb_panic, struct pt_regs *fp) 539void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
1330{ 540{
@@ -1349,3 +559,23 @@ void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
1349 dump_stack(); 559 dump_stack();
1350 panic("Unrecoverable event"); 560 panic("Unrecoverable event");
1351} 561}
562
563#ifdef CONFIG_BUG
564int is_valid_bugaddr(unsigned long addr)
565{
566 unsigned int opcode;
567
568 if (!get_instruction(&opcode, (unsigned short *)addr))
569 return 0;
570
571 return opcode == BFIN_BUG_OPCODE;
572}
573#endif
574
575/* stub this out */
576#ifndef CONFIG_DEBUG_VERBOSE
577void show_regs(struct pt_regs *fp)
578{
579
580}
581#endif
diff --git a/arch/blackfin/lib/memset.S b/arch/blackfin/lib/memset.S
index c30d99b10969..eab1bef3f5bf 100644
--- a/arch/blackfin/lib/memset.S
+++ b/arch/blackfin/lib/memset.S
@@ -20,6 +20,7 @@
20 * R1 = filler byte 20 * R1 = filler byte
21 * R2 = count 21 * R2 = count
22 * Favours word aligned data. 22 * Favours word aligned data.
23 * The strncpy assumes that I0 and I1 are not used in this function
23 */ 24 */
24 25
25ENTRY(_memset) 26ENTRY(_memset)
diff --git a/arch/blackfin/lib/strcmp.S b/arch/blackfin/lib/strcmp.S
new file mode 100644
index 000000000000..d7c1d158973b
--- /dev/null
+++ b/arch/blackfin/lib/strcmp.S
@@ -0,0 +1,43 @@
1/*
2 * Copyright 2005-2010 Analog Devices Inc.
3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */
6
7#include <linux/linkage.h>
8
9/* void *strcmp(char *s1, const char *s2);
10 * R0 = address (s1)
11 * R1 = address (s2)
12 *
13 * Returns an integer less than, equal to, or greater than zero if s1
14 * (or the first n bytes thereof) is found, respectively, to be less
15 * than, to match, or be greater than s2.
16 */
17
18#ifdef CONFIG_STRCMP_L1
19.section .l1.text
20#else
21.text
22#endif
23
24.align 2
25
26ENTRY(_strcmp)
27 P0 = R0 ; /* s1 */
28 P1 = R1 ; /* s2 */
29
301:
31 R0 = B[P0++] (Z); /* get *s1 */
32 R1 = B[P1++] (Z); /* get *s2 */
33 CC = R0 == R1; /* compare a byte */
34 if ! cc jump 2f; /* not equal, break out */
35 CC = R0; /* at end of s1? */
36 if cc jump 1b (bp); /* no, keep going */
37 jump.s 3f; /* strings are equal */
382:
39 R0 = R0 - R1; /* *s1 - *s2 */
403:
41 RTS;
42
43ENDPROC(_strcmp)
diff --git a/arch/blackfin/lib/strcmp.c b/arch/blackfin/lib/strcmp.c
deleted file mode 100644
index fde39a1950ce..000000000000
--- a/arch/blackfin/lib/strcmp.c
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Provide symbol in case str func is not inlined.
3 *
4 * Copyright (c) 2006-2007 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#define strcmp __inline_strcmp
10#include <asm/string.h>
11#undef strcmp
12
13#include <linux/module.h>
14
15int strcmp(const char *dest, const char *src)
16{
17 return __inline_strcmp(dest, src);
18}
19EXPORT_SYMBOL(strcmp);
diff --git a/arch/blackfin/lib/strcpy.S b/arch/blackfin/lib/strcpy.S
new file mode 100644
index 000000000000..a6a0c6363806
--- /dev/null
+++ b/arch/blackfin/lib/strcpy.S
@@ -0,0 +1,35 @@
1/*
2 * Copyright 2005-2010 Analog Devices Inc.
3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */
6
7#include <linux/linkage.h>
8
9/* void *strcpy(char *dest, const char *src);
10 * R0 = address (dest)
11 * R1 = address (src)
12 *
13 * Returns a pointer to the destination string dest
14 */
15
16#ifdef CONFIG_STRCPY_L1
17.section .l1.text
18#else
19.text
20#endif
21
22.align 2
23
24ENTRY(_strcpy)
25 P0 = R0 ; /* dst*/
26 P1 = R1 ; /* src*/
27
281:
29 R1 = B [P1++] (Z);
30 B [P0++] = R1;
31 CC = R1;
32 if cc jump 1b (bp);
33 RTS;
34
35ENDPROC(_strcpy)
diff --git a/arch/blackfin/lib/strcpy.c b/arch/blackfin/lib/strcpy.c
deleted file mode 100644
index 2a8836b1f4d3..000000000000
--- a/arch/blackfin/lib/strcpy.c
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Provide symbol in case str func is not inlined.
3 *
4 * Copyright (c) 2006-2007 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#define strcpy __inline_strcpy
10#include <asm/string.h>
11#undef strcpy
12
13#include <linux/module.h>
14
15char *strcpy(char *dest, const char *src)
16{
17 return __inline_strcpy(dest, src);
18}
19EXPORT_SYMBOL(strcpy);
diff --git a/arch/blackfin/lib/strncmp.S b/arch/blackfin/lib/strncmp.S
new file mode 100644
index 000000000000..6da37c34a847
--- /dev/null
+++ b/arch/blackfin/lib/strncmp.S
@@ -0,0 +1,52 @@
1/*
2 * Copyright 2005-2010 Analog Devices Inc.
3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */
6
7#include <linux/linkage.h>
8
9/* void *strncpy(char *s1, const char *s2, size_t n);
10 * R0 = address (dest)
11 * R1 = address (src)
12 * R2 = size (n)
13 * Returns a pointer to the destination string dest
14 */
15
16#ifdef CONFIG_STRNCMP_L1
17.section .l1.text
18#else
19.text
20#endif
21
22.align 2
23
24ENTRY(_strncmp)
25 CC = R2 == 0;
26 if CC JUMP 5f;
27
28 P0 = R0 ; /* s1 */
29 P1 = R1 ; /* s2 */
301:
31 R0 = B[P0++] (Z); /* get *s1 */
32 R1 = B[P1++] (Z); /* get *s2 */
33 CC = R0 == R1; /* compare a byte */
34 if ! cc jump 3f; /* not equal, break out */
35 CC = R0; /* at end of s1? */
36 if ! cc jump 4f; /* yes, all done */
37 R2 += -1; /* no, adjust count */
38 CC = R2 == 0;
39 if ! cc jump 1b (bp); /* more to do, keep going */
402:
41 R0 = 0; /* strings are equal */
42 jump.s 4f;
433:
44 R0 = R0 - R1; /* *s1 - *s2 */
454:
46 RTS;
47
485:
49 R0 = 0;
50 RTS;
51
52ENDPROC(_strncmp)
diff --git a/arch/blackfin/lib/strncmp.c b/arch/blackfin/lib/strncmp.c
deleted file mode 100644
index 46518b1d2983..000000000000
--- a/arch/blackfin/lib/strncmp.c
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Provide symbol in case str func is not inlined.
3 *
4 * Copyright (c) 2006-2007 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#define strncmp __inline_strncmp
10#include <asm/string.h>
11#include <linux/module.h>
12#undef strncmp
13
14int strncmp(const char *cs, const char *ct, size_t count)
15{
16 return __inline_strncmp(cs, ct, count);
17}
18EXPORT_SYMBOL(strncmp);
diff --git a/arch/blackfin/lib/strncpy.S b/arch/blackfin/lib/strncpy.S
new file mode 100644
index 000000000000..f3931d50b4a7
--- /dev/null
+++ b/arch/blackfin/lib/strncpy.S
@@ -0,0 +1,85 @@
1/*
2 * Copyright 2005-2010 Analog Devices Inc.
3 *
4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */
6
7#include <linux/linkage.h>
8#include <asm/context.S>
9
10/* void *strncpy(char *dest, const char *src, size_t n);
11 * R0 = address (dest)
12 * R1 = address (src)
13 * R2 = size
14 * Returns a pointer (R0) to the destination string dest
15 * we do this by not changing R0
16 */
17
18#ifdef CONFIG_STRNCPY_L1
19.section .l1.text
20#else
21.text
22#endif
23
24.align 2
25
26ENTRY(_strncpy)
27 CC = R2 == 0;
28 if CC JUMP 4f;
29
30 P2 = R2 ; /* size */
31 P0 = R0 ; /* dst*/
32 P1 = R1 ; /* src*/
33
34 LSETUP (1f, 2f) LC0 = P2;
351:
36 R1 = B [P1++] (Z);
37 B [P0++] = R1;
38 CC = R1 == 0;
392:
40 if CC jump 3f;
41
42 RTS;
43
44 /* if src is shorter than n, we need to null pad bytes in dest
45 * but, we can get here when the last byte is zero, and we don't
46 * want to copy an extra byte at the end, so we need to check
47 */
483:
49 R2 = LC0;
50 CC = R2
51 if ! CC jump 6f;
52
53 /* if the required null padded portion is small, do it here, rather than
54 * handling the overhead of memset (which is OK when things are big).
55 */
56 R3 = 0x20;
57 CC = R2 < R3;
58 IF CC jump 4f;
59
60 R2 += -1;
61
62 /* Set things up for memset
63 * R0 = address
64 * R1 = filler byte (this case it's zero, set above)
65 * R2 = count (set above)
66 */
67
68 I1 = R0;
69 R0 = RETS;
70 I0 = R0;
71 R0 = P0;
72 pseudo_long_call _memset, p0;
73 R0 = I0;
74 RETS = R0;
75 R0 = I1;
76 RTS;
77
784:
79 LSETUP(5f, 5f) LC0;
805:
81 B [P0++] = R1;
826:
83 RTS;
84
85ENDPROC(_strncpy)
diff --git a/arch/blackfin/lib/strncpy.c b/arch/blackfin/lib/strncpy.c
deleted file mode 100644
index ea1dc6bf2373..000000000000
--- a/arch/blackfin/lib/strncpy.c
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Provide symbol in case str func is not inlined.
3 *
4 * Copyright (c) 2006-2007 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#define strncpy __inline_strncpy
10#include <asm/string.h>
11#undef strncpy
12
13#include <linux/module.h>
14
15char *strncpy(char *dest, const char *src, size_t n)
16{
17 return __inline_strncpy(dest, src, n);
18}
19EXPORT_SYMBOL(strncpy);
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index ebe76d1e874a..f392af641657 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -98,6 +98,10 @@ static struct musb_hdrc_config musb_config = {
98 .num_eps = 8, 98 .num_eps = 8,
99 .dma_channels = 8, 99 .dma_channels = 8,
100 .gpio_vrsel = GPIO_PF11, 100 .gpio_vrsel = GPIO_PF11,
101 /* Some custom boards need to be active low, just set it to "0"
102 * if it is the case.
103 */
104 .gpio_vrsel_active = 1,
101}; 105};
102 106
103static struct musb_hdrc_platform_data musb_plat = { 107static struct musb_hdrc_platform_data musb_plat = {
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 55069af4f67d..606eb36b9d6e 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -62,6 +62,10 @@ static struct musb_hdrc_config musb_config = {
62 .num_eps = 8, 62 .num_eps = 8,
63 .dma_channels = 8, 63 .dma_channels = 8,
64 .gpio_vrsel = GPIO_PG13, 64 .gpio_vrsel = GPIO_PG13,
65 /* Some custom boards need to be active low, just set it to "0"
66 * if it is the case.
67 */
68 .gpio_vrsel_active = 1,
65}; 69};
66 70
67static struct musb_hdrc_platform_data musb_plat = { 71static struct musb_hdrc_platform_data musb_plat = {
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 923383386aa1..a05c967a24cf 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -102,6 +102,10 @@ static struct musb_hdrc_config musb_config = {
102 .num_eps = 8, 102 .num_eps = 8,
103 .dma_channels = 8, 103 .dma_channels = 8,
104 .gpio_vrsel = GPIO_PG13, 104 .gpio_vrsel = GPIO_PG13,
105 /* Some custom boards need to be active low, just set it to "0"
106 * if it is the case.
107 */
108 .gpio_vrsel_active = 1,
105}; 109};
106 110
107static struct musb_hdrc_platform_data musb_plat = { 111static struct musb_hdrc_platform_data musb_plat = {
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index c489d602c590..05d45994480e 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -23,12 +23,13 @@
23#include <asm/dma.h> 23#include <asm/dma.h>
24#include <asm/bfin5xx_spi.h> 24#include <asm/bfin5xx_spi.h>
25#include <asm/reboot.h> 25#include <asm/reboot.h>
26#include <asm/portmux.h>
26#include <linux/spi/ad7877.h> 27#include <linux/spi/ad7877.h>
27 28
28/* 29/*
29 * Name the Board for the /proc/cpuinfo 30 * Name the Board for the /proc/cpuinfo
30 */ 31 */
31char *bfin_board_name = "CamSig Minotaur BF537"; 32const char bfin_board_name[] = "CamSig Minotaur BF537";
32 33
33#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) 34#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
34static struct resource bfin_pcmcia_cf_resources[] = { 35static struct resource bfin_pcmcia_cf_resources[] = {
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 066d5c261f47..cf396ea40092 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1702,628 +1702,6 @@
1702#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ 1702#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1703#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ 1703#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1704 1704
1705/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
1706/* CAN_CONTROL Masks */
1707#define SRS 0x0001 /* Software Reset */
1708#define DNM 0x0002 /* Device Net Mode */
1709#define ABO 0x0004 /* Auto-Bus On Enable */
1710#define TXPRIO 0x0008 /* TX Priority (Priority/Mailbox*) */
1711#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
1712#define SMR 0x0020 /* Sleep Mode Request */
1713#define CSR 0x0040 /* CAN Suspend Mode Request */
1714#define CCR 0x0080 /* CAN Configuration Mode Request */
1715
1716/* CAN_STATUS Masks */
1717#define WT 0x0001 /* TX Warning Flag */
1718#define WR 0x0002 /* RX Warning Flag */
1719#define EP 0x0004 /* Error Passive Mode */
1720#define EBO 0x0008 /* Error Bus Off Mode */
1721#define SMA 0x0020 /* Sleep Mode Acknowledge */
1722#define CSA 0x0040 /* Suspend Mode Acknowledge */
1723#define CCA 0x0080 /* Configuration Mode Acknowledge */
1724#define MBPTR 0x1F00 /* Mailbox Pointer */
1725#define TRM 0x4000 /* Transmit Mode */
1726#define REC 0x8000 /* Receive Mode */
1727
1728/* CAN_CLOCK Masks */
1729#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
1730
1731/* CAN_TIMING Masks */
1732#define TSEG1 0x000F /* Time Segment 1 */
1733#define TSEG2 0x0070 /* Time Segment 2 */
1734#define SAM 0x0080 /* Sampling */
1735#define SJW 0x0300 /* Synchronization Jump Width */
1736
1737/* CAN_DEBUG Masks */
1738#define DEC 0x0001 /* Disable CAN Error Counters */
1739#define DRI 0x0002 /* Disable CAN RX Input */
1740#define DTO 0x0004 /* Disable CAN TX Output */
1741#define DIL 0x0008 /* Disable CAN Internal Loop */
1742#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
1743#define MRB 0x0020 /* Mode Read Back Enable */
1744#define CDE 0x8000 /* CAN Debug Enable */
1745
1746/* CAN_CEC Masks */
1747#define RXECNT 0x00FF /* Receive Error Counter */
1748#define TXECNT 0xFF00 /* Transmit Error Counter */
1749
1750/* CAN_INTR Masks */
1751#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
1752#define MBRIF MBRIRQ /* legacy */
1753#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
1754#define MBTIF MBTIRQ /* legacy */
1755#define GIRQ 0x0004 /* Global Interrupt */
1756#define SMACK 0x0008 /* Sleep Mode Acknowledge */
1757#define CANTX 0x0040 /* CAN TX Bus Value */
1758#define CANRX 0x0080 /* CAN RX Bus Value */
1759
1760/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
1761#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
1762#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
1763#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
1764#define BASEID 0x1FFC /* Base Identifier */
1765#define IDE 0x2000 /* Identifier Extension */
1766#define RTR 0x4000 /* Remote Frame Transmission Request */
1767#define AME 0x8000 /* Acceptance Mask Enable */
1768
1769/* CAN_MBxx_TIMESTAMP Masks */
1770#define TSV 0xFFFF /* Timestamp */
1771
1772/* CAN_MBxx_LENGTH Masks */
1773#define DLC 0x000F /* Data Length Code */
1774
1775/* CAN_AMxxH and CAN_AMxxL Masks */
1776#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
1777#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
1778#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
1779#define BASEID 0x1FFC /* Base Identifier */
1780#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
1781#define FMD 0x4000 /* Full Mask Data Field Enable */
1782#define FDF 0x8000 /* Filter On Data Field Enable */
1783
1784/* CAN_MC1 Masks */
1785#define MC0 0x0001 /* Enable Mailbox 0 */
1786#define MC1 0x0002 /* Enable Mailbox 1 */
1787#define MC2 0x0004 /* Enable Mailbox 2 */
1788#define MC3 0x0008 /* Enable Mailbox 3 */
1789#define MC4 0x0010 /* Enable Mailbox 4 */
1790#define MC5 0x0020 /* Enable Mailbox 5 */
1791#define MC6 0x0040 /* Enable Mailbox 6 */
1792#define MC7 0x0080 /* Enable Mailbox 7 */
1793#define MC8 0x0100 /* Enable Mailbox 8 */
1794#define MC9 0x0200 /* Enable Mailbox 9 */
1795#define MC10 0x0400 /* Enable Mailbox 10 */
1796#define MC11 0x0800 /* Enable Mailbox 11 */
1797#define MC12 0x1000 /* Enable Mailbox 12 */
1798#define MC13 0x2000 /* Enable Mailbox 13 */
1799#define MC14 0x4000 /* Enable Mailbox 14 */
1800#define MC15 0x8000 /* Enable Mailbox 15 */
1801
1802/* CAN_MC2 Masks */
1803#define MC16 0x0001 /* Enable Mailbox 16 */
1804#define MC17 0x0002 /* Enable Mailbox 17 */
1805#define MC18 0x0004 /* Enable Mailbox 18 */
1806#define MC19 0x0008 /* Enable Mailbox 19 */
1807#define MC20 0x0010 /* Enable Mailbox 20 */
1808#define MC21 0x0020 /* Enable Mailbox 21 */
1809#define MC22 0x0040 /* Enable Mailbox 22 */
1810#define MC23 0x0080 /* Enable Mailbox 23 */
1811#define MC24 0x0100 /* Enable Mailbox 24 */
1812#define MC25 0x0200 /* Enable Mailbox 25 */
1813#define MC26 0x0400 /* Enable Mailbox 26 */
1814#define MC27 0x0800 /* Enable Mailbox 27 */
1815#define MC28 0x1000 /* Enable Mailbox 28 */
1816#define MC29 0x2000 /* Enable Mailbox 29 */
1817#define MC30 0x4000 /* Enable Mailbox 30 */
1818#define MC31 0x8000 /* Enable Mailbox 31 */
1819
1820/* CAN_MD1 Masks */
1821#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
1822#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
1823#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
1824#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
1825#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
1826#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
1827#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
1828#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
1829#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
1830#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
1831#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
1832#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
1833#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
1834#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
1835#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
1836#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
1837
1838/* CAN_MD2 Masks */
1839#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
1840#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
1841#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
1842#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
1843#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
1844#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
1845#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
1846#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
1847#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
1848#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
1849#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
1850#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
1851#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
1852#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
1853#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
1854#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
1855
1856/* CAN_RMP1 Masks */
1857#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
1858#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
1859#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
1860#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
1861#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
1862#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
1863#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
1864#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
1865#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
1866#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
1867#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
1868#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
1869#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
1870#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
1871#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
1872#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
1873
1874/* CAN_RMP2 Masks */
1875#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
1876#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
1877#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
1878#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
1879#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
1880#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
1881#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
1882#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
1883#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
1884#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
1885#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
1886#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
1887#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
1888#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
1889#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
1890#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
1891
1892/* CAN_RML1 Masks */
1893#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
1894#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
1895#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
1896#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
1897#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
1898#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
1899#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
1900#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
1901#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
1902#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
1903#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
1904#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
1905#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
1906#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
1907#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
1908#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
1909
1910/* CAN_RML2 Masks */
1911#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
1912#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
1913#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
1914#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
1915#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
1916#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
1917#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
1918#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
1919#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
1920#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
1921#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
1922#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
1923#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
1924#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
1925#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
1926#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
1927
1928/* CAN_OPSS1 Masks */
1929#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
1930#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
1931#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
1932#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
1933#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
1934#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
1935#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
1936#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
1937#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
1938#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
1939#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
1940#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
1941#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
1942#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
1943#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
1944#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
1945
1946/* CAN_OPSS2 Masks */
1947#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
1948#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
1949#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
1950#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
1951#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
1952#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
1953#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
1954#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
1955#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
1956#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
1957#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
1958#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
1959#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
1960#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
1961#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
1962#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
1963
1964/* CAN_TRR1 Masks */
1965#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
1966#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
1967#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
1968#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
1969#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
1970#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
1971#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
1972#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
1973#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
1974#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
1975#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
1976#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
1977#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
1978#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
1979#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
1980#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
1981
1982/* CAN_TRR2 Masks */
1983#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
1984#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
1985#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
1986#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
1987#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
1988#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
1989#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
1990#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
1991#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
1992#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
1993#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
1994#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
1995#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
1996#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
1997#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
1998#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
1999
2000/* CAN_TRS1 Masks */
2001#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
2002#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
2003#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
2004#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
2005#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
2006#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
2007#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
2008#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
2009#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
2010#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
2011#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
2012#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
2013#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
2014#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
2015#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
2016#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
2017
2018/* CAN_TRS2 Masks */
2019#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
2020#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
2021#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
2022#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
2023#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
2024#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
2025#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
2026#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
2027#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
2028#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
2029#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
2030#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
2031#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
2032#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
2033#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
2034#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
2035
2036/* CAN_AA1 Masks */
2037#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
2038#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
2039#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
2040#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
2041#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
2042#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
2043#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
2044#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
2045#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
2046#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
2047#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
2048#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
2049#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
2050#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
2051#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
2052#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
2053
2054/* CAN_AA2 Masks */
2055#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
2056#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
2057#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
2058#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
2059#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
2060#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
2061#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
2062#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
2063#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
2064#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
2065#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
2066#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
2067#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
2068#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
2069#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
2070#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
2071
2072/* CAN_TA1 Masks */
2073#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
2074#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
2075#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
2076#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
2077#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
2078#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
2079#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
2080#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
2081#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
2082#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
2083#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
2084#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
2085#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
2086#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
2087#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
2088#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
2089
2090/* CAN_TA2 Masks */
2091#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
2092#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
2093#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
2094#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
2095#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
2096#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
2097#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
2098#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
2099#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
2100#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
2101#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
2102#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
2103#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
2104#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
2105#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
2106#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
2107
2108/* CAN_MBTD Masks */
2109#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
2110#define TDA 0x0040 /* Temporary Disable Acknowledge */
2111#define TDR 0x0080 /* Temporary Disable Request */
2112
2113/* CAN_RFH1 Masks */
2114#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
2115#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
2116#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
2117#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
2118#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
2119#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
2120#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
2121#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
2122#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
2123#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
2124#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
2125#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
2126#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
2127#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
2128#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
2129#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
2130
2131/* CAN_RFH2 Masks */
2132#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
2133#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
2134#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
2135#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
2136#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
2137#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
2138#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
2139#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
2140#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
2141#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
2142#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
2143#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
2144#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
2145#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
2146#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
2147#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
2148
2149/* CAN_MBTIF1 Masks */
2150#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
2151#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
2152#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
2153#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
2154#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
2155#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
2156#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
2157#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
2158#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
2159#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
2160#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
2161#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
2162#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
2163#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
2164#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
2165#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
2166
2167/* CAN_MBTIF2 Masks */
2168#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
2169#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
2170#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
2171#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
2172#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
2173#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
2174#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
2175#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
2176#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
2177#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
2178#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
2179#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
2180#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
2181#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
2182#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
2183#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
2184
2185/* CAN_MBRIF1 Masks */
2186#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
2187#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
2188#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
2189#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
2190#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
2191#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
2192#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
2193#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
2194#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
2195#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
2196#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
2197#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
2198#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
2199#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
2200#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
2201#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
2202
2203/* CAN_MBRIF2 Masks */
2204#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
2205#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
2206#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
2207#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
2208#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
2209#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
2210#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
2211#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
2212#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
2213#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
2214#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
2215#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
2216#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
2217#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
2218#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
2219#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
2220
2221/* CAN_MBIM1 Masks */
2222#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
2223#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
2224#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
2225#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
2226#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
2227#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
2228#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
2229#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
2230#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
2231#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
2232#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
2233#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
2234#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
2235#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
2236#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
2237#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
2238
2239/* CAN_MBIM2 Masks */
2240#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
2241#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
2242#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
2243#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
2244#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
2245#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
2246#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
2247#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
2248#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
2249#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
2250#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
2251#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
2252#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
2253#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
2254#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
2255#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
2256
2257/* CAN_GIM Masks */
2258#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
2259#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
2260#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
2261#define BOIM 0x0008 /* Enable Bus Off Interrupt */
2262#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
2263#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
2264#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
2265#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
2266#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
2267#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
2268#define ADIM 0x0400 /* Enable Access Denied Interrupt */
2269
2270/* CAN_GIS Masks */
2271#define EWTIS 0x0001 /* TX Error Count IRQ Status */
2272#define EWRIS 0x0002 /* RX Error Count IRQ Status */
2273#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
2274#define BOIS 0x0008 /* Bus Off IRQ Status */
2275#define WUIS 0x0010 /* Wake-Up IRQ Status */
2276#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
2277#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
2278#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
2279#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
2280#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
2281#define ADIS 0x0400 /* Access Denied IRQ Status */
2282
2283/* CAN_GIF Masks */
2284#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
2285#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
2286#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
2287#define BOIF 0x0008 /* Bus Off IRQ Flag */
2288#define WUIF 0x0010 /* Wake-Up IRQ Flag */
2289#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
2290#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
2291#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
2292#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
2293#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
2294#define ADIF 0x0400 /* Access Denied IRQ Flag */
2295
2296/* CAN_UCCNF Masks */
2297#define UCCNF 0x000F /* Universal Counter Mode */
2298#define UC_STAMP 0x0001 /* Timestamp Mode */
2299#define UC_WDOG 0x0002 /* Watchdog Mode */
2300#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
2301#define UC_ERROR 0x0006 /* CAN Error Frame Count */
2302#define UC_OVER 0x0007 /* CAN Overload Frame Count */
2303#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
2304#define UC_AA 0x0009 /* TX Abort Count */
2305#define UC_TA 0x000A /* TX Successful Count */
2306#define UC_REJECT 0x000B /* RX Message Rejected Count */
2307#define UC_RML 0x000C /* RX Message Lost Count */
2308#define UC_RX 0x000D /* Total Successful RX Messages Count */
2309#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
2310#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
2311#define UCRC 0x0020 /* Universal Counter Reload/Clear */
2312#define UCCT 0x0040 /* Universal Counter CAN Trigger */
2313#define UCE 0x0080 /* Universal Counter Enable */
2314
2315/* CAN_ESR Masks */
2316#define ACKE 0x0004 /* Acknowledge Error */
2317#define SER 0x0008 /* Stuff Error */
2318#define CRCE 0x0010 /* CRC Error */
2319#define SA0 0x0020 /* Stuck At Dominant Error */
2320#define BEF 0x0040 /* Bit Error Flag */
2321#define FER 0x0080 /* Form Error Flag */
2322
2323/* CAN_EWR Masks */
2324#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
2325#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
2326
2327/* ******************* PIN CONTROL REGISTER MASKS ************************/ 1705/* ******************* PIN CONTROL REGISTER MASKS ************************/
2328/* PORT_MUX Masks */ 1706/* PORT_MUX Masks */
2329#define PJSE 0x0001 /* Port J SPI/SPORT Enable */ 1707#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 789a4f226f7b..1a6d617c5fcf 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -74,7 +74,7 @@
74 74
75#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */ 75#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
76#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */ 76#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
77#define IRQ_MAC_ERROR 44 /*PPI Error Interrupt */ 77#define IRQ_MAC_ERROR 44 /*MAC Status/Error Interrupt */
78#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */ 78#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */
79#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */ 79#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */
80#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */ 80#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index fac563e6f62f..d7061d9f2a83 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -2418,625 +2418,4 @@
2418#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ 2418#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
2419#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ 2419#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
2420 2420
2421
2422/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
2423/* CAN_CONTROL Masks */
2424#define SRS 0x0001 /* Software Reset */
2425#define DNM 0x0002 /* Device Net Mode */
2426#define ABO 0x0004 /* Auto-Bus On Enable */
2427#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
2428#define SMR 0x0020 /* Sleep Mode Request */
2429#define CSR 0x0040 /* CAN Suspend Mode Request */
2430#define CCR 0x0080 /* CAN Configuration Mode Request */
2431
2432/* CAN_STATUS Masks */
2433#define WT 0x0001 /* TX Warning Flag */
2434#define WR 0x0002 /* RX Warning Flag */
2435#define EP 0x0004 /* Error Passive Mode */
2436#define EBO 0x0008 /* Error Bus Off Mode */
2437#define CSA 0x0040 /* Suspend Mode Acknowledge */
2438#define CCA 0x0080 /* Configuration Mode Acknowledge */
2439#define MBPTR 0x1F00 /* Mailbox Pointer */
2440#define TRM 0x4000 /* Transmit Mode */
2441#define REC 0x8000 /* Receive Mode */
2442
2443/* CAN_CLOCK Masks */
2444#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
2445
2446/* CAN_TIMING Masks */
2447#define TSEG1 0x000F /* Time Segment 1 */
2448#define TSEG2 0x0070 /* Time Segment 2 */
2449#define SAM 0x0080 /* Sampling */
2450#define SJW 0x0300 /* Synchronization Jump Width */
2451
2452/* CAN_DEBUG Masks */
2453#define DEC 0x0001 /* Disable CAN Error Counters */
2454#define DRI 0x0002 /* Disable CAN RX Input */
2455#define DTO 0x0004 /* Disable CAN TX Output */
2456#define DIL 0x0008 /* Disable CAN Internal Loop */
2457#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
2458#define MRB 0x0020 /* Mode Read Back Enable */
2459#define CDE 0x8000 /* CAN Debug Enable */
2460
2461/* CAN_CEC Masks */
2462#define RXECNT 0x00FF /* Receive Error Counter */
2463#define TXECNT 0xFF00 /* Transmit Error Counter */
2464
2465/* CAN_INTR Masks */
2466#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
2467#define MBRIF MBRIRQ /* legacy */
2468#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
2469#define MBTIF MBTIRQ /* legacy */
2470#define GIRQ 0x0004 /* Global Interrupt */
2471#define SMACK 0x0008 /* Sleep Mode Acknowledge */
2472#define CANTX 0x0040 /* CAN TX Bus Value */
2473#define CANRX 0x0080 /* CAN RX Bus Value */
2474
2475/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
2476#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
2477#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
2478#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
2479#define BASEID 0x1FFC /* Base Identifier */
2480#define IDE 0x2000 /* Identifier Extension */
2481#define RTR 0x4000 /* Remote Frame Transmission Request */
2482#define AME 0x8000 /* Acceptance Mask Enable */
2483
2484/* CAN_MBxx_TIMESTAMP Masks */
2485#define TSV 0xFFFF /* Timestamp */
2486
2487/* CAN_MBxx_LENGTH Masks */
2488#define DLC 0x000F /* Data Length Code */
2489
2490/* CAN_AMxxH and CAN_AMxxL Masks */
2491#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
2492#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
2493#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
2494#define BASEID 0x1FFC /* Base Identifier */
2495#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
2496#define FMD 0x4000 /* Full Mask Data Field Enable */
2497#define FDF 0x8000 /* Filter On Data Field Enable */
2498
2499/* CAN_MC1 Masks */
2500#define MC0 0x0001 /* Enable Mailbox 0 */
2501#define MC1 0x0002 /* Enable Mailbox 1 */
2502#define MC2 0x0004 /* Enable Mailbox 2 */
2503#define MC3 0x0008 /* Enable Mailbox 3 */
2504#define MC4 0x0010 /* Enable Mailbox 4 */
2505#define MC5 0x0020 /* Enable Mailbox 5 */
2506#define MC6 0x0040 /* Enable Mailbox 6 */
2507#define MC7 0x0080 /* Enable Mailbox 7 */
2508#define MC8 0x0100 /* Enable Mailbox 8 */
2509#define MC9 0x0200 /* Enable Mailbox 9 */
2510#define MC10 0x0400 /* Enable Mailbox 10 */
2511#define MC11 0x0800 /* Enable Mailbox 11 */
2512#define MC12 0x1000 /* Enable Mailbox 12 */
2513#define MC13 0x2000 /* Enable Mailbox 13 */
2514#define MC14 0x4000 /* Enable Mailbox 14 */
2515#define MC15 0x8000 /* Enable Mailbox 15 */
2516
2517/* CAN_MC2 Masks */
2518#define MC16 0x0001 /* Enable Mailbox 16 */
2519#define MC17 0x0002 /* Enable Mailbox 17 */
2520#define MC18 0x0004 /* Enable Mailbox 18 */
2521#define MC19 0x0008 /* Enable Mailbox 19 */
2522#define MC20 0x0010 /* Enable Mailbox 20 */
2523#define MC21 0x0020 /* Enable Mailbox 21 */
2524#define MC22 0x0040 /* Enable Mailbox 22 */
2525#define MC23 0x0080 /* Enable Mailbox 23 */
2526#define MC24 0x0100 /* Enable Mailbox 24 */
2527#define MC25 0x0200 /* Enable Mailbox 25 */
2528#define MC26 0x0400 /* Enable Mailbox 26 */
2529#define MC27 0x0800 /* Enable Mailbox 27 */
2530#define MC28 0x1000 /* Enable Mailbox 28 */
2531#define MC29 0x2000 /* Enable Mailbox 29 */
2532#define MC30 0x4000 /* Enable Mailbox 30 */
2533#define MC31 0x8000 /* Enable Mailbox 31 */
2534
2535/* CAN_MD1 Masks */
2536#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
2537#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
2538#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
2539#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
2540#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
2541#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
2542#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
2543#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
2544#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
2545#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
2546#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
2547#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
2548#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
2549#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
2550#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
2551#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
2552
2553/* CAN_MD2 Masks */
2554#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
2555#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
2556#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
2557#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
2558#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
2559#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
2560#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
2561#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
2562#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
2563#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
2564#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
2565#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
2566#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
2567#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
2568#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
2569#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
2570
2571/* CAN_RMP1 Masks */
2572#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
2573#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
2574#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
2575#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
2576#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
2577#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
2578#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
2579#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
2580#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
2581#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
2582#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
2583#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
2584#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
2585#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
2586#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
2587#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
2588
2589/* CAN_RMP2 Masks */
2590#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
2591#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
2592#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
2593#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
2594#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
2595#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
2596#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
2597#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
2598#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
2599#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
2600#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
2601#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
2602#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
2603#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
2604#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
2605#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
2606
2607/* CAN_RML1 Masks */
2608#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
2609#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
2610#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
2611#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
2612#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
2613#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
2614#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
2615#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
2616#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
2617#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
2618#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
2619#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
2620#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
2621#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
2622#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
2623#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
2624
2625/* CAN_RML2 Masks */
2626#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
2627#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
2628#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
2629#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
2630#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
2631#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
2632#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
2633#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
2634#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
2635#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
2636#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
2637#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
2638#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
2639#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
2640#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
2641#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
2642
2643/* CAN_OPSS1 Masks */
2644#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
2645#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
2646#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
2647#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
2648#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
2649#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
2650#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
2651#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
2652#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
2653#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
2654#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
2655#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
2656#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
2657#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
2658#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
2659#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
2660
2661/* CAN_OPSS2 Masks */
2662#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
2663#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
2664#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
2665#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
2666#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
2667#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
2668#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
2669#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
2670#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
2671#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
2672#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
2673#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
2674#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
2675#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
2676#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
2677#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
2678
2679/* CAN_TRR1 Masks */
2680#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
2681#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
2682#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
2683#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
2684#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
2685#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
2686#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
2687#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
2688#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
2689#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
2690#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
2691#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
2692#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
2693#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
2694#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
2695#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
2696
2697/* CAN_TRR2 Masks */
2698#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
2699#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
2700#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
2701#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
2702#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
2703#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
2704#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
2705#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
2706#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
2707#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
2708#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
2709#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
2710#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
2711#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
2712#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
2713#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
2714
2715/* CAN_TRS1 Masks */
2716#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
2717#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
2718#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
2719#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
2720#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
2721#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
2722#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
2723#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
2724#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
2725#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
2726#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
2727#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
2728#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
2729#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
2730#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
2731#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
2732
2733/* CAN_TRS2 Masks */
2734#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
2735#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
2736#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
2737#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
2738#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
2739#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
2740#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
2741#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
2742#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
2743#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
2744#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
2745#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
2746#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
2747#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
2748#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
2749#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
2750
2751/* CAN_AA1 Masks */
2752#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
2753#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
2754#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
2755#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
2756#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
2757#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
2758#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
2759#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
2760#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
2761#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
2762#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
2763#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
2764#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
2765#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
2766#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
2767#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
2768
2769/* CAN_AA2 Masks */
2770#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
2771#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
2772#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
2773#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
2774#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
2775#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
2776#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
2777#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
2778#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
2779#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
2780#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
2781#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
2782#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
2783#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
2784#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
2785#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
2786
2787/* CAN_TA1 Masks */
2788#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
2789#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
2790#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
2791#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
2792#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
2793#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
2794#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
2795#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
2796#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
2797#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
2798#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
2799#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
2800#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
2801#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
2802#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
2803#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
2804
2805/* CAN_TA2 Masks */
2806#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
2807#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
2808#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
2809#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
2810#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
2811#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
2812#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
2813#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
2814#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
2815#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
2816#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
2817#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
2818#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
2819#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
2820#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
2821#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
2822
2823/* CAN_MBTD Masks */
2824#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
2825#define TDA 0x0040 /* Temporary Disable Acknowledge */
2826#define TDR 0x0080 /* Temporary Disable Request */
2827
2828/* CAN_RFH1 Masks */
2829#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
2830#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
2831#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
2832#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
2833#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
2834#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
2835#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
2836#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
2837#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
2838#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
2839#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
2840#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
2841#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
2842#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
2843#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
2844#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
2845
2846/* CAN_RFH2 Masks */
2847#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
2848#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
2849#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
2850#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
2851#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
2852#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
2853#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
2854#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
2855#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
2856#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
2857#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
2858#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
2859#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
2860#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
2861#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
2862#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
2863
2864/* CAN_MBTIF1 Masks */
2865#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
2866#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
2867#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
2868#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
2869#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
2870#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
2871#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
2872#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
2873#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
2874#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
2875#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
2876#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
2877#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
2878#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
2879#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
2880#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
2881
2882/* CAN_MBTIF2 Masks */
2883#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
2884#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
2885#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
2886#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
2887#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
2888#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
2889#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
2890#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
2891#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
2892#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
2893#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
2894#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
2895#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
2896#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
2897#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
2898#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
2899
2900/* CAN_MBRIF1 Masks */
2901#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
2902#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
2903#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
2904#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
2905#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
2906#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
2907#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
2908#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
2909#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
2910#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
2911#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
2912#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
2913#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
2914#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
2915#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
2916#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
2917
2918/* CAN_MBRIF2 Masks */
2919#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
2920#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
2921#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
2922#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
2923#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
2924#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
2925#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
2926#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
2927#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
2928#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
2929#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
2930#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
2931#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
2932#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
2933#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
2934#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
2935
2936/* CAN_MBIM1 Masks */
2937#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
2938#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
2939#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
2940#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
2941#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
2942#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
2943#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
2944#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
2945#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
2946#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
2947#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
2948#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
2949#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
2950#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
2951#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
2952#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
2953
2954/* CAN_MBIM2 Masks */
2955#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
2956#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
2957#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
2958#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
2959#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
2960#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
2961#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
2962#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
2963#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
2964#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
2965#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
2966#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
2967#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
2968#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
2969#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
2970#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
2971
2972/* CAN_GIM Masks */
2973#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
2974#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
2975#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
2976#define BOIM 0x0008 /* Enable Bus Off Interrupt */
2977#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
2978#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
2979#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
2980#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
2981#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
2982#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
2983#define ADIM 0x0400 /* Enable Access Denied Interrupt */
2984
2985/* CAN_GIS Masks */
2986#define EWTIS 0x0001 /* TX Error Count IRQ Status */
2987#define EWRIS 0x0002 /* RX Error Count IRQ Status */
2988#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
2989#define BOIS 0x0008 /* Bus Off IRQ Status */
2990#define WUIS 0x0010 /* Wake-Up IRQ Status */
2991#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
2992#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
2993#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
2994#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
2995#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
2996#define ADIS 0x0400 /* Access Denied IRQ Status */
2997
2998/* CAN_GIF Masks */
2999#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
3000#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
3001#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
3002#define BOIF 0x0008 /* Bus Off IRQ Flag */
3003#define WUIF 0x0010 /* Wake-Up IRQ Flag */
3004#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
3005#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
3006#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
3007#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
3008#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
3009#define ADIF 0x0400 /* Access Denied IRQ Flag */
3010
3011/* CAN_UCCNF Masks */
3012#define UCCNF 0x000F /* Universal Counter Mode */
3013#define UC_STAMP 0x0001 /* Timestamp Mode */
3014#define UC_WDOG 0x0002 /* Watchdog Mode */
3015#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
3016#define UC_ERROR 0x0006 /* CAN Error Frame Count */
3017#define UC_OVER 0x0007 /* CAN Overload Frame Count */
3018#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
3019#define UC_AA 0x0009 /* TX Abort Count */
3020#define UC_TA 0x000A /* TX Successful Count */
3021#define UC_REJECT 0x000B /* RX Message Rejected Count */
3022#define UC_RML 0x000C /* RX Message Lost Count */
3023#define UC_RX 0x000D /* Total Successful RX Messages Count */
3024#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
3025#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
3026#define UCRC 0x0020 /* Universal Counter Reload/Clear */
3027#define UCCT 0x0040 /* Universal Counter CAN Trigger */
3028#define UCE 0x0080 /* Universal Counter Enable */
3029
3030/* CAN_ESR Masks */
3031#define ACKE 0x0004 /* Acknowledge Error */
3032#define SER 0x0008 /* Stuff Error */
3033#define CRCE 0x0010 /* CRC Error */
3034#define SA0 0x0020 /* Stuck At Dominant Error */
3035#define BEF 0x0040 /* Bit Error Flag */
3036#define FER 0x0080 /* Form Error Flag */
3037
3038/* CAN_EWR Masks */
3039#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
3040#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
3041
3042#endif /* _DEF_BF539_H */ 2421#endif /* _DEF_BF539_H */
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index f60c333fec66..dbb6b1d83f6d 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -498,6 +498,10 @@ static struct musb_hdrc_config musb_config = {
498 .num_eps = 8, 498 .num_eps = 8,
499 .dma_channels = 8, 499 .dma_channels = 8,
500 .gpio_vrsel = GPIO_PH6, 500 .gpio_vrsel = GPIO_PH6,
501 /* Some custom boards need to be active low, just set it to "0"
502 * if it is the case.
503 */
504 .gpio_vrsel_active = 1,
501}; 505};
502 506
503static struct musb_hdrc_platform_data musb_plat = { 507static struct musb_hdrc_platform_data musb_plat = {
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 06919db00a74..6fcfb9187c35 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -603,6 +603,10 @@ static struct musb_hdrc_config musb_config = {
603 .num_eps = 8, 603 .num_eps = 8,
604 .dma_channels = 8, 604 .dma_channels = 8,
605 .gpio_vrsel = GPIO_PE7, 605 .gpio_vrsel = GPIO_PE7,
606 /* Some custom boards need to be active low, just set it to "0"
607 * if it is the case.
608 */
609 .gpio_vrsel_active = 1,
606}; 610};
607 611
608static struct musb_hdrc_platform_data musb_plat = { 612static struct musb_hdrc_platform_data musb_plat = {
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index ab04d137fd8b..0ed06c2366fe 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -2104,677 +2104,6 @@
2104 2104
2105#define ECCCNT 0x3ff /* Transfer Count */ 2105#define ECCCNT 0x3ff /* Transfer Count */
2106 2106
2107/* Bit masks for CAN0_CONTROL */
2108
2109#define SRS 0x1 /* Software Reset */
2110#define DNM 0x2 /* DeviceNet Mode */
2111#define ABO 0x4 /* Auto Bus On */
2112#define WBA 0x10 /* Wakeup On CAN Bus Activity */
2113#define SMR 0x20 /* Sleep Mode Request */
2114#define CSR 0x40 /* CAN Suspend Mode Request */
2115#define CCR 0x80 /* CAN Configuration Mode Request */
2116
2117/* Bit masks for CAN0_STATUS */
2118
2119#define WT 0x1 /* CAN Transmit Warning Flag */
2120#define WR 0x2 /* CAN Receive Warning Flag */
2121#define EP 0x4 /* CAN Error Passive Mode */
2122#define EBO 0x8 /* CAN Error Bus Off Mode */
2123#define CSA 0x40 /* CAN Suspend Mode Acknowledge */
2124#define CCA 0x80 /* CAN Configuration Mode Acknowledge */
2125#define MBPTR 0x1f00 /* Mailbox Pointer */
2126#define TRM 0x4000 /* Transmit Mode Status */
2127#define REC 0x8000 /* Receive Mode Status */
2128
2129/* Bit masks for CAN0_DEBUG */
2130
2131#define DEC 0x1 /* Disable Transmit/Receive Error Counters */
2132#define DRI 0x2 /* Disable CANRX Input Pin */
2133#define DTO 0x4 /* Disable CANTX Output Pin */
2134#define DIL 0x8 /* Disable Internal Loop */
2135#define MAA 0x10 /* Mode Auto-Acknowledge */
2136#define MRB 0x20 /* Mode Read Back */
2137#define CDE 0x8000 /* CAN Debug Mode Enable */
2138
2139/* Bit masks for CAN0_CLOCK */
2140
2141#define BRP 0x3ff /* CAN Bit Rate Prescaler */
2142
2143/* Bit masks for CAN0_TIMING */
2144
2145#define SJW 0x300 /* Synchronization Jump Width */
2146#define SAM 0x80 /* Sampling */
2147#define TSEG2 0x70 /* Time Segment 2 */
2148#define TSEG1 0xf /* Time Segment 1 */
2149
2150/* Bit masks for CAN0_INTR */
2151
2152#define CANRX 0x80 /* Serial Input From Transceiver */
2153#define CANTX 0x40 /* Serial Output To Transceiver */
2154#define SMACK 0x8 /* Sleep Mode Acknowledge */
2155#define GIRQ 0x4 /* Global Interrupt Request Status */
2156#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */
2157#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */
2158
2159/* Bit masks for CAN0_GIM */
2160
2161#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */
2162#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */
2163#define EPIM 0x4 /* Error Passive Interrupt Mask */
2164#define BOIM 0x8 /* Bus Off Interrupt Mask */
2165#define WUIM 0x10 /* Wakeup Interrupt Mask */
2166#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */
2167#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */
2168#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */
2169#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */
2170#define ADIM 0x400 /* Access Denied Interrupt Mask */
2171
2172/* Bit masks for CAN0_GIS */
2173
2174#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */
2175#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */
2176#define EPIS 0x4 /* Error Passive Interrupt Status */
2177#define BOIS 0x8 /* Bus Off Interrupt Status */
2178#define WUIS 0x10 /* Wakeup Interrupt Status */
2179#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */
2180#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */
2181#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */
2182#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */
2183#define ADIS 0x400 /* Access Denied Interrupt Status */
2184
2185/* Bit masks for CAN0_GIF */
2186
2187#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */
2188#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */
2189#define EPIF 0x4 /* Error Passive Interrupt Flag */
2190#define BOIF 0x8 /* Bus Off Interrupt Flag */
2191#define WUIF 0x10 /* Wakeup Interrupt Flag */
2192#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */
2193#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */
2194#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */
2195#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */
2196#define ADIF 0x400 /* Access Denied Interrupt Flag */
2197
2198/* Bit masks for CAN0_MBTD */
2199
2200#define TDR 0x80 /* Temporary Disable Request */
2201#define TDA 0x40 /* Temporary Disable Acknowledge */
2202#define TDPTR 0x1f /* Temporary Disable Pointer */
2203
2204/* Bit masks for CAN0_UCCNF */
2205
2206#define UCCNF 0xf /* Universal Counter Configuration */
2207#define UCRC 0x20 /* Universal Counter Reload/Clear */
2208#define UCCT 0x40 /* Universal Counter CAN Trigger */
2209#define UCE 0x80 /* Universal Counter Enable */
2210
2211/* Bit masks for CAN0_CEC */
2212
2213#define RXECNT 0xff /* Receive Error Counter */
2214#define TXECNT 0xff00 /* Transmit Error Counter */
2215
2216/* Bit masks for CAN0_ESR */
2217
2218#define FER 0x80 /* Form Error */
2219#define BEF 0x40 /* Bit Error Flag */
2220#define SA0 0x20 /* Stuck At Dominant */
2221#define CRCE 0x10 /* CRC Error */
2222#define SER 0x8 /* Stuff Bit Error */
2223#define ACKE 0x4 /* Acknowledge Error */
2224
2225/* Bit masks for CAN0_EWR */
2226
2227#define EWLTEC 0xff00 /* Transmit Error Warning Limit */
2228#define EWLREC 0xff /* Receive Error Warning Limit */
2229
2230/* Bit masks for CAN0_AMxx_H */
2231
2232#define FDF 0x8000 /* Filter On Data Field */
2233#define FMD 0x4000 /* Full Mask Data */
2234#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */
2235#define BASEID 0x1ffc /* Base Identifier */
2236#define EXTID_HI 0x3 /* Extended Identifier High Bits */
2237
2238/* Bit masks for CAN0_AMxx_L */
2239
2240#define EXTID_LO 0xffff /* Extended Identifier Low Bits */
2241#define DFM 0xffff /* Data Field Mask */
2242
2243/* Bit masks for CAN0_MBxx_ID1 */
2244
2245#define AME 0x8000 /* Acceptance Mask Enable */
2246#define RTR 0x4000 /* Remote Transmission Request */
2247#define IDE 0x2000 /* Identifier Extension */
2248#define BASEID 0x1ffc /* Base Identifier */
2249#define EXTID_HI 0x3 /* Extended Identifier High Bits */
2250
2251/* Bit masks for CAN0_MBxx_ID0 */
2252
2253#define EXTID_LO 0xffff /* Extended Identifier Low Bits */
2254#define DFM 0xffff /* Data Field Mask */
2255
2256/* Bit masks for CAN0_MBxx_TIMESTAMP */
2257
2258#define TSV 0xffff /* Time Stamp Value */
2259
2260/* Bit masks for CAN0_MBxx_LENGTH */
2261
2262#define DLC 0xf /* Data Length Code */
2263
2264/* Bit masks for CAN0_MBxx_DATA3 */
2265
2266#define CAN_BYTE0 0xff00 /* Data Field Byte 0 */
2267#define CAN_BYTE1 0xff /* Data Field Byte 1 */
2268
2269/* Bit masks for CAN0_MBxx_DATA2 */
2270
2271#define CAN_BYTE2 0xff00 /* Data Field Byte 2 */
2272#define CAN_BYTE3 0xff /* Data Field Byte 3 */
2273
2274/* Bit masks for CAN0_MBxx_DATA1 */
2275
2276#define CAN_BYTE4 0xff00 /* Data Field Byte 4 */
2277#define CAN_BYTE5 0xff /* Data Field Byte 5 */
2278
2279/* Bit masks for CAN0_MBxx_DATA0 */
2280
2281#define CAN_BYTE6 0xff00 /* Data Field Byte 6 */
2282#define CAN_BYTE7 0xff /* Data Field Byte 7 */
2283
2284/* Bit masks for CAN0_MC1 */
2285
2286#define MC0 0x1 /* Mailbox 0 Enable */
2287#define MC1 0x2 /* Mailbox 1 Enable */
2288#define MC2 0x4 /* Mailbox 2 Enable */
2289#define MC3 0x8 /* Mailbox 3 Enable */
2290#define MC4 0x10 /* Mailbox 4 Enable */
2291#define MC5 0x20 /* Mailbox 5 Enable */
2292#define MC6 0x40 /* Mailbox 6 Enable */
2293#define MC7 0x80 /* Mailbox 7 Enable */
2294#define MC8 0x100 /* Mailbox 8 Enable */
2295#define MC9 0x200 /* Mailbox 9 Enable */
2296#define MC10 0x400 /* Mailbox 10 Enable */
2297#define MC11 0x800 /* Mailbox 11 Enable */
2298#define MC12 0x1000 /* Mailbox 12 Enable */
2299#define MC13 0x2000 /* Mailbox 13 Enable */
2300#define MC14 0x4000 /* Mailbox 14 Enable */
2301#define MC15 0x8000 /* Mailbox 15 Enable */
2302
2303/* Bit masks for CAN0_MC2 */
2304
2305#define MC16 0x1 /* Mailbox 16 Enable */
2306#define MC17 0x2 /* Mailbox 17 Enable */
2307#define MC18 0x4 /* Mailbox 18 Enable */
2308#define MC19 0x8 /* Mailbox 19 Enable */
2309#define MC20 0x10 /* Mailbox 20 Enable */
2310#define MC21 0x20 /* Mailbox 21 Enable */
2311#define MC22 0x40 /* Mailbox 22 Enable */
2312#define MC23 0x80 /* Mailbox 23 Enable */
2313#define MC24 0x100 /* Mailbox 24 Enable */
2314#define MC25 0x200 /* Mailbox 25 Enable */
2315#define MC26 0x400 /* Mailbox 26 Enable */
2316#define MC27 0x800 /* Mailbox 27 Enable */
2317#define MC28 0x1000 /* Mailbox 28 Enable */
2318#define MC29 0x2000 /* Mailbox 29 Enable */
2319#define MC30 0x4000 /* Mailbox 30 Enable */
2320#define MC31 0x8000 /* Mailbox 31 Enable */
2321
2322/* Bit masks for CAN0_MD1 */
2323
2324#define MD0 0x1 /* Mailbox 0 Receive Enable */
2325#define MD1 0x2 /* Mailbox 1 Receive Enable */
2326#define MD2 0x4 /* Mailbox 2 Receive Enable */
2327#define MD3 0x8 /* Mailbox 3 Receive Enable */
2328#define MD4 0x10 /* Mailbox 4 Receive Enable */
2329#define MD5 0x20 /* Mailbox 5 Receive Enable */
2330#define MD6 0x40 /* Mailbox 6 Receive Enable */
2331#define MD7 0x80 /* Mailbox 7 Receive Enable */
2332#define MD8 0x100 /* Mailbox 8 Receive Enable */
2333#define MD9 0x200 /* Mailbox 9 Receive Enable */
2334#define MD10 0x400 /* Mailbox 10 Receive Enable */
2335#define MD11 0x800 /* Mailbox 11 Receive Enable */
2336#define MD12 0x1000 /* Mailbox 12 Receive Enable */
2337#define MD13 0x2000 /* Mailbox 13 Receive Enable */
2338#define MD14 0x4000 /* Mailbox 14 Receive Enable */
2339#define MD15 0x8000 /* Mailbox 15 Receive Enable */
2340
2341/* Bit masks for CAN0_MD2 */
2342
2343#define MD16 0x1 /* Mailbox 16 Receive Enable */
2344#define MD17 0x2 /* Mailbox 17 Receive Enable */
2345#define MD18 0x4 /* Mailbox 18 Receive Enable */
2346#define MD19 0x8 /* Mailbox 19 Receive Enable */
2347#define MD20 0x10 /* Mailbox 20 Receive Enable */
2348#define MD21 0x20 /* Mailbox 21 Receive Enable */
2349#define MD22 0x40 /* Mailbox 22 Receive Enable */
2350#define MD23 0x80 /* Mailbox 23 Receive Enable */
2351#define MD24 0x100 /* Mailbox 24 Receive Enable */
2352#define MD25 0x200 /* Mailbox 25 Receive Enable */
2353#define MD26 0x400 /* Mailbox 26 Receive Enable */
2354#define MD27 0x800 /* Mailbox 27 Receive Enable */
2355#define MD28 0x1000 /* Mailbox 28 Receive Enable */
2356#define MD29 0x2000 /* Mailbox 29 Receive Enable */
2357#define MD30 0x4000 /* Mailbox 30 Receive Enable */
2358#define MD31 0x8000 /* Mailbox 31 Receive Enable */
2359
2360/* Bit masks for CAN0_RMP1 */
2361
2362#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */
2363#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */
2364#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */
2365#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */
2366#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */
2367#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */
2368#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */
2369#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */
2370#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */
2371#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */
2372#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */
2373#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */
2374#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */
2375#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */
2376#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */
2377#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */
2378
2379/* Bit masks for CAN0_RMP2 */
2380
2381#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */
2382#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */
2383#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */
2384#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */
2385#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */
2386#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */
2387#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */
2388#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */
2389#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */
2390#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */
2391#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */
2392#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */
2393#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */
2394#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */
2395#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */
2396#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */
2397
2398/* Bit masks for CAN0_RML1 */
2399
2400#define RML0 0x1 /* Mailbox 0 Receive Message Lost */
2401#define RML1 0x2 /* Mailbox 1 Receive Message Lost */
2402#define RML2 0x4 /* Mailbox 2 Receive Message Lost */
2403#define RML3 0x8 /* Mailbox 3 Receive Message Lost */
2404#define RML4 0x10 /* Mailbox 4 Receive Message Lost */
2405#define RML5 0x20 /* Mailbox 5 Receive Message Lost */
2406#define RML6 0x40 /* Mailbox 6 Receive Message Lost */
2407#define RML7 0x80 /* Mailbox 7 Receive Message Lost */
2408#define RML8 0x100 /* Mailbox 8 Receive Message Lost */
2409#define RML9 0x200 /* Mailbox 9 Receive Message Lost */
2410#define RML10 0x400 /* Mailbox 10 Receive Message Lost */
2411#define RML11 0x800 /* Mailbox 11 Receive Message Lost */
2412#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */
2413#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */
2414#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */
2415#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */
2416
2417/* Bit masks for CAN0_RML2 */
2418
2419#define RML16 0x1 /* Mailbox 16 Receive Message Lost */
2420#define RML17 0x2 /* Mailbox 17 Receive Message Lost */
2421#define RML18 0x4 /* Mailbox 18 Receive Message Lost */
2422#define RML19 0x8 /* Mailbox 19 Receive Message Lost */
2423#define RML20 0x10 /* Mailbox 20 Receive Message Lost */
2424#define RML21 0x20 /* Mailbox 21 Receive Message Lost */
2425#define RML22 0x40 /* Mailbox 22 Receive Message Lost */
2426#define RML23 0x80 /* Mailbox 23 Receive Message Lost */
2427#define RML24 0x100 /* Mailbox 24 Receive Message Lost */
2428#define RML25 0x200 /* Mailbox 25 Receive Message Lost */
2429#define RML26 0x400 /* Mailbox 26 Receive Message Lost */
2430#define RML27 0x800 /* Mailbox 27 Receive Message Lost */
2431#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */
2432#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */
2433#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */
2434#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */
2435
2436/* Bit masks for CAN0_OPSS1 */
2437
2438#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
2439#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
2440#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
2441#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
2442#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
2443#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
2444#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
2445#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
2446#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
2447#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
2448#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
2449#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
2450#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
2451#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
2452#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
2453#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
2454
2455/* Bit masks for CAN0_OPSS2 */
2456
2457#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
2458#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
2459#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
2460#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
2461#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
2462#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
2463#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
2464#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
2465#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
2466#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
2467#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
2468#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
2469#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
2470#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
2471#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
2472#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
2473
2474/* Bit masks for CAN0_TRS1 */
2475
2476#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */
2477#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */
2478#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */
2479#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */
2480#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */
2481#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */
2482#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */
2483#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */
2484#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */
2485#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */
2486#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */
2487#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */
2488#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */
2489#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */
2490#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */
2491#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */
2492
2493/* Bit masks for CAN0_TRS2 */
2494
2495#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */
2496#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */
2497#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */
2498#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */
2499#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */
2500#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */
2501#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */
2502#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */
2503#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */
2504#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */
2505#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */
2506#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */
2507#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */
2508#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */
2509#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */
2510#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */
2511
2512/* Bit masks for CAN0_TRR1 */
2513
2514#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */
2515#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */
2516#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */
2517#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */
2518#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */
2519#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */
2520#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */
2521#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */
2522#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */
2523#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */
2524#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */
2525#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */
2526#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */
2527#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */
2528#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */
2529#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */
2530
2531/* Bit masks for CAN0_TRR2 */
2532
2533#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */
2534#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */
2535#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */
2536#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */
2537#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */
2538#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */
2539#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */
2540#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */
2541#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */
2542#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */
2543#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */
2544#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */
2545#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */
2546#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */
2547#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */
2548#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */
2549
2550/* Bit masks for CAN0_AA1 */
2551
2552#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */
2553#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */
2554#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */
2555#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */
2556#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */
2557#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */
2558#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */
2559#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */
2560#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */
2561#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */
2562#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */
2563#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */
2564#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */
2565#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */
2566#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */
2567#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */
2568
2569/* Bit masks for CAN0_AA2 */
2570
2571#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */
2572#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */
2573#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */
2574#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */
2575#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */
2576#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */
2577#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */
2578#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */
2579#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */
2580#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */
2581#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */
2582#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */
2583#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */
2584#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */
2585#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */
2586#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */
2587
2588/* Bit masks for CAN0_TA1 */
2589
2590#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */
2591#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */
2592#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */
2593#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */
2594#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */
2595#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */
2596#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */
2597#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */
2598#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */
2599#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */
2600#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */
2601#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */
2602#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */
2603#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */
2604#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */
2605#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */
2606
2607/* Bit masks for CAN0_TA2 */
2608
2609#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */
2610#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */
2611#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */
2612#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */
2613#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */
2614#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */
2615#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */
2616#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */
2617#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */
2618#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */
2619#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */
2620#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */
2621#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */
2622#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */
2623#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */
2624#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */
2625
2626/* Bit masks for CAN0_RFH1 */
2627
2628#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */
2629#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */
2630#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */
2631#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */
2632#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */
2633#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */
2634#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */
2635#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */
2636#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */
2637#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */
2638#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */
2639#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */
2640#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */
2641#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */
2642#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */
2643#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */
2644
2645/* Bit masks for CAN0_RFH2 */
2646
2647#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */
2648#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */
2649#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */
2650#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */
2651#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */
2652#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */
2653#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */
2654#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */
2655#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */
2656#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */
2657#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */
2658#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */
2659#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */
2660#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */
2661#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */
2662#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */
2663
2664/* Bit masks for CAN0_MBIM1 */
2665
2666#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */
2667#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */
2668#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */
2669#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */
2670#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */
2671#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */
2672#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */
2673#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */
2674#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */
2675#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */
2676#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */
2677#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */
2678#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */
2679#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */
2680#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */
2681#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */
2682
2683/* Bit masks for CAN0_MBIM2 */
2684
2685#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */
2686#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */
2687#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */
2688#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */
2689#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */
2690#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */
2691#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */
2692#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */
2693#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */
2694#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */
2695#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */
2696#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */
2697#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */
2698#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */
2699#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */
2700#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */
2701
2702/* Bit masks for CAN0_MBTIF1 */
2703
2704#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */
2705#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */
2706#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */
2707#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */
2708#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */
2709#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */
2710#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */
2711#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */
2712#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */
2713#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */
2714#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */
2715#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */
2716#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */
2717#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */
2718#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */
2719#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */
2720
2721/* Bit masks for CAN0_MBTIF2 */
2722
2723#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */
2724#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */
2725#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */
2726#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */
2727#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */
2728#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */
2729#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */
2730#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */
2731#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */
2732#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */
2733#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */
2734#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */
2735#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */
2736#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */
2737#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */
2738#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */
2739
2740/* Bit masks for CAN0_MBRIF1 */
2741
2742#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */
2743#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */
2744#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */
2745#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */
2746#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */
2747#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */
2748#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */
2749#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */
2750#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */
2751#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */
2752#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */
2753#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */
2754#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */
2755#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */
2756#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */
2757#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */
2758
2759/* Bit masks for CAN0_MBRIF2 */
2760
2761#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */
2762#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */
2763#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */
2764#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */
2765#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */
2766#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */
2767#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */
2768#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */
2769#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */
2770#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */
2771#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */
2772#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */
2773#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */
2774#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */
2775#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */
2776#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */
2777
2778/* Bit masks for EPPIx_STATUS */ 2107/* Bit masks for EPPIx_STATUS */
2779 2108
2780#define CFIFO_ERR 0x1 /* Chroma FIFO Error */ 2109#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
index 5163e2c383c5..bfcfa86db2b5 100644
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -44,6 +44,7 @@
44#include <linux/spi/flash.h> 44#include <linux/spi/flash.h>
45#include <linux/irq.h> 45#include <linux/irq.h>
46#include <linux/interrupt.h> 46#include <linux/interrupt.h>
47#include <linux/jiffies.h>
47#include <linux/i2c-pca-platform.h> 48#include <linux/i2c-pca-platform.h>
48#include <linux/delay.h> 49#include <linux/delay.h>
49#include <linux/io.h> 50#include <linux/io.h>
@@ -112,7 +113,7 @@ static struct resource bfin_i2c_pca_resources[] = {
112struct i2c_pca9564_pf_platform_data pca9564_platform_data = { 113struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
113 .gpio = -1, 114 .gpio = -1,
114 .i2c_clock_speed = 330000, 115 .i2c_clock_speed = 330000,
115 .timeout = 10000 116 .timeout = HZ,
116}; 117};
117 118
118/* PCA9564 I2C Bus driver */ 119/* PCA9564 I2C Bus driver */
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 7ad8878bfa18..1c8c4c7245c3 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -92,26 +92,29 @@ static void __init search_IAR(void)
92{ 92{
93 unsigned ivg, irq_pos = 0; 93 unsigned ivg, irq_pos = 0;
94 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { 94 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
95 int irqn; 95 int irqN;
96 96
97 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos]; 97 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
98 98
99 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { 99 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
100 int iar_shift = (irqn & 7) * 4; 100 int irqn;
101 if (ivg == (0xf & 101 u32 iar = bfin_read32((unsigned long *)SIC_IAR0 +
102#if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \ 102#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
103 || defined(CONFIG_BF539) || defined(CONFIG_BF51x) 103 defined(CONFIG_BF538) || defined(CONFIG_BF539)
104 bfin_read32((unsigned long *)SIC_IAR0 + 104 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
105 ((irqn % 32) >> 3) + ((irqn / 32) *
106 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
107#else 105#else
108 bfin_read32((unsigned long *)SIC_IAR0 + 106 (irqN >> 3)
109 (irqn >> 3)) >> iar_shift)) {
110#endif 107#endif
111 ivg_table[irq_pos].irqno = IVG7 + irqn; 108 );
112 ivg_table[irq_pos].isrflag = 1 << (irqn % 32); 109
113 ivg7_13[ivg].istop++; 110 for (irqn = irqN; irqn < irqN + 4; ++irqn) {
114 irq_pos++; 111 int iar_shift = (irqn & 7) * 4;
112 if (ivg == (0xf & (iar >> iar_shift))) {
113 ivg_table[irq_pos].irqno = IVG7 + irqn;
114 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
115 ivg7_13[ivg].istop++;
116 irq_pos++;
117 }
115 } 118 }
116 } 119 }
117 } 120 }
@@ -662,14 +665,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
662#ifdef CONFIG_PM 665#ifdef CONFIG_PM
663int bfin_gpio_set_wake(unsigned int irq, unsigned int state) 666int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
664{ 667{
665 unsigned gpio = irq_to_gpio(irq); 668 return gpio_pm_wakeup_ctrl(irq_to_gpio(irq), state);
666
667 if (state)
668 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
669 else
670 gpio_pm_wakeup_free(gpio);
671
672 return 0;
673} 669}
674#endif 670#endif
675 671
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index c1f1ccc846f0..ea7f95f6bb4c 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -20,35 +20,11 @@
20#include <asm/dma.h> 20#include <asm/dma.h>
21#include <asm/dpmc.h> 21#include <asm/dpmc.h>
22 22
23#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
24#define WAKEUP_TYPE PM_WAKE_HIGH
25#endif
26
27#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_L
28#define WAKEUP_TYPE PM_WAKE_LOW
29#endif
30
31#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_F
32#define WAKEUP_TYPE PM_WAKE_FALLING
33#endif
34
35#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_R
36#define WAKEUP_TYPE PM_WAKE_RISING
37#endif
38
39#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_B
40#define WAKEUP_TYPE PM_WAKE_BOTH_EDGES
41#endif
42
43 23
44void bfin_pm_suspend_standby_enter(void) 24void bfin_pm_suspend_standby_enter(void)
45{ 25{
46 unsigned long flags; 26 unsigned long flags;
47 27
48#ifdef CONFIG_PM_WAKEUP_BY_GPIO
49 gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
50#endif
51
52 local_irq_save_hw(flags); 28 local_irq_save_hw(flags);
53 bfin_pm_standby_setup(); 29 bfin_pm_standby_setup();
54 30
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 7cecbaf0358a..a17107a700d5 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -170,8 +170,8 @@ static irqreturn_t ipi_handler(int irq, void *dev_instance)
170 kfree(msg); 170 kfree(msg);
171 break; 171 break;
172 default: 172 default:
173 printk(KERN_CRIT "CPU%u: Unknown IPI message \ 173 printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
174 0x%lx\n", cpu, msg->type); 174 cpu, msg->type);
175 kfree(msg); 175 kfree(msg);
176 break; 176 break;
177 } 177 }
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 355b87aa6b93..bb4e8fff4b55 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -15,23 +15,11 @@
15#include "blackfin_sram.h" 15#include "blackfin_sram.h"
16 16
17/* 17/*
18 * BAD_PAGE is the page that is used for page faults when linux 18 * ZERO_PAGE is a special page that is used for zero-initialized data and COW.
19 * is out-of-memory. Older versions of linux just did a 19 * Let the bss do its zero-init magic so we don't have to do it ourselves.
20 * do_exit(), but using this instead means there is less risk
21 * for a process dying in kernel mode, possibly leaving a inode
22 * unused etc..
23 *
24 * BAD_PAGETABLE is the accompanying page-table: it is initialized
25 * to point to BAD_PAGE entries.
26 *
27 * ZERO_PAGE is a special page that is used for zero-initialized
28 * data and COW.
29 */ 20 */
30static unsigned long empty_bad_page_table; 21char empty_zero_page[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE)));
31 22EXPORT_SYMBOL(empty_zero_page);
32static unsigned long empty_bad_page;
33
34static unsigned long empty_zero_page;
35 23
36#ifndef CONFIG_EXCEPTION_L1_SCRATCH 24#ifndef CONFIG_EXCEPTION_L1_SCRATCH
37#if defined CONFIG_SYSCALL_TAB_L1 25#if defined CONFIG_SYSCALL_TAB_L1
@@ -52,40 +40,26 @@ EXPORT_SYMBOL(cpu_pda);
52void __init paging_init(void) 40void __init paging_init(void)
53{ 41{
54 /* 42 /*
55 * make sure start_mem is page aligned, otherwise bootmem and 43 * make sure start_mem is page aligned, otherwise bootmem and
56 * page_alloc get different views og the world 44 * page_alloc get different views of the world
57 */ 45 */
58 unsigned long end_mem = memory_end & PAGE_MASK; 46 unsigned long end_mem = memory_end & PAGE_MASK;
59 47
60 pr_debug("start_mem is %#lx virtual_end is %#lx\n", PAGE_ALIGN(memory_start), end_mem); 48 unsigned long zones_size[MAX_NR_ZONES] = {
61 49 [0] = 0,
62 /* 50 [ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT,
63 * initialize the bad page table and bad page to point 51 [ZONE_NORMAL] = 0,
64 * to a couple of allocated pages 52#ifdef CONFIG_HIGHMEM
65 */ 53 [ZONE_HIGHMEM] = 0,
66 empty_bad_page_table = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); 54#endif
67 empty_bad_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); 55 };
68 empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
69 memset((void *)empty_zero_page, 0, PAGE_SIZE);
70 56
71 /* 57 /* Set up SFC/DFC registers (user data space) */
72 * Set up SFC/DFC registers (user data space)
73 */
74 set_fs(KERNEL_DS); 58 set_fs(KERNEL_DS);
75 59
76 pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n", 60 pr_debug("free_area_init -> start_mem is %#lx virtual_end is %#lx\n",
77 PAGE_ALIGN(memory_start), end_mem); 61 PAGE_ALIGN(memory_start), end_mem);
78 62 free_area_init(zones_size);
79 {
80 unsigned long zones_size[MAX_NR_ZONES] = { 0, };
81
82 zones_size[ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT;
83 zones_size[ZONE_NORMAL] = 0;
84#ifdef CONFIG_HIGHMEM
85 zones_size[ZONE_HIGHMEM] = 0;
86#endif
87 free_area_init(zones_size);
88 }
89} 63}
90 64
91asmlinkage void __init init_pda(void) 65asmlinkage void __init init_pda(void)
diff --git a/arch/blackfin/mm/isram-driver.c b/arch/blackfin/mm/isram-driver.c
index 39b058564f62..7e2e674ed444 100644
--- a/arch/blackfin/mm/isram-driver.c
+++ b/arch/blackfin/mm/isram-driver.c
@@ -43,13 +43,12 @@ static DEFINE_SPINLOCK(dtest_lock);
43/* Takes a void pointer */ 43/* Takes a void pointer */
44#define IADDR2DTEST(x) \ 44#define IADDR2DTEST(x) \
45 ({ unsigned long __addr = (unsigned long)(x); \ 45 ({ unsigned long __addr = (unsigned long)(x); \
46 (__addr & 0x47F8) | /* address bits 14 & 10:3 */ \ 46 ((__addr & (1 << 11)) << (26 - 11)) | /* addr bit 11 (Way0/Way1) */ \
47 (__addr & 0x8000) << 23 | /* Bank A/B */ \ 47 (1 << 24) | /* instruction access = 1 */ \
48 (__addr & 0x0800) << 15 | /* address bit 11 */ \ 48 ((__addr & (1 << 15)) << (23 - 15)) | /* addr bit 15 (Data Bank) */ \
49 (__addr & 0x3000) << 4 | /* address bits 13:12 */ \ 49 ((__addr & (3 << 12)) << (16 - 12)) | /* addr bits 13:12 (Subbank) */ \
50 (__addr & 0x8000) << 8 | /* address bit 15 */ \ 50 (__addr & 0x47F8) | /* addr bits 14 & 10:3 */ \
51 (0x1000000) | /* instruction access = 1 */ \ 51 (1 << 2); /* data array = 1 */ \
52 (0x4); /* data array = 1 */ \
53 }) 52 })
54 53
55/* Takes a pointer, and returns the offset (in bits) which things should be shifted */ 54/* Takes a pointer, and returns the offset (in bits) which things should be shifted */
@@ -196,7 +195,7 @@ EXPORT_SYMBOL(isram_memcpy);
196 195
197#ifdef CONFIG_BFIN_ISRAM_SELF_TEST 196#ifdef CONFIG_BFIN_ISRAM_SELF_TEST
198 197
199#define TEST_LEN 0x100 198static int test_len = 0x20000;
200 199
201static __init void hex_dump(unsigned char *buf, int len) 200static __init void hex_dump(unsigned char *buf, int len)
202{ 201{
@@ -212,15 +211,15 @@ static __init int isram_read_test(char *sdram, void *l1inst)
212 pr_info("INFO: running isram_read tests\n"); 211 pr_info("INFO: running isram_read tests\n");
213 212
214 /* setup some different data to play with */ 213 /* setup some different data to play with */
215 for (i = 0; i < TEST_LEN; ++i) 214 for (i = 0; i < test_len; ++i)
216 sdram[i] = i; 215 sdram[i] = i % 255;
217 dma_memcpy(l1inst, sdram, TEST_LEN); 216 dma_memcpy(l1inst, sdram, test_len);
218 217
219 /* make sure we can read the L1 inst */ 218 /* make sure we can read the L1 inst */
220 for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) { 219 for (i = 0; i < test_len; i += sizeof(uint64_t)) {
221 data1 = isram_read(l1inst + i); 220 data1 = isram_read(l1inst + i);
222 memcpy(&data2, sdram + i, sizeof(data2)); 221 memcpy(&data2, sdram + i, sizeof(data2));
223 if (memcmp(&data1, &data2, sizeof(uint64_t))) { 222 if (data1 != data2) {
224 pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n", 223 pr_err("FAIL: isram_read(%p) returned %#llx but wanted %#llx\n",
225 l1inst + i, data1, data2); 224 l1inst + i, data1, data2);
226 ++ret; 225 ++ret;
@@ -238,25 +237,25 @@ static __init int isram_write_test(char *sdram, void *l1inst)
238 pr_info("INFO: running isram_write tests\n"); 237 pr_info("INFO: running isram_write tests\n");
239 238
240 /* setup some different data to play with */ 239 /* setup some different data to play with */
241 memset(sdram, 0, TEST_LEN * 2); 240 memset(sdram, 0, test_len * 2);
242 dma_memcpy(l1inst, sdram, TEST_LEN); 241 dma_memcpy(l1inst, sdram, test_len);
243 for (i = 0; i < TEST_LEN; ++i) 242 for (i = 0; i < test_len; ++i)
244 sdram[i] = i; 243 sdram[i] = i % 255;
245 244
246 /* make sure we can write the L1 inst */ 245 /* make sure we can write the L1 inst */
247 for (i = 0; i < TEST_LEN; i += sizeof(uint64_t)) { 246 for (i = 0; i < test_len; i += sizeof(uint64_t)) {
248 memcpy(&data1, sdram + i, sizeof(data1)); 247 memcpy(&data1, sdram + i, sizeof(data1));
249 isram_write(l1inst + i, data1); 248 isram_write(l1inst + i, data1);
250 data2 = isram_read(l1inst + i); 249 data2 = isram_read(l1inst + i);
251 if (memcmp(&data1, &data2, sizeof(uint64_t))) { 250 if (data1 != data2) {
252 pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n", 251 pr_err("FAIL: isram_write(%p, %#llx) != %#llx\n",
253 l1inst + i, data1, data2); 252 l1inst + i, data1, data2);
254 ++ret; 253 ++ret;
255 } 254 }
256 } 255 }
257 256
258 dma_memcpy(sdram + TEST_LEN, l1inst, TEST_LEN); 257 dma_memcpy(sdram + test_len, l1inst, test_len);
259 if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) { 258 if (memcmp(sdram, sdram + test_len, test_len)) {
260 pr_err("FAIL: isram_write() did not work properly\n"); 259 pr_err("FAIL: isram_write() did not work properly\n");
261 ++ret; 260 ++ret;
262 } 261 }
@@ -268,12 +267,12 @@ static __init int
268_isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy, 267_isram_memcpy_test(char pattern, void *sdram, void *l1inst, const char *smemcpy,
269 void *(*fmemcpy)(void *, const void *, size_t)) 268 void *(*fmemcpy)(void *, const void *, size_t))
270{ 269{
271 memset(sdram, pattern, TEST_LEN); 270 memset(sdram, pattern, test_len);
272 fmemcpy(l1inst, sdram, TEST_LEN); 271 fmemcpy(l1inst, sdram, test_len);
273 fmemcpy(sdram + TEST_LEN, l1inst, TEST_LEN); 272 fmemcpy(sdram + test_len, l1inst, test_len);
274 if (memcmp(sdram, sdram + TEST_LEN, TEST_LEN)) { 273 if (memcmp(sdram, sdram + test_len, test_len)) {
275 pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n", 274 pr_err("FAIL: %s(%p <=> %p, %#x) failed (data is %#x)\n",
276 smemcpy, l1inst, sdram, TEST_LEN, pattern); 275 smemcpy, l1inst, sdram, test_len, pattern);
277 return 1; 276 return 1;
278 } 277 }
279 return 0; 278 return 0;
@@ -292,12 +291,13 @@ static __init int isram_memcpy_test(char *sdram, void *l1inst)
292 /* check read of small, unaligned, and hardware 64bit limits */ 291 /* check read of small, unaligned, and hardware 64bit limits */
293 pr_info("INFO: running isram_memcpy (read) tests\n"); 292 pr_info("INFO: running isram_memcpy (read) tests\n");
294 293
295 for (i = 0; i < TEST_LEN; ++i) 294 /* setup some different data to play with */
296 sdram[i] = i; 295 for (i = 0; i < test_len; ++i)
297 dma_memcpy(l1inst, sdram, TEST_LEN); 296 sdram[i] = i % 255;
297 dma_memcpy(l1inst, sdram, test_len);
298 298
299 thisret = 0; 299 thisret = 0;
300 for (i = 0; i < TEST_LEN - 32; ++i) { 300 for (i = 0; i < test_len - 32; ++i) {
301 unsigned char cmp[32]; 301 unsigned char cmp[32];
302 for (j = 1; j <= 32; ++j) { 302 for (j = 1; j <= 32; ++j) {
303 memset(cmp, 0, sizeof(cmp)); 303 memset(cmp, 0, sizeof(cmp));
@@ -310,7 +310,7 @@ static __init int isram_memcpy_test(char *sdram, void *l1inst)
310 pr_cont("\n"); 310 pr_cont("\n");
311 if (++thisret > 20) { 311 if (++thisret > 20) {
312 pr_err("FAIL: skipping remaining series\n"); 312 pr_err("FAIL: skipping remaining series\n");
313 i = TEST_LEN; 313 i = test_len;
314 break; 314 break;
315 } 315 }
316 } 316 }
@@ -321,11 +321,11 @@ static __init int isram_memcpy_test(char *sdram, void *l1inst)
321 /* check write of small, unaligned, and hardware 64bit limits */ 321 /* check write of small, unaligned, and hardware 64bit limits */
322 pr_info("INFO: running isram_memcpy (write) tests\n"); 322 pr_info("INFO: running isram_memcpy (write) tests\n");
323 323
324 memset(sdram + TEST_LEN, 0, TEST_LEN); 324 memset(sdram + test_len, 0, test_len);
325 dma_memcpy(l1inst, sdram + TEST_LEN, TEST_LEN); 325 dma_memcpy(l1inst, sdram + test_len, test_len);
326 326
327 thisret = 0; 327 thisret = 0;
328 for (i = 0; i < TEST_LEN - 32; ++i) { 328 for (i = 0; i < test_len - 32; ++i) {
329 unsigned char cmp[32]; 329 unsigned char cmp[32];
330 for (j = 1; j <= 32; ++j) { 330 for (j = 1; j <= 32; ++j) {
331 isram_memcpy(l1inst + i, sdram + i, j); 331 isram_memcpy(l1inst + i, sdram + i, j);
@@ -338,7 +338,7 @@ static __init int isram_memcpy_test(char *sdram, void *l1inst)
338 pr_cont("\n"); 338 pr_cont("\n");
339 if (++thisret > 20) { 339 if (++thisret > 20) {
340 pr_err("FAIL: skipping remaining series\n"); 340 pr_err("FAIL: skipping remaining series\n");
341 i = TEST_LEN; 341 i = test_len;
342 break; 342 break;
343 } 343 }
344 } 344 }
@@ -355,22 +355,30 @@ static __init int isram_test_init(void)
355 char *sdram; 355 char *sdram;
356 void *l1inst; 356 void *l1inst;
357 357
358 sdram = kmalloc(TEST_LEN * 2, GFP_KERNEL); 358 /* Try to test as much of L1SRAM as possible */
359 if (!sdram) { 359 while (test_len) {
360 pr_warning("SKIP: could not allocate sdram\n"); 360 test_len >>= 1;
361 return 0; 361 l1inst = l1_inst_sram_alloc(test_len);
362 if (l1inst)
363 break;
362 } 364 }
363
364 l1inst = l1_inst_sram_alloc(TEST_LEN);
365 if (!l1inst) { 365 if (!l1inst) {
366 kfree(sdram);
367 pr_warning("SKIP: could not allocate L1 inst\n"); 366 pr_warning("SKIP: could not allocate L1 inst\n");
368 return 0; 367 return 0;
369 } 368 }
369 pr_info("INFO: testing %#x bytes (%p - %p)\n",
370 test_len, l1inst, l1inst + test_len);
371
372 sdram = kmalloc(test_len * 2, GFP_KERNEL);
373 if (!sdram) {
374 sram_free(l1inst);
375 pr_warning("SKIP: could not allocate sdram\n");
376 return 0;
377 }
370 378
371 /* sanity check initial L1 inst state */ 379 /* sanity check initial L1 inst state */
372 ret = 1; 380 ret = 1;
373 pr_info("INFO: running initial dma_memcpy checks\n"); 381 pr_info("INFO: running initial dma_memcpy checks %p\n", sdram);
374 if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy)) 382 if (_isram_memcpy_test(0xa, sdram, l1inst, dma_memcpy))
375 goto abort; 383 goto abort;
376 if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy)) 384 if (_isram_memcpy_test(0x5, sdram, l1inst, dma_memcpy))
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
index 49b2ff2c8b74..627e04b5ba9a 100644
--- a/arch/blackfin/mm/sram-alloc.c
+++ b/arch/blackfin/mm/sram-alloc.c
@@ -256,7 +256,8 @@ static void *_sram_alloc(size_t size, struct sram_piece *pfree_head,
256 plast->next = pslot->next; 256 plast->next = pslot->next;
257 pavail = pslot; 257 pavail = pslot;
258 } else { 258 } else {
259 pavail = kmem_cache_alloc(sram_piece_cache, GFP_KERNEL); 259 /* use atomic so our L1 allocator can be used atomically */
260 pavail = kmem_cache_alloc(sram_piece_cache, GFP_ATOMIC);
260 261
261 if (!pavail) 262 if (!pavail)
262 return NULL; 263 return NULL;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 23:48:19 -0500