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-rw-r--r--arch/mips/bcm63xx/Kconfig4
-rw-r--r--arch/mips/bcm63xx/clk.c70
-rw-r--r--arch/mips/bcm63xx/cpu.c79
-rw-r--r--arch/mips/bcm63xx/dev-uart.c2
-rw-r--r--arch/mips/bcm63xx/irq.c24
-rw-r--r--arch/mips/bcm63xx/prom.c7
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h99
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h2
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h109
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h4
-rw-r--r--arch/mips/pci/pci-bcm63xx.c4
11 files changed, 377 insertions, 27 deletions
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index fb177d6df066..6b1b9ad8d857 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -20,6 +20,10 @@ config BCM63XX_CPU_6348
20config BCM63XX_CPU_6358 20config BCM63XX_CPU_6358
21 bool "support 6358 CPU" 21 bool "support 6358 CPU"
22 select HW_HAS_PCI 22 select HW_HAS_PCI
23
24config BCM63XX_CPU_6368
25 bool "support 6368 CPU"
26 select HW_HAS_PCI
23endmenu 27endmenu
24 28
25source "arch/mips/bcm63xx/boards/Kconfig" 29source "arch/mips/bcm63xx/boards/Kconfig"
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 2c68ee9ccee2..9d57c71b7b58 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -10,6 +10,7 @@
10#include <linux/mutex.h> 10#include <linux/mutex.h>
11#include <linux/err.h> 11#include <linux/err.h>
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/delay.h>
13#include <bcm63xx_cpu.h> 14#include <bcm63xx_cpu.h>
14#include <bcm63xx_io.h> 15#include <bcm63xx_io.h>
15#include <bcm63xx_regs.h> 16#include <bcm63xx_regs.h>
@@ -113,6 +114,34 @@ static struct clk clk_ephy = {
113}; 114};
114 115
115/* 116/*
117 * Ethernet switch clock
118 */
119static void enetsw_set(struct clk *clk, int enable)
120{
121 if (!BCMCPU_IS_6368())
122 return;
123 bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
124 CKCTL_6368_SWPKT_USB_EN |
125 CKCTL_6368_SWPKT_SAR_EN, enable);
126 if (enable) {
127 u32 val;
128
129 /* reset switch core afer clock change */
130 val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
131 val &= ~SOFTRESET_6368_ENETSW_MASK;
132 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
133 msleep(10);
134 val |= SOFTRESET_6368_ENETSW_MASK;
135 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
136 msleep(10);
137 }
138}
139
140static struct clk clk_enetsw = {
141 .set = enetsw_set,
142};
143
144/*
116 * PCM clock 145 * PCM clock
117 */ 146 */
118static void pcm_set(struct clk *clk, int enable) 147static void pcm_set(struct clk *clk, int enable)
@@ -131,9 +160,10 @@ static struct clk clk_pcm = {
131 */ 160 */
132static void usbh_set(struct clk *clk, int enable) 161static void usbh_set(struct clk *clk, int enable)
133{ 162{
134 if (!BCMCPU_IS_6348()) 163 if (BCMCPU_IS_6348())
135 return; 164 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
136 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); 165 else if (BCMCPU_IS_6368())
166 bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
137} 167}
138 168
139static struct clk clk_usbh = { 169static struct clk clk_usbh = {
@@ -162,6 +192,36 @@ static struct clk clk_spi = {
162}; 192};
163 193
164/* 194/*
195 * XTM clock
196 */
197static void xtm_set(struct clk *clk, int enable)
198{
199 if (!BCMCPU_IS_6368())
200 return;
201
202 bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
203 CKCTL_6368_SWPKT_SAR_EN, enable);
204
205 if (enable) {
206 u32 val;
207
208 /* reset sar core afer clock change */
209 val = bcm_perf_readl(PERF_SOFTRESET_6368_REG);
210 val &= ~SOFTRESET_6368_SAR_MASK;
211 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
212 mdelay(1);
213 val |= SOFTRESET_6368_SAR_MASK;
214 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
215 mdelay(1);
216 }
217}
218
219
220static struct clk clk_xtm = {
221 .set = xtm_set,
222};
223
224/*
165 * Internal peripheral clock 225 * Internal peripheral clock
166 */ 226 */
167static struct clk clk_periph = { 227static struct clk clk_periph = {
@@ -204,12 +264,16 @@ struct clk *clk_get(struct device *dev, const char *id)
204 return &clk_enet0; 264 return &clk_enet0;
205 if (!strcmp(id, "enet1")) 265 if (!strcmp(id, "enet1"))
206 return &clk_enet1; 266 return &clk_enet1;
267 if (!strcmp(id, "enetsw"))
268 return &clk_enetsw;
207 if (!strcmp(id, "ephy")) 269 if (!strcmp(id, "ephy"))
208 return &clk_ephy; 270 return &clk_ephy;
209 if (!strcmp(id, "usbh")) 271 if (!strcmp(id, "usbh"))
210 return &clk_usbh; 272 return &clk_usbh;
211 if (!strcmp(id, "spi")) 273 if (!strcmp(id, "spi"))
212 return &clk_spi; 274 return &clk_spi;
275 if (!strcmp(id, "xtm"))
276 return &clk_xtm;
213 if (!strcmp(id, "periph")) 277 if (!strcmp(id, "periph"))
214 return &clk_periph; 278 return &clk_periph;
215 if (BCMCPU_IS_6358() && !strcmp(id, "pcm")) 279 if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 8bd5133eafd1..80941687b9dd 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -63,6 +63,15 @@ static const int bcm6358_irqs[] = {
63 63
64}; 64};
65 65
66static const unsigned long bcm6368_regs_base[] = {
67 __GEN_CPU_REGS_TABLE(6368)
68};
69
70static const int bcm6368_irqs[] = {
71 __GEN_CPU_IRQ_TABLE(6368)
72
73};
74
66u16 __bcm63xx_get_cpu_id(void) 75u16 __bcm63xx_get_cpu_id(void)
67{ 76{
68 return bcm63xx_cpu_id; 77 return bcm63xx_cpu_id;
@@ -89,20 +98,19 @@ unsigned int bcm63xx_get_memory_size(void)
89 98
90static unsigned int detect_cpu_clock(void) 99static unsigned int detect_cpu_clock(void)
91{ 100{
92 unsigned int tmp, n1 = 0, n2 = 0, m1 = 0; 101 switch (bcm63xx_get_cpu_id()) {
93 102 case BCM6338_CPU_ID:
94 /* BCM6338 has a fixed 240 Mhz frequency */ 103 /* BCM6338 has a fixed 240 Mhz frequency */
95 if (BCMCPU_IS_6338())
96 return 240000000; 104 return 240000000;
97 105
98 /* BCM6345 has a fixed 140Mhz frequency */ 106 case BCM6345_CPU_ID:
99 if (BCMCPU_IS_6345()) 107 /* BCM6345 has a fixed 140Mhz frequency */
100 return 140000000; 108 return 140000000;
101 109
102 /* 110 case BCM6348_CPU_ID:
103 * frequency depends on PLL configuration: 111 {
104 */ 112 unsigned int tmp, n1, n2, m1;
105 if (BCMCPU_IS_6348()) { 113
106 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */ 114 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
107 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG); 115 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
108 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT; 116 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
@@ -111,17 +119,47 @@ static unsigned int detect_cpu_clock(void)
111 n1 += 1; 119 n1 += 1;
112 n2 += 2; 120 n2 += 2;
113 m1 += 1; 121 m1 += 1;
122 return (16 * 1000000 * n1 * n2) / m1;
114 } 123 }
115 124
116 if (BCMCPU_IS_6358()) { 125 case BCM6358_CPU_ID:
126 {
127 unsigned int tmp, n1, n2, m1;
128
117 /* 16MHz * N1 * N2 / M1_CPU */ 129 /* 16MHz * N1 * N2 / M1_CPU */
118 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG); 130 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
119 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT; 131 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
120 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT; 132 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
121 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT; 133 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
134 return (16 * 1000000 * n1 * n2) / m1;
122 } 135 }
123 136
124 return (16 * 1000000 * n1 * n2) / m1; 137 case BCM6368_CPU_ID:
138 {
139 unsigned int tmp, p1, p2, ndiv, m1;
140
141 /* (64MHz / P1) * P2 * NDIV / M1_CPU */
142 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
143
144 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
145 DMIPSPLLCFG_6368_P1_SHIFT;
146
147 p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
148 DMIPSPLLCFG_6368_P2_SHIFT;
149
150 ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
151 DMIPSPLLCFG_6368_NDIV_SHIFT;
152
153 tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
154 m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
155 DMIPSPLLDIV_6368_MDIV_SHIFT;
156
157 return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
158 }
159
160 default:
161 BUG();
162 }
125} 163}
126 164
127/* 165/*
@@ -143,7 +181,7 @@ static unsigned int detect_memory_size(void)
143 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; 181 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
144 } 182 }
145 183
146 if (BCMCPU_IS_6358()) { 184 if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
147 val = bcm_memc_readl(MEMC_CFG_REG); 185 val = bcm_memc_readl(MEMC_CFG_REG);
148 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; 186 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
149 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; 187 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@@ -188,9 +226,18 @@ void __init bcm63xx_cpu_init(void)
188 bcm63xx_irqs = bcm6345_irqs; 226 bcm63xx_irqs = bcm6345_irqs;
189 break; 227 break;
190 case CPU_BMIPS4350: 228 case CPU_BMIPS4350:
191 expected_cpu_id = BCM6358_CPU_ID; 229 switch (read_c0_prid() & 0xf0) {
192 bcm63xx_regs_base = bcm6358_regs_base; 230 case 0x10:
193 bcm63xx_irqs = bcm6358_irqs; 231 expected_cpu_id = BCM6358_CPU_ID;
232 bcm63xx_regs_base = bcm6358_regs_base;
233 bcm63xx_irqs = bcm6358_irqs;
234 break;
235 case 0x30:
236 expected_cpu_id = BCM6368_CPU_ID;
237 bcm63xx_regs_base = bcm6368_regs_base;
238 bcm63xx_irqs = bcm6368_irqs;
239 break;
240 }
194 break; 241 break;
195 } 242 }
196 243
diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c
index c2963da0253e..d6e42c608325 100644
--- a/arch/mips/bcm63xx/dev-uart.c
+++ b/arch/mips/bcm63xx/dev-uart.c
@@ -54,7 +54,7 @@ int __init bcm63xx_uart_register(unsigned int id)
54 if (id >= ARRAY_SIZE(bcm63xx_uart_devices)) 54 if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
55 return -ENODEV; 55 return -ENODEV;
56 56
57 if (id == 1 && !BCMCPU_IS_6358()) 57 if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368()))
58 return -ENODEV; 58 return -ENODEV;
59 59
60 if (id == 0) { 60 if (id == 0) {
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 9f538846b3f7..9a216a451d92 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -71,6 +71,17 @@ static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
71#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358 71#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
72#define ext_irq_cfg_reg2 0 72#define ext_irq_cfg_reg2 0
73#endif 73#endif
74#ifdef CONFIG_BCM63XX_CPU_6368
75#define irq_stat_reg PERF_IRQSTAT_6368_REG
76#define irq_mask_reg PERF_IRQMASK_6368_REG
77#define irq_bits 64
78#define is_ext_irq_cascaded 1
79#define ext_irq_start (BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE)
80#define ext_irq_end (BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE)
81#define ext_irq_count 6
82#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6368
83#define ext_irq_cfg_reg2 PERF_EXTIRQ_CFG_REG2_6368
84#endif
74 85
75#if irq_bits == 32 86#if irq_bits == 32
76#define dispatch_internal __dispatch_internal 87#define dispatch_internal __dispatch_internal
@@ -134,6 +145,17 @@ static void bcm63xx_init_irq(void)
134 ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE; 145 ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
135 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358; 146 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
136 break; 147 break;
148 case BCM6368_CPU_ID:
149 irq_stat_addr += PERF_IRQSTAT_6368_REG;
150 irq_mask_addr += PERF_IRQMASK_6368_REG;
151 irq_bits = 64;
152 ext_irq_count = 6;
153 is_ext_irq_cascaded = 1;
154 ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
155 ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
156 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
157 ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
158 break;
137 default: 159 default:
138 BUG(); 160 BUG();
139 } 161 }
@@ -406,7 +428,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
406 reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); 428 reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
407 } 429 }
408 430
409 if (BCMCPU_IS_6338() || BCMCPU_IS_6358()) { 431 if (BCMCPU_IS_6338() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
410 if (levelsense) 432 if (levelsense)
411 reg |= EXTIRQ_CFG_LEVELSENSE(irq); 433 reg |= EXTIRQ_CFG_LEVELSENSE(irq);
412 else 434 else
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index be252efa0757..99d7f405cbeb 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -32,9 +32,12 @@ void __init prom_init(void)
32 mask = CKCTL_6345_ALL_SAFE_EN; 32 mask = CKCTL_6345_ALL_SAFE_EN;
33 else if (BCMCPU_IS_6348()) 33 else if (BCMCPU_IS_6348())
34 mask = CKCTL_6348_ALL_SAFE_EN; 34 mask = CKCTL_6348_ALL_SAFE_EN;
35 else 35 else if (BCMCPU_IS_6358())
36 /* BCMCPU_IS_6358() */
37 mask = CKCTL_6358_ALL_SAFE_EN; 36 mask = CKCTL_6358_ALL_SAFE_EN;
37 else if (BCMCPU_IS_6368())
38 mask = CKCTL_6368_ALL_SAFE_EN;
39 else
40 mask = 0;
38 41
39 reg = bcm_perf_readl(PERF_CKCTL_REG); 42 reg = bcm_perf_readl(PERF_CKCTL_REG);
40 reg &= ~mask; 43 reg &= ~mask;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 46f03322e2ca..23403a32c158 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -13,6 +13,7 @@
13#define BCM6345_CPU_ID 0x6345 13#define BCM6345_CPU_ID 0x6345
14#define BCM6348_CPU_ID 0x6348 14#define BCM6348_CPU_ID 0x6348
15#define BCM6358_CPU_ID 0x6358 15#define BCM6358_CPU_ID 0x6358
16#define BCM6368_CPU_ID 0x6368
16 17
17void __init bcm63xx_cpu_init(void); 18void __init bcm63xx_cpu_init(void);
18u16 __bcm63xx_get_cpu_id(void); 19u16 __bcm63xx_get_cpu_id(void);
@@ -71,6 +72,19 @@ unsigned int bcm63xx_get_cpu_freq(void);
71# define BCMCPU_IS_6358() (0) 72# define BCMCPU_IS_6358() (0)
72#endif 73#endif
73 74
75#ifdef CONFIG_BCM63XX_CPU_6368
76# ifdef bcm63xx_get_cpu_id
77# undef bcm63xx_get_cpu_id
78# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
79# define BCMCPU_RUNTIME_DETECT
80# else
81# define bcm63xx_get_cpu_id() BCM6368_CPU_ID
82# endif
83# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
84#else
85# define BCMCPU_IS_6368() (0)
86#endif
87
74#ifndef bcm63xx_get_cpu_id 88#ifndef bcm63xx_get_cpu_id
75#error "No CPU support configured" 89#error "No CPU support configured"
76#endif 90#endif
@@ -307,6 +321,47 @@ enum bcm63xx_regs_set {
307#define BCM_6358_PCMDMAS_BASE (0xfffe1a00) 321#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
308 322
309 323
324/*
325 * 6368 register sets base address
326 */
327#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
328#define BCM_6368_PERF_BASE (0xb0000000)
329#define BCM_6368_TIMER_BASE (0xb0000040)
330#define BCM_6368_WDT_BASE (0xb000005c)
331#define BCM_6368_UART0_BASE (0xb0000100)
332#define BCM_6368_UART1_BASE (0xb0000120)
333#define BCM_6368_GPIO_BASE (0xb0000080)
334#define BCM_6368_SPI_BASE (0xdeadbeef)
335#define BCM_6368_SPI2_BASE (0xb0000800)
336#define BCM_6368_UDC0_BASE (0xdeadbeef)
337#define BCM_6368_OHCI0_BASE (0xb0001600)
338#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
339#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
340#define BCM_6368_MPI_BASE (0xb0001000)
341#define BCM_6368_PCMCIA_BASE (0xb0001054)
342#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
343#define BCM_6368_M2M_BASE (0xdeadbeef)
344#define BCM_6368_DSL_BASE (0xdeadbeef)
345#define BCM_6368_ENET0_BASE (0xdeadbeef)
346#define BCM_6368_ENET1_BASE (0xdeadbeef)
347#define BCM_6368_ENETDMA_BASE (0xb0006800)
348#define BCM_6368_ENETDMAC_BASE (0xb0006a00)
349#define BCM_6368_ENETDMAS_BASE (0xb0006c00)
350#define BCM_6368_ENETSW_BASE (0xb0f00000)
351#define BCM_6368_EHCI0_BASE (0xb0001500)
352#define BCM_6368_SDRAM_BASE (0xdeadbeef)
353#define BCM_6368_MEMC_BASE (0xb0001200)
354#define BCM_6368_DDR_BASE (0xb0001280)
355#define BCM_6368_ATM_BASE (0xdeadbeef)
356#define BCM_6368_XTM_BASE (0xb0001800)
357#define BCM_6368_XTMDMA_BASE (0xb0005000)
358#define BCM_6368_XTMDMAC_BASE (0xb0005200)
359#define BCM_6368_XTMDMAS_BASE (0xb0005400)
360#define BCM_6368_PCM_BASE (0xb0004000)
361#define BCM_6368_PCMDMA_BASE (0xb0005800)
362#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
363#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
364
310 365
311extern const unsigned long *bcm63xx_regs_base; 366extern const unsigned long *bcm63xx_regs_base;
312 367
@@ -410,6 +465,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
410#ifdef CONFIG_BCM63XX_CPU_6358 465#ifdef CONFIG_BCM63XX_CPU_6358
411 __GEN_RSET(6358) 466 __GEN_RSET(6358)
412#endif 467#endif
468#ifdef CONFIG_BCM63XX_CPU_6368
469 __GEN_RSET(6368)
470#endif
413#endif 471#endif
414 /* unreached */ 472 /* unreached */
415 return 0; 473 return 0;
@@ -574,6 +632,47 @@ enum bcm63xx_irq {
574#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27) 632#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
575#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28) 633#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
576 634
635/*
636 * 6368 irqs
637 */
638#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
639
640#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
641#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
642#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
643#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
644#define BCM_6368_ENET0_IRQ 0
645#define BCM_6368_ENET1_IRQ 0
646#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
647#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
648#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
649#define BCM_6368_PCMCIA_IRQ 0
650#define BCM_6368_ENET0_RXDMA_IRQ 0
651#define BCM_6368_ENET0_TXDMA_IRQ 0
652#define BCM_6368_ENET1_RXDMA_IRQ 0
653#define BCM_6368_ENET1_TXDMA_IRQ 0
654#define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)
655#define BCM_6368_ATM_IRQ 0
656#define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)
657#define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)
658#define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)
659#define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)
660#define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)
661#define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)
662#define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)
663#define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)
664#define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)
665#define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)
666
667#define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)
668#define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)
669#define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)
670#define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)
671#define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)
672#define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)
673#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
674#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
675
577extern const int *bcm63xx_irqs; 676extern const int *bcm63xx_irqs;
578 677
579#define __GEN_CPU_IRQ_TABLE(__cpu) \ 678#define __GEN_CPU_IRQ_TABLE(__cpu) \
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 3999ec0aa7f5..3d5de96d4036 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -14,6 +14,8 @@ static inline unsigned long bcm63xx_gpio_count(void)
14 return 8; 14 return 8;
15 case BCM6345_CPU_ID: 15 case BCM6345_CPU_ID:
16 return 16; 16 return 16;
17 case BCM6368_CPU_ID:
18 return 38;
17 case BCM6348_CPU_ID: 19 case BCM6348_CPU_ID:
18 default: 20 default:
19 return 37; 21 return 37;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 2b3a2d6bdb03..50057507c4e7 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -83,6 +83,37 @@
83 CKCTL_6358_USBSU_EN | \ 83 CKCTL_6358_USBSU_EN | \
84 CKCTL_6358_EPHY_EN) 84 CKCTL_6358_EPHY_EN)
85 85
86#define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
87#define CKCTL_6368_VDSL_AFE_EN (1 << 3)
88#define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
89#define CKCTL_6368_VDSL_EN (1 << 5)
90#define CKCTL_6368_PHYMIPS_EN (1 << 6)
91#define CKCTL_6368_SWPKT_USB_EN (1 << 7)
92#define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
93#define CKCTL_6368_SPI_CLK_EN (1 << 9)
94#define CKCTL_6368_USBD_CLK_EN (1 << 10)
95#define CKCTL_6368_SAR_CLK_EN (1 << 11)
96#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12)
97#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13)
98#define CKCTL_6368_PCM_CLK_EN (1 << 14)
99#define CKCTL_6368_USBH_CLK_EN (1 << 15)
100#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
101#define CKCTL_6368_NAND_CLK_EN (1 << 17)
102#define CKCTL_6368_IPSEC_CLK_EN (1 << 17)
103
104#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
105 CKCTL_6368_SWPKT_SAR_EN | \
106 CKCTL_6368_SPI_CLK_EN | \
107 CKCTL_6368_USBD_CLK_EN | \
108 CKCTL_6368_SAR_CLK_EN | \
109 CKCTL_6368_ROBOSW_CLK_EN | \
110 CKCTL_6368_UTOPIA_CLK_EN | \
111 CKCTL_6368_PCM_CLK_EN | \
112 CKCTL_6368_USBH_CLK_EN | \
113 CKCTL_6368_DISABLE_GLESS_EN | \
114 CKCTL_6368_NAND_CLK_EN | \
115 CKCTL_6368_IPSEC_CLK_EN)
116
86/* System PLL Control register */ 117/* System PLL Control register */
87#define PERF_SYS_PLL_CTL_REG 0x8 118#define PERF_SYS_PLL_CTL_REG 0x8
88#define SYS_PLL_SOFT_RESET 0x1 119#define SYS_PLL_SOFT_RESET 0x1
@@ -92,17 +123,22 @@
92#define PERF_IRQMASK_6345_REG 0xc 123#define PERF_IRQMASK_6345_REG 0xc
93#define PERF_IRQMASK_6348_REG 0xc 124#define PERF_IRQMASK_6348_REG 0xc
94#define PERF_IRQMASK_6358_REG 0xc 125#define PERF_IRQMASK_6358_REG 0xc
126#define PERF_IRQMASK_6368_REG 0x20
95 127
96/* Interrupt Status register */ 128/* Interrupt Status register */
97#define PERF_IRQSTAT_6338_REG 0x10 129#define PERF_IRQSTAT_6338_REG 0x10
98#define PERF_IRQSTAT_6345_REG 0x10 130#define PERF_IRQSTAT_6345_REG 0x10
99#define PERF_IRQSTAT_6348_REG 0x10 131#define PERF_IRQSTAT_6348_REG 0x10
100#define PERF_IRQSTAT_6358_REG 0x10 132#define PERF_IRQSTAT_6358_REG 0x10
133#define PERF_IRQSTAT_6368_REG 0x28
101 134
102/* External Interrupt Configuration register */ 135/* External Interrupt Configuration register */
103#define PERF_EXTIRQ_CFG_REG_6338 0x14 136#define PERF_EXTIRQ_CFG_REG_6338 0x14
104#define PERF_EXTIRQ_CFG_REG_6348 0x14 137#define PERF_EXTIRQ_CFG_REG_6348 0x14
105#define PERF_EXTIRQ_CFG_REG_6358 0x14 138#define PERF_EXTIRQ_CFG_REG_6358 0x14
139#define PERF_EXTIRQ_CFG_REG_6368 0x18
140
141#define PERF_EXTIRQ_CFG_REG2_6368 0x1c
106 142
107/* for 6348 only */ 143/* for 6348 only */
108#define EXTIRQ_CFG_SENSE_6348(x) (1 << (x)) 144#define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
@@ -126,6 +162,7 @@
126 162
127/* Soft Reset register */ 163/* Soft Reset register */
128#define PERF_SOFTRESET_REG 0x28 164#define PERF_SOFTRESET_REG 0x28
165#define PERF_SOFTRESET_6368_REG 0x10
129 166
130#define SOFTRESET_6338_SPI_MASK (1 << 0) 167#define SOFTRESET_6338_SPI_MASK (1 << 0)
131#define SOFTRESET_6338_ENET_MASK (1 << 2) 168#define SOFTRESET_6338_ENET_MASK (1 << 2)
@@ -166,6 +203,15 @@
166 SOFTRESET_6348_ACLC_MASK | \ 203 SOFTRESET_6348_ACLC_MASK | \
167 SOFTRESET_6348_ADSLMIPSPLL_MASK) 204 SOFTRESET_6348_ADSLMIPSPLL_MASK)
168 205
206#define SOFTRESET_6368_SPI_MASK (1 << 0)
207#define SOFTRESET_6368_MPI_MASK (1 << 3)
208#define SOFTRESET_6368_EPHY_MASK (1 << 6)
209#define SOFTRESET_6368_SAR_MASK (1 << 7)
210#define SOFTRESET_6368_ENETSW_MASK (1 << 10)
211#define SOFTRESET_6368_USBS_MASK (1 << 11)
212#define SOFTRESET_6368_USBH_MASK (1 << 12)
213#define SOFTRESET_6368_PCM_MASK (1 << 13)
214
169/* MIPS PLL control register */ 215/* MIPS PLL control register */
170#define PERF_MIPSPLLCTL_REG 0x34 216#define PERF_MIPSPLLCTL_REG 0x34
171#define MIPSPLLCTL_N1_SHIFT 20 217#define MIPSPLLCTL_N1_SHIFT 20
@@ -421,6 +467,44 @@
421#define GPIO_MODE_6358_SERIAL_LED (1 << 10) 467#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
422#define GPIO_MODE_6358_UTOPIA (1 << 12) 468#define GPIO_MODE_6358_UTOPIA (1 << 12)
423 469
470#define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
471#define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
472#define GPIO_MODE_6368_SYS_IRQ (1 << 2)
473#define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
474#define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
475#define GPIO_MODE_6368_INET_LED (1 << 5)
476#define GPIO_MODE_6368_EPHY0_LED (1 << 6)
477#define GPIO_MODE_6368_EPHY1_LED (1 << 7)
478#define GPIO_MODE_6368_EPHY2_LED (1 << 8)
479#define GPIO_MODE_6368_EPHY3_LED (1 << 9)
480#define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
481#define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
482#define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
483#define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
484#define GPIO_MODE_6368_USBD_LED (1 << 14)
485#define GPIO_MODE_6368_NTR_PULSE (1 << 15)
486#define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
487#define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
488#define GPIO_MODE_6368_PCI_INTB (1 << 18)
489#define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
490#define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
491#define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
492#define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
493#define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
494#define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
495#define GPIO_MODE_6368_EBI_CS2 (1 << 26)
496#define GPIO_MODE_6368_EBI_CS3 (1 << 27)
497#define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
498#define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
499#define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
500#define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
501
502
503#define GPIO_BASEMODE_6368_REG 0x38
504#define GPIO_BASEMODE_6368_UART2 0x1
505#define GPIO_BASEMODE_6368_GPIO 0x0
506#define GPIO_BASEMODE_6368_MASK 0x7
507/* those bits must be kept as read in gpio basemode register*/
424 508
425/************************************************************************* 509/*************************************************************************
426 * _REG relative to RSET_ENET 510 * _REG relative to RSET_ENET
@@ -631,7 +715,9 @@
631 * _REG relative to RSET_USBH_PRIV 715 * _REG relative to RSET_USBH_PRIV
632 *************************************************************************/ 716 *************************************************************************/
633 717
634#define USBH_PRIV_SWAP_REG 0x0 718#define USBH_PRIV_SWAP_6358_REG 0x0
719#define USBH_PRIV_SWAP_6368_REG 0x1c
720
635#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 721#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
636#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) 722#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
637#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 723#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
@@ -641,7 +727,13 @@
641#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 727#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
642#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) 728#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
643 729
644#define USBH_PRIV_TEST_REG 0x24 730#define USBH_PRIV_TEST_6358_REG 0x24
731#define USBH_PRIV_TEST_6368_REG 0x14
732
733#define USBH_PRIV_SETUP_6368_REG 0x28
734#define USBH_PRIV_SETUP_IOC_SHIFT 4
735#define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
736
645 737
646 738
647/************************************************************************* 739/*************************************************************************
@@ -837,6 +929,19 @@
837#define DMIPSPLLCFG_N2_SHIFT 29 929#define DMIPSPLLCFG_N2_SHIFT 29
838#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) 930#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
839 931
932#define DDR_DMIPSPLLCFG_6368_REG 0x20
933#define DMIPSPLLCFG_6368_P1_SHIFT 0
934#define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
935#define DMIPSPLLCFG_6368_P2_SHIFT 4
936#define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
937#define DMIPSPLLCFG_6368_NDIV_SHIFT 16
938#define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
939
940#define DDR_DMIPSPLLDIV_6368_REG 0x24
941#define DMIPSPLLDIV_6368_MDIV_SHIFT 0
942#define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
943
944
840/************************************************************************* 945/*************************************************************************
841 * _REG relative to RSET_M2M 946 * _REG relative to RSET_M2M
842 *************************************************************************/ 947 *************************************************************************/
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index e3fe04dc50bd..ef94ba73646e 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -18,6 +18,10 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
18 if (offset >= 0xfff00000) 18 if (offset >= 0xfff00000)
19 return 1; 19 return 1;
20 break; 20 break;
21 case BCM6368_CPU_ID:
22 if (offset >= 0xb0000000 && offset < 0xb1000000)
23 return 1;
24 break;
21 } 25 }
22 return 0; 26 return 0;
23} 27}
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 82e0fde1dba0..39eb7c417e2f 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -99,7 +99,7 @@ static int __init bcm63xx_pci_init(void)
99 unsigned int mem_size; 99 unsigned int mem_size;
100 u32 val; 100 u32 val;
101 101
102 if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358()) 102 if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
103 return -ENODEV; 103 return -ENODEV;
104 104
105 if (!bcm63xx_pci_enabled) 105 if (!bcm63xx_pci_enabled)
@@ -159,7 +159,7 @@ static int __init bcm63xx_pci_init(void)
159 /* setup PCI to local bus access, used by PCI device to target 159 /* setup PCI to local bus access, used by PCI device to target
160 * local RAM while bus mastering */ 160 * local RAM while bus mastering */
161 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3); 161 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
162 if (BCMCPU_IS_6358()) 162 if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
163 val = MPI_SP0_REMAP_ENABLE_MASK; 163 val = MPI_SP0_REMAP_ENABLE_MASK;
164 else 164 else
165 val = 0; 165 val = 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-31 01:38:03 -0400