diff options
-rw-r--r-- | arch/ppc/kernel/cpu_setup_6xx.S | 5 | ||||
-rw-r--r-- | arch/ppc/kernel/l2cr.S | 31 |
2 files changed, 34 insertions, 2 deletions
diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S index 468721d9ebd2..3fb1fb619d2c 100644 --- a/arch/ppc/kernel/cpu_setup_6xx.S +++ b/arch/ppc/kernel/cpu_setup_6xx.S | |||
@@ -249,8 +249,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM) | |||
249 | sync | 249 | sync |
250 | isync | 250 | isync |
251 | 251 | ||
252 | /* Enable L2 HW prefetch | 252 | /* Enable L2 HW prefetch, if L2 is enabled |
253 | */ | 253 | */ |
254 | mfspr r3,SPRN_L2CR | ||
255 | andis. r3,r3,L2CR_L2E@h | ||
256 | beqlr | ||
254 | mfspr r3,SPRN_MSSCR0 | 257 | mfspr r3,SPRN_MSSCR0 |
255 | ori r3,r3,3 | 258 | ori r3,r3,3 |
256 | sync | 259 | sync |
diff --git a/arch/ppc/kernel/l2cr.S b/arch/ppc/kernel/l2cr.S index c39441048266..861115249b35 100644 --- a/arch/ppc/kernel/l2cr.S +++ b/arch/ppc/kernel/l2cr.S | |||
@@ -156,6 +156,26 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |||
156 | The bit moved on the 7450..... | 156 | The bit moved on the 7450..... |
157 | ****/ | 157 | ****/ |
158 | 158 | ||
159 | BEGIN_FTR_SECTION | ||
160 | /* Disable L2 prefetch on some 745x and try to ensure | ||
161 | * L2 prefetch engines are idle. As explained by errata | ||
162 | * text, we can't be sure they are, we just hope very hard | ||
163 | * that well be enough (sic !). At least I noticed Apple | ||
164 | * doesn't even bother doing the dcbf's here... | ||
165 | */ | ||
166 | mfspr r4,SPRN_MSSCR0 | ||
167 | rlwinm r4,r4,0,0,29 | ||
168 | sync | ||
169 | mtspr SPRN_MSSCR0,r4 | ||
170 | sync | ||
171 | isync | ||
172 | lis r4,KERNELBASE@h | ||
173 | dcbf 0,r4 | ||
174 | dcbf 0,r4 | ||
175 | dcbf 0,r4 | ||
176 | dcbf 0,r4 | ||
177 | END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450) | ||
178 | |||
159 | /* TODO: use HW flush assist when available */ | 179 | /* TODO: use HW flush assist when available */ |
160 | 180 | ||
161 | lis r4,0x0002 | 181 | lis r4,0x0002 |
@@ -230,7 +250,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450) | |||
230 | oris r3,r3,0x8000 | 250 | oris r3,r3,0x8000 |
231 | mtspr SPRN_L2CR,r3 | 251 | mtspr SPRN_L2CR,r3 |
232 | sync | 252 | sync |
233 | 253 | ||
254 | /* Enable L2 HW prefetch on 744x/745x */ | ||
255 | BEGIN_FTR_SECTION | ||
256 | mfspr r3,SPRN_MSSCR0 | ||
257 | ori r3,r3,3 | ||
258 | sync | ||
259 | mtspr SPRN_MSSCR0,r3 | ||
260 | sync | ||
261 | isync | ||
262 | END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450) | ||
234 | 4: | 263 | 4: |
235 | 264 | ||
236 | /* Restore HID0[DPM] to whatever it was before */ | 265 | /* Restore HID0[DPM] to whatever it was before */ |