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-rw-r--r--arch/mips/mm/tlb-r4k.c21
1 files changed, 8 insertions, 13 deletions
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 2cde1b772443..2e0e21ef433e 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -26,11 +26,6 @@ extern void build_tlb_refill_handler(void);
26 */ 26 */
27#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) 27#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
28 28
29/* CP0 hazard avoidance. */
30#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
31 "nop; nop; nop; nop; nop; nop;\n\t" \
32 ".set reorder\n\t")
33
34/* Atomicity and interruptability */ 29/* Atomicity and interruptability */
35#ifdef CONFIG_MIPS_MT_SMTC 30#ifdef CONFIG_MIPS_MT_SMTC
36 31
@@ -126,7 +121,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
126 start += (PAGE_SIZE << 1); 121 start += (PAGE_SIZE << 1);
127 mtc0_tlbw_hazard(); 122 mtc0_tlbw_hazard();
128 tlb_probe(); 123 tlb_probe();
129 BARRIER; 124 tlb_probe_hazard();
130 idx = read_c0_index(); 125 idx = read_c0_index();
131 write_c0_entrylo0(0); 126 write_c0_entrylo0(0);
132 write_c0_entrylo1(0); 127 write_c0_entrylo1(0);
@@ -168,7 +163,7 @@ void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
168 start += (PAGE_SIZE << 1); 163 start += (PAGE_SIZE << 1);
169 mtc0_tlbw_hazard(); 164 mtc0_tlbw_hazard();
170 tlb_probe(); 165 tlb_probe();
171 BARRIER; 166 tlb_probe_hazard();
172 idx = read_c0_index(); 167 idx = read_c0_index();
173 write_c0_entrylo0(0); 168 write_c0_entrylo0(0);
174 write_c0_entrylo1(0); 169 write_c0_entrylo1(0);
@@ -202,7 +197,7 @@ void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
202 write_c0_entryhi(page | newpid); 197 write_c0_entryhi(page | newpid);
203 mtc0_tlbw_hazard(); 198 mtc0_tlbw_hazard();
204 tlb_probe(); 199 tlb_probe();
205 BARRIER; 200 tlb_probe_hazard();
206 idx = read_c0_index(); 201 idx = read_c0_index();
207 write_c0_entrylo0(0); 202 write_c0_entrylo0(0);
208 write_c0_entrylo1(0); 203 write_c0_entrylo1(0);
@@ -235,7 +230,7 @@ void local_flush_tlb_one(unsigned long page)
235 write_c0_entryhi(page); 230 write_c0_entryhi(page);
236 mtc0_tlbw_hazard(); 231 mtc0_tlbw_hazard();
237 tlb_probe(); 232 tlb_probe();
238 BARRIER; 233 tlb_probe_hazard();
239 idx = read_c0_index(); 234 idx = read_c0_index();
240 write_c0_entrylo0(0); 235 write_c0_entrylo0(0);
241 write_c0_entrylo1(0); 236 write_c0_entrylo1(0);
@@ -279,7 +274,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
279 pgdp = pgd_offset(vma->vm_mm, address); 274 pgdp = pgd_offset(vma->vm_mm, address);
280 mtc0_tlbw_hazard(); 275 mtc0_tlbw_hazard();
281 tlb_probe(); 276 tlb_probe();
282 BARRIER; 277 tlb_probe_hazard();
283 pudp = pud_offset(pgdp, address); 278 pudp = pud_offset(pgdp, address);
284 pmdp = pmd_offset(pudp, address); 279 pmdp = pmd_offset(pudp, address);
285 idx = read_c0_index(); 280 idx = read_c0_index();
@@ -320,7 +315,7 @@ static void r4k_update_mmu_cache_hwbug(struct vm_area_struct * vma,
320 pgdp = pgd_offset(vma->vm_mm, address); 315 pgdp = pgd_offset(vma->vm_mm, address);
321 mtc0_tlbw_hazard(); 316 mtc0_tlbw_hazard();
322 tlb_probe(); 317 tlb_probe();
323 BARRIER; 318 tlb_probe_hazard();
324 pmdp = pmd_offset(pgdp, address); 319 pmdp = pmd_offset(pgdp, address);
325 idx = read_c0_index(); 320 idx = read_c0_index();
326 ptep = pte_offset_map(pmdp, address); 321 ptep = pte_offset_map(pmdp, address);
@@ -351,7 +346,7 @@ void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
351 wired = read_c0_wired(); 346 wired = read_c0_wired();
352 write_c0_wired(wired + 1); 347 write_c0_wired(wired + 1);
353 write_c0_index(wired); 348 write_c0_index(wired);
354 BARRIER; 349 tlbw_use_hazard(); /* What is the hazard here? */
355 write_c0_pagemask(pagemask); 350 write_c0_pagemask(pagemask);
356 write_c0_entryhi(entryhi); 351 write_c0_entryhi(entryhi);
357 write_c0_entrylo0(entrylo0); 352 write_c0_entrylo0(entrylo0);
@@ -361,7 +356,7 @@ void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
361 tlbw_use_hazard(); 356 tlbw_use_hazard();
362 357
363 write_c0_entryhi(old_ctx); 358 write_c0_entryhi(old_ctx);
364 BARRIER; 359 tlbw_use_hazard(); /* What is the hazard here? */
365 write_c0_pagemask(old_pagemask); 360 write_c0_pagemask(old_pagemask);
366 local_flush_tlb_all(); 361 local_flush_tlb_all();
367 EXIT_CRITICAL(flags); 362 EXIT_CRITICAL(flags);