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-rw-r--r--arch/arm/Kconfig12
-rw-r--r--arch/arm/mm/proc-v7.S5
2 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49f85664083d..9faccc411c2a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -778,6 +778,18 @@ config ARM_ERRATA_458693
778 in the ACTLR register. Note that setting specific bits in the ACTLR 778 in the ACTLR register. Note that setting specific bits in the ACTLR
779 register may not be available in non-secure mode. 779 register may not be available in non-secure mode.
780 780
781config ARM_ERRATA_460075
782 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
783 depends on CPU_V7
784 help
785 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
786 erratum. Any asynchronous access to the L2 cache may encounter a
787 situation in which recent store transactions to the L2 cache are lost
788 and overwritten with stale memory contents from external memory. The
789 workaround disables the write-allocate mode for the L2 cache via the
790 ACTLR register. Note that setting specific bits in the ACTLR register
791 may not be available in non-secure mode.
792
781endmenu 793endmenu
782 794
783source "arch/arm/common/Kconfig" 795source "arch/arm/common/Kconfig"
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 370baa7a0f08..f2305441e7d1 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -194,6 +194,11 @@ __v7_setup:
194 orr r10, r10, #(1 << 9) @ set PLDNOP to 1 194 orr r10, r10, #(1 << 9) @ set PLDNOP to 1
195 mcr p15, 0, r10, c1, c0, 1 @ write aux control register 195 mcr p15, 0, r10, c1, c0, 1 @ write aux control register
196#endif 196#endif
197#ifdef CONFIG_ARM_ERRATA_460075
198 mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
199 orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit
200 mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
201#endif
197 mov r10, #0 202 mov r10, #0
198#ifdef HARVARD_CACHE 203#ifdef HARVARD_CACHE
199 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 204 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate