190 files changed, 7915 insertions, 1508 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index d6befb2c470f..33d0ec494e34 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -685,6 +685,18 @@ ARM/MAGICIAN MACHINE SUPPORT
 M:      Philipp Zabel <philipp.zabel@gmail.com>
 S:      Maintained
 
+ARM/Marvell Loki/Kirkwood/MV78xx0/Orion SOC support
+M:      Lennert Buytenhek <buytenh@marvell.com>
+M:      Nicolas Pitre <nico@marvell.com>
+L:      linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
+T:      git git://git.marvell.com/orion
+S:      Maintained
+F:      arch/arm/mach-loki/
+F:      arch/arm/mach-kirkwood/
+F:      arch/arm/mach-mv78xx0/
+F:      arch/arm/mach-orion5x/
+F:      arch/arm/plat-orion/
+
 ARM/MIOA701 MACHINE SUPPORT
 M:      Robert Jarzmik <robert.jarzmik@free.fr>
 L:      linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a7eb44a1955c..9746667c1973 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -46,10 +46,6 @@ config GENERIC_CLOCKEVENTS_BROADCAST
         depends on GENERIC_CLOCKEVENTS
         default y if SMP && !LOCAL_TIMERS
 
-config MMU
-        bool
-        default y
-
 config NO_IOPORT
         bool
 
@@ -188,6 +184,13 @@ source "kernel/Kconfig.freezer"
 
 menu "System Type"
 
+config MMU
+        bool "MMU-based Paged Memory Management Support"
+        default y
+        help
+          Select if you want MMU-based virtualised addressing space
+          support by paged memory management. If unsure, say 'Y'.
+
 choice
         prompt "ARM system type"
         default ARCH_VERSATILE
@@ -972,6 +975,21 @@ config HZ
         default AT91_TIMER_HZ if ARCH_AT91
         default 100
 
+config THUMB2_KERNEL
+        bool "Compile the kernel in Thumb-2 mode"
+        depends on CPU_V7 && EXPERIMENTAL
+        select AEABI
+        select ARM_ASM_UNIFIED
+        help
+          By enabling this option, the kernel will be compiled in
+          Thumb-2 mode. A compiler/assembler that understand the unified
+          ARM-Thumb syntax is needed.
+
+          If unsure, say N.
+
+config ARM_ASM_UNIFIED
+        bool
+
 config AEABI
         bool "Use the ARM EABI to compile the kernel"
         help
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index a89e4734b8f0..1a6f70e52921 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -8,6 +8,7 @@ source "lib/Kconfig.debug"
 # n, but then RMK will have to kill you ;).
 config FRAME_POINTER
         bool
+        depends on !THUMB2_KERNEL
         default y if !ARM_UNWIND
         help
           If you say N here, the resulting kernel will be slightly smaller and
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c877d6df23d1..8f117acd98e9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -93,9 +93,16 @@ ifeq ($(CONFIG_ARM_UNWIND),y)
 CFLAGS_ABI      +=-funwind-tables
 endif
 
+ifeq ($(CONFIG_THUMB2_KERNEL),y)
+AFLAGS_AUTOIT   :=$(call as-option,-Wa$(comma)-mimplicit-it=thumb,-Wa$(comma)-mauto-it)
+AFLAGS_NOWARN   :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)
+CFLAGS_THUMB2   :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)
+AFLAGS_THUMB2   :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb
+endif
+
 # Need -Uarm for gcc < 3.x
-KBUILD_CFLAGS   +=$(CFLAGS_ABI) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
-KBUILD_AFLAGS   +=$(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float
+KBUILD_CFLAGS   +=$(CFLAGS_ABI) $(CFLAGS_THUMB2) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
+KBUILD_AFLAGS   +=$(CFLAGS_ABI) $(AFLAGS_THUMB2) $(arch-y) $(tune-y) -include asm/unified.h -msoft-float
 
 CHECKFLAGS      += -D__arm__
 
@@ -135,6 +142,7 @@ machine-$(CONFIG_ARCH_MSM)		:= msm
 machine-$(CONFIG_ARCH_MV78XX0)          := mv78xx0
 machine-$(CONFIG_ARCH_MX1)              := mx1
 machine-$(CONFIG_ARCH_MX2)              := mx2
+machine-$(CONFIG_ARCH_MX25)             := mx25
 machine-$(CONFIG_ARCH_MX3)              := mx3
 machine-$(CONFIG_ARCH_NETX)             := netx
 machine-$(CONFIG_ARCH_NS9XXX)           := ns9xxx
@@ -158,6 +166,7 @@ machine-$(CONFIG_ARCH_U300)		:= u300
 machine-$(CONFIG_ARCH_VERSATILE)        := versatile
 machine-$(CONFIG_ARCH_W90X900)          := w90x900
 machine-$(CONFIG_FOOTBRIDGE)            := footbridge
+machine-$(CONFIG_ARCH_MXC91231)         := mxc91231
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index da226abce2d0..4a590f4113e2 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -61,7 +61,7 @@ endif
 
 quiet_cmd_uimage = UIMAGE  $@
       cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
-                   -C none -a $(LOADADDR) -e $(LOADADDR) \
+                   -C none -a $(LOADADDR) -e $(STARTADDR) \
                    -n 'Linux-$(KERNELRELEASE)' -d $< $@
 
 ifeq ($(CONFIG_ZBOOT_ROM),y)
@@ -70,6 +70,13 @@ else
 $(obj)/uImage: LOADADDR=$(ZRELADDR)
 endif
 
+ifeq ($(CONFIG_THUMB2_KERNEL),y)
+# Set bit 0 to 1 so that "mov pc, rx" switches to Thumb-2 mode
+$(obj)/uImage: STARTADDR=$(shell echo $(LOADADDR) | sed -e "s/.$$/1/")
+else
+$(obj)/uImage: STARTADDR=$(LOADADDR)
+endif
+
 $(obj)/uImage:  $(obj)/zImage FORCE
         $(call if_changed,uimage)
         @echo '  Image $@ is ready'
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 4515728c5345..fa6fbf45cf3b 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -140,7 +140,8 @@ start:
                 tst     r2, #3                  @ not user?
                 bne     not_angel
                 mov     r0, #0x17               @ angel_SWIreason_EnterSVC
-                swi     0x123456                @ angel_SWI_ARM
+ ARM(           swi     0x123456        )       @ angel_SWI_ARM
+ THUMB(         svc     0xab            )       @ angel_SWI_THUMB
 not_angel:
                 mrs     r2, cpsr                @ turn off interrupts to
                 orr     r2, r2, #0xc0           @ prevent angel from running
@@ -161,7 +162,9 @@ not_angel:
 
                 .text
                 adr     r0, LC0
-                ldmia   r0, {r1, r2, r3, r4, r5, r6, ip, sp}
+ ARM(           ldmia   r0, {r1, r2, r3, r4, r5, r6, ip, sp}    )
+ THUMB(         ldmia   r0, {r1, r2, r3, r4, r5, r6, ip}        )
+ THUMB(         ldr     sp, [r0, #28]                           )
                 subs    r0, r0, r1              @ calculate the delta offset
 
                                                 @ if delta is zero, we are
@@ -263,22 +266,25 @@ not_relocated:	mov	r0, #0
  * r6     = processor ID
  * r7     = architecture ID
  * r8     = atags pointer
- * r9-r14 = corrupted
+ * r9-r12,r14 = corrupted
  */
                 add     r1, r5, r0              @ end of decompressed kernel
                 adr     r2, reloc_start
                 ldr     r3, LC1
                 add     r3, r2, r3
-1:              ldmia   r2!, {r9 - r14}         @ copy relocation code
-                stmia   r1!, {r9 - r14}
-                ldmia   r2!, {r9 - r14}
-                stmia   r1!, {r9 - r14}
+1:              ldmia   r2!, {r9 - r12, r14}    @ copy relocation code
+                stmia   r1!, {r9 - r12, r14}
+                ldmia   r2!, {r9 - r12, r14}
+                stmia   r1!, {r9 - r12, r14}
                 cmp     r2, r3
                 blo     1b
-                add     sp, r1, #128            @ relocate the stack
+                mov     sp, r1
+                add     sp, sp, #128            @ relocate the stack
 
                 bl      cache_clean_flush
-                add     pc, r5, r0              @ call relocation code
+ ARM(           add     pc, r5, r0              ) @ call relocation code
+ THUMB(         add     r12, r5, r0             )
+ THUMB(         mov     pc, r12                 ) @ call relocation code
 
 /*
  * We're not in danger of overwriting ourselves.  Do this the simple way.
@@ -291,6 +297,7 @@ wont_overwrite:	mov	r0, r4
                 bl      decompress_kernel
                 b       call_kernel
 
+                .align  2
                 .type   LC0, #object
 LC0:            .word   LC0                     @ r1
                 .word   __bss_start             @ r2
@@ -431,6 +438,7 @@ ENDPROC(__setup_mmu)
 
 __armv4_mmu_cache_on:
                 mov     r12, lr
+#ifdef CONFIG_MMU
                 bl      __setup_mmu
                 mov     r0, #0
                 mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
@@ -444,10 +452,12 @@ __armv4_mmu_cache_on:
                 bl      __common_mmu_cache_on
                 mov     r0, #0
                 mcr     p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
+#endif
                 mov     pc, r12
 
 __armv7_mmu_cache_on:
                 mov     r12, lr
+#ifdef CONFIG_MMU
                 mrc     p15, 0, r11, c0, c1, 4  @ read ID_MMFR0
                 tst     r11, #0xf               @ VMSA
                 blne    __setup_mmu
@@ -455,9 +465,11 @@ __armv7_mmu_cache_on:
                 mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
                 tst     r11, #0xf               @ VMSA
                 mcrne   p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
+#endif
                 mrc     p15, 0, r0, c1, c0, 0   @ read control reg
                 orr     r0, r0, #0x5000         @ I-cache enable, RR cache replacement
                 orr     r0, r0, #0x003c         @ write buffer
+#ifdef CONFIG_MMU
 #ifdef CONFIG_CPU_ENDIAN_BE8
                 orr     r0, r0, #1 << 25        @ big-endian page tables
 #endif
@@ -465,6 +477,7 @@ __armv7_mmu_cache_on:
                 movne   r1, #-1
                 mcrne   p15, 0, r3, c2, c0, 0   @ load page table pointer
                 mcrne   p15, 0, r1, c3, c0, 0   @ load domain access control
+#endif
                 mcr     p15, 0, r0, c1, c0, 0   @ load control register
                 mrc     p15, 0, r0, c1, c0, 0   @ and read it back
                 mov     r0, #0
@@ -498,6 +511,7 @@ __arm6_mmu_cache_on:
                 mov     pc, r12
 
 __common_mmu_cache_on:
+#ifndef CONFIG_THUMB2_KERNEL
 #ifndef DEBUG
                 orr     r0, r0, #0x000d         @ Write buffer, mmu
 #endif
@@ -509,6 +523,7 @@ __common_mmu_cache_on:
 1:              mcr     p15, 0, r0, c1, c0, 0   @ load control register
                 mrc     p15, 0, r0, c1, c0, 0   @ and read it back to
                 sub     pc, lr, r0, lsr #32     @ properly flush pipeline
+#endif
 
 /*
  * All code following this line is relocatable.  It is relocated by
@@ -522,7 +537,7 @@ __common_mmu_cache_on:
  * r6     = processor ID
  * r7     = architecture ID
  * r8     = atags pointer
- * r9-r14 = corrupted
+ * r9-r12,r14 = corrupted
  */
                 .align  5
 reloc_start:    add     r9, r5, r0
@@ -531,13 +546,14 @@ reloc_start:	add	r9, r5, r0
                 mov     r1, r4
 1:
                 .rept   4
-                ldmia   r5!, {r0, r2, r3, r10 - r14}    @ relocate kernel
-                stmia   r1!, {r0, r2, r3, r10 - r14}
+                ldmia   r5!, {r0, r2, r3, r10 - r12, r14}       @ relocate kernel
+                stmia   r1!, {r0, r2, r3, r10 - r12, r14}
                 .endr
 
                 cmp     r5, r9
                 blo     1b
-                add     sp, r1, #128            @ relocate the stack
+                mov     sp, r1
+                add     sp, sp, #128            @ relocate the stack
                 debug_reloc_end
 
 call_kernel:    bl      cache_clean_flush
@@ -571,7 +587,9 @@ call_cache_fn:	adr	r12, proc_types
                 ldr     r2, [r12, #4]           @ get mask
                 eor     r1, r1, r6              @ (real ^ match)
                 tst     r1, r2                  @       & mask
-                addeq   pc, r12, r3             @ call cache function
+ ARM(           addeq   pc, r12, r3             ) @ call cache function
+ THUMB(         addeq   r12, r3                 )
+ THUMB(         moveq   pc, r12                 ) @ call cache function
                 add     r12, r12, #4*5
                 b       1b
 
@@ -589,13 +607,15 @@ call_cache_fn:	adr	r12, proc_types
  * methods.  Writeback caches _must_ have the flush method
  * defined.
  */
+                .align  2
                 .type   proc_types,#object
 proc_types:
                 .word   0x41560600              @ ARM6/610
                 .word   0xffffffe0
-                b       __arm6_mmu_cache_off    @ works, but slow
-                b       __arm6_mmu_cache_off
+                W(b)    __arm6_mmu_cache_off    @ works, but slow
+                W(b)    __arm6_mmu_cache_off
                 mov     pc, lr
+ THUMB(         nop                             )
 @               b       __arm6_mmu_cache_on             @ untested
 @               b       __arm6_mmu_cache_off
 @               b       __armv3_mmu_cache_flush
@@ -603,76 +623,84 @@ proc_types:
                 .word   0x00000000              @ old ARM ID
                 .word   0x0000f000
                 mov     pc, lr
+ THUMB(         nop                             )
                 mov     pc, lr
+ THUMB(         nop                             )
                 mov     pc, lr
+ THUMB(         nop                             )
 
                 .word   0x41007000              @ ARM7/710
                 .word   0xfff8fe00
-                b       __arm7_mmu_cache_off
-                b       __arm7_mmu_cache_off
+                W(b)    __arm7_mmu_cache_off
+                W(b)    __arm7_mmu_cache_off
                 mov     pc, lr
+ THUMB(         nop                             )
 
                 .word   0x41807200              @ ARM720T (writethrough)
                 .word   0xffffff00
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
                 mov     pc, lr
+ THUMB(         nop                             )
 
                 .word   0x41007400              @ ARM74x
                 .word   0xff00ff00
-                b       __armv3_mpu_cache_on
-                b       __armv3_mpu_cache_off
-                b       __armv3_mpu_cache_flush
+                W(b)    __armv3_mpu_cache_on
+                W(b)    __armv3_mpu_cache_off
+                W(b)    __armv3_mpu_cache_flush
                 
                 .word   0x41009400              @ ARM94x
                 .word   0xff00ff00
-                b       __armv4_mpu_cache_on
-                b       __armv4_mpu_cache_off
-                b       __armv4_mpu_cache_flush
+                W(b)    __armv4_mpu_cache_on
+                W(b)    __armv4_mpu_cache_off
+                W(b)    __armv4_mpu_cache_flush
 
                 .word   0x00007000              @ ARM7 IDs
                 .word   0x0000f000
                 mov     pc, lr
+ THUMB(         nop                             )
                 mov     pc, lr
+ THUMB(         nop                             )
                 mov     pc, lr
+ THUMB(         nop                             )
 
                 @ Everything from here on will be the new ID system.
 
                 .word   0x4401a100              @ sa110 / sa1100
                 .word   0xffffffe0
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x6901b110              @ sa1110
                 .word   0xfffffff0
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x56056930
                 .word   0xff0ffff0              @ PXA935
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x56158000              @ PXA168
                 .word   0xfffff000
-                b __armv4_mmu_cache_on
-                b __armv4_mmu_cache_off
-                b __armv5tej_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv5tej_mmu_cache_flush
 
                 .word   0x56056930
                 .word   0xff0ffff0              @ PXA935
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x56050000              @ Feroceon
                 .word   0xff0f0000
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv5tej_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv5tej_mmu_cache_flush
 
 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
                 /* this conflicts with the standard ARMv5TE entry */
@@ -685,47 +713,50 @@ proc_types:
 
                 .word   0x66015261              @ FA526
                 .word   0xff01fff1
-                b       __fa526_cache_on
-                b       __armv4_mmu_cache_off
-                b       __fa526_cache_flush
+                W(b)    __fa526_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __fa526_cache_flush
 
                 @ These match on the architecture ID
 
                 .word   0x00020000              @ ARMv4T
                 .word   0x000f0000
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x00050000              @ ARMv5TE
                 .word   0x000f0000
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x00060000              @ ARMv5TEJ
                 .word   0x000f0000
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv5tej_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_flush
 
                 .word   0x0007b000              @ ARMv6
                 .word   0x000ff000
-                b       __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
-                b       __armv6_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_off
+                W(b)    __armv6_mmu_cache_flush
 
                 .word   0x000f0000              @ new CPU Id
                 .word   0x000f0000
-                b       __armv7_mmu_cache_on
-                b       __armv7_mmu_cache_off
-                b       __armv7_mmu_cache_flush
+                W(b)    __armv7_mmu_cache_on
+                W(b)    __armv7_mmu_cache_off
+                W(b)    __armv7_mmu_cache_flush
 
                 .word   0                       @ unrecognised type
                 .word   0
                 mov     pc, lr
+ THUMB(         nop                             )
                 mov     pc, lr
+ THUMB(         nop                             )
                 mov     pc, lr
+ THUMB(         nop                             )
 
                 .size   proc_types, . - proc_types
 
@@ -760,22 +791,30 @@ __armv3_mpu_cache_off:
                 mov     pc, lr
 
 __armv4_mmu_cache_off:
+#ifdef CONFIG_MMU
                 mrc     p15, 0, r0, c1, c0
                 bic     r0, r0, #0x000d
                 mcr     p15, 0, r0, c1, c0      @ turn MMU and cache off
                 mov     r0, #0
                 mcr     p15, 0, r0, c7, c7      @ invalidate whole cache v4
                 mcr     p15, 0, r0, c8, c7      @ invalidate whole TLB v4
+#endif
                 mov     pc, lr
 
 __armv7_mmu_cache_off:
                 mrc     p15, 0, r0, c1, c0
+#ifdef CONFIG_MMU
                 bic     r0, r0, #0x000d
+#else
+                bic     r0, r0, #0x000c
+#endif
                 mcr     p15, 0, r0, c1, c0      @ turn MMU and cache off
                 mov     r12, lr
                 bl      __armv7_mmu_cache_flush
                 mov     r0, #0
+#ifdef CONFIG_MMU
                 mcr     p15, 0, r0, c8, c7, 0   @ invalidate whole TLB
+#endif
                 mcr     p15, 0, r0, c7, c5, 6   @ invalidate BTC
                 mcr     p15, 0, r0, c7, c10, 4  @ DSB
                 mcr     p15, 0, r0, c7, c5, 4   @ ISB
@@ -852,7 +891,7 @@ __armv7_mmu_cache_flush:
                 b       iflush
 hierarchical:
                 mcr     p15, 0, r10, c7, c10, 5 @ DMB
-                stmfd   sp!, {r0-r5, r7, r9, r11}
+                stmfd   sp!, {r0-r7, r9-r11}
                 mrc     p15, 1, r0, c0, c0, 1   @ read clidr
                 ands    r3, r0, #0x7000000      @ extract loc from clidr
                 mov     r3, r3, lsr #23         @ left align loc bit field
@@ -877,8 +916,12 @@ loop1:
 loop2:
                 mov     r9, r4                  @ create working copy of max way size
 loop3:
-                orr     r11, r10, r9, lsl r5    @ factor way and cache number into r11
-                orr     r11, r11, r7, lsl r2    @ factor index number into r11
+ ARM(           orr     r11, r10, r9, lsl r5    ) @ factor way and cache number into r11
+ ARM(           orr     r11, r11, r7, lsl r2    ) @ factor index number into r11
+ THUMB(         lsl     r6, r9, r5              )
+ THUMB(         orr     r11, r10, r6            ) @ factor way and cache number into r11
+ THUMB(         lsl     r6, r7, r2              )
+ THUMB(         orr     r11, r11, r6            ) @ factor index number into r11
                 mcr     p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
                 subs    r9, r9, #1              @ decrement the way
                 bge     loop3
@@ -889,7 +932,7 @@ skip:
                 cmp     r3, r10
                 bgt     loop1
 finished:
-                ldmfd   sp!, {r0-r5, r7, r9, r11}
+                ldmfd   sp!, {r0-r7, r9-r11}
                 mov     r10, #0                 @ swith back to cache level 0
                 mcr     p15, 2, r10, c0, c0, 0  @ select current cache level in cssr
 iflush:
@@ -923,9 +966,13 @@ __armv4_mmu_cache_flush:
                 mov     r11, #8
                 mov     r11, r11, lsl r3        @ cache line size in bytes
 no_cache_id:
-                bic     r1, pc, #63             @ align to longest cache line
+                mov     r1, pc
+                bic     r1, r1, #63             @ align to longest cache line
                 add     r2, r1, r2
-1:              ldr     r3, [r1], r11           @ s/w flush D cache
+1:
+ ARM(           ldr     r3, [r1], r11           ) @ s/w flush D cache
+ THUMB(         ldr     r3, [r1]                ) @ s/w flush D cache
+ THUMB(         add     r1, r1, r11             )
                 teq     r1, r2
                 bne     1b
 
@@ -945,6 +992,7 @@ __armv3_mpu_cache_flush:
  * memory, which again must be relocatable.
  */
 #ifdef DEBUG
+                .align  2
                 .type   phexbuf,#object
 phexbuf:        .space  12
                 .size   phexbuf, . - phexbuf
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 44912cd5da13..00f46d9ce299 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -166,3 +166,87 @@
 #endif
 #endif
         .endm
+
+#ifdef CONFIG_THUMB2_KERNEL
+        .macro  setmode, mode, reg
+        mov     \reg, #\mode
+        msr     cpsr_c, \reg
+        .endm
+#else
+        .macro  setmode, mode, reg
+        msr     cpsr_c, #\mode
+        .endm
+#endif
+
+/*
+ * STRT/LDRT access macros with ARM and Thumb-2 variants
+ */
+#ifdef CONFIG_THUMB2_KERNEL
+
+        .macro  usraccoff, instr, reg, ptr, inc, off, cond, abort
+9999:
+        .if     \inc == 1
+        \instr\cond\()bt \reg, [\ptr, #\off]
+        .elseif \inc == 4
+        \instr\cond\()t \reg, [\ptr, #\off]
+        .else
+        .error  "Unsupported inc macro argument"
+        .endif
+
+        .section __ex_table,"a"
+        .align  3
+        .long   9999b, \abort
+        .previous
+        .endm
+
+        .macro  usracc, instr, reg, ptr, inc, cond, rept, abort
+        @ explicit IT instruction needed because of the label
+        @ introduced by the USER macro
+        .ifnc   \cond,al
+        .if     \rept == 1
+        itt     \cond
+        .elseif \rept == 2
+        ittt    \cond
+        .else
+        .error  "Unsupported rept macro argument"
+        .endif
+        .endif
+
+        @ Slightly optimised to avoid incrementing the pointer twice
+        usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
+        .if     \rept == 2
+        usraccoff \instr, \reg, \ptr, \inc, 4, \cond, \abort
+        .endif
+
+        add\cond \ptr, #\rept * \inc
+        .endm
+
+#else   /* !CONFIG_THUMB2_KERNEL */
+
+        .macro  usracc, instr, reg, ptr, inc, cond, rept, abort
+        .rept   \rept
+9999:
+        .if     \inc == 1
+        \instr\cond\()bt \reg, [\ptr], #\inc
+        .elseif \inc == 4
+        \instr\cond\()t \reg, [\ptr], #\inc
+        .else
+        .error  "Unsupported inc macro argument"
+        .endif
+
+        .section __ex_table,"a"
+        .align  3
+        .long   9999b, \abort
+        .previous
+        .endr
+        .endm
+
+#endif  /* CONFIG_THUMB2_KERNEL */
+
+        .macro  strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
+        usracc  str, \reg, \ptr, \inc, \cond, \rept, \abort
+        .endm
+
+        .macro  ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
+        usracc  ldr, \reg, \ptr, \inc, \cond, \rept, \abort
+        .endm
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index c207504de84d..c3b911ee9151 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -55,6 +55,9 @@ typedef struct user_fp elf_fpregset_t;
 #define R_ARM_MOVW_ABS_NC       43
 #define R_ARM_MOVT_ABS          44
 
+#define R_ARM_THM_CALL          10
+#define R_ARM_THM_JUMP24        30
+
 /*
  * These are used to set parameters in the core dumps.
  */
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 9ee743b95de8..bfcc15929a7f 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -99,6 +99,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
         __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
         "1:     ldrt    %0, [%3]\n"
         "       teq     %0, %1\n"
+        "       it      eq      @ explicit IT needed for the 2b label\n"
         "2:     streqt  %2, [%3]\n"
         "3:\n"
         "       .section __ex_table,\"a\"\n"
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 85763db87449..376be1a62866 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -44,7 +44,13 @@
  * The module space lives between the addresses given by TASK_SIZE
  * and PAGE_OFFSET - it must be within 32MB of the kernel text.
  */
+#ifndef CONFIG_THUMB2_KERNEL
 #define MODULES_VADDR           (PAGE_OFFSET - 16*1024*1024)
+#else
+/* smaller range for Thumb-2 symbols relocation (2^24)*/
+#define MODULES_VADDR           (PAGE_OFFSET - 8*1024*1024)
+#endif
+
 #if TASK_SIZE > MODULES_VADDR
 #error Top of user space clashes with start of module space
 #endif
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index 263fed05ea33..bcdb9291ef0c 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -62,8 +62,10 @@ static inline void check_context(struct mm_struct *mm)
 
 static inline void check_context(struct mm_struct *mm)
 {
+#ifdef CONFIG_MMU
         if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
                 __check_kvm_seq(mm);
+#endif
 }
 
 #define init_new_context(tsk,mm)        0
diff --git a/arch/arm/include/asm/page-nommu.h b/arch/arm/include/asm/page-nommu.h
index 3574c0deb37f..d1b162a18dcb 100644
--- a/arch/arm/include/asm/page-nommu.h
+++ b/arch/arm/include/asm/page-nommu.h
@@ -43,7 +43,4 @@ typedef unsigned long pgprot_t;
 #define __pmd(x)        (x)
 #define __pgprot(x)     (x)
 
-extern unsigned long memory_start;
-extern unsigned long memory_end;
-
 #endif
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 67b833c9b6b9..bbecccda76d0 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -82,6 +82,14 @@
 #define PSR_ENDSTATE    0
 #endif
 
+/* 
+ * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
+ * process is located in memory.
+ */
+#define PT_TEXT_ADDR            0x10000
+#define PT_DATA_ADDR            0x10004
+#define PT_TEXT_END_ADDR        0x10008
+
 #ifndef __ASSEMBLY__
 
 /*
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 0da9bc9b3b1d..1d6bd40a4322 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -17,6 +17,7 @@
 #include <asm/memory.h>
 #include <asm/domain.h>
 #include <asm/system.h>
+#include <asm/unified.h>
 
 #define VERIFY_READ 0
 #define VERIFY_WRITE 1
@@ -365,8 +366,10 @@ do {									\
 
 #define __put_user_asm_dword(x,__pu_addr,err)                   \
         __asm__ __volatile__(                                   \
-        "1:     strt    " __reg_oper1 ", [%1], #4\n"            \
-        "2:     strt    " __reg_oper0 ", [%1]\n"                \
+ ARM(   "1:     strt    " __reg_oper1 ", [%1], #4\n"    )       \
+ ARM(   "2:     strt    " __reg_oper0 ", [%1]\n"        )       \
+ THUMB( "1:     strt    " __reg_oper1 ", [%1]\n"        )       \
+ THUMB( "2:     strt    " __reg_oper0 ", [%1, #4]\n"    )       \
         "3:\n"                                                  \
         "       .section .fixup,\"ax\"\n"                       \
         "       .align  2\n"                                    \
diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h
new file mode 100644
index 000000000000..073e85b9b961
--- /dev/null
+++ b/arch/arm/include/asm/unified.h
@@ -0,0 +1,126 @@
+/*
+ * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_UNIFIED_H
+#define __ASM_UNIFIED_H
+
+#if defined(__ASSEMBLY__) && defined(CONFIG_ARM_ASM_UNIFIED)
+        .syntax unified
+#endif
+
+#ifdef CONFIG_THUMB2_KERNEL
+
+#if __GNUC__ < 4
+#error Thumb-2 kernel requires gcc >= 4
+#endif
+
+/* The CPSR bit describing the instruction set (Thumb) */
+#define PSR_ISETSTATE   PSR_T_BIT
+
+#define ARM(x...)
+#define THUMB(x...)     x
+#define W(instr)        instr.w
+#define BSYM(sym)       sym + 1
+
+#else   /* !CONFIG_THUMB2_KERNEL */
+
+/* The CPSR bit describing the instruction set (ARM) */
+#define PSR_ISETSTATE   0
+
+#define ARM(x...)       x
+#define THUMB(x...)
+#define W(instr)        instr
+#define BSYM(sym)       sym
+
+#endif  /* CONFIG_THUMB2_KERNEL */
+
+#ifndef CONFIG_ARM_ASM_UNIFIED
+
+/*
+ * If the unified assembly syntax isn't used (in ARM mode), these
+ * macros expand to an empty string
+ */
+#ifdef __ASSEMBLY__
+        .macro  it, cond
+        .endm
+        .macro  itt, cond
+        .endm
+        .macro  ite, cond
+        .endm
+        .macro  ittt, cond
+        .endm
+        .macro  itte, cond
+        .endm
+        .macro  itet, cond
+        .endm
+        .macro  itee, cond
+        .endm
+        .macro  itttt, cond
+        .endm
+        .macro  ittte, cond
+        .endm
+        .macro  ittet, cond
+        .endm
+        .macro  ittee, cond
+        .endm
+        .macro  itett, cond
+        .endm
+        .macro  itete, cond
+        .endm
+        .macro  iteet, cond
+        .endm
+        .macro  iteee, cond
+        .endm
+#else   /* !__ASSEMBLY__ */
+__asm__(
+"       .macro  it, cond\n"
+"       .endm\n"
+"       .macro  itt, cond\n"
+"       .endm\n"
+"       .macro  ite, cond\n"
+"       .endm\n"
+"       .macro  ittt, cond\n"
+"       .endm\n"
+"       .macro  itte, cond\n"
+"       .endm\n"
+"       .macro  itet, cond\n"
+"       .endm\n"
+"       .macro  itee, cond\n"
+"       .endm\n"
+"       .macro  itttt, cond\n"
+"       .endm\n"
+"       .macro  ittte, cond\n"
+"       .endm\n"
+"       .macro  ittet, cond\n"
+"       .endm\n"
+"       .macro  ittee, cond\n"
+"       .endm\n"
+"       .macro  itett, cond\n"
+"       .endm\n"
+"       .macro  itete, cond\n"
+"       .endm\n"
+"       .macro  iteet, cond\n"
+"       .endm\n"
+"       .macro  iteee, cond\n"
+"       .endm\n");
+#endif  /* __ASSEMBLY__ */
+
+#endif  /* CONFIG_ARM_ASM_UNIFIED */
+
+#endif  /* !__ASM_UNIFIED_H */
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 792abd0dfae1..3d727a8a23bc 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -34,7 +34,7 @@
         @
         @ routine called with r0 = irq number, r1 = struct pt_regs *
         @
-        adrne   lr, 1b
+        adrne   lr, BSYM(1b)
         bne     asm_do_IRQ
 
 #ifdef CONFIG_SMP
@@ -46,13 +46,13 @@
          */
         test_for_ipi r0, r6, r5, lr
         movne   r0, sp
-        adrne   lr, 1b
+        adrne   lr, BSYM(1b)
         bne     do_IPI
 
 #ifdef CONFIG_LOCAL_TIMERS
         test_for_ltirq r0, r6, r5, lr
         movne   r0, sp
-        adrne   lr, 1b
+        adrne   lr, BSYM(1b)
         bne     do_local_timer
 #endif
 #endif
@@ -70,7 +70,10 @@
  */
         .macro  inv_entry, reason
         sub     sp, sp, #S_FRAME_SIZE
-        stmib   sp, {r1 - lr}
+ ARM(   stmib   sp, {r1 - lr}           )
+ THUMB( stmia   sp, {r0 - r12}          )
+ THUMB( str     sp, [sp, #S_SP]         )
+ THUMB( str     lr, [sp, #S_LR]         )
         mov     r1, #\reason
         .endm
 
@@ -126,17 +129,24 @@ ENDPROC(__und_invalid)
         .macro  svc_entry, stack_hole=0
  UNWIND(.fnstart                )
  UNWIND(.save {r0 - pc}         )
-        sub     sp, sp, #(S_FRAME_SIZE + \stack_hole)
+        sub     sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
+#ifdef CONFIG_THUMB2_KERNEL
+ SPFIX( str     r0, [sp]        )       @ temporarily saved
+ SPFIX( mov     r0, sp          )
+ SPFIX( tst     r0, #4          )       @ test original stack alignment
+ SPFIX( ldr     r0, [sp]        )       @ restored
+#else
  SPFIX( tst     sp, #4          )
- SPFIX( bicne   sp, sp, #4      )
-        stmib   sp, {r1 - r12}
+#endif
+ SPFIX( subeq   sp, sp, #4      )
+        stmia   sp, {r1 - r12}
 
         ldmia   r0, {r1 - r3}
-        add     r5, sp, #S_SP           @ here for interlock avoidance
+        add     r5, sp, #S_SP - 4       @ here for interlock avoidance
         mov     r4, #-1                 @  ""  ""      ""       ""
-        add     r0, sp, #(S_FRAME_SIZE + \stack_hole)
- SPFIX( addne   r0, r0, #4      )
-        str     r1, [sp]                @ save the "real" r0 copied
+        add     r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
+ SPFIX( addeq   r0, r0, #4      )
+        str     r1, [sp, #-4]!          @ save the "real" r0 copied
                                         @ from the exception stack
 
         mov     r1, lr
@@ -198,9 +208,8 @@ __dabt_svc:
         @
         @ restore SPSR and restart the instruction
         @
-        ldr     r0, [sp, #S_PSR]
-        msr     spsr_cxsf, r0
-        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+        ldr     r2, [sp, #S_PSR]
+        svc_exit r2                             @ return from exception
  UNWIND(.fnend          )
 ENDPROC(__dabt_svc)
 
@@ -224,13 +233,12 @@ __irq_svc:
         tst     r0, #_TIF_NEED_RESCHED
         blne    svc_preempt
 #endif
-        ldr     r0, [sp, #S_PSR]                @ irqs are already disabled
-        msr     spsr_cxsf, r0
+        ldr     r4, [sp, #S_PSR]                @ irqs are already disabled
 #ifdef CONFIG_TRACE_IRQFLAGS
-        tst     r0, #PSR_I_BIT
+        tst     r4, #PSR_I_BIT
         bleq    trace_hardirqs_on
 #endif
-        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+        svc_exit r4                             @ return from exception
  UNWIND(.fnend          )
 ENDPROC(__irq_svc)
 
@@ -265,7 +273,7 @@ __und_svc:
         @  r0 - instruction
         @
         ldr     r0, [r2, #-4]
-        adr     r9, 1f
+        adr     r9, BSYM(1f)
         bl      call_fpe
 
         mov     r0, sp                          @ struct pt_regs *regs
@@ -279,9 +287,8 @@ __und_svc:
         @
         @ restore SPSR and restart the instruction
         @
-        ldr     lr, [sp, #S_PSR]                @ Get SVC cpsr
-        msr     spsr_cxsf, lr
-        ldmia   sp, {r0 - pc}^                  @ Restore SVC registers
+        ldr     r2, [sp, #S_PSR]                @ Get SVC cpsr
+        svc_exit r2                             @ return from exception
  UNWIND(.fnend          )
 ENDPROC(__und_svc)
 
@@ -322,9 +329,8 @@ __pabt_svc:
         @
         @ restore SPSR and restart the instruction
         @
-        ldr     r0, [sp, #S_PSR]
-        msr     spsr_cxsf, r0
-        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+        ldr     r2, [sp, #S_PSR]
+        svc_exit r2                             @ return from exception
  UNWIND(.fnend          )
 ENDPROC(__pabt_svc)
 
@@ -352,7 +358,8 @@ ENDPROC(__pabt_svc)
  UNWIND(.fnstart        )
  UNWIND(.cantunwind     )       @ don't unwind the user space
         sub     sp, sp, #S_FRAME_SIZE
-        stmib   sp, {r1 - r12}
+ ARM(   stmib   sp, {r1 - r12}  )
+ THUMB( stmia   sp, {r0 - r12}  )
 
         ldmia   r0, {r1 - r3}
         add     r0, sp, #S_PC           @ here for interlock avoidance
@@ -371,7 +378,8 @@ ENDPROC(__pabt_svc)
         @ Also, separately save sp_usr and lr_usr
         @
         stmia   r0, {r2 - r4}
-        stmdb   r0, {sp, lr}^
+ ARM(   stmdb   r0, {sp, lr}^                   )
+ THUMB( store_user_sp_lr r0, r1, S_SP - S_PC    )
 
         @
         @ Enable the alignment trap while in kernel mode
@@ -428,7 +436,7 @@ __dabt_usr:
         @
         enable_irq
         mov     r2, sp
-        adr     lr, ret_from_exception
+        adr     lr, BSYM(ret_from_exception)
         b       do_DataAbort
  UNWIND(.fnend          )
 ENDPROC(__dabt_usr)
@@ -450,7 +458,9 @@ __irq_usr:
         ldr     r0, [tsk, #TI_PREEMPT]
         str     r8, [tsk, #TI_PREEMPT]
         teq     r0, r7
-        strne   r0, [r0, -r0]
+ ARM(   strne   r0, [r0, -r0]   )
+ THUMB( movne   r0, #0          )
+ THUMB( strne   r0, [r0]        )
 #endif
 #ifdef CONFIG_TRACE_IRQFLAGS
         bl      trace_hardirqs_on
@@ -474,9 +484,10 @@ __und_usr:
         @
         @  r0 - instruction
         @
-        adr     r9, ret_from_exception
-        adr     lr, __und_usr_unknown
+        adr     r9, BSYM(ret_from_exception)
+        adr     lr, BSYM(__und_usr_unknown)
         tst     r3, #PSR_T_BIT                  @ Thumb mode?
+        itet    eq                              @ explicit IT needed for the 1f label
         subeq   r4, r2, #4                      @ ARM instr at LR - 4
         subne   r4, r2, #2                      @ Thumb instr at LR - 2
 1:      ldreqt  r0, [r4]
@@ -486,7 +497,10 @@ __und_usr:
         beq     call_fpe
         @ Thumb instruction
 #if __LINUX_ARM_ARCH__ >= 7
-2:      ldrht   r5, [r4], #2
+2:
+ ARM(   ldrht   r5, [r4], #2    )
+ THUMB( ldrht   r5, [r4]        )
+ THUMB( add     r4, r4, #2      )
         and     r0, r5, #0xf800                 @ mask bits 111x x... .... ....
         cmp     r0, #0xe800                     @ 32bit instruction if xx != 0
         blo     __und_usr_unknown
@@ -575,9 +589,11 @@ call_fpe:
         moveq   pc, lr
         get_thread_info r10                     @ get current thread
         and     r8, r0, #0x00000f00             @ mask out CP number
+ THUMB( lsr     r8, r8, #8              )
         mov     r7, #1
         add     r6, r10, #TI_USED_CP
-        strb    r7, [r6, r8, lsr #8]            @ set appropriate used_cp[]
+ ARM(   strb    r7, [r6, r8, lsr #8]    )       @ set appropriate used_cp[]
+ THUMB( strb    r7, [r6, r8]            )       @ set appropriate used_cp[]
 #ifdef CONFIG_IWMMXT
         @ Test if we need to give access to iWMMXt coprocessors
         ldr     r5, [r10, #TI_FLAGS]
@@ -585,36 +601,38 @@ call_fpe:
         movcss  r7, r5, lsr #(TIF_USING_IWMMXT + 1)
         bcs     iwmmxt_task_enable
 #endif
-        add     pc, pc, r8, lsr #6
-        mov     r0, r0
-
-        mov     pc, lr                          @ CP#0
-        b       do_fpe                          @ CP#1 (FPE)
-        b       do_fpe                          @ CP#2 (FPE)
-        mov     pc, lr                          @ CP#3
+ ARM(   add     pc, pc, r8, lsr #6      )
+ THUMB( lsl     r8, r8, #2              )
+ THUMB( add     pc, r8                  )
+        nop
+
+        W(mov)  pc, lr                          @ CP#0
+        W(b)    do_fpe                          @ CP#1 (FPE)
+        W(b)    do_fpe                          @ CP#2 (FPE)
+        W(mov)  pc, lr                          @ CP#3
 #ifdef CONFIG_CRUNCH
         b       crunch_task_enable              @ CP#4 (MaverickCrunch)
         b       crunch_task_enable              @ CP#5 (MaverickCrunch)
         b       crunch_task_enable              @ CP#6 (MaverickCrunch)
 #else
-        mov     pc, lr                          @ CP#4
-        mov     pc, lr                          @ CP#5
-        mov     pc, lr                          @ CP#6
+        W(mov)  pc, lr                          @ CP#4
+        W(mov)  pc, lr                          @ CP#5
+        W(mov)  pc, lr                          @ CP#6
 #endif
-        mov     pc, lr                          @ CP#7
-        mov     pc, lr                          @ CP#8
-        mov     pc, lr                          @ CP#9
+        W(mov)  pc, lr                          @ CP#7
+        W(mov)  pc, lr                          @ CP#8
+        W(mov)  pc, lr                          @ CP#9
 #ifdef CONFIG_VFP
-        b       do_vfp                          @ CP#10 (VFP)
-        b       do_vfp                          @ CP#11 (VFP)
+        W(b)    do_vfp                          @ CP#10 (VFP)
+        W(b)    do_vfp                          @ CP#11 (VFP)
 #else
-        mov     pc, lr                          @ CP#10 (VFP)
-        mov     pc, lr                          @ CP#11 (VFP)
+        W(mov)  pc, lr                          @ CP#10 (VFP)
+        W(mov)  pc, lr                          @ CP#11 (VFP)
 #endif
-        mov     pc, lr                          @ CP#12
-        mov     pc, lr                          @ CP#13
-        mov     pc, lr                          @ CP#14 (Debug)
-        mov     pc, lr                          @ CP#15 (Control)
+        W(mov)  pc, lr                          @ CP#12
+        W(mov)  pc, lr                          @ CP#13
+        W(mov)  pc, lr                          @ CP#14 (Debug)
+        W(mov)  pc, lr                          @ CP#15 (Control)
 
 #ifdef CONFIG_NEON
         .align  6
@@ -665,7 +683,7 @@ no_fp:	mov	pc, lr
 __und_usr_unknown:
         enable_irq
         mov     r0, sp
-        adr     lr, ret_from_exception
+        adr     lr, BSYM(ret_from_exception)
         b       do_undefinstr
 ENDPROC(__und_usr_unknown)
 
@@ -709,7 +727,10 @@ ENTRY(__switch_to)
  UNWIND(.cantunwind     )
         add     ip, r1, #TI_CPU_SAVE
         ldr     r3, [r2, #TI_TP_VALUE]
-        stmia   ip!, {r4 - sl, fp, sp, lr}      @ Store most regs on stack
+ ARM(   stmia   ip!, {r4 - sl, fp, sp, lr} )    @ Store most regs on stack
+ THUMB( stmia   ip!, {r4 - sl, fp}         )    @ Store most regs on stack
+ THUMB( str     sp, [ip], #4               )
+ THUMB( str     lr, [ip], #4               )
 #ifdef CONFIG_MMU
         ldr     r6, [r2, #TI_CPU_DOMAIN]
 #endif
@@ -734,8 +755,12 @@ ENTRY(__switch_to)
         ldr     r0, =thread_notify_head
         mov     r1, #THREAD_NOTIFY_SWITCH
         bl      atomic_notifier_call_chain
+ THUMB( mov     ip, r4                     )
         mov     r0, r5
-        ldmia   r4, {r4 - sl, fp, sp, pc}       @ Load all regs saved previously
+ ARM(   ldmia   r4, {r4 - sl, fp, sp, pc}  )    @ Load all regs saved previously
+ THUMB( ldmia   ip!, {r4 - sl, fp}         )    @ Load all regs saved previously
+ THUMB( ldr     sp, [ip], #4               )
+ THUMB( ldr     pc, [ip]                   )
  UNWIND(.fnend          )
 ENDPROC(__switch_to)
 
@@ -770,6 +795,7 @@ ENDPROC(__switch_to)
  * if your compiled code is not going to use the new instructions for other
  * purpose.
  */
+ THUMB( .arm    )
 
         .macro  usr_ret, reg
 #ifdef CONFIG_ARM_THUMB
@@ -1018,6 +1044,7 @@ __kuser_helper_version:				@ 0xffff0ffc
         .globl  __kuser_helper_end
 __kuser_helper_end:
 
+ THUMB( .thumb  )
 
 /*
  * Vector stubs.
@@ -1052,17 +1079,23 @@ vector_\name:
         @ Prepare for SVC32 mode.  IRQs remain disabled.
         @
         mrs     r0, cpsr
-        eor     r0, r0, #(\mode ^ SVC_MODE)
+        eor     r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
         msr     spsr_cxsf, r0
 
         @
         @ the branch table must immediately follow this code
         @
         and     lr, lr, #0x0f
+ THUMB( adr     r0, 1f                  )
+ THUMB( ldr     lr, [r0, lr, lsl #2]    )
         mov     r0, sp
-        ldr     lr, [pc, lr, lsl #2]
+ ARM(   ldr     lr, [pc, lr, lsl #2]    )
         movs    pc, lr                  @ branch to handler in SVC mode
 ENDPROC(vector_\name)
+
+        .align  2
+        @ handler addresses follow this label
+1:
         .endm
 
         .globl  __stubs_start
@@ -1200,14 +1233,16 @@ __stubs_end:
 
         .globl  __vectors_start
 __vectors_start:
-        swi     SYS_ERROR0
-        b       vector_und + stubs_offset
-        ldr     pc, .LCvswi + stubs_offset
-        b       vector_pabt + stubs_offset
-        b       vector_dabt + stubs_offset
-        b       vector_addrexcptn + stubs_offset
-        b       vector_irq + stubs_offset
-        b       vector_fiq + stubs_offset
+ ARM(   swi     SYS_ERROR0      )
+ THUMB( svc     #0              )
+ THUMB( nop                     )
+        W(b)    vector_und + stubs_offset
+        W(ldr)  pc, .LCvswi + stubs_offset
+        W(b)    vector_pabt + stubs_offset
+        W(b)    vector_dabt + stubs_offset
+        W(b)    vector_addrexcptn + stubs_offset
+        W(b)    vector_irq + stubs_offset
+        W(b)    vector_fiq + stubs_offset
 
         .globl  __vectors_end
 __vectors_end:
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 99208728d48f..df19e8bf2e4a 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -33,14 +33,7 @@ ret_fast_syscall:
         /* perform architecture specific actions before user return */
         arch_ret_to_user r1, lr
 
-        @ fast_restore_user_regs
-        ldr     r1, [sp, #S_OFF + S_PSR]        @ get calling cpsr
-        ldr     lr, [sp, #S_OFF + S_PC]!        @ get pc
-        msr     spsr_cxsf, r1                   @ save in spsr_svc
-        ldmdb   sp, {r1 - lr}^                  @ get calling r1 - lr
-        mov     r0, r0
-        add     sp, sp, #S_FRAME_SIZE - S_PC
-        movs    pc, lr                          @ return & move spsr_svc into cpsr
+        restore_user_regs fast = 1, offset = S_OFF
  UNWIND(.fnend          )
 
 /*
@@ -73,14 +66,7 @@ no_work_pending:
         /* perform architecture specific actions before user return */
         arch_ret_to_user r1, lr
 
-        @ slow_restore_user_regs
-        ldr     r1, [sp, #S_PSR]                @ get calling cpsr
-        ldr     lr, [sp, #S_PC]!                @ get pc
-        msr     spsr_cxsf, r1                   @ save in spsr_svc
-        ldmdb   sp, {r0 - lr}^                  @ get calling r0 - lr
-        mov     r0, r0
-        add     sp, sp, #S_FRAME_SIZE - S_PC
-        movs    pc, lr                          @ return & move spsr_svc into cpsr
+        restore_user_regs fast = 0, offset = 0
 ENDPROC(ret_to_user)
 
 /*
@@ -201,8 +187,10 @@ ftrace_stub:
 ENTRY(vector_swi)
         sub     sp, sp, #S_FRAME_SIZE
         stmia   sp, {r0 - r12}                  @ Calling r0 - r12
-        add     r8, sp, #S_PC
-        stmdb   r8, {sp, lr}^                   @ Calling sp, lr
+ ARM(   add     r8, sp, #S_PC           )
+ ARM(   stmdb   r8, {sp, lr}^           )       @ Calling sp, lr
+ THUMB( mov     r8, sp                  )
+ THUMB( store_user_sp_lr r8, r10, S_SP  )       @ calling sp, lr
         mrs     r8, spsr                        @ called from non-FIQ mode, so ok.
         str     lr, [sp, #S_PC]                 @ Save calling PC
         str     r8, [sp, #S_PSR]                @ Save CPSR
@@ -291,7 +279,7 @@ ENTRY(vector_swi)
         bne     __sys_trace
 
         cmp     scno, #NR_syscalls              @ check upper syscall limit
-        adr     lr, ret_fast_syscall            @ return address
+        adr     lr, BSYM(ret_fast_syscall)      @ return address
         ldrcc   pc, [tbl, scno, lsl #2]         @ call sys_* routine
 
         add     r1, sp, #S_OFF
@@ -312,7 +300,7 @@ __sys_trace:
         mov     r0, #0                          @ trace entry [IP = 0]
         bl      syscall_trace
 
-        adr     lr, __sys_trace_return          @ return address
+        adr     lr, BSYM(__sys_trace_return)    @ return address
         mov     scno, r0                        @ syscall number (possibly new)
         add     r1, sp, #S_R0 + S_OFF           @ pointer to regs
         cmp     scno, #NR_syscalls              @ check upper syscall limit
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 87ab4e157997..a4eaf4f920c5 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -36,11 +36,6 @@
 #endif
         .endm
 
-        .macro  get_thread_info, rd
-        mov     \rd, sp, lsr #13
-        mov     \rd, \rd, lsl #13
-        .endm
-
         .macro  alignment_trap, rtemp
 #ifdef CONFIG_ALIGNMENT_TRAP
         ldr     \rtemp, .LCcralign
@@ -49,6 +44,93 @@
 #endif
         .endm
 
+        @
+        @ Store/load the USER SP and LR registers by switching to the SYS
+        @ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
+        @ available. Should only be called from SVC mode
+        @
+        .macro  store_user_sp_lr, rd, rtemp, offset = 0
+        mrs     \rtemp, cpsr
+        eor     \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
+        msr     cpsr_c, \rtemp                  @ switch to the SYS mode
+
+        str     sp, [\rd, #\offset]             @ save sp_usr
+        str     lr, [\rd, #\offset + 4]         @ save lr_usr
+
+        eor     \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
+        msr     cpsr_c, \rtemp                  @ switch back to the SVC mode
+        .endm
+
+        .macro  load_user_sp_lr, rd, rtemp, offset = 0
+        mrs     \rtemp, cpsr
+        eor     \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
+        msr     cpsr_c, \rtemp                  @ switch to the SYS mode
+
+        ldr     sp, [\rd, #\offset]             @ load sp_usr
+        ldr     lr, [\rd, #\offset + 4]         @ load lr_usr
+
+        eor     \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
+        msr     cpsr_c, \rtemp                  @ switch back to the SVC mode
+        .endm
+
+#ifndef CONFIG_THUMB2_KERNEL
+        .macro  svc_exit, rpsr
+        msr     spsr_cxsf, \rpsr
+        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+        .endm
+
+        .macro  restore_user_regs, fast = 0, offset = 0
+        ldr     r1, [sp, #\offset + S_PSR]      @ get calling cpsr
+        ldr     lr, [sp, #\offset + S_PC]!      @ get pc
+        msr     spsr_cxsf, r1                   @ save in spsr_svc
+        .if     \fast
+        ldmdb   sp, {r1 - lr}^                  @ get calling r1 - lr
+        .else
+        ldmdb   sp, {r0 - lr}^                  @ get calling r0 - lr
+        .endif
+        add     sp, sp, #S_FRAME_SIZE - S_PC
+        movs    pc, lr                          @ return & move spsr_svc into cpsr
+        .endm
+
+        .macro  get_thread_info, rd
+        mov     \rd, sp, lsr #13
+        mov     \rd, \rd, lsl #13
+        .endm
+#else   /* CONFIG_THUMB2_KERNEL */
+        .macro  svc_exit, rpsr
+        ldr     r0, [sp, #S_SP]                 @ top of the stack
+        ldr     r1, [sp, #S_PC]                 @ return address
+        tst     r0, #4                          @ orig stack 8-byte aligned?
+        stmdb   r0, {r1, \rpsr}                 @ rfe context
+        ldmia   sp, {r0 - r12}
+        ldr     lr, [sp, #S_LR]
+        addeq   sp, sp, #S_FRAME_SIZE - 8       @ aligned
+        addne   sp, sp, #S_FRAME_SIZE - 4       @ not aligned
+        rfeia   sp!
+        .endm
+
+        .macro  restore_user_regs, fast = 0, offset = 0
+        mov     r2, sp
+        load_user_sp_lr r2, r3, \offset + S_SP  @ calling sp, lr
+        ldr     r1, [sp, #\offset + S_PSR]      @ get calling cpsr
+        ldr     lr, [sp, #\offset + S_PC]       @ get pc
+        add     sp, sp, #\offset + S_SP
+        msr     spsr_cxsf, r1                   @ save in spsr_svc
+        .if     \fast
+        ldmdb   sp, {r1 - r12}                  @ get calling r1 - r12
+        .else
+        ldmdb   sp, {r0 - r12}                  @ get calling r0 - r12
+        .endif
+        add     sp, sp, #S_FRAME_SIZE - S_SP
+        movs    pc, lr                          @ return & move spsr_svc into cpsr
+        .endm
+
+        .macro  get_thread_info, rd
+        mov     \rd, sp
+        lsr     \rd, \rd, #13
+        mov     \rd, \rd, lsl #13
+        .endm
+#endif  /* !CONFIG_THUMB2_KERNEL */
 
 /*
  * These are the registers used in the syscall handler, and allow us to
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 991952c644d1..93ad576b2d74 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -14,6 +14,7 @@
 #define ATAG_CORE 0x54410001
 #define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2)
 
+        .align  2
         .type   __switch_data, %object
 __switch_data:
         .long   __mmap_switched
@@ -51,7 +52,9 @@ __mmap_switched:
         strcc   fp, [r6],#4
         bcc     1b
 
-        ldmia   r3, {r4, r5, r6, r7, sp}
+ ARM(   ldmia   r3, {r4, r5, r6, r7, sp})
+ THUMB( ldmia   r3, {r4, r5, r6, r7}    )
+ THUMB( ldr     sp, [r3, #16]           )
         str     r9, [r4]                        @ Save processor ID
         str     r1, [r5]                        @ Save machine type
         str     r2, [r6]                        @ Save atags pointer
@@ -155,7 +158,8 @@ ENDPROC(__error)
  */
 __lookup_processor_type:
         adr     r3, 3f
-        ldmda   r3, {r5 - r7}
+        ldmia   r3, {r5 - r7}
+        add     r3, r3, #8
         sub     r3, r3, r7                      @ get offset between virt&phys
         add     r5, r5, r3                      @ convert virt addresses to
         add     r6, r6, r3                      @ physical address space
@@ -185,9 +189,10 @@ ENDPROC(lookup_processor_type)
  * Look in <asm/procinfo.h> and arch/arm/kernel/arch.[ch] for
  * more information about the __proc_info and __arch_info structures.
  */
-        .long   __proc_info_begin
+        .align  2
+3:      .long   __proc_info_begin
         .long   __proc_info_end
-3:      .long   .
+4:      .long   .
         .long   __arch_info_begin
         .long   __arch_info_end
 
@@ -203,7 +208,7 @@ ENDPROC(lookup_processor_type)
  *  r5 = mach_info pointer in physical address space
  */
 __lookup_machine_type:
-        adr     r3, 3b
+        adr     r3, 4b
         ldmia   r3, {r4, r5, r6}
         sub     r3, r3, r4                      @ get offset between virt&phys
         add     r5, r5, r3                      @ convert virt addresses to
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index cc87e1765ed2..e5dfc2895e24 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -34,7 +34,7 @@
  */
         .section ".text.head", "ax"
 ENTRY(stext)
-        msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                 @ and irqs disabled
 #ifndef CONFIG_CPU_CP15
         ldr     r9, =CONFIG_PROCESSOR_ID
@@ -50,8 +50,10 @@ ENTRY(stext)
 
         ldr     r13, __switch_data              @ address to jump to after
                                                 @ the initialization is done
-        adr     lr, __after_proc_init           @ return (PIC) address
-        add     pc, r10, #PROCINFO_INITFUNC
+        adr     lr, BSYM(__after_proc_init)     @ return (PIC) address
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
 ENDPROC(stext)
 
 /*
@@ -59,7 +61,10 @@ ENDPROC(stext)
  */
 __after_proc_init:
 #ifdef CONFIG_CPU_CP15
-        mrc     p15, 0, r0, c1, c0, 0           @ read control reg
+        /*
+         * CP15 system control register value returned in r0 from
+         * the CPU init function.
+         */
 #ifdef CONFIG_ALIGNMENT_TRAP
         orr     r0, r0, #CR_A
 #else
@@ -82,7 +87,8 @@ __after_proc_init:
         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 #endif /* CONFIG_CPU_CP15 */
 
-        mov     pc, r13                         @ clear the BSS and jump
+        mov     r3, r13
+        mov     pc, r3                          @ clear the BSS and jump
                                                 @ to start_kernel
 ENDPROC(__after_proc_init)
         .ltorg
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 21e17dc94cb5..38ccbe1d3b2c 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -76,7 +76,7 @@
  */
         .section ".text.head", "ax"
 ENTRY(stext)
-        msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                 @ and irqs disabled
         mrc     p15, 0, r9, c0, c0              @ get processor id
         bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
@@ -97,8 +97,10 @@ ENTRY(stext)
          */
         ldr     r13, __switch_data              @ address to jump to after
                                                 @ mmu has been enabled
-        adr     lr, __enable_mmu                @ return (PIC) address
-        add     pc, r10, #PROCINFO_INITFUNC
+        adr     lr, BSYM(__enable_mmu)          @ return (PIC) address
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
 ENDPROC(stext)
 
 #if defined(CONFIG_SMP)
@@ -110,7 +112,7 @@ ENTRY(secondary_startup)
          * the processor type - there is no need to check the machine type
          * as it has already been validated by the primary processor.
          */
-        msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
         mrc     p15, 0, r9, c0, c0              @ get processor id
         bl      __lookup_processor_type
         movs    r10, r5                         @ invalid processor?
@@ -121,12 +123,15 @@ ENTRY(secondary_startup)
          * Use the page tables supplied from  __cpu_up.
          */
         adr     r4, __secondary_data
-        ldmia   r4, {r5, r7, r13}               @ address to jump to after
+        ldmia   r4, {r5, r7, r12}               @ address to jump to after
         sub     r4, r4, r5                      @ mmu has been enabled
         ldr     r4, [r7, r4]                    @ get secondary_data.pgdir
-        adr     lr, __enable_mmu                @ return address
-        add     pc, r10, #PROCINFO_INITFUNC     @ initialise processor
-                                                @ (return control reg)
+        adr     lr, BSYM(__enable_mmu)          @ return address
+        mov     r13, r12                        @ __secondary_switched address
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     ) @ initialise processor
+                                                  @ (return control reg)
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
 ENDPROC(secondary_startup)
 
         /*
@@ -193,8 +198,8 @@ __turn_mmu_on:
         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
         mrc     p15, 0, r3, c0, c0, 0           @ read id reg
         mov     r3, r3
-        mov     r3, r3
-        mov     pc, r13
+        mov     r3, r13
+        mov     pc, r3
 ENDPROC(__turn_mmu_on)
 
 
@@ -235,7 +240,8 @@ __create_page_tables:
          * will be removed by paging_init().  We use our current program
          * counter to determine corresponding section base address.
          */
-        mov     r6, pc, lsr #20                 @ start of kernel section
+        mov     r6, pc
+        mov     r6, r6, lsr #20                 @ start of kernel section
         orr     r3, r7, r6, lsl #20             @ flags + kernel base
         str     r3, [r4, r6, lsl #2]            @ identity mapping
 
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index bac03c81489d..f28c5e9c51ea 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -102,6 +102,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
                 unsigned long loc;
                 Elf32_Sym *sym;
                 s32 offset;
+                u32 upper, lower, sign, j1, j2;
 
                 offset = ELF32_R_SYM(rel->r_info);
                 if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym))) {
@@ -184,6 +185,58 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
                                         (offset & 0x0fff);
                         break;
 
+                case R_ARM_THM_CALL:
+                case R_ARM_THM_JUMP24:
+                        upper = *(u16 *)loc;
+                        lower = *(u16 *)(loc + 2);
+
+                        /*
+                         * 25 bit signed address range (Thumb-2 BL and B.W
+                         * instructions):
+                         *   S:I1:I2:imm10:imm11:0
+                         * where:
+                         *   S     = upper[10]   = offset[24]
+                         *   I1    = ~(J1 ^ S)   = offset[23]
+                         *   I2    = ~(J2 ^ S)   = offset[22]
+                         *   imm10 = upper[9:0]  = offset[21:12]
+                         *   imm11 = lower[10:0] = offset[11:1]
+                         *   J1    = lower[13]
+                         *   J2    = lower[11]
+                         */
+                        sign = (upper >> 10) & 1;
+                        j1 = (lower >> 13) & 1;
+                        j2 = (lower >> 11) & 1;
+                        offset = (sign << 24) | ((~(j1 ^ sign) & 1) << 23) |
+                                ((~(j2 ^ sign) & 1) << 22) |
+                                ((upper & 0x03ff) << 12) |
+                                ((lower & 0x07ff) << 1);
+                        if (offset & 0x01000000)
+                                offset -= 0x02000000;
+                        offset += sym->st_value - loc;
+
+                        /* only Thumb addresses allowed (no interworking) */
+                        if (!(offset & 1) ||
+                            offset <= (s32)0xff000000 ||
+                            offset >= (s32)0x01000000) {
+                                printk(KERN_ERR
+                                       "%s: relocation out of range, section "
+                                       "%d reloc %d sym '%s'\n", module->name,
+                                       relindex, i, strtab + sym->st_name);
+                                return -ENOEXEC;
+                        }
+
+                        sign = (offset >> 24) & 1;
+                        j1 = sign ^ (~(offset >> 23) & 1);
+                        j2 = sign ^ (~(offset >> 22) & 1);
+                        *(u16 *)loc = (u16)((upper & 0xf800) | (sign << 10) |
+                                            ((offset >> 12) & 0x03ff));
+                        *(u16 *)(loc + 2) = (u16)((lower & 0xd000) |
+                                                  (j1 << 13) | (j2 << 11) |
+                                                  ((offset >> 1) & 0x07ff));
+                        upper = *(u16 *)loc;
+                        lower = *(u16 *)(loc + 2);
+                        break;
+
                 default:
                         printk(KERN_ERR "%s: unknown relocation: %u\n",
                                module->name, ELF32_R_TYPE(rel->r_info));
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 39196dff478c..790fbee92ec5 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -388,7 +388,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
         regs.ARM_r2 = (unsigned long)fn;
         regs.ARM_r3 = (unsigned long)kernel_thread_exit;
         regs.ARM_pc = (unsigned long)kernel_thread_helper;
-        regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE;
+        regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE;
 
         return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
 }
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 89882a1d0187..a2ea3854cb3c 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -521,7 +521,13 @@ static int ptrace_read_user(struct task_struct *tsk, unsigned long off,
                 return -EIO;
 
         tmp = 0;
-        if (off < sizeof(struct pt_regs))
+        if (off == PT_TEXT_ADDR)
+                tmp = tsk->mm->start_code;
+        else if (off == PT_DATA_ADDR)
+                tmp = tsk->mm->start_data;
+        else if (off == PT_TEXT_END_ADDR)
+                tmp = tsk->mm->end_code;
+        else if (off < sizeof(struct pt_regs))
                 tmp = get_user_reg(tsk, off >> 2);
 
         return put_user(tmp, ret);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index bc5e4128f9f3..d4d4f77c91b2 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -25,6 +25,7 @@
 #include <linux/smp.h>
 #include <linux/fs.h>
 
+#include <asm/unified.h>
 #include <asm/cpu.h>
 #include <asm/cputype.h>
 #include <asm/elf.h>
@@ -327,25 +328,38 @@ void cpu_init(void)
         }
 
         /*
+         * Define the placement constraint for the inline asm directive below.
+         * In Thumb-2, msr with an immediate value is not allowed.
+         */
+#ifdef CONFIG_THUMB2_KERNEL
+#define PLC     "r"
+#else
+#define PLC     "I"
+#endif
+
+        /*
          * setup stacks for re-entrant exception handlers
          */
         __asm__ (
         "msr    cpsr_c, %1\n\t"
-        "add    sp, %0, %2\n\t"
+        "add    r14, %0, %2\n\t"
+        "mov    sp, r14\n\t"
         "msr    cpsr_c, %3\n\t"
-        "add    sp, %0, %4\n\t"
+        "add    r14, %0, %4\n\t"
+        "mov    sp, r14\n\t"
         "msr    cpsr_c, %5\n\t"
-        "add    sp, %0, %6\n\t"
+        "add    r14, %0, %6\n\t"
+        "mov    sp, r14\n\t"
         "msr    cpsr_c, %7"
             :
             : "r" (stk),
-              "I" (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
+              PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
               "I" (offsetof(struct stack, irq[0])),
-              "I" (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
+              PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
               "I" (offsetof(struct stack, abt[0])),
-              "I" (PSR_F_BIT | PSR_I_BIT | UND_MODE),
+              PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
               "I" (offsetof(struct stack, und[0])),
-              "I" (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
+              PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
             : "r14");
 }
 
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index dd56e11f339a..39baf1128bfa 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -62,7 +62,11 @@ struct unwind_ctrl_block {
 };
 
 enum regs {
+#ifdef CONFIG_THUMB2_KERNEL
+        FP = 7,
+#else
         FP = 11,
+#endif
         SP = 13,
         LR = 14,
         PC = 15
diff --git a/arch/arm/lib/ashldi3.S b/arch/arm/lib/ashldi3.S
index 1154d924080b..638deb13da1c 100644
--- a/arch/arm/lib/ashldi3.S
+++ b/arch/arm/lib/ashldi3.S
@@ -43,7 +43,9 @@ ENTRY(__aeabi_llsl)
         rsb     ip, r2, #32
         movmi   ah, ah, lsl r2
         movpl   ah, al, lsl r3
-        orrmi   ah, ah, al, lsr ip
+ ARM(   orrmi   ah, ah, al, lsr ip      )
+ THUMB( lsrmi   r3, al, ip              )
+ THUMB( orrmi   ah, ah, r3              )
         mov     al, al, lsl r2
         mov     pc, lr
 
diff --git a/arch/arm/lib/ashrdi3.S b/arch/arm/lib/ashrdi3.S
index 9f8b35572f8c..015e8aa5a1d1 100644
--- a/arch/arm/lib/ashrdi3.S
+++ b/arch/arm/lib/ashrdi3.S
@@ -43,7 +43,9 @@ ENTRY(__aeabi_lasr)
         rsb     ip, r2, #32
         movmi   al, al, lsr r2
         movpl   al, ah, asr r3
-        orrmi   al, al, ah, lsl ip
+ ARM(   orrmi   al, al, ah, lsl ip      )
+ THUMB( lslmi   r3, ah, ip              )
+ THUMB( orrmi   al, al, r3              )
         mov     ah, ah, asr r2
         mov     pc, lr
 
diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S
index b0951d0e8b2c..aaf7220d9e30 100644
--- a/arch/arm/lib/backtrace.S
+++ b/arch/arm/lib/backtrace.S
@@ -38,7 +38,9 @@ ENDPROC(c_backtrace)
                 beq     no_frame                @ we have no stack frames
 
                 tst     r1, #0x10               @ 26 or 32-bit mode?
-                moveq   mask, #0xfc000003       @ mask for 26-bit
+ ARM(           moveq   mask, #0xfc000003       )
+ THUMB(         moveq   mask, #0xfc000000       )
+ THUMB(         orreq   mask, #0x03             )
                 movne   mask, #0                @ mask for 32-bit
 
 1:              stmfd   sp!, {pc}               @ calculate offset of PC stored
@@ -126,7 +128,9 @@ ENDPROC(c_backtrace)
                 mov     reg, #10
                 mov     r7, #0
 1:              mov     r3, #1
-                tst     instr, r3, lsl reg
+ ARM(           tst     instr, r3, lsl reg      )
+ THUMB(         lsl     r3, reg                 )
+ THUMB(         tst     instr, r3               )
                 beq     2f
                 add     r7, r7, #1
                 teq     r7, #6
diff --git a/arch/arm/lib/clear_user.S b/arch/arm/lib/clear_user.S
index 844f56785ebc..1279abd8b886 100644
--- a/arch/arm/lib/clear_user.S
+++ b/arch/arm/lib/clear_user.S
@@ -27,21 +27,20 @@ WEAK(__clear_user)
                 ands    ip, r0, #3
                 beq     1f
                 cmp     ip, #2
-USER(           strbt   r2, [r0], #1)
-USER(           strlebt r2, [r0], #1)
-USER(           strltbt r2, [r0], #1)
+                strusr  r2, r0, 1
+                strusr  r2, r0, 1, le
+                strusr  r2, r0, 1, lt
                 rsb     ip, ip, #4
                 sub     r1, r1, ip              @  7  6  5  4  3  2  1
 1:              subs    r1, r1, #8              @ -1 -2 -3 -4 -5 -6 -7
-USER(           strplt  r2, [r0], #4)
-USER(           strplt  r2, [r0], #4)
+                strusr  r2, r0, 4, pl, rept=2
                 bpl     1b
                 adds    r1, r1, #4              @  3  2  1  0 -1 -2 -3
-USER(           strplt  r2, [r0], #4)
+                strusr  r2, r0, 4, pl
 2:              tst     r1, #2                  @ 1x 1x 0x 0x 1x 1x 0x
-USER(           strnebt r2, [r0], #1)
-USER(           strnebt r2, [r0], #1)
+                strusr  r2, r0, 1, ne, rept=2
                 tst     r1, #1                  @ x1 x0 x1 x0 x1 x0 x1
+                it      ne                      @ explicit IT needed for the label
 USER(           strnebt r2, [r0])
                 mov     r0, #0
                 ldmfd   sp!, {r1, pc}
diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
index 56799a165cc4..e4fe124acedc 100644
--- a/arch/arm/lib/copy_from_user.S
+++ b/arch/arm/lib/copy_from_user.S
@@ -33,11 +33,15 @@
  *      Number of bytes NOT copied.
  */
 
+#ifndef CONFIG_THUMB2_KERNEL
+#define LDR1W_SHIFT     0
+#else
+#define LDR1W_SHIFT     1
+#endif
+#define STR1W_SHIFT     0
+
         .macro ldr1w ptr reg abort
-100:    ldrt \reg, [\ptr], #4
-        .section __ex_table, "a"
-        .long 100b, \abort
-        .previous
+        ldrusr  \reg, \ptr, 4, abort=\abort
         .endm
 
         .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
@@ -53,14 +57,11 @@
         .endm
 
         .macro ldr1b ptr reg cond=al abort
-100:    ldr\cond\()bt \reg, [\ptr], #1
-        .section __ex_table, "a"
-        .long 100b, \abort
-        .previous
+        ldrusr  \reg, \ptr, 1, \cond, abort=\abort
         .endm
 
         .macro str1w ptr reg abort
-        str \reg, [\ptr], #4
+        W(str) \reg, [\ptr], #4
         .endm
 
         .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index 139cce646055..805e3f8fb007 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -57,6 +57,13 @@
  *
  *      Restore registers with the values previously saved with the
  *      'preserv' macro. Called upon code termination.
+ *
+ * LDR1W_SHIFT
+ * STR1W_SHIFT
+ *
+ *      Correction to be applied to the "ip" register when branching into
+ *      the ldr1w or str1w instructions (some of these macros may expand to
+ *      than one 32bit instruction in Thumb-2)
  */
 
 
@@ -99,9 +106,15 @@
 
 5:              ands    ip, r2, #28
                 rsb     ip, ip, #32
+#if LDR1W_SHIFT > 0
+                lsl     ip, ip, #LDR1W_SHIFT
+#endif
                 addne   pc, pc, ip              @ C is always clear here
                 b       7f
-6:              nop
+6:
+                .rept   (1 << LDR1W_SHIFT)
+                W(nop)
+                .endr
                 ldr1w   r1, r3, abort=20f
                 ldr1w   r1, r4, abort=20f
                 ldr1w   r1, r5, abort=20f
@@ -110,9 +123,16 @@
                 ldr1w   r1, r8, abort=20f
                 ldr1w   r1, lr, abort=20f
 
+#if LDR1W_SHIFT < STR1W_SHIFT
+                lsl     ip, ip, #STR1W_SHIFT - LDR1W_SHIFT
+#elif LDR1W_SHIFT > STR1W_SHIFT
+                lsr     ip, ip, #LDR1W_SHIFT - STR1W_SHIFT
+#endif
                 add     pc, pc, ip
                 nop
-                nop
+                .rept   (1 << STR1W_SHIFT)
+                W(nop)
+                .endr
                 str1w   r0, r3, abort=20f
                 str1w   r0, r4, abort=20f
                 str1w   r0, r5, abort=20f
diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
index 878820f0a320..1a71e1584442 100644
--- a/arch/arm/lib/copy_to_user.S
+++ b/arch/arm/lib/copy_to_user.S
@@ -33,8 +33,15 @@
  *      Number of bytes NOT copied.
  */
 
+#define LDR1W_SHIFT     0
+#ifndef CONFIG_THUMB2_KERNEL
+#define STR1W_SHIFT     0
+#else
+#define STR1W_SHIFT     1
+#endif
+
         .macro ldr1w ptr reg abort
-        ldr \reg, [\ptr], #4
+        W(ldr) \reg, [\ptr], #4
         .endm
 
         .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
@@ -50,10 +57,7 @@
         .endm
 
         .macro str1w ptr reg abort
-100:    strt \reg, [\ptr], #4
-        .section __ex_table, "a"
-        .long 100b, \abort
-        .previous
+        strusr  \reg, \ptr, 4, abort=\abort
         .endm
 
         .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
@@ -68,10 +72,7 @@
         .endm
 
         .macro str1b ptr reg cond=al abort
-100:    str\cond\()bt \reg, [\ptr], #1
-        .section __ex_table, "a"
-        .long 100b, \abort
-        .previous
+        strusr  \reg, \ptr, 1, \cond, abort=\abort
         .endm
 
         .macro enter reg1 reg2
diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S
index 14677fb4b0c4..fd0e9dcd9fdc 100644
--- a/arch/arm/lib/csumpartialcopyuser.S
+++ b/arch/arm/lib/csumpartialcopyuser.S
@@ -26,50 +26,28 @@
                 .endm
 
                 .macro  load1b, reg1
-9999:           ldrbt   \reg1, [r0], $1
-                .section __ex_table, "a"
-                .align  3
-                .long   9999b, 6001f
-                .previous
+                ldrusr  \reg1, r0, 1
                 .endm
 
                 .macro  load2b, reg1, reg2
-9999:           ldrbt   \reg1, [r0], $1
-9998:           ldrbt   \reg2, [r0], $1
-                .section __ex_table, "a"
-                .long   9999b, 6001f
-                .long   9998b, 6001f
-                .previous
+                ldrusr  \reg1, r0, 1
+                ldrusr  \reg2, r0, 1
                 .endm
 
                 .macro  load1l, reg1
-9999:           ldrt    \reg1, [r0], $4
-                .section __ex_table, "a"
-                .align  3
-                .long   9999b, 6001f
-                .previous
+                ldrusr  \reg1, r0, 4
                 .endm
 
                 .macro  load2l, reg1, reg2
-9999:           ldrt    \reg1, [r0], $4
-9998:           ldrt    \reg2, [r0], $4
-                .section __ex_table, "a"
-                .long   9999b, 6001f
-                .long   9998b, 6001f
-                .previous
+                ldrusr  \reg1, r0, 4
+                ldrusr  \reg2, r0, 4
                 .endm
 
                 .macro  load4l, reg1, reg2, reg3, reg4
-9999:           ldrt    \reg1, [r0], $4
-9998:           ldrt    \reg2, [r0], $4
-9997:           ldrt    \reg3, [r0], $4
-9996:           ldrt    \reg4, [r0], $4
-                .section __ex_table, "a"
-                .long   9999b, 6001f
-                .long   9998b, 6001f
-                .long   9997b, 6001f
-                .long   9996b, 6001f
-                .previous
+                ldrusr  \reg1, r0, 4
+                ldrusr  \reg2, r0, 4
+                ldrusr  \reg3, r0, 4
+                ldrusr  \reg4, r0, 4
                 .endm
 
 /*
@@ -92,14 +70,14 @@
  */
                 .section .fixup,"ax"
                 .align  4
-6001:           mov     r4, #-EFAULT
+9001:           mov     r4, #-EFAULT
                 ldr     r5, [fp, #4]            @ *err_ptr
                 str     r4, [r5]
                 ldmia   sp, {r1, r2}            @ retrieve dst, len
                 add     r2, r2, r1
                 mov     r0, #0                  @ zero the buffer
-6002:           teq     r2, r1
+9002:           teq     r2, r1
                 strneb  r0, [r1], #1
-                bne     6002b
+                bne     9002b
                 load_regs
                 .previous
diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
index 1425e789ba86..faa7748142da 100644
--- a/arch/arm/lib/div64.S
+++ b/arch/arm/lib/div64.S
@@ -177,7 +177,9 @@ ENTRY(__do_div64)
         mov     yh, xh, lsr ip
         mov     yl, xl, lsr ip
         rsb     ip, ip, #32
-        orr     yl, yl, xh, lsl ip
+ ARM(   orr     yl, yl, xh, lsl ip      )
+ THUMB( lsl     xh, xh, ip              )
+ THUMB( orr     yl, yl, xh              )
         mov     xh, xl, lsl ip
         mov     xh, xh, lsr ip
         mov     pc, lr
diff --git a/arch/arm/lib/findbit.S b/arch/arm/lib/findbit.S
index 8c4defc4f3c4..1e4cbd4e7be9 100644
--- a/arch/arm/lib/findbit.S
+++ b/arch/arm/lib/findbit.S
@@ -25,7 +25,10 @@ ENTRY(_find_first_zero_bit_le)
                 teq     r1, #0  
                 beq     3f
                 mov     r2, #0
-1:              ldrb    r3, [r0, r2, lsr #3]
+1:
+ ARM(           ldrb    r3, [r0, r2, lsr #3]    )
+ THUMB(         lsr     r3, r2, #3              )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 eors    r3, r3, #0xff           @ invert bits
                 bne     .L_found                @ any now set - found zero bit
                 add     r2, r2, #8              @ next bit pointer
@@ -44,7 +47,9 @@ ENTRY(_find_next_zero_bit_le)
                 beq     3b
                 ands    ip, r2, #7
                 beq     1b                      @ If new byte, goto old routine
-                ldrb    r3, [r0, r2, lsr #3]
+ ARM(           ldrb    r3, [r0, r2, lsr #3]    )
+ THUMB(         lsr     r3, r2, #3              )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 eor     r3, r3, #0xff           @ now looking for a 1 bit
                 movs    r3, r3, lsr ip          @ shift off unused bits
                 bne     .L_found
@@ -61,7 +66,10 @@ ENTRY(_find_first_bit_le)
                 teq     r1, #0  
                 beq     3f
                 mov     r2, #0
-1:              ldrb    r3, [r0, r2, lsr #3]
+1:
+ ARM(           ldrb    r3, [r0, r2, lsr #3]    )
+ THUMB(         lsr     r3, r2, #3              )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 movs    r3, r3
                 bne     .L_found                @ any now set - found zero bit
                 add     r2, r2, #8              @ next bit pointer
@@ -80,7 +88,9 @@ ENTRY(_find_next_bit_le)
                 beq     3b
                 ands    ip, r2, #7
                 beq     1b                      @ If new byte, goto old routine
-                ldrb    r3, [r0, r2, lsr #3]
+ ARM(           ldrb    r3, [r0, r2, lsr #3]    )
+ THUMB(         lsr     r3, r2, #3              )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 movs    r3, r3, lsr ip          @ shift off unused bits
                 bne     .L_found
                 orr     r2, r2, #7              @ if zero, then no bits here
@@ -95,7 +105,9 @@ ENTRY(_find_first_zero_bit_be)
                 beq     3f
                 mov     r2, #0
 1:              eor     r3, r2, #0x18           @ big endian byte ordering
-                ldrb    r3, [r0, r3, lsr #3]
+ ARM(           ldrb    r3, [r0, r3, lsr #3]    )
+ THUMB(         lsr     r3, #3                  )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 eors    r3, r3, #0xff           @ invert bits
                 bne     .L_found                @ any now set - found zero bit
                 add     r2, r2, #8              @ next bit pointer
@@ -111,7 +123,9 @@ ENTRY(_find_next_zero_bit_be)
                 ands    ip, r2, #7
                 beq     1b                      @ If new byte, goto old routine
                 eor     r3, r2, #0x18           @ big endian byte ordering
-                ldrb    r3, [r0, r3, lsr #3]
+ ARM(           ldrb    r3, [r0, r3, lsr #3]    )
+ THUMB(         lsr     r3, #3                  )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 eor     r3, r3, #0xff           @ now looking for a 1 bit
                 movs    r3, r3, lsr ip          @ shift off unused bits
                 bne     .L_found
@@ -125,7 +139,9 @@ ENTRY(_find_first_bit_be)
                 beq     3f
                 mov     r2, #0
 1:              eor     r3, r2, #0x18           @ big endian byte ordering
-                ldrb    r3, [r0, r3, lsr #3]
+ ARM(           ldrb    r3, [r0, r3, lsr #3]    )
+ THUMB(         lsr     r3, #3                  )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 movs    r3, r3
                 bne     .L_found                @ any now set - found zero bit
                 add     r2, r2, #8              @ next bit pointer
@@ -141,7 +157,9 @@ ENTRY(_find_next_bit_be)
                 ands    ip, r2, #7
                 beq     1b                      @ If new byte, goto old routine
                 eor     r3, r2, #0x18           @ big endian byte ordering
-                ldrb    r3, [r0, r3, lsr #3]
+ ARM(           ldrb    r3, [r0, r3, lsr #3]    )
+ THUMB(         lsr     r3, #3                  )
+ THUMB(         ldrb    r3, [r0, r3]            )
                 movs    r3, r3, lsr ip          @ shift off unused bits
                 bne     .L_found
                 orr     r2, r2, #7              @ if zero, then no bits here
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index 6763088b7607..a1814d927122 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -36,8 +36,13 @@ ENTRY(__get_user_1)
 ENDPROC(__get_user_1)
 
 ENTRY(__get_user_2)
+#ifdef CONFIG_THUMB2_KERNEL
+2:      ldrbt   r2, [r0]
+3:      ldrbt   r3, [r0, #1]
+#else
 2:      ldrbt   r2, [r0], #1
 3:      ldrbt   r3, [r0]
+#endif
 #ifndef __ARMEB__
         orr     r2, r2, r3, lsl #8
 #else
diff --git a/arch/arm/lib/io-writesw-armv4.S b/arch/arm/lib/io-writesw-armv4.S
index d6585612c86b..ff4f71b579ee 100644
--- a/arch/arm/lib/io-writesw-armv4.S
+++ b/arch/arm/lib/io-writesw-armv4.S
@@ -75,7 +75,10 @@ ENTRY(__raw_writesw)
 #endif
 
 .Loutsw_noalign:
-                ldr     r3, [r1, -r3]!
+ ARM(           ldr     r3, [r1, -r3]!  )
+ THUMB(         rsb     r3, r3, #0      )
+ THUMB(         ldr     r3, [r1, r3]    )
+ THUMB(         sub     r1, r3          )
                 subcs   r2, r2, #1
                 bcs     2f
                 subs    r2, r2, #2
diff --git a/arch/arm/lib/lshrdi3.S b/arch/arm/lib/lshrdi3.S
index 99ea338bf87c..f83d449141f7 100644
--- a/arch/arm/lib/lshrdi3.S
+++ b/arch/arm/lib/lshrdi3.S
@@ -43,7 +43,9 @@ ENTRY(__aeabi_llsr)
         rsb     ip, r2, #32
         movmi   al, al, lsr r2
         movpl   al, ah, lsr r3
-        orrmi   al, al, ah, lsl ip
+ ARM(   orrmi   al, al, ah, lsl ip      )
+ THUMB( lslmi   r3, ah, ip              )
+ THUMB( orrmi   al, al, r3              )
         mov     ah, ah, lsr r2
         mov     pc, lr
 
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index e0d002641d3f..a9b9e2287a09 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -13,8 +13,11 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+#define LDR1W_SHIFT     0
+#define STR1W_SHIFT     0
+
         .macro ldr1w ptr reg abort
-        ldr \reg, [\ptr], #4
+        W(ldr) \reg, [\ptr], #4
         .endm
 
         .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
@@ -30,7 +33,7 @@
         .endm
 
         .macro str1w ptr reg abort
-        str \reg, [\ptr], #4
+        W(str) \reg, [\ptr], #4
         .endm
 
         .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
index 12549187088c..5025c863713d 100644
--- a/arch/arm/lib/memmove.S
+++ b/arch/arm/lib/memmove.S
@@ -75,24 +75,24 @@ ENTRY(memmove)
                 addne   pc, pc, ip              @ C is always clear here
                 b       7f
 6:              nop
-                ldr     r3, [r1, #-4]!
-                ldr     r4, [r1, #-4]!
-                ldr     r5, [r1, #-4]!
-                ldr     r6, [r1, #-4]!
-                ldr     r7, [r1, #-4]!
-                ldr     r8, [r1, #-4]!
-                ldr     lr, [r1, #-4]!
+                W(ldr)  r3, [r1, #-4]!
+                W(ldr)  r4, [r1, #-4]!
+                W(ldr)  r5, [r1, #-4]!
+                W(ldr)  r6, [r1, #-4]!
+                W(ldr)  r7, [r1, #-4]!
+                W(ldr)  r8, [r1, #-4]!
+                W(ldr)  lr, [r1, #-4]!
 
                 add     pc, pc, ip
                 nop
                 nop
-                str     r3, [r0, #-4]!
-                str     r4, [r0, #-4]!
-                str     r5, [r0, #-4]!
-                str     r6, [r0, #-4]!
-                str     r7, [r0, #-4]!
-                str     r8, [r0, #-4]!
-                str     lr, [r0, #-4]!
+                W(str)  r3, [r0, #-4]!
+                W(str)  r4, [r0, #-4]!
+                W(str)  r5, [r0, #-4]!
+                W(str)  r6, [r0, #-4]!
+                W(str)  r7, [r0, #-4]!
+                W(str)  r8, [r0, #-4]!
+                W(str)  lr, [r0, #-4]!
 
         CALGN(  bcs     2b                      )
 
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S
index 864f3c1c4f18..02fedbf07c0d 100644
--- a/arch/arm/lib/putuser.S
+++ b/arch/arm/lib/putuser.S
@@ -37,6 +37,15 @@ ENDPROC(__put_user_1)
 
 ENTRY(__put_user_2)
         mov     ip, r2, lsr #8
+#ifdef CONFIG_THUMB2_KERNEL
+#ifndef __ARMEB__
+2:      strbt   r2, [r0]
+3:      strbt   ip, [r0, #1]
+#else
+2:      strbt   ip, [r0]
+3:      strbt   r2, [r0, #1]
+#endif
+#else   /* !CONFIG_THUMB2_KERNEL */
 #ifndef __ARMEB__
 2:      strbt   r2, [r0], #1
 3:      strbt   ip, [r0]
@@ -44,6 +53,7 @@ ENTRY(__put_user_2)
 2:      strbt   ip, [r0], #1
 3:      strbt   r2, [r0]
 #endif
+#endif  /* CONFIG_THUMB2_KERNEL */
         mov     r0, #0
         mov     pc, lr
 ENDPROC(__put_user_2)
@@ -55,8 +65,13 @@ ENTRY(__put_user_4)
 ENDPROC(__put_user_4)
 
 ENTRY(__put_user_8)
+#ifdef CONFIG_THUMB2_KERNEL
+5:      strt    r2, [r0]
+6:      strt    r3, [r0, #4]
+#else
 5:      strt    r2, [r0], #4
 6:      strt    r3, [r0]
+#endif
         mov     r0, #0
         mov     pc, lr
 ENDPROC(__put_user_8)
diff --git a/arch/arm/lib/sha1.S b/arch/arm/lib/sha1.S
index a16fb208c841..09b548cac1a4 100644
--- a/arch/arm/lib/sha1.S
+++ b/arch/arm/lib/sha1.S
@@ -187,6 +187,7 @@ ENTRY(sha_transform)
 
 ENDPROC(sha_transform)
 
+        .align  2
 .L_sha_K:
         .word   0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6
 
@@ -195,6 +196,7 @@ ENDPROC(sha_transform)
  * void sha_init(__u32 *buf)
  */
 
+        .align  2
 .L_sha_initial_digest:
         .word   0x67452301, 0xefcdab89, 0x98badcfe, 0x10325476, 0xc3d2e1f0
 
diff --git a/arch/arm/lib/strncpy_from_user.S b/arch/arm/lib/strncpy_from_user.S
index 330373c26dd9..1c9814f346c6 100644
--- a/arch/arm/lib/strncpy_from_user.S
+++ b/arch/arm/lib/strncpy_from_user.S
@@ -23,7 +23,7 @@
 ENTRY(__strncpy_from_user)
         mov     ip, r1
 1:      subs    r2, r2, #1
-USER(   ldrplbt r3, [r1], #1)
+        ldrusr  r3, r1, 1, pl
         bmi     2f
         strb    r3, [r0], #1
         teq     r3, #0
diff --git a/arch/arm/lib/strnlen_user.S b/arch/arm/lib/strnlen_user.S
index 90bb9d020836..7855b2906659 100644
--- a/arch/arm/lib/strnlen_user.S
+++ b/arch/arm/lib/strnlen_user.S
@@ -23,7 +23,7 @@
 ENTRY(__strnlen_user)
         mov     r2, r0
 1:
-USER(   ldrbt   r3, [r0], #1)
+        ldrusr  r3, r0, 1
         teq     r3, #0
         beq     2f
         subs    r1, r1, #1
diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h
index 1251319ef9ae..d795642fad22 100644
--- a/arch/arm/mach-integrator/include/mach/hardware.h
+++ b/arch/arm/mach-integrator/include/mach/hardware.h
@@ -36,8 +36,12 @@
 #define PCIO_BASE               PCI_IO_VADDR
 #define PCIMEM_BASE             PCI_MEMORY_VADDR
 
+#ifdef CONFIG_MMU
 /* macro to get at IO space when running virtually */
 #define IO_ADDRESS(x) (((x) >> 4) + IO_BASE) 
+#else
+#define IO_ADDRESS(x) (x)
+#endif
 
 #define pcibios_assign_all_busses()     1
 
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 4ac04055c2ea..452931b2690e 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -49,14 +49,14 @@
 
 #define INTCP_PA_CLCD_BASE              0xc0000000
 
-#define INTCP_VA_CIC_BASE               0xf1000040
-#define INTCP_VA_PIC_BASE               0xf1400000
-#define INTCP_VA_SIC_BASE               0xfca00000
+#define INTCP_VA_CIC_BASE               IO_ADDRESS(INTEGRATOR_HDR_BASE) + 0x40
+#define INTCP_VA_PIC_BASE               IO_ADDRESS(INTEGRATOR_IC_BASE)
+#define INTCP_VA_SIC_BASE               IO_ADDRESS(0xca000000)
 
 #define INTCP_PA_ETH_BASE               0xc8000000
 #define INTCP_ETH_SIZE                  0x10
 
-#define INTCP_VA_CTRL_BASE              0xfcb00000
+#define INTCP_VA_CTRL_BASE              IO_ADDRESS(0xcb000000)
 #define INTCP_FLASHPROG                 0x04
 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
@@ -121,12 +121,12 @@ static struct map_desc intcp_io_desc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = 0xfca00000,
+                .virtual        = IO_ADDRESS(0xca000000),
                 .pfn            = __phys_to_pfn(0xca000000),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = 0xfcb00000,
+                .virtual        = IO_ADDRESS(0xcb000000),
                 .pfn            = __phys_to_pfn(0xcb000000),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE
@@ -394,8 +394,8 @@ static struct platform_device *intcp_devs[] __initdata = {
  */
 static unsigned int mmc_status(struct device *dev)
 {
-        unsigned int status = readl(0xfca00004);
-        writel(8, 0xfcb00008);
+        unsigned int status = readl(IO_ADDRESS(0xca000000) + 4);
+        writel(8, IO_ADDRESS(0xcb000000) + 8);
 
         return status & 8;
 }
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 25100f7acf4c..0aca451b216d 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -38,6 +38,12 @@ config MACH_TS219
           Say 'Y' here if you want your kernel to support the
           QNAP TS-119 and TS-219 Turbo NAS devices.
 
+config MACH_OPENRD_BASE
+        bool "Marvell OpenRD Base Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell OpenRD Base Board.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 9dd680e964d6..80ab0ec90ee1 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -6,5 +6,6 @@ obj-$(CONFIG_MACH_RD88F6281)		+= rd88f6281-setup.o
 obj-$(CONFIG_MACH_MV88F6281GTW_GE)      += mv88f6281gtw_ge-setup.o
 obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
 obj-$(CONFIG_MACH_TS219)                += ts219-setup.o
+obj-$(CONFIG_MACH_OPENRD_BASE)          += openrd_base-setup.o
 
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 0f6919838011..0acb61f3c10b 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -838,7 +838,8 @@ int __init kirkwood_find_tclk(void)
         u32 dev, rev;
 
         kirkwood_pcie_id(&dev, &rev);
-        if (dev == MV88F6281_DEV_ID && rev == MV88F6281_REV_A0)
+        if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
+                                        rev == MV88F6281_REV_A1))
                 return 200000000;
 
         return 166666667;
@@ -872,6 +873,8 @@ static char * __init kirkwood_id(void)
                         return "MV88F6281-Z0";
                 else if (rev == MV88F6281_REV_A0)
                         return "MV88F6281-A0";
+                else if (rev == MV88F6281_REV_A1)
+                        return "MV88F6281-A1";
                 else
                         return "MV88F6281-Rev-Unsupported";
         } else if (dev == MV88F6192_DEV_ID) {
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 07af858814a0..54c132731d2d 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -101,6 +101,7 @@
 #define MV88F6281_DEV_ID        0x6281
 #define MV88F6281_REV_Z0        0
 #define MV88F6281_REV_A0        2
+#define MV88F6281_REV_A1        3
 
 #define MV88F6192_DEV_ID        0x6192
 #define MV88F6192_REV_Z0        0
diff --git a/arch/arm/mach-kirkwood/openrd_base-setup.c b/arch/arm/mach-kirkwood/openrd_base-setup.c
new file mode 100644
index 000000000000..947dfb8cd5b2
--- /dev/null
+++ b/arch/arm/mach-kirkwood/openrd_base-setup.c
@@ -0,0 +1,84 @@
+/*
+ * arch/arm/mach-kirkwood/openrd_base-setup.c
+ *
+ * Marvell OpenRD Base Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mtd_partition openrd_base_nand_parts[] = {
+        {
+                .name = "u-boot",
+                .offset = 0,
+                .size = SZ_1M
+        }, {
+                .name = "uImage",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = SZ_4M
+        }, {
+                .name = "root",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = MTDPART_SIZ_FULL
+        },
+};
+
+static struct mv643xx_eth_platform_data openrd_base_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+static struct mv_sata_platform_data openrd_base_sata_data = {
+        .n_ports        = 2,
+};
+
+static struct mvsdio_platform_data openrd_base_mvsdio_data = {
+        .gpio_card_detect = 29, /* MPP29 used as SD card detect */
+};
+
+static unsigned int openrd_base_mpp_config[] __initdata = {
+        MPP29_GPIO,
+        0
+};
+
+static void __init openrd_base_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(openrd_base_mpp_config);
+
+        kirkwood_uart0_init();
+        kirkwood_nand_init(ARRAY_AND_SIZE(openrd_base_nand_parts), 25);
+
+        kirkwood_ehci_init();
+
+        kirkwood_ge00_init(&openrd_base_ge00_data);
+        kirkwood_sata_init(&openrd_base_sata_data);
+        kirkwood_sdio_init(&openrd_base_mvsdio_data);
+}
+
+MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
+        /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = openrd_base_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
index 0d0f306851d0..d1b588519ad2 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-mx1/clock.c
@@ -18,11 +18,14 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/list.h>
 #include <linux/math64.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 
+#include <asm/clkdev.h>
+
 #include <mach/clock.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
@@ -94,7 +97,6 @@ static unsigned long clk16m_get_rate(struct clk *clk)
 }
 
 static struct clk clk16m = {
-        .name = "CLK16M",
         .get_rate = clk16m_get_rate,
         .enable = _clk_enable,
         .enable_reg = CCM_CSCR,
@@ -111,7 +113,6 @@ static unsigned long clk32_get_rate(struct clk *clk)
 }
 
 static struct clk clk32 = {
-        .name = "CLK32",
         .get_rate = clk32_get_rate,
 };
 
@@ -121,7 +122,6 @@ static unsigned long clk32_premult_get_rate(struct clk *clk)
 }
 
 static struct clk clk32_premult = {
-        .name = "CLK32_premultiplier",
         .parent = &clk32,
         .get_rate = clk32_premult_get_rate,
 };
@@ -156,7 +156,6 @@ static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
 }
 
 static struct clk prem_clk = {
-        .name = "prem_clk",
         .set_parent = prem_clk_set_parent,
 };
 
@@ -167,7 +166,6 @@ static unsigned long system_clk_get_rate(struct clk *clk)
 }
 
 static struct clk system_clk = {
-        .name = "system_clk",
         .parent = &prem_clk,
         .get_rate = system_clk_get_rate,
 };
@@ -179,7 +177,6 @@ static unsigned long mcu_clk_get_rate(struct clk *clk)
 }
 
 static struct clk mcu_clk = {
-        .name = "mcu_clk",
         .parent = &clk32_premult,
         .get_rate = mcu_clk_get_rate,
 };
@@ -195,7 +192,6 @@ static unsigned long fclk_get_rate(struct clk *clk)
 }
 
 static struct clk fclk = {
-        .name = "fclk",
         .parent = &mcu_clk,
         .get_rate = fclk_get_rate,
 };
@@ -238,7 +234,6 @@ static int hclk_set_rate(struct clk *clk, unsigned long rate)
 }
 
 static struct clk hclk = {
-        .name = "hclk",
         .parent = &system_clk,
         .get_rate = hclk_get_rate,
         .round_rate = hclk_round_rate,
@@ -280,7 +275,6 @@ static int clk48m_set_rate(struct clk *clk, unsigned long rate)
 }
 
 static struct clk clk48m = {
-        .name = "CLK48M",
         .parent = &system_clk,
         .get_rate = clk48m_get_rate,
         .round_rate = clk48m_round_rate,
@@ -400,21 +394,18 @@ static int perclk3_set_rate(struct clk *clk, unsigned long rate)
 
 static struct clk perclk[] = {
         {
-                .name = "perclk",
                 .id = 0,
                 .parent = &system_clk,
                 .get_rate = perclk1_get_rate,
                 .round_rate = perclk1_round_rate,
                 .set_rate = perclk1_set_rate,
         }, {
-                .name = "perclk",
                 .id = 1,
                 .parent = &system_clk,
                 .get_rate = perclk2_get_rate,
                 .round_rate = perclk2_round_rate,
                 .set_rate = perclk2_set_rate,
         }, {
-                .name = "perclk",
                 .id = 2,
                 .parent = &system_clk,
                 .get_rate = perclk3_get_rate,
@@ -457,12 +448,10 @@ static int clko_set_parent(struct clk *clk, struct clk *parent)
 }
 
 static struct clk clko_clk = {
-        .name = "clko_clk",
         .set_parent = clko_set_parent,
 };
 
 static struct clk dma_clk = {
-        .name = "dma",
         .parent = &hclk,
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
@@ -473,7 +462,6 @@ static struct clk dma_clk = {
 };
 
 static struct clk csi_clk = {
-        .name = "csi_clk",
         .parent = &hclk,
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
@@ -484,7 +472,6 @@ static struct clk csi_clk = {
 };
 
 static struct clk mma_clk = {
-        .name = "mma_clk",
         .parent = &hclk,
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
@@ -495,7 +482,6 @@ static struct clk mma_clk = {
 };
 
 static struct clk usbd_clk = {
-        .name = "usbd_clk",
         .parent = &clk48m,
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
@@ -506,99 +492,85 @@ static struct clk usbd_clk = {
 };
 
 static struct clk gpt_clk = {
-        .name = "gpt_clk",
         .parent = &perclk[0],
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk uart_clk = {
-        .name = "uart",
         .parent = &perclk[0],
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk i2c_clk = {
-        .name = "i2c_clk",
         .parent = &hclk,
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk spi_clk = {
-        .name = "spi_clk",
         .parent = &perclk[1],
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk sdhc_clk = {
-        .name = "sdhc_clk",
         .parent = &perclk[1],
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk lcdc_clk = {
-        .name = "lcdc_clk",
         .parent = &perclk[1],
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk mshc_clk = {
-        .name = "mshc_clk",
         .parent = &hclk,
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk ssi_clk = {
-        .name = "ssi_clk",
         .parent = &perclk[2],
         .round_rate = _clk_parent_round_rate,
         .set_rate = _clk_parent_set_rate,
 };
 
 static struct clk rtc_clk = {
-        .name = "rtc_clk",
         .parent = &clk32,
 };
 
-static struct clk *mxc_clks[] = {
-        &clk16m,
-        &clk32,
-        &clk32_premult,
-        &prem_clk,
-        &system_clk,
-        &mcu_clk,
-        &fclk,
-        &hclk,
-        &clk48m,
-        &perclk[0],
-        &perclk[1],
-        &perclk[2],
-        &clko_clk,
-        &dma_clk,
-        &csi_clk,
-        &mma_clk,
-        &usbd_clk,
-        &gpt_clk,
-        &uart_clk,
-        &i2c_clk,
-        &spi_clk,
-        &sdhc_clk,
-        &lcdc_clk,
-        &mshc_clk,
-        &ssi_clk,
-        &rtc_clk,
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+static struct clk_lookup lookups[] __initdata = {
+        _REGISTER_CLOCK(NULL, "dma", dma_clk)
+        _REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
+        _REGISTER_CLOCK(NULL, "mma", mma_clk)
+        _REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
+        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk)
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
+        _REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
+        _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
+        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+        _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
+        _REGISTER_CLOCK(NULL, "ssi", ssi_clk)
+        _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
 };
 
 int __init mx1_clocks_init(unsigned long fref)
 {
-        struct clk **clkp;
         unsigned int reg;
+        int i;
 
         /* disable clocks we are able to */
         __raw_writel(0, SCM_GCCR);
@@ -620,13 +592,13 @@ int __init mx1_clocks_init(unsigned long fref)
         reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
         clko_clk.parent = (struct clk *)clko_clocks[reg];
 
-        for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
-                clk_register(*clkp);
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
 
         clk_enable(&hclk);
         clk_enable(&fclk);
 
-        mxc_timer_init(&gpt_clk);
+        mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT);
 
         return 0;
 }
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
index 76d1ffb48079..b6be29d1cb08 100644
--- a/arch/arm/mach-mx1/devices.c
+++ b/arch/arm/mach-mx1/devices.c
@@ -29,12 +29,11 @@
 #include "devices.h"
 
 static struct resource imx_csi_resources[] = {
-        [0] = {
+        {
                 .start  = 0x00224000,
                 .end    = 0x00224010,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = CSI_INT,
                 .end    = CSI_INT,
                 .flags  = IORESOURCE_IRQ,
@@ -55,12 +54,11 @@ struct platform_device imx_csi_device = {
 };
 
 static struct resource imx_i2c_resources[] = {
-        [0] = {
+        {
                 .start  = 0x00217000,
                 .end    = 0x00217010,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = I2C_INT,
                 .end    = I2C_INT,
                 .flags  = IORESOURCE_IRQ,
@@ -75,22 +73,19 @@ struct platform_device imx_i2c_device = {
 };
 
 static struct resource imx_uart1_resources[] = {
-        [0] = {
+        {
                 .start  = UART1_BASE_ADDR,
                 .end    = UART1_BASE_ADDR + 0xD0,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = UART1_MINT_RX,
                 .end    = UART1_MINT_RX,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
+        }, {
                 .start  = UART1_MINT_TX,
                 .end    = UART1_MINT_TX,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
+        }, {
                 .start  = UART1_MINT_RTS,
                 .end    = UART1_MINT_RTS,
                 .flags  = IORESOURCE_IRQ,
@@ -105,22 +100,19 @@ struct platform_device imx_uart1_device = {
 };
 
 static struct resource imx_uart2_resources[] = {
-        [0] = {
+        {
                 .start  = UART2_BASE_ADDR,
                 .end    = UART2_BASE_ADDR + 0xD0,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = UART2_MINT_RX,
                 .end    = UART2_MINT_RX,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
+        }, {
                 .start  = UART2_MINT_TX,
                 .end    = UART2_MINT_TX,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
+        }, {
                 .start  = UART2_MINT_RTS,
                 .end    = UART2_MINT_RTS,
                 .flags  = IORESOURCE_IRQ,
@@ -135,17 +127,15 @@ struct platform_device imx_uart2_device = {
 };
 
 static struct resource imx_rtc_resources[] = {
-        [0] = {
+        {
                 .start  = 0x00204000,
                 .end    = 0x00204024,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = RTC_INT,
                 .end    = RTC_INT,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
+        }, {
                 .start  = RTC_SAMINT,
                 .end    = RTC_SAMINT,
                 .flags  = IORESOURCE_IRQ,
@@ -160,12 +150,11 @@ struct platform_device imx_rtc_device = {
 };
 
 static struct resource imx_wdt_resources[] = {
-        [0] = {
+        {
                 .start  = 0x00201000,
                 .end    = 0x00201008,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = WDT_INT,
                 .end    = WDT_INT,
                 .flags  = IORESOURCE_IRQ,
@@ -180,42 +169,35 @@ struct platform_device imx_wdt_device = {
 };
 
 static struct resource imx_usb_resources[] = {
-        [0] = {
+        {
                 .start  = 0x00212000,
                 .end    = 0x00212148,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = USBD_INT0,
                 .end    = USBD_INT0,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
+        }, {
                 .start  = USBD_INT1,
                 .end    = USBD_INT1,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
+        }, {
                 .start  = USBD_INT2,
                 .end    = USBD_INT2,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [4] = {
+        }, {
                 .start  = USBD_INT3,
                 .end    = USBD_INT3,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [5] = {
+        }, {
                 .start  = USBD_INT4,
                 .end    = USBD_INT4,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [6] = {
+        }, {
                 .start  = USBD_INT5,
                 .end    = USBD_INT5,
                 .flags  = IORESOURCE_IRQ,
-        },
-        [7] = {
+        }, {
                 .start  = USBD_INT6,
                 .end    = USBD_INT6,
                 .flags  = IORESOURCE_IRQ,
@@ -231,29 +213,26 @@ struct platform_device imx_usb_device = {
 
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
-        [0] = {
+        {
                 .chip.label = "gpio-0",
                 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
                 .irq = GPIO_INT_PORTA,
-                .virtual_irq_start = MXC_GPIO_IRQ_START
-        },
-        [1] = {
+                .virtual_irq_start = MXC_GPIO_IRQ_START,
+        }, {
                 .chip.label = "gpio-1",
                 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
                 .irq = GPIO_INT_PORTB,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32
-        },
-        [2] = {
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+        }, {
                 .chip.label = "gpio-2",
                 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
                 .irq = GPIO_INT_PORTC,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 64
-        },
-        [3] = {
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+        }, {
                 .chip.label = "gpio-3",
                 .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
                 .irq = GPIO_INT_PORTD,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 96
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
         }
 };
 
diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-mx1/generic.c
index 7622c9b38c97..7f9fc1034c08 100644
--- a/arch/arm/mach-mx1/generic.c
+++ b/arch/arm/mach-mx1/generic.c
@@ -41,6 +41,13 @@ static struct map_desc imx_io_desc[] __initdata = {
 void __init mx1_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX1);
+        mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR));
 
         iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
 }
+
+void __init mx1_init_irq(void)
+{
+        mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+}
+
diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mx1ads.c
index e5b0c0a83c3b..30f04e56fafe 100644
--- a/arch/arm/mach-mx1/mx1ads.c
+++ b/arch/arm/mach-mx1/mx1ads.c
@@ -104,12 +104,10 @@ static struct imxi2c_platform_data mx1ads_i2c_data = {
 
 static struct i2c_board_info mx1ads_i2c_devices[] = {
         {
-                I2C_BOARD_INFO("pcf857x", 0x22),
-                .type = "pcf8575",
+                I2C_BOARD_INFO("pcf8575", 0x22),
                 .platform_data = &pcf857x_data[0],
         }, {
-                I2C_BOARD_INFO("pcf857x", 0x24),
-                .type = "pcf8575",
+                I2C_BOARD_INFO("pcf8575", 0x24),
                 .platform_data = &pcf857x_data[1],
         },
 };
@@ -151,7 +149,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
         .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx1_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx1_init_irq,
         .timer          = &mx1ads_timer,
         .init_machine   = mx1ads_init,
 MACHINE_END
@@ -161,7 +159,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
         .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx1_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx1_init_irq,
         .timer          = &mx1ads_timer,
         .init_machine   = mx1ads_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx1/scb9328.c b/arch/arm/mach-mx1/scb9328.c
index 20e0b5bcdffc..325d98df6053 100644
--- a/arch/arm/mach-mx1/scb9328.c
+++ b/arch/arm/mach-mx1/scb9328.c
@@ -68,22 +68,20 @@ static struct dm9000_plat_data dm9000_platdata = {
  * to gain access to address latch registers and the data path.
  */
 static struct resource dm9000x_resources[] = {
-        [0] = {
+        {
                 .name   = "address area",
                 .start  = IMX_CS5_PHYS,
                 .end    = IMX_CS5_PHYS + 1,
-                .flags  = IORESOURCE_MEM        /* address access */
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,       /* address access */
+        }, {
                 .name   = "data area",
                 .start  = IMX_CS5_PHYS + 4,
                 .end    = IMX_CS5_PHYS + 5,
-                .flags  = IORESOURCE_MEM        /* data access */
-        },
-        [2] = {
+                .flags  = IORESOURCE_MEM,       /* data access */
+        }, {
                 .start  = IRQ_GPIOC(3),
                 .end    = IRQ_GPIOC(3),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
 
@@ -154,7 +152,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
         .io_pg_offst    = ((0xe0200000) >> 18) & 0xfffc,
         .boot_params    = 0x08000100,
         .map_io         = mx1_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx1_init_irq,
         .timer          = &scb9328_timer,
         .init_machine   = scb9328_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
index c77da586b71d..c8a2eac4d13c 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-mx2/Kconfig
@@ -53,6 +53,34 @@ config MACH_PCM970_BASEBOARD
 
 endchoice
 
+config MACH_EUKREA_CPUIMX27
+        bool "Eukrea CPUIMX27 module"
+        depends on MACH_MX27
+        help
+          Include support for Eukrea CPUIMX27 platform. This includes
+          specific configurations for the module and its peripherals.
+
+config MACH_EUKREA_CPUIMX27_USESDHC2
+        bool "CPUIMX27 integrates SDHC2 module"
+        depends on MACH_EUKREA_CPUIMX27
+        help
+          This adds support for the internal SDHC2 used on CPUIMX27 used
+          for wifi or eMMC.
+
+choice
+        prompt "Baseboard"
+        depends on MACH_EUKREA_CPUIMX27
+        default MACH_EUKREA_MBIMX27_BASEBOARD
+
+config MACH_EUKREA_MBIMX27_BASEBOARD
+        prompt "Eukrea MBIMX27 development board"
+        bool
+        help
+          This adds board specific devices that can be found on Eukrea's
+          MBIMX27 evaluation board.
+
+endchoice
+
 config MACH_MX27_3DS
         bool "MX27PDK platform"
         depends on MACH_MX27
@@ -67,4 +95,11 @@ config MACH_MX27LITE
           Include support for MX27 LITEKIT platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_PCA100
+        bool "Phytec phyCARD-s (pca100)"
+        depends on MACH_MX27
+        help
+          Include support for phyCARD-s (aka pca100) platform. This
+          includes specific configurations for the module and its peripherals.
+
 endif
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index b9b1cca4e9bc..19560f045632 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -17,4 +17,7 @@ obj-$(CONFIG_MACH_PCM038) += pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
 obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o
 obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o
+obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
+obj-$(CONFIG_MACH_PCA100) += pca100.o
 
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
index 0850fb88ec15..eede79855f4a 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -1004,6 +1004,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
         clk_enable(&uart_clk[0]);
 #endif
 
-        mxc_timer_init(&gpt_clk[0]);
+        mxc_timer_init(&gpt_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);
         return 0;
 }
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index 2c971442f3f2..4089951acb47 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -643,7 +643,14 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "cspi3", cspi3_clk)
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
         _REGISTER_CLOCK(NULL, "csi", csi_clk)
-        _REGISTER_CLOCK(NULL, "usb", usb_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
         _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk)
         _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk)
         _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
@@ -748,7 +755,7 @@ int __init mx27_clocks_init(unsigned long fref)
         clk_enable(&uart1_clk);
 #endif
 
-        mxc_timer_init(&gpt1_clk);
+        mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);
 
         return 0;
 }
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index a0f1b3674327..50199aff0143 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -40,45 +40,87 @@
 #include "devices.h"
 
 /*
- * Resource definition for the MXC IrDA
+ * SPI master controller
+ *
+ * - i.MX1: 2 channel (slighly different register setting)
+ * - i.MX21: 2 channel
+ * - i.MX27: 3 channel
  */
-static struct resource mxc_irda_resources[] = {
-        [0] = {
-                .start   = UART3_BASE_ADDR,
-                .end     = UART3_BASE_ADDR + SZ_4K - 1,
-                .flags   = IORESOURCE_MEM,
+static struct resource mxc_spi_resources0[] = {
+        {
+               .start = CSPI1_BASE_ADDR,
+               .end = CSPI1_BASE_ADDR + SZ_4K - 1,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = MXC_INT_CSPI1,
+               .end = MXC_INT_CSPI1,
+               .flags = IORESOURCE_IRQ,
         },
-        [1] = {
-                .start   = MXC_INT_UART3,
-                .end     = MXC_INT_UART3,
-                .flags   = IORESOURCE_IRQ,
+};
+
+static struct resource mxc_spi_resources1[] = {
+        {
+                .start = CSPI2_BASE_ADDR,
+                .end = CSPI2_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_CSPI2,
+                .end = MXC_INT_CSPI2,
+                .flags = IORESOURCE_IRQ,
         },
 };
 
-/* Platform Data for MXC IrDA */
-struct platform_device mxc_irda_device = {
-        .name = "mxc_irda",
+#ifdef CONFIG_MACH_MX27
+static struct resource mxc_spi_resources2[] = {
+        {
+                .start = CSPI3_BASE_ADDR,
+                .end = CSPI3_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_CSPI3,
+                .end = MXC_INT_CSPI3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+#endif
+
+struct platform_device mxc_spi_device0 = {
+        .name = "spi_imx",
         .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_irda_resources),
-        .resource = mxc_irda_resources,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources0),
+        .resource = mxc_spi_resources0,
+};
+
+struct platform_device mxc_spi_device1 = {
+        .name = "spi_imx",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources1),
+        .resource = mxc_spi_resources1,
+};
+
+#ifdef CONFIG_MACH_MX27
+struct platform_device mxc_spi_device2 = {
+        .name = "spi_imx",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources2),
+        .resource = mxc_spi_resources2,
 };
+#endif
 
 /*
  * General Purpose Timer
- * - i.MX1: 2 timer (slighly different register handling)
- * - i.MX21: 3 timer
- * - i.MX27: 6 timer
+ * - i.MX21: 3 timers
+ * - i.MX27: 6 timers
  */
 
 /* We use gpt0 as system timer, so do not add a device for this one */
 
 static struct resource timer1_resources[] = {
-        [0] = {
+        {
                 .start  = GPT2_BASE_ADDR,
                 .end    = GPT2_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start   = MXC_INT_GPT2,
                 .end     = MXC_INT_GPT2,
                 .flags   = IORESOURCE_IRQ,
@@ -89,16 +131,15 @@ struct platform_device mxc_gpt1 = {
         .name = "imx_gpt",
         .id = 1,
         .num_resources = ARRAY_SIZE(timer1_resources),
-        .resource = timer1_resources
+        .resource = timer1_resources,
 };
 
 static struct resource timer2_resources[] = {
-        [0] = {
+        {
                 .start  = GPT3_BASE_ADDR,
                 .end    = GPT3_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start   = MXC_INT_GPT3,
                 .end     = MXC_INT_GPT3,
                 .flags   = IORESOURCE_IRQ,
@@ -109,17 +150,16 @@ struct platform_device mxc_gpt2 = {
         .name = "imx_gpt",
         .id = 2,
         .num_resources = ARRAY_SIZE(timer2_resources),
-        .resource = timer2_resources
+        .resource = timer2_resources,
 };
 
 #ifdef CONFIG_MACH_MX27
 static struct resource timer3_resources[] = {
-        [0] = {
+        {
                 .start  = GPT4_BASE_ADDR,
                 .end    = GPT4_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start   = MXC_INT_GPT4,
                 .end     = MXC_INT_GPT4,
                 .flags   = IORESOURCE_IRQ,
@@ -130,16 +170,15 @@ struct platform_device mxc_gpt3 = {
         .name = "imx_gpt",
         .id = 3,
         .num_resources = ARRAY_SIZE(timer3_resources),
-        .resource = timer3_resources
+        .resource = timer3_resources,
 };
 
 static struct resource timer4_resources[] = {
-        [0] = {
+        {
                 .start  = GPT5_BASE_ADDR,
                 .end    = GPT5_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start   = MXC_INT_GPT5,
                 .end     = MXC_INT_GPT5,
                 .flags   = IORESOURCE_IRQ,
@@ -150,16 +189,15 @@ struct platform_device mxc_gpt4 = {
         .name = "imx_gpt",
         .id = 4,
         .num_resources = ARRAY_SIZE(timer4_resources),
-        .resource = timer4_resources
+        .resource = timer4_resources,
 };
 
 static struct resource timer5_resources[] = {
-        [0] = {
+        {
                 .start  = GPT6_BASE_ADDR,
                 .end    = GPT6_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start   = MXC_INT_GPT6,
                 .end     = MXC_INT_GPT6,
                 .flags   = IORESOURCE_IRQ,
@@ -170,7 +208,7 @@ struct platform_device mxc_gpt5 = {
         .name = "imx_gpt",
         .id = 5,
         .num_resources = ARRAY_SIZE(timer5_resources),
-        .resource = timer5_resources
+        .resource = timer5_resources,
 };
 #endif
 
@@ -214,11 +252,11 @@ static struct resource mxc_nand_resources[] = {
         {
                 .start  = NFC_BASE_ADDR,
                 .end    = NFC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
         }, {
                 .start  = MXC_INT_NANDFC,
                 .end    = MXC_INT_NANDFC,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -240,8 +278,7 @@ static struct resource mxc_fb[] = {
                 .start = LCDC_BASE_ADDR,
                 .end   = LCDC_BASE_ADDR + 0xFFF,
                 .flags = IORESOURCE_MEM,
-        },
-        {
+        }, {
                 .start = MXC_INT_LCDC,
                 .end   = MXC_INT_LCDC,
                 .flags = IORESOURCE_IRQ,
@@ -264,11 +301,11 @@ static struct resource mxc_fec_resources[] = {
         {
                 .start  = FEC_BASE_ADDR,
                 .end    = FEC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
         }, {
                 .start  = MXC_INT_FEC,
                 .end    = MXC_INT_FEC,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -281,15 +318,14 @@ struct platform_device mxc_fec_device = {
 #endif
 
 static struct resource mxc_i2c_1_resources[] = {
-        [0] = {
+        {
                 .start  = I2C_BASE_ADDR,
                 .end    = I2C_BASE_ADDR + 0x0fff,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start  = MXC_INT_I2C,
                 .end    = MXC_INT_I2C,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
         }
 };
 
@@ -297,20 +333,19 @@ struct platform_device mxc_i2c_device0 = {
         .name = "imx-i2c",
         .id = 0,
         .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
-        .resource = mxc_i2c_1_resources
+        .resource = mxc_i2c_1_resources,
 };
 
 #ifdef CONFIG_MACH_MX27
 static struct resource mxc_i2c_2_resources[] = {
-        [0] = {
+        {
                 .start  = I2C2_BASE_ADDR,
                 .end    = I2C2_BASE_ADDR + 0x0fff,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start  = MXC_INT_I2C2,
                 .end    = MXC_INT_I2C2,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
         }
 };
 
@@ -318,17 +353,16 @@ struct platform_device mxc_i2c_device1 = {
         .name = "imx-i2c",
         .id = 1,
         .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
-        .resource = mxc_i2c_2_resources
+        .resource = mxc_i2c_2_resources,
 };
 #endif
 
 static struct resource mxc_pwm_resources[] = {
-        [0] = {
+        {
                 .start  = PWM_BASE_ADDR,
                 .end    = PWM_BASE_ADDR + 0x0fff,
-                .flags  = IORESOURCE_MEM
-        },
-        [1] = {
+                .flags  = IORESOURCE_MEM,
+        }, {
                 .start   = MXC_INT_PWM,
                 .end     = MXC_INT_PWM,
                 .flags   = IORESOURCE_IRQ,
@@ -339,28 +373,26 @@ struct platform_device mxc_pwm_device = {
         .name = "mxc_pwm",
         .id = 0,
         .num_resources = ARRAY_SIZE(mxc_pwm_resources),
-        .resource = mxc_pwm_resources
+        .resource = mxc_pwm_resources,
 };
 
 /*
  * Resource definition for the MXC SDHC
  */
 static struct resource mxc_sdhc1_resources[] = {
-        [0] = {
-                        .start = SDHC1_BASE_ADDR,
-                        .end   = SDHC1_BASE_ADDR + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                        },
-        [1] = {
-                        .start = MXC_INT_SDHC1,
-                        .end   = MXC_INT_SDHC1,
-                        .flags = IORESOURCE_IRQ,
-                        },
-        [2] = {
-                        .start  = DMA_REQ_SDHC1,
-                        .end    = DMA_REQ_SDHC1,
-                        .flags  = IORESOURCE_DMA
-                },
+        {
+                .start = SDHC1_BASE_ADDR,
+                .end   = SDHC1_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_SDHC1,
+                .end   = MXC_INT_SDHC1,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start  = DMA_REQ_SDHC1,
+                .end    = DMA_REQ_SDHC1,
+                .flags  = IORESOURCE_DMA,
+        },
 };
 
 static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
@@ -377,21 +409,19 @@ struct platform_device mxc_sdhc_device0 = {
 };
 
 static struct resource mxc_sdhc2_resources[] = {
-        [0] = {
-                        .start = SDHC2_BASE_ADDR,
-                        .end   = SDHC2_BASE_ADDR + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                        },
-        [1] = {
-                        .start = MXC_INT_SDHC2,
-                        .end   = MXC_INT_SDHC2,
-                        .flags = IORESOURCE_IRQ,
-                        },
-        [2] = {
-                        .start  = DMA_REQ_SDHC2,
-                        .end    = DMA_REQ_SDHC2,
-                        .flags  = IORESOURCE_DMA
-                },
+        {
+                .start = SDHC2_BASE_ADDR,
+                .end   = SDHC2_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_SDHC2,
+                .end   = MXC_INT_SDHC2,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start  = DMA_REQ_SDHC2,
+                .end    = DMA_REQ_SDHC2,
+                .flags  = IORESOURCE_DMA,
+        },
 };
 
 static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
@@ -407,35 +437,123 @@ struct platform_device mxc_sdhc_device1 = {
        .resource       = mxc_sdhc2_resources,
 };
 
+#ifdef CONFIG_MACH_MX27
+static struct resource otg_resources[] = {
+        {
+                .start  = OTG_BASE_ADDR,
+                .end    = OTG_BASE_ADDR + 0x1ff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MXC_INT_USB3,
+                .end    = MXC_INT_USB3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 otg_dmamask = 0xffffffffUL;
+
+/* OTG gadget device */
+struct platform_device mxc_otg_udc_device = {
+        .name           = "fsl-usb2-udc",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &otg_dmamask,
+                .coherent_dma_mask      = 0xffffffffUL,
+        },
+        .resource       = otg_resources,
+        .num_resources  = ARRAY_SIZE(otg_resources),
+};
+
+/* OTG host */
+struct platform_device mxc_otg_host = {
+        .name = "mxc-ehci",
+        .id = 0,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &otg_dmamask,
+        },
+        .resource = otg_resources,
+        .num_resources = ARRAY_SIZE(otg_resources),
+};
+
+/* USB host 1 */
+
+static u64 usbh1_dmamask = 0xffffffffUL;
+
+static struct resource mxc_usbh1_resources[] = {
+        {
+                .start = OTG_BASE_ADDR + 0x200,
+                .end = OTG_BASE_ADDR + 0x3ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_USB1,
+                .end = MXC_INT_USB1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_usbh1 = {
+        .name = "mxc-ehci",
+        .id = 1,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh1_dmamask,
+        },
+        .resource = mxc_usbh1_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
+};
+
+/* USB host 2 */
+static u64 usbh2_dmamask = 0xffffffffUL;
+
+static struct resource mxc_usbh2_resources[] = {
+        {
+                .start = OTG_BASE_ADDR + 0x400,
+                .end = OTG_BASE_ADDR + 0x5ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_USB2,
+                .end = MXC_INT_USB2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_usbh2 = {
+        .name = "mxc-ehci",
+        .id = 2,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh2_dmamask,
+        },
+        .resource = mxc_usbh2_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
+};
+#endif
+
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
-        [0] = {
+        {
                 .chip.label = "gpio-0",
                 .irq = MXC_INT_GPIO,
                 .base = IO_ADDRESS(GPIO_BASE_ADDR),
                 .virtual_irq_start = MXC_GPIO_IRQ_START,
-        },
-        [1] = {
+        }, {
                 .chip.label = "gpio-1",
                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-        },
-        [2] = {
+        }, {
                 .chip.label = "gpio-2",
                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
-        },
-        [3] = {
+        }, {
                 .chip.label = "gpio-3",
                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
-        },
-        [4] = {
+        }, {
                 .chip.label = "gpio-4",
                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
-        },
-        [5] = {
+        }, {
                 .chip.label = "gpio-5",
                 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
index 049005bb6aa9..d315406d6725 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-mx2/devices.h
@@ -4,7 +4,6 @@ extern struct platform_device mxc_gpt3;
 extern struct platform_device mxc_gpt4;
 extern struct platform_device mxc_gpt5;
 extern struct platform_device mxc_wdt;
-extern struct platform_device mxc_irda_device;
 extern struct platform_device mxc_uart_device0;
 extern struct platform_device mxc_uart_device1;
 extern struct platform_device mxc_uart_device2;
@@ -20,3 +19,11 @@ extern struct platform_device mxc_i2c_device0;
 extern struct platform_device mxc_i2c_device1;
 extern struct platform_device mxc_sdhc_device0;
 extern struct platform_device mxc_sdhc_device1;
+extern struct platform_device mxc_otg_udc_device;
+extern struct platform_device mxc_otg_host;
+extern struct platform_device mxc_usbh1;
+extern struct platform_device mxc_usbh2;
+extern struct platform_device mxc_spi_device0;
+extern struct platform_device mxc_spi_device1;
+extern struct platform_device mxc_spi_device2;
+
diff --git a/arch/arm/mach-mx2/eukrea_cpuimx27.c b/arch/arm/mach-mx2/eukrea_cpuimx27.c
new file mode 100644
index 000000000000..7b187606682c
--- /dev/null
+++ b/arch/arm/mach-mx2/eukrea_cpuimx27.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm038.c which is :
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/board-eukrea_cpuimx27.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/i2c.h>
+#include <mach/iomux.h>
+#include <mach/imx-uart.h>
+#include <mach/mxc_nand.h>
+
+#include "devices.h"
+
+static int eukrea_cpuimx27_pins[] = {
+        /* UART1 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* UART4 */
+        PB26_AF_UART4_RTS,
+        PB28_AF_UART4_TXD,
+        PB29_AF_UART4_CTS,
+        PB31_AF_UART4_RXD,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+        /* I2C1 */
+        PD17_PF_I2C_DATA,
+        PD18_PF_I2C_CLK,
+        /* SDHC2 */
+        PB4_PF_SD2_D0,
+        PB5_PF_SD2_D1,
+        PB6_PF_SD2_D2,
+        PB7_PF_SD2_D3,
+        PB8_PF_SD2_CMD,
+        PB9_PF_SD2_CLK,
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+        /* Quad UART's IRQ */
+        GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN,
+#endif
+};
+
+static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
+        .width = 2,
+};
+
+static struct resource eukrea_cpuimx27_flash_resource = {
+        .start = 0xc0000000,
+        .end   = 0xc3ffffff,
+        .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &eukrea_cpuimx27_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &eukrea_cpuimx27_flash_resource,
+};
+
+static struct imxuart_platform_data uart_pdata[] = {
+        {
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+};
+
+static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+        &eukrea_cpuimx27_nor_mtd_device,
+        &mxc_fec_device,
+};
+
+static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = {
+        .bitrate = 100000,
+};
+
+static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        },
+};
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+static struct plat_serial8250_port serial_platform_data[] = {
+        {
+                .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x200000),
+                .irq = IRQ_GPIOB(23),
+                .uartclk = 14745600,
+                .regshift = 1,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x400000),
+                .irq = IRQ_GPIOB(22),
+                .uartclk = 14745600,
+                .regshift = 1,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x800000),
+                .irq = IRQ_GPIOB(27),
+                .uartclk = 14745600,
+                .regshift = 1,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x1000000),
+                .irq = IRQ_GPIOB(30),
+                .uartclk = 14745600,
+                .regshift = 1,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+        }
+};
+
+static struct platform_device serial_device = {
+        .name = "serial8250",
+        .id = 0,
+        .dev = {
+                .platform_data = serial_platform_data,
+        },
+};
+#endif
+
+static void __init eukrea_cpuimx27_init(void)
+{
+        mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
+                ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
+
+        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+
+        mxc_register_device(&mxc_nand_device, &eukrea_cpuimx27_nand_board_info);
+
+        i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
+                                ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
+
+        mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data);
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
+        /* SDHC2 can be used for Wifi */
+        mxc_register_device(&mxc_sdhc_device1, NULL);
+        /* in which case UART4 is also used for Bluetooth */
+        mxc_register_device(&mxc_uart_device3, &uart_pdata[1]);
+#endif
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+        platform_device_register(&serial_device);
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
+        eukrea_mbimx27_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx27_timer_init(void)
+{
+        mx27_clocks_init(26000000);
+}
+
+static struct sys_timer eukrea_cpuimx27_timer = {
+        .init = eukrea_cpuimx27_timer_init,
+};
+
+MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx27_map_io,
+        .init_irq       = mx27_init_irq,
+        .init_machine   = eukrea_cpuimx27_init,
+        .timer          = &eukrea_cpuimx27_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
new file mode 100644
index 000000000000..7382b6d27ee1
--- /dev/null
+++ b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
+
+#include <asm/mach/arch.h>
+
+#include <mach/common.h>
+#include <mach/iomux.h>
+#include <mach/imxfb.h>
+#include <mach/hardware.h>
+#include <mach/mmc.h>
+#include <mach/imx-uart.h>
+
+#include "devices.h"
+
+static int eukrea_mbimx27_pins[] = {
+        /* UART2 */
+        PE3_PF_UART2_CTS,
+        PE4_PF_UART2_RTS,
+        PE6_PF_UART2_TXD,
+        PE7_PF_UART2_RXD,
+        /* UART3 */
+        PE8_PF_UART3_TXD,
+        PE9_PF_UART3_RXD,
+        PE10_PF_UART3_CTS,
+        PE11_PF_UART3_RTS,
+        /* UART4 */
+        PB26_AF_UART4_RTS,
+        PB28_AF_UART4_TXD,
+        PB29_AF_UART4_CTS,
+        PB31_AF_UART4_RXD,
+        /* SDHC1*/
+        PE18_PF_SD1_D0,
+        PE19_PF_SD1_D1,
+        PE20_PF_SD1_D2,
+        PE21_PF_SD1_D3,
+        PE22_PF_SD1_CMD,
+        PE23_PF_SD1_CLK,
+        /* display */
+        PA5_PF_LSCLK,
+        PA6_PF_LD0,
+        PA7_PF_LD1,
+        PA8_PF_LD2,
+        PA9_PF_LD3,
+        PA10_PF_LD4,
+        PA11_PF_LD5,
+        PA12_PF_LD6,
+        PA13_PF_LD7,
+        PA14_PF_LD8,
+        PA15_PF_LD9,
+        PA16_PF_LD10,
+        PA17_PF_LD11,
+        PA18_PF_LD12,
+        PA19_PF_LD13,
+        PA20_PF_LD14,
+        PA21_PF_LD15,
+        PA22_PF_LD16,
+        PA23_PF_LD17,
+        PA28_PF_HSYNC,
+        PA29_PF_VSYNC,
+        PA30_PF_CONTRAST,
+        PA31_PF_OE_ACD,
+        /* SPI1 */
+        PD28_PF_CSPI1_SS0,
+        PD29_PF_CSPI1_SCLK,
+        PD30_PF_CSPI1_MISO,
+        PD31_PF_CSPI1_MOSI,
+};
+
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "led1",
+                .default_trigger        = "heartbeat",
+                .active_low             = 1,
+                .gpio                   = GPIO_PORTF | 16,
+        },
+        {
+                .name                   = "led2",
+                .default_trigger        = "none",
+                .active_low             = 1,
+                .gpio                   = GPIO_PORTF | 19,
+        },
+        {
+                .name                   = "backlight",
+                .default_trigger        = "backlight",
+                .active_low             = 0,
+                .gpio                   = GPIO_PORTE | 5,
+        },
+};
+
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+
+static struct platform_device leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_led_info,
+        },
+};
+
+static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
+        {
+                .mode = {
+                        .name           = "CMO-QGVA",
+                        .refresh        = 60,
+                        .xres           = 320,
+                        .yres           = 240,
+                        .pixclock       = 156000,
+                        .hsync_len      = 30,
+                        .left_margin    = 38,
+                        .right_margin   = 20,
+                        .vsync_len      = 3,
+                        .upper_margin   = 15,
+                        .lower_margin   = 4,
+                },
+                .pcr            = 0xFAD08B80,
+                .bpp            = 16,
+        },
+};
+
+static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
+        .mode = eukrea_mbimx27_modes,
+        .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
+
+        .pwmr           = 0x00A903FF,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00040060,
+};
+
+static struct imxuart_platform_data uart_pdata[] = {
+        {
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+        {
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+};
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+        || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+
+#define ADS7846_PENDOWN (GPIO_PORTD | 25)
+
+static void ads7846_dev_init(void)
+{
+        if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
+                printk(KERN_ERR "can't get ads746 pen down GPIO\n");
+                return;
+        }
+
+        gpio_direction_input(ADS7846_PENDOWN);
+}
+
+static int ads7846_get_pendown_state(void)
+{
+        return !gpio_get_value(ADS7846_PENDOWN);
+}
+
+static struct ads7846_platform_data ads7846_config __initdata = {
+        .get_pendown_state      = ads7846_get_pendown_state,
+        .keep_vref_on           = 1,
+};
+
+static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
+        [0] = {
+                .modalias       = "ads7846",
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .max_speed_hz   = 1500000,
+                .irq            = IRQ_GPIOD(25),
+                .platform_data  = &ads7846_config,
+                .mode           = SPI_MODE_2,
+        },
+};
+
+static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
+
+static struct spi_imx_master eukrea_mbimx27_spi_0_data = {
+        .chipselect     = eukrea_mbimx27_spi_cs,
+        .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
+};
+#endif
+
+static struct platform_device *platform_devices[] __initdata = {
+        &leds_gpio,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx27 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimx27_baseboard_init(void)
+{
+        mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
+                ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
+
+        mxc_register_device(&mxc_uart_device1, &uart_pdata[0]);
+        mxc_register_device(&mxc_uart_device2, &uart_pdata[1]);
+
+        mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
+        mxc_register_device(&mxc_sdhc_device0, NULL);
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+        || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+        /* SPI and ADS7846 Touchscreen controler init */
+        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+        mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
+        mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data);
+        spi_register_board_info(eukrea_mbimx27_spi_board_info,
+                        ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
+        ads7846_dev_init();
+#endif
+
+        /* Leds configuration */
+        mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
+        mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
+        /* Backlight */
+        mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c
index 169372f69d8f..ae8f759134d1 100644
--- a/arch/arm/mach-mx2/generic.c
+++ b/arch/arm/mach-mx2/generic.c
@@ -72,6 +72,7 @@ static struct map_desc mxc_io_desc[] __initdata = {
 void __init mx21_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX21);
+        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
 
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
@@ -79,7 +80,18 @@ void __init mx21_map_io(void)
 void __init mx27_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX27);
+        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
 
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+void __init mx27_init_irq(void)
+{
+        mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+}
+
+void __init mx21_init_irq(void)
+{
+        mx27_init_irq();
+}
+
diff --git a/arch/arm/mach-mx2/mx21ads.c b/arch/arm/mach-mx2/mx21ads.c
index a5ee461cb405..cf5f77cbc2f1 100644
--- a/arch/arm/mach-mx2/mx21ads.c
+++ b/arch/arm/mach-mx2/mx21ads.c
@@ -164,25 +164,33 @@ static void mx21ads_fb_exit(struct platform_device *pdev)
  * Connected is a portrait Sharp-QVGA display
  * of type: LQ035Q7DB02
  */
-static struct imx_fb_platform_data mx21ads_fb_data = {
-        .pixclock       = 188679, /* in ps */
-        .xres           = 240,
-        .yres           = 320,
-
-        .bpp            = 16,
-        .hsync_len      = 2,
-        .left_margin    = 6,
-        .right_margin   = 16,
+static struct imx_fb_videomode mx21ads_modes[] = {
+        {
+                .mode = {
+                        .name           = "Sharp-LQ035Q7",
+                        .refresh        = 60,
+                        .xres           = 240,
+                        .yres           = 320,
+                        .pixclock       = 188679, /* in ps (5.3MHz) */
+                        .hsync_len      = 2,
+                        .left_margin    = 6,
+                        .right_margin   = 16,
+                        .vsync_len      = 1,
+                        .upper_margin   = 8,
+                        .lower_margin   = 10,
+                },
+                .pcr            = 0xfb108bc7,
+                .bpp            = 16,
+        },
+};
 
-        .vsync_len      = 1,
-        .upper_margin   = 8,
-        .lower_margin   = 10,
-        .fixed_screen_cpu = 0,
+static struct imx_fb_platform_data mx21ads_fb_data = {
+        .mode = mx21ads_modes,
+        .num_modes = ARRAY_SIZE(mx21ads_modes),
 
-        .pcr            = 0xFB108BC7,
-        .pwmr           = 0x00A901ff,
-        .lscr1          = 0x00120300,
-        .dmacr          = 0x00020008,
+        .pwmr           = 0x00a903ff,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00020008,
 
         .init = mx21ads_fb_init,
         .exit = mx21ads_fb_exit,
@@ -280,7 +288,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
         .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx21ads_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx21_init_irq,
         .init_machine   = mx21ads_board_init,
         .timer          = &mx21ads_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
index 02daddac6995..83e412b713e6 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -183,20 +183,29 @@ void lcd_power(int on)
                 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
 }
 
-static struct imx_fb_platform_data mx27ads_fb_data = {
-        .pixclock       = 188679,
-        .xres           = 240,
-        .yres           = 320,
-
-        .bpp            = 16,
-        .hsync_len      = 1,
-        .left_margin    = 9,
-        .right_margin   = 16,
+static struct imx_fb_videomode mx27ads_modes[] = {
+        {
+                .mode = {
+                        .name           = "Sharp-LQ035Q7",
+                        .refresh        = 60,
+                        .xres           = 240,
+                        .yres           = 320,
+                        .pixclock       = 188679, /* in ps (5.3MHz) */
+                        .hsync_len      = 1,
+                        .left_margin    = 9,
+                        .right_margin   = 16,
+                        .vsync_len      = 1,
+                        .upper_margin   = 7,
+                        .lower_margin   = 9,
+                },
+                .bpp            = 16,
+                .pcr            = 0xFB008BC0,
+        },
+};
 
-        .vsync_len      = 1,
-        .upper_margin   = 7,
-        .lower_margin   = 9,
-        .fixed_screen_cpu = 0,
+static struct imx_fb_platform_data mx27ads_fb_data = {
+        .mode = mx27ads_modes,
+        .num_modes = ARRAY_SIZE(mx27ads_modes),
 
         /*
          * - HSYNC active high
@@ -207,7 +216,6 @@ static struct imx_fb_platform_data mx27ads_fb_data = {
          * - data enable low active
          * - enable sharp mode
          */
-        .pcr            = 0xFB008BC0,
         .pwmr           = 0x00A903FF,
         .lscr1          = 0x00120300,
         .dmacr          = 0x00020010,
@@ -330,7 +338,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
         .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx27ads_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
         .init_machine   = mx27ads_board_init,
         .timer          = &mx27ads_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27lite.c b/arch/arm/mach-mx2/mx27lite.c
index 3ae11cb8c04b..82ea227ea0cf 100644
--- a/arch/arm/mach-mx2/mx27lite.c
+++ b/arch/arm/mach-mx2/mx27lite.c
@@ -89,7 +89,7 @@ MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
         .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx27_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
         .init_machine   = mx27lite_init,
         .timer          = &mx27lite_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27pdk.c b/arch/arm/mach-mx2/mx27pdk.c
index 1d9238c7a6c3..6761d1b79e43 100644
--- a/arch/arm/mach-mx2/mx27pdk.c
+++ b/arch/arm/mach-mx2/mx27pdk.c
@@ -89,7 +89,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
         .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx27_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
         .init_machine   = mx27pdk_init,
         .timer          = &mx27pdk_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/pca100.c
new file mode 100644
index 000000000000..fe5b165b88cc
--- /dev/null
+++ b/arch/arm/mach-mx2/pca100.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/dma-mapping.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/eeprom.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux.h>
+#include <mach/i2c.h>
+#include <asm/mach/time.h>
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+#include <mach/spi.h>
+#endif
+#include <mach/imx-uart.h>
+#include <mach/mxc_nand.h>
+#include <mach/irqs.h>
+#include <mach/mmc.h>
+
+#include "devices.h"
+
+static int pca100_pins[] = {
+        /* UART1 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* SDHC */
+        PB4_PF_SD2_D0,
+        PB5_PF_SD2_D1,
+        PB6_PF_SD2_D2,
+        PB7_PF_SD2_D3,
+        PB8_PF_SD2_CMD,
+        PB9_PF_SD2_CLK,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+        /* SSI1 */
+        PC20_PF_SSI1_FS,
+        PC21_PF_SSI1_RXD,
+        PC22_PF_SSI1_TXD,
+        PC23_PF_SSI1_CLK,
+        /* onboard I2C */
+        PC5_PF_I2C2_SDA,
+        PC6_PF_I2C2_SCL,
+        /* external I2C */
+        PD17_PF_I2C_DATA,
+        PD18_PF_I2C_CLK,
+        /* SPI1 */
+        PD25_PF_CSPI1_RDY,
+        PD29_PF_CSPI1_SCLK,
+        PD30_PF_CSPI1_MISO,
+        PD31_PF_CSPI1_MOSI,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct mxc_nand_platform_data pca100_nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+        &mxc_w1_master_device,
+        &mxc_fec_device,
+};
+
+static struct imxi2c_platform_data pca100_i2c_1_data = {
+        .bitrate = 100000,
+};
+
+static struct at24_platform_data board_eeprom = {
+        .byte_len = 4096,
+        .page_size = 32,
+        .flags = AT24_FLAG_ADDR16,
+};
+
+static struct i2c_board_info pca100_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
+                .platform_data = &board_eeprom,
+        }, {
+                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
+                .type = "pcf8563"
+        }, {
+                I2C_BOARD_INFO("lm75", 0x4a),
+                .type = "lm75"
+        }
+};
+
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+static struct spi_eeprom at25320 = {
+        .name           = "at25320an",
+        .byte_len       = 4096,
+        .page_size      = 32,
+        .flags          = EE_ADDR2,
+};
+
+static struct spi_board_info pca100_spi_board_info[] __initdata = {
+        {
+                .modalias = "at25",
+                .max_speed_hz = 30000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .platform_data = &at25320,
+        },
+};
+
+static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
+
+static struct spi_imx_master pca100_spi_0_data = {
+        .chipselect     = pca100_spi_cs,
+        .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
+};
+#endif
+
+static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
+                void *data)
+{
+        int ret;
+
+        ret = request_irq(IRQ_GPIOC(29), detect_irq,
+                          IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+                          "imx-mmc-detect", data);
+        if (ret)
+                printk(KERN_ERR
+                        "pca100: Failed to reuest irq for sd/mmc detection\n");
+
+        return ret;
+}
+
+static void pca100_sdhc2_exit(struct device *dev, void *data)
+{
+        free_irq(IRQ_GPIOC(29), data);
+}
+
+static struct imxmmc_platform_data sdhc_pdata = {
+        .init = pca100_sdhc2_init,
+        .exit = pca100_sdhc2_exit,
+};
+
+static void __init pca100_init(void)
+{
+        int ret;
+
+        ret = mxc_gpio_setup_multiple_pins(pca100_pins,
+                        ARRAY_SIZE(pca100_pins), "PCA100");
+        if (ret)
+                printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
+
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+
+        mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
+        mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
+
+        mxc_register_device(&mxc_nand_device, &pca100_nand_board_info);
+
+        /* only the i2c master 1 is used on this CPU card */
+        i2c_register_board_info(1, pca100_i2c_devices,
+                                ARRAY_SIZE(pca100_i2c_devices));
+
+        mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
+
+        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+        mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
+
+        /* GPIO0_IRQ */
+        mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
+        /* GPIO1_IRQ */
+        mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
+        /* GPIO2_IRQ */
+        mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
+
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+        spi_register_board_info(pca100_spi_board_info,
+                                ARRAY_SIZE(pca100_spi_board_info));
+        mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
+#endif
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init pca100_timer_init(void)
+{
+        mx27_clocks_init(26000000);
+}
+
+static struct sys_timer pca100_timer = {
+        .init = pca100_timer_init,
+};
+
+MACHINE_START(PCA100, "phyCARD-i.MX27")
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx27_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = pca100_init,
+        .timer          = &pca100_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
index a4628d004343..ee65dda584cf 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -186,17 +186,13 @@ static struct at24_platform_data board_eeprom = {
 };
 
 static struct i2c_board_info pcm038_i2c_devices[] = {
-        [0] = {
+        {
                 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
                 .platform_data = &board_eeprom,
-        },
-        [1] = {
-                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
-                .type = "pcf8563"
-        },
-        [2] = {
+        }, {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        }, {
                 I2C_BOARD_INFO("lm75", 0x4a),
-                .type = "lm75"
         }
 };
 
@@ -220,6 +216,9 @@ static void __init pcm038_init(void)
 
         mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
 
+        /* PE18 for user-LED D40 */
+        mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
+
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
 #ifdef CONFIG_MACH_PCM970_BASEBOARD
@@ -241,7 +240,7 @@ MACHINE_START(PCM038, "phyCORE-i.MX27")
         .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx27_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
         .init_machine   = pcm038_init,
         .timer          = &pcm038_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
index 6a3acaf57dd4..c261f59b0b4c 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -19,6 +19,7 @@
 #include <linux/gpio.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/can/platform/sja1000.h>
 
 #include <asm/mach/arch.h>
 
@@ -125,40 +126,96 @@ static struct imxmmc_platform_data sdhc_pdata = {
         .exit = pcm970_sdhc2_exit,
 };
 
-/*
- * Connected is a portrait Sharp-QVGA display
- * of type: LQ035Q7DH06
- */
-static struct imx_fb_platform_data pcm038_fb_data = {
-        .pixclock       = 188679, /* in ps (5.3MHz) */
-        .xres           = 240,
-        .yres           = 320,
-
-        .bpp            = 16,
-        .hsync_len      = 7,
-        .left_margin    = 5,
-        .right_margin   = 16,
+static struct imx_fb_videomode pcm970_modes[] = {
+        {
+                .mode = {
+                        .name           = "Sharp-LQ035Q7",
+                        .refresh        = 60,
+                        .xres           = 240,
+                        .yres           = 320,
+                        .pixclock       = 188679, /* in ps (5.3MHz) */
+                        .hsync_len      = 7,
+                        .left_margin    = 5,
+                        .right_margin   = 16,
+                        .vsync_len      = 1,
+                        .upper_margin   = 7,
+                        .lower_margin   = 9,
+                },
+                /*
+                 * - HSYNC active high
+                 * - VSYNC active high
+                 * - clk notenabled while idle
+                 * - clock not inverted
+                 * - data not inverted
+                 * - data enable low active
+                 * - enable sharp mode
+                 */
+                .pcr            = 0xF00080C0,
+                .bpp            = 16,
+        }, {
+                .mode = {
+                        .name           = "TX090",
+                        .refresh        = 60,
+                        .xres           = 240,
+                        .yres           = 320,
+                        .pixclock       = 38255,
+                        .left_margin    = 144,
+                        .right_margin   = 0,
+                        .upper_margin   = 7,
+                        .lower_margin   = 40,
+                        .hsync_len      = 96,
+                        .vsync_len      = 1,
+                },
+                /*
+                 * - HSYNC active low (1 << 22)
+                 * - VSYNC active low (1 << 23)
+                 * - clk notenabled while idle
+                 * - clock not inverted
+                 * - data not inverted
+                 * - data enable low active
+                 * - enable sharp mode
+                 */
+                .pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19),
+                .bpp = 32,
+        },
+};
 
-        .vsync_len      = 1,
-        .upper_margin   = 7,
-        .lower_margin   = 9,
-        .fixed_screen_cpu = 0,
+static struct imx_fb_platform_data pcm038_fb_data = {
+        .mode = pcm970_modes,
+        .num_modes = ARRAY_SIZE(pcm970_modes),
 
-        /*
-         * - HSYNC active high
-         * - VSYNC active high
-         * - clk notenabled while idle
-         * - clock not inverted
-         * - data not inverted
-         * - data enable low active
-         * - enable sharp mode
-         */
-        .pcr            = 0xFA0080C0,
         .pwmr           = 0x00A903FF,
         .lscr1          = 0x00120300,
         .dmacr          = 0x00020010,
 };
 
+static struct resource pcm970_sja1000_resources[] = {
+        {
+                .start   = CS4_BASE_ADDR,
+                .end     = CS4_BASE_ADDR + 0x100 - 1,
+                .flags   = IORESOURCE_MEM,
+        }, {
+                .start   = IRQ_GPIOE(19),
+                .end     = IRQ_GPIOE(19),
+                .flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
+        },
+};
+
+struct sja1000_platform_data pcm970_sja1000_platform_data = {
+        .clock          = 16000000 / 2,
+        .ocr            = 0x40 | 0x18,
+        .cdr            = 0x40,
+};
+
+static struct platform_device pcm970_sja1000 = {
+        .name = "sja1000_platform",
+        .dev = {
+                .platform_data = &pcm970_sja1000_platform_data,
+        },
+        .resource = pcm970_sja1000_resources,
+        .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
+};
+
 /*
  * system init for baseboard usage. Will be called by pcm038 init.
  *
@@ -172,4 +229,5 @@ void __init pcm970_baseboard_init(void)
 
         mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
         mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
+        platform_device_register(&pcm970_sja1000);
 }
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
new file mode 100644
index 000000000000..cc28f56eae80
--- /dev/null
+++ b/arch/arm/mach-mx25/Kconfig
@@ -0,0 +1,9 @@
+if ARCH_MX25
+
+comment "MX25 platforms:"
+
+config MACH_MX25_3DS
+        select ARCH_MXC_IOMUX_V3
+        bool "Support MX25PDK (3DS) Platform"
+
+endif
diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
new file mode 100644
index 000000000000..fe23836a9f3d
--- /dev/null
+++ b/arch/arm/mach-mx25/Makefile
@@ -0,0 +1,3 @@
+obj-y                           := mm.o devices.o
+obj-$(CONFIG_ARCH_MX25)         += clock.o
+obj-$(CONFIG_MACH_MX25_3DS)     += mx25pdk.o
diff --git a/arch/arm/mach-mx25/Makefile.boot b/arch/arm/mach-mx25/Makefile.boot
new file mode 100644
index 000000000000..e1dd366f836b
--- /dev/null
+++ b/arch/arm/mach-mx25/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x80008000
+params_phys-y   := 0x80000100
+initrd_phys-y   := 0x80800000
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
new file mode 100644
index 000000000000..ef26951a5275
--- /dev/null
+++ b/arch/arm/mach-mx25/clock.c
@@ -0,0 +1,219 @@
+/*
+ * Copyright (C) 2009 by Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/mx25.h>
+
+#define CRM_BASE        MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
+
+#define CCM_MPCTL       0x00
+#define CCM_UPCTL       0x04
+#define CCM_CCTL        0x08
+#define CCM_CGCR0       0x0C
+#define CCM_CGCR1       0x10
+#define CCM_CGCR2       0x14
+#define CCM_PCDR0       0x18
+#define CCM_PCDR1       0x1C
+#define CCM_PCDR2       0x20
+#define CCM_PCDR3       0x24
+#define CCM_RCSR        0x28
+#define CCM_CRDR        0x2C
+#define CCM_DCVR0       0x30
+#define CCM_DCVR1       0x34
+#define CCM_DCVR2       0x38
+#define CCM_DCVR3       0x3c
+#define CCM_LTR0        0x40
+#define CCM_LTR1        0x44
+#define CCM_LTR2        0x48
+#define CCM_LTR3        0x4c
+
+static unsigned long get_rate_mpll(void)
+{
+        ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL);
+
+        return mxc_decode_pll(mpctl, 24000000);
+}
+
+static unsigned long get_rate_upll(void)
+{
+        ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL);
+
+        return mxc_decode_pll(mpctl, 24000000);
+}
+
+unsigned long get_rate_arm(struct clk *clk)
+{
+        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
+        unsigned long rate = get_rate_mpll();
+
+        if (cctl & (1 << 14))
+                rate = (rate * 3) >> 1;
+
+        return rate / ((cctl >> 30) + 1);
+}
+
+static unsigned long get_rate_ahb(struct clk *clk)
+{
+        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
+
+        return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1);
+}
+
+static unsigned long get_rate_ipg(struct clk *clk)
+{
+        return get_rate_ahb(NULL) >> 1;
+}
+
+static unsigned long get_rate_per(int per)
+{
+        unsigned long ofs = (per & 0x3) * 8;
+        unsigned long reg = per & ~0x3;
+        unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f;
+        unsigned long fref;
+
+        if (readl(CRM_BASE + 0x64) & (1 << per))
+                fref = get_rate_upll();
+        else
+                fref = get_rate_ipg(NULL);
+
+        return fref / (val + 1);
+}
+
+static unsigned long get_rate_uart(struct clk *clk)
+{
+        return get_rate_per(15);
+}
+
+static unsigned long get_rate_i2c(struct clk *clk)
+{
+        return get_rate_per(6);
+}
+
+static unsigned long get_rate_nfc(struct clk *clk)
+{
+        return get_rate_per(8);
+}
+
+static unsigned long get_rate_otg(struct clk *clk)
+{
+        return 48000000; /* FIXME */
+}
+
+static int clk_cgcr_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void clk_cgcr_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+#define DEFINE_CLOCK(name, i, er, es, gr, sr)           \
+        static struct clk name = {                      \
+                .id             = i,                    \
+                .enable_reg     = CRM_BASE + er,        \
+                .enable_shift   = es,                   \
+                .get_rate       = gr,                   \
+                .set_rate       = sr,                   \
+                .enable         = clk_cgcr_enable,      \
+                .disable        = clk_cgcr_disable,     \
+        }
+
+DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL);
+DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL);
+DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL);
+DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL);
+DEFINE_CLOCK(uart4_clk,  0, CCM_CGCR2, 17, get_rate_uart, NULL);
+DEFINE_CLOCK(uart5_clk,  0, CCM_CGCR2, 18, get_rate_uart, NULL);
+DEFINE_CLOCK(nfc_clk,    0, CCM_CGCR0,  8, get_rate_nfc, NULL);
+DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL);
+DEFINE_CLOCK(pwm1_clk,   0, CCM_CGCR1, 31, get_rate_ipg, NULL);
+DEFINE_CLOCK(pwm2_clk,   0, CCM_CGCR2,  0, get_rate_ipg, NULL);
+DEFINE_CLOCK(pwm3_clk,   0, CCM_CGCR2,  1, get_rate_ipg, NULL);
+DEFINE_CLOCK(pwm4_clk,   0, CCM_CGCR2,  2, get_rate_ipg, NULL);
+DEFINE_CLOCK(kpp_clk,    0, CCM_CGCR1, 28, get_rate_ipg, NULL);
+DEFINE_CLOCK(tsc_clk,    0, CCM_CGCR2, 13, get_rate_ipg, NULL);
+DEFINE_CLOCK(i2c_clk,    0, CCM_CGCR0,  6, get_rate_i2c, NULL);
+
+#define _REGISTER_CLOCK(d, n, c)        \
+        {                               \
+                .dev_id = d,            \
+                .con_id = n,            \
+                .clk = &c,              \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+        _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
+        _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+        _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
+        _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
+        _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
+        _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
+        _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
+        _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
+        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
+        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
+};
+
+int __init mx25_clocks_init(unsigned long fref)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+
+        mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
+
+        return 0;
+}
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
new file mode 100644
index 000000000000..eb12de1da42d
--- /dev/null
+++ b/arch/arm/mach-mx25/devices.c
@@ -0,0 +1,402 @@
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <mach/mx25.h>
+#include <mach/irqs.h>
+
+static struct resource uart0[] = {
+        {
+                .start = 0x43f90000,
+                .end = 0x43f93fff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 45,
+                .end = 45,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device0 = {
+        .name = "imx-uart",
+        .id = 0,
+        .resource = uart0,
+        .num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct resource uart1[] = {
+        {
+                .start = 0x43f94000,
+                .end = 0x43f97fff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 32,
+                .end = 32,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device1 = {
+        .name = "imx-uart",
+        .id = 1,
+        .resource = uart1,
+        .num_resources = ARRAY_SIZE(uart1),
+};
+
+static struct resource uart2[] = {
+        {
+                .start = 0x5000c000,
+                .end = 0x5000ffff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 18,
+                .end = 18,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device2 = {
+        .name = "imx-uart",
+        .id = 2,
+        .resource = uart2,
+        .num_resources = ARRAY_SIZE(uart2),
+};
+
+static struct resource uart3[] = {
+        {
+                .start = 0x50008000,
+                .end = 0x5000bfff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 5,
+                .end = 5,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device3 = {
+        .name = "imx-uart",
+        .id = 3,
+        .resource = uart3,
+        .num_resources = ARRAY_SIZE(uart3),
+};
+
+static struct resource uart4[] = {
+        {
+                .start = 0x5002c000,
+                .end = 0x5002ffff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 40,
+                .end = 40,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device4 = {
+        .name = "imx-uart",
+        .id = 4,
+        .resource = uart4,
+        .num_resources = ARRAY_SIZE(uart4),
+};
+
+#define MX25_OTG_BASE_ADDR 0x53FF4000
+
+static u64 otg_dmamask = DMA_BIT_MASK(32);
+
+static struct resource mxc_otg_resources[] = {
+        {
+                .start = MX25_OTG_BASE_ADDR,
+                .end = MX25_OTG_BASE_ADDR + 0x1ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 37,
+                .end = 37,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_otg = {
+        .name = "mxc-ehci",
+        .id = 0,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &otg_dmamask,
+        },
+        .resource = mxc_otg_resources,
+        .num_resources = ARRAY_SIZE(mxc_otg_resources),
+};
+
+/* OTG gadget device */
+struct platform_device otg_udc_device = {
+        .name = "fsl-usb2-udc",
+        .id   = -1,
+        .dev  = {
+                .dma_mask          = &otg_dmamask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource = mxc_otg_resources,
+        .num_resources = ARRAY_SIZE(mxc_otg_resources),
+};
+
+static u64 usbh2_dmamask = DMA_BIT_MASK(32);
+
+static struct resource mxc_usbh2_resources[] = {
+        {
+                .start = MX25_OTG_BASE_ADDR + 0x400,
+                .end = MX25_OTG_BASE_ADDR + 0x5ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 35,
+                .end = 35,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_usbh2 = {
+        .name = "mxc-ehci",
+        .id = 1,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh2_dmamask,
+        },
+        .resource = mxc_usbh2_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
+};
+
+static struct resource mxc_spi_resources0[] = {
+        {
+               .start = 0x43fa4000,
+               .end = 0x43fa7fff,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = 14,
+               .end = 14,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_spi_device0 = {
+        .name = "spi_imx",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources0),
+        .resource = mxc_spi_resources0,
+};
+
+static struct resource mxc_spi_resources1[] = {
+        {
+               .start = 0x50010000,
+               .end = 0x50013fff,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = 13,
+               .end = 13,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_spi_device1 = {
+        .name = "spi_imx",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources1),
+        .resource = mxc_spi_resources1,
+};
+
+static struct resource mxc_spi_resources2[] = {
+        {
+               .start = 0x50004000,
+               .end = 0x50007fff,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = 0,
+               .end = 0,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_spi_device2 = {
+        .name = "spi_imx",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources2),
+        .resource = mxc_spi_resources2,
+};
+
+static struct resource mxc_pwm_resources0[] = {
+        {
+                .start  = 0x53fe0000,
+                .end    = 0x53fe3fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 26,
+                .end     = 26,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_pwm_device0 = {
+        .name = "mxc_pwm",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_pwm_resources0),
+        .resource = mxc_pwm_resources0,
+};
+
+static struct resource mxc_pwm_resources1[] = {
+        {
+                .start  = 0x53fa0000,
+                .end    = 0x53fa3fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 36,
+                .end     = 36,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_pwm_device1 = {
+        .name = "mxc_pwm",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_pwm_resources1),
+        .resource = mxc_pwm_resources1,
+};
+
+static struct resource mxc_pwm_resources2[] = {
+        {
+                .start  = 0x53fa8000,
+                .end    = 0x53fabfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 41,
+                .end     = 41,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_pwm_device2 = {
+        .name = "mxc_pwm",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_pwm_resources2),
+        .resource = mxc_pwm_resources2,
+};
+
+static struct resource mxc_keypad_resources[] = {
+        {
+                .start  = 0x43fa8000,
+                .end    = 0x43fabfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 24,
+                .end     = 24,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_keypad_device = {
+        .name = "mxc-keypad",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(mxc_keypad_resources),
+        .resource = mxc_keypad_resources,
+};
+
+static struct resource mxc_pwm_resources3[] = {
+        {
+                .start  = 0x53fc8000,
+                .end    = 0x53fcbfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 42,
+                .end     = 42,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_pwm_device3 = {
+        .name = "mxc_pwm",
+        .id = 3,
+        .num_resources = ARRAY_SIZE(mxc_pwm_resources3),
+        .resource = mxc_pwm_resources3,
+};
+
+static struct resource mxc_i2c_1_resources[] = {
+        {
+                .start  = 0x43f80000,
+                .end    = 0x43f83fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 3,
+                .end    = 3,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_i2c_device0 = {
+        .name = "imx-i2c",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
+        .resource = mxc_i2c_1_resources,
+};
+
+static struct resource mxc_i2c_2_resources[] = {
+        {
+                .start  = 0x43f98000,
+                .end    = 0x43f9bfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 4,
+                .end    = 4,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_i2c_device1 = {
+        .name = "imx-i2c",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
+        .resource = mxc_i2c_2_resources,
+};
+
+static struct resource mxc_i2c_3_resources[] = {
+        {
+                .start  = 0x43f84000,
+                .end    = 0x43f87fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 10,
+                .end    = 10,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_i2c_device2 = {
+        .name = "imx-i2c",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_i2c_3_resources),
+        .resource = mxc_i2c_3_resources,
+};
+
+static struct mxc_gpio_port imx_gpio_ports[] = {
+        {
+                .chip.label = "gpio-0",
+                .base = (void __iomem *)MX25_GPIO1_BASE_ADDR_VIRT,
+                .irq = 52,
+                .virtual_irq_start = MXC_GPIO_IRQ_START,
+        }, {
+                .chip.label = "gpio-1",
+                .base = (void __iomem *)MX25_GPIO2_BASE_ADDR_VIRT,
+                .irq = 51,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+        }, {
+                .chip.label = "gpio-2",
+                .base = (void __iomem *)MX25_GPIO3_BASE_ADDR_VIRT,
+                .irq = 16,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+        }, {
+                .chip.label = "gpio-3",
+                .base = (void __iomem *)MX25_GPIO4_BASE_ADDR_VIRT,
+                .irq = 23,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
+        }
+};
+
+int __init mxc_register_gpios(void)
+{
+        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
+}
+
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
new file mode 100644
index 000000000000..fe6bf88ad1dd
--- /dev/null
+++ b/arch/arm/mach-mx25/devices.h
@@ -0,0 +1,19 @@
+extern struct platform_device mxc_uart_device0;
+extern struct platform_device mxc_uart_device1;
+extern struct platform_device mxc_uart_device2;
+extern struct platform_device mxc_uart_device3;
+extern struct platform_device mxc_uart_device4;
+extern struct platform_device mxc_otg;
+extern struct platform_device otg_udc_device;
+extern struct platform_device mxc_usbh2;
+extern struct platform_device mxc_spi_device0;
+extern struct platform_device mxc_spi_device1;
+extern struct platform_device mxc_spi_device2;
+extern struct platform_device mxc_pwm_device0;
+extern struct platform_device mxc_pwm_device1;
+extern struct platform_device mxc_pwm_device2;
+extern struct platform_device mxc_pwm_device3;
+extern struct platform_device mxc_keypad_device;
+extern struct platform_device mxc_i2c_device0;
+extern struct platform_device mxc_i2c_device1;
+extern struct platform_device mxc_i2c_device2;
diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-mx25/mm.c
new file mode 100644
index 000000000000..a7e587ff3e9e
--- /dev/null
+++ b/arch/arm/mach-mx25/mm.c
@@ -0,0 +1,76 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MX31 specific definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/err.h>
+
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/mx25.h>
+#include <mach/iomux-v3.h>
+
+/*
+ * This table defines static virtual address mappings for I/O regions.
+ * These are the mappings common across all MX3 boards.
+ */
+static struct map_desc mxc_io_desc[] __initdata = {
+        {
+                .virtual        = MX25_AVIC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MX25_AVIC_BASE_ADDR),
+                .length         = MX25_AVIC_SIZE,
+                .type           = MT_DEVICE_NONSHARED
+        }, {
+                .virtual        = MX25_AIPS1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MX25_AIPS1_BASE_ADDR),
+                .length         = MX25_AIPS1_SIZE,
+                .type           = MT_DEVICE_NONSHARED
+        }, {
+                .virtual        = MX25_AIPS2_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MX25_AIPS2_BASE_ADDR),
+                .length         = MX25_AIPS2_SIZE,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx25_map_io(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX25);
+        mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
+
+        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
+
+void __init mx25_init_irq(void)
+{
+        mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
+}
+
diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mx25pdk.c
new file mode 100644
index 000000000000..92aa4fd19d99
--- /dev/null
+++ b/arch/arm/mach-mx25/mx25pdk.c
@@ -0,0 +1,58 @@
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/mx25.h>
+#include <mach/mxc_nand.h>
+#include "devices.h"
+#include <mach/iomux-v3.h>
+
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct mxc_nand_platform_data nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
+
+static void __init mx25pdk_init(void)
+{
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_usbh2, NULL);
+        mxc_register_device(&mxc_nand_device, &nand_board_info);
+}
+
+
+static void __init mx25pdk_timer_init(void)
+{
+        mx25_clocks_init(26000000);
+}
+
+static struct sys_timer mx25pdk_timer = {
+        .init   = mx25pdk_timer_init,
+};
+
+MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
+        /* Maintainer: Freescale Semiconductor, Inc. */
+        .phys_io        = MX25_AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx25_map_io,
+        .init_irq       = mx25_init_irq,
+        .init_machine   = mx25pdk_init,
+        .timer          = &mx25pdk_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c
index ee331fd6b1bd..776c0ee1b3cd 100644
--- a/arch/arm/mach-mx3/armadillo5x0.c
+++ b/arch/arm/mach-mx3/armadillo5x0.c
@@ -352,7 +352,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x00000100,
         .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .timer          = &armadillo5x0_timer,
         .init_machine   = armadillo5x0_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 577ee83d1f60..fe5c4217322e 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -273,6 +273,19 @@ static unsigned long get_rate_csi(struct clk *clk)
         return rate / get_3_3_div((pdr2 >> 16) & 0x3f);
 }
 
+static unsigned long get_rate_otg(struct clk *clk)
+{
+        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long rate;
+
+        if (pdr4 & (1 << 9))
+                rate = get_rate_arm();
+        else
+                rate = get_rate_ppll();
+
+        return rate / get_3_3_div((pdr4 >> 22) & 0x3f);
+}
+
 static unsigned long get_rate_ipg_per(struct clk *clk)
 {
         unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
@@ -365,7 +378,7 @@ DEFINE_CLOCK(ssi2_clk,   1, CCM_CGR2, 14, get_rate_ssi, NULL);
 DEFINE_CLOCK(uart1_clk,  0, CCM_CGR2, 16, get_rate_uart, NULL);
 DEFINE_CLOCK(uart2_clk,  1, CCM_CGR2, 18, get_rate_uart, NULL);
 DEFINE_CLOCK(uart3_clk,  2, CCM_CGR2, 20, get_rate_uart, NULL);
-DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, NULL, NULL);
+DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
 DEFINE_CLOCK(wdog_clk,   0, CCM_CGR2, 24, NULL, NULL);
 DEFINE_CLOCK(max_clk,    0, CCM_CGR2, 26, NULL, NULL);
 DEFINE_CLOCK(admux_clk,  0, CCM_CGR2, 30, NULL, NULL);
@@ -426,7 +439,10 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
         _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
-        _REGISTER_CLOCK(NULL, "usbotg", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
         _REGISTER_CLOCK("mxc_wdt.0", NULL, wdog_clk)
         _REGISTER_CLOCK(NULL, "max", max_clk)
         _REGISTER_CLOCK(NULL, "admux", admux_clk)
@@ -456,7 +472,7 @@ int __init mx35_clocks_init()
         __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);
         __raw_writel(0, CCM_BASE + CCM_CGR3);
 
-        mxc_timer_init(&gpt_clk);
+        mxc_timer_init(&gpt_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT);
 
         return 0;
 }
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index 8b14239724c9..06bd6180bfc3 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -29,6 +29,7 @@
 
 #include <mach/clock.h>
 #include <mach/hardware.h>
+#include <mach/mx31.h>
 #include <mach/common.h>
 
 #include "crm_regs.h"
@@ -402,6 +403,11 @@ static unsigned long clk_ckih_get_rate(struct clk *clk)
         return ckih_rate;
 }
 
+static unsigned long clk_ckil_get_rate(struct clk *clk)
+{
+        return CKIL_CLK_FREQ;
+}
+
 static struct clk ckih_clk = {
         .get_rate = clk_ckih_get_rate,
 };
@@ -508,6 +514,7 @@ DEFINE_CLOCK(usb_clk1,    0, NULL,          0, usb_get_rate, NULL, &usb_pll_clk)
 DEFINE_CLOCK(nfc_clk,     0, NULL,          0, nfc_get_rate, NULL, &ahb_clk);
 DEFINE_CLOCK(scc_clk,     0, NULL,          0, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
+DEFINE_CLOCK(ckil_clk,    0, NULL,          0, clk_ckil_get_rate, NULL, NULL);
 
 #define _REGISTER_CLOCK(d, n, c) \
         { \
@@ -518,9 +525,9 @@ DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
 
 static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "emi", emi_clk)
-        _REGISTER_CLOCK(NULL, "cspi", cspi1_clk)
-        _REGISTER_CLOCK(NULL, "cspi", cspi2_clk)
-        _REGISTER_CLOCK(NULL, "cspi", cspi3_clk)
+        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
         _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
         _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
@@ -531,6 +538,12 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
         _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
         _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
         _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
@@ -559,6 +572,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "iim", iim_clk)
         _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
         _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
+        _REGISTER_CLOCK("mxc_rtc", NULL, ckil_clk)
 };
 
 int __init mx31_clocks_init(unsigned long fref)
@@ -609,7 +623,7 @@ int __init mx31_clocks_init(unsigned long fref)
                 __raw_writel(reg, MXC_CCM_PMCR1);
         }
 
-        mxc_timer_init(&ipg_clk);
+        mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT);
 
         return 0;
 }
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index 9e87e08fb121..8a577f367250 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -129,19 +129,17 @@ struct platform_device mxc_uart_device4 = {
 
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
-        [0] = {
+        {
                 .chip.label = "gpio-0",
                 .base = IO_ADDRESS(GPIO1_BASE_ADDR),
                 .irq = MXC_INT_GPIO1,
                 .virtual_irq_start = MXC_GPIO_IRQ_START,
-        },
-        [1] = {
+        }, {
                 .chip.label = "gpio-1",
                 .base = IO_ADDRESS(GPIO2_BASE_ADDR),
                 .irq = MXC_INT_GPIO2,
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-        },
-        [2] = {
+        }, {
                 .chip.label = "gpio-2",
                 .base = IO_ADDRESS(GPIO3_BASE_ADDR),
                 .irq = MXC_INT_GPIO3,
@@ -173,11 +171,11 @@ static struct resource mxc_nand_resources[] = {
         {
                 .start  = 0, /* runtime dependent */
                 .end    = 0,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
         }, {
                 .start  = MXC_INT_NANDFC,
                 .end    = MXC_INT_NANDFC,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -193,8 +191,7 @@ static struct resource mxc_i2c0_resources[] = {
                 .start = I2C_BASE_ADDR,
                 .end = I2C_BASE_ADDR + SZ_4K - 1,
                 .flags = IORESOURCE_MEM,
-        },
-        {
+        }, {
                 .start = MXC_INT_I2C,
                 .end = MXC_INT_I2C,
                 .flags = IORESOURCE_IRQ,
@@ -213,8 +210,7 @@ static struct resource mxc_i2c1_resources[] = {
                 .start = I2C2_BASE_ADDR,
                 .end = I2C2_BASE_ADDR + SZ_4K - 1,
                 .flags = IORESOURCE_MEM,
-        },
-        {
+        }, {
                 .start = MXC_INT_I2C2,
                 .end = MXC_INT_I2C2,
                 .flags = IORESOURCE_IRQ,
@@ -233,8 +229,7 @@ static struct resource mxc_i2c2_resources[] = {
                 .start = I2C3_BASE_ADDR,
                 .end = I2C3_BASE_ADDR + SZ_4K - 1,
                 .flags = IORESOURCE_MEM,
-        },
-        {
+        }, {
                 .start = MXC_INT_I2C3,
                 .end = MXC_INT_I2C3,
                 .flags = IORESOURCE_IRQ,
@@ -371,8 +366,8 @@ struct platform_device mx3_camera = {
 
 static struct resource otg_resources[] = {
         {
-                .start  = OTG_BASE_ADDR,
-                .end    = OTG_BASE_ADDR + 0x1ff,
+                .start  = MX31_OTG_BASE_ADDR,
+                .end    = MX31_OTG_BASE_ADDR + 0x1ff,
                 .flags  = IORESOURCE_MEM,
         }, {
                 .start  = MXC_INT_USB3,
@@ -395,16 +390,142 @@ struct platform_device mxc_otg_udc_device = {
         .num_resources  = ARRAY_SIZE(otg_resources),
 };
 
+/* OTG host */
+struct platform_device mxc_otg_host = {
+        .name = "mxc-ehci",
+        .id = 0,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &otg_dmamask,
+        },
+        .resource = otg_resources,
+        .num_resources = ARRAY_SIZE(otg_resources),
+};
+
+/* USB host 1 */
+
+static u64 usbh1_dmamask = ~(u32)0;
+
+static struct resource mxc_usbh1_resources[] = {
+        {
+                .start = MX31_OTG_BASE_ADDR + 0x200,
+                .end = MX31_OTG_BASE_ADDR + 0x3ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_USB1,
+                .end = MXC_INT_USB1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_usbh1 = {
+        .name = "mxc-ehci",
+        .id = 1,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh1_dmamask,
+        },
+        .resource = mxc_usbh1_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
+};
+
+/* USB host 2 */
+static u64 usbh2_dmamask = ~(u32)0;
+
+static struct resource mxc_usbh2_resources[] = {
+        {
+                .start = MX31_OTG_BASE_ADDR + 0x400,
+                .end = MX31_OTG_BASE_ADDR + 0x5ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_USB2,
+                .end = MXC_INT_USB2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_usbh2 = {
+        .name = "mxc-ehci",
+        .id = 2,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh2_dmamask,
+        },
+        .resource = mxc_usbh2_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
+};
+
+/*
+ * SPI master controller
+ * 3 channels
+ */
+static struct resource imx_spi_0_resources[] = {
+        {
+               .start = CSPI1_BASE_ADDR,
+               .end = CSPI1_BASE_ADDR + SZ_4K - 1,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = MXC_INT_CSPI1,
+               .end = MXC_INT_CSPI1,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource imx_spi_1_resources[] = {
+        {
+                .start = CSPI2_BASE_ADDR,
+                .end = CSPI2_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_CSPI2,
+                .end = MXC_INT_CSPI2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource imx_spi_2_resources[] = {
+        {
+                .start = CSPI3_BASE_ADDR,
+                .end = CSPI3_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_CSPI3,
+                .end = MXC_INT_CSPI3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_spi_device0 = {
+        .name = "spi_imx",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(imx_spi_0_resources),
+        .resource = imx_spi_0_resources,
+};
+
+struct platform_device imx_spi_device1 = {
+        .name = "spi_imx",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(imx_spi_1_resources),
+        .resource = imx_spi_1_resources,
+};
+
+struct platform_device imx_spi_device2 = {
+        .name = "spi_imx",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(imx_spi_2_resources),
+        .resource = imx_spi_2_resources,
+};
+
 #ifdef CONFIG_ARCH_MX35
 static struct resource mxc_fec_resources[] = {
         {
                 .start  = MXC_FEC_BASE_ADDR,
                 .end    = MXC_FEC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
         }, {
                 .start  = MXC_INT_FEC,
                 .end    = MXC_INT_FEC,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -426,6 +547,14 @@ static int mx3_devices_init(void)
         if (cpu_is_mx35()) {
                 mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
                 mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
+                otg_resources[0].start = MX35_OTG_BASE_ADDR;
+                otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
+                otg_resources[1].start = MXC_INT_USBOTG;
+                otg_resources[1].end = MXC_INT_USBOTG;
+                mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
+                mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
+                mxc_usbh1_resources[1].start = MXC_INT_USBHS;
+                mxc_usbh1_resources[1].end = MXC_INT_USBHS;
         }
 
         return 0;
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index ffd494ddd4ac..79f2be45d139 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -16,5 +16,11 @@ extern struct platform_device mxc_fec_device;
 extern struct platform_device mxcsdhc_device0;
 extern struct platform_device mxcsdhc_device1;
 extern struct platform_device mxc_otg_udc_device;
+extern struct platform_device mxc_otg_host;
+extern struct platform_device mxc_usbh1;
+extern struct platform_device mxc_usbh2;
 extern struct platform_device mxc_rnga_device;
+extern struct platform_device imx_spi_device0;
+extern struct platform_device imx_spi_device1;
+extern struct platform_device imx_spi_device2;
 
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 1f5fdd456cb9..ad5a1122d765 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -30,6 +30,7 @@
 
 #include <mach/common.h>
 #include <mach/hardware.h>
+#include <mach/iomux-v3.h>
 
 /*!
  * @file mm.c
@@ -75,6 +76,7 @@ static struct map_desc mxc_io_desc[] __initdata = {
 void __init mx31_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX31);
+        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
 
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
@@ -82,10 +84,22 @@ void __init mx31_map_io(void)
 void __init mx35_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX35);
+        mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
 
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+void __init mx31_init_irq(void)
+{
+        mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+}
+
+void __init mx35_init_irq(void)
+{
+        mx31_init_irq();
+}
+
 #ifdef CONFIG_CACHE_L2X0
 static int mxc_init_l2x0(void)
 {
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index 30e2767a78ae..0497c152be18 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -517,7 +517,7 @@ static void __init mx31ads_map_io(void)
 
 static void __init mx31ads_init_irq(void)
 {
-        mxc_init_irq();
+        mx31_init_irq();
         mx31ads_init_expio();
 }
 
diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mx31lilly.c
index 6ab2f163cb95..423025150f6f 100644
--- a/arch/arm/mach-mx3/mx31lilly.c
+++ b/arch/arm/mach-mx3/mx31lilly.c
@@ -148,7 +148,7 @@ MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .init_machine   = mx31lilly_board_init,
         .timer          = &mx31lilly_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
index 86fe70fa3e13..a8d57decdfdb 100644
--- a/arch/arm/mach-mx3/mx31lite.c
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -71,12 +71,11 @@ static struct smsc911x_platform_config smsc911x_config = {
 };
 
 static struct resource smsc911x_resources[] = {
-        [0] = {
+        {
                 .start          = CS4_BASE_ADDR,
                 .end            = CS4_BASE_ADDR + 0x100,
                 .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start          = IOMUX_TO_IRQ(MX31_PIN_SFS6),
                 .end            = IOMUX_TO_IRQ(MX31_PIN_SFS6),
                 .flags          = IORESOURCE_IRQ,
@@ -162,7 +161,7 @@ MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx31lite_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &mx31lite_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 4704405165a1..b3e8f251ac79 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -16,7 +16,6 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#include <linux/fsl_devices.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
@@ -40,18 +39,6 @@ static unsigned int devboard_pins[] = {
         MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
         MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
         MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
-        /* USB OTG */
-        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
-        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
-        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
-        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
-        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
-        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
-        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
-        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
-        MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
-        MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
-        MX31_PIN_USB_OC__GPIO1_30,
 };
 
 static struct imxuart_platform_data uart_pdata = {
@@ -111,33 +98,6 @@ static struct imxmmc_platform_data sdhc2_pdata = {
         .exit   = devboard_sdhc2_exit,
 };
 
-static struct fsl_usb2_platform_data usb_pdata = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_ULPI,
-};
-
-#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)
-#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
-
-static void devboard_usbotg_init(void)
-{
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG);
-
-        gpio_request(OTG_EN_B, "usb-udc-en");
-        gpio_direction_output(OTG_EN_B, 0);
-}
-
 /*
  * system init for baseboard usage. Will be called by mx31moboard init.
  */
@@ -151,7 +111,4 @@ void __init mx31moboard_devboard_init(void)
         mxc_register_device(&mxc_uart_device1, &uart_pdata);
 
         mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
-
-        devboard_usbotg_init();
-        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
 }
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 641c3d6153ae..3e2b73051b94 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -16,7 +16,6 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#include <linux/fsl_devices.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
@@ -48,18 +47,8 @@ static unsigned int marxbot_pins[] = {
         MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
         MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
         MX31_PIN_TXD2__GPIO1_28,
-        /* USB OTG */
-        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
-        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
-        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
-        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
-        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
-        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
-        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
-        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
-        MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
-        MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
-        MX31_PIN_USB_OC__GPIO1_30,
+        /* dsPIC resets */
+        MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22,
 };
 
 #define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
@@ -115,31 +104,20 @@ static struct imxmmc_platform_data sdhc2_pdata = {
         .exit   = marxbot_sdhc2_exit,
 };
 
-static struct fsl_usb2_platform_data usb_pdata = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_ULPI,
-};
-
-#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)
-#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
+#define TRSLAT_RST_B    IOMUX_TO_GPIO(MX31_PIN_STXD5)
+#define DSPICS_RST_B    IOMUX_TO_GPIO(MX31_PIN_SRXD5)
 
-static void marxbot_usbotg_init(void)
+static void dspics_resets_init(void)
 {
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG);
-
-        gpio_request(OTG_EN_B, "usb-udc-en");
-        gpio_direction_output(OTG_EN_B, 0);
+        if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
+                gpio_direction_output(TRSLAT_RST_B, 1);
+                gpio_export(TRSLAT_RST_B, false);
+        }
+
+        if (!gpio_request(DSPICS_RST_B, "dspics-rst")) {
+                gpio_direction_output(DSPICS_RST_B, 1);
+                gpio_export(DSPICS_RST_B, false);
+        }
 }
 
 /*
@@ -152,8 +130,7 @@ void __init mx31moboard_marxbot_init(void)
         mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins),
                 "marxbot");
 
-        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
+        dspics_resets_init();
 
-        marxbot_usbotg_init();
-        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
 }
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c
index a17f2e411609..d3c6bb26271f 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mx31moboard.c
@@ -16,9 +16,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+#include <linux/delay.h>
+#include <linux/fsl_devices.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/leds.h>
 #include <linux/memory.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
@@ -36,6 +39,7 @@
 #include <mach/iomux-mx3.h>
 #include <mach/i2c.h>
 #include <mach/mmc.h>
+#include <mach/mx31.h>
 
 #include "devices.h"
 
@@ -55,6 +59,26 @@ static unsigned int moboard_pins[] = {
         MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0,
         MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD,
         MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27,
+        /* USB reset */
+        MX31_PIN_GPIO1_0__GPIO1_0,
+        /* USB OTG */
+        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+        MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+        MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
+        MX31_PIN_USB_OC__GPIO1_30,
+        /* LEDs */
+        MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
+        MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
+        /* SEL */
+        MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
+        MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
 };
 
 static struct physmap_flash_data mx31moboard_flash_data = {
@@ -142,8 +166,109 @@ static struct imxmmc_platform_data sdhc1_pdata = {
         .exit   = moboard_sdhc1_exit,
 };
 
+/*
+ * this pin is dedicated for all mx31moboard systems, so we do it here
+ */
+#define USB_RESET_B     IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)
+
+static void usb_xcvr_reset(void)
+{
+        gpio_request(USB_RESET_B, "usb-reset");
+        gpio_direction_output(USB_RESET_B, 0);
+        mdelay(1);
+        gpio_set_value(USB_RESET_B, 1);
+}
+
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
+
+static void moboard_usbotg_init(void)
+{
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
+
+        gpio_request(OTG_EN_B, "usb-udc-en");
+        gpio_direction_output(OTG_EN_B, 0);
+}
+
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_ULPI,
+};
+
+static struct gpio_led mx31moboard_leds[] = {
+        {
+                .name   = "coreboard-led-0:red:running",
+                .default_trigger = "heartbeat",
+                .gpio   = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
+        }, {
+                .name   = "coreboard-led-1:red",
+                .gpio   = IOMUX_TO_GPIO(MX31_PIN_STX0),
+        }, {
+                .name   = "coreboard-led-2:red",
+                .gpio   = IOMUX_TO_GPIO(MX31_PIN_SRX0),
+        }, {
+                .name   = "coreboard-led-3:red",
+                .gpio   = IOMUX_TO_GPIO(MX31_PIN_SIMPD0),
+        },
+};
+
+static struct gpio_led_platform_data mx31moboard_led_pdata = {
+        .num_leds       = ARRAY_SIZE(mx31moboard_leds),
+        .leds           = mx31moboard_leds,
+};
+
+static struct platform_device mx31moboard_leds_device = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &mx31moboard_led_pdata,
+        },
+};
+
+#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
+#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
+#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
+#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
+
+static void mx31moboard_init_sel_gpios(void)
+{
+        if (!gpio_request(SEL0, "sel0")) {
+                gpio_direction_input(SEL0);
+                gpio_export(SEL0, true);
+        }
+
+        if (!gpio_request(SEL1, "sel1")) {
+                gpio_direction_input(SEL1);
+                gpio_export(SEL1, true);
+        }
+
+        if (!gpio_request(SEL2, "sel2")) {
+                gpio_direction_input(SEL2);
+                gpio_export(SEL2, true);
+        }
+
+        if (!gpio_request(SEL3, "sel3")) {
+                gpio_direction_input(SEL3);
+                gpio_export(SEL3, true);
+        }
+}
+
 static struct platform_device *devices[] __initdata = {
         &mx31moboard_flash,
+        &mx31moboard_leds_device,
 };
 
 static int mx31moboard_baseboard;
@@ -162,11 +287,18 @@ static void __init mxc_board_init(void)
         mxc_register_device(&mxc_uart_device0, &uart_pdata);
         mxc_register_device(&mxc_uart_device4, &uart_pdata);
 
+        mx31moboard_init_sel_gpios();
+
         mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
         mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
 
         mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata);
 
+        usb_xcvr_reset();
+
+        moboard_usbotg_init();
+        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+
         switch (mx31moboard_baseboard) {
         case MX31NOBOARD:
                 break;
@@ -197,7 +329,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &mx31moboard_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c
index c19838d2e369..0f7a2f06bc2d 100644
--- a/arch/arm/mach-mx3/mx31pdk.c
+++ b/arch/arm/mach-mx3/mx31pdk.c
@@ -265,7 +265,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx31pdk_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &mx31pdk_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx35pdk.c b/arch/arm/mach-mx3/mx35pdk.c
index 6d15374414b9..6ff186e46ceb 100644
--- a/arch/arm/mach-mx3/mx35pdk.c
+++ b/arch/arm/mach-mx3/mx35pdk.c
@@ -98,7 +98,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx35_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx35_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &mx35pdk_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
index 840cfda341d0..6cbaabedf386 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -32,6 +32,7 @@
 #include <linux/spi/spi.h>
 #include <linux/irq.h>
 #include <linux/fsl_devices.h>
+#include <linux/can/platform/sja1000.h>
 
 #include <media/soc_camera.h>
 
@@ -169,6 +170,8 @@ static unsigned int pcm037_pins[] = {
         MX31_PIN_CSI_MCLK__CSI_MCLK,
         MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
         MX31_PIN_CSI_VSYNC__CSI_VSYNC,
+        /* GPIO */
+        IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
 };
 
 static struct physmap_flash_data pcm037_flash_data = {
@@ -244,12 +247,11 @@ static struct imxuart_platform_data uart_pdata = {
 };
 
 static struct resource smsc911x_resources[] = {
-        [0] = {
+        {
                 .start          = CS1_BASE_ADDR + 0x300,
                 .end            = CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
                 .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start          = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
                 .end            = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
                 .flags          = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
@@ -339,8 +341,7 @@ static struct i2c_board_info pcm037_i2c_devices[] = {
                 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
                 .platform_data = &board_eeprom,
         }, {
-                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
-                .type = "pcf8563",
+                I2C_BOARD_INFO("pcf8563", 0x51),
         }
 };
 
@@ -515,6 +516,33 @@ static struct mx3fb_platform_data mx3fb_pdata = {
         .num_modes      = ARRAY_SIZE(fb_modedb),
 };
 
+static struct resource pcm970_sja1000_resources[] = {
+        {
+                .start   = CS5_BASE_ADDR,
+                .end     = CS5_BASE_ADDR + 0x100 - 1,
+                .flags   = IORESOURCE_MEM,
+        }, {
+                .start   = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
+                .end     = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
+                .flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
+        },
+};
+
+struct sja1000_platform_data pcm970_sja1000_platform_data = {
+        .clock          = 16000000 / 2,
+        .ocr            = 0x40 | 0x18,
+        .cdr            = 0x40,
+};
+
+static struct platform_device pcm970_sja1000 = {
+        .name = "sja1000_platform",
+        .dev = {
+                .platform_data = &pcm970_sja1000_platform_data,
+        },
+        .resource = pcm970_sja1000_resources,
+        .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
+};
+
 /*
  * Board specific initialization.
  */
@@ -575,6 +603,8 @@ static void __init mxc_board_init(void)
 
         if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
                 mxc_register_device(&mx3_camera, &camera_pdata);
+
+        platform_device_register(&pcm970_sja1000);
 }
 
 static void __init pcm037_timer_init(void)
@@ -592,7 +622,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &pcm037_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/pcm043.c
index 8d27c324abf2..e18a224671fa 100644
--- a/arch/arm/mach-mx3/pcm043.c
+++ b/arch/arm/mach-mx3/pcm043.c
@@ -133,8 +133,7 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
                 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
                 .platform_data = &board_eeprom,
         }, {
-                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
-                .type = "pcf8563",
+                I2C_BOARD_INFO("pcf8563", 0x51),
         }
 };
 #endif
@@ -203,7 +202,8 @@ static struct pad_desc pcm043_pads[] = {
         MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
         MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
         MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
-        MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
+        /* gpio */
+        MX35_PAD_ATA_CS0__GPIO2_6,
 };
 
 /*
@@ -245,7 +245,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx35_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx35_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &pcm043_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/qong.c
index 82b31c4ab11f..044511f1b9a9 100644
--- a/arch/arm/mach-mx3/qong.c
+++ b/arch/arm/mach-mx3/qong.c
@@ -81,13 +81,12 @@ static inline void mxc_init_imx_uart(void)
 }
 
 static struct resource dnet_resources[] = {
-        [0] = {
+        {
                 .name   = "dnet-memory",
                 .start  = QONG_DNET_BASEADDR,
                 .end    = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
                 .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
+        }, {
                 .start  = QONG_FPGA_IRQ,
                 .end    = QONG_FPGA_IRQ,
                 .flags  = IORESOURCE_IRQ,
@@ -280,7 +279,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
         .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
         .boot_params    = PHYS_OFFSET + 0x100,
         .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
         .init_machine   = mxc_board_init,
         .timer          = &qong_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mxc91231/Kconfig b/arch/arm/mach-mxc91231/Kconfig
new file mode 100644
index 000000000000..8e5fa38ebb67
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_MXC91231
+
+comment "MXC91231 platforms:"
+
+config MACH_MAGX_ZN5
+        bool "Support Motorola Zn5 GSM phone"
+        default n
+        help
+          Include support for Motorola Zn5 GSM phone.
+
+endif
diff --git a/arch/arm/mach-mxc91231/Makefile b/arch/arm/mach-mxc91231/Makefile
new file mode 100644
index 000000000000..011d5e197125
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Makefile
@@ -0,0 +1,2 @@
+obj-y   := mm.o clock.o devices.o system.o iomux.o
+obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o
diff --git a/arch/arm/mach-mxc91231/Makefile.boot b/arch/arm/mach-mxc91231/Makefile.boot
new file mode 100644
index 000000000000..9939a19d99a1
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x90008000
+params_phys-y   := 0x90000100
+initrd_phys-y   := 0x90800000
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c
new file mode 100644
index 000000000000..ecfa37fef8ad
--- /dev/null
+++ b/arch/arm/mach-mxc91231/clock.c
@@ -0,0 +1,642 @@
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#include <asm/clkdev.h>
+#include <asm/bug.h>
+#include <asm/div64.h>
+
+#include "crm_regs.h"
+
+#define CRM_SMALL_DIVIDER(base, name) \
+        crm_small_divider(base, \
+                          base ## _ ## name ## _OFFSET, \
+                          base ## _ ## name ## _MASK)
+#define CRM_1DIVIDER(base, name) \
+        crm_divider(base, \
+                    base ## _ ## name ## _OFFSET, \
+                    base ## _ ## name ## _MASK, 1)
+#define CRM_16DIVIDER(base, name) \
+        crm_divider(base, \
+                    base ## _ ## name ## _OFFSET, \
+                    base ## _ ## name ## _MASK, 16)
+
+static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
+{
+        static const u32 crm_small_dividers[] = {
+                2, 3, 4, 5, 6, 8, 10, 12
+        };
+        u8 idx;
+
+        idx = (__raw_readl(reg) & mask) >> offset;
+        if (idx > 7)
+                return 1;
+
+        return crm_small_dividers[idx];
+}
+
+static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
+{
+        u32 div;
+        div = (__raw_readl(reg) & mask) >> offset;
+        return div ? div : z;
+}
+
+static int _clk_1bit_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_1bit_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_3bit_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 0x7 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_3bit_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(0x7 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static unsigned long ckih_rate;
+
+static unsigned long clk_ckih_get_rate(struct clk *clk)
+{
+        return ckih_rate;
+}
+
+static struct clk ckih_clk = {
+        .get_rate = clk_ckih_get_rate,
+};
+
+static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
+{
+        return 2 * clk_get_rate(clk->parent);
+}
+
+static struct clk ckih_x2_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_ckih_x2_get_rate,
+};
+
+static unsigned long clk_ckil_get_rate(struct clk *clk)
+{
+        return CKIL_CLK_FREQ;
+}
+
+static struct clk ckil_clk = {
+        .get_rate = clk_ckil_get_rate,
+};
+
+/* plls stuff */
+static struct clk mcu_pll_clk;
+static struct clk dsp_pll_clk;
+static struct clk usb_pll_clk;
+
+static struct clk *pll_clk(u8 sel)
+{
+        switch (sel) {
+        case 0:
+                return &mcu_pll_clk;
+        case 1:
+                return &dsp_pll_clk;
+        case 2:
+                return &usb_pll_clk;
+        }
+        BUG();
+}
+
+static void __iomem *pll_base(struct clk *clk)
+{
+        if (clk == &mcu_pll_clk)
+                return MXC_PLL0_BASE;
+        else if (clk == &dsp_pll_clk)
+                return MXC_PLL1_BASE;
+        else if (clk == &usb_pll_clk)
+                return MXC_PLL2_BASE;
+        BUG();
+}
+
+static unsigned long clk_pll_get_rate(struct clk *clk)
+{
+        const void __iomem *pllbase;
+        unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
+        long mfn, mfn_abs, mfd, pdf;
+        s64 temp;
+        pllbase = pll_base(clk);
+
+        pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
+        if (pll_hfsm == 0) {
+                dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
+                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
+                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
+        } else {
+                dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
+                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
+                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
+        }
+
+        pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
+        mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
+        mfi = (mfi <= 5) ? 5 : mfi;
+        mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
+        mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
+        mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
+
+        if (mfn < 0)
+                mfn_abs = -mfn;
+        else
+                mfn_abs = mfn;
+
+/* XXX: actually this asumes that ckih is fed to pll, but spec says
+ * that ckih_x2 is also possible. need to check this out.
+ */
+        ref_clk = clk_get_rate(&ckih_clk);
+
+        ref_clk *= 2;
+        ref_clk /= pdf + 1;
+
+        temp = (u64) ref_clk * mfn_abs;
+        do_div(temp, mfd);
+        if (mfn < 0)
+                temp = -temp;
+        temp += ref_clk * mfi;
+
+        return temp;
+}
+
+static int clk_pll_enable(struct clk *clk)
+{
+        void __iomem *ctl;
+        u32 reg;
+
+        ctl = pll_base(clk);
+        reg = __raw_readl(ctl);
+        reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
+        __raw_writel(reg, ctl);
+        do {
+                reg = __raw_readl(ctl);
+        } while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
+        return 0;
+}
+
+static void clk_pll_disable(struct clk *clk)
+{
+        void __iomem *ctl;
+        u32 reg;
+
+        ctl = pll_base(clk);
+        reg = __raw_readl(ctl);
+        reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
+        __raw_writel(reg, ctl);
+}
+
+static struct clk mcu_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_pll_get_rate,
+        .enable = clk_pll_enable,
+        .disable = clk_pll_disable,
+};
+
+static struct clk dsp_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_pll_get_rate,
+        .enable = clk_pll_enable,
+        .disable = clk_pll_disable,
+};
+
+static struct clk usb_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_pll_get_rate,
+        .enable = clk_pll_enable,
+        .disable = clk_pll_disable,
+};
+/* plls stuff end */
+
+/* ap_ref_clk stuff */
+static struct clk ap_ref_clk;
+
+static unsigned long clk_ap_ref_get_rate(struct clk *clk)
+{
+        u32 ascsr, acsr;
+        u8 ap_pat_ref_div_2, ap_isel, acs, ads;
+
+        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+        acsr = __raw_readl(MXC_CRMAP_ACSR);
+
+        /* 0 for ckih, 1 for ckih*2 */
+        ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
+        /* reg divider */
+        ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
+        /* undocumented, 1 for disabling divider */
+        ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
+        /* 0 for pat_ref, 1 for divider out */
+        acs = acsr & MXC_CRMAP_ACSR_ACS;
+
+        if (acs & !ads)
+                /* use divided clock */
+                return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);
+
+        return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
+}
+
+static struct clk ap_ref_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_ap_ref_get_rate,
+};
+/* ap_ref_clk stuff end */
+
+/* ap_pre_dfs_clk stuff */
+static struct clk ap_pre_dfs_clk;
+
+static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
+{
+        u32 acsr, ascsr;
+
+        acsr = __raw_readl(MXC_CRMAP_ACSR);
+        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+
+        if (acsr & MXC_CRMAP_ACSR_ACS) {
+                u8 sel;
+                sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
+                        MXC_CRMAP_ASCSR_APSEL_OFFSET;
+                return clk_get_rate(pll_clk(sel)) /
+                        CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
+        }
+        return clk_get_rate(&ap_ref_clk);
+}
+
+static struct clk ap_pre_dfs_clk = {
+        .get_rate = clk_ap_pre_dfs_get_rate,
+};
+/* ap_pre_dfs_clk stuff end */
+
+/* usb_clk stuff */
+static struct clk usb_clk;
+
+static struct clk *clk_usb_parent(struct clk *clk)
+{
+        u32 acsr, ascsr;
+
+        acsr = __raw_readl(MXC_CRMAP_ACSR);
+        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+
+        if (acsr & MXC_CRMAP_ACSR_ACS) {
+                u8 sel;
+                sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
+                        MXC_CRMAP_ASCSR_USBSEL_OFFSET;
+                return pll_clk(sel);
+        }
+        return &ap_ref_clk;
+}
+
+static unsigned long clk_usb_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) /
+                CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
+}
+
+static struct clk usb_clk = {
+        .enable_reg = MXC_CRMAP_ACDER2,
+        .enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
+        .get_rate = clk_usb_get_rate,
+        .enable = _clk_1bit_enable,
+        .disable = _clk_1bit_disable,
+};
+/* usb_clk stuff end */
+
+static unsigned long clk_ipg_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
+}
+
+static unsigned long clk_ahb_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) /
+                CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
+}
+
+static struct clk ipg_clk = {
+        .parent = &ap_pre_dfs_clk,
+        .get_rate = clk_ipg_get_rate,
+};
+
+static struct clk ahb_clk = {
+        .parent = &ap_pre_dfs_clk,
+        .get_rate = clk_ahb_get_rate,
+};
+
+/* perclk_clk stuff */
+static struct clk perclk_clk;
+
+static unsigned long clk_perclk_get_rate(struct clk *clk)
+{
+        u32 acder2;
+
+        acder2 = __raw_readl(MXC_CRMAP_ACDER2);
+        if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
+                return 2 * clk_get_rate(clk->parent);
+
+        return clk_get_rate(clk->parent);
+}
+
+static struct clk perclk_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_perclk_get_rate,
+};
+/* perclk_clk stuff end */
+
+/* uart_clk stuff */
+static struct clk uart_clk[];
+
+static unsigned long clk_uart_get_rate(struct clk *clk)
+{
+        u32 div;
+
+        switch (clk->id) {
+        case 0:
+        case 1:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
+                break;
+        case 2:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
+                break;
+        default:
+                BUG();
+        }
+        return clk_get_rate(clk->parent) / div;
+}
+
+static struct clk uart_clk[] = {
+        {
+                .id = 0,
+                .parent = &perclk_clk,
+                .enable_reg = MXC_CRMAP_APRA,
+                .enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
+                .get_rate = clk_uart_get_rate,
+                .enable = _clk_1bit_enable,
+                .disable = _clk_1bit_disable,
+        }, {
+                .id = 1,
+                .parent = &perclk_clk,
+                .enable_reg = MXC_CRMAP_APRA,
+                .enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
+                .get_rate = clk_uart_get_rate,
+                .enable = _clk_1bit_enable,
+                .disable = _clk_1bit_disable,
+        }, {
+                .id = 2,
+                .parent = &perclk_clk,
+                .enable_reg = MXC_CRMAP_APRA,
+                .enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
+                .get_rate = clk_uart_get_rate,
+                .enable = _clk_1bit_enable,
+                .disable = _clk_1bit_disable,
+        },
+};
+/* uart_clk stuff end */
+
+/* sdhc_clk stuff */
+static struct clk nfc_clk;
+
+static unsigned long clk_nfc_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) /
+                CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
+}
+
+static struct clk nfc_clk = {
+        .parent = &ahb_clk,
+        .enable_reg = MXC_CRMAP_ACDER2,
+        .enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
+        .get_rate = clk_nfc_get_rate,
+        .enable = _clk_1bit_enable,
+        .disable = _clk_1bit_disable,
+};
+/* sdhc_clk stuff end */
+
+/* sdhc_clk stuff */
+static struct clk sdhc_clk[];
+
+static struct clk *clk_sdhc_parent(struct clk *clk)
+{
+        u32 aprb;
+        u8 sel;
+        u32 mask;
+        int offset;
+
+        aprb = __raw_readl(MXC_CRMAP_APRB);
+
+        switch (clk->id) {
+        case 0:
+                mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
+                offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
+                break;
+        case 1:
+                mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
+                offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
+                break;
+        default:
+                BUG();
+        }
+        sel = (aprb & mask) >> offset;
+
+        switch (sel) {
+        case 0:
+                return &ckih_clk;
+        case 1:
+                return &ckih_x2_clk;
+        }
+        return &usb_clk;
+}
+
+static unsigned long clk_sdhc_get_rate(struct clk *clk)
+{
+        u32 div;
+
+        switch (clk->id) {
+        case 0:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
+                break;
+        case 1:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
+                break;
+        default:
+                BUG();
+        }
+
+        return clk_get_rate(clk->parent) / div;
+}
+
+static int clk_sdhc_enable(struct clk *clk)
+{
+        u32 amlpmre1, aprb;
+
+        amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
+        aprb = __raw_readl(MXC_CRMAP_APRB);
+        switch (clk->id) {
+        case 0:
+                amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
+                aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
+                break;
+        case 1:
+                amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
+                aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
+                break;
+        }
+        __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
+        __raw_writel(aprb, MXC_CRMAP_APRB);
+        return 0;
+}
+
+static void clk_sdhc_disable(struct clk *clk)
+{
+        u32 amlpmre1, aprb;
+
+        amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
+        aprb = __raw_readl(MXC_CRMAP_APRB);
+        switch (clk->id) {
+        case 0:
+                amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
+                aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
+                break;
+        case 1:
+                amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
+                aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
+                break;
+        }
+        __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
+        __raw_writel(aprb, MXC_CRMAP_APRB);
+}
+
+static struct clk sdhc_clk[] = {
+        {
+                .id = 0,
+                .get_rate = clk_sdhc_get_rate,
+                .enable = clk_sdhc_enable,
+                .disable = clk_sdhc_disable,
+        }, {
+                .id = 1,
+                .get_rate = clk_sdhc_get_rate,
+                .enable = clk_sdhc_enable,
+                .disable = clk_sdhc_disable,
+        },
+};
+/* sdhc_clk stuff end */
+
+/* wdog_clk stuff */
+static struct clk wdog_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRD,
+                .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRD,
+                .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        },
+};
+/* wdog_clk stuff end */
+
+/* gpt_clk stuff */
+static struct clk gpt_clk = {
+        .parent = &ipg_clk,
+        .enable_reg = MXC_CRMAP_AMLPMRC,
+        .enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
+        .enable = _clk_3bit_enable,
+        .disable = _clk_3bit_disable,
+};
+/* gpt_clk stuff end */
+
+/* cspi_clk stuff */
+static struct clk cspi_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRE2,
+                .enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRE1,
+                .enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        },
+};
+/* cspi_clk stuff end */
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
+        _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
+        _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
+        _REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
+        _REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
+        _REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
+};
+
+int __init mxc91231_clocks_init(unsigned long fref)
+{
+        void __iomem *gpt_base;
+        int i;
+
+        ckih_rate = fref;
+
+        usb_clk.parent = clk_usb_parent(&usb_clk);
+        sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
+        sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
+
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+
+        gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
+        mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
+
+        return 0;
+}
diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
new file mode 100644
index 000000000000..ce4f59058189
--- /dev/null
+++ b/arch/arm/mach-mxc91231/crm_regs.h
@@ -0,0 +1,399 @@
+/*
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ * Copyright 2006-2007 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
+#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
+
+#define CKIL_CLK_FREQ                   32768
+
+#define MXC_CRM_AP_BASE                 MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR)
+#define MXC_CRM_COM_BASE                MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR)
+#define MXC_DSM_BASE                    MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR)
+#define MXC_PLL0_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR)
+#define MXC_PLL1_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR)
+#define MXC_PLL2_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR)
+#define MXC_CLKCTL_BASE                 MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR)
+
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL                  0x00
+#define MXC_PLL_DP_CONFIG               0x04
+#define MXC_PLL_DP_OP                   0x08
+#define MXC_PLL_DP_MFD                  0x0C
+#define MXC_PLL_DP_MFN                  0x10
+#define MXC_PLL_DP_HFS_OP               0x1C
+#define MXC_PLL_DP_HFS_MFD              0x20
+#define MXC_PLL_DP_HFS_MFN              0x24
+
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN      0x1000
+#define MXC_PLL_DP_CTL_ADE              0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV      0x400
+#define MXC_PLL_DP_CTL_HFSM             0x80
+#define MXC_PLL_DP_CTL_PRE              0x40
+#define MXC_PLL_DP_CTL_UPEN             0x20
+#define MXC_PLL_DP_CTL_RST              0x10
+#define MXC_PLL_DP_CTL_RCP              0x8
+#define MXC_PLL_DP_CTL_PLM              0x4
+#define MXC_PLL_DP_CTL_BRM0             0x2
+#define MXC_PLL_DP_CTL_LRF              0x1
+
+#define MXC_PLL_DP_OP_MFI_OFFSET        4
+#define MXC_PLL_DP_OP_MFI_MASK          0xF
+#define MXC_PLL_DP_OP_PDF_OFFSET        0
+#define MXC_PLL_DP_OP_PDF_MASK          0xF
+
+#define MXC_PLL_DP_MFD_OFFSET           0
+#define MXC_PLL_DP_MFD_MASK             0x7FFFFFF
+
+#define MXC_PLL_DP_MFN_OFFSET           0
+#define MXC_PLL_DP_MFN_MASK             0x7FFFFFF
+
+/* CRM AP Register Offsets */
+#define MXC_CRMAP_ASCSR                 (MXC_CRM_AP_BASE + 0x00)
+#define MXC_CRMAP_ACDR                  (MXC_CRM_AP_BASE + 0x04)
+#define MXC_CRMAP_ACDER1                (MXC_CRM_AP_BASE + 0x08)
+#define MXC_CRMAP_ACDER2                (MXC_CRM_AP_BASE + 0x0C)
+#define MXC_CRMAP_ACGCR                 (MXC_CRM_AP_BASE + 0x10)
+#define MXC_CRMAP_ACCGCR                (MXC_CRM_AP_BASE + 0x14)
+#define MXC_CRMAP_AMLPMRA               (MXC_CRM_AP_BASE + 0x18)
+#define MXC_CRMAP_AMLPMRB               (MXC_CRM_AP_BASE + 0x1C)
+#define MXC_CRMAP_AMLPMRC               (MXC_CRM_AP_BASE + 0x20)
+#define MXC_CRMAP_AMLPMRD               (MXC_CRM_AP_BASE + 0x24)
+#define MXC_CRMAP_AMLPMRE1              (MXC_CRM_AP_BASE + 0x28)
+#define MXC_CRMAP_AMLPMRE2              (MXC_CRM_AP_BASE + 0x2C)
+#define MXC_CRMAP_AMLPMRF               (MXC_CRM_AP_BASE + 0x30)
+#define MXC_CRMAP_AMLPMRG               (MXC_CRM_AP_BASE + 0x34)
+#define MXC_CRMAP_APGCR                 (MXC_CRM_AP_BASE + 0x38)
+#define MXC_CRMAP_ACSR                  (MXC_CRM_AP_BASE + 0x3C)
+#define MXC_CRMAP_ADCR                  (MXC_CRM_AP_BASE + 0x40)
+#define MXC_CRMAP_ACR                   (MXC_CRM_AP_BASE + 0x44)
+#define MXC_CRMAP_AMCR                  (MXC_CRM_AP_BASE + 0x48)
+#define MXC_CRMAP_APCR                  (MXC_CRM_AP_BASE + 0x4C)
+#define MXC_CRMAP_AMORA                 (MXC_CRM_AP_BASE + 0x50)
+#define MXC_CRMAP_AMORB                 (MXC_CRM_AP_BASE + 0x54)
+#define MXC_CRMAP_AGPR                  (MXC_CRM_AP_BASE + 0x58)
+#define MXC_CRMAP_APRA                  (MXC_CRM_AP_BASE + 0x5C)
+#define MXC_CRMAP_APRB                  (MXC_CRM_AP_BASE + 0x60)
+#define MXC_CRMAP_APOR                  (MXC_CRM_AP_BASE + 0x64)
+#define MXC_CRMAP_ADFMR                 (MXC_CRM_AP_BASE + 0x68)
+
+/* CRM AP Register Bit definitions */
+#define MXC_CRMAP_ASCSR_CRS                     0x10000
+#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET       15
+#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2          0x8000
+#define MXC_CRMAP_ASCSR_USBSEL_OFFSET           13
+#define MXC_CRMAP_ASCSR_USBSEL_MASK             (0x3 << 13)
+#define MXC_CRMAP_ASCSR_CSISEL_OFFSET           11
+#define MXC_CRMAP_ASCSR_CSISEL_MASK             (0x3 << 11)
+#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET          7
+#define MXC_CRMAP_ASCSR_SSI2SEL_MASK            (0x3 << 7)
+#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET          5
+#define MXC_CRMAP_ASCSR_SSI1SEL_MASK            (0x3 << 5)
+#define MXC_CRMAP_ASCSR_APSEL_OFFSET            3
+#define MXC_CRMAP_ASCSR_APSEL_MASK              (0x3 << 3)
+#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET       2
+#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1          0x4
+#define MXC_CRMAP_ASCSR_APISEL                  0x1
+
+#define MXC_CRMAP_ACDR_ARMDIV_OFFSET            8
+#define MXC_CRMAP_ACDR_ARMDIV_MASK              (0xF << 8)
+#define MXC_CRMAP_ACDR_AHBDIV_OFFSET            4
+#define MXC_CRMAP_ACDR_AHBDIV_MASK              (0xF << 4)
+#define MXC_CRMAP_ACDR_IPDIV_OFFSET             0
+#define MXC_CRMAP_ACDR_IPDIV_MASK               0xF
+
+#define MXC_CRMAP_ACDER1_CSIEN_OFFSET           30
+#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET          24
+#define MXC_CRMAP_ACDER1_CSIDIV_MASK            (0x3F << 24)
+#define MXC_CRMAP_ACDER1_SSI2EN_OFFSET          14
+#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET         8
+#define MXC_CRMAP_ACDER1_SSI2DIV_MASK           (0x3F << 8)
+#define MXC_CRMAP_ACDER1_SSI1EN_OFFSET          6
+#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET         0
+#define MXC_CRMAP_ACDER1_SSI1DIV_MASK           0x3F
+
+#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET    24
+#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK      (0x7 << 24)
+#define MXC_CRMAP_ACDER2_NFCEN_OFFSET           20
+#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET          16
+#define MXC_CRMAP_ACDER2_NFCDIV_MASK            (0xF << 16)
+#define MXC_CRMAP_ACDER2_USBEN_OFFSET           12
+#define MXC_CRMAP_ACDER2_USBDIV_OFFSET          8
+#define MXC_CRMAP_ACDER2_USBDIV_MASK            (0xF << 8)
+#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET       5
+#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK         (0x3 << 5)
+#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET         0
+#define MXC_CRMAP_ACDER2_BAUDDIV_MASK           0xF
+
+#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET         22
+#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET         19
+#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK           (0x7 << 19)
+#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET         12
+#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET         9
+#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET         6
+#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET         3
+#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK           (0x7 << 3)
+
+#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET         0
+#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK           0x7
+
+#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET         28
+#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK           (0x7 << 28)
+#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET         22
+#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET         16
+#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK           (0x7 << 16)
+#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET         12
+#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET         9
+#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET         6
+#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET         3
+#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK           (0x7 << 3)
+#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET         0
+#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK           0x7
+
+#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET         22
+#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET         12
+#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET         9
+#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET         6
+#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET         0
+#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK           0x7
+
+#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET        28
+#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK          (0x7 << 28)
+#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET        25
+#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK          (0x7 << 25)
+#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET        22
+#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK          (0x7 << 22)
+#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET        19
+#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK          (0x7 << 19)
+#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET        16
+#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK          (0x7 << 16)
+#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET        12
+#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK          (0x7 << 12)
+#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET        9
+#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK          (0x7 << 9)
+#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET        6
+#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK          (0x7 << 6)
+#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET        3
+#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK          (0x7 << 3)
+#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET        0
+#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK          0x7
+
+#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET        0
+#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK          0x7
+
+#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET         19
+#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK           (0x7 << 19)
+#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET         16
+#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK           (0x7 << 16)
+#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET         9
+#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET         6
+#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET         3
+#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK           (0x7 << 3)
+#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET         0
+#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK           (0x7 << 0)
+
+#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET         28
+#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK           (0x7 << 28)
+#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET         22
+#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET         19
+#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK           (0x7 << 19)
+#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET         16
+#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK           (0x7 << 16)
+#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET         12
+#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET         9
+#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET         6
+#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET         3
+#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK           (0x7 << 3)
+#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET         0
+#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK           0x7
+
+#define MXC_CRMAP_AGPR_IPUPAD_OFFSET            20
+#define MXC_CRMAP_AGPR_IPUPAD_MASK              (0x7 << 20)
+
+#define MXC_CRMAP_APRA_EL1TEN_OFFSET            29
+#define MXC_CRMAP_APRA_SIMEN_OFFSET             24
+#define MXC_CRMAP_APRA_UART3DIV_OFFSET          17
+#define MXC_CRMAP_APRA_UART3DIV_MASK            (0xF << 17)
+#define MXC_CRMAP_APRA_UART3EN_OFFSET           16
+#define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14
+#define MXC_CRMAP_APRA_MQSPIEN_OFFSET           13
+#define MXC_CRMAP_APRA_UART2EN_OFFSET           8
+#define MXC_CRMAP_APRA_UART1EN_OFFSET           0
+
+#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET        13
+#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK          (0x7 << 13)
+#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET         9
+#define MXC_CRMAP_APRB_SDHC2_DIV_MASK           (0xF << 9)
+#define MXC_CRMAP_APRB_SDHC2EN_OFFSET           8
+#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET        5
+#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK          (0x7 << 5)
+#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET         1
+#define MXC_CRMAP_APRB_SDHC1_DIV_MASK           (0xF << 1)
+#define MXC_CRMAP_APRB_SDHC1EN_OFFSET           0
+
+#define MXC_CRMAP_ACSR_ADS_OFFSET               8
+#define MXC_CRMAP_ACSR_ADS                      (0x1 << 8)
+#define MXC_CRMAP_ACSR_ACS                      0x1
+
+#define MXC_CRMAP_ADCR_LFDF_0                   (0x0 << 8)
+#define MXC_CRMAP_ADCR_LFDF_2                   (0x1 << 8)
+#define MXC_CRMAP_ADCR_LFDF_4                   (0x2 << 8)
+#define MXC_CRMAP_ADCR_LFDF_8                   (0x3 << 8)
+#define MXC_CRMAP_ADCR_LFDF_OFFSET              8
+#define MXC_CRMAP_ADCR_LFDF_MASK                (0x3 << 8)
+#define MXC_CRMAP_ADCR_ALT_PLL                  0x80
+#define MXC_CRMAP_ADCR_DFS_DIVEN                0x20
+#define MXC_CRMAP_ADCR_DIV_BYP                  0x2
+#define MXC_CRMAP_ADCR_VSTAT                    0x8
+#define MXC_CRMAP_ADCR_TSTAT                    0x10
+#define MXC_CRMAP_ADCR_DVFS_VCTRL               0x10
+#define MXC_CRMAP_ADCR_CLK_ON                   0x40
+
+#define MXC_CRMAP_ADFMR_FC_OFFSET               16
+#define MXC_CRMAP_ADFMR_FC_MASK                 (0x1F << 16)
+#define MXC_CRMAP_ADFMR_MF_OFFSET               1
+#define MXC_CRMAP_ADFMR_MF_MASK                 (0x3FF << 1)
+#define MXC_CRMAP_ADFMR_DFM_CLK_READY           0x1
+#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN            0x8000
+
+#define MXC_CRMAP_ACR_CKOHS_HIGH                (1 << 18)
+#define MXC_CRMAP_ACR_CKOS_HIGH                 (1 << 16)
+#define MXC_CRMAP_ACR_CKOHS_MASK                (0x7 << 12)
+#define MXC_CRMAP_ACR_CKOHD                     (1 << 11)
+#define MXC_CRMAP_ACR_CKOHDIV_MASK              (0xF << 8)
+#define MXC_CRMAP_ACR_CKOHDIV_OFFSET            8
+#define MXC_CRMAP_ACR_CKOD                      (1 << 7)
+#define MXC_CRMAP_ACR_CKOS_MASK                 (0x7 << 4)
+
+/* AP Warm reset */
+#define MXC_CRMAP_AMCR_SW_AP                    (1 << 14)
+
+/* Bit definitions of ACGCR in CRM_AP for tree level clock gating */
+#define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT          0x00000001
+#define MXC_CRMAP_ACGCR_ACG0_STOP               0x00000003
+#define MXC_CRMAP_ACGCR_ACG0_RUN                0x00000007
+#define MXC_CRMAP_ACGCR_ACG0_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT          0x00000008
+#define MXC_CRMAP_ACGCR_ACG1_STOP               0x00000018
+#define MXC_CRMAP_ACGCR_ACG1_RUN                0x00000038
+#define MXC_CRMAP_ACGCR_ACG1_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT          0x00000040
+#define MXC_CRMAP_ACGCR_ACG2_STOP               0x000000C0
+#define MXC_CRMAP_ACGCR_ACG2_RUN                0x000001C0
+#define MXC_CRMAP_ACGCR_ACG2_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT          0x00000200
+#define MXC_CRMAP_ACGCR_ACG3_STOP               0x00000600
+#define MXC_CRMAP_ACGCR_ACG3_RUN                0x00000E00
+#define MXC_CRMAP_ACGCR_ACG3_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT          0x00001000
+#define MXC_CRMAP_ACGCR_ACG4_STOP               0x00003000
+#define MXC_CRMAP_ACGCR_ACG4_RUN                0x00007000
+#define MXC_CRMAP_ACGCR_ACG4_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT          0x00010000
+#define MXC_CRMAP_ACGCR_ACG5_STOP               0x00030000
+#define MXC_CRMAP_ACGCR_ACG5_RUN                0x00070000
+#define MXC_CRMAP_ACGCR_ACG5_DISABLED           0x00000000
+
+#define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT          0x00080000
+#define MXC_CRMAP_ACGCR_ACG6_STOP               0x00180000
+#define MXC_CRMAP_ACGCR_ACG6_RUN                0x00380000
+#define MXC_CRMAP_ACGCR_ACG6_DISABLED           0x00000000
+
+#define NUM_GATE_CTRL                           6
+
+/* CRM COM Register Offsets */
+#define MXC_CRMCOM_CSCR                         (MXC_CRM_COM_BASE + 0x0C)
+#define MXC_CRMCOM_CCCR                         (MXC_CRM_COM_BASE + 0x10)
+
+/* CRM COM Bit Definitions */
+#define MXC_CRMCOM_CSCR_PPD1                    0x08000000
+#define MXC_CRMCOM_CSCR_CKOHSEL                 (1 << 18)
+#define MXC_CRMCOM_CSCR_CKOSEL                  (1 << 17)
+#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET           8
+#define MXC_CRMCOM_CCCR_CC_DIV_MASK             (0x1F << 8)
+#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET           0
+#define MXC_CRMCOM_CCCR_CC_SEL_MASK             0x3
+
+/* DSM Register Offsets */
+#define MXC_DSM_SLEEP_TIME                      (MXC_DSM_BASE + 0x0c)
+#define MXC_DSM_CONTROL0                        (MXC_DSM_BASE + 0x20)
+#define MXC_DSM_CONTROL1                        (MXC_DSM_BASE + 0x24)
+#define MXC_DSM_CTREN                           (MXC_DSM_BASE + 0x28)
+#define MXC_DSM_WARM_PER                        (MXC_DSM_BASE + 0x40)
+#define MXC_DSM_LOCK_PER                        (MXC_DSM_BASE + 0x44)
+#define MXC_DSM_MGPER                           (MXC_DSM_BASE + 0x4c)
+#define MXC_DSM_CRM_CONTROL                     (MXC_DSM_BASE + 0x50)
+
+/* Bit definitions of various registers in DSM */
+#define MXC_DSM_CRM_CTRL_DVFS_BYP               0x00000008
+#define MXC_DSM_CRM_CTRL_DVFS_VCTRL             0x00000004
+#define MXC_DSM_CRM_CTRL_LPMD1                  0x00000002
+#define MXC_DSM_CRM_CTRL_LPMD0                  0x00000001
+#define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE         0x00000000
+#define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE         0x00000001
+#define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE          0x00000003
+#define MXC_DSM_CONTROL0_STBY_COMMIT_EN         0x00000200
+#define MXC_DSM_CONTROL0_MSTR_EN                0x00000001
+#define MXC_DSM_CONTROL0_RESTART                0x00000010
+/* Counter Block reset */
+#define MXC_DSM_CONTROL1_CB_RST                 0x00000002
+/* State Machine reset */
+#define MXC_DSM_CONTROL1_SM_RST                 0x00000004
+/* Bit needed to reset counter block */
+#define MXC_CONTROL1_RST_CNT32                  0x00000008
+#define MXC_DSM_CONTROL1_RST_CNT32_EN           0x00000800
+#define MXC_DSM_CONTROL1_SLEEP                  0x00000100
+#define MXC_DSM_CONTROL1_WAKEUP_DISABLE         0x00004000
+#define MXC_DSM_CTREN_CNT32                     0x00000001
+
+/* Magic Fix enable bit */
+#define MXC_DSM_MGPER_EN_MGFX                   0x80000000
+#define MXC_DSM_MGPER_PER_MASK                  0x000003FF
+#define MXC_DSM_MGPER_PER(n)                    (MXC_DSM_MGPER_PER_MASK & n)
+
+/* Address offsets of the CLKCTL registers */
+#define MXC_CLKCTL_GP_CTRL      (MXC_CLKCTL_BASE + 0x00)
+#define MXC_CLKCTL_GP_SER       (MXC_CLKCTL_BASE + 0x04)
+#define MXC_CLKCTL_GP_CER       (MXC_CLKCTL_BASE + 0x08)
+
+#endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */
diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
new file mode 100644
index 000000000000..353bd977b393
--- /dev/null
+++ b/arch/arm/mach-mxc91231/devices.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <linux/gpio.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/imx-uart.h>
+
+static struct resource uart0[] = {
+        {
+                .start = MXC91231_UART1_BASE_ADDR,
+                .end = MXC91231_UART1_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_UART1_RX,
+                .end = MXC91231_INT_UART1_RX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART1_TX,
+                .end = MXC91231_INT_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART1_MINT,
+                .end = MXC91231_INT_UART1_MINT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device0 = {
+        .name = "imx-uart",
+        .id = 0,
+        .resource = uart0,
+        .num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct resource uart1[] = {
+        {
+                .start = MXC91231_UART2_BASE_ADDR,
+                .end = MXC91231_UART2_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_UART2_RX,
+                .end = MXC91231_INT_UART2_RX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART2_TX,
+                .end = MXC91231_INT_UART2_TX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART2_MINT,
+                .end = MXC91231_INT_UART2_MINT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_uart_device1 = {
+        .name = "imx-uart",
+        .id = 1,
+        .resource = uart1,
+        .num_resources = ARRAY_SIZE(uart1),
+};
+
+static struct resource uart2[] = {
+        {
+                .start = MXC91231_UART3_BASE_ADDR,
+                .end = MXC91231_UART3_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_UART3_RX,
+                .end = MXC91231_INT_UART3_RX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART3_TX,
+                .end = MXC91231_INT_UART3_TX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART3_MINT,
+                .end = MXC91231_INT_UART3_MINT,
+                .flags = IORESOURCE_IRQ,
+
+        },
+};
+
+struct platform_device mxc_uart_device2 = {
+        .name = "imx-uart",
+        .id = 2,
+        .resource = uart2,
+        .num_resources = ARRAY_SIZE(uart2),
+};
+
+/* GPIO port description */
+static struct mxc_gpio_port mxc_gpio_ports[] = {
+        [0] = {
+                .chip.label = "gpio-0",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO1_AP_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO1,
+                .virtual_irq_start = MXC_GPIO_IRQ_START,
+        },
+        [1] = {
+                .chip.label = "gpio-1",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO2_AP_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO2,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+        },
+        [2] = {
+                .chip.label = "gpio-2",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO3_AP_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO3,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+        },
+        [3] = {
+                .chip.label = "gpio-3",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO4_SH_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO4,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
+        },
+};
+
+int __init mxc_register_gpios(void)
+{
+        return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
+}
+
+static struct resource mxc_nand_resources[] = {
+        {
+                .start  = MXC91231_NFC_BASE_ADDR,
+                .end    = MXC91231_NFC_BASE_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM
+        }, {
+                .start  = MXC91231_INT_NANDFC,
+                .end    = MXC91231_INT_NANDFC,
+                .flags  = IORESOURCE_IRQ
+        },
+};
+
+struct platform_device mxc_nand_device = {
+        .name = "mxc_nand",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_nand_resources),
+        .resource = mxc_nand_resources,
+};
+
+static struct resource mxc_sdhc0_resources[] = {
+        {
+                .start = MXC91231_MMC_SDHC1_BASE_ADDR,
+                .end = MXC91231_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_MMC_SDHC1,
+                .end = MXC91231_INT_MMC_SDHC1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource mxc_sdhc1_resources[] = {
+        {
+                .start = MXC91231_MMC_SDHC2_BASE_ADDR,
+                .end = MXC91231_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_MMC_SDHC2,
+                .end = MXC91231_INT_MMC_SDHC2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_sdhc_device0 = {
+        .name = "mxc-mmc",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_sdhc0_resources),
+        .resource = mxc_sdhc0_resources,
+};
+
+struct platform_device mxc_sdhc_device1 = {
+        .name = "mxc-mmc",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
+        .resource = mxc_sdhc1_resources,
+};
+
+static struct resource mxc_cspi0_resources[] = {
+        {
+                .start = MXC91231_CSPI1_BASE_ADDR,
+                .end = MXC91231_CSPI1_BASE_ADDR + 0x20,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_CSPI1,
+                .end = MXC91231_INT_CSPI1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_cspi_device0 = {
+        .name = "spi_imx",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_cspi0_resources),
+        .resource = mxc_cspi0_resources,
+};
+
+static struct resource mxc_cspi1_resources[] = {
+        {
+                .start = MXC91231_CSPI2_BASE_ADDR,
+                .end = MXC91231_CSPI2_BASE_ADDR + 0x20,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_CSPI2,
+                .end = MXC91231_INT_CSPI2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_cspi_device1 = {
+        .name = "spi_imx",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_cspi1_resources),
+        .resource = mxc_cspi1_resources,
+};
+
+static struct resource mxc_wdog0_resources[] = {
+        {
+                .start = MXC91231_WDOG1_BASE_ADDR,
+                .end = MXC91231_WDOG1_BASE_ADDR + 0x10,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device mxc_wdog_device0 = {
+        .name = "mxc-wdt",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_wdog0_resources),
+        .resource = mxc_wdog0_resources,
+};
diff --git a/arch/arm/mach-mxc91231/devices.h b/arch/arm/mach-mxc91231/devices.h
new file mode 100644
index 000000000000..72a2136ce27d
--- /dev/null
+++ b/arch/arm/mach-mxc91231/devices.h
@@ -0,0 +1,13 @@
+extern struct platform_device mxc_uart_device0;
+extern struct platform_device mxc_uart_device1;
+extern struct platform_device mxc_uart_device2;
+
+extern struct platform_device mxc_nand_device;
+
+extern struct platform_device mxc_sdhc_device0;
+extern struct platform_device mxc_sdhc_device1;
+
+extern struct platform_device mxc_cspi_device0;
+extern struct platform_device mxc_cspi_device1;
+
+extern struct platform_device mxc_wdog_device0;
diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c
new file mode 100644
index 000000000000..405d9b19d891
--- /dev/null
+++ b/arch/arm/mach-mxc91231/iomux.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/iomux-mxc91231.h>
+
+/*
+ * IOMUX register (base) addresses
+ */
+#define IOMUX_AP_BASE           MXC91231_IO_ADDRESS(MXC91231_IOMUX_AP_BASE_ADDR)
+#define IOMUX_COM_BASE          MXC91231_IO_ADDRESS(MXC91231_IOMUX_COM_BASE_ADDR)
+#define IOMUXSW_AP_MUX_CTL      (IOMUX_AP_BASE + 0x000)
+#define IOMUXSW_SP_MUX_CTL      (IOMUX_COM_BASE + 0x000)
+#define IOMUXSW_PAD_CTL         (IOMUX_COM_BASE + 0x200)
+
+#define IOMUXINT_OBS1           (IOMUX_AP_BASE + 0x600)
+#define IOMUXINT_OBS2           (IOMUX_AP_BASE + 0x004)
+
+static DEFINE_SPINLOCK(gpio_mux_lock);
+
+#define NB_PORTS                        ((PIN_MAX + 32) / 32)
+#define PIN_GLOBAL_NUM(pin) \
+        (((pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT)*PIN_AP_MAX + \
+         ((pin & MUX_REG_MASK) >> MUX_REG_SHIFT)*4 +            \
+         ((pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT))
+
+unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
+/*
+ * set the mode for a IOMUX pin.
+ */
+int mxc_iomux_mode(const unsigned int pin_mode)
+{
+        u32 side, field, l, mode, ret = 0;
+        void __iomem *reg;
+
+        side = (pin_mode & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT;
+        switch (side) {
+        case MUX_SIDE_AP:
+                reg = IOMUXSW_AP_MUX_CTL;
+                break;
+        case MUX_SIDE_SP:
+                reg = IOMUXSW_SP_MUX_CTL;
+                break;
+        default:
+                return -EINVAL;
+        }
+        reg += ((pin_mode & MUX_REG_MASK) >> MUX_REG_SHIFT) * 4;
+        field = (pin_mode & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT;
+        mode = (pin_mode & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+
+        spin_lock(&gpio_mux_lock);
+
+        l = __raw_readl(reg);
+        l &= ~(0xff << (field * 8));
+        l |= mode << (field * 8);
+        __raw_writel(l, reg);
+
+        spin_unlock(&gpio_mux_lock);
+
+        return ret;
+}
+EXPORT_SYMBOL(mxc_iomux_mode);
+
+/*
+ * This function configures the pad value for a IOMUX pin.
+ */
+void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
+{
+        u32 padgrp, field, l;
+        void __iomem *reg;
+
+        padgrp = (pin & MUX_PADGRP_MASK) >> MUX_PADGRP_SHIFT;
+        reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
+        field = (pin + 2) % 3;
+
+        pr_debug("%s: reg offset = 0x%x, field = %d\n",
+                        __func__, (pin + 2) / 3, field);
+
+        spin_lock(&gpio_mux_lock);
+
+        l = __raw_readl(reg);
+        l &= ~(0x1ff << (field * 10));
+        l |= config << (field * 10);
+        __raw_writel(l, reg);
+
+        spin_unlock(&gpio_mux_lock);
+}
+EXPORT_SYMBOL(mxc_iomux_set_pad);
+
+/*
+ * allocs a single pin:
+ *      - reserves the pin so that it is not claimed by another driver
+ *      - setups the iomux according to the configuration
+ */
+int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label)
+{
+        unsigned pad = PIN_GLOBAL_NUM(pin_mode);
+        if (pad >= (PIN_MAX + 1)) {
+                printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
+                        pad, label ? label : "?");
+                return -EINVAL;
+        }
+
+        if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
+                printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
+                        pad, label ? label : "?");
+                return -EBUSY;
+        }
+        mxc_iomux_mode(pin_mode);
+
+        return 0;
+}
+EXPORT_SYMBOL(mxc_iomux_alloc_pin);
+
+int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+                const char *label)
+{
+        unsigned int *p = pin_list;
+        int i;
+        int ret = -EINVAL;
+
+        for (i = 0; i < count; i++) {
+                ret = mxc_iomux_alloc_pin(*p, label);
+                if (ret)
+                        goto setup_error;
+                p++;
+        }
+        return 0;
+
+setup_error:
+        mxc_iomux_release_multiple_pins(pin_list, i);
+        return ret;
+}
+EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
+
+void mxc_iomux_release_pin(const unsigned int pin_mode)
+{
+        unsigned pad = PIN_GLOBAL_NUM(pin_mode);
+
+        if (pad < (PIN_MAX + 1))
+                clear_bit(pad, mxc_pin_alloc_map);
+}
+EXPORT_SYMBOL(mxc_iomux_release_pin);
+
+void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
+{
+        unsigned int *p = pin_list;
+        int i;
+
+        for (i = 0; i < count; i++) {
+                mxc_iomux_release_pin(*p);
+                p++;
+        }
+}
+EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
new file mode 100644
index 000000000000..7dbe4ca12efd
--- /dev/null
+++ b/arch/arm/mach-mxc91231/magx-zn5.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
+ *
+ * This file is released under the GPLv2 or later.
+ */
+
+#include <linux/irq.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/time.h>
+#include <asm/mach/arch.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mxc91231.h>
+#include <mach/mmc.h>
+#include <mach/imx-uart.h>
+
+#include "devices.h"
+
+static struct imxuart_platform_data uart_pdata = {
+};
+
+static struct imxmmc_platform_data sdhc_pdata = {
+};
+
+static void __init zn5_init(void)
+{
+        pm_power_off = mxc91231_power_off;
+
+        mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_DAT_VP__RXD2, "uart2-rx");
+        mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_SE0_VM__TXD2, "uart2-tx");
+
+        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+
+        mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
+
+        mxc_register_device(&mxc_wdog_device0, NULL);
+
+        return;
+}
+
+static void __init zn5_timer_init(void)
+{
+        mxc91231_clocks_init(26000000); /* 26mhz ckih */
+}
+
+struct sys_timer zn5_timer = {
+        .init = zn5_timer_init,
+};
+
+MACHINE_START(MAGX_ZN5, "Motorola Zn5")
+        .phys_io        = MXC91231_AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mxc91231_map_io,
+        .init_irq       = mxc91231_init_irq,
+        .timer          = &zn5_timer,
+        .init_machine   = zn5_init,
+MACHINE_END
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
new file mode 100644
index 000000000000..6becda3ff331
--- /dev/null
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2004-2005 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MXC specific definitions
+ *  Copyright 2006 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+/*
+ * This structure defines the MXC memory map.
+ */
+static struct map_desc mxc_io_desc[] __initdata = {
+        {
+                .virtual        = MXC91231_L2CC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_L2CC_BASE_ADDR),
+                .length         = MXC91231_L2CC_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_X_MEMC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_X_MEMC_BASE_ADDR),
+                .length         = MXC91231_X_MEMC_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_ROMP_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_ROMP_BASE_ADDR),
+                .length         = MXC91231_ROMP_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_AVIC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_AVIC_BASE_ADDR),
+                .length         = MXC91231_AVIC_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_AIPS1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_AIPS1_BASE_ADDR),
+                .length         = MXC91231_AIPS1_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_SPBA0_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_SPBA0_BASE_ADDR),
+                .length         = MXC91231_SPBA0_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_SPBA1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_SPBA1_BASE_ADDR),
+                .length         = MXC91231_SPBA1_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_AIPS2_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_AIPS2_BASE_ADDR),
+                .length         = MXC91231_AIPS2_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory map for
+ * the IO modules.
+ */
+void __init mxc91231_map_io(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MXC91231);
+
+        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
+
+void __init mxc91231_init_irq(void)
+{
+        mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
+}
diff --git a/arch/arm/mach-mxc91231/system.c b/arch/arm/mach-mxc91231/system.c
new file mode 100644
index 000000000000..736f7efd874a
--- /dev/null
+++ b/arch/arm/mach-mxc91231/system.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
+ *
+ * This file is released under the GPLv2 or later.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <asm/proc-fns.h>
+#include <mach/hardware.h>
+
+#include "crm_regs.h"
+
+#define WDOG_WCR                MXC91231_IO_ADDRESS(MXC91231_WDOG1_BASE_ADDR)
+#define WDOG_WCR_OUT_ENABLE     (1 << 6)
+#define WDOG_WCR_ASSERT         (1 << 5)
+
+void mxc91231_power_off(void)
+{
+        u16 wcr;
+
+        wcr = __raw_readw(WDOG_WCR);
+        wcr |= WDOG_WCR_OUT_ENABLE;
+        wcr &= ~WDOG_WCR_ASSERT;
+        __raw_writew(wcr, WDOG_WCR);
+}
+
+void mxc91231_arch_reset(char mode, const char *cmd)
+{
+        u32 amcr;
+
+        /* Reset the AP using CRM */
+        amcr = __raw_readl(MXC_CRMAP_AMCR);
+        amcr &= ~MXC_CRMAP_AMCR_SW_AP;
+        __raw_writel(amcr, MXC_CRMAP_AMCR);
+
+        mdelay(10);
+        cpu_reset(0);
+}
+
+void mxc91231_prepare_idle(void)
+{
+        u32 crm_ctl;
+
+        /* Go to WAIT mode after WFI */
+        crm_ctl = __raw_readl(MXC_DSM_CRM_CONTROL);
+        crm_ctl &= ~(MXC_DSM_CRM_CTRL_LPMD0 | MXC_DSM_CRM_CTRL_LPMD1);
+        crm_ctl |=  MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE;
+        __raw_writel(crm_ctl, MXC_DSM_CRM_CONTROL);
+}
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 57e477bd89c6..7e1e721f0324 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -39,7 +39,7 @@ static struct platform_device *sdp4430_devices[] __initdata = {
 };
 
 static struct omap_uart_config sdp4430_uart_config __initdata = {
-        .enabled_uarts  = (1 << 0) | (1 << 1) | (1 << 2),
+        .enabled_uarts  = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3),
 };
 
 static struct omap_lcd_config sdp4430_lcd_config __initdata = {
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index dff5528fbfb5..e26af837510b 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -51,6 +51,7 @@
 
 #define OVERO_GPIO_BT_XGATE     15
 #define OVERO_GPIO_W2W_NRESET   16
+#define OVERO_GPIO_PENDOWN      114
 #define OVERO_GPIO_BT_NRESET    164
 #define OVERO_GPIO_USBH_CPEN    168
 #define OVERO_GPIO_USBH_NRESET  183
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 1d3c93bf86d3..f3c91a1ca391 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -29,9 +29,9 @@
  * These registers appear once per CM module.
  */
 
-#define OMAP3430_CM_REVISION            OMAP_CM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP3430_CM_SYSCONFIG           OMAP_CM_REGADDR(OCP_MOD, 0x0010)
-#define OMAP3430_CM_POLCTRL             OMAP_CM_REGADDR(OCP_MOD, 0x009c)
+#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
 
 #define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
 #define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index a5c0f0435cd6..d49dfb5e931f 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -169,6 +169,42 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
 #define OMAP34XX_MCBSP_PDATA_SZ         0
 #endif
 
+static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
+        {
+                .phys_base      = OMAP44XX_MCBSP1_BASE,
+                .dma_rx_sync    = OMAP44XX_DMA_MCBSP1_RX,
+                .dma_tx_sync    = OMAP44XX_DMA_MCBSP1_TX,
+                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+        },
+        {
+                .phys_base      = OMAP44XX_MCBSP2_BASE,
+                .dma_rx_sync    = OMAP44XX_DMA_MCBSP2_RX,
+                .dma_tx_sync    = OMAP44XX_DMA_MCBSP2_TX,
+                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+        },
+        {
+                .phys_base      = OMAP44XX_MCBSP3_BASE,
+                .dma_rx_sync    = OMAP44XX_DMA_MCBSP3_RX,
+                .dma_tx_sync    = OMAP44XX_DMA_MCBSP3_TX,
+                .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+        },
+        {
+                .phys_base      = OMAP44XX_MCBSP4_BASE,
+                .dma_rx_sync    = OMAP44XX_DMA_MCBSP4_RX,
+                .dma_tx_sync    = OMAP44XX_DMA_MCBSP4_TX,
+                .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+        },
+};
+#define OMAP44XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap44xx_mcbsp_pdata)
+
 static int __init omap2_mcbsp_init(void)
 {
         if (cpu_is_omap2420())
@@ -177,6 +213,8 @@ static int __init omap2_mcbsp_init(void)
                 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
         if (cpu_is_omap34xx())
                 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
+        if (cpu_is_omap44xx())
+                omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
 
         mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
                                                                 GFP_KERNEL);
@@ -192,6 +230,9 @@ static int __init omap2_mcbsp_init(void)
         if (cpu_is_omap34xx())
                 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
                                                 OMAP34XX_MCBSP_PDATA_SZ);
+        if (cpu_is_omap44xx())
+                omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
+                                                OMAP44XX_MCBSP_PDATA_SZ);
 
         return omap_mcbsp_init();
 }
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index f7b3baf76678..21201cd4117b 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -11,9 +11,6 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PM_H
 #define __ARCH_ARM_MACH_OMAP2_PM_H
 
-extern int omap2_pm_init(void);
-extern int omap3_pm_init(void);
-
 #ifdef CONFIG_PM_DEBUG
 extern void omap2_pm_dump(int mode, int resume, unsigned int us);
 extern int omap2_pm_debug;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index db1025562fb0..528dbdc26e23 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -470,7 +470,7 @@ static void __init prcm_setup_regs(void)
                           WKUP_MOD, PM_WKEN);
 }
 
-int __init omap2_pm_init(void)
+static int __init omap2_pm_init(void)
 {
         u32 l;
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 841d4c5ed8be..488d595d8e4b 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -39,7 +39,9 @@
 struct power_state {
         struct powerdomain *pwrdm;
         u32 next_state;
+#ifdef CONFIG_SUSPEND
         u32 saved_state;
+#endif
         struct list_head node;
 };
 
@@ -293,6 +295,9 @@ out:
         local_irq_enable();
 }
 
+#ifdef CONFIG_SUSPEND
+static suspend_state_t suspend_state;
+
 static int omap3_pm_prepare(void)
 {
         disable_hlt();
@@ -321,7 +326,6 @@ static int omap3_pm_suspend(void)
 restore:
         /* Restore next_pwrsts */
         list_for_each_entry(pwrst, &pwrst_list, node) {
-                set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
                 if (state > pwrst->next_state) {
                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
@@ -329,6 +333,7 @@ restore:
                                pwrst->pwrdm->name, pwrst->next_state);
                         ret = -1;
                 }
+                set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
         }
         if (ret)
                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
@@ -339,11 +344,11 @@ restore:
         return ret;
 }
 
-static int omap3_pm_enter(suspend_state_t state)
+static int omap3_pm_enter(suspend_state_t unused)
 {
         int ret = 0;
 
-        switch (state) {
+        switch (suspend_state) {
         case PM_SUSPEND_STANDBY:
         case PM_SUSPEND_MEM:
                 ret = omap3_pm_suspend();
@@ -360,12 +365,30 @@ static void omap3_pm_finish(void)
         enable_hlt();
 }
 
+/* Hooks to enable / disable UART interrupts during suspend */
+static int omap3_pm_begin(suspend_state_t state)
+{
+        suspend_state = state;
+        omap_uart_enable_irqs(0);
+        return 0;
+}
+
+static void omap3_pm_end(void)
+{
+        suspend_state = PM_SUSPEND_ON;
+        omap_uart_enable_irqs(1);
+        return;
+}
+
 static struct platform_suspend_ops omap_pm_ops = {
+        .begin          = omap3_pm_begin,
+        .end            = omap3_pm_end,
         .prepare        = omap3_pm_prepare,
         .enter          = omap3_pm_enter,
         .finish         = omap3_pm_finish,
         .valid          = suspend_valid_only_mem,
 };
+#endif /* CONFIG_SUSPEND */
 
 
 /**
@@ -613,6 +636,24 @@ static void __init prcm_setup_regs(void)
         /* Clear any pending PRCM interrupts */
         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
+        /* Don't attach IVA interrupts */
+        prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
+        prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
+        prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
+        prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
+
+        /* Clear any pending 'reset' flags */
+        prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
+        prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
+
+        /* Clear any pending PRCM interrupts */
+        prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+
         omap3_iva_idle();
         omap3_d2d_idle();
 }
@@ -652,7 +693,7 @@ static int __init clkdms_setup(struct clockdomain *clkdm)
         return 0;
 }
 
-int __init omap3_pm_init(void)
+static int __init omap3_pm_init(void)
 {
         struct power_state *pwrst, *tmp;
         int ret;
@@ -692,7 +733,9 @@ int __init omap3_pm_init(void)
         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
                                          omap34xx_cpu_suspend_sz);
 
+#ifdef CONFIG_SUSPEND
         suspend_set_ops(&omap_pm_ops);
+#endif /* CONFIG_SUSPEND */
 
         pm_idle = omap3_pm_idle;
 
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index b094c15bfe47..ce22344b94e7 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -54,6 +54,7 @@ struct omap_uart_state {
 
         struct plat_serial8250_port *p;
         struct list_head node;
+        struct platform_device pdev;
 
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
         int context_valid;
@@ -68,10 +69,9 @@ struct omap_uart_state {
 #endif
 };
 
-static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
 static LIST_HEAD(uart_list);
 
-static struct plat_serial8250_port serial_platform_data[] = {
+static struct plat_serial8250_port serial_platform_data0[] = {
         {
                 .membase        = IO_ADDRESS(OMAP_UART1_BASE),
                 .mapbase        = OMAP_UART1_BASE,
@@ -81,6 +81,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .regshift       = 2,
                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
         }, {
+                .flags          = 0
+        }
+};
+
+static struct plat_serial8250_port serial_platform_data1[] = {
+        {
                 .membase        = IO_ADDRESS(OMAP_UART2_BASE),
                 .mapbase        = OMAP_UART2_BASE,
                 .irq            = 73,
@@ -89,6 +95,12 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .regshift       = 2,
                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
         }, {
+                .flags          = 0
+        }
+};
+
+static struct plat_serial8250_port serial_platform_data2[] = {
+        {
                 .membase        = IO_ADDRESS(OMAP_UART3_BASE),
                 .mapbase        = OMAP_UART3_BASE,
                 .irq            = 74,
@@ -97,6 +109,16 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .regshift       = 2,
                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
         }, {
+#ifdef CONFIG_ARCH_OMAP4
+                .membase        = IO_ADDRESS(OMAP_UART4_BASE),
+                .mapbase        = OMAP_UART4_BASE,
+                .irq            = 70,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = OMAP24XX_BASE_BAUD * 16,
+        }, {
+#endif
                 .flags          = 0
         }
 };
@@ -217,6 +239,40 @@ static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
         clk_disable(uart->fck);
 }
 
+static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
+{
+        /* Set wake-enable bit */
+        if (uart->wk_en && uart->wk_mask) {
+                u32 v = __raw_readl(uart->wk_en);
+                v |= uart->wk_mask;
+                __raw_writel(v, uart->wk_en);
+        }
+
+        /* Ensure IOPAD wake-enables are set */
+        if (cpu_is_omap34xx() && uart->padconf) {
+                u16 v = omap_ctrl_readw(uart->padconf);
+                v |= OMAP3_PADCONF_WAKEUPENABLE0;
+                omap_ctrl_writew(v, uart->padconf);
+        }
+}
+
+static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
+{
+        /* Clear wake-enable bit */
+        if (uart->wk_en && uart->wk_mask) {
+                u32 v = __raw_readl(uart->wk_en);
+                v &= ~uart->wk_mask;
+                __raw_writel(v, uart->wk_en);
+        }
+
+        /* Ensure IOPAD wake-enables are cleared */
+        if (cpu_is_omap34xx() && uart->padconf) {
+                u16 v = omap_ctrl_readw(uart->padconf);
+                v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
+                omap_ctrl_writew(v, uart->padconf);
+        }
+}
+
 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
                                           int enable)
 {
@@ -246,6 +302,11 @@ static void omap_uart_block_sleep(struct omap_uart_state *uart)
 
 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 {
+        if (device_may_wakeup(&uart->pdev.dev))
+                omap_uart_enable_wakeup(uart);
+        else
+                omap_uart_disable_wakeup(uart);
+
         if (!uart->clocked)
                 return;
 
@@ -292,7 +353,6 @@ void omap_uart_resume_idle(int num)
                         /* Check for normal UART wakeup */
                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
                                 omap_uart_block_sleep(uart);
-
                         return;
                 }
         }
@@ -346,16 +406,13 @@ static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
         return IRQ_NONE;
 }
 
-static u32 sleep_timeout = DEFAULT_TIMEOUT;
-
 static void omap_uart_idle_init(struct omap_uart_state *uart)
 {
-        u32 v;
         struct plat_serial8250_port *p = uart->p;
         int ret;
 
         uart->can_sleep = 0;
-        uart->timeout = sleep_timeout;
+        uart->timeout = DEFAULT_TIMEOUT;
         setup_timer(&uart->timer, omap_uart_idle_timer,
                     (unsigned long) uart);
         mod_timer(&uart->timer, jiffies + uart->timeout);
@@ -413,76 +470,101 @@ static void omap_uart_idle_init(struct omap_uart_state *uart)
                 uart->padconf = 0;
         }
 
-        /* Set wake-enable bit */
-        if (uart->wk_en && uart->wk_mask) {
-                v = __raw_readl(uart->wk_en);
-                v |= uart->wk_mask;
-                __raw_writel(v, uart->wk_en);
-        }
-
-        /* Ensure IOPAD wake-enables are set */
-        if (cpu_is_omap34xx() && uart->padconf) {
-                u16 v;
-
-                v = omap_ctrl_readw(uart->padconf);
-                v |= OMAP3_PADCONF_WAKEUPENABLE0;
-                omap_ctrl_writew(v, uart->padconf);
-        }
-
         p->flags |= UPF_SHARE_IRQ;
         ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
                           "serial idle", (void *)uart);
         WARN_ON(ret);
 }
 
-static ssize_t sleep_timeout_show(struct kobject *kobj,
-                                  struct kobj_attribute *attr,
+void omap_uart_enable_irqs(int enable)
+{
+        int ret;
+        struct omap_uart_state *uart;
+
+        list_for_each_entry(uart, &uart_list, node) {
+                if (enable)
+                        ret = request_irq(uart->p->irq, omap_uart_interrupt,
+                                IRQF_SHARED, "serial idle", (void *)uart);
+                else
+                        free_irq(uart->p->irq, (void *)uart);
+        }
+}
+
+static ssize_t sleep_timeout_show(struct device *dev,
+                                  struct device_attribute *attr,
                                   char *buf)
 {
-        return sprintf(buf, "%u\n", sleep_timeout / HZ);
+        struct platform_device *pdev = container_of(dev,
+                                        struct platform_device, dev);
+        struct omap_uart_state *uart = container_of(pdev,
+                                        struct omap_uart_state, pdev);
+
+        return sprintf(buf, "%u\n", uart->timeout / HZ);
 }
 
-static ssize_t sleep_timeout_store(struct kobject *kobj,
-                                   struct kobj_attribute *attr,
+static ssize_t sleep_timeout_store(struct device *dev,
+                                   struct device_attribute *attr,
                                    const char *buf, size_t n)
 {
-        struct omap_uart_state *uart;
+        struct platform_device *pdev = container_of(dev,
+                                        struct platform_device, dev);
+        struct omap_uart_state *uart = container_of(pdev,
+                                        struct omap_uart_state, pdev);
         unsigned int value;
 
         if (sscanf(buf, "%u", &value) != 1) {
                 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
                 return -EINVAL;
         }
-        sleep_timeout = value * HZ;
-        list_for_each_entry(uart, &uart_list, node) {
-                uart->timeout = sleep_timeout;
-                if (uart->timeout)
-                        mod_timer(&uart->timer, jiffies + uart->timeout);
-                else
-                        /* A zero value means disable timeout feature */
-                        omap_uart_block_sleep(uart);
-        }
+
+        uart->timeout = value * HZ;
+        if (uart->timeout)
+                mod_timer(&uart->timer, jiffies + uart->timeout);
+        else
+                /* A zero value means disable timeout feature */
+                omap_uart_block_sleep(uart);
+
         return n;
 }
 
-static struct kobj_attribute sleep_timeout_attr =
-        __ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
-
+DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
+#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 #else
 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
+#define DEV_CREATE_FILE(dev, attr)
 #endif /* CONFIG_PM */
 
-static struct platform_device serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = serial_platform_data,
+static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
+        {
+                .pdev = {
+                        .name                   = "serial8250",
+                        .id                     = PLAT8250_DEV_PLATFORM,
+                        .dev                    = {
+                                .platform_data  = serial_platform_data0,
+                        },
+                },
+        }, {
+                .pdev = {
+                        .name                   = "serial8250",
+                        .id                     = PLAT8250_DEV_PLATFORM1,
+                        .dev                    = {
+                                .platform_data  = serial_platform_data1,
+                        },
+                },
+        }, {
+                .pdev = {
+                        .name                   = "serial8250",
+                        .id                     = PLAT8250_DEV_PLATFORM2,
+                        .dev                    = {
+                                .platform_data  = serial_platform_data2,
+                        },
+                },
         },
 };
 
 void __init omap_serial_init(void)
 {
-        int i, err;
+        int i;
         const struct omap_uart_config *info;
         char name[16];
 
@@ -496,14 +578,12 @@ void __init omap_serial_init(void)
 
         if (info == NULL)
                 return;
-        if (cpu_is_omap44xx()) {
-                for (i = 0; i < OMAP_MAX_NR_PORTS; i++)
-                        serial_platform_data[i].irq += 32;
-        }
 
         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
-                struct plat_serial8250_port *p = serial_platform_data + i;
                 struct omap_uart_state *uart = &omap_uart[i];
+                struct platform_device *pdev = &uart->pdev;
+                struct device *dev = &pdev->dev;
+                struct plat_serial8250_port *p = dev->platform_data;
 
                 if (!(info->enabled_uarts & (1 << i))) {
                         p->membase = NULL;
@@ -531,20 +611,21 @@ void __init omap_serial_init(void)
                 uart->num = i;
                 p->private_data = uart;
                 uart->p = p;
-                list_add(&uart->node, &uart_list);
+                list_add_tail(&uart->node, &uart_list);
+
+                if (cpu_is_omap44xx())
+                        p->irq += 32;
 
                 omap_uart_enable_clocks(uart);
                 omap_uart_reset(uart);
                 omap_uart_idle_init(uart);
-        }
-
-        err = platform_device_register(&serial_device);
-
-#ifdef CONFIG_PM
-        if (!err)
-                err = sysfs_create_file(&serial_device.dev.kobj,
-                                        &sleep_timeout_attr.attr);
-#endif
 
+                if (WARN_ON(platform_device_register(pdev)))
+                        continue;
+                if ((cpu_is_omap34xx() && uart->padconf) ||
+                    (uart->wk_en && uart->wk_mask)) {
+                        device_init_wakeup(dev, true);
+                        DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
+                }
+        }
 }
-
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 2c7035d8dcbf..5062b05b76b7 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -89,6 +89,20 @@ config MACH_EDMINI_V2
           Say 'Y' here if you want your kernel to support the
           LaCie Ethernet Disk mini V2.
 
+config MACH_D2NET
+        bool "LaCie d2 Network"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie d2 Network NAS.
+
+config MACH_BIGDISK
+        bool "LaCie Big Disk Network"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Big Disk Network NAS.
+
 config MACH_MSS2
         bool "Maxtor Shared Storage II"
         help
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index edc38e2c856f..1db8a3a2708a 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -12,6 +12,8 @@ obj-$(CONFIG_MACH_WRT350N_V2)	+= wrt350n-v2-setup.o
 obj-$(CONFIG_MACH_TS78XX)       += ts78xx-setup.o
 obj-$(CONFIG_MACH_MV2120)       += mv2120-setup.o
 obj-$(CONFIG_MACH_EDMINI_V2)    += edmini_v2-setup.o
+obj-$(CONFIG_MACH_D2NET)        += d2net-setup.o
+obj-$(CONFIG_MACH_BIGDISK)      += d2net-setup.o
 obj-$(CONFIG_MACH_MSS2)         += mss2-setup.o
 obj-$(CONFIG_MACH_WNR854T)      += wnr854t-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_GE)        += rd88f5181l-ge-setup.o
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index d78731edebb6..1a5d6a0e2602 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -84,7 +84,8 @@ static int __init orion5x_cpu_win_can_remap(int win)
         orion5x_pcie_id(&dev, &rev);
         if ((dev == MV88F5281_DEV_ID && win < 4)
             || (dev == MV88F5182_DEV_ID && win < 2)
-            || (dev == MV88F5181_DEV_ID && win < 2))
+            || (dev == MV88F5181_DEV_ID && win < 2)
+            || (dev == MV88F6183_DEV_ID && win < 4))
                 return 1;
 
         return 0;
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
new file mode 100644
index 000000000000..9d4bf763f25b
--- /dev/null
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -0,0 +1,365 @@
+/*
+ * arch/arm/mach-orion5x/d2net-setup.c
+ *
+ * LaCie d2Network and Big Disk Network NAS setup
+ *
+ * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <mach/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * LaCie d2 Network Info
+ ****************************************************************************/
+
+/*
+ * 512KB NOR flash Device bus boot chip select
+ */
+
+#define D2NET_NOR_BOOT_BASE             0xfff80000
+#define D2NET_NOR_BOOT_SIZE             SZ_512K
+
+/*****************************************************************************
+ * 512KB NOR Flash on Boot Device
+ ****************************************************************************/
+
+/*
+ * TODO: Check write support on flash MX29LV400CBTC-70G
+ */
+
+static struct mtd_partition d2net_partitions[] = {
+        {
+                .name           = "Full512kb",
+                .size           = MTDPART_SIZ_FULL,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+};
+
+static struct physmap_flash_data d2net_nor_flash_data = {
+        .width          = 1,
+        .parts          = d2net_partitions,
+        .nr_parts       = ARRAY_SIZE(d2net_partitions),
+};
+
+static struct resource d2net_nor_flash_resource = {
+        .flags                  = IORESOURCE_MEM,
+        .start                  = D2NET_NOR_BOOT_BASE,
+        .end                    = D2NET_NOR_BOOT_BASE
+                                        + D2NET_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device d2net_nor_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &d2net_nor_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &d2net_nor_flash_resource,
+};
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data d2net_eth_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+/*****************************************************************************
+ * I2C devices
+ ****************************************************************************/
+
+/*
+ * i2c addr | chip         | description
+ * 0x32     | Ricoh 5C372b | RTC
+ * 0x3e     | GMT G762     | PWM fan controller
+ * 0x50     | HT24LC08     | eeprom (1kB)
+ *
+ * TODO: Add G762 support to the g760a driver.
+ */
+static struct i2c_board_info __initdata d2net_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("rs5c372b", 0x32),
+        }, {
+                I2C_BOARD_INFO("24c08", 0x50),
+        },
+};
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+
+static struct mv_sata_platform_data d2net_sata_data = {
+        .n_ports        = 2,
+};
+
+#define D2NET_GPIO_SATA0_POWER  3
+#define D2NET_GPIO_SATA1_POWER  12
+
+static void __init d2net_sata_power_init(void)
+{
+        int err;
+
+        err = gpio_request(D2NET_GPIO_SATA0_POWER, "SATA0 power");
+        if (err == 0) {
+                err = gpio_direction_output(D2NET_GPIO_SATA0_POWER, 1);
+                if (err)
+                        gpio_free(D2NET_GPIO_SATA0_POWER);
+        }
+        if (err)
+                pr_err("d2net: failed to configure SATA0 power GPIO\n");
+
+        err = gpio_request(D2NET_GPIO_SATA1_POWER, "SATA1 power");
+        if (err == 0) {
+                err = gpio_direction_output(D2NET_GPIO_SATA1_POWER, 1);
+                if (err)
+                        gpio_free(D2NET_GPIO_SATA1_POWER);
+        }
+        if (err)
+                pr_err("d2net: failed to configure SATA1 power GPIO\n");
+}
+
+/*****************************************************************************
+ * GPIO LED's
+ ****************************************************************************/
+
+/*
+ * The blue front LED is wired to the CPLD and can blink in relation with the
+ * SATA activity. This feature is disabled to make this LED compatible with
+ * the leds-gpio driver: MPP14 and MPP15 are configured to act like output
+ * GPIO's and have to stay in an active state. This is needed to set the blue
+ * LED in a "fix on" state regardless of the SATA activity.
+ *
+ * The following array detail the different LED registers and the combination
+ * of their possible values:
+ *
+ * led_off   | blink_ctrl | SATA active | LED state
+ *           |            |             |
+ *    1      |     x      |      x      |  off
+ *    0      |     0      |      0      |  off
+ *    0      |     1      |      0      |  blink (rate 300ms)
+ *    0      |     x      |      1      |  on
+ *
+ * Notes: The blue and the red front LED's can't be on at the same time.
+ *        Red LED have priority.
+ */
+
+#define D2NET_GPIO_RED_LED              6
+#define D2NET_GPIO_BLUE_LED_BLINK_CTRL  16
+#define D2NET_GPIO_BLUE_LED_OFF         23
+#define D2NET_GPIO_SATA0_ACT            14
+#define D2NET_GPIO_SATA1_ACT            15
+
+static struct gpio_led d2net_leds[] = {
+        {
+                .name = "d2net:blue:power",
+                .gpio = D2NET_GPIO_BLUE_LED_OFF,
+                .active_low = 1,
+        },
+        {
+                .name = "d2net:red:fail",
+                .gpio = D2NET_GPIO_RED_LED,
+        },
+};
+
+static struct gpio_led_platform_data d2net_led_data = {
+        .num_leds = ARRAY_SIZE(d2net_leds),
+        .leds = d2net_leds,
+};
+
+static struct platform_device d2net_gpio_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_led_data,
+        },
+};
+
+static void __init d2net_gpio_leds_init(void)
+{
+        /* Configure GPIO over MPP max number. */
+        orion_gpio_set_valid(D2NET_GPIO_BLUE_LED_OFF, 1);
+
+        if (gpio_request(D2NET_GPIO_SATA0_ACT, "LED SATA0 activity") != 0)
+                return;
+        if (gpio_direction_output(D2NET_GPIO_SATA0_ACT, 1) != 0)
+                goto err_free_1;
+        if (gpio_request(D2NET_GPIO_SATA1_ACT, "LED SATA1 activity") != 0)
+                goto err_free_1;
+        if (gpio_direction_output(D2NET_GPIO_SATA1_ACT, 1) != 0)
+                goto err_free_2;
+        platform_device_register(&d2net_gpio_leds);
+        return;
+
+err_free_2:
+        gpio_free(D2NET_GPIO_SATA1_ACT);
+err_free_1:
+        gpio_free(D2NET_GPIO_SATA0_ACT);
+        return;
+}
+
+/****************************************************************************
+ * GPIO keys
+ ****************************************************************************/
+
+#define D2NET_GPIO_PUSH_BUTTON          18
+#define D2NET_GPIO_POWER_SWITCH_ON      8
+#define D2NET_GPIO_POWER_SWITCH_OFF     9
+
+#define D2NET_SWITCH_POWER_ON           0x1
+#define D2NET_SWITCH_POWER_OFF          0x2
+
+static struct gpio_keys_button d2net_buttons[] = {
+        {
+                .type           = EV_SW,
+                .code           = D2NET_SWITCH_POWER_OFF,
+                .gpio           = D2NET_GPIO_POWER_SWITCH_OFF,
+                .desc           = "Power rocker switch (auto|off)",
+                .active_low     = 0,
+        },
+        {
+                .type           = EV_SW,
+                .code           = D2NET_SWITCH_POWER_ON,
+                .gpio           = D2NET_GPIO_POWER_SWITCH_ON,
+                .desc           = "Power rocker switch (on|auto)",
+                .active_low     = 0,
+        },
+        {
+                .type           = EV_KEY,
+                .code           = KEY_POWER,
+                .gpio           = D2NET_GPIO_PUSH_BUTTON,
+                .desc           = "Front Push Button",
+                .active_low     = 0,
+        },
+};
+
+static struct gpio_keys_platform_data d2net_button_data = {
+        .buttons        = d2net_buttons,
+        .nbuttons       = ARRAY_SIZE(d2net_buttons),
+};
+
+static struct platform_device d2net_gpio_buttons = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_button_data,
+        },
+};
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+
+static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },       /* Board ID (bit 0) */
+        {  1, MPP_GPIO },       /* Board ID (bit 1) */
+        {  2, MPP_GPIO },       /* Board ID (bit 2) */
+        {  3, MPP_GPIO },       /* SATA 0 power */
+        {  4, MPP_UNUSED },
+        {  5, MPP_GPIO },       /* Fan fail detection */
+        {  6, MPP_GPIO },       /* Red front LED */
+        {  7, MPP_UNUSED },
+        {  8, MPP_GPIO },       /* Rear power switch (on|auto) */
+        {  9, MPP_GPIO },       /* Rear power switch (auto|off) */
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_GPIO },       /* SATA 1 power */
+        { 13, MPP_UNUSED },
+        { 14, MPP_GPIO },       /* SATA 0 active */
+        { 15, MPP_GPIO },       /* SATA 1 active */
+        { 16, MPP_GPIO },       /* Blue front LED blink control */
+        { 17, MPP_UNUSED },
+        { 18, MPP_GPIO },       /* Front button (0 = Released, 1 = Pushed ) */
+        { 19, MPP_UNUSED },
+        { -1 }
+        /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
+        /* 23: Blue front LED off */
+        /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */
+};
+
+static void __init d2net_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(d2net_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&d2net_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+
+        d2net_sata_power_init();
+        orion5x_sata_init(&d2net_sata_data);
+
+        orion5x_setup_dev_boot_win(D2NET_NOR_BOOT_BASE,
+                                D2NET_NOR_BOOT_SIZE);
+        platform_device_register(&d2net_nor_flash);
+
+        platform_device_register(&d2net_gpio_buttons);
+
+        d2net_gpio_leds_init();
+
+        pr_notice("d2net: Flash write are not yet supported.\n");
+
+        i2c_register_board_info(0, d2net_i2c_devices,
+                                ARRAY_SIZE(d2net_i2c_devices));
+}
+
+/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
+
+#ifdef CONFIG_MACH_D2NET
+MACHINE_START(D2NET, "LaCie d2 Network")
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = d2net_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_BIGDISK
+MACHINE_START(BIGDISK, "LaCie Big Disk Network")
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = d2net_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
+#endif
+
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index d4cfa2145386..dfc9b0bc6eb2 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -75,7 +75,7 @@ config MACH_REALVIEW_PBX
 
 config REALVIEW_HIGH_PHYS_OFFSET
         bool "High physical base address for the RealView platform"
-        depends on !MACH_REALVIEW_PB1176
+        depends on MMU && !MACH_REALVIEW_PB1176
         default y
         help
           RealView boards other than PB1176 have the RAM available at
diff --git a/arch/arm/mach-realview/include/mach/hardware.h b/arch/arm/mach-realview/include/mach/hardware.h
index b42c14f89acb..8a638d15797f 100644
--- a/arch/arm/mach-realview/include/mach/hardware.h
+++ b/arch/arm/mach-realview/include/mach/hardware.h
@@ -25,6 +25,7 @@
 #include <asm/sizes.h>
 
 /* macro to get at IO space when running virtually */
+#ifdef CONFIG_MMU
 /*
  * Statically mapped addresses:
  *
@@ -33,6 +34,9 @@
  * 1fxx xxxx -> fexx xxxx
  */
 #define IO_ADDRESS(x)           (((x) & 0x03ffffff) + 0xfb000000)
+#else
+#define IO_ADDRESS(x)           (x)
+#endif
 #define __io_address(n)         __io(IO_ADDRESS(n))
 
 #endif
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index ac0e83f1cc3a..a88458b4799d 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -20,6 +20,7 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/localtimer.h>
+#include <asm/unified.h>
 
 #include <mach/board-eb.h>
 #include <mach/board-pb11mp.h>
@@ -137,26 +138,19 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 static void __init poke_milo(void)
 {
-        extern void secondary_startup(void);
-
         /* nobody is to be released from the pen yet */
         pen_release = -1;
 
         /*
-         * write the address of secondary startup into the system-wide
-         * flags register, then clear the bottom two bits, which is what
-         * BootMonitor is waiting for
+         * Write the address of secondary startup into the system-wide flags
+         * register. The BootMonitor waits for this register to become
+         * non-zero.
          */
-#if 1
 #define REALVIEW_SYS_FLAGSS_OFFSET 0x30
-        __raw_writel(virt_to_phys(realview_secondary_startup),
-                     __io_address(REALVIEW_SYS_BASE) +
-                     REALVIEW_SYS_FLAGSS_OFFSET);
 #define REALVIEW_SYS_FLAGSC_OFFSET 0x34
-        __raw_writel(3,
+        __raw_writel(BSYM(virt_to_phys(realview_secondary_startup)),
                      __io_address(REALVIEW_SYS_BASE) +
-                     REALVIEW_SYS_FLAGSC_OFFSET);
-#endif
+                     REALVIEW_SYS_FLAGSS_OFFSET);
 
         mb();
 }
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 03cd27d917b9..b270d6228fe2 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -159,7 +159,9 @@ union offset_union {
 
 #define __get8_unaligned_check(ins,val,addr,err)        \
         __asm__(                                        \
-        "1:     "ins"   %1, [%2], #1\n"                 \
+ ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
+ THUMB( "1:     "ins"   %1, [%2]\n"     )               \
+ THUMB( "       add     %2, %2, #1\n"   )               \
         "2:\n"                                          \
         "       .section .fixup,\"ax\"\n"               \
         "       .align  2\n"                            \
@@ -215,7 +217,9 @@ union offset_union {
         do {                                                    \
                 unsigned int err = 0, v = val, a = addr;        \
                 __asm__( FIRST_BYTE_16                          \
-                "1:     "ins"   %1, [%2], #1\n"                 \
+         ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
+         THUMB( "1:     "ins"   %1, [%2]\n"     )               \
+         THUMB( "       add     %2, %2, #1\n"   )               \
                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
                 "2:     "ins"   %1, [%2]\n"                     \
                 "3:\n"                                          \
@@ -245,11 +249,17 @@ union offset_union {
         do {                                                    \
                 unsigned int err = 0, v = val, a = addr;        \
                 __asm__( FIRST_BYTE_32                          \
-                "1:     "ins"   %1, [%2], #1\n"                 \
+         ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
+         THUMB( "1:     "ins"   %1, [%2]\n"     )               \
+         THUMB( "       add     %2, %2, #1\n"   )               \
                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
-                "2:     "ins"   %1, [%2], #1\n"                 \
+         ARM(   "2:     "ins"   %1, [%2], #1\n" )               \
+         THUMB( "2:     "ins"   %1, [%2]\n"     )               \
+         THUMB( "       add     %2, %2, #1\n"   )               \
                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
-                "3:     "ins"   %1, [%2], #1\n"                 \
+         ARM(   "3:     "ins"   %1, [%2], #1\n" )               \
+         THUMB( "3:     "ins"   %1, [%2]\n"     )               \
+         THUMB( "       add     %2, %2, #1\n"   )               \
                 "       mov     %1, %1, "NEXT_BYTE"\n"          \
                 "4:     "ins"   %1, [%2]\n"                     \
                 "5:\n"                                          \
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index be93ff02a98d..bda0ec31a4e2 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -21,7 +21,7 @@
  *
  *      Flush the whole D-cache.
  *
- *      Corrupted registers: r0-r5, r7, r9-r11
+ *      Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
  *
  *      - mm    - mm_struct describing address space
  */
@@ -51,8 +51,12 @@ loop1:
 loop2:
         mov     r9, r4                          @ create working copy of max way size
 loop3:
-        orr     r11, r10, r9, lsl r5            @ factor way and cache number into r11
-        orr     r11, r11, r7, lsl r2            @ factor index number into r11
+ ARM(   orr     r11, r10, r9, lsl r5    )       @ factor way and cache number into r11
+ THUMB( lsl     r6, r9, r5              )
+ THUMB( orr     r11, r10, r6            )       @ factor way and cache number into r11
+ ARM(   orr     r11, r11, r7, lsl r2    )       @ factor index number into r11
+ THUMB( lsl     r6, r7, r2              )
+ THUMB( orr     r11, r11, r6            )       @ factor index number into r11
         mcr     p15, 0, r11, c7, c14, 2         @ clean & invalidate by set/way
         subs    r9, r9, #1                      @ decrement the way
         bge     loop3
@@ -82,11 +86,13 @@ ENDPROC(v7_flush_dcache_all)
  *
  */
 ENTRY(v7_flush_kern_cache_all)
-        stmfd   sp!, {r4-r5, r7, r9-r11, lr}
+ ARM(   stmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
+ THUMB( stmfd   sp!, {r4-r7, r9-r11, lr}        )
         bl      v7_flush_dcache_all
         mov     r0, #0
         mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
-        ldmfd   sp!, {r4-r5, r7, r9-r11, lr}
+ ARM(   ldmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
+ THUMB( ldmfd   sp!, {r4-r7, r9-r11, lr}        )
         mov     pc, lr
 ENDPROC(v7_flush_kern_cache_all)
 
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 510c179b0ac8..b30925fcbcdc 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -36,7 +36,34 @@
 #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
 #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
 
+static u64 get_coherent_dma_mask(struct device *dev)
+{
+        u64 mask = ISA_DMA_THRESHOLD;
+
+        if (dev) {
+                mask = dev->coherent_dma_mask;
+
+                /*
+                 * Sanity check the DMA mask - it must be non-zero, and
+                 * must be able to be satisfied by a DMA allocation.
+                 */
+                if (mask == 0) {
+                        dev_warn(dev, "coherent DMA mask is unset\n");
+                        return 0;
+                }
+
+                if ((~mask) & ISA_DMA_THRESHOLD) {
+                        dev_warn(dev, "coherent DMA mask %#llx is smaller "
+                                 "than system GFP_DMA mask %#llx\n",
+                                 mask, (unsigned long long)ISA_DMA_THRESHOLD);
+                        return 0;
+                }
+        }
 
+        return mask;
+}
+
+#ifdef CONFIG_MMU
 /*
  * These are the page tables (2MB each) covering uncached, DMA consistent allocations
  */
@@ -152,7 +179,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
         struct page *page;
         struct arm_vm_region *c;
         unsigned long order;
-        u64 mask = ISA_DMA_THRESHOLD, limit;
+        u64 mask = get_coherent_dma_mask(dev);
+        u64 limit;
 
         if (!consistent_pte[0]) {
                 printk(KERN_ERR "%s: not initialised\n", __func__);
@@ -160,25 +188,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
                 return NULL;
         }
 
-        if (dev) {
-                mask = dev->coherent_dma_mask;
-
-                /*
-                 * Sanity check the DMA mask - it must be non-zero, and
-                 * must be able to be satisfied by a DMA allocation.
-                 */
-                if (mask == 0) {
-                        dev_warn(dev, "coherent DMA mask is unset\n");
-                        goto no_page;
-                }
-
-                if ((~mask) & ISA_DMA_THRESHOLD) {
-                        dev_warn(dev, "coherent DMA mask %#llx is smaller "
-                                 "than system GFP_DMA mask %#llx\n",
-                                 mask, (unsigned long long)ISA_DMA_THRESHOLD);
-                        goto no_page;
-                }
-        }
+        if (!mask)
+                goto no_page;
 
         /*
          * Sanity check the allocation size.
@@ -267,6 +278,31 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
         *handle = ~0;
         return NULL;
 }
+#else   /* !CONFIG_MMU */
+static void *
+__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
+            pgprot_t prot)
+{
+        void *virt;
+        u64 mask = get_coherent_dma_mask(dev);
+
+        if (!mask)
+                goto error;
+
+        if (mask != 0xffffffff)
+                gfp |= GFP_DMA;
+        virt = kmalloc(size, gfp);
+        if (!virt)
+                goto error;
+
+        *handle =  virt_to_dma(dev, virt);
+        return virt;
+
+error:
+        *handle = ~0;
+        return NULL;
+}
+#endif  /* CONFIG_MMU */
 
 /*
  * Allocate DMA-coherent memory space and return both the kernel remapped
@@ -311,9 +347,10 @@ EXPORT_SYMBOL(dma_alloc_writecombine);
 static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
                     void *cpu_addr, dma_addr_t dma_addr, size_t size)
 {
+        int ret = -ENXIO;
+#ifdef CONFIG_MMU
         unsigned long flags, user_size, kern_size;
         struct arm_vm_region *c;
-        int ret = -ENXIO;
 
         user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
 
@@ -334,6 +371,7 @@ static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
                                               vma->vm_page_prot);
                 }
         }
+#endif  /* CONFIG_MMU */
 
         return ret;
 }
@@ -358,6 +396,7 @@ EXPORT_SYMBOL(dma_mmap_writecombine);
  * free a page as defined by the above mapping.
  * Must not be called with IRQs disabled.
  */
+#ifdef CONFIG_MMU
 void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle)
 {
         struct arm_vm_region *c;
@@ -444,6 +483,14 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr
                __func__, cpu_addr);
         dump_stack();
 }
+#else   /* !CONFIG_MMU */
+void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle)
+{
+        if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
+                return;
+        kfree(cpu_addr);
+}
+#endif  /* CONFIG_MMU */
 EXPORT_SYMBOL(dma_free_coherent);
 
 /*
@@ -451,10 +498,12 @@ EXPORT_SYMBOL(dma_free_coherent);
  */
 static int __init consistent_init(void)
 {
+        int ret = 0;
+#ifdef CONFIG_MMU
         pgd_t *pgd;
         pmd_t *pmd;
         pte_t *pte;
-        int ret = 0, i = 0;
+        int i = 0;
         u32 base = CONSISTENT_BASE;
 
         do {
@@ -477,6 +526,7 @@ static int __init consistent_init(void)
                 consistent_pte[i++] = pte;
                 base += (1 << PGDIR_SHIFT);
         } while (base < CONSISTENT_END);
+#endif  /* !CONFIG_MMU */
 
         return ret;
 }
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 6fdcbb709827..556c8daf087d 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -16,6 +16,7 @@
 #include <linux/kprobes.h>
 #include <linux/uaccess.h>
 #include <linux/page-flags.h>
+#include <linux/sched.h>
 
 #include <asm/system.h>
 #include <asm/pgtable.h>
@@ -23,6 +24,7 @@
 
 #include "fault.h"
 
+#ifdef CONFIG_MMU
 
 #ifdef CONFIG_KPROBES
 static inline int notify_page_fault(struct pt_regs *regs, unsigned int fsr)
@@ -97,6 +99,10 @@ void show_pte(struct mm_struct *mm, unsigned long addr)
 
         printk("\n");
 }
+#else                                   /* CONFIG_MMU */
+void show_pte(struct mm_struct *mm, unsigned long addr)
+{ }
+#endif                                  /* CONFIG_MMU */
 
 /*
  * Oops.  The kernel tried to access some page that wasn't present.
@@ -171,6 +177,7 @@ void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
                 __do_kernel_fault(mm, addr, fsr, regs);
 }
 
+#ifdef CONFIG_MMU
 #define VM_FAULT_BADMAP         0x010000
 #define VM_FAULT_BADACCESS      0x020000
 
@@ -322,6 +329,13 @@ no_context:
         __do_kernel_fault(mm, addr, fsr, regs);
         return 0;
 }
+#else                                   /* CONFIG_MMU */
+static int
+do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
+{
+        return 0;
+}
+#endif                                  /* CONFIG_MMU */
 
 /*
  * First Level Translation Fault Handler
@@ -340,6 +354,7 @@ no_context:
  * interrupt or a critical region, and should only copy the information
  * from the master page table, nothing more.
  */
+#ifdef CONFIG_MMU
 static int __kprobes
 do_translation_fault(unsigned long addr, unsigned int fsr,
                      struct pt_regs *regs)
@@ -378,6 +393,14 @@ bad_area:
         do_bad_area(addr, fsr, regs);
         return 0;
 }
+#else                                   /* CONFIG_MMU */
+static int
+do_translation_fault(unsigned long addr, unsigned int fsr,
+                     struct pt_regs *regs)
+{
+        return 0;
+}
+#endif                                  /* CONFIG_MMU */
 
 /*
  * Some section permission faults need to be handled gracefully.
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index ad7bacc693b2..900811cc9130 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -12,6 +12,7 @@
 #include <asm/cacheflush.h>
 #include <asm/sections.h>
 #include <asm/page.h>
+#include <asm/setup.h>
 #include <asm/mach/arch.h>
 
 #include "mm.h"
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 54b1f721dec8..f1559c227784 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -77,6 +77,7 @@
  * Sanity check the PTE configuration for the code below - which makes
  * certain assumptions about how these bits are layed out.
  */
+#ifdef CONFIG_MMU
 #if L_PTE_SHARED != PTE_EXT_SHARED
 #error PTE shared bit mismatch
 #endif
@@ -90,6 +91,7 @@
      L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
 #error Invalid Linux PTE bit settings
 #endif
+#endif  /* CONFIG_MMU */
 
 /*
  * The ARMv6 and ARMv7 set_pte_ext translation function.
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 180a08d03a03..f3fa1c32fe92 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -127,7 +127,9 @@ ENDPROC(cpu_v7_switch_mm)
  */
 ENTRY(cpu_v7_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
+ ARM(   str     r1, [r0], #-2048        )       @ linux version
+ THUMB( str     r1, [r0]                )       @ linux version
+ THUMB( sub     r0, r0, #2048           )
 
         bic     r3, r1, #0x000003f0
         bic     r3, r3, #PTE_TYPE_MASK
@@ -232,7 +234,6 @@ __v7_setup:
         mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
         mov     r10, #0x1f                      @ domains 0, 1 = manager
         mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
-#endif
         /*
          * Memory region attributes with SCTLR.TRE=1
          *
@@ -265,6 +266,7 @@ __v7_setup:
         ldr     r6, =0x40e040e0                 @ NMRR
         mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
         mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
+#endif
         adr     r5, v7_crval
         ldmia   r5, {r5, r6}
 #ifdef CONFIG_CPU_ENDIAN_BE8
@@ -273,6 +275,7 @@ __v7_setup:
         mrc     p15, 0, r0, c1, c0, 0           @ read control register
         bic     r0, r0, r5                      @ clear bits them
         orr     r0, r0, r6                      @ set them
+ THUMB( orr     r0, r0, #1 << 30        )       @ Thumb exceptions
         mov     pc, lr                          @ return to head.S:__ret
 ENDPROC(__v7_setup)
 
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 8986b7412235..ca5c7c226341 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -9,6 +9,7 @@ choice
 config ARCH_MX1
         bool "MX1-based"
         select CPU_ARM920T
+        select COMMON_CLKDEV
         help
           This enables support for systems based on the Freescale i.MX1 family
 
@@ -19,6 +20,13 @@ config ARCH_MX2
         help
           This enables support for systems based on the Freescale i.MX2 family
 
+config ARCH_MX25
+        bool "MX25-based"
+        select CPU_ARM926T
+        select COMMON_CLKDEV
+        help
+          This enables support for systems based on the Freescale i.MX25 family
+
 config ARCH_MX3
         bool "MX3-based"
         select CPU_V6
@@ -26,11 +34,20 @@ config ARCH_MX3
         help
           This enables support for systems based on the Freescale i.MX3 family
 
+config ARCH_MXC91231
+        bool "MXC91231-based"
+        select CPU_V6
+        select COMMON_CLKDEV
+        help
+          This enables support for systems based on the Freescale MXC91231 family
+
 endchoice
 
 source "arch/arm/mach-mx1/Kconfig"
 source "arch/arm/mach-mx2/Kconfig"
 source "arch/arm/mach-mx3/Kconfig"
+source "arch/arm/mach-mx25/Kconfig"
+source "arch/arm/mach-mxc91231/Kconfig"
 
 endmenu
 
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 92e13566cd4f..9e8fbd57495c 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -39,6 +39,7 @@
 #include <linux/string.h>
 
 #include <mach/clock.h>
+#include <mach/hardware.h>
 
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
@@ -47,76 +48,6 @@ static DEFINE_MUTEX(clocks_mutex);
  * Standard clock functions defined in include/linux/clk.h
  *-------------------------------------------------------------------------*/
 
-/*
- * All the code inside #ifndef CONFIG_COMMON_CLKDEV can be removed once all
- * MXC architectures have switched to using clkdev.
- */
-#ifndef CONFIG_COMMON_CLKDEV
-/*
- * Retrieve a clock by name.
- *
- * Note that we first try to use device id on the bus
- * and clock name. If this fails, we try to use "<name>.<id>". If this fails,
- * we try to use clock name only.
- * The reference count to the clock's module owner ref count is incremented.
- */
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        struct clk *p, *clk = ERR_PTR(-ENOENT);
-        int idno;
-        const char *str;
-
-        if (id == NULL)
-                return clk;
-
-        if (dev == NULL || dev->bus != &platform_bus_type)
-                idno = -1;
-        else
-                idno = to_platform_device(dev)->id;
-
-        mutex_lock(&clocks_mutex);
-
-        list_for_each_entry(p, &clocks, node) {
-                if (p->id == idno &&
-                    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        goto found;
-                }
-        }
-
-        str = strrchr(id, '.');
-        if (str) {
-                int cnt = str - id;
-                str++;
-                idno = simple_strtol(str, NULL, 10);
-                list_for_each_entry(p, &clocks, node) {
-                        if (p->id == idno &&
-                            strlen(p->name) == cnt &&
-                            strncmp(id, p->name, cnt) == 0 &&
-                            try_module_get(p->owner)) {
-                                clk = p;
-                                goto found;
-                        }
-                }
-        }
-
-        list_for_each_entry(p, &clocks, node) {
-                if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        goto found;
-                }
-        }
-
-        printk(KERN_WARNING "clk: Unable to get requested clock: %s\n", id);
-
-found:
-        mutex_unlock(&clocks_mutex);
-
-        return clk;
-}
-EXPORT_SYMBOL(clk_get);
-#endif
-
 static void __clk_disable(struct clk *clk)
 {
         if (clk == NULL || IS_ERR(clk))
@@ -193,16 +124,6 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
-#ifndef CONFIG_COMMON_CLKDEV
-/* Decrement the clock's module reference count */
-void clk_put(struct clk *clk)
-{
-        if (clk && !IS_ERR(clk))
-                module_put(clk->owner);
-}
-EXPORT_SYMBOL(clk_put);
-#endif
-
 /* Round the requested clock rate to the nearest supported
  * rate that is less than or equal to the requested rate.
  * This is dependent on the clock's current parent.
@@ -265,80 +186,6 @@ struct clk *clk_get_parent(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_parent);
 
-#ifndef CONFIG_COMMON_CLKDEV
-/*
- * Add a new clock to the clock tree.
- */
-int clk_register(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-
-        mutex_lock(&clocks_mutex);
-        list_add(&clk->node, &clocks);
-        mutex_unlock(&clocks_mutex);
-
-        return 0;
-}
-EXPORT_SYMBOL(clk_register);
-
-/* Remove a clock from the clock tree */
-void clk_unregister(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return;
-
-        mutex_lock(&clocks_mutex);
-        list_del(&clk->node);
-        mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clk_unregister);
-
-#ifdef CONFIG_PROC_FS
-static int mxc_clock_read_proc(char *page, char **start, off_t off,
-                                int count, int *eof, void *data)
-{
-        struct clk *clkp;
-        char *p = page;
-        int len;
-
-        list_for_each_entry(clkp, &clocks, node) {
-                p += sprintf(p, "%s-%d:\t\t%lu, %d", clkp->name, clkp->id,
-                                clk_get_rate(clkp), clkp->usecount);
-                if (clkp->parent)
-                        p += sprintf(p, ", %s-%d\n", clkp->parent->name,
-                                     clkp->parent->id);
-                else
-                        p += sprintf(p, "\n");
-        }
-
-        len = (p - page) - off;
-        if (len < 0)
-                len = 0;
-
-        *eof = (len <= count) ? 1 : 0;
-        *start = page + off;
-
-        return len;
-}
-
-static int __init mxc_setup_proc_entry(void)
-{
-        struct proc_dir_entry *res;
-
-        res = create_proc_read_entry("cpu/clocks", 0, NULL,
-                                     mxc_clock_read_proc, NULL);
-        if (!res) {
-                printk(KERN_ERR "Failed to create proc/cpu/clocks\n");
-                return -ENOMEM;
-        }
-        return 0;
-}
-
-late_initcall(mxc_setup_proc_entry);
-#endif /* CONFIG_PROC_FS */
-#endif
-
 /*
  * Get the resulting clock rate from a PLL register value and the input
  * frequency. PLLs with this register layout can at least be found on
@@ -363,12 +210,11 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
 
         mfn_abs = mfn;
 
-#if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21
-        if (mfn >= 0x200) {
-                mfn |= 0xFFFFFE00;
-                mfn_abs = -mfn;
-        }
-#endif
+        /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
+         * 2's complements number
+         */
+        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+                mfn_abs = 0x400 - mfn;
 
         freq *= 2;
         freq /= pd + 1;
@@ -376,8 +222,10 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
         ll = (unsigned long long)freq * mfn_abs;
 
         do_div(ll, mfd + 1);
-        if (mfn < 0)
+
+        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
                 ll = -ll;
+
         ll = (freq * mfi) + ll;
 
         return ll;
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 7506d963be4b..cfc4a8b43e6a 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -29,6 +29,23 @@
 static struct mxc_gpio_port *mxc_gpio_ports;
 static int gpio_table_size;
 
+#define cpu_is_mx1_mx2()        (cpu_is_mx1() || cpu_is_mx2())
+
+#define GPIO_DR         (cpu_is_mx1_mx2() ? 0x1c : 0x00)
+#define GPIO_GDIR       (cpu_is_mx1_mx2() ? 0x00 : 0x04)
+#define GPIO_PSR        (cpu_is_mx1_mx2() ? 0x24 : 0x08)
+#define GPIO_ICR1       (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
+#define GPIO_ICR2       (cpu_is_mx1_mx2() ? 0x2C : 0x10)
+#define GPIO_IMR        (cpu_is_mx1_mx2() ? 0x30 : 0x14)
+#define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
+#define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
+
+#define GPIO_INT_LOW_LEV        (cpu_is_mx1_mx2() ? 0x3 : 0x0)
+#define GPIO_INT_HIGH_LEV       (cpu_is_mx1_mx2() ? 0x2 : 0x1)
+#define GPIO_INT_RISE_EDGE      (cpu_is_mx1_mx2() ? 0x0 : 0x2)
+#define GPIO_INT_FALL_EDGE      (cpu_is_mx1_mx2() ? 0x1 : 0x3)
+#define GPIO_INT_NONE           0x4
+
 /* Note: This driver assumes 32 GPIOs are handled in one register */
 
 static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
@@ -162,7 +179,6 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
         }
 }
 
-#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
 /* MX1 and MX3 has one interrupt *per* gpio port */
 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
@@ -174,9 +190,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 
         mxc_gpio_irq_handler(port, irq_stat);
 }
-#endif
 
-#ifdef CONFIG_ARCH_MX2
 /* MX2 has one interrupt *for all* gpio ports */
 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
@@ -195,7 +209,6 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
                         mxc_gpio_irq_handler(&port[i], irq_stat);
         }
 }
-#endif
 
 static struct irq_chip gpio_irq_chip = {
         .ack = gpio_ack_irq,
@@ -284,17 +297,18 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                 /* its a serious configuration bug when it fails */
                 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
 
-#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
-                /* setup one handler for each entry */
-                set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
-                set_irq_data(port[i].irq, &port[i]);
-#endif
+                if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) {
+                        /* setup one handler for each entry */
+                        set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
+                        set_irq_data(port[i].irq, &port[i]);
+                }
+        }
+
+        if (cpu_is_mx2()) {
+                /* setup one handler for all GPIO interrupts */
+                set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
+                set_irq_data(port[0].irq, port);
         }
 
-#ifdef CONFIG_ARCH_MX2
-        /* setup one handler for all GPIO interrupts */
-        set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
-        set_irq_data(port[0].irq, port);
-#endif
         return 0;
 }
diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
index 8769e910e559..0376c133c9f4 100644
--- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
+++ b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
@@ -12,11 +12,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
 #define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
 
-#include <mach/hardware.h>
-
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
new file mode 100644
index 000000000000..a1fd5830af48
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * Based on board-pcm038.h which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
+#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
+
+#ifndef __ASSEMBLY__
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ * TODO: Add your own baseboard init function and call it from
+ * inside eukrea_cpuimx27_init().
+ *
+ * This example here is for the development board. Refer
+ * eukrea_mbimx27-baseboard.c
+ */
+
+extern void eukrea_mbimx27_baseboard_init(void);
+
+#endif
+
+#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
index 06701df74c42..0cf4fa29510c 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
@@ -15,12 +15,6 @@
 #define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
 
 /*
- * MXC UART EVB board level configurations
- */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPI_IO_ADDRESS(UART1_BASE_ADDR)
-
-/*
  * Memory-mapped I/O on MX21ADS base board
  */
 #define MX21ADS_MMIO_BASE_ADDR   0xF5000000
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
index d42f4e6116f8..7776d230327f 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
@@ -26,12 +26,6 @@
                                 MXC_MAX_VIRTUAL_INTS)
 
 /*
- * MXC UART EVB board level configurations
- */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPI_IO_ADDRESS(UART1_BASE_ADDR)
-
-/*
  * @name Memory Size parameters
  */
 
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
index a870f8ea2443..ea87551d2736 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
@@ -11,9 +11,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__
 #define __ASM_ARCH_MXC_BOARD_MX27LITE_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
index 552b55d714d8..fec1bcfa9164 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
@@ -11,9 +11,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__
 #define __ASM_ARCH_MXC_BOARD_MX27PDK_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 06e6895f7f65..2cbfa35e82ff 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -114,9 +114,4 @@
 
 #define MXC_MAX_EXP_IO_LINES    16
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
index 78cf31e22e4d..eb5a5024622e 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
@@ -22,11 +22,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
 #define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
 
-/* mandatory for CONFIG_LL_DEBUG */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
-
 #ifndef __ASSEMBLY__
 
 enum mx31lilly_boards {
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 52fbdf2d6f26..8e64325d6905 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -11,8 +11,5 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
 #define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
 
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
 
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index 303fd2434a21..d5be6b5a6acf 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -19,11 +19,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
 #define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
-
 #ifndef __ASSEMBLY__
 
 enum mx31moboard_boards {
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
index 519bab3eb28b..2bbd6ed17f50 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
@@ -11,11 +11,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__
 #define __ASM_ARCH_MXC_BOARD_MX31PDK_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 /* Definitions for components on the Debug board */
 
 /* Base address of CPLD controller on the Debug board */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
index 1111037d6d9d..383f1c04df06 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
@@ -19,9 +19,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__
 #define __ASM_ARCH_MXC_BOARD_MX35PDK_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h
index f0a1fa1938a2..13411709b13a 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm037.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm037.h
@@ -19,9 +19,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
 #define __ASM_ARCH_MXC_BOARD_PCM037_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
index 4fcd7499e092..410f9786ed22 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm038.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
@@ -19,11 +19,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
 #define __ASM_ARCH_MXC_BOARD_PCM038_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
-
 #ifndef __ASSEMBLY__
 /*
  * This CPU module needs a baseboard to work. After basic initializing
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/plat-mxc/include/mach/board-pcm043.h
index 15fbdf16abcd..1ac4e1682e5c 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm043.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm043.h
@@ -19,9 +19,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__
 #define __ASM_ARCH_MXC_BOARD_PCM043_H__
 
-/* mandatory for CONFIG_LL_DEBUG */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
index 04033ec637d2..6d88c7af4b23 100644
--- a/arch/arm/plat-mxc/include/mach/board-qong.h
+++ b/arch/arm/plat-mxc/include/mach/board-qong.h
@@ -11,11 +11,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
 #define __ASM_ARCH_MXC_BOARD_QONG_H__
 
-/* mandatory for CONFIG_DEBUG_LL */
-
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
-
 /* NOR FLASH */
 #define QONG_NOR_SIZE           (128*1024*1024)
 
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 02c3cd004db3..286cb9b0a25b 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -16,18 +16,33 @@ struct clk;
 
 extern void mx1_map_io(void);
 extern void mx21_map_io(void);
+extern void mx25_map_io(void);
 extern void mx27_map_io(void);
 extern void mx31_map_io(void);
 extern void mx35_map_io(void);
-extern void mxc_init_irq(void);
-extern void mxc_timer_init(struct clk *timer_clk);
+extern void mxc91231_map_io(void);
+extern void mxc_init_irq(void __iomem *);
+extern void mx1_init_irq(void);
+extern void mx21_init_irq(void);
+extern void mx25_init_irq(void);
+extern void mx27_init_irq(void);
+extern void mx31_init_irq(void);
+extern void mx35_init_irq(void);
+extern void mxc91231_init_irq(void);
+extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
 extern int mx1_clocks_init(unsigned long fref);
 extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
+extern int mx25_clocks_init(unsigned long fref);
 extern int mx27_clocks_init(unsigned long fref);
 extern int mx31_clocks_init(unsigned long fref);
 extern int mx35_clocks_init(void);
+extern int mxc91231_clocks_init(unsigned long fref);
 extern int mxc_register_gpios(void);
 extern int mxc_register_device(struct platform_device *pdev, void *data);
 extern void mxc_set_cpu_type(unsigned int type);
+extern void mxc_arch_reset_init(void __iomem *);
+extern void mxc91231_power_off(void);
+extern void mxc91231_arch_reset(int, const char *);
+extern void mxc91231_prepare_idle(void);
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index bbc5f6753cfb..15b2b148a105 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -11,52 +11,52 @@
  *
  */
 
-#include <mach/hardware.h>
-
-#ifdef CONFIG_MACH_MX31ADS
-#include <mach/board-mx31ads.h>
-#endif
-#ifdef CONFIG_MACH_PCM037
-#include <mach/board-pcm037.h>
-#endif
-#ifdef CONFIG_MACH_MX31LITE
-#include <mach/board-mx31lite.h>
-#endif
-#ifdef CONFIG_MACH_MX27ADS
-#include <mach/board-mx27ads.h>
-#endif
-#ifdef CONFIG_MACH_MX21ADS
-#include <mach/board-mx21ads.h>
+#ifdef CONFIG_ARCH_MX1
+#include <mach/mx1.h>
+#define UART_PADDR      UART1_BASE_ADDR
+#define UART_VADDR      IO_ADDRESS(UART1_BASE_ADDR)
 #endif
-#ifdef CONFIG_MACH_PCM038
-#include <mach/board-pcm038.h>
+
+#ifdef CONFIG_ARCH_MX25
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#ifdef CONFIG_MACH_MX31_3DS
-#include <mach/board-mx31pdk.h>
+#include <mach/mx25.h>
+#define UART_PADDR      UART1_BASE_ADDR
+#define UART_VADDR      MX25_AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif
-#ifdef CONFIG_MACH_QONG
-#include <mach/board-qong.h>
+
+#ifdef CONFIG_ARCH_MX2
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#ifdef CONFIG_MACH_PCM043
-#include <mach/board-pcm043.h>
+#include <mach/mx2x.h>
+#define UART_PADDR      UART1_BASE_ADDR
+#define UART_VADDR      AIPI_IO_ADDRESS(UART1_BASE_ADDR)
 #endif
-#ifdef CONFIG_MACH_MX27_3DS
-#include <mach/board-mx27pdk.h>
+
+#ifdef CONFIG_ARCH_MX3
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#ifdef CONFIG_MACH_ARMADILLO5X0
-#include <mach/board-armadillo5x0.h>
+#include <mach/mx3x.h>
+#define UART_PADDR      UART1_BASE_ADDR
+#define UART_VADDR      AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif
-#ifdef CONFIG_MACH_MX35_3DS
-#include <mach/board-mx35pdk.h>
+
+#ifdef CONFIG_ARCH_MXC91231
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#ifdef CONFIG_MACH_MX27LITE
-#include <mach/board-mx27lite.h>
+#include <mach/mxc91231.h>
+#define UART_PADDR      MXC91231_UART2_BASE_ADDR
+#define UART_VADDR      MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
 #endif
                 .macro  addruart,rx
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
-                ldreq   \rx, =MXC_LL_UART_PADDR @ physical
-                ldrne   \rx, =MXC_LL_UART_VADDR @ virtual
+                ldreq   \rx, =UART_PADDR        @ physical
+                ldrne   \rx, =UART_VADDR        @ virtual
                 .endm
 
                 .macro  senduart,rd,rx
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 5f01d60da845..7cf290efe768 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -18,7 +18,8 @@
         .endm
 
         .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
+        ldr     \base, =avic_base
+        ldr     \base, [\base]
 #ifdef CONFIG_MXC_IRQ_PRIOR
         ldr     r4, [\base, #AVIC_NIMASK]
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 42e4ee37ca1f..78db75475f69 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -42,6 +42,14 @@
 # include <mach/mx1.h>
 #endif
 
+#ifdef CONFIG_ARCH_MX25
+# include <mach/mx25.h>
+#endif
+
+#ifdef CONFIG_ARCH_MXC91231
+# include <mach/mxc91231.h>
+#endif
+
 #include <mach/mxc.h>
 
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h
index 9f0101157ec1..5263506b7ddf 100644
--- a/arch/arm/plat-mxc/include/mach/imxfb.h
+++ b/arch/arm/plat-mxc/include/mach/imxfb.h
@@ -2,6 +2,8 @@
  * This structure describes the machine which we are running on.
  */
 
+#include <linux/fb.h>
+
 #define PCR_TFT         (1 << 31)
 #define PCR_COLOR       (1 << 30)
 #define PCR_PBSIZ_1     (0 << 28)
@@ -13,7 +15,8 @@
 #define PCR_BPIX_4      (2 << 25)
 #define PCR_BPIX_8      (3 << 25)
 #define PCR_BPIX_12     (4 << 25)
-#define PCR_BPIX_16     (4 << 25)
+#define PCR_BPIX_16     (5 << 25)
+#define PCR_BPIX_18     (6 << 25)
 #define PCR_PIXPOL      (1 << 24)
 #define PCR_FLMPOL      (1 << 23)
 #define PCR_LPPOL       (1 << 22)
@@ -46,29 +49,21 @@
 #define DMACR_HM(x)     (((x) & 0xf) << 16)
 #define DMACR_TM(x)     ((x) & 0xf)
 
-struct imx_fb_platform_data {
-        u_long          pixclock;
-
-        u_short         xres;
-        u_short         yres;
-
-        u_int           nonstd;
-        u_char          bpp;
-        u_char          hsync_len;
-        u_char          left_margin;
-        u_char          right_margin;
+struct imx_fb_videomode {
+        struct fb_videomode mode;
+        u32 pcr;
+        unsigned char   bpp;
+};
 
-        u_char          vsync_len;
-        u_char          upper_margin;
-        u_char          lower_margin;
-        u_char          sync;
+struct imx_fb_platform_data {
+        struct imx_fb_videomode *mode;
+        int             num_modes;
 
         u_int           cmap_greyscale:1,
                         cmap_inverse:1,
                         cmap_static:1,
                         unused:29;
 
-        u_int           pcr;
         u_int           pwmr;
         u_int           lscr1;
         u_int           dmacr;
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
new file mode 100644
index 000000000000..810c47f56e77
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -0,0 +1,517 @@
+/*
+ * arch/arm/plat-mxc/include/mach/iomux-mx25.h
+ *
+ * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
+ *
+ * based on arch/arm/mach-mx25/mx25_pins.h
+ *    Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * and
+ * arch/arm/plat-mxc/include/mach/iomux-mx35.h
+ *    Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __IOMUX_MX25_H__
+#define __IOMUX_MX25_H__
+
+#include <mach/iomux-v3.h>
+
+#ifndef GPIO_PORTA
+#error Please include mach/iomux.h
+#endif
+
+/*
+ *
+ * @brief MX25 I/O Pin List
+ *
+ * @ingroup GPIO_MX25
+ */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * IOMUX/PAD Bit field definitions
+ */
+
+#define MX25_PAD_A10__A10               IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A10__GPIO_4_0          IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A13__A13               IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A13__GPIO_4_1          IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A14__A14               IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A14__GPIO_2_0          IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A15__A15               IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A15__GPIO_2_1          IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A16__A16               IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A16__GPIO_2_2          IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A17__A17               IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A17__GPIO_2_3          IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A18__A18               IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A18__GPIO_2_4          IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A18__FEC_COL           IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTL)
+
+#define MX25_PAD_A19__A19               IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A19__FEC_RX_ER         IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTL)
+#define MX25_PAD_A19__GPIO_2_5          IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A20__A20               IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A20__GPIO_2_6          IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A20__FEC_RDATA2        IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTL)
+
+#define MX25_PAD_A21__A21               IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A21__GPIO_2_7          IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A21__FEC_RDATA3        IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTL)
+
+#define MX25_PAD_A22__A22               IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A22__GPIO_2_8          IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A23__A23               IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A23__GPIO_2_9          IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_A24__A24               IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A24__GPIO_2_10         IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A24__FEC_RX_CLK        IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTL)
+
+#define MX25_PAD_A25__A25               IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A25__GPIO_2_11         IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A25__FEC_CRS           IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTL)
+
+#define MX25_PAD_EB0__EB0               IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_EB0__AUD4_TXD          IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
+#define MX25_PAD_EB0__GPIO_2_12         IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_EB1__EB1               IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_EB1__AUD4_RXD          IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL)
+#define MX25_PAD_EB1__GPIO_2_13         IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_OE__OE                 IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_OE__AUD4_TXC           IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_OE__GPIO_2_14          IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CS0__CS0               IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS0__GPIO_4_2          IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CS1__CS1               IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS1__GPIO_4_3          IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CS4__CS4               IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS4__UART5_CTS         IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS4__GPIO_3_20         IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CS5__CS5               IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS5__UART5_RTS         IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS5__GPIO_3_21         IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NF_CE0__NF_CE0         IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_NF_CE0__GPIO_3_22      IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_ECB__ECB               IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_ECB__UART5_TXD_MUX     IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_ECB__GPIO_3_23         IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LBA__LBA               IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LBA__UART5_RXD_MUX     IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL)
+#define MX25_PAD_LBA__GPIO_3_24         IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_BCLK__BCLK             IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BCLK__GPIO_4_4         IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_RW__RW                 IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_RW__AUD4_TXFS          IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL)
+#define MX25_PAD_RW__GPIO_3_25          IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NFWE_B__NFWE_B         IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFWE_B__GPIO_3_26      IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NFRE_B__NFRE_B         IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFRE_B__GPIO_3_27      IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NFALE__NFALE           IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFALE__GPIO_3_28       IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NFCLE__NFCLE           IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFCLE__GPIO_3_29       IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NFWP_B__NFWP_B         IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFWP_B__GPIO_3_30      IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_NFRB__NFRB             IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_NFRB__GPIO_3_31        IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D15__D15               IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D15__LD16              IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D15__GPIO_4_5          IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D14__D14               IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D14__LD17              IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D14__GPIO_4_6          IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D13__D13               IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D13__LD18              IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D13__GPIO_4_7          IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D12__D12               IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D12__GPIO_4_8          IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D11__D11               IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D11__GPIO_4_9          IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D10__D10               IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D10__GPIO_4_10         IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D10__USBOTG_OC         IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP)
+
+#define MX25_PAD_D9__D9                 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D9__GPIO_4_11          IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D9__USBH2_PWR          IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE)
+
+#define MX25_PAD_D8__D8                 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D8__GPIO_4_12          IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D8__USBH2_OC           IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP)
+
+#define MX25_PAD_D7__D7                 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D7__GPIO_4_13          IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D6__D6                 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D6__GPIO_4_14          IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D5__D5                 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D5__GPIO_4_15          IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D4__D4                 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D4__GPIO_4_16          IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D3__D3                 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D3__GPIO_4_17          IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D2__D2                 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D2__GPIO_4_18          IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D1__D1                 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D1__GPIO_4_19          IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_D0__D0                 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D0__GPIO_4_20          IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD0__LD0               IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD0__CSI_D0            IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD0__GPIO_2_15         IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD1__LD1               IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD1__CSI_D1            IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD1__GPIO_2_16         IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD2__LD2               IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD2__GPIO_2_17         IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD3__LD3               IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD3__GPIO_2_18         IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD4__LD4               IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD4__GPIO_2_19         IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD5__LD5               IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD5__GPIO_1_19         IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD6__LD6               IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD6__GPIO_1_20         IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD7__LD7               IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD7__GPIO_1_21         IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LD8__LD8               IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD8__FEC_TX_ERR        IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTL)
+
+#define MX25_PAD_LD9__LD9               IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD9__FEC_COL           IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTL)
+
+#define MX25_PAD_LD10__LD10             IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD10__FEC_RX_ER        IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTL)
+
+#define MX25_PAD_LD11__LD11             IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD11__FEC_RDATA2       IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTL)
+
+#define MX25_PAD_LD12__LD12             IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD12__FEC_RDATA3       IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTL)
+
+#define MX25_PAD_LD13__LD13             IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD13__FEC_TDATA2       IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTL)
+
+#define MX25_PAD_LD14__LD14             IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD14__FEC_TDATA3       IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTL)
+
+#define MX25_PAD_LD15__LD15             IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD15__FEC_RX_CLK       IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTL)
+
+#define MX25_PAD_HSYNC__HSYNC           IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_HSYNC__GPIO_1_22       IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_VSYNC__VSYNC           IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSYNC__GPIO_1_23       IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_LSCLK__LSCLK           IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LSCLK__GPIO_1_24       IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_OE_ACD__OE_ACD         IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_OE_ACD__GPIO_1_25      IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CONTRAST__CONTRAST     IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CONTRAST__FEC_CRS      IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTL)
+
+#define MX25_PAD_PWM__PWM               IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_PWM__GPIO_1_26         IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_PWM__USBH2_OC          IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP)
+
+#define MX25_PAD_CSI_D2__CSI_D2         IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D2__UART5_RXD_MUX  IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D2__GPIO_1_27      IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D3__CSI_D3         IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D3__GPIO_1_28      IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D4__CSI_D4         IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D4__UART5_RTS      IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D4__GPIO_1_29      IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D5__CSI_D5         IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D5__GPIO_1_30      IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D6__CSI_D6         IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D6__GPIO_1_31      IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D7__CSI_D7         IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D7__GPIO_1_6       IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D8__CSI_D8         IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D8__GPIO_1_7       IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_D9__CSI_D9         IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D9__GPIO_4_21      IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_MCLK__CSI_MCLK     IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_MCLK__GPIO_1_8     IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_VSYNC__CSI_VSYNC   IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_VSYNC__GPIO_1_9    IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_HSYNC__CSI_HSYNC   IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_HSYNC__GPIO_1_10   IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_PIXCLK__GPIO_1_11  IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_I2C1_CLK__I2C1_CLK     IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_I2C1_CLK__GPIO_1_12    IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_I2C1_DAT__I2C1_DAT     IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_I2C1_DAT__GPIO_1_13    IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_MOSI__GPIO_1_14  IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_MISO__GPIO_1_15  IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSPI1_SS0__CSPI1_SS0   IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_SS0__GPIO_1_16   IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSPI1_SS1__CSPI1_SS1   IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_SS1__GPIO_1_17   IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_SCLK__GPIO_1_18  IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CSPI1_RDY__CSPI1_RDY   IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_CSPI1_RDY__GPIO_2_22   IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN)
+#define MX25_PAD_UART1_RXD__GPIO_4_22   IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART1_TXD__GPIO_4_23   IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
+#define MX25_PAD_UART1_RTS__CSI_D0      IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL)
+#define MX25_PAD_UART1_RTS__GPIO_4_24   IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
+#define MX25_PAD_UART1_CTS__CSI_D1      IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL)
+#define MX25_PAD_UART1_CTS__GPIO_4_25   IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART2_RXD__UART2_RXD   IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_RXD__GPIO_4_26   IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_TXD__GPIO_4_27   IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART2_RTS__UART2_RTS   IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_RTS__FEC_COL     IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTL)
+#define MX25_PAD_UART2_RTS__GPIO_4_28   IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UART2_CTS__FEC_RX_ER   IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTL)
+#define MX25_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_CTS__GPIO_4_29   IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_SD1_CMD__SD1_CMD       IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_CMD__FEC_RDATA2    IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_CMD__GPIO_2_23     IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_SD1_CLK__SD1_CLK       IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_CLK__FEC_RDATA3    IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_CLK__GPIO_2_24     IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_SD1_DATA0__SD1_DATA0   IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA0__GPIO_2_25   IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_SD1_DATA1__SD1_DATA1   IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA1__AUD7_RXD    IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA1__GPIO_2_26   IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_SD1_DATA2__SD1_DATA2   IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA2__FEC_RX_CLK  IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_DATA2__GPIO_2_27   IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_SD1_DATA3__SD1_DATA3   IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA3__FEC_CRS     IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_DATA3__GPIO_2_28   IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_ROW0__KPP_ROW0     IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW0__GPIO_2_29    IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_ROW1__KPP_ROW1     IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW1__GPIO_2_30    IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_ROW2__KPP_ROW2     IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW2__CSI_D0       IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
+#define MX25_PAD_KPP_ROW2__GPIO_2_31    IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_ROW3__KPP_ROW3     IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW3__CSI_LD1      IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
+#define MX25_PAD_KPP_ROW3__GPIO_3_0     IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_COL0__KPP_COL0     IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL0__GPIO_3_1     IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_COL1__KPP_COL1     IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL1__GPIO_3_2     IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_COL2__KPP_COL2     IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL2__GPIO_3_3     IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_KPP_COL3__KPP_COL3     IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL3__GPIO_3_4     IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_MDC__FEC_MDC       IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_MDC__AUD4_TXD      IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
+#define MX25_PAD_FEC_MDC__GPIO_3_5      IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_MDIO__FEC_MDIO     IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP)
+#define MX25_PAD_FEC_MDIO__AUD4_RXD     IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
+#define MX25_PAD_FEC_MDIO__GPIO_3_6     IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_TDATA0__GPIO_3_7   IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_TDATA1__AUD4_TXFS  IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
+#define MX25_PAD_FEC_TDATA1__GPIO_3_8   IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_TX_EN__FEC_TX_EN   IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_TX_EN__GPIO_3_9    IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
+#define MX25_PAD_FEC_RDATA0__GPIO_3_10  IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
+#define MX25_PAD_FEC_RDATA1__GPIO_3_11  IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_RX_DV__FEC_RX_DV   IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
+#define MX25_PAD_FEC_RX_DV__CAN2_RX     IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
+#define MX25_PAD_FEC_RX_DV__GPIO_3_12   IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN)
+#define MX25_PAD_FEC_TX_CLK__GPIO_3_13  IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_RTCK__RTCK             IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_RTCK__OWIRE            IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_RTCK__GPIO_3_14        IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_DE_B__DE_B             IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_DE_B__GPIO_2_20        IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_TDO__TDO               IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_GPIO_A__GPIO_A         IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_A__CAN1_TX        IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
+#define MX25_PAD_GPIO_A__USBOTG_PWR     IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE)
+
+#define MX25_PAD_GPIO_B__GPIO_B         IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_B__CAN1_RX        IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K)
+#define MX25_PAD_GPIO_B__USBOTG_OC      IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP)
+
+#define MX25_PAD_GPIO_C__GPIO_C         IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_C__CAN2_TX        IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
+
+#define MX25_PAD_GPIO_D__GPIO_D         IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_D__CAN2_RX        IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
+
+#define MX25_PAD_GPIO_E__GPIO_E         IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_E__AUD7_TXD       IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_GPIO_F__GPIO_F         IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_F__AUD7_TXC       IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_EXT_ARMCLK__GPIO_3_15  IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_VSTBY_REQ__VSTBY_REQ   IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSTBY_REQ__AUD7_TXFS   IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSTBY_REQ__GPIO_3_17   IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSTBY_ACK__VSTBY_ACK   IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSTBY_ACK__GPIO_3_18   IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_POWER_FAIL__AUD7_RXD   IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL)
+#define MX25_PAD_POWER_FAIL__GPIO_3_19  IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CLKO__CLKO             IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CLKO__GPIO_2_21        IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BOOT_MODE0__GPIO_4_30  IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BOOT_MODE1__GPIO_4_31  IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL)
+
+#define MX25_PAD_CTL_GRP_DVS_MISC       IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_FEC        IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_JTAG       IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_NFC        IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_CSI        IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_WEIM       IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_DDR        IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_CRM        IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_KPP        IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_SDHC1      IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_LCD        IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_UART       IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_NFC        IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_CSI        IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_CSPI1      IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DDRTYPE        IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_SDHC1      IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_LCD        IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+
+#endif // __ASSEMBLY__
+#endif // __IOMUX_MX25_H__
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 2eb182f73876..446f86763816 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -635,6 +635,19 @@ enum iomux_pins {
 #define MX31_PIN_USBOTG_DIR__USBOTG_DIR        IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBOTG_NXT__USBOTG_NXT        IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBOTG_STP__USBOTG_STP        IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM        IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_MISO__USBH1_RXDP        IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SS0__USBH1_TXDM         IOMUX_MODE(MX31_PIN_CSPI1_SS0,  IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SS1__USBH1_TXDP         IOMUX_MODE(MX31_PIN_CSPI1_SS1,  IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SS2__USBH1_RCV          IOMUX_MODE(MX31_PIN_CSPI1_SS2,  IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SCLK__USBH1_OEB         IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS       IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_USBH2_DATA0__USBH2_DATA0      IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_DATA1__USBH2_DATA1      IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_CLK__USBH2_CLK          IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_DIR__USBH2_DIR          IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_NXT__USBH2_NXT          IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_STP__USBH2_STP          IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USB_OC__GPIO1_30       IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_I2C_DAT__I2C1_SDA      IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_I2C_CLK__I2C1_SCL      IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
@@ -669,6 +682,18 @@ enum iomux_pins {
 #define MX31_PIN_GPIO3_0__GPIO3_0       IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_GPIO3_1__GPIO3_1       IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_TXD2__GPIO1_28         IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_GPIO1_0__GPIO1_0       IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SVEN0__GPIO2_0         IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_STX0__GPIO2_1          IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SRX0__GPIO2_2          IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SIMPD0__GPIO2_3        IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_DTR_DCE1__GPIO2_8      IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_DSR_DCE1__GPIO2_9      IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_RI_DCE1__GPIO2_10      IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_DCD_DCE1__GPIO2_11     IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_STXD5__GPIO1_21       IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SRXD5__GPIO1_22       IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
+
 
 /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
  * cspi1_ss1*/
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
new file mode 100644
index 000000000000..9f13061192c8
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Dmitriy Taychenachev <dimichxp@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __MACH_IOMUX_MXC91231_H__
+#define __MACH_IOMUX_MXC91231_H__
+
+/*
+ * various IOMUX output functions
+ */
+
+#define IOMUX_OCONFIG_GPIO (0 << 4)     /* used as GPIO */
+#define IOMUX_OCONFIG_FUNC (1 << 4)     /* used as function */
+#define IOMUX_OCONFIG_ALT1 (2 << 4)     /* used as alternate function 1 */
+#define IOMUX_OCONFIG_ALT2 (3 << 4)     /* used as alternate function 2 */
+#define IOMUX_OCONFIG_ALT3 (4 << 4)     /* used as alternate function 3 */
+#define IOMUX_OCONFIG_ALT4 (5 << 4)     /* used as alternate function 4 */
+#define IOMUX_OCONFIG_ALT5 (6 << 4)     /* used as alternate function 5 */
+#define IOMUX_OCONFIG_ALT6 (7 << 4)     /* used as alternate function 6 */
+#define IOMUX_ICONFIG_NONE  0           /* not configured for input */
+#define IOMUX_ICONFIG_GPIO  1           /* used as GPIO */
+#define IOMUX_ICONFIG_FUNC  2           /* used as function */
+#define IOMUX_ICONFIG_ALT1  4           /* used as alternate function 1 */
+#define IOMUX_ICONFIG_ALT2  8           /* used as alternate function 2 */
+
+#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
+#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
+#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
+#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
+
+/*
+ * setups a single pin:
+ *      - reserves the pin so that it is not claimed by another driver
+ *      - setups the iomux according to the configuration
+ *      - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
+ */
+int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label);
+/*
+ * setups mutliple pins
+ * convenient way to call the above function with tables
+ */
+int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+                const char *label);
+
+/*
+ * releases a single pin:
+ *      - make it available for a future use by another driver
+ *      - frees the GPIO if the pin was configured as GPIO
+ *      - DOES NOT reconfigure the IOMUX in its reset state
+ */
+void mxc_iomux_release_pin(const unsigned int pin_mode);
+/*
+ * releases multiple pins
+ * convenvient way to call the above function with tables
+ */
+void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count);
+
+#define MUX_SIDE_AP             (0)
+#define MUX_SIDE_SP             (1)
+
+#define MUX_SIDE_SHIFT          (26)
+#define MUX_SIDE_MASK           (0x1 << MUX_SIDE_SHIFT)
+
+#define MUX_GPIO_PORT_SHIFT     (23)
+#define MUX_GPIO_PORT_MASK      (0x7 << MUX_GPIO_PORT_SHIFT)
+
+#define MUX_GPIO_PIN_SHIFT      (20)
+#define MUX_GPIO_PIN_MASK       (0x1f << MUX_GPIO_PIN_SHIFT)
+
+#define MUX_REG_SHIFT           (15)
+#define MUX_REG_MASK            (0x1f << MUX_REG_SHIFT)
+
+#define MUX_FIELD_SHIFT         (13)
+#define MUX_FIELD_MASK          (0x3 << MUX_FIELD_SHIFT)
+
+#define MUX_PADGRP_SHIFT        (8)
+#define MUX_PADGRP_MASK         (0x1f << MUX_PADGRP_SHIFT)
+
+#define MUX_PIN_MASK            (0xffffff << 8)
+
+#define GPIO_PORT_MAX           (3)
+
+#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \
+        (((side) << MUX_SIDE_SHIFT) |             \
+         (gport << MUX_GPIO_PORT_SHIFT) |               \
+         ((gpin) << MUX_GPIO_PIN_SHIFT) |               \
+         ((ctlreg) << MUX_REG_SHIFT) |          \
+         ((ctlfield) << MUX_FIELD_SHIFT) |              \
+         ((padgrp) << MUX_PADGRP_SHIFT))
+
+#define MUX_MODE_OUT_SHIFT      (4)
+#define MUX_MODE_IN_SHIFT       (0)
+#define MUX_MODE_SHIFT          (0)
+#define MUX_MODE_MASK           (0xff << MUX_MODE_SHIFT)
+
+#define IOMUX_MODE(pin, mode) \
+        (pin | (mode << MUX_MODE_SHIFT))
+
+enum iomux_pins {
+        /* AP Side pins */
+        MXC91231_PIN_AP_CLE             = IOMUX_PIN(0, 0,  0,  0, 0, 24),
+        MXC91231_PIN_AP_ALE             = IOMUX_PIN(0, 0,  1,  0, 1, 24),
+        MXC91231_PIN_AP_CE_B            = IOMUX_PIN(0, 0,  2,  0, 2, 24),
+        MXC91231_PIN_AP_RE_B            = IOMUX_PIN(0, 0,  3,  0, 3, 24),
+        MXC91231_PIN_AP_WE_B            = IOMUX_PIN(0, 0,  4,  1, 0, 24),
+        MXC91231_PIN_AP_WP_B            = IOMUX_PIN(0, 0,  5,  1, 1, 24),
+        MXC91231_PIN_AP_BSY_B           = IOMUX_PIN(0, 0,  6,  1, 2, 24),
+        MXC91231_PIN_AP_U1_TXD          = IOMUX_PIN(0, 0,  7,  1, 3, 28),
+        MXC91231_PIN_AP_U1_RXD          = IOMUX_PIN(0, 0,  8,  2, 0, 28),
+        MXC91231_PIN_AP_U1_RTS_B        = IOMUX_PIN(0, 0,  9,  2, 1, 28),
+        MXC91231_PIN_AP_U1_CTS_B        = IOMUX_PIN(0, 0, 10,  2, 2, 28),
+        MXC91231_PIN_AP_AD1_TXD         = IOMUX_PIN(0, 0, 11,  2, 3,  9),
+        MXC91231_PIN_AP_AD1_RXD         = IOMUX_PIN(0, 0, 12,  3, 0,  9),
+        MXC91231_PIN_AP_AD1_TXC         = IOMUX_PIN(0, 0, 13,  3, 1,  9),
+        MXC91231_PIN_AP_AD1_TXFS        = IOMUX_PIN(0, 0, 14,  3, 2,  9),
+        MXC91231_PIN_AP_AD2_TXD         = IOMUX_PIN(0, 0, 15,  3, 3,  9),
+        MXC91231_PIN_AP_AD2_RXD         = IOMUX_PIN(0, 0, 16,  4, 0,  9),
+        MXC91231_PIN_AP_AD2_TXC         = IOMUX_PIN(0, 0, 17,  4, 1,  9),
+        MXC91231_PIN_AP_AD2_TXFS        = IOMUX_PIN(0, 0, 18,  4, 2,  9),
+        MXC91231_PIN_AP_OWDAT           = IOMUX_PIN(0, 0, 19,  4, 3, 28),
+        MXC91231_PIN_AP_IPU_LD17        = IOMUX_PIN(0, 0, 20,  5, 0, 28),
+        MXC91231_PIN_AP_IPU_D3_VSYNC    = IOMUX_PIN(0, 0, 21,  5, 1, 28),
+        MXC91231_PIN_AP_IPU_D3_HSYNC    = IOMUX_PIN(0, 0, 22,  5, 2, 28),
+        MXC91231_PIN_AP_IPU_D3_CLK      = IOMUX_PIN(0, 0, 23,  5, 3, 28),
+        MXC91231_PIN_AP_IPU_D3_DRDY     = IOMUX_PIN(0, 0, 24,  6, 0, 28),
+        MXC91231_PIN_AP_IPU_D3_CONTR    = IOMUX_PIN(0, 0, 25,  6, 1, 28),
+        MXC91231_PIN_AP_IPU_D0_CS       = IOMUX_PIN(0, 0, 26,  6, 2, 28),
+        MXC91231_PIN_AP_IPU_LD16        = IOMUX_PIN(0, 0, 27,  6, 3, 28),
+        MXC91231_PIN_AP_IPU_D2_CS       = IOMUX_PIN(0, 0, 28,  7, 0, 28),
+        MXC91231_PIN_AP_IPU_PAR_RS      = IOMUX_PIN(0, 0, 29,  7, 1, 28),
+        MXC91231_PIN_AP_IPU_D3_PS       = IOMUX_PIN(0, 0, 30,  7, 2, 28),
+        MXC91231_PIN_AP_IPU_D3_CLS      = IOMUX_PIN(0, 0, 31,  7, 3, 28),
+        MXC91231_PIN_AP_IPU_RD          = IOMUX_PIN(0, 1,  0,  8, 0, 28),
+        MXC91231_PIN_AP_IPU_WR          = IOMUX_PIN(0, 1,  1,  8, 1, 28),
+        MXC91231_PIN_AP_IPU_LD0         = IOMUX_PIN(0, 7,  0,  8, 2, 28),
+        MXC91231_PIN_AP_IPU_LD1         = IOMUX_PIN(0, 7,  0,  8, 3, 28),
+        MXC91231_PIN_AP_IPU_LD2         = IOMUX_PIN(0, 7,  0,  9, 0, 28),
+        MXC91231_PIN_AP_IPU_LD3         = IOMUX_PIN(0, 1,  2,  9, 1, 28),
+        MXC91231_PIN_AP_IPU_LD4         = IOMUX_PIN(0, 1,  3,  9, 2, 28),
+        MXC91231_PIN_AP_IPU_LD5         = IOMUX_PIN(0, 1,  4,  9, 3, 28),
+        MXC91231_PIN_AP_IPU_LD6         = IOMUX_PIN(0, 1,  5, 10, 0, 28),
+        MXC91231_PIN_AP_IPU_LD7         = IOMUX_PIN(0, 1,  6, 10, 1, 28),
+        MXC91231_PIN_AP_IPU_LD8         = IOMUX_PIN(0, 1,  7, 10, 2, 28),
+        MXC91231_PIN_AP_IPU_LD9         = IOMUX_PIN(0, 1,  8, 10, 3, 28),
+        MXC91231_PIN_AP_IPU_LD10        = IOMUX_PIN(0, 1,  9, 11, 0, 28),
+        MXC91231_PIN_AP_IPU_LD11        = IOMUX_PIN(0, 1, 10, 11, 1, 28),
+        MXC91231_PIN_AP_IPU_LD12        = IOMUX_PIN(0, 1, 11, 11, 2, 28),
+        MXC91231_PIN_AP_IPU_LD13        = IOMUX_PIN(0, 1, 12, 11, 3, 28),
+        MXC91231_PIN_AP_IPU_LD14        = IOMUX_PIN(0, 1, 13, 12, 0, 28),
+        MXC91231_PIN_AP_IPU_LD15        = IOMUX_PIN(0, 1, 14, 12, 1, 28),
+        MXC91231_PIN_AP_KPROW4          = IOMUX_PIN(0, 7,  0, 12, 2, 10),
+        MXC91231_PIN_AP_KPROW5          = IOMUX_PIN(0, 1, 16, 12, 3, 10),
+        MXC91231_PIN_AP_GPIO_AP_B17     = IOMUX_PIN(0, 1, 17, 13, 0, 10),
+        MXC91231_PIN_AP_GPIO_AP_B18     = IOMUX_PIN(0, 1, 18, 13, 1, 10),
+        MXC91231_PIN_AP_KPCOL3          = IOMUX_PIN(0, 1, 19, 13, 2, 11),
+        MXC91231_PIN_AP_KPCOL4          = IOMUX_PIN(0, 1, 20, 13, 3, 11),
+        MXC91231_PIN_AP_KPCOL5          = IOMUX_PIN(0, 1, 21, 14, 0, 11),
+        MXC91231_PIN_AP_GPIO_AP_B22     = IOMUX_PIN(0, 1, 22, 14, 1, 11),
+        MXC91231_PIN_AP_GPIO_AP_B23     = IOMUX_PIN(0, 1, 23, 14, 2, 11),
+        MXC91231_PIN_AP_CSI_D0          = IOMUX_PIN(0, 1, 24, 14, 3, 21),
+        MXC91231_PIN_AP_CSI_D1          = IOMUX_PIN(0, 1, 25, 15, 0, 21),
+        MXC91231_PIN_AP_CSI_D2          = IOMUX_PIN(0, 1, 26, 15, 1, 21),
+        MXC91231_PIN_AP_CSI_D3          = IOMUX_PIN(0, 1, 27, 15, 2, 21),
+        MXC91231_PIN_AP_CSI_D4          = IOMUX_PIN(0, 1, 28, 15, 3, 21),
+        MXC91231_PIN_AP_CSI_D5          = IOMUX_PIN(0, 1, 29, 16, 0, 21),
+        MXC91231_PIN_AP_CSI_D6          = IOMUX_PIN(0, 1, 30, 16, 1, 21),
+        MXC91231_PIN_AP_CSI_D7          = IOMUX_PIN(0, 1, 31, 16, 2, 21),
+        MXC91231_PIN_AP_CSI_D8          = IOMUX_PIN(0, 2,  0, 16, 3, 21),
+        MXC91231_PIN_AP_CSI_D9          = IOMUX_PIN(0, 2,  1, 17, 0, 21),
+        MXC91231_PIN_AP_CSI_MCLK        = IOMUX_PIN(0, 2,  2, 17, 1, 21),
+        MXC91231_PIN_AP_CSI_VSYNC       = IOMUX_PIN(0, 2,  3, 17, 2, 21),
+        MXC91231_PIN_AP_CSI_HSYNC       = IOMUX_PIN(0, 2,  4, 17, 3, 21),
+        MXC91231_PIN_AP_CSI_PIXCLK      = IOMUX_PIN(0, 2,  5, 18, 0, 21),
+        MXC91231_PIN_AP_I2CLK           = IOMUX_PIN(0, 2,  6, 18, 1, 12),
+        MXC91231_PIN_AP_I2DAT           = IOMUX_PIN(0, 2,  7, 18, 2, 12),
+        MXC91231_PIN_AP_GPIO_AP_C8      = IOMUX_PIN(0, 2,  8, 18, 3,  9),
+        MXC91231_PIN_AP_GPIO_AP_C9      = IOMUX_PIN(0, 2,  9, 19, 0,  9),
+        MXC91231_PIN_AP_GPIO_AP_C10     = IOMUX_PIN(0, 2, 10, 19, 1,  9),
+        MXC91231_PIN_AP_GPIO_AP_C11     = IOMUX_PIN(0, 2, 11, 19, 2,  9),
+        MXC91231_PIN_AP_GPIO_AP_C12     = IOMUX_PIN(0, 2, 12, 19, 3,  9),
+        MXC91231_PIN_AP_GPIO_AP_C13     = IOMUX_PIN(0, 2, 13, 20, 0, 28),
+        MXC91231_PIN_AP_GPIO_AP_C14     = IOMUX_PIN(0, 2, 14, 20, 1, 28),
+        MXC91231_PIN_AP_GPIO_AP_C15     = IOMUX_PIN(0, 2, 15, 20, 2,  9),
+        MXC91231_PIN_AP_GPIO_AP_C16     = IOMUX_PIN(0, 2, 16, 20, 3,  9),
+        MXC91231_PIN_AP_GPIO_AP_C17     = IOMUX_PIN(0, 2, 17, 21, 0,  9),
+        MXC91231_PIN_AP_ED_INT0         = IOMUX_PIN(0, 2, 18, 21, 1, 22),
+        MXC91231_PIN_AP_ED_INT1         = IOMUX_PIN(0, 2, 19, 21, 2, 22),
+        MXC91231_PIN_AP_ED_INT2         = IOMUX_PIN(0, 2, 20, 21, 3, 22),
+        MXC91231_PIN_AP_ED_INT3         = IOMUX_PIN(0, 2, 21, 22, 0, 22),
+        MXC91231_PIN_AP_ED_INT4         = IOMUX_PIN(0, 2, 22, 22, 1, 23),
+        MXC91231_PIN_AP_ED_INT5         = IOMUX_PIN(0, 2, 23, 22, 2, 23),
+        MXC91231_PIN_AP_ED_INT6         = IOMUX_PIN(0, 2, 24, 22, 3, 23),
+        MXC91231_PIN_AP_ED_INT7         = IOMUX_PIN(0, 2, 25, 23, 0, 23),
+        MXC91231_PIN_AP_U2_DSR_B        = IOMUX_PIN(0, 2, 26, 23, 1, 28),
+        MXC91231_PIN_AP_U2_RI_B         = IOMUX_PIN(0, 2, 27, 23, 2, 28),
+        MXC91231_PIN_AP_U2_CTS_B        = IOMUX_PIN(0, 2, 28, 23, 3, 28),
+        MXC91231_PIN_AP_U2_DTR_B        = IOMUX_PIN(0, 2, 29, 24, 0, 28),
+        MXC91231_PIN_AP_KPROW0          = IOMUX_PIN(0, 7,  0, 24, 1, 10),
+        MXC91231_PIN_AP_KPROW1          = IOMUX_PIN(0, 1, 15, 24, 2, 10),
+        MXC91231_PIN_AP_KPROW2          = IOMUX_PIN(0, 7,  0, 24, 3, 10),
+        MXC91231_PIN_AP_KPROW3          = IOMUX_PIN(0, 7,  0, 25, 0, 10),
+        MXC91231_PIN_AP_KPCOL0          = IOMUX_PIN(0, 7,  0, 25, 1, 11),
+        MXC91231_PIN_AP_KPCOL1          = IOMUX_PIN(0, 7,  0, 25, 2, 11),
+        MXC91231_PIN_AP_KPCOL2          = IOMUX_PIN(0, 7,  0, 25, 3, 11),
+
+        /* Shared pins */
+        MXC91231_PIN_SP_U3_TXD          = IOMUX_PIN(1, 3,  0,  0, 0, 28),
+        MXC91231_PIN_SP_U3_RXD          = IOMUX_PIN(1, 3,  1,  0, 1, 28),
+        MXC91231_PIN_SP_U3_RTS_B        = IOMUX_PIN(1, 3,  2,  0, 2, 28),
+        MXC91231_PIN_SP_U3_CTS_B        = IOMUX_PIN(1, 3,  3,  0, 3, 28),
+        MXC91231_PIN_SP_USB_TXOE_B      = IOMUX_PIN(1, 3,  4,  1, 0, 28),
+        MXC91231_PIN_SP_USB_DAT_VP      = IOMUX_PIN(1, 3,  5,  1, 1, 28),
+        MXC91231_PIN_SP_USB_SE0_VM      = IOMUX_PIN(1, 3,  6,  1, 2, 28),
+        MXC91231_PIN_SP_USB_RXD         = IOMUX_PIN(1, 3,  7,  1, 3, 28),
+        MXC91231_PIN_SP_UH2_TXOE_B      = IOMUX_PIN(1, 3,  8,  2, 0, 28),
+        MXC91231_PIN_SP_UH2_SPEED       = IOMUX_PIN(1, 3,  9,  2, 1, 28),
+        MXC91231_PIN_SP_UH2_SUSPEN      = IOMUX_PIN(1, 3, 10,  2, 2, 28),
+        MXC91231_PIN_SP_UH2_TXDP        = IOMUX_PIN(1, 3, 11,  2, 3, 28),
+        MXC91231_PIN_SP_UH2_RXDP        = IOMUX_PIN(1, 3, 12,  3, 0, 28),
+        MXC91231_PIN_SP_UH2_RXDM        = IOMUX_PIN(1, 3, 13,  3, 1, 28),
+        MXC91231_PIN_SP_UH2_OVR         = IOMUX_PIN(1, 3, 14,  3, 2, 28),
+        MXC91231_PIN_SP_UH2_PWR         = IOMUX_PIN(1, 3, 15,  3, 3, 28),
+        MXC91231_PIN_SP_SD1_DAT0        = IOMUX_PIN(1, 3, 16,  4, 0, 25),
+        MXC91231_PIN_SP_SD1_DAT1        = IOMUX_PIN(1, 3, 17,  4, 1, 25),
+        MXC91231_PIN_SP_SD1_DAT2        = IOMUX_PIN(1, 3, 18,  4, 2, 25),
+        MXC91231_PIN_SP_SD1_DAT3        = IOMUX_PIN(1, 3, 19,  4, 3, 25),
+        MXC91231_PIN_SP_SD1_CMD         = IOMUX_PIN(1, 3, 20,  5, 0, 25),
+        MXC91231_PIN_SP_SD1_CLK         = IOMUX_PIN(1, 3, 21,  5, 1, 25),
+        MXC91231_PIN_SP_SD2_DAT0        = IOMUX_PIN(1, 3, 22,  5, 2, 26),
+        MXC91231_PIN_SP_SD2_DAT1        = IOMUX_PIN(1, 3, 23,  5, 3, 26),
+        MXC91231_PIN_SP_SD2_DAT2        = IOMUX_PIN(1, 3, 24,  6, 0, 26),
+        MXC91231_PIN_SP_SD2_DAT3        = IOMUX_PIN(1, 3, 25,  6, 1, 26),
+        MXC91231_PIN_SP_GPIO_SP_A26     = IOMUX_PIN(1, 3, 26,  6, 2, 28),
+        MXC91231_PIN_SP_SPI1_CLK        = IOMUX_PIN(1, 3, 27,  6, 3, 13),
+        MXC91231_PIN_SP_SPI1_MOSI       = IOMUX_PIN(1, 3, 28,  7, 0, 13),
+        MXC91231_PIN_SP_SPI1_MISO       = IOMUX_PIN(1, 3, 29,  7, 1, 13),
+        MXC91231_PIN_SP_SPI1_SS0        = IOMUX_PIN(1, 3, 30,  7, 2, 13),
+        MXC91231_PIN_SP_SPI1_SS1        = IOMUX_PIN(1, 3, 31,  7, 3, 13),
+        MXC91231_PIN_SP_SD2_CMD         = IOMUX_PIN(1, 7,  0,  8, 0, 26),
+        MXC91231_PIN_SP_SD2_CLK         = IOMUX_PIN(1, 7,  0,  8, 1, 26),
+        MXC91231_PIN_SP_SIM1_RST_B      = IOMUX_PIN(1, 2, 30,  8, 2, 28),
+        MXC91231_PIN_SP_SIM1_SVEN       = IOMUX_PIN(1, 7,  0,  8, 3, 28),
+        MXC91231_PIN_SP_SIM1_CLK        = IOMUX_PIN(1, 7,  0,  9, 0, 28),
+        MXC91231_PIN_SP_SIM1_TRXD       = IOMUX_PIN(1, 7,  0,  9, 1, 28),
+        MXC91231_PIN_SP_SIM1_PD         = IOMUX_PIN(1, 2, 31,  9, 2, 28),
+        MXC91231_PIN_SP_UH2_TXDM        = IOMUX_PIN(1, 7,  0,  9, 3, 28),
+        MXC91231_PIN_SP_UH2_RXD         = IOMUX_PIN(1, 7,  0, 10, 0, 28),
+};
+
+#define PIN_AP_MAX      (104)
+#define PIN_SP_MAX      (41)
+
+#define PIN_MAX         (PIN_AP_MAX + PIN_SP_MAX)
+
+/*
+ * Convenience values for use with mxc_iomux_mode()
+ *
+ * Format here is MXC91231_PIN_(pin name)__(function)
+ */
+
+#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \
+        IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC)
+#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \
+        IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC)
+#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \
+        IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1)
+#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \
+        IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1)
+
+
+#endif /* __MACH_IOMUX_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 7cd84547658f..a0fa40265468 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -68,28 +68,24 @@ struct pad_desc {
 /*
  * Use to set PAD control
  */
-#define PAD_CTL_DRIVE_VOLTAGE_3_3_V     0
-#define PAD_CTL_DRIVE_VOLTAGE_1_8_V     1
 
-#define PAD_CTL_NO_HYSTERESIS           0
-#define PAD_CTL_HYSTERESIS              1
+#define PAD_CTL_DVS                     (1 << 13)
+#define PAD_CTL_HYS                     (1 << 8)
 
-#define PAD_CTL_PULL_DISABLED           0x0
-#define PAD_CTL_PULL_KEEPER             0xa
-#define PAD_CTL_PULL_DOWN_100K          0xc
-#define PAD_CTL_PULL_UP_47K             0xd
-#define PAD_CTL_PULL_UP_100K            0xe
-#define PAD_CTL_PULL_UP_22K             0xf
+#define PAD_CTL_PKE                     (1 << 7)
+#define PAD_CTL_PUE                     (1 << 6)
+#define PAD_CTL_PUS_100K_DOWN           (0 << 4)
+#define PAD_CTL_PUS_47K_UP              (1 << 4)
+#define PAD_CTL_PUS_100K_UP             (2 << 4)
+#define PAD_CTL_PUS_22K_UP              (3 << 4)
 
-#define PAD_CTL_OUTPUT_CMOS             0
-#define PAD_CTL_OUTPUT_OPEN_DRAIN       1
+#define PAD_CTL_ODE                     (1 << 3)
 
-#define PAD_CTL_DRIVE_STRENGTH_NORM     0
-#define PAD_CTL_DRIVE_STRENGTH_HIGH     1
-#define PAD_CTL_DRIVE_STRENGTH_MAX      2
+#define PAD_CTL_DSE_STANDARD            (0 << 1)
+#define PAD_CTL_DSE_HIGH                (1 << 1)
+#define PAD_CTL_DSE_MAX                 (2 << 1)
 
-#define PAD_CTL_SLEW_RATE_SLOW          0
-#define PAD_CTL_SLEW_RATE_FAST          1
+#define PAD_CTL_SRE_FAST                (1 << 0)
 
 /*
  * setups a single pad:
@@ -117,5 +113,10 @@ void mxc_iomux_v3_release_pad(struct pad_desc *pad);
  */
 void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
 
+/*
+ * Initialise the iomux controller
+ */
+void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
+
 #endif /* __MACH_IOMUX_V3_H__*/
 
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
index 171f8adc1109..6d49f8ae3259 100644
--- a/arch/arm/plat-mxc/include/mach/iomux.h
+++ b/arch/arm/plat-mxc/include/mach/iomux.h
@@ -49,6 +49,9 @@
 #ifdef CONFIG_ARCH_MX2
 # define GPIO_PORT_MAX  5
 #endif
+#ifdef CONFIG_ARCH_MX25
+# define GPIO_PORT_MAX  3
+#endif
 
 #ifndef GPIO_PORT_MAX
 # error "GPIO config port count unknown!"
@@ -107,6 +110,9 @@
 #include <mach/iomux-mx27.h>
 #endif
 #endif
+#ifdef CONFIG_ARCH_MX25
+#include <mach/iomux-mx25.h>
+#endif
 
 
 /* decode irq number to use with IMR(x), ISR(x) and friends */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 518a36504b88..ead9d592168d 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -24,6 +24,10 @@
 #define MXC_GPIO_IRQS           (32 * 6)
 #elif defined CONFIG_ARCH_MX3
 #define MXC_GPIO_IRQS           (32 * 3)
+#elif defined CONFIG_ARCH_MX25
+#define MXC_GPIO_IRQS           (32 * 4)
+#elif defined CONFIG_ARCH_MXC91231
+#define MXC_GPIO_IRQS           (32 * 4)
 #endif
 
 /*
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 6065e00176ed..d3afafdcc0e5 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -22,6 +22,10 @@
 #endif
 #elif defined CONFIG_ARCH_MX3
 #define PHYS_OFFSET             UL(0x80000000)
+#elif defined CONFIG_ARCH_MX25
+#define PHYS_OFFSET             UL(0x80000000)
+#elif defined CONFIG_ARCH_MXC91231
+#define PHYS_OFFSET             UL(0x90000000)
 #endif
 
 #if defined(CONFIG_MX1_VIDEO)
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 1000bf330bcd..1b2890a5c452 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -12,10 +12,6 @@
 #ifndef __ASM_ARCH_MXC_MX1_H__
 #define __ASM_ARCH_MXC_MX1_H__
 
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
 #include <mach/vmalloc.h>
 
 /*
@@ -138,20 +134,6 @@
 #define GPIO_INT_PORTD          62
 #define WDT_INT                 63
 
-/* gpio and gpio based interrupt handling */
-#define GPIO_DR                 0x1C
-#define GPIO_GDIR               0x00
-#define GPIO_PSR                0x24
-#define GPIO_ICR1               0x28
-#define GPIO_ICR2               0x2C
-#define GPIO_IMR                0x30
-#define GPIO_ISR                0x34
-#define GPIO_INT_LOW_LEV        0x3
-#define GPIO_INT_HIGH_LEV       0x2
-#define GPIO_INT_RISE_EDGE      0x0
-#define GPIO_INT_FALL_EDGE      0x1
-#define GPIO_INT_NONE           0x4
-
 /* DMA */
 #define DMA_REQ_UART3_T         2
 #define DMA_REQ_UART3_R         3
@@ -179,8 +161,4 @@
 #define DMA_REQ_UART1_T         30
 #define DMA_REQ_UART1_R         31
 
-/* mandatory for CONFIG_DEBUG_LL */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       IO_ADDRESS(UART1_BASE_ADDR)
-
 #endif /*  __ASM_ARCH_MXC_MX1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 8b070a041a99..21112c695ec5 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -25,11 +25,6 @@
 #ifndef __ASM_ARCH_MXC_MX21_H__
 #define __ASM_ARCH_MXC_MX21_H__
 
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
-
 /* Memory regions and CS */
 #define SDRAM_BASE_ADDR         0xC0000000
 #define CSD1_BASE_ADDR          0xC4000000
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
new file mode 100644
index 000000000000..ec64bd9a8ab1
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -0,0 +1,44 @@
+#ifndef __MACH_MX25_H__
+#define __MACH_MX25_H__
+
+#define MX25_AIPS1_BASE_ADDR            0x43F00000
+#define MX25_AIPS1_BASE_ADDR_VIRT       0xFC000000
+#define MX25_AIPS1_SIZE                 SZ_1M
+#define MX25_AIPS2_BASE_ADDR            0x53F00000
+#define MX25_AIPS2_BASE_ADDR_VIRT       0xFC200000
+#define MX25_AIPS2_SIZE                 SZ_1M
+#define MX25_AVIC_BASE_ADDR             0x68000000
+#define MX25_AVIC_BASE_ADDR_VIRT        0xFC400000
+#define MX25_AVIC_SIZE                  SZ_1M
+
+#define MX25_IOMUXC_BASE_ADDR           (MX25_AIPS1_BASE_ADDR + 0xac000)
+
+#define MX25_CRM_BASE_ADDR              (MX25_AIPS2_BASE_ADDR + 0x80000)
+#define MX25_GPT1_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0x90000)
+#define MX25_WDOG_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xdc000)
+
+#define MX25_GPIO1_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
+#define MX25_GPIO2_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
+#define MX25_GPIO3_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
+#define MX25_GPIO4_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
+
+#define MX25_AIPS1_IO_ADDRESS(x)  \
+        (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
+#define MX25_AIPS2_IO_ADDRESS(x)  \
+        (((x) - MX25_AIPS2_BASE_ADDR) + MX25_AIPS2_BASE_ADDR_VIRT)
+#define MX25_AVIC_IO_ADDRESS(x)  \
+        (((x) - MX25_AVIC_BASE_ADDR) + MX25_AVIC_BASE_ADDR_VIRT)
+
+#define __in_range(addr, name)  ((addr) >= name##_BASE_ADDR && (addr) < name##_BASE_ADDR + name##_SIZE)
+
+#define MX25_IO_ADDRESS(x)                                      \
+        (void __force __iomem *)                                \
+        (__in_range(x, MX25_AIPS1) ? MX25_AIPS1_IO_ADDRESS(x) : \
+        __in_range(x, MX25_AIPS2) ? MX25_AIPS2_IO_ADDRESS(x) :  \
+        __in_range(x, MX25_AVIC) ? MX25_AVIC_IO_ADDRESS(x) :    \
+        0xDEADBEEF)
+
+#define UART1_BASE_ADDR                 0x43f90000
+#define UART2_BASE_ADDR                 0x43f94000
+
+#endif /* __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 6e93f2c0b7bb..dc3ad9aa952a 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -24,10 +24,6 @@
 #ifndef __ASM_ARCH_MXC_MX27_H__
 #define __ASM_ARCH_MXC_MX27_H__
 
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
 /* IRAM */
 #define IRAM_BASE_ADDR          0xFFFF4C00      /* internal ram */
 
@@ -120,7 +116,4 @@ extern int mx27_revision(void);
 
 /* Mandatory defines used globally */
 
-/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
-#define ARCH_NR_GPIOS           (192 + 16)
-
 #endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index fc40d3ab8c5b..db5d921e0fe6 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -23,10 +23,6 @@
 #ifndef __ASM_ARCH_MXC_MX2x_H__
 #define __ASM_ARCH_MXC_MX2x_H__
 
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
 /* The following addresses are common between i.MX21 and i.MX27 */
 
 /* Register offests */
@@ -154,20 +150,6 @@
 #define MXC_INT_GPIO            8
 #define MXC_INT_CSPI3           6
 
-/* gpio and gpio based interrupt handling */
-#define GPIO_DR                 0x1C
-#define GPIO_GDIR               0x00
-#define GPIO_PSR                0x24
-#define GPIO_ICR1               0x28
-#define GPIO_ICR2               0x2C
-#define GPIO_IMR                0x30
-#define GPIO_ISR                0x34
-#define GPIO_INT_LOW_LEV        0x3
-#define GPIO_INT_HIGH_LEV       0x2
-#define GPIO_INT_RISE_EDGE      0x0
-#define GPIO_INT_FALL_EDGE      0x1
-#define GPIO_INT_NONE           0x4
-
 /* fixed DMA request numbers */
 #define DMA_REQ_CSI_RX          31
 #define DMA_REQ_CSI_STAT        30
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 0b06941b6139..14ac0dcc82f4 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -4,7 +4,7 @@
 #define MX31_IRAM_BASE_ADDR             0x1FFC0000      /* internal ram */
 #define MX31_IRAM_SIZE                  SZ_16K
 
-#define OTG_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00088000)
+#define MX31_OTG_BASE_ADDR      (AIPS1_BASE_ADDR + 0x00088000)
 #define ATA_BASE_ADDR           (AIPS1_BASE_ADDR + 0x0008C000)
 #define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B0000)
 #define UART5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B4000)
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 6465fefb42e3..ab4cfec6c8ab 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -5,6 +5,7 @@
 #define MX35_IRAM_SIZE          SZ_128K
 
 #define MXC_FEC_BASE_ADDR       0x50038000
+#define MX35_OTG_BASE_ADDR      0x53ff4000
 #define MX35_NFC_BASE_ADDR      0xBB000000
 
 /*
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index b559a4bb5769..009f4440276b 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -11,10 +11,6 @@
 #ifndef __ASM_ARCH_MXC_MX31_H__
 #define __ASM_ARCH_MXC_MX31_H__
 
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
-
 /*
  * MX31 memory map:
  *
@@ -263,25 +259,8 @@
 #define SYSTEM_REV_MIN          CHIP_REV_1_0
 #define SYSTEM_REV_NUM          3
 
-/* gpio and gpio based interrupt handling */
-#define GPIO_DR                 0x00
-#define GPIO_GDIR               0x04
-#define GPIO_PSR                0x08
-#define GPIO_ICR1               0x0C
-#define GPIO_ICR2               0x10
-#define GPIO_IMR                0x14
-#define GPIO_ISR                0x18
-#define GPIO_INT_LOW_LEV        0x0
-#define GPIO_INT_HIGH_LEV       0x1
-#define GPIO_INT_RISE_EDGE      0x2
-#define GPIO_INT_FALL_EDGE      0x3
-#define GPIO_INT_NONE           0x4
-
 /* Mandatory defines used globally */
 
-/* this CPU supports up to 96 GPIOs */
-#define ARCH_NR_GPIOS           96
-
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 
 extern unsigned int system_rev;
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 5fa2a07f4eaf..51990536b845 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -26,9 +26,11 @@
 
 #define MXC_CPU_MX1             1
 #define MXC_CPU_MX21            21
+#define MXC_CPU_MX25            25
 #define MXC_CPU_MX27            27
 #define MXC_CPU_MX31            31
 #define MXC_CPU_MX35            35
+#define MXC_CPU_MXC91231        91231
 
 #ifndef __ASSEMBLY__
 extern unsigned int __mxc_cpu_type;
@@ -58,6 +60,18 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx21()          (0)
 #endif
 
+#ifdef CONFIG_ARCH_MX25
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MX25
+# endif
+# define cpu_is_mx25()          (mxc_cpu_type == MXC_CPU_MX25)
+#else
+# define cpu_is_mx25()          (0)
+#endif
+
 #ifdef CONFIG_MACH_MX27
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
@@ -94,13 +108,25 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx35()          (0)
 #endif
 
+#ifdef CONFIG_ARCH_MXC91231
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MXC91231
+# endif
+# define cpu_is_mxc91231()      (mxc_cpu_type == MXC_CPU_MXC91231)
+#else
+# define cpu_is_mxc91231()      (0)
+#endif
+
 #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
 #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10)
 #define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4)
 #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8)
 #endif
 
-#define cpu_is_mx3()    (cpu_is_mx31() || cpu_is_mx35())
+#define cpu_is_mx3()    (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
 #define cpu_is_mx2()    (cpu_is_mx21() || cpu_is_mx27())
 
 #endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
new file mode 100644
index 000000000000..81484d1ef232
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -0,0 +1,315 @@
+/*
+ *  Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - Platform specific register memory map
+ *
+ *  Copyright 2005-2007 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __MACH_MXC91231_H__
+#define __MACH_MXC91231_H__
+
+/*
+ * L2CC
+ */
+#define MXC91231_L2CC_BASE_ADDR         0x30000000
+#define MXC91231_L2CC_BASE_ADDR_VIRT    0xF9000000
+#define MXC91231_L2CC_SIZE              SZ_64K
+
+/*
+ * AIPS 1
+ */
+#define MXC91231_AIPS1_BASE_ADDR        0x43F00000
+#define MXC91231_AIPS1_BASE_ADDR_VIRT   0xFC000000
+#define MXC91231_AIPS1_SIZE             SZ_1M
+
+#define MXC91231_AIPS1_CTRL_BASE_ADDR   MXC91231_AIPS1_BASE_ADDR
+#define MXC91231_MAX_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x04000)
+#define MXC91231_EVTMON_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0x08000)
+#define MXC91231_CLKCTL_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0x0C000)
+#define MXC91231_ETB_SLOT4_BASE_ADDR    (MXC91231_AIPS1_BASE_ADDR + 0x10000)
+#define MXC91231_ETB_SLOT5_BASE_ADDR    (MXC91231_AIPS1_BASE_ADDR + 0x14000)
+#define MXC91231_ECT_CTIO_BASE_ADDR     (MXC91231_AIPS1_BASE_ADDR + 0x18000)
+#define MXC91231_I2C_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x80000)
+#define MXC91231_MU_BASE_ADDR           (MXC91231_AIPS1_BASE_ADDR + 0x88000)
+#define MXC91231_UART1_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x90000)
+#define MXC91231_UART2_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x94000)
+#define MXC91231_DSM_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x98000)
+#define MXC91231_OWIRE_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x9C000)
+#define MXC91231_SSI1_BASE_ADDR         (MXC91231_AIPS1_BASE_ADDR + 0xA0000)
+#define MXC91231_KPP_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0xA8000)
+#define MXC91231_IOMUX_AP_BASE_ADDR     (MXC91231_AIPS1_BASE_ADDR + 0xAC000)
+#define MXC91231_CTI_AP_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0xB8000)
+
+/*
+ * AIPS 2
+ */
+#define MXC91231_AIPS2_BASE_ADDR        0x53F00000
+#define MXC91231_AIPS2_BASE_ADDR_VIRT   0xFC100000
+#define MXC91231_AIPS2_SIZE             SZ_1M
+
+#define MXC91231_GEMK_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
+#define MXC91231_GPT1_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0x90000)
+#define MXC91231_EPIT1_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0x94000)
+#define MXC91231_SCC_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xAC000)
+#define MXC91231_RNGA_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xB0000)
+#define MXC91231_IPU_CTRL_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xC0000)
+#define MXC91231_AUDMUX_BASE_ADDR       (MXC91231_AIPS2_BASE_ADDR + 0xC4000)
+#define MXC91231_EDIO_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xC8000)
+#define MXC91231_GPIO1_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xCC000)
+#define MXC91231_GPIO2_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xD0000)
+#define MXC91231_SDMA_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xD4000)
+#define MXC91231_RTC_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xD8000)
+#define MXC91231_WDOG1_BASE_ADDR        (MXC91231_AIPS2_BASE_ADDR + 0xDC000)
+#define MXC91231_PWM_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xE0000)
+#define MXC91231_GPIO3_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xE4000)
+#define MXC91231_WDOG2_BASE_ADDR        (MXC91231_AIPS2_BASE_ADDR + 0xE8000)
+#define MXC91231_RTIC_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xEC000)
+#define MXC91231_LPMC_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xF0000)
+
+/*
+ * SPBA global module 0
+ */
+#define MXC91231_SPBA0_BASE_ADDR        0x50000000
+#define MXC91231_SPBA0_BASE_ADDR_VIRT   0xFC200000
+#define MXC91231_SPBA0_SIZE             SZ_1M
+
+#define MXC91231_MMC_SDHC1_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x04000)
+#define MXC91231_MMC_SDHC2_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x08000)
+#define MXC91231_UART3_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x0C000)
+#define MXC91231_CSPI2_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x10000)
+#define MXC91231_SSI2_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x14000)
+#define MXC91231_SIM_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x18000)
+#define MXC91231_IIM_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x1C000)
+#define MXC91231_CTI_SDMA_BASE_ADDR     (MXC91231_SPBA0_BASE_ADDR + 0x20000)
+#define MXC91231_USBOTG_CTRL_BASE_ADDR  (MXC91231_SPBA0_BASE_ADDR + 0x24000)
+#define MXC91231_USBOTG_DATA_BASE_ADDR  (MXC91231_SPBA0_BASE_ADDR + 0x28000)
+#define MXC91231_CSPI1_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x30000)
+#define MXC91231_SPBA_CTRL_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x3C000)
+#define MXC91231_IOMUX_COM_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x40000)
+#define MXC91231_CRM_COM_BASE_ADDR      (MXC91231_SPBA0_BASE_ADDR + 0x44000)
+#define MXC91231_CRM_AP_BASE_ADDR       (MXC91231_SPBA0_BASE_ADDR + 0x48000)
+#define MXC91231_PLL0_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x4C000)
+#define MXC91231_PLL1_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x50000)
+#define MXC91231_PLL2_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x54000)
+#define MXC91231_GPIO4_SH_BASE_ADDR     (MXC91231_SPBA0_BASE_ADDR + 0x58000)
+#define MXC91231_HAC_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
+#define MXC91231_SAHARA_BASE_ADDR       (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
+#define MXC91231_PLL3_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x60000)
+
+/*
+ * SPBA global module 1
+ */
+#define MXC91231_SPBA1_BASE_ADDR        0x52000000
+#define MXC91231_SPBA1_BASE_ADDR_VIRT   0xFC300000
+#define MXC91231_SPBA1_SIZE             SZ_1M
+
+#define MXC91231_MQSPI_BASE_ADDR        (MXC91231_SPBA1_BASE_ADDR + 0x34000)
+#define MXC91231_EL1T_BASE_ADDR         (MXC91231_SPBA1_BASE_ADDR + 0x38000)
+
+/*!
+ * Defines for SPBA modules
+ */
+#define MXC91231_SPBA_SDHC1             0x04
+#define MXC91231_SPBA_SDHC2             0x08
+#define MXC91231_SPBA_UART3             0x0C
+#define MXC91231_SPBA_CSPI2             0x10
+#define MXC91231_SPBA_SSI2              0x14
+#define MXC91231_SPBA_SIM               0x18
+#define MXC91231_SPBA_IIM               0x1C
+#define MXC91231_SPBA_CTI_SDMA          0x20
+#define MXC91231_SPBA_USBOTG_CTRL_REGS  0x24
+#define MXC91231_SPBA_USBOTG_DATA_REGS  0x28
+#define MXC91231_SPBA_CSPI1             0x30
+#define MXC91231_SPBA_MQSPI             0x34
+#define MXC91231_SPBA_EL1T              0x38
+#define MXC91231_SPBA_IOMUX             0x40
+#define MXC91231_SPBA_CRM_COM           0x44
+#define MXC91231_SPBA_CRM_AP            0x48
+#define MXC91231_SPBA_PLL0              0x4C
+#define MXC91231_SPBA_PLL1              0x50
+#define MXC91231_SPBA_PLL2              0x54
+#define MXC91231_SPBA_GPIO4             0x58
+#define MXC91231_SPBA_SAHARA            0x5C
+
+/*
+ * ROMP and AVIC
+ */
+#define MXC91231_ROMP_BASE_ADDR         0x60000000
+#define MXC91231_ROMP_BASE_ADDR_VIRT    0xFC400000
+#define MXC91231_ROMP_SIZE              SZ_64K
+
+#define MXC91231_AVIC_BASE_ADDR         0x68000000
+#define MXC91231_AVIC_BASE_ADDR_VIRT    0xFC410000
+#define MXC91231_AVIC_SIZE              SZ_64K
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define MXC91231_X_MEMC_BASE_ADDR       0xB8000000
+#define MXC91231_X_MEMC_BASE_ADDR_VIRT  0xFC420000
+#define MXC91231_X_MEMC_SIZE            SZ_64K
+
+#define MXC91231_NFC_BASE_ADDR          (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
+#define MXC91231_ESDCTL_BASE_ADDR       (MXC91231_X_MEMC_BASE_ADDR + 0x1000)
+#define MXC91231_WEIM_BASE_ADDR         (MXC91231_X_MEMC_BASE_ADDR + 0x2000)
+#define MXC91231_M3IF_BASE_ADDR         (MXC91231_X_MEMC_BASE_ADDR + 0x3000)
+#define MXC91231_EMI_CTL_BASE_ADDR      (MXC91231_X_MEMC_BASE_ADDR + 0x4000)
+
+/*
+ * Memory regions and CS
+ * CPLD is connected on CS4
+ * CS5 is TP1021 or it is not connected
+ * */
+#define MXC91231_FB_RAM_BASE_ADDR       0x78000000
+#define MXC91231_FB_RAM_SIZE            SZ_256K
+#define MXC91231_CSD0_BASE_ADDR         0x80000000
+#define MXC91231_CSD1_BASE_ADDR         0x90000000
+#define MXC91231_CS0_BASE_ADDR          0xA0000000
+#define MXC91231_CS1_BASE_ADDR          0xA8000000
+#define MXC91231_CS2_BASE_ADDR          0xB0000000
+#define MXC91231_CS3_BASE_ADDR          0xB2000000
+#define MXC91231_CS4_BASE_ADDR          0xB4000000
+#define MXC91231_CS5_BASE_ADDR          0xB6000000
+
+/* Is given address belongs to the specified memory region? */
+#define ADDRESS_IN_REGION(addr, start, size) \
+        (((addr) >= (start)) && ((addr) < (start)+(size)))
+
+/* Is given address belongs to the specified named `module'? */
+#define MXC91231_IS_MODULE(addr, module) \
+        ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \
+                                MXC91231_ ## module ## _SIZE)
+/*
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+
+#define MXC91231_IO_ADDRESS(x) \
+        (void __iomem *) \
+        (MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \
+         0xDEADBEEF)
+
+
+/*
+ * define the address mapping macros: in physical address order
+ */
+#define MXC91231_L2CC_IO_ADDRESS(x)  \
+        (((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT)
+
+#define MXC91231_AIPS1_IO_ADDRESS(x)  \
+        (((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT)
+
+#define MXC91231_SPBA0_IO_ADDRESS(x)  \
+        (((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT)
+
+#define MXC91231_SPBA1_IO_ADDRESS(x)  \
+        (((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT)
+
+#define MXC91231_AIPS2_IO_ADDRESS(x)  \
+        (((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT)
+
+#define MXC91231_ROMP_IO_ADDRESS(x)  \
+        (((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT)
+
+#define MXC91231_AVIC_IO_ADDRESS(x)  \
+        (((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT)
+
+#define MXC91231_X_MEMC_IO_ADDRESS(x)  \
+        (((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT)
+
+/*
+ * Interrupt numbers
+ */
+#define MXC91231_INT_GPIO3              0
+#define MXC91231_INT_EL1T_CI            1
+#define MXC91231_INT_EL1T_RFCI          2
+#define MXC91231_INT_EL1T_RFI           3
+#define MXC91231_INT_EL1T_MCU           4
+#define MXC91231_INT_EL1T_IPI           5
+#define MXC91231_INT_MU_GEN             6
+#define MXC91231_INT_GPIO4              7
+#define MXC91231_INT_MMC_SDHC2          8
+#define MXC91231_INT_MMC_SDHC1          9
+#define MXC91231_INT_I2C                10
+#define MXC91231_INT_SSI2               11
+#define MXC91231_INT_SSI1               12
+#define MXC91231_INT_CSPI2              13
+#define MXC91231_INT_CSPI1              14
+#define MXC91231_INT_RTIC               15
+#define MXC91231_INT_SAHARA             15
+#define MXC91231_INT_HAC                15
+#define MXC91231_INT_UART3_RX           16
+#define MXC91231_INT_UART3_TX           17
+#define MXC91231_INT_UART3_MINT         18
+#define MXC91231_INT_ECT                19
+#define MXC91231_INT_SIM_IPB            20
+#define MXC91231_INT_SIM_DATA           21
+#define MXC91231_INT_RNGA               22
+#define MXC91231_INT_DSM_AP             23
+#define MXC91231_INT_KPP                24
+#define MXC91231_INT_RTC                25
+#define MXC91231_INT_PWM                26
+#define MXC91231_INT_GEMK_AP            27
+#define MXC91231_INT_EPIT               28
+#define MXC91231_INT_GPT                29
+#define MXC91231_INT_UART2_RX           30
+#define MXC91231_INT_UART2_TX           31
+#define MXC91231_INT_UART2_MINT         32
+#define MXC91231_INT_NANDFC             33
+#define MXC91231_INT_SDMA               34
+#define MXC91231_INT_USB_WAKEUP         35
+#define MXC91231_INT_USB_SOF            36
+#define MXC91231_INT_PMU_EVTMON         37
+#define MXC91231_INT_USB_FUNC           38
+#define MXC91231_INT_USB_DMA            39
+#define MXC91231_INT_USB_CTRL           40
+#define MXC91231_INT_IPU_ERR            41
+#define MXC91231_INT_IPU_SYN            42
+#define MXC91231_INT_UART1_RX           43
+#define MXC91231_INT_UART1_TX           44
+#define MXC91231_INT_UART1_MINT         45
+#define MXC91231_INT_IIM                46
+#define MXC91231_INT_MU_RX_OR           47
+#define MXC91231_INT_MU_TX_OR           48
+#define MXC91231_INT_SCC_SCM            49
+#define MXC91231_INT_SCC_SMN            50
+#define MXC91231_INT_GPIO2              51
+#define MXC91231_INT_GPIO1              52
+#define MXC91231_INT_MQSPI1             53
+#define MXC91231_INT_MQSPI2             54
+#define MXC91231_INT_WDOG2              55
+#define MXC91231_INT_EXT_INT7           56
+#define MXC91231_INT_EXT_INT6           57
+#define MXC91231_INT_EXT_INT5           58
+#define MXC91231_INT_EXT_INT4           59
+#define MXC91231_INT_EXT_INT3           60
+#define MXC91231_INT_EXT_INT2           61
+#define MXC91231_INT_EXT_INT1           62
+#define MXC91231_INT_EXT_INT0           63
+
+#define MXC91231_MAX_INT_LINES          63
+#define MXC91231_MAX_EXT_LINES          8
+
+#endif /* __MACH_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index e56241af870e..ef00199568de 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -21,8 +21,18 @@
 #ifndef __ASM_ARCH_MXC_SYSTEM_H__
 #define __ASM_ARCH_MXC_SYSTEM_H__
 
+#include <mach/hardware.h>
+#include <mach/common.h>
+
 static inline void arch_idle(void)
 {
+#ifdef CONFIG_ARCH_MXC91231
+        if (cpu_is_mxc91231()) {
+                /* Need this to set DSM low-power mode */
+                mxc91231_prepare_idle();
+        }
+#endif
+
         cpu_do_idle();
 }
 
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 07b4a73c9d2f..527a6c24788e 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -26,6 +26,10 @@
 #define CLOCK_TICK_RATE         13300000
 #elif defined CONFIG_ARCH_MX3
 #define CLOCK_TICK_RATE         16625000
+#elif defined CONFIG_ARCH_MX25
+#define CLOCK_TICK_RATE         16000000
+#elif defined CONFIG_ARCH_MXC91231
+#define CLOCK_TICK_RATE         13000000
 #endif
 
 #endif                          /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index de6fe0365982..082a3908256b 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -26,8 +26,11 @@
 #define __MXC_BOOT_UNCOMPRESS
 
 #include <mach/hardware.h>
+#include <asm/mach-types.h>
 
-#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
+static unsigned long uart_base;
+
+#define UART(x) (*(volatile unsigned long *)(uart_base + (x)))
 
 #define USR2 0x98
 #define USR2_TXFE (1<<14)
@@ -46,19 +49,10 @@
 
 static void putc(int ch)
 {
-        static unsigned long serial_port = 0;
-
-        if (unlikely(serial_port == 0)) {
-                do {
-                        serial_port = UART1_BASE_ADDR;
-                        if (UART(UCR1) & UCR1_UARTEN)
-                                break;
-                        serial_port = UART2_BASE_ADDR;
-                        if (UART(UCR1) & UCR1_UARTEN)
-                                break;
-                        return;
-                } while (0);
-        }
+        if (!uart_base)
+                return;
+        if (!(UART(UCR1) & UCR1_UARTEN))
+                return;
 
         while (!(UART(USR2) & USR2_TXFE))
                 barrier();
@@ -68,11 +62,49 @@ static void putc(int ch)
 
 #define flush() do { } while (0)
 
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
+#define MX1_UART1_BASE_ADDR     0x00206000
+#define MX25_UART1_BASE_ADDR    0x43f90000
+#define MX2X_UART1_BASE_ADDR    0x1000a000
+#define MX3X_UART1_BASE_ADDR    0x43F90000
+#define MX3X_UART2_BASE_ADDR    0x43F94000
+
+static __inline__ void __arch_decomp_setup(unsigned long arch_id)
+{
+        switch (arch_id) {
+        case MACH_TYPE_MX1ADS:
+        case MACH_TYPE_SCB9328:
+                uart_base = MX1_UART1_BASE_ADDR;
+                break;
+        case MACH_TYPE_MX25_3DS:
+                uart_base = MX25_UART1_BASE_ADDR;
+                break;
+        case MACH_TYPE_IMX27LITE:
+        case MACH_TYPE_MX27_3DS:
+        case MACH_TYPE_MX27ADS:
+        case MACH_TYPE_PCM038:
+        case MACH_TYPE_MX21ADS:
+                uart_base = MX2X_UART1_BASE_ADDR;
+                break;
+        case MACH_TYPE_MX31LITE:
+        case MACH_TYPE_ARMADILLO5X0:
+        case MACH_TYPE_MX31MOBOARD:
+        case MACH_TYPE_QONG:
+        case MACH_TYPE_MX31_3DS:
+        case MACH_TYPE_PCM037:
+        case MACH_TYPE_MX31ADS:
+        case MACH_TYPE_MX35_3DS:
+        case MACH_TYPE_PCM043:
+                uart_base = MX3X_UART1_BASE_ADDR;
+                break;
+        case MACH_TYPE_MAGX_ZN5:
+                uart_base = MX3X_UART2_BASE_ADDR;
+                break;
+        default:
+                break;
+        }
+}
 
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
 #define arch_decomp_wdog()
 
 #endif                          /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index 77a078f9513f..851ca99bf1b1 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -29,7 +29,7 @@
 #include <asm/mach/map.h>
 #include <mach/iomux-v3.h>
 
-#define IOMUX_BASE      IO_ADDRESS(IOMUXC_BASE_ADDR)
+static void __iomem *base;
 
 static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG];
 
@@ -45,14 +45,14 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
         if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map))
                 return -EBUSY;
         if (pad->mux_ctrl_ofs)
-                __raw_writel(pad->mux_mode, IOMUX_BASE + pad->mux_ctrl_ofs);
+                __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs);
 
         if (pad->select_input_ofs)
                 __raw_writel(pad->select_input,
-                                IOMUX_BASE + pad->select_input_ofs);
+                                base + pad->select_input_ofs);
 
-        if (!(pad->pad_ctrl & NO_PAD_CTRL))
-                __raw_writel(pad->pad_ctrl, IOMUX_BASE + pad->pad_ctrl_ofs);
+        if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs)
+                __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs);
         return 0;
 }
 EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
@@ -96,3 +96,8 @@ void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count)
         }
 }
 EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads);
+
+void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
+{
+        base = iomux_v3_base;
+}
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 8aee76304f8f..778ddfe57d89 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -44,7 +44,7 @@
 #define AVIC_FIPNDH             0x60    /* fast int pending high */
 #define AVIC_FIPNDL             0x64    /* fast int pending low */
 
-static void __iomem *avic_base;
+void __iomem *avic_base;
 
 int imx_irq_set_priority(unsigned char irq, unsigned char prio)
 {
@@ -113,11 +113,11 @@ static struct irq_chip mxc_avic_chip = {
  * interrupts. It registers the interrupt enable and disable functions
  * to the kernel for each interrupt source.
  */
-void __init mxc_init_irq(void)
+void __init mxc_init_irq(void __iomem *irqbase)
 {
         int i;
 
-        avic_base = IO_ADDRESS(AVIC_BASE_ADDR);
+        avic_base = irqbase;
 
         /* put the AVIC into the reset value with
          * all interrupts disabled
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index ae34198a79dd..5cdbd605ac05 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -32,6 +32,7 @@
 #define MX3_PWMPR                 0x10    /* PWM Period Register */
 #define MX3_PWMCR_PRESCALER(x)    (((x - 1) & 0xFFF) << 4)
 #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define MX3_PWMCR_CLKSRC_IPG      (1 << 16)
 #define MX3_PWMCR_EN              (1 << 0)
 
 
@@ -55,9 +56,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
         if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
                 return -EINVAL;
 
-        if (cpu_is_mx27() || cpu_is_mx3()) {
+        if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25()) {
                 unsigned long long c;
                 unsigned long period_cycles, duty_cycles, prescale;
+                u32 cr;
+
                 c = clk_get_rate(pwm->clk);
                 c = c * period_ns;
                 do_div(c, 1000000000);
@@ -72,9 +75,15 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 
                 writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR);
                 writel(period_cycles, pwm->mmio_base + MX3_PWMPR);
-                writel(MX3_PWMCR_PRESCALER(prescale - 1) |
-                        MX3_PWMCR_CLKSRC_IPG_HIGH | MX3_PWMCR_EN,
-                        pwm->mmio_base + MX3_PWMCR);
+
+                cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN;
+
+                if (cpu_is_mx25())
+                        cr |= MX3_PWMCR_CLKSRC_IPG;
+                else
+                        cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
+
+                writel(cr, pwm->mmio_base + MX3_PWMCR);
         } else if (cpu_is_mx1() || cpu_is_mx21()) {
                 /* The PWM subsystem allows for exact frequencies. However,
                  * I cannot connect a scope on my device to the PWM line and
@@ -118,6 +127,8 @@ EXPORT_SYMBOL(pwm_enable);
 
 void pwm_disable(struct pwm_device *pwm)
 {
+        writel(0, pwm->mmio_base + MX3_PWMCR);
+
         if (pwm->clk_enabled) {
                 clk_disable(pwm->clk);
                 pwm->clk_enabled = 0;
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 79c37577c916..97f42799fa58 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -27,32 +27,38 @@
 #include <linux/delay.h>
 
 #include <mach/hardware.h>
+#include <mach/common.h>
 #include <asm/proc-fns.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_ARCH_MX1
-#define WDOG_WCR_REG            IO_ADDRESS(WDT_BASE_ADDR)
-#define WDOG_WCR_ENABLE         (1 << 0)
-#else
-#define WDOG_WCR_REG            IO_ADDRESS(WDOG_BASE_ADDR)
-#define WDOG_WCR_ENABLE         (1 << 2)
-#endif
+static void __iomem *wdog_base;
 
 /*
  * Reset the system. It is called by machine_restart().
  */
 void arch_reset(char mode, const char *cmd)
 {
-        if (!cpu_is_mx1()) {
+        unsigned int wcr_enable;
+
+#ifdef CONFIG_ARCH_MXC91231
+        if (cpu_is_mxc91231()) {
+                mxc91231_arch_reset(mode, cmd);
+                return;
+        }
+#endif
+        if (cpu_is_mx1()) {
+                wcr_enable = (1 << 0);
+        } else {
                 struct clk *clk;
 
                 clk = clk_get_sys("imx-wdt.0", NULL);
                 if (!IS_ERR(clk))
                         clk_enable(clk);
+                wcr_enable = (1 << 2);
         }
 
         /* Assert SRS signal */
-        __raw_writew(WDOG_WCR_ENABLE, WDOG_WCR_REG);
+        __raw_writew(wcr_enable, wdog_base);
 
         /* wait for reset to assert... */
         mdelay(500);
@@ -65,3 +71,8 @@ void arch_reset(char mode, const char *cmd)
         /* we'll take a jump through zero as a poor second */
         cpu_reset(0);
 }
+
+void mxc_arch_reset_init(void __iomem *base)
+{
+        wdog_base = base;
+}
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 88fb3a57e029..844567ee35fe 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -47,7 +47,7 @@
 #define MX2_TSTAT_CAPT          (1 << 1)
 #define MX2_TSTAT_COMP          (1 << 0)
 
-/* MX31, MX35 */
+/* MX31, MX35, MX25, MXC91231 */
 #define MX3_TCTL_WAITEN         (1 << 3)
 #define MX3_TCTL_CLK_IPG        (1 << 6)
 #define MX3_TCTL_FRR            (1 << 9)
@@ -66,7 +66,7 @@ static inline void gpt_irq_disable(void)
 {
         unsigned int tmp;
 
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 __raw_writel(0, timer_base + MX3_IR);
         else {
                 tmp = __raw_readl(timer_base + MXC_TCTL);
@@ -76,7 +76,7 @@ static inline void gpt_irq_disable(void)
 
 static inline void gpt_irq_enable(void)
 {
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 __raw_writel(1<<0, timer_base + MX3_IR);
         else {
                 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
@@ -90,7 +90,7 @@ static void gpt_irq_acknowledge(void)
                 __raw_writel(0, timer_base + MX1_2_TSTAT);
         if (cpu_is_mx2())
                 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT);
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
 }
 
@@ -117,7 +117,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
 {
         unsigned int c = clk_get_rate(timer_clk);
 
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 clocksource_mxc.read = mx3_get_cycles;
 
         clocksource_mxc.mult = clocksource_hz2mult(c,
@@ -180,7 +180,7 @@ static void mxc_set_mode(enum clock_event_mode mode,
 
         if (mode != clockevent_mode) {
                 /* Set event time into far-far future */
-                if (cpu_is_mx3())
+                if (cpu_is_mx3() || cpu_is_mx25())
                         __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3,
                                         timer_base + MX3_TCMP);
                 else
@@ -233,7 +233,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
         struct clock_event_device *evt = &clockevent_mxc;
         uint32_t tstat;
 
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 tstat = __raw_readl(timer_base + MX3_TSTAT);
         else
                 tstat = __raw_readl(timer_base + MX1_2_TSTAT);
@@ -264,7 +264,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
 {
         unsigned int c = clk_get_rate(timer_clk);
 
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 clockevent_mxc.set_next_event = mx3_set_next_event;
 
         clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
@@ -281,30 +281,13 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
         return 0;
 }
 
-void __init mxc_timer_init(struct clk *timer_clk)
+void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 {
         uint32_t tctl_val;
-        int irq;
 
         clk_enable(timer_clk);
 
-        if (cpu_is_mx1()) {
-#ifdef CONFIG_ARCH_MX1
-                timer_base = IO_ADDRESS(TIM1_BASE_ADDR);
-                irq = TIM1_INT;
-#endif
-        } else if (cpu_is_mx2()) {
-#ifdef CONFIG_ARCH_MX2
-                timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
-                irq = MXC_INT_GPT1;
-#endif
-        } else if (cpu_is_mx3()) {
-#ifdef CONFIG_ARCH_MX3
-                timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
-                irq = MXC_INT_GPT;
-#endif
-        } else
-                BUG();
+        timer_base = base;
 
         /*
          * Initialise to a known state (all timers off, and timing reset)
@@ -313,7 +296,7 @@ void __init mxc_timer_init(struct clk *timer_clk)
         __raw_writel(0, timer_base + MXC_TCTL);
         __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
 
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                 tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
         else
                 tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 843e8af64066..1868c0d8f9b5 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -78,10 +78,10 @@ static int omap_target(struct cpufreq_policy *policy,
 
         /* Ensure desired rate is within allowed range.  Some govenors
          * (ondemand) will just pass target_freq=0 to get the minimum. */
-        if (target_freq < policy->cpuinfo.min_freq)
-                target_freq = policy->cpuinfo.min_freq;
-        if (target_freq > policy->cpuinfo.max_freq)
-                target_freq = policy->cpuinfo.max_freq;
+        if (target_freq < policy->min)
+                target_freq = policy->min;
+        if (target_freq > policy->max)
+                target_freq = policy->max;
 
         freqs.old = omap_getspeed(0);
         freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000;
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 26b387c12423..00940dc6bb50 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -138,6 +138,32 @@
 #define OMAP24XX_GPIO_CLEARDATAOUT      0x0090
 #define OMAP24XX_GPIO_SETDATAOUT        0x0094
 
+#define OMAP4_GPIO_REVISION             0x0000
+#define OMAP4_GPIO_SYSCONFIG            0x0010
+#define OMAP4_GPIO_EOI                  0x0020
+#define OMAP4_GPIO_IRQSTATUSRAW0        0x0024
+#define OMAP4_GPIO_IRQSTATUSRAW1        0x0028
+#define OMAP4_GPIO_IRQSTATUS0           0x002c
+#define OMAP4_GPIO_IRQSTATUS1           0x0030
+#define OMAP4_GPIO_IRQSTATUSSET0        0x0034
+#define OMAP4_GPIO_IRQSTATUSSET1        0x0038
+#define OMAP4_GPIO_IRQSTATUSCLR0        0x003c
+#define OMAP4_GPIO_IRQSTATUSCLR1        0x0040
+#define OMAP4_GPIO_IRQWAKEN0            0x0044
+#define OMAP4_GPIO_IRQWAKEN1            0x0048
+#define OMAP4_GPIO_SYSSTATUS            0x0104
+#define OMAP4_GPIO_CTRL                 0x0130
+#define OMAP4_GPIO_OE                   0x0134
+#define OMAP4_GPIO_DATAIN               0x0138
+#define OMAP4_GPIO_DATAOUT              0x013c
+#define OMAP4_GPIO_LEVELDETECT0         0x0140
+#define OMAP4_GPIO_LEVELDETECT1         0x0144
+#define OMAP4_GPIO_RISINGDETECT         0x0148
+#define OMAP4_GPIO_FALLINGDETECT        0x014c
+#define OMAP4_GPIO_DEBOUNCENABLE        0x0150
+#define OMAP4_GPIO_DEBOUNCINGTIME       0x0154
+#define OMAP4_GPIO_CLEARDATAOUT         0x0190
+#define OMAP4_GPIO_SETDATAOUT           0x0194
 /*
  * omap34xx specific GPIO registers
  */
@@ -386,12 +412,16 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
                 reg += OMAP850_GPIO_DIR_CONTROL;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_OE;
                 break;
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+        case METHOD_GPIO_24XX:
+                reg += OMAP4_GPIO_OE;
+                break;
+#endif
         default:
                 WARN_ON(1);
                 return;
@@ -459,8 +489,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                         l &= ~(1 << gpio);
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 if (enable)
                         reg += OMAP24XX_GPIO_SETDATAOUT;
@@ -469,6 +498,15 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                 l = 1 << gpio;
                 break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+        case METHOD_GPIO_24XX:
+                if (enable)
+                        reg += OMAP4_GPIO_SETDATAOUT;
+                else
+                        reg += OMAP4_GPIO_CLEARDATAOUT;
+                l = 1 << gpio;
+                break;
+#endif
         default:
                 WARN_ON(1);
                 return;
@@ -511,12 +549,16 @@ static int __omap_get_gpio_datain(int gpio)
                 reg += OMAP850_GPIO_DATA_INPUT;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_DATAIN;
                 break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+        case METHOD_GPIO_24XX:
+                reg += OMAP4_GPIO_DATAIN;
+                break;
+#endif
         default:
                 return -EINVAL;
         }
@@ -544,7 +586,11 @@ void omap_set_gpio_debounce(int gpio, int enable)
 
         bank = get_gpio_bank(gpio);
         reg = bank->base;
+#ifdef CONFIG_ARCH_OMAP4
+        reg += OMAP4_GPIO_DEBOUNCENABLE;
+#else
         reg += OMAP24XX_GPIO_DEBOUNCE_EN;
+#endif
 
         spin_lock_irqsave(&bank->lock, flags);
         val = __raw_readl(reg);
@@ -581,7 +627,11 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time)
         reg = bank->base;
 
         enc_time &= 0xff;
+#ifdef CONFIG_ARCH_OMAP4
+        reg += OMAP4_GPIO_DEBOUNCINGTIME;
+#else
         reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
+#endif
         __raw_writel(enc_time, reg);
 }
 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
@@ -593,23 +643,46 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
 {
         void __iomem *base = bank->base;
         u32 gpio_bit = 1 << gpio;
+        u32 val;
 
-        MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
-                trigger & IRQ_TYPE_LEVEL_LOW);
-        MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
-                trigger & IRQ_TYPE_LEVEL_HIGH);
-        MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
-                trigger & IRQ_TYPE_EDGE_RISING);
-        MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
-                trigger & IRQ_TYPE_EDGE_FALLING);
-
+        if (cpu_is_omap44xx()) {
+                MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_LOW);
+                MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_HIGH);
+                MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_RISING);
+                MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_FALLING);
+        } else {
+                MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_LOW);
+                MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_HIGH);
+                MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_RISING);
+                MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_FALLING);
+        }
         if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
-                if (trigger != 0)
-                        __raw_writel(1 << gpio, bank->base
+                if (cpu_is_omap44xx()) {
+                        if (trigger != 0)
+                                __raw_writel(1 << gpio, bank->base+
+                                                OMAP4_GPIO_IRQWAKEN0);
+                        else {
+                                val = __raw_readl(bank->base +
+                                                        OMAP4_GPIO_IRQWAKEN0);
+                                __raw_writel(val & (~(1 << gpio)), bank->base +
+                                                         OMAP4_GPIO_IRQWAKEN0);
+                        }
+                } else {
+                        if (trigger != 0)
+                                __raw_writel(1 << gpio, bank->base
                                         + OMAP24XX_GPIO_SETWKUENA);
-                else
-                        __raw_writel(1 << gpio, bank->base
+                        else
+                                __raw_writel(1 << gpio, bank->base
                                         + OMAP24XX_GPIO_CLEARWKUENA);
+                }
         } else {
                 if (trigger != 0)
                         bank->enabled_non_wakeup_gpios |= gpio_bit;
@@ -617,9 +690,15 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
                         bank->enabled_non_wakeup_gpios &= ~gpio_bit;
         }
 
-        bank->level_mask =
-                __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
-                __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+        if (cpu_is_omap44xx()) {
+                bank->level_mask =
+                        __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
+                        __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
+        } else {
+                bank->level_mask =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+        }
 }
 #endif
 
@@ -783,12 +862,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
                 reg += OMAP850_GPIO_INT_STATUS;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_IRQSTATUS1;
                 break;
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+        case METHOD_GPIO_24XX:
+                reg += OMAP4_GPIO_IRQSTATUS0;
+                break;
+#endif
         default:
                 WARN_ON(1);
                 return;
@@ -798,12 +881,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
         /* Workaround for clearing DSP GPIO interrupts to allow retention */
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+#endif
+#if defined(CONFIG_ARCH_OMAP4)
+        reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
+#endif
+        if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 __raw_writel(gpio_mask, reg);
 
         /* Flush posted write for the irq status to avoid spurious interrupts */
         __raw_readl(reg);
-#endif
+        }
 }
 
 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
@@ -853,13 +940,18 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
                 inv = 1;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 reg += OMAP24XX_GPIO_IRQENABLE1;
                 mask = 0xffffffff;
                 break;
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+        case METHOD_GPIO_24XX:
+                reg += OMAP4_GPIO_IRQSTATUSSET0;
+                mask = 0xffffffff;
+                break;
+#endif
         default:
                 WARN_ON(1);
                 return 0;
@@ -927,8 +1019,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                         l |= gpio_mask;
                 break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         case METHOD_GPIO_24XX:
                 if (enable)
                         reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@ -937,6 +1028,15 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                 l = gpio_mask;
                 break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+        case METHOD_GPIO_24XX:
+                if (enable)
+                        reg += OMAP4_GPIO_IRQSTATUSSET0;
+                else
+                        reg += OMAP4_GPIO_IRQSTATUSCLR0;
+                l = gpio_mask;
+                break;
+#endif
         default:
                 WARN_ON(1);
                 return;
@@ -1112,11 +1212,14 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         if (bank->method == METHOD_GPIO_850)
                 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
         if (bank->method == METHOD_GPIO_24XX)
                 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+        if (bank->method == METHOD_GPIO_24XX)
+                isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
+#endif
         while(1) {
                 u32 isr_saved, level_mask = 0;
                 u32 enabled;
@@ -1189,6 +1292,7 @@ static void gpio_mask_irq(unsigned int irq)
         struct gpio_bank *bank = get_irq_chip_data(irq);
 
         _set_gpio_irqenable(bank, gpio, 0);
+        _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
 }
 
 static void gpio_unmask_irq(unsigned int irq)
@@ -1196,6 +1300,11 @@ static void gpio_unmask_irq(unsigned int irq)
         unsigned int gpio = irq - IH_GPIO_BASE;
         struct gpio_bank *bank = get_irq_chip_data(irq);
         unsigned int irq_mask = 1 << get_gpio_index(gpio);
+        struct irq_desc *desc = irq_to_desc(irq);
+        u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
+
+        if (trigger)
+                _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
 
         /* For level-triggered GPIOs, the clearing must be done after
          * the HW source is cleared, thus after the handler has run */
@@ -1547,7 +1656,7 @@ static int __init _omap_gpio_init(void)
 
                 gpio_bank_count = OMAP34XX_NR_GPIOS;
                 gpio_bank = gpio_bank_44xx;
-                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
+                rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
                 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
                         (rev >> 4) & 0x0f, rev & 0x0f);
         }
@@ -1581,7 +1690,16 @@ static int __init _omap_gpio_init(void)
                         static const u32 non_wakeup_gpios[] = {
                                 0xe203ffc0, 0x08700040
                         };
-
+                if (cpu_is_omap44xx()) {
+                        __raw_writel(0xffffffff, bank->base +
+                                                OMAP4_GPIO_IRQSTATUSCLR0);
+                        __raw_writew(0x0015, bank->base +
+                                                OMAP4_GPIO_SYSCONFIG);
+                        __raw_writel(0x00000000, bank->base +
+                                                 OMAP4_GPIO_DEBOUNCENABLE);
+                        /* Initialize interface clock ungated, module enabled */
+                        __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
+                } else {
                         __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
                         __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
                         __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
@@ -1589,12 +1707,12 @@ static int __init _omap_gpio_init(void)
 
                         /* Initialize interface clock ungated, module enabled */
                         __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
+                }
                         if (i < ARRAY_SIZE(non_wakeup_gpios))
                                 bank->non_wakeup_gpios = non_wakeup_gpios[i];
                         gpio_count = 32;
                 }
 #endif
-
                 /* REVISIT eventually switch from OMAP-specific gpio structs
                  * over to the generic ones
                  */
@@ -1680,14 +1798,20 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
                         wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                         break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                 case METHOD_GPIO_24XX:
                         wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
                         wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
                         wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
                         break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                case METHOD_GPIO_24XX:
+                        wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        break;
+#endif
                 default:
                         continue;
                 }
@@ -1722,13 +1846,18 @@ static int omap_gpio_resume(struct sys_device *dev)
                         wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                         break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                 case METHOD_GPIO_24XX:
                         wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
                         wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
                         break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                case METHOD_GPIO_24XX:
+                        wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        break;
+#endif
                 default:
                         continue;
                 }
@@ -1772,21 +1901,29 @@ void omap2_gpio_prepare_for_retention(void)
 
                 if (!(bank->enabled_non_wakeup_gpios))
                         continue;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                                defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
                 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                bank->saved_datain = __raw_readl(bank->base +
+                                                        OMAP4_GPIO_DATAIN);
+                l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
+                l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
+#endif
                 bank->saved_fallingdetect = l1;
                 bank->saved_risingdetect = l2;
                 l1 &= ~bank->enabled_non_wakeup_gpios;
                 l2 &= ~bank->enabled_non_wakeup_gpios;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
+                __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
+#endif
                 c++;
         }
         if (!c) {
@@ -1808,27 +1945,29 @@ void omap2_gpio_resume_after_retention(void)
 
                 if (!(bank->enabled_non_wakeup_gpios))
                         continue;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                 __raw_writel(bank->saved_fallingdetect,
                                  bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                 __raw_writel(bank->saved_risingdetect,
                                  bank->base + OMAP24XX_GPIO_RISINGDETECT);
+                l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+                __raw_writel(bank->saved_fallingdetect,
+                                 bank->base + OMAP4_GPIO_FALLINGDETECT);
+                __raw_writel(bank->saved_risingdetect,
+                                 bank->base + OMAP4_GPIO_RISINGDETECT);
+                l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
 #endif
                 /* Check if any of the non-wakeup interrupt GPIOs have changed
                  * state.  If so, generate an IRQ by software.  This is
                  * horribly racy, but it's the best we can do to work around
                  * this silicon bug. */
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
-                l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
-#endif
                 l ^= bank->saved_datain;
                 l &= bank->non_wakeup_gpios;
                 if (l) {
                         u32 old0, old1;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                         old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
                         old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
                         __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
@@ -1836,6 +1975,20 @@ void omap2_gpio_resume_after_retention(void)
                         __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
                         __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                        old0 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_LEVELDETECT0);
+                        old1 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_LEVELDETECT1);
+                        __raw_writel(old0 | l, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT0);
+                        __raw_writel(old1 | l, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT1);
+                        __raw_writel(old0, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT0);
+                        __raw_writel(old1, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT1);
+#endif
                 }
         }
 
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
index 7b939cc01962..72f680b7180d 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -122,6 +122,11 @@
 #define OMAP_DMA4_CCFN(n)               (0x60 * (n) + 0xc0)
 #define OMAP_DMA4_COLOR(n)              (0x60 * (n) + 0xc4)
 
+/* Additional registers available on OMAP4 */
+#define OMAP_DMA4_CDP(n)                (0x60 * (n) + 0xd0)
+#define OMAP_DMA4_CNDP(n)               (0x60 * (n) + 0xd4)
+#define OMAP_DMA4_CCDN(n)               (0x60 * (n) + 0xd8)
+
 /* Dummy defines to keep multi-omap compiles happy */
 #define OMAP1_DMA_REVISION              0
 #define OMAP1_DMA_IRQSTATUS_L0          0
@@ -311,6 +316,89 @@
 #define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
 #define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
 
+/* DMA request lines for 44xx */
+#define OMAP44XX_DMA_DSS_DISPC_REQ      6       /* S_DMA_5 */
+#define OMAP44XX_DMA_SYS_REQ2           7       /* S_DMA_6 */
+#define OMAP44XX_DMA_ISS_REQ1           9       /* S_DMA_8 */
+#define OMAP44XX_DMA_ISS_REQ2           10      /* S_DMA_9 */
+#define OMAP44XX_DMA_ISS_REQ3           12      /* S_DMA_11 */
+#define OMAP44XX_DMA_ISS_REQ4           13      /* S_DMA_12 */
+#define OMAP44XX_DMA_DSS_RFBI_REQ       14      /* S_DMA_13 */
+#define OMAP44XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
+#define OMAP44XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
+#define OMAP44XX_DMA_MCBSP2_TX          17      /* S_DMA_16 */
+#define OMAP44XX_DMA_MCBSP2_RX          18      /* S_DMA_17 */
+#define OMAP44XX_DMA_MCBSP3_TX          19      /* S_DMA_18 */
+#define OMAP44XX_DMA_MCBSP3_RX          20      /* S_DMA_19 */
+#define OMAP44XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
+#define OMAP44XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
+#define OMAP44XX_DMA_I2C3_TX            25      /* S_DMA_24 */
+#define OMAP44XX_DMA_I2C3_RX            26      /* S_DMA_25 */
+#define OMAP44XX_DMA_I2C1_TX            27      /* S_DMA_26 */
+#define OMAP44XX_DMA_I2C1_RX            28      /* S_DMA_27 */
+#define OMAP44XX_DMA_I2C2_TX            29      /* S_DMA_28 */
+#define OMAP44XX_DMA_I2C2_RX            30      /* S_DMA_29 */
+#define OMAP44XX_DMA_MCBSP4_TX          31      /* S_DMA_30 */
+#define OMAP44XX_DMA_MCBSP4_RX          32      /* S_DMA_31 */
+#define OMAP44XX_DMA_MCBSP1_TX          33      /* S_DMA_32 */
+#define OMAP44XX_DMA_MCBSP1_RX          34      /* S_DMA_33 */
+#define OMAP44XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
+#define OMAP44XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
+#define OMAP44XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
+#define OMAP44XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
+#define OMAP44XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
+#define OMAP44XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
+#define OMAP44XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
+#define OMAP44XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
+#define OMAP44XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
+#define OMAP44XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
+#define OMAP44XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
+#define OMAP44XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
+#define OMAP44XX_DMA_MMC2_TX            47      /* S_DMA_46 */
+#define OMAP44XX_DMA_MMC2_RX            48      /* S_DMA_47 */
+#define OMAP44XX_DMA_UART1_TX           49      /* S_DMA_48 */
+#define OMAP44XX_DMA_UART1_RX           50      /* S_DMA_49 */
+#define OMAP44XX_DMA_UART2_TX           51      /* S_DMA_50 */
+#define OMAP44XX_DMA_UART2_RX           52      /* S_DMA_51 */
+#define OMAP44XX_DMA_UART3_TX           53      /* S_DMA_52 */
+#define OMAP44XX_DMA_UART3_RX           54      /* S_DMA_53 */
+#define OMAP44XX_DMA_UART4_TX           55      /* S_DMA_54 */
+#define OMAP44XX_DMA_UART4_RX           56      /* S_DMA_55 */
+#define OMAP44XX_DMA_MMC4_TX            57      /* S_DMA_56 */
+#define OMAP44XX_DMA_MMC4_RX            58      /* S_DMA_57 */
+#define OMAP44XX_DMA_MMC5_TX            59      /* S_DMA_58 */
+#define OMAP44XX_DMA_MMC5_RX            60      /* S_DMA_59 */
+#define OMAP44XX_DMA_MMC1_TX            61      /* S_DMA_60 */
+#define OMAP44XX_DMA_MMC1_RX            62      /* S_DMA_61 */
+#define OMAP44XX_DMA_SYS_REQ3           64      /* S_DMA_63 */
+#define OMAP44XX_DMA_MCPDM_UP           65      /* S_DMA_64 */
+#define OMAP44XX_DMA_MCPDM_DL           66      /* S_DMA_65 */
+#define OMAP44XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
+#define OMAP44XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ0      72      /* S_DMA_71 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ1      73      /* S_DMA_72 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ2      74      /* S_DMA_73 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ3      75      /* S_DMA_74 */
+#define OMAP44XX_DMA_DSS_HDMI_REQ       76      /* S_DMA_75 */
+#define OMAP44XX_DMA_MMC3_TX            77      /* S_DMA_76 */
+#define OMAP44XX_DMA_MMC3_RX            78      /* S_DMA_77 */
+#define OMAP44XX_DMA_USIM_TX            79      /* S_DMA_78 */
+#define OMAP44XX_DMA_USIM_RX            80      /* S_DMA_79 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ0      81      /* S_DMA_80 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ1      82      /* S_DMA_81 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ2      83      /* S_DMA_82 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ3      84      /* S_DMA_83 */
+#define OMAP44XX_DMA_ABE_REQ0           101     /* S_DMA_100 */
+#define OMAP44XX_DMA_ABE_REQ1           102     /* S_DMA_101 */
+#define OMAP44XX_DMA_ABE_REQ2           103     /* S_DMA_102 */
+#define OMAP44XX_DMA_ABE_REQ3           104     /* S_DMA_103 */
+#define OMAP44XX_DMA_ABE_REQ4           105     /* S_DMA_104 */
+#define OMAP44XX_DMA_ABE_REQ5           106     /* S_DMA_105 */
+#define OMAP44XX_DMA_ABE_REQ6           107     /* S_DMA_106 */
+#define OMAP44XX_DMA_ABE_REQ7           108     /* S_DMA_107 */
+#define OMAP44XX_DMA_I2C4_TX            124     /* S_DMA_123 */
+#define OMAP44XX_DMA_I2C4_RX            125     /* S_DMA_124 */
+
 /*----------------------------------------------------------------------------*/
 
 /* Hardware registers for LCD DMA */
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index bb154ea76769..ec6f81e06d39 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -53,6 +53,11 @@
 #define OMAP34XX_MCBSP4_BASE    0x49026000
 #define OMAP34XX_MCBSP5_BASE    0x48096000
 
+#define OMAP44XX_MCBSP1_BASE    0x49022000
+#define OMAP44XX_MCBSP2_BASE    0x49024000
+#define OMAP44XX_MCBSP3_BASE    0x49026000
+#define OMAP44XX_MCBSP4_BASE    0x48074000
+
 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
 
 #define OMAP_MCBSP_REG_DRR2     0x00
@@ -98,7 +103,8 @@
 #define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
 #define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
 
-#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+        defined(CONFIG_ARCH_OMAP4)
 
 #define OMAP_MCBSP_REG_DRR2     0x00
 #define OMAP_MCBSP_REG_DRR1     0x04
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index 13abd02d1527..def0529c75eb 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -59,6 +59,7 @@ extern void omap_uart_check_wakeup(void);
 extern void omap_uart_prepare_suspend(void);
 extern void omap_uart_prepare_idle(int num);
 extern void omap_uart_resume_idle(int num);
+extern void omap_uart_enable_irqs(int enable);
 #endif
 
 #endif
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index efa0e0111f38..e42fa7cfc795 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -191,7 +191,7 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
-        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
                 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
                 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
         }
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index a2bed62aec21..4fa9903b83cf 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -42,6 +42,7 @@ ENTRY(vfp_null_entry)
         mov     pc, lr
 ENDPROC(vfp_null_entry)
 
+        .align  2
 .LCvfp:
         .word   vfp_vector
 
@@ -61,6 +62,7 @@ ENTRY(vfp_testing_entry)
         mov     pc, r9                  @ we have handled the fault
 ENDPROC(vfp_testing_entry)
 
+        .align  2
 VFP_arch_address:
         .word   VFP_arch
 
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index 1aeae38725dd..66dc2d03b7fc 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -209,40 +209,55 @@ ENDPROC(vfp_save_state)
 last_VFP_context_address:
         .word   last_VFP_context
 
-ENTRY(vfp_get_float)
-        add     pc, pc, r0, lsl #3
+        .macro  tbl_branch, base, tmp, shift
+#ifdef CONFIG_THUMB2_KERNEL
+        adr     \tmp, 1f
+        add     \tmp, \tmp, \base, lsl \shift
+        mov     pc, \tmp
+#else
+        add     pc, pc, \base, lsl \shift
         mov     r0, r0
+#endif
+1:
+        .endm
+
+ENTRY(vfp_get_float)
+        tbl_branch r0, r3, #3
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mrc     p10, 0, r0, c\dr, c0, 0 @ fmrs  r0, s0
+1:      mrc     p10, 0, r0, c\dr, c0, 0 @ fmrs  r0, s0
         mov     pc, lr
-        mrc     p10, 0, r0, c\dr, c0, 4 @ fmrs  r0, s1
+        .org    1b + 8
+1:      mrc     p10, 0, r0, c\dr, c0, 4 @ fmrs  r0, s1
         mov     pc, lr
+        .org    1b + 8
         .endr
 ENDPROC(vfp_get_float)
 
 ENTRY(vfp_put_float)
-        add     pc, pc, r1, lsl #3
-        mov     r0, r0
+        tbl_branch r1, r3, #3
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mcr     p10, 0, r0, c\dr, c0, 0 @ fmsr  r0, s0
+1:      mcr     p10, 0, r0, c\dr, c0, 0 @ fmsr  r0, s0
         mov     pc, lr
-        mcr     p10, 0, r0, c\dr, c0, 4 @ fmsr  r0, s1
+        .org    1b + 8
+1:      mcr     p10, 0, r0, c\dr, c0, 4 @ fmsr  r0, s1
         mov     pc, lr
+        .org    1b + 8
         .endr
 ENDPROC(vfp_put_float)
 
 ENTRY(vfp_get_double)
-        add     pc, pc, r0, lsl #3
-        mov     r0, r0
+        tbl_branch r0, r3, #3
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        fmrrd   r0, r1, d\dr
+1:      fmrrd   r0, r1, d\dr
         mov     pc, lr
+        .org    1b + 8
         .endr
 #ifdef CONFIG_VFPv3
         @ d16 - d31 registers
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mrrc    p11, 3, r0, r1, c\dr    @ fmrrd r0, r1, d\dr
+1:      mrrc    p11, 3, r0, r1, c\dr    @ fmrrd r0, r1, d\dr
         mov     pc, lr
+        .org    1b + 8
         .endr
 #endif
 
@@ -253,17 +268,18 @@ ENTRY(vfp_get_double)
 ENDPROC(vfp_get_double)
 
 ENTRY(vfp_put_double)
-        add     pc, pc, r2, lsl #3
-        mov     r0, r0
+        tbl_branch r2, r3, #3
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        fmdrr   d\dr, r0, r1
+1:      fmdrr   d\dr, r0, r1
         mov     pc, lr
+        .org    1b + 8
         .endr
 #ifdef CONFIG_VFPv3
         @ d16 - d31 registers
         .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mcrr    p11, 3, r1, r2, c\dr    @ fmdrr r1, r2, d\dr
+1:      mcrr    p11, 3, r1, r2, c\dr    @ fmdrr r1, r2, d\dr
         mov     pc, lr
+        .org    1b + 8
         .endr
 #endif
 ENDPROC(vfp_put_double)
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
index 5d7b58f1fe42..7485afd0df4c 100644
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -67,21 +67,8 @@
 #define UBIR  0xa4 /* BRM Incremental Register */
 #define UBMR  0xa8 /* BRM Modulator Register */
 #define UBRC  0xac /* Baud Rate Count Register */
-#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
-#define ONEMS 0xb0 /* One Millisecond register */
-#define UTS   0xb4 /* UART Test Register */
-#endif
-#ifdef CONFIG_ARCH_MX1
-#define BIPR1 0xb0 /* Incremental Preset Register 1 */
-#define BIPR2 0xb4 /* Incremental Preset Register 2 */
-#define BIPR3 0xb8 /* Incremental Preset Register 3 */
-#define BIPR4 0xbc /* Incremental Preset Register 4 */
-#define BMPR1 0xc0 /* BRM Modulator Register 1 */
-#define BMPR2 0xc4 /* BRM Modulator Register 2 */
-#define BMPR3 0xc8 /* BRM Modulator Register 3 */
-#define BMPR4 0xcc /* BRM Modulator Register 4 */
-#define UTS   0xd0 /* UART Test Register */
-#endif
+#define MX2_ONEMS 0xb0 /* One Millisecond register */
+#define UTS (cpu_is_mx1() ? 0xd0 : 0xb4) /* UART Test Register */
 
 /* UART Control Register Bit Fields.*/
 #define  URXD_CHARRDY    (1<<15)
@@ -101,12 +88,7 @@
 #define  UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
 #define  UCR1_SNDBRK     (1<<4)  /* Send break */
 #define  UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
-#ifdef CONFIG_ARCH_MX1
-#define  UCR1_UARTCLKEN  (1<<2)  /* UART clock enabled */
-#endif
-#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
-#define  UCR1_UARTCLKEN  (0)     /* not present on mx2/mx3 */
-#endif
+#define  MX1_UCR1_UARTCLKEN  (1<<2)      /* UART clock enabled, mx1 only */
 #define  UCR1_DOZE       (1<<1)  /* Doze */
 #define  UCR1_UARTEN     (1<<0)  /* UART enabled */
 #define  UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
@@ -132,13 +114,9 @@
 #define  UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
 #define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 #define  UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
-#ifdef CONFIG_ARCH_MX1
-#define  UCR3_REF25      (1<<3)  /* Ref freq 25 MHz, only on mx1 */
-#define  UCR3_REF30      (1<<2)  /* Ref Freq 30 MHz, only on mx1 */
-#endif
-#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
-#define  UCR3_RXDMUXSEL  (1<<2)  /* RXD Muxed Input Select, on mx2/mx3 */
-#endif
+#define  MX1_UCR3_REF25          (1<<3)  /* Ref freq 25 MHz, only on mx1 */
+#define  MX1_UCR3_REF30          (1<<2)  /* Ref Freq 30 MHz, only on mx1 */
+#define  MX2_UCR3_RXDMUXSEL      (1<<2)  /* RXD Muxed Input Select, on mx2/mx3 */
 #define  UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
 #define  UCR3_BPEN       (1<<0)  /* Preset registers enable */
 #define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
@@ -186,12 +164,10 @@
 #define  UTS_SOFTRST     (1<<0)  /* Software reset */
 
 /* We've been assigned a range on the "Low-density serial ports" major */
-#ifdef CONFIG_ARCH_MXC
 #define SERIAL_IMX_MAJOR        207
 #define MINOR_START             16
 #define DEV_NAME                "ttymxc"
 #define MAX_INTERNAL_IRQ        MXC_INTERNAL_IRQS
-#endif
 
 /*
  * This determines how often we check the modem status signals
@@ -706,11 +682,11 @@ static int imx_startup(struct uart_port *port)
                 }
         }
 
-#if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3
-        temp = readl(sport->port.membase + UCR3);
-        temp |= UCR3_RXDMUXSEL;
-        writel(temp, sport->port.membase + UCR3);
-#endif
+        if (!cpu_is_mx1()) {
+                temp = readl(sport->port.membase + UCR3);
+                temp |= MX2_UCR3_RXDMUXSEL;
+                writel(temp, sport->port.membase + UCR3);
+        }
 
         if (USE_IRDA(sport)) {
                 temp = readl(sport->port.membase + UCR4);
@@ -942,9 +918,9 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios,
         writel(num, sport->port.membase + UBIR);
         writel(denom, sport->port.membase + UBMR);
 
-#ifdef ONEMS
-        writel(sport->port.uartclk / div / 1000, sport->port.membase + ONEMS);
-#endif
+        if (!cpu_is_mx1())
+                writel(sport->port.uartclk / div / 1000,
+                                sport->port.membase + MX2_ONEMS);
 
         writel(old_ucr1, sport->port.membase + UCR1);
 
@@ -1074,17 +1050,20 @@ static void
 imx_console_write(struct console *co, const char *s, unsigned int count)
 {
         struct imx_port *sport = imx_ports[co->index];
-        unsigned int old_ucr1, old_ucr2;
+        unsigned int old_ucr1, old_ucr2, ucr1;
 
         /*
          *      First, save UCR1/2 and then disable interrupts
          */
-        old_ucr1 = readl(sport->port.membase + UCR1);
+        ucr1 = old_ucr1 = readl(sport->port.membase + UCR1);
         old_ucr2 = readl(sport->port.membase + UCR2);
 
-        writel((old_ucr1 | UCR1_UARTCLKEN | UCR1_UARTEN) &
-                ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
-                sport->port.membase + UCR1);
+        if (cpu_is_mx1())
+                ucr1 |= MX1_UCR1_UARTCLKEN;
+        ucr1 |= UCR1_UARTEN;
+        ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
+
+        writel(ucr1, sport->port.membase + UCR1);
 
         writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
 
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index 15a0ee6d8e23..30ae3022f633 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -33,6 +33,7 @@
 #include <linux/math64.h>
 
 #include <mach/imxfb.h>
+#include <mach/hardware.h>
 
 /*
  * Complain if VAR is out of range.
@@ -129,6 +130,10 @@
 #define LCDISR_EOF      (1<<1)
 #define LCDISR_BOF      (1<<0)
 
+/* Used fb-mode. Can be set on kernel command line, therefore file-static. */
+static const char *fb_mode;
+
+
 /*
  * These are the bitfields for each
  * display depth that we support.
@@ -145,10 +150,6 @@ struct imxfb_info {
         void __iomem            *regs;
         struct clk              *clk;
 
-        u_int                   max_bpp;
-        u_int                   max_xres;
-        u_int                   max_yres;
-
         /*
          * These are the addresses we mapped
          * the framebuffer memory region to.
@@ -172,6 +173,9 @@ struct imxfb_info {
                                 cmap_static:1,
                                 unused:30;
 
+        struct imx_fb_videomode *mode;
+        int                     num_modes;
+
         void (*lcd_power)(int);
         void (*backlight_power)(int);
 };
@@ -298,6 +302,18 @@ static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
         return ret;
 }
 
+static const struct imx_fb_videomode *imxfb_find_mode(struct imxfb_info *fbi)
+{
+        struct imx_fb_videomode *m;
+        int i;
+
+        for (i = 0, m = &fbi->mode[0]; i < fbi->num_modes; i++, m++) {
+                if (!strcmp(m->mode.name, fb_mode))
+                        return m;
+        }
+        return NULL;
+}
+
 /*
  *  imxfb_check_var():
  *    Round up in the following order: bits_per_pixel, xres,
@@ -308,35 +324,81 @@ static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 {
         struct imxfb_info *fbi = info->par;
         struct imxfb_rgb *rgb;
+        const struct imx_fb_videomode *imxfb_mode;
+        unsigned long lcd_clk;
+        unsigned long long tmp;
+        u32 pcr = 0;
 
         if (var->xres < MIN_XRES)
                 var->xres = MIN_XRES;
         if (var->yres < MIN_YRES)
                 var->yres = MIN_YRES;
-        if (var->xres > fbi->max_xres)
-                var->xres = fbi->max_xres;
-        if (var->yres > fbi->max_yres)
-                var->yres = fbi->max_yres;
-        var->xres_virtual = max(var->xres_virtual, var->xres);
-        var->yres_virtual = max(var->yres_virtual, var->yres);
+
+        imxfb_mode = imxfb_find_mode(fbi);
+        if (!imxfb_mode)
+                return -EINVAL;
+
+        var->xres               = imxfb_mode->mode.xres;
+        var->yres               = imxfb_mode->mode.yres;
+        var->bits_per_pixel     = imxfb_mode->bpp;
+        var->pixclock           = imxfb_mode->mode.pixclock;
+        var->hsync_len          = imxfb_mode->mode.hsync_len;
+        var->left_margin        = imxfb_mode->mode.left_margin;
+        var->right_margin       = imxfb_mode->mode.right_margin;
+        var->vsync_len          = imxfb_mode->mode.vsync_len;
+        var->upper_margin       = imxfb_mode->mode.upper_margin;
+        var->lower_margin       = imxfb_mode->mode.lower_margin;
+        var->sync               = imxfb_mode->mode.sync;
+        var->xres_virtual       = max(var->xres_virtual, var->xres);
+        var->yres_virtual       = max(var->yres_virtual, var->yres);
 
         pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel);
+
+        lcd_clk = clk_get_rate(fbi->clk);
+
+        tmp = var->pixclock * (unsigned long long)lcd_clk;
+
+        do_div(tmp, 1000000);
+
+        if (do_div(tmp, 1000000) > 500000)
+                tmp++;
+
+        pcr = (unsigned int)tmp;
+
+        if (--pcr > 0x3F) {
+                pcr = 0x3F;
+                printk(KERN_WARNING "Must limit pixel clock to %luHz\n",
+                                lcd_clk / pcr);
+        }
+
         switch (var->bits_per_pixel) {
         case 32:
+                pcr |= PCR_BPIX_18;
                 rgb = &def_rgb_18;
                 break;
         case 16:
         default:
-                if (fbi->pcr & PCR_TFT)
+                if (cpu_is_mx1())
+                        pcr |= PCR_BPIX_12;
+                else
+                        pcr |= PCR_BPIX_16;
+
+                if (imxfb_mode->pcr & PCR_TFT)
                         rgb = &def_rgb_16_tft;
                 else
                         rgb = &def_rgb_16_stn;
                 break;
         case 8:
+                pcr |= PCR_BPIX_8;
                 rgb = &def_rgb_8;
                 break;
         }
 
+        /* add sync polarities */
+        pcr |= imxfb_mode->pcr & ~(0x3f | (7 << 25));
+
+        fbi->pcr = pcr;
+
         /*
          * Copy the RGB parameters for this display
          * from the machine specific parameters.
@@ -393,10 +455,6 @@ static void imxfb_enable_controller(struct imxfb_info *fbi)
 
         writel(fbi->screen_dma, fbi->regs + LCDC_SSA);
 
-        /* physical screen start address            */
-        writel(VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4),
-                fbi->regs + LCDC_VPW);
-
         /* panning offset 0 (0 pixel offset)        */
         writel(0x00000000, fbi->regs + LCDC_POS);
 
@@ -468,8 +526,6 @@ static struct fb_ops imxfb_ops = {
 static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info)
 {
         struct imxfb_info *fbi = info->par;
-        unsigned int pcr, lcd_clk;
-        unsigned long long tmp;
 
         pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
                 var->xres, var->hsync_len,
@@ -505,6 +561,10 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
                         info->fix.id, var->lower_margin);
 #endif
 
+        /* physical screen start address            */
+        writel(VPW_VPW(var->xres * var->bits_per_pixel / 8 / 4),
+                fbi->regs + LCDC_VPW);
+
         writel(HCR_H_WIDTH(var->hsync_len - 1) |
                 HCR_H_WAIT_1(var->right_margin - 1) |
                 HCR_H_WAIT_2(var->left_margin - 3),
@@ -518,22 +578,7 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
         writel(SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres),
                         fbi->regs + LCDC_SIZE);
 
-        lcd_clk = clk_get_rate(fbi->clk);
-        tmp = var->pixclock * (unsigned long long)lcd_clk;
-        do_div(tmp, 1000000);
-        if (do_div(tmp, 1000000) > 500000)
-                tmp++;
-        pcr = (unsigned int)tmp;
-        if (--pcr > 0x3F) {
-                pcr = 0x3F;
-                printk(KERN_WARNING "Must limit pixel clock to %uHz\n",
-                                lcd_clk / pcr);
-        }
-
-        /* add sync polarities */
-        pcr |= fbi->pcr & ~0x3F;
-
-        writel(pcr, fbi->regs + LCDC_PCR);
+        writel(fbi->pcr, fbi->regs + LCDC_PCR);
         writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
         writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
         writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
@@ -575,6 +620,8 @@ static int __init imxfb_init_fbinfo(struct platform_device *pdev)
         struct imx_fb_platform_data *pdata = pdev->dev.platform_data;
         struct fb_info *info = dev_get_drvdata(&pdev->dev);
         struct imxfb_info *fbi = info->par;
+        struct imx_fb_videomode *m;
+        int i;
 
         pr_debug("%s\n",__func__);
 
@@ -603,35 +650,18 @@ static int __init imxfb_init_fbinfo(struct platform_device *pdev)
         info->fbops                     = &imxfb_ops;
         info->flags                     = FBINFO_FLAG_DEFAULT |
                                           FBINFO_READS_FAST;
-
-        fbi->max_xres                   = pdata->xres;
-        info->var.xres                  = pdata->xres;
-        info->var.xres_virtual          = pdata->xres;
-        fbi->max_yres                   = pdata->yres;
-        info->var.yres                  = pdata->yres;
-        info->var.yres_virtual          = pdata->yres;
-        fbi->max_bpp                    = pdata->bpp;
-        info->var.bits_per_pixel        = pdata->bpp;
-        info->var.nonstd                = pdata->nonstd;
-        info->var.pixclock              = pdata->pixclock;
-        info->var.hsync_len             = pdata->hsync_len;
-        info->var.left_margin           = pdata->left_margin;
-        info->var.right_margin          = pdata->right_margin;
-        info->var.vsync_len             = pdata->vsync_len;
-        info->var.upper_margin          = pdata->upper_margin;
-        info->var.lower_margin          = pdata->lower_margin;
-        info->var.sync                  = pdata->sync;
         info->var.grayscale             = pdata->cmap_greyscale;
         fbi->cmap_inverse               = pdata->cmap_inverse;
         fbi->cmap_static                = pdata->cmap_static;
-        fbi->pcr                        = pdata->pcr;
         fbi->lscr1                      = pdata->lscr1;
         fbi->dmacr                      = pdata->dmacr;
         fbi->pwmr                       = pdata->pwmr;
         fbi->lcd_power                  = pdata->lcd_power;
         fbi->backlight_power            = pdata->backlight_power;
-        info->fix.smem_len              = fbi->max_xres * fbi->max_yres *
-                                          fbi->max_bpp / 8;
+
+        for (i = 0, m = &pdata->mode[0]; i < pdata->num_modes; i++, m++)
+                info->fix.smem_len = max_t(size_t, info->fix.smem_len,
+                                m->mode.xres * m->mode.yres * m->bpp / 8);
 
         return 0;
 }
@@ -642,9 +672,9 @@ static int __init imxfb_probe(struct platform_device *pdev)
         struct fb_info *info;
         struct imx_fb_platform_data *pdata;
         struct resource *res;
-        int ret;
+        int ret, i;
 
-        printk("i.MX Framebuffer driver\n");
+        dev_info(&pdev->dev, "i.MX Framebuffer driver\n");
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!res)
@@ -662,6 +692,9 @@ static int __init imxfb_probe(struct platform_device *pdev)
 
         fbi = info->par;
 
+        if (!fb_mode)
+                fb_mode = pdata->mode[0].mode.name;
+
         platform_set_drvdata(pdev, info);
 
         ret = imxfb_init_fbinfo(pdev);
@@ -684,7 +717,7 @@ static int __init imxfb_probe(struct platform_device *pdev)
 
         fbi->regs = ioremap(res->start, resource_size(res));
         if (fbi->regs == NULL) {
-                printk(KERN_ERR"Cannot map frame buffer registers\n");
+                dev_err(&pdev->dev, "Cannot map frame buffer registers\n");
                 goto failed_ioremap;
         }
 
@@ -719,6 +752,13 @@ static int __init imxfb_probe(struct platform_device *pdev)
                         goto failed_platform_init;
         }
 
+        fbi->mode = pdata->mode;
+        fbi->num_modes = pdata->num_modes;
+
+        INIT_LIST_HEAD(&info->modelist);
+        for (i = 0; i < pdata->num_modes; i++)
+                fb_add_videomode(&pdata->mode[i].mode, &info->modelist);
+
         /*
          * This makes sure that our colour bitfield
          * descriptors are correctly initialised.
@@ -754,7 +794,7 @@ failed_map:
 failed_getclock:
         iounmap(fbi->regs);
 failed_ioremap:
-        release_mem_region(res->start, res->end - res->start);
+        release_mem_region(res->start, resource_size(res));
 failed_req:
         kfree(info->pseudo_palette);
 failed_init:
@@ -785,7 +825,7 @@ static int __devexit imxfb_remove(struct platform_device *pdev)
         framebuffer_release(info);
 
         iounmap(fbi->regs);
-        release_mem_region(res->start, res->end - res->start + 1);
+        release_mem_region(res->start, resource_size(res));
         clk_disable(fbi->clk);
         clk_put(fbi->clk);
 
@@ -811,8 +851,34 @@ static struct platform_driver imxfb_driver = {
         },
 };
 
+static int imxfb_setup(void)
+{
+#ifndef MODULE
+        char *opt, *options = NULL;
+
+        if (fb_get_options("imxfb", &options))
+                return -ENODEV;
+
+        if (!options || !*options)
+                return 0;
+
+        while ((opt = strsep(&options, ",")) != NULL) {
+                if (!*opt)
+                        continue;
+                else
+                        fb_mode = opt;
+        }
+#endif
+        return 0;
+}
+
 int __init imxfb_init(void)
 {
+        int ret = imxfb_setup();
+
+        if (ret < 0)
+                return ret;
+
         return platform_driver_probe(&imxfb_driver, imxfb_probe);
 }