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-rw-r--r--arch/powerpc/include/asm/mmu-book3e.h12
-rw-r--r--arch/powerpc/include/asm/reg_booke.h6
-rw-r--r--arch/powerpc/mm/tlb_nohash_low.S2
3 files changed, 12 insertions, 8 deletions
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index d74580469361..74695816205c 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -114,6 +114,18 @@
114 114
115#define MAS7_RPN 0xFFFFFFFF 115#define MAS7_RPN 0xFFFFFFFF
116 116
117/* Bit definitions for MMUCSR0 */
118#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
119#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
120#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
121#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
122#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
123 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
124#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
125#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
126#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
127#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
128
117/* TLBnCFG encoding */ 129/* TLBnCFG encoding */
118#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ 130#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
119#define TLBnCFG_HES 0x00002000 /* HW select supported */ 131#define TLBnCFG_HES 0x00002000 /* HW select supported */
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 2c9c706e6448..9bb81d99b765 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -430,12 +430,6 @@
430#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ 430#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
431#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ 431#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
432 432
433/* Bit definitions for MMUCSR0 */
434#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
435#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
436#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
437#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
438
439/* Bit definitions for SGR. */ 433/* Bit definitions for SGR. */
440#define SGR_NORMAL 0 /* Speculative fetching allowed. */ 434#define SGR_NORMAL 0 /* Speculative fetching allowed. */
441#define SGR_GUARDED 1 /* Speculative fetching disallowed. */ 435#define SGR_GUARDED 1 /* Speculative fetching disallowed. */
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index 7bcd9fbf6cc6..bbdc5b577b85 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -124,8 +124,6 @@ _GLOBAL(_tlbil_pid)
124 * to have the larger code path before the _SECTION_ELSE 124 * to have the larger code path before the _SECTION_ELSE
125 */ 125 */
126 126
127#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
128 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
129/* 127/*
130 * Flush MMU TLB on the local processor 128 * Flush MMU TLB on the local processor
131 */ 129 */