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-rw-r--r--arch/arm/plat-s3c64xx/s3c6400-clock.c49
1 files changed, 5 insertions, 44 deletions
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index ffd56deb9e81..aba08c7d312f 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -360,10 +360,6 @@ static struct clksrc_clk clk_mmc0 = {
360 .id = 0, 360 .id = 0,
361 .ctrlbit = S3C_CLKCON_SCLK_MMC0, 361 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
362 .enable = s3c64xx_sclk_ctrl, 362 .enable = s3c64xx_sclk_ctrl,
363 .set_parent = s3c64xx_setparent_clksrc,
364 .get_rate = s3c64xx_getrate_clksrc,
365 .set_rate = s3c64xx_setrate_clksrc,
366 .round_rate = s3c64xx_roundrate_clksrc,
367 }, 363 },
368 .shift = S3C6400_CLKSRC_MMC0_SHIFT, 364 .shift = S3C6400_CLKSRC_MMC0_SHIFT,
369 .mask = S3C6400_CLKSRC_MMC0_MASK, 365 .mask = S3C6400_CLKSRC_MMC0_MASK,
@@ -378,10 +374,6 @@ static struct clksrc_clk clk_mmc1 = {
378 .id = 1, 374 .id = 1,
379 .ctrlbit = S3C_CLKCON_SCLK_MMC1, 375 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
380 .enable = s3c64xx_sclk_ctrl, 376 .enable = s3c64xx_sclk_ctrl,
381 .get_rate = s3c64xx_getrate_clksrc,
382 .set_rate = s3c64xx_setrate_clksrc,
383 .set_parent = s3c64xx_setparent_clksrc,
384 .round_rate = s3c64xx_roundrate_clksrc,
385 }, 377 },
386 .shift = S3C6400_CLKSRC_MMC1_SHIFT, 378 .shift = S3C6400_CLKSRC_MMC1_SHIFT,
387 .mask = S3C6400_CLKSRC_MMC1_MASK, 379 .mask = S3C6400_CLKSRC_MMC1_MASK,
@@ -396,10 +388,6 @@ static struct clksrc_clk clk_mmc2 = {
396 .id = 2, 388 .id = 2,
397 .ctrlbit = S3C_CLKCON_SCLK_MMC2, 389 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
398 .enable = s3c64xx_sclk_ctrl, 390 .enable = s3c64xx_sclk_ctrl,
399 .get_rate = s3c64xx_getrate_clksrc,
400 .set_rate = s3c64xx_setrate_clksrc,
401 .set_parent = s3c64xx_setparent_clksrc,
402 .round_rate = s3c64xx_roundrate_clksrc,
403 }, 391 },
404 .shift = S3C6400_CLKSRC_MMC2_SHIFT, 392 .shift = S3C6400_CLKSRC_MMC2_SHIFT,
405 .mask = S3C6400_CLKSRC_MMC2_MASK, 393 .mask = S3C6400_CLKSRC_MMC2_MASK,
@@ -414,10 +402,6 @@ static struct clksrc_clk clk_usbhost = {
414 .id = -1, 402 .id = -1,
415 .ctrlbit = S3C_CLKCON_SCLK_UHOST, 403 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
416 .enable = s3c64xx_sclk_ctrl, 404 .enable = s3c64xx_sclk_ctrl,
417 .set_parent = s3c64xx_setparent_clksrc,
418 .get_rate = s3c64xx_getrate_clksrc,
419 .set_rate = s3c64xx_setrate_clksrc,
420 .round_rate = s3c64xx_roundrate_clksrc,
421 }, 405 },
422 .shift = S3C6400_CLKSRC_UHOST_SHIFT, 406 .shift = S3C6400_CLKSRC_UHOST_SHIFT,
423 .mask = S3C6400_CLKSRC_UHOST_MASK, 407 .mask = S3C6400_CLKSRC_UHOST_MASK,
@@ -432,10 +416,6 @@ static struct clksrc_clk clk_uart_uclk1 = {
432 .id = -1, 416 .id = -1,
433 .ctrlbit = S3C_CLKCON_SCLK_UART, 417 .ctrlbit = S3C_CLKCON_SCLK_UART,
434 .enable = s3c64xx_sclk_ctrl, 418 .enable = s3c64xx_sclk_ctrl,
435 .set_parent = s3c64xx_setparent_clksrc,
436 .get_rate = s3c64xx_getrate_clksrc,
437 .set_rate = s3c64xx_setrate_clksrc,
438 .round_rate = s3c64xx_roundrate_clksrc,
439 }, 419 },
440 .shift = S3C6400_CLKSRC_UART_SHIFT, 420 .shift = S3C6400_CLKSRC_UART_SHIFT,
441 .mask = S3C6400_CLKSRC_UART_MASK, 421 .mask = S3C6400_CLKSRC_UART_MASK,
@@ -452,10 +432,6 @@ static struct clksrc_clk clk_spi0 = {
452 .id = 0, 432 .id = 0,
453 .ctrlbit = S3C_CLKCON_SCLK_SPI0, 433 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
454 .enable = s3c64xx_sclk_ctrl, 434 .enable = s3c64xx_sclk_ctrl,
455 .set_parent = s3c64xx_setparent_clksrc,
456 .get_rate = s3c64xx_getrate_clksrc,
457 .set_rate = s3c64xx_setrate_clksrc,
458 .round_rate = s3c64xx_roundrate_clksrc,
459 }, 435 },
460 .shift = S3C6400_CLKSRC_SPI0_SHIFT, 436 .shift = S3C6400_CLKSRC_SPI0_SHIFT,
461 .mask = S3C6400_CLKSRC_SPI0_MASK, 437 .mask = S3C6400_CLKSRC_SPI0_MASK,
@@ -470,10 +446,6 @@ static struct clksrc_clk clk_spi1 = {
470 .id = 1, 446 .id = 1,
471 .ctrlbit = S3C_CLKCON_SCLK_SPI1, 447 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
472 .enable = s3c64xx_sclk_ctrl, 448 .enable = s3c64xx_sclk_ctrl,
473 .set_parent = s3c64xx_setparent_clksrc,
474 .get_rate = s3c64xx_getrate_clksrc,
475 .set_rate = s3c64xx_setrate_clksrc,
476 .round_rate = s3c64xx_roundrate_clksrc,
477 }, 449 },
478 .shift = S3C6400_CLKSRC_SPI1_SHIFT, 450 .shift = S3C6400_CLKSRC_SPI1_SHIFT,
479 .mask = S3C6400_CLKSRC_SPI1_MASK, 451 .mask = S3C6400_CLKSRC_SPI1_MASK,
@@ -516,10 +488,6 @@ static struct clksrc_clk clk_audio0 = {
516 .id = 0, 488 .id = 0,
517 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, 489 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
518 .enable = s3c64xx_sclk_ctrl, 490 .enable = s3c64xx_sclk_ctrl,
519 .set_parent = s3c64xx_setparent_clksrc,
520 .get_rate = s3c64xx_getrate_clksrc,
521 .set_rate = s3c64xx_setrate_clksrc,
522 .round_rate = s3c64xx_roundrate_clksrc,
523 }, 491 },
524 .shift = S3C6400_CLKSRC_AUDIO0_SHIFT, 492 .shift = S3C6400_CLKSRC_AUDIO0_SHIFT,
525 .mask = S3C6400_CLKSRC_AUDIO0_MASK, 493 .mask = S3C6400_CLKSRC_AUDIO0_MASK,
@@ -547,10 +515,6 @@ static struct clksrc_clk clk_audio1 = {
547 .id = 1, 515 .id = 1,
548 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, 516 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
549 .enable = s3c64xx_sclk_ctrl, 517 .enable = s3c64xx_sclk_ctrl,
550 .set_parent = s3c64xx_setparent_clksrc,
551 .get_rate = s3c64xx_getrate_clksrc,
552 .set_rate = s3c64xx_setrate_clksrc,
553 .round_rate = s3c64xx_roundrate_clksrc,
554 }, 518 },
555 .shift = S3C6400_CLKSRC_AUDIO1_SHIFT, 519 .shift = S3C6400_CLKSRC_AUDIO1_SHIFT,
556 .mask = S3C6400_CLKSRC_AUDIO1_MASK, 520 .mask = S3C6400_CLKSRC_AUDIO1_MASK,
@@ -565,10 +529,6 @@ static struct clksrc_clk clk_irda = {
565 .id = 0, 529 .id = 0,
566 .ctrlbit = S3C_CLKCON_SCLK_IRDA, 530 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
567 .enable = s3c64xx_sclk_ctrl, 531 .enable = s3c64xx_sclk_ctrl,
568 .set_parent = s3c64xx_setparent_clksrc,
569 .get_rate = s3c64xx_getrate_clksrc,
570 .set_rate = s3c64xx_setrate_clksrc,
571 .round_rate = s3c64xx_roundrate_clksrc,
572 }, 532 },
573 .shift = S3C6400_CLKSRC_IRDA_SHIFT, 533 .shift = S3C6400_CLKSRC_IRDA_SHIFT,
574 .mask = S3C6400_CLKSRC_IRDA_MASK, 534 .mask = S3C6400_CLKSRC_IRDA_MASK,
@@ -592,10 +552,6 @@ static struct clksrc_clk clk_camif = {
592 .id = -1, 552 .id = -1,
593 .ctrlbit = S3C_CLKCON_SCLK_CAM, 553 .ctrlbit = S3C_CLKCON_SCLK_CAM,
594 .enable = s3c64xx_sclk_ctrl, 554 .enable = s3c64xx_sclk_ctrl,
595 .set_parent = s3c64xx_setparent_clksrc,
596 .get_rate = s3c64xx_getrate_clksrc,
597 .set_rate = s3c64xx_setrate_clksrc,
598 .round_rate = s3c64xx_roundrate_clksrc,
599 }, 555 },
600 .shift = 0, 556 .shift = 0,
601 .mask = 0, 557 .mask = 0,
@@ -637,6 +593,11 @@ static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
637 return; 593 return;
638 } 594 }
639 595
596 clk->clk.get_rate = s3c64xx_getrate_clksrc;
597 clk->clk.set_rate = s3c64xx_setrate_clksrc;
598 clk->clk.set_parent = s3c64xx_setparent_clksrc;
599 clk->clk.round_rate = s3c64xx_roundrate_clksrc;
600
640 clk->clk.parent = srcs->sources[clksrc]; 601 clk->clk.parent = srcs->sources[clksrc];
641 602
642 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", 603 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 13:23:35 -0500