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-rw-r--r--arch/sh/boards/mach-sdk7786/Makefile2
-rw-r--r--arch/sh/boards/mach-sdk7786/fpga.c37
-rw-r--r--arch/sh/boards/mach-sdk7786/setup.c78
-rw-r--r--arch/sh/include/mach-sdk7786/mach/fpga.h112
4 files changed, 159 insertions, 70 deletions
diff --git a/arch/sh/boards/mach-sdk7786/Makefile b/arch/sh/boards/mach-sdk7786/Makefile
index f663768429f0..50c8065deaa0 100644
--- a/arch/sh/boards/mach-sdk7786/Makefile
+++ b/arch/sh/boards/mach-sdk7786/Makefile
@@ -1 +1 @@
obj-y := setup.o obj-y := setup.o fpga.o
diff --git a/arch/sh/boards/mach-sdk7786/fpga.c b/arch/sh/boards/mach-sdk7786/fpga.c
new file mode 100644
index 000000000000..99f903c8b238
--- /dev/null
+++ b/arch/sh/boards/mach-sdk7786/fpga.c
@@ -0,0 +1,37 @@
1/*
2 * SDK7786 FPGA Support.
3 *
4 * Copyright (C) 2010 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/bcd.h>
13#include <mach/fpga.h>
14
15#define FPGA_REGS_BASE 0x07fff800
16#define FPGA_REGS_SIZE 0x490
17
18void __iomem *sdk7786_fpga_base;
19
20void __init sdk7786_fpga_init(void)
21{
22 u16 version, date;
23
24 sdk7786_fpga_base = ioremap_nocache(FPGA_REGS_BASE, FPGA_REGS_SIZE);
25 if (unlikely(!sdk7786_fpga_base)) {
26 panic("FPGA remapping failed.\n");
27 return;
28 }
29
30 version = fpga_read_reg(FPGAVR);
31 date = fpga_read_reg(FPGADR);
32
33 pr_info("\tFPGA version:\t%d.%d (built on %d/%d/%d)\n",
34 bcd2bin(version >> 8) & 0xf, bcd2bin(version & 0xf),
35 ((date >> 12) & 0xf) + 2000,
36 (date >> 8) & 0xf, bcd2bin(date & 0xff));
37}
diff --git a/arch/sh/boards/mach-sdk7786/setup.c b/arch/sh/boards/mach-sdk7786/setup.c
index 0e4b1c39742c..8dbbdea9c983 100644
--- a/arch/sh/boards/mach-sdk7786/setup.c
+++ b/arch/sh/boards/mach-sdk7786/setup.c
@@ -18,6 +18,7 @@
18#include <asm/machvec.h> 18#include <asm/machvec.h>
19#include <asm/heartbeat.h> 19#include <asm/heartbeat.h>
20#include <asm/sizes.h> 20#include <asm/sizes.h>
21#include <mach/fpga.h>
21 22
22static struct resource heartbeat_resource = { 23static struct resource heartbeat_resource = {
23 .start = 0x07fff8b0, 24 .start = 0x07fff8b0,
@@ -103,27 +104,17 @@ static struct platform_device *sh7786_devices[] __initdata = {
103 &smbus_pcie_device, 104 &smbus_pcie_device,
104}; 105};
105 106
106#define SBCR_REGS_BASE 0x07fff990
107
108#define SCBR_I2CMEN (1 << 0) /* FPGA I2C master enable */
109#define SCBR_I2CCEN (1 << 1) /* CPU I2C master enable */
110
111static int sdk7786_i2c_setup(void) 107static int sdk7786_i2c_setup(void)
112{ 108{
113 void __iomem *sbcr;
114 unsigned int tmp; 109 unsigned int tmp;
115 110
116 sbcr = ioremap_nocache(SBCR_REGS_BASE, SZ_16);
117
118 /* 111 /*
119 * Hand over I2C control to the FPGA. 112 * Hand over I2C control to the FPGA.
120 */ 113 */
121 tmp = ioread16(sbcr); 114 tmp = fpga_read_reg(SBCR);
122 tmp &= ~SCBR_I2CCEN; 115 tmp &= ~SCBR_I2CCEN;
123 tmp |= SCBR_I2CMEN; 116 tmp |= SCBR_I2CMEN;
124 iowrite16(tmp, sbcr); 117 fpga_write_reg(tmp, SBCR);
125
126 iounmap(sbcr);
127 118
128 return i2c_register_board_info(0, sdk7786_i2c_devices, 119 return i2c_register_board_info(0, sdk7786_i2c_devices,
129 ARRAY_SIZE(sdk7786_i2c_devices)); 120 ARRAY_SIZE(sdk7786_i2c_devices));
@@ -141,43 +132,6 @@ static int __init sdk7786_devices_setup(void)
141} 132}
142__initcall(sdk7786_devices_setup); 133__initcall(sdk7786_devices_setup);
143 134
144#define FPGA_REGS_BASE 0x07fff800
145#define FPGA_REGS_SIZE 1152
146
147#define INTASR 0x010
148#define INTAMR 0x020
149#define INTBSR 0x090
150#define INTBMR 0x0a0
151#define INTMSR 0x130
152
153#define IASELR1 0x210
154#define IASELR2 0x220
155#define IASELR3 0x230
156#define IASELR4 0x240
157#define IASELR5 0x250
158#define IASELR6 0x260
159#define IASELR7 0x270
160#define IASELR8 0x280
161#define IASELR9 0x290
162#define IASELR10 0x2a0
163#define IASELR11 0x2b0
164#define IASELR12 0x2c0
165#define IASELR13 0x2d0
166#define IASELR14 0x2e0
167#define IASELR15 0x2f0
168
169static void __iomem *fpga_regs;
170
171static u16 fpga_read_reg(unsigned int reg)
172{
173 return __raw_readw(fpga_regs + reg);
174}
175
176static void fpga_write_reg(u16 val, unsigned int reg)
177{
178 __raw_writew(val, fpga_regs + reg);
179}
180
181enum { 135enum {
182 ATA_IRQ_BIT = 1, 136 ATA_IRQ_BIT = 1,
183 SPI_BUSY_BIT = 2, 137 SPI_BUSY_BIT = 2,
@@ -197,12 +151,6 @@ static void __init init_sdk7786_IRQ(void)
197{ 151{
198 unsigned int tmp; 152 unsigned int tmp;
199 153
200 fpga_regs = ioremap_nocache(FPGA_REGS_BASE, FPGA_REGS_SIZE);
201 if (!fpga_regs) {
202 printk(KERN_ERR "Couldn't map FPGA registers\n");
203 return;
204 }
205
206 /* Enable priority encoding for all IRLs */ 154 /* Enable priority encoding for all IRLs */
207 fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR); 155 fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR);
208 156
@@ -219,21 +167,9 @@ static void __init init_sdk7786_IRQ(void)
219 plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK); 167 plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
220} 168}
221 169
222#define MODSWR_REGS 0x07fff830
223
224static int sdk7786_mode_pins(void) 170static int sdk7786_mode_pins(void)
225{ 171{
226 void __iomem *modswr; 172 return fpga_read_reg(MODSWR);
227 int pin_states;
228
229 modswr = ioremap_nocache(MODSWR_REGS, SZ_16);
230 if (!modswr)
231 return -ENXIO;
232
233 pin_states = ioread16(modswr);
234 iounmap(modswr);
235
236 return pin_states;
237} 173}
238 174
239static int sdk7786_clk_init(void) 175static int sdk7786_clk_init(void)
@@ -260,7 +196,11 @@ static int sdk7786_clk_init(void)
260/* Initialize the board */ 196/* Initialize the board */
261static void __init sdk7786_setup(char **cmdline_p) 197static void __init sdk7786_setup(char **cmdline_p)
262{ 198{
263 printk(KERN_INFO "Renesas Technology Corp. SDK7786 support.\n"); 199 pr_info("Renesas Technology Europe SDK7786 support:\n");
200
201 sdk7786_fpga_init();
202
203 pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
264} 204}
265 205
266/* 206/*
diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h
new file mode 100644
index 000000000000..a85d9853d34f
--- /dev/null
+++ b/arch/sh/include/mach-sdk7786/mach/fpga.h
@@ -0,0 +1,112 @@
1#ifndef __MACH_SDK7786_FPGA_H
2#define __MACH_SDK7786_FPGA_H
3
4#include <linux/io.h>
5#include <linux/types.h>
6#include <linux/bitops.h>
7
8#define SRSTR 0x000
9#define INTASR 0x010
10#define INTAMR 0x020
11#define MODSWR 0x030
12#define INTTESTR 0x040
13#define SYSSR 0x050
14#define NRGPR 0x060
15#define NMISR 0x070
16
17#define NMIMR 0x080
18#define NMIMR_MAN_NMIM BIT(0) /* Manual NMI mask */
19#define NMIMR_AUX_NMIM BIT(1) /* Auxiliary NMI mask */
20
21#define INTBSR 0x090
22#define INTBMR 0x0a0
23#define USRLEDR 0x0b0
24#define MAPSWR 0x0c0
25#define FPGAVR 0x0d0
26#define FPGADR 0x0e0
27#define PCBRR 0x0f0
28#define RSR 0x100
29#define EXTASR 0x110
30#define SPCAR 0x120
31#define INTMSR 0x130
32#define PCIECR 0x140
33#define FAER 0x150
34#define USRGPIR 0x160
35/* 0x170 reserved */
36#define LCLASR 0x180
37
38#define SBCR 0x190
39#define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */
40#define SCBR_I2CCEN BIT(1) /* CPU I2C master enable */
41
42#define PWRCR 0x1a0
43#define SPCBR 0x1b0
44#define SPICR 0x1c0
45#define SPIDR 0x1d0
46#define I2CCR 0x1e0
47#define I2CDR 0x1f0
48#define FPGACR 0x200
49#define IASELR1 0x210
50#define IASELR2 0x220
51#define IASELR3 0x230
52#define IASELR4 0x240
53#define IASELR5 0x250
54#define IASELR6 0x260
55#define IASELR7 0x270
56#define IASELR8 0x280
57#define IASELR9 0x290
58#define IASELR10 0x2a0
59#define IASELR11 0x2b0
60#define IASELR12 0x2c0
61#define IASELR13 0x2d0
62#define IASELR14 0x2e0
63#define IASELR15 0x2f0
64/* 0x300 reserved */
65#define IBSELR1 0x310
66#define IBSELR2 0x320
67#define IBSELR3 0x330
68#define IBSELR4 0x340
69#define IBSELR5 0x350
70#define IBSELR6 0x360
71#define IBSELR7 0x370
72#define IBSELR8 0x380
73#define IBSELR9 0x390
74#define IBSELR10 0x3a0
75#define IBSELR11 0x3b0
76#define IBSELR12 0x3c0
77#define IBSELR13 0x3d0
78#define IBSELR14 0x3e0
79#define IBSELR15 0x3f0
80#define USRACR 0x400
81#define BEEPR 0x410
82#define USRLCDR 0x420
83#define SMBCR 0x430
84#define SMBDR 0x440
85#define USBCR 0x450
86#define AMSR 0x460
87#define ACCR 0x470
88#define SDIFCR 0x480
89
90/* arch/sh/boards/mach-sdk7786/fpga.c */
91extern void __iomem *sdk7786_fpga_base;
92extern void sdk7786_fpga_init(void);
93
94#define SDK7786_FPGA_REGADDR(reg) (sdk7786_fpga_base + (reg))
95
96/*
97 * A convenience wrapper from register offset to internal I2C address,
98 * when the FPGA is in I2C slave mode.
99 */
100#define SDK7786_FPGA_I2CADDR(reg) ((reg) >> 3)
101
102static inline u16 fpga_read_reg(unsigned int reg)
103{
104 return ioread16(sdk7786_fpga_base + reg);
105}
106
107static inline void fpga_write_reg(u16 val, unsigned int reg)
108{
109 iowrite16(val, sdk7786_fpga_base + reg);
110}
111
112#endif /* __MACH_SDK7786_FPGA_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-11 06:35:12 -0500