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-rw-r--r--arch/arm/mach-s5pv210/clock.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index f57fa1ee6ff0..d5acd261795c 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -78,6 +78,15 @@ static struct clksrc_clk clk_armclk = {
78 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, 78 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
79}; 79};
80 80
81static struct clksrc_clk clk_hclk_msys = {
82 .clk = {
83 .name = "hclk_msys",
84 .id = -1,
85 .parent = &clk_armclk.clk,
86 },
87 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
88};
89
81static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) 90static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
82{ 91{
83 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable); 92 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
@@ -98,11 +107,6 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
98 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); 107 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
99} 108}
100 109
101static struct clk clk_h200 = {
102 .name = "hclk200",
103 .id = -1,
104};
105
106static struct clk clk_h100 = { 110static struct clk clk_h100 = {
107 .name = "hclk100", 111 .name = "hclk100",
108 .id = -1, 112 .id = -1,
@@ -134,7 +138,6 @@ static struct clk clk_p66 = {
134}; 138};
135 139
136static struct clk *sys_clks[] = { 140static struct clk *sys_clks[] = {
137 &clk_h200,
138 &clk_h100, 141 &clk_h100,
139 &clk_h166, 142 &clk_h166,
140 &clk_h133, 143 &clk_h133,
@@ -349,6 +352,7 @@ static struct clksrc_clk *sysclks[] = {
349 &clk_mout_epll, 352 &clk_mout_epll,
350 &clk_mout_mpll, 353 &clk_mout_mpll,
351 &clk_armclk, 354 &clk_armclk,
355 &clk_hclk_msys,
352}; 356};
353 357
354#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 358#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@@ -358,7 +362,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
358 struct clk *xtal_clk; 362 struct clk *xtal_clk;
359 unsigned long xtal; 363 unsigned long xtal;
360 unsigned long armclk; 364 unsigned long armclk;
361 unsigned long hclk200; 365 unsigned long hclk_msys;
362 unsigned long hclk166; 366 unsigned long hclk166;
363 unsigned long hclk133; 367 unsigned long hclk133;
364 unsigned long pclk100; 368 unsigned long pclk100;
@@ -398,10 +402,7 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
398 apll, mpll, epll); 402 apll, mpll, epll);
399 403
400 armclk = clk_get_rate(&clk_armclk.clk); 404 armclk = clk_get_rate(&clk_armclk.clk);
401 if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX200_MASK) 405 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
402 hclk200 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
403 else
404 hclk200 = armclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
405 406
406 if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX166_MASK) { 407 if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX166_MASK) {
407 hclk166 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M); 408 hclk166 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
@@ -415,13 +416,13 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
415 } else 416 } else
416 hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133); 417 hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
417 418
418 pclk100 = hclk200 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100); 419 pclk100 = hclk_msys / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100);
419 pclk83 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83); 420 pclk83 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
420 pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66); 421 pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
421 422
422 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \ 423 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \
423 HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", 424 HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
424 armclk, hclk200, hclk166, hclk133, pclk100, pclk83, pclk66); 425 armclk, hclk_msys, hclk166, hclk133, pclk100, pclk83, pclk66);
425 426
426 clk_f.rate = armclk; 427 clk_f.rate = armclk;
427 clk_h.rate = hclk133; 428 clk_h.rate = hclk133;
@@ -430,7 +431,6 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
430 clk_p83.rate = pclk83; 431 clk_p83.rate = pclk83;
431 clk_h133.rate = hclk133; 432 clk_h133.rate = hclk133;
432 clk_h166.rate = hclk166; 433 clk_h166.rate = hclk166;
433 clk_h200.rate = hclk200;
434 434
435 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) 435 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
436 s3c_set_clksrc(&clksrcs[ptr], true); 436 s3c_set_clksrc(&clksrcs[ptr], true);