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-rw-r--r--arch/arm/common/vic.c8
-rw-r--r--arch/arm/include/asm/hardware/vic.h10
2 files changed, 10 insertions, 8 deletions
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index f1e4b8f60cab..ecf0bfbab107 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -69,12 +69,12 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
69 /* 69 /*
70 * Make sure we clear all existing interrupts 70 * Make sure we clear all existing interrupts
71 */ 71 */
72 writel(0, base + VIC_VECT_ADDR); 72 writel(0, base + VIC_PL190_VECT_ADDR);
73 for (i = 0; i < 19; i++) { 73 for (i = 0; i < 19; i++) {
74 unsigned int value; 74 unsigned int value;
75 75
76 value = readl(base + VIC_VECT_ADDR); 76 value = readl(base + VIC_PL190_VECT_ADDR);
77 writel(value, base + VIC_VECT_ADDR); 77 writel(value, base + VIC_PL190_VECT_ADDR);
78 } 78 }
79 79
80 for (i = 0; i < 16; i++) { 80 for (i = 0; i < 16; i++) {
@@ -82,7 +82,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
82 writel(VIC_VECT_CNTL_ENABLE | i, reg); 82 writel(VIC_VECT_CNTL_ENABLE | i, reg);
83 } 83 }
84 84
85 writel(32, base + VIC_DEF_VECT_ADDR); 85 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
86 86
87 for (i = 0; i < 32; i++) { 87 for (i = 0; i < 32; i++) {
88 unsigned int irq = irq_start + i; 88 unsigned int irq = irq_start + i;
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
index 263f2c362a30..f87328d4a180 100644
--- a/arch/arm/include/asm/hardware/vic.h
+++ b/arch/arm/include/asm/hardware/vic.h
@@ -29,15 +29,17 @@
29#define VIC_INT_SOFT 0x18 29#define VIC_INT_SOFT 0x18
30#define VIC_INT_SOFT_CLEAR 0x1c 30#define VIC_INT_SOFT_CLEAR 0x1c
31#define VIC_PROTECT 0x20 31#define VIC_PROTECT 0x20
32#define VIC_VECT_ADDR 0x30 32#define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */
33#define VIC_DEF_VECT_ADDR 0x34 33#define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */
34 34
35#define VIC_VECT_ADDR0 0x100 /* 0 to 15 */ 35#define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */
36#define VIC_VECT_CNTL0 0x200 /* 0 to 15 */ 36#define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */
37#define VIC_ITCR 0x300 /* VIC test control register */ 37#define VIC_ITCR 0x300 /* VIC test control register */
38 38
39#define VIC_VECT_CNTL_ENABLE (1 << 5) 39#define VIC_VECT_CNTL_ENABLE (1 << 5)
40 40
41#define VIC_PL192_VECT_ADDR 0xF00
42
41#ifndef __ASSEMBLY__ 43#ifndef __ASSEMBLY__
42void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources); 44void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources);
43#endif 45#endif