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-rw-r--r--Documentation/powerpc/dts-bindings/fsl/dma.txt34
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/esdhc.txt24
-rw-r--r--arch/powerpc/Kconfig19
-rw-r--r--arch/powerpc/boot/Makefile9
-rw-r--r--arch/powerpc/boot/cuboot-amigaone.c35
-rw-r--r--arch/powerpc/boot/dts/amigaone.dts173
-rw-r--r--arch/powerpc/boot/dts/cm5200.dts49
-rw-r--r--arch/powerpc/boot/dts/digsy_mtc.dts254
-rw-r--r--arch/powerpc/boot/dts/gef_sbc310.dts364
-rw-r--r--arch/powerpc/boot/dts/lite5200.dts52
-rw-r--r--arch/powerpc/boot/dts/lite5200b.dts63
-rw-r--r--arch/powerpc/boot/dts/media5200.dts318
-rw-r--r--arch/powerpc/boot/dts/motionpro.dts42
-rw-r--r--arch/powerpc/boot/dts/mpc8315erdb.dts64
-rw-r--r--arch/powerpc/boot/dts/mpc8377_mds.dts71
-rw-r--r--arch/powerpc/boot/dts/mpc8377_rdb.dts102
-rw-r--r--arch/powerpc/boot/dts/mpc8378_mds.dts71
-rw-r--r--arch/powerpc/boot/dts/mpc8378_rdb.dts102
-rw-r--r--arch/powerpc/boot/dts/mpc8379_mds.dts7
-rw-r--r--arch/powerpc/boot/dts/mpc8379_rdb.dts38
-rw-r--r--arch/powerpc/boot/dts/pcm030.dts182
-rw-r--r--arch/powerpc/boot/dts/tqm5200.dts32
-rw-r--r--arch/powerpc/boot/dts/tqm8540.dts5
-rw-r--r--arch/powerpc/boot/dts/tqm8541.dts5
-rw-r--r--arch/powerpc/boot/dts/tqm8548-bigflash.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8548.dts9
-rw-r--r--arch/powerpc/boot/dts/tqm8555.dts5
-rw-r--r--arch/powerpc/boot/dts/tqm8560.dts9
-rw-r--r--arch/powerpc/boot/serial.c3
-rwxr-xr-xarch/powerpc/boot/wrapper3
-rw-r--r--arch/powerpc/configs/86xx/gef_sbc310_defconfig1613
-rw-r--r--arch/powerpc/configs/amigaone_defconfig1636
-rw-r--r--arch/powerpc/include/asm/highmem.h2
-rw-r--r--arch/powerpc/include/asm/machdep.h2
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc32.h57
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc64.h29
-rw-r--r--arch/powerpc/include/asm/pgtable.h84
-rw-r--r--arch/powerpc/include/asm/reg_booke.h1
-rw-r--r--arch/powerpc/kernel/Makefile1
-rw-r--r--arch/powerpc/kernel/cpu_setup_fsl_booke.S31
-rw-r--r--arch/powerpc/kernel/cputable.c8
-rw-r--r--arch/powerpc/kernel/head_booke.h6
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S81
-rw-r--r--arch/powerpc/kernel/pci-common.c41
-rw-r--r--arch/powerpc/kernel/pci_32.c21
-rw-r--r--arch/powerpc/kernel/pci_64.c19
-rw-r--r--arch/powerpc/kernel/prom.c6
-rw-r--r--arch/powerpc/kernel/setup_64.c7
-rw-r--r--arch/powerpc/mm/fault.c46
-rw-r--r--arch/powerpc/mm/fsl_booke_mmu.c93
-rw-r--r--arch/powerpc/mm/mem.c33
-rw-r--r--arch/powerpc/mm/mmap.c6
-rw-r--r--arch/powerpc/mm/numa.c35
-rw-r--r--arch/powerpc/mm/pgtable.c131
-rw-r--r--arch/powerpc/platforms/52xx/Kconfig12
-rw-r--r--arch/powerpc/platforms/52xx/Makefile3
-rw-r--r--arch/powerpc/platforms/52xx/media5200.c273
-rw-r--r--arch/powerpc/platforms/52xx/mpc5200_simple.c1
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_gpio.c85
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_gpt.c435
-rw-r--r--arch/powerpc/platforms/52xx/mpc52xx_pic.c170
-rw-r--r--arch/powerpc/platforms/83xx/mpc831x_rdb.c2
-rw-r--r--arch/powerpc/platforms/83xx/mpc837x_mds.c10
-rw-r--r--arch/powerpc/platforms/83xx/mpc837x_rdb.c2
-rw-r--r--arch/powerpc/platforms/86xx/Kconfig10
-rw-r--r--arch/powerpc/platforms/86xx/Makefile1
-rw-r--r--arch/powerpc/platforms/86xx/gef_gpio.c36
-rw-r--r--arch/powerpc/platforms/86xx/gef_sbc310.c230
-rw-r--r--arch/powerpc/platforms/Kconfig1
-rw-r--r--arch/powerpc/platforms/Makefile1
-rw-r--r--arch/powerpc/platforms/amigaone/Kconfig18
-rw-r--r--arch/powerpc/platforms/amigaone/Makefile1
-rw-r--r--arch/powerpc/platforms/amigaone/setup.c170
-rw-r--r--arch/powerpc/platforms/chrp/pegasos_eth.c72
-rw-r--r--arch/powerpc/platforms/pseries/eeh_driver.c68
-rw-r--r--arch/powerpc/platforms/pseries/msi.c42
-rw-r--r--arch/powerpc/platforms/pseries/pci_dlpar.c2
-rw-r--r--arch/powerpc/sysdev/cpm2.c3
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c244
-rw-r--r--drivers/macintosh/therm_adt746x.c4
-rw-r--r--drivers/net/fec_mpc52xx.c6
-rw-r--r--drivers/serial/mpc52xx_uart.c40
-rw-r--r--drivers/watchdog/Kconfig2
-rw-r--r--include/linux/pci_ids.h8
-rw-r--r--lib/lmb.c42
85 files changed, 7088 insertions, 1048 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/dma.txt b/Documentation/powerpc/dts-bindings/fsl/dma.txt
index cc453110fc46..0732cdd05ba1 100644
--- a/Documentation/powerpc/dts-bindings/fsl/dma.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/dma.txt
@@ -35,30 +35,30 @@ Example:
35 #address-cells = <1>; 35 #address-cells = <1>;
36 #size-cells = <1>; 36 #size-cells = <1>;
37 compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; 37 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
38 reg = <82a8 4>; 38 reg = <0x82a8 4>;
39 ranges = <0 8100 1a4>; 39 ranges = <0 0x8100 0x1a4>;
40 interrupt-parent = <&ipic>; 40 interrupt-parent = <&ipic>;
41 interrupts = <47 8>; 41 interrupts = <71 8>;
42 cell-index = <0>; 42 cell-index = <0>;
43 dma-channel@0 { 43 dma-channel@0 {
44 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 44 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
45 cell-index = <0>; 45 cell-index = <0>;
46 reg = <0 80>; 46 reg = <0 0x80>;
47 }; 47 };
48 dma-channel@80 { 48 dma-channel@80 {
49 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 49 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
50 cell-index = <1>; 50 cell-index = <1>;
51 reg = <80 80>; 51 reg = <0x80 0x80>;
52 }; 52 };
53 dma-channel@100 { 53 dma-channel@100 {
54 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 54 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
55 cell-index = <2>; 55 cell-index = <2>;
56 reg = <100 80>; 56 reg = <0x100 0x80>;
57 }; 57 };
58 dma-channel@180 { 58 dma-channel@180 {
59 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 59 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
60 cell-index = <3>; 60 cell-index = <3>;
61 reg = <180 80>; 61 reg = <0x180 0x80>;
62 }; 62 };
63 }; 63 };
64 64
@@ -93,36 +93,36 @@ Example:
93 #address-cells = <1>; 93 #address-cells = <1>;
94 #size-cells = <1>; 94 #size-cells = <1>;
95 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; 95 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
96 reg = <21300 4>; 96 reg = <0x21300 4>;
97 ranges = <0 21100 200>; 97 ranges = <0 0x21100 0x200>;
98 cell-index = <0>; 98 cell-index = <0>;
99 dma-channel@0 { 99 dma-channel@0 {
100 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 100 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
101 reg = <0 80>; 101 reg = <0 0x80>;
102 cell-index = <0>; 102 cell-index = <0>;
103 interrupt-parent = <&mpic>; 103 interrupt-parent = <&mpic>;
104 interrupts = <14 2>; 104 interrupts = <20 2>;
105 }; 105 };
106 dma-channel@80 { 106 dma-channel@80 {
107 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 107 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
108 reg = <80 80>; 108 reg = <0x80 0x80>;
109 cell-index = <1>; 109 cell-index = <1>;
110 interrupt-parent = <&mpic>; 110 interrupt-parent = <&mpic>;
111 interrupts = <15 2>; 111 interrupts = <21 2>;
112 }; 112 };
113 dma-channel@100 { 113 dma-channel@100 {
114 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 114 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
115 reg = <100 80>; 115 reg = <0x100 0x80>;
116 cell-index = <2>; 116 cell-index = <2>;
117 interrupt-parent = <&mpic>; 117 interrupt-parent = <&mpic>;
118 interrupts = <16 2>; 118 interrupts = <22 2>;
119 }; 119 };
120 dma-channel@180 { 120 dma-channel@180 {
121 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 121 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
122 reg = <180 80>; 122 reg = <0x180 0x80>;
123 cell-index = <3>; 123 cell-index = <3>;
124 interrupt-parent = <&mpic>; 124 interrupt-parent = <&mpic>;
125 interrupts = <17 2>; 125 interrupts = <23 2>;
126 }; 126 };
127 }; 127 };
128 128
diff --git a/Documentation/powerpc/dts-bindings/fsl/esdhc.txt b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
new file mode 100644
index 000000000000..600846557763
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
@@ -0,0 +1,24 @@
1* Freescale Enhanced Secure Digital Host Controller (eSDHC)
2
3The Enhanced Secure Digital Host Controller provides an interface
4for MMC, SD, and SDIO types of memory cards.
5
6Required properties:
7 - compatible : should be
8 "fsl,<chip>-esdhc", "fsl,mpc8379-esdhc" for MPC83xx processors.
9 "fsl,<chip>-esdhc", "fsl,mpc8536-esdhc" for MPC85xx processors.
10 - reg : should contain eSDHC registers location and length.
11 - interrupts : should contain eSDHC interrupt.
12 - interrupt-parent : interrupt source phandle.
13 - clock-frequency : specifies eSDHC base clock frequency.
14
15Example:
16
17sdhci@2e000 {
18 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
19 reg = <0x2e000 0x1000>;
20 interrupts = <42 0x8>;
21 interrupt-parent = <&ipic>;
22 /* Filled in by U-Boot */
23 clock-frequency = <0>;
24};
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 74cc312c347c..ccdd8de3c558 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -594,6 +594,7 @@ config FSL_SOC
594config FSL_PCI 594config FSL_PCI
595 bool 595 bool
596 select PPC_INDIRECT_PCI 596 select PPC_INDIRECT_PCI
597 select PCI_QUIRKS
597 598
598config 4xx_SOC 599config 4xx_SOC
599 bool 600 bool
@@ -730,6 +731,22 @@ config LOWMEM_SIZE
730 hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL 731 hex "Maximum low memory size (in bytes)" if LOWMEM_SIZE_BOOL
731 default "0x30000000" 732 default "0x30000000"
732 733
734config LOWMEM_CAM_NUM_BOOL
735 bool "Set number of CAMs to use to map low memory"
736 depends on ADVANCED_OPTIONS && FSL_BOOKE
737 help
738 This option allows you to set the maximum number of CAM slots that
739 will be used to map low memory. There are a limited number of slots
740 available and even more limited number that will fit in the L1 MMU.
741 However, using more entries will allow mapping more low memory. This
742 can be useful in optimizing the layout of kernel virtual memory.
743
744 Say N here unless you know what you are doing.
745
746config LOWMEM_CAM_NUM
747 int "Number of CAMs to use to map low memory" if LOWMEM_CAM_NUM_BOOL
748 default 3
749
733config RELOCATABLE 750config RELOCATABLE
734 bool "Build a relocatable kernel (EXPERIMENTAL)" 751 bool "Build a relocatable kernel (EXPERIMENTAL)"
735 depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE 752 depends on EXPERIMENTAL && ADVANCED_OPTIONS && FLATMEM && FSL_BOOKE
@@ -794,7 +811,7 @@ config PHYSICAL_START
794 811
795config PHYSICAL_ALIGN 812config PHYSICAL_ALIGN
796 hex 813 hex
797 default "0x10000000" if FSL_BOOKE 814 default "0x04000000" if FSL_BOOKE
798 help 815 help
799 This value puts the alignment restrictions on physical address 816 This value puts the alignment restrictions on physical address
800 where kernel is loaded and run from. Kernel is compiled for an 817 where kernel is loaded and run from. Kernel is compiled for an
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index e84df338ea29..4458abb67c51 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -70,7 +70,7 @@ src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c
70 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \ 70 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
71 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \ 71 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
72 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \ 72 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
73 cuboot-acadia.c 73 cuboot-acadia.c cuboot-amigaone.c
74src-boot := $(src-wlib) $(src-plat) empty.c 74src-boot := $(src-wlib) $(src-plat) empty.c
75 75
76src-boot := $(addprefix $(obj)/, $(src-boot)) 76src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -235,7 +235,9 @@ image-$(CONFIG_PPC_ADDER875) += cuImage.adder875-uboot \
235 dtbImage.adder875-redboot 235 dtbImage.adder875-redboot
236 236
237# Board ports in arch/powerpc/platform/52xx/Kconfig 237# Board ports in arch/powerpc/platform/52xx/Kconfig
238image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 cuImage.lite5200b 238image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 lite5200.dtb
239image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200b lite5200b.dtb
240image-$(CONFIG_PPC_MEDIA5200) += cuImage.media5200 media5200.dtb
239 241
240# Board ports in arch/powerpc/platform/82xx/Kconfig 242# Board ports in arch/powerpc/platform/82xx/Kconfig
241image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads 243image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads
@@ -274,6 +276,9 @@ image-$(CONFIG_STORCENTER) += cuImage.storcenter
274image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2 276image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2
275image-$(CONFIG_PPC_C2K) += cuImage.c2k 277image-$(CONFIG_PPC_C2K) += cuImage.c2k
276 278
279# Board port in arch/powerpc/platform/amigaone/Kconfig
280image-$(CONFIG_AMIGAONE) += cuImage.amigaone
281
277# For 32-bit powermacs, build the COFF and miboot images 282# For 32-bit powermacs, build the COFF and miboot images
278# as well as the ELF images. 283# as well as the ELF images.
279ifeq ($(CONFIG_PPC32),y) 284ifeq ($(CONFIG_PPC32),y)
diff --git a/arch/powerpc/boot/cuboot-amigaone.c b/arch/powerpc/boot/cuboot-amigaone.c
new file mode 100644
index 000000000000..d5029674030b
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-amigaone.c
@@ -0,0 +1,35 @@
1/*
2 * Old U-boot compatibility for AmigaOne
3 *
4 * Author: Gerhard Pircher (gerhard_pircher@gmx.net)
5 *
6 * Based on cuboot-83xx.c
7 * Copyright (c) 2007 Freescale Semiconductor, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include "ops.h"
15#include "stdio.h"
16#include "cuboot.h"
17
18#include "ppcboot.h"
19
20static bd_t bd;
21
22static void platform_fixups(void)
23{
24 dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
25 dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
26}
27
28void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
29 unsigned long r6, unsigned long r7)
30{
31 CUBOOT_INIT();
32 fdt_init(_dtb_start);
33 serial_console_init();
34 platform_ops.fixups = platform_fixups;
35}
diff --git a/arch/powerpc/boot/dts/amigaone.dts b/arch/powerpc/boot/dts/amigaone.dts
new file mode 100644
index 000000000000..26549fca2ed4
--- /dev/null
+++ b/arch/powerpc/boot/dts/amigaone.dts
@@ -0,0 +1,173 @@
1/*
2 * AmigaOne Device Tree Source
3 *
4 * Copyright 2008 Gerhard Pircher (gerhard_pircher@gmx.net)
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "AmigaOne";
16 compatible = "eyetech,amigaone";
17 coherency-off;
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 cpus {
22 #cpus = <1>;
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 cpu@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <32>; // 32 bytes
30 i-cache-line-size = <32>; // 32 bytes
31 d-cache-size = <32768>; // L1, 32K
32 i-cache-size = <32768>; // L1, 32K
33 timebase-frequency = <0>; // 33.3 MHz, from U-boot
34 clock-frequency = <0>; // From U-boot
35 bus-frequency = <0>; // From U-boot
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 reg = <0 0>; // From U-boot
42 };
43
44 pci@80000000 {
45 device_type = "pci";
46 compatible = "mai-logic,articia-s";
47 bus-frequency = <33333333>;
48 bus-range = <0 0xff>;
49 ranges = <0x01000000 0 0x00000000 0xfe000000 0 0x00c00000 // PCI I/O
50 0x02000000 0 0x80000000 0x80000000 0 0x7d000000 // PCI memory
51 0x02000000 0 0x00000000 0xfd000000 0 0x01000000>; // PCI alias memory (ISA)
52 // Configuration address and data register.
53 reg = <0xfec00cf8 4
54 0xfee00cfc 4>;
55 8259-interrupt-acknowledge = <0xfef00000>;
56 // Do not define a interrupt-parent here, if there is no
57 // interrupt-map property.
58 #address-cells = <3>;
59 #size-cells = <2>;
60
61 isa@7 {
62 device_type = "isa";
63 compatible = "pciclass,0601";
64 vendor-id = <0x00001106>;
65 device-id = <0x00000686>;
66 revision-id = <0x00000010>;
67 class-code = <0x00060100>;
68 subsystem-id = <0>;
69 subsystem-vendor-id = <0>;
70 devsel-speed = <0x00000001>;
71 min-grant = <0>;
72 max-latency = <0>;
73 /* First 64k for I/O at 0x0 on PCI mapped to 0x0 on ISA. */
74 ranges = <0x00000001 0 0x01000000 0 0x00000000 0x00010000>;
75 interrupt-parent = <&i8259>;
76 #interrupt-cells = <2>;
77 #address-cells = <2>;
78 #size-cells = <1>;
79
80 dma-controller@0 {
81 compatible = "pnpPNP,200";
82 reg = <1 0x00000000 0x00000020
83 1 0x00000080 0x00000010
84 1 0x000000c0 0x00000020>;
85 };
86
87 i8259: interrupt-controller@20 {
88 device_type = "interrupt-controller";
89 compatible = "pnpPNP,000";
90 interrupt-controller;
91 reg = <1 0x00000020 0x00000002
92 1 0x000000a0 0x00000002
93 1 0x000004d0 0x00000002>;
94 reserved-interrupts = <2>;
95 #interrupt-cells = <2>;
96 };
97
98 timer@40 {
99 // Also adds pcspkr to platform devices.
100 compatible = "pnpPNP,100";
101 reg = <1 0x00000040 0x00000020>;
102 };
103
104 8042@60 {
105 device_type = "8042";
106 reg = <1 0x00000060 0x00000001
107 1 0x00000064 0x00000001>;
108 interrupts = <1 3 12 3>;
109 #address-cells = <1>;
110 #size-cells = <0>;
111
112 keyboard@0 {
113 compatible = "pnpPNP,303";
114 reg = <0>;
115 };
116
117 mouse@1 {
118 compatible = "pnpPNP,f03";
119 reg = <1>;
120 };
121 };
122
123 rtc@70 {
124 compatible = "pnpPNP,b00";
125 reg = <1 0x00000070 0x00000002>;
126 interrupts = <8 3>;
127 };
128
129 serial@3f8 {
130 device_type = "serial";
131 compatible = "pnpPNP,501","pnpPNP,500";
132 reg = <1 0x000003f8 0x00000008>;
133 interrupts = <4 3>;
134 clock-frequency = <1843200>;
135 current-speed = <115200>;
136 };
137
138 serial@2f8 {
139 device_type = "serial";
140 compatible = "pnpPNP,501","pnpPNP,500";
141 reg = <1 0x000002f8 0x00000008>;
142 interrupts = <3 3>;
143 clock-frequency = <1843200>;
144 current-speed = <115200>;
145 };
146
147 parallel@378 {
148 device_type = "parallel";
149 // No ECP support for now, otherwise add "pnpPNP,401".
150 compatible = "pnpPNP,400";
151 reg = <1 0x00000378 0x00000003
152 1 0x00000778 0x00000003>;
153 };
154
155 fdc@3f0 {
156 device_type = "fdc";
157 compatible = "pnpPNP,700";
158 reg = <1 0x000003f0 0x00000008>;
159 interrupts = <6 3>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162
163 disk@0 {
164 reg = <0>;
165 };
166 };
167 };
168 };
169
170 chosen {
171 linux,stdout-path = "/pci@80000000/isa@7/serial@3f8";
172 };
173};
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
index 2f74cc4e093e..cee8080aa245 100644
--- a/arch/powerpc/boot/dts/cm5200.dts
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -17,6 +17,7 @@
17 compatible = "schindler,cm5200"; 17 compatible = "schindler,cm5200";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -66,7 +67,6 @@
66 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
67 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
68 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt; 70 fsl,has-wdt;
71 }; 71 };
72 72
@@ -74,84 +74,76 @@
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
77 interrupt-parent = <&mpc5200_pic>;
78 }; 77 };
79 78
80 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
83 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
84 interrupt-parent = <&mpc5200_pic>;
85 }; 83 };
86 84
87 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
89 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
90 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
91 interrupt-parent = <&mpc5200_pic>;
92 }; 89 };
93 90
94 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
95 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
96 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
97 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
98 interrupt-parent = <&mpc5200_pic>;
99 }; 95 };
100 96
101 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
104 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
105 interrupt-parent = <&mpc5200_pic>;
106 }; 101 };
107 102
108 timer@660 { // General Purpose Timer 103 timer@660 { // General Purpose Timer
109 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
110 reg = <0x660 0x10>; 105 reg = <0x660 0x10>;
111 interrupts = <1 15 0>; 106 interrupts = <1 15 0>;
112 interrupt-parent = <&mpc5200_pic>;
113 }; 107 };
114 108
115 timer@670 { // General Purpose Timer 109 timer@670 { // General Purpose Timer
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 reg = <0x670 0x10>; 111 reg = <0x670 0x10>;
118 interrupts = <1 16 0>; 112 interrupts = <1 16 0>;
119 interrupt-parent = <&mpc5200_pic>;
120 }; 113 };
121 114
122 rtc@800 { // Real time clock 115 rtc@800 { // Real time clock
123 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
124 reg = <0x800 0x100>; 117 reg = <0x800 0x100>;
125 interrupts = <1 5 0 1 6 0>; 118 interrupts = <1 5 0 1 6 0>;
126 interrupt-parent = <&mpc5200_pic>;
127 }; 119 };
128 120
129 gpio@b00 { 121 gpio_simple: gpio@b00 {
130 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 122 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
131 reg = <0xb00 0x40>; 123 reg = <0xb00 0x40>;
132 interrupts = <1 7 0>; 124 interrupts = <1 7 0>;
133 interrupt-parent = <&mpc5200_pic>; 125 gpio-controller;
126 #gpio-cells = <2>;
134 }; 127 };
135 128
136 gpio@c00 { 129 gpio_wkup: gpio@c00 {
137 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 130 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
138 reg = <0xc00 0x40>; 131 reg = <0xc00 0x40>;
139 interrupts = <1 8 0 0 3 0>; 132 interrupts = <1 8 0 0 3 0>;
140 interrupt-parent = <&mpc5200_pic>; 133 gpio-controller;
134 #gpio-cells = <2>;
141 }; 135 };
142 136
143 spi@f00 { 137 spi@f00 {
144 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 138 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
145 reg = <0xf00 0x20>; 139 reg = <0xf00 0x20>;
146 interrupts = <2 13 0 2 14 0>; 140 interrupts = <2 13 0 2 14 0>;
147 interrupt-parent = <&mpc5200_pic>;
148 }; 141 };
149 142
150 usb@1000 { 143 usb@1000 {
151 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 144 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
152 reg = <0x1000 0xff>; 145 reg = <0x1000 0xff>;
153 interrupts = <2 6 0>; 146 interrupts = <2 6 0>;
154 interrupt-parent = <&mpc5200_pic>;
155 }; 147 };
156 148
157 dma-controller@1200 { 149 dma-controller@1200 {
@@ -161,7 +153,6 @@
161 3 4 0 3 5 0 3 6 0 3 7 0 153 3 4 0 3 5 0 3 6 0 3 7 0
162 3 8 0 3 9 0 3 10 0 3 11 0 154 3 8 0 3 9 0 3 10 0 3 11 0
163 3 12 0 3 13 0 3 14 0 3 15 0>; 155 3 12 0 3 13 0 3 14 0 3 15 0>;
164 interrupt-parent = <&mpc5200_pic>;
165 }; 156 };
166 157
167 xlb@1f00 { 158 xlb@1f00 {
@@ -170,48 +161,34 @@
170 }; 161 };
171 162
172 serial@2000 { // PSC1 163 serial@2000 { // PSC1
173 device_type = "serial";
174 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 164 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
175 port-number = <0>; // Logical port assignment
176 reg = <0x2000 0x100>; 165 reg = <0x2000 0x100>;
177 interrupts = <2 1 0>; 166 interrupts = <2 1 0>;
178 interrupt-parent = <&mpc5200_pic>;
179 }; 167 };
180 168
181 serial@2200 { // PSC2 169 serial@2200 { // PSC2
182 device_type = "serial"; 170 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
183 compatible = "fsl,mpc5200-psc-uart";
184 port-number = <1>; // Logical port assignment
185 reg = <0x2200 0x100>; 171 reg = <0x2200 0x100>;
186 interrupts = <2 2 0>; 172 interrupts = <2 2 0>;
187 interrupt-parent = <&mpc5200_pic>;
188 }; 173 };
189 174
190 serial@2400 { // PSC3 175 serial@2400 { // PSC3
191 device_type = "serial"; 176 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
192 compatible = "fsl,mpc5200-psc-uart";
193 port-number = <2>; // Logical port assignment
194 reg = <0x2400 0x100>; 177 reg = <0x2400 0x100>;
195 interrupts = <2 3 0>; 178 interrupts = <2 3 0>;
196 interrupt-parent = <&mpc5200_pic>;
197 }; 179 };
198 180
199 serial@2c00 { // PSC6 181 serial@2c00 { // PSC6
200 device_type = "serial";
201 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 182 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
202 port-number = <5>; // Logical port assignment
203 reg = <0x2c00 0x100>; 183 reg = <0x2c00 0x100>;
204 interrupts = <2 4 0>; 184 interrupts = <2 4 0>;
205 interrupt-parent = <&mpc5200_pic>;
206 }; 185 };
207 186
208 ethernet@3000 { 187 ethernet@3000 {
209 device_type = "network";
210 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 188 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
211 reg = <0x3000 0x400>; 189 reg = <0x3000 0x400>;
212 local-mac-address = [ 00 00 00 00 00 00 ]; 190 local-mac-address = [ 00 00 00 00 00 00 ];
213 interrupts = <2 5 0>; 191 interrupts = <2 5 0>;
214 interrupt-parent = <&mpc5200_pic>;
215 phy-handle = <&phy0>; 192 phy-handle = <&phy0>;
216 }; 193 };
217 194
@@ -221,10 +198,8 @@
221 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 198 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
222 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 199 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
223 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 200 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
224 interrupt-parent = <&mpc5200_pic>;
225 201
226 phy0: ethernet-phy@0 { 202 phy0: ethernet-phy@0 {
227 device_type = "ethernet-phy";
228 reg = <0>; 203 reg = <0>;
229 }; 204 };
230 }; 205 };
@@ -235,7 +210,6 @@
235 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 210 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
236 reg = <0x3d40 0x40>; 211 reg = <0x3d40 0x40>;
237 interrupts = <2 16 0>; 212 interrupts = <2 16 0>;
238 interrupt-parent = <&mpc5200_pic>;
239 fsl5200-clocking; 213 fsl5200-clocking;
240 }; 214 };
241 215
@@ -245,9 +219,8 @@
245 }; 219 };
246 }; 220 };
247 221
248 lpb { 222 localbus {
249 model = "fsl,lpb"; 223 compatible = "fsl,mpc5200b-lpb","simple-bus";
250 compatible = "fsl,lpb";
251 #address-cells = <2>; 224 #address-cells = <2>;
252 #size-cells = <1>; 225 #size-cells = <1>;
253 ranges = <0 0 0xfc000000 0x2000000>; 226 ranges = <0 0 0xfc000000 0x2000000>;
diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
new file mode 100644
index 000000000000..0e85ebf7e4c8
--- /dev/null
+++ b/arch/powerpc/boot/dts/digsy_mtc.dts
@@ -0,0 +1,254 @@
1/*
2 * Digsy MTC board Device Tree Source
3 *
4 * Copyright (C) 2009 Semihalf
5 *
6 * Based on the CM5200 by M. Balakowicz
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "intercontrol,digsy-mtc";
18 compatible = "intercontrol,digsy-mtc";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 PowerPC,5200@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
37 };
38 };
39
40 memory {
41 device_type = "memory";
42 reg = <0x00000000 0x02000000>; // 32MB
43 };
44
45 soc5200@f0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr";
49 ranges = <0 0xf0000000 0x0000c000>;
50 reg = <0xf0000000 0x00000100>;
51 bus-frequency = <0>; // from bootloader
52 system-frequency = <0>; // from bootloader
53
54 cdm@200 {
55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
56 reg = <0x200 0x38>;
57 };
58
59 mpc5200_pic: interrupt-controller@500 {
60 // 5200 interrupts are encoded into two levels;
61 interrupt-controller;
62 #interrupt-cells = <3>;
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>;
65 };
66
67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 reg = <0x600 0x10>;
70 interrupts = <1 9 0>;
71 fsl,has-wdt;
72 };
73
74 timer@610 { // General Purpose Timer
75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
76 reg = <0x610 0x10>;
77 interrupts = <1 10 0>;
78 };
79
80 timer@620 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>;
83 interrupts = <1 11 0>;
84 };
85
86 timer@630 { // General Purpose Timer
87 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
88 reg = <0x630 0x10>;
89 interrupts = <1 12 0>;
90 };
91
92 timer@640 { // General Purpose Timer
93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
94 reg = <0x640 0x10>;
95 interrupts = <1 13 0>;
96 };
97
98 timer@650 { // General Purpose Timer
99 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
100 reg = <0x650 0x10>;
101 interrupts = <1 14 0>;
102 };
103
104 timer@660 { // General Purpose Timer
105 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
106 reg = <0x660 0x10>;
107 interrupts = <1 15 0>;
108 };
109
110 timer@670 { // General Purpose Timer
111 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
112 reg = <0x670 0x10>;
113 interrupts = <1 16 0>;
114 };
115
116 gpio_simple: gpio@b00 {
117 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
118 reg = <0xb00 0x40>;
119 interrupts = <1 7 0>;
120 gpio-controller;
121 #gpio-cells = <2>;
122 };
123
124 gpio_wkup: gpio@c00 {
125 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
126 reg = <0xc00 0x40>;
127 interrupts = <1 8 0 0 3 0>;
128 gpio-controller;
129 #gpio-cells = <2>;
130 };
131
132 spi@f00 {
133 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
134 reg = <0xf00 0x20>;
135 interrupts = <2 13 0 2 14 0>;
136 };
137
138 usb@1000 {
139 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
140 reg = <0x1000 0xff>;
141 interrupts = <2 6 0>;
142 };
143
144 dma-controller@1200 {
145 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
146 reg = <0x1200 0x80>;
147 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
148 3 4 0 3 5 0 3 6 0 3 7 0
149 3 8 0 3 9 0 3 10 0 3 11 0
150 3 12 0 3 13 0 3 14 0 3 15 0>;
151 };
152
153 xlb@1f00 {
154 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
155 reg = <0x1f00 0x100>;
156 };
157
158 serial@2400 { // PSC3
159 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
160 reg = <0x2400 0x100>;
161 interrupts = <2 3 0>;
162 };
163
164 serial@2600 { // PSC4
165 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
166 reg = <0x2600 0x100>;
167 interrupts = <2 11 0>;
168 };
169
170 ethernet@3000 {
171 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
172 reg = <0x3000 0x400>;
173 local-mac-address = [ 00 00 00 00 00 00 ];
174 interrupts = <2 5 0>;
175 phy-handle = <&phy0>;
176 };
177
178 mdio@3000 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
182 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
183 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
184
185 phy0: ethernet-phy@0 {
186 reg = <0>;
187 };
188 };
189
190 ata@3a00 {
191 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
192 reg = <0x3a00 0x100>;
193 interrupts = <2 7 0>;
194 };
195
196 i2c@3d00 {
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
200 reg = <0x3d00 0x40>;
201 interrupts = <2 15 0>;
202 fsl5200-clocking;
203
204 rtc@50 {
205 compatible = "at,24c08";
206 reg = <0x50>;
207 };
208
209 rtc@68 {
210 compatible = "dallas,ds1339";
211 reg = <0x68>;
212 };
213 };
214
215 sram@8000 {
216 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
217 reg = <0x8000 0x4000>;
218 };
219 };
220
221 lpb {
222 compatible = "fsl,mpc5200b-lpb","simple-bus";
223 #address-cells = <2>;
224 #size-cells = <1>;
225 ranges = <0 0 0xff000000 0x1000000>;
226
227 // 16-bit flash device at LocalPlus Bus CS0
228 flash@0,0 {
229 compatible = "cfi-flash";
230 reg = <0 0 0x1000000>;
231 bank-width = <2>;
232 device-width = <2>;
233 #size-cells = <1>;
234 #address-cells = <1>;
235
236 partition@0 {
237 label = "kernel";
238 reg = <0x0 0x00200000>;
239 };
240 partition@200000 {
241 label = "root";
242 reg = <0x00200000 0x00300000>;
243 };
244 partition@500000 {
245 label = "user";
246 reg = <0x00500000 0x00a00000>;
247 };
248 partition@f00000 {
249 label = "u-boot";
250 reg = <0x00f00000 0x100000>;
251 };
252 };
253 };
254};
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
new file mode 100644
index 000000000000..09eeb438216b
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -0,0 +1,364 @@
1/*
2 * GE Fanuc SBC310 Device Tree Source
3 *
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 */
16
17/*
18 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
19 */
20
21/dts-v1/;
22
23/ {
24 model = "GEF_SBC310";
25 compatible = "gef,sbc310";
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 aliases {
30 ethernet0 = &enet0;
31 ethernet1 = &enet1;
32 serial0 = &serial0;
33 serial1 = &serial1;
34 pci0 = &pci0;
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 PowerPC,8641@0 {
42 device_type = "cpu";
43 reg = <0>;
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
51 };
52 PowerPC,8641@1 {
53 device_type = "cpu";
54 reg = <1>;
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
62 };
63 };
64
65 memory {
66 device_type = "memory";
67 reg = <0x0 0x40000000>; // set by uboot
68 };
69
70 localbus@fef05000 {
71 #address-cells = <2>;
72 #size-cells = <1>;
73 compatible = "fsl,mpc8641-localbus", "simple-bus";
74 reg = <0xfef05000 0x1000>;
75 interrupts = <19 2>;
76 interrupt-parent = <&mpic>;
77
78 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
79 1 0 0xe0000000 0x08000000 // Paged Flash 0
80 2 0 0xe8000000 0x08000000 // Paged Flash 1
81 3 0 0xfc100000 0x00020000 // NVRAM
82 4 0 0xfc000000 0x00010000>; // FPGA
83
84 /* flash@0,0 is a mirror of part of the memory in flash@1,0
85 flash@0,0 {
86 compatible = "cfi-flash";
87 reg = <0 0 0x01000000>;
88 bank-width = <2>;
89 device-width = <2>;
90 #address-cells = <1>;
91 #size-cells = <1>;
92 partition@0 {
93 label = "firmware";
94 reg = <0x00000000 0x01000000>;
95 read-only;
96 };
97 };
98 */
99
100 flash@1,0 {
101 compatible = "cfi-flash";
102 reg = <1 0 0x8000000>;
103 bank-width = <2>;
104 device-width = <2>;
105 #address-cells = <1>;
106 #size-cells = <1>;
107 partition@0 {
108 label = "user";
109 reg = <0x00000000 0x07800000>;
110 };
111 partition@7800000 {
112 label = "firmware";
113 reg = <0x07800000 0x00800000>;
114 read-only;
115 };
116 };
117
118 fpga@4,0 {
119 compatible = "gef,fpga-regs";
120 reg = <0x4 0x0 0x40>;
121 };
122
123 wdt@4,2000 {
124 #interrupt-cells = <2>;
125 device_type = "watchdog";
126 compatible = "gef,fpga-wdt";
127 reg = <0x4 0x2000 0x8>;
128 interrupts = <0x1a 0x4>;
129 interrupt-parent = <&gef_pic>;
130 };
131/*
132 wdt@4,2010 {
133 #interrupt-cells = <2>;
134 device_type = "watchdog";
135 compatible = "gef,fpga-wdt";
136 reg = <0x4 0x2010 0x8>;
137 interrupts = <0x1b 0x4>;
138 interrupt-parent = <&gef_pic>;
139 };
140*/
141 gef_pic: pic@4,4000 {
142 #interrupt-cells = <1>;
143 interrupt-controller;
144 compatible = "gef,fpga-pic";
145 reg = <0x4 0x4000 0x20>;
146 interrupts = <0x8
147 0x9>;
148 interrupt-parent = <&mpic>;
149
150 };
151 gef_gpio: gpio@4,8000 {
152 #gpio-cells = <2>;
153 compatible = "gef,sbc310-gpio";
154 reg = <0x4 0x8000 0x24>;
155 gpio-controller;
156 };
157 };
158
159 soc@fef00000 {
160 #address-cells = <1>;
161 #size-cells = <1>;
162 #interrupt-cells = <2>;
163 device_type = "soc";
164 compatible = "simple-bus";
165 ranges = <0x0 0xfef00000 0x00100000>;
166 reg = <0xfef00000 0x100000>; // CCSRBAR 1M
167 bus-frequency = <33333333>;
168
169 i2c1: i2c@3000 {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 compatible = "fsl-i2c";
173 reg = <0x3000 0x100>;
174 interrupts = <0x2b 0x2>;
175 interrupt-parent = <&mpic>;
176 dfsrr;
177
178 rtc@51 {
179 compatible = "epson,rx8581";
180 reg = <0x00000051>;
181 };
182 };
183
184 i2c2: i2c@3100 {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 compatible = "fsl-i2c";
188 reg = <0x3100 0x100>;
189 interrupts = <0x2b 0x2>;
190 interrupt-parent = <&mpic>;
191 dfsrr;
192
193 hwmon@48 {
194 compatible = "national,lm92";
195 reg = <0x48>;
196 };
197
198 hwmon@4c {
199 compatible = "adi,adt7461";
200 reg = <0x4c>;
201 };
202
203 eti@6b {
204 compatible = "dallas,ds1682";
205 reg = <0x6b>;
206 };
207 };
208
209 dma@21300 {
210 #address-cells = <1>;
211 #size-cells = <1>;
212 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
213 reg = <0x21300 0x4>;
214 ranges = <0x0 0x21100 0x200>;
215 cell-index = <0>;
216 dma-channel@0 {
217 compatible = "fsl,mpc8641-dma-channel",
218 "fsl,eloplus-dma-channel";
219 reg = <0x0 0x80>;
220 cell-index = <0>;
221 interrupt-parent = <&mpic>;
222 interrupts = <20 2>;
223 };
224 dma-channel@80 {
225 compatible = "fsl,mpc8641-dma-channel",
226 "fsl,eloplus-dma-channel";
227 reg = <0x80 0x80>;
228 cell-index = <1>;
229 interrupt-parent = <&mpic>;
230 interrupts = <21 2>;
231 };
232 dma-channel@100 {
233 compatible = "fsl,mpc8641-dma-channel",
234 "fsl,eloplus-dma-channel";
235 reg = <0x100 0x80>;
236 cell-index = <2>;
237 interrupt-parent = <&mpic>;
238 interrupts = <22 2>;
239 };
240 dma-channel@180 {
241 compatible = "fsl,mpc8641-dma-channel",
242 "fsl,eloplus-dma-channel";
243 reg = <0x180 0x80>;
244 cell-index = <3>;
245 interrupt-parent = <&mpic>;
246 interrupts = <23 2>;
247 };
248 };
249
250 mdio@24520 {
251 #address-cells = <1>;
252 #size-cells = <0>;
253 compatible = "fsl,gianfar-mdio";
254 reg = <0x24520 0x20>;
255
256 phy0: ethernet-phy@0 {
257 interrupt-parent = <&gef_pic>;
258 interrupts = <0x9 0x4>;
259 reg = <1>;
260 };
261 phy2: ethernet-phy@2 {
262 interrupt-parent = <&gef_pic>;
263 interrupts = <0x8 0x4>;
264 reg = <3>;
265 };
266 };
267
268 enet0: ethernet@24000 {
269 device_type = "network";
270 model = "eTSEC";
271 compatible = "gianfar";
272 reg = <0x24000 0x1000>;
273 local-mac-address = [ 00 00 00 00 00 00 ];
274 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
275 interrupt-parent = <&mpic>;
276 phy-handle = <&phy0>;
277 phy-connection-type = "gmii";
278 };
279
280 enet1: ethernet@26000 {
281 device_type = "network";
282 model = "eTSEC";
283 compatible = "gianfar";
284 reg = <0x26000 0x1000>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
287 interrupt-parent = <&mpic>;
288 phy-handle = <&phy2>;
289 phy-connection-type = "gmii";
290 };
291
292 serial0: serial@4500 {
293 cell-index = <0>;
294 device_type = "serial";
295 compatible = "ns16550";
296 reg = <0x4500 0x100>;
297 clock-frequency = <0>;
298 interrupts = <0x2a 0x2>;
299 interrupt-parent = <&mpic>;
300 };
301
302 serial1: serial@4600 {
303 cell-index = <1>;
304 device_type = "serial";
305 compatible = "ns16550";
306 reg = <0x4600 0x100>;
307 clock-frequency = <0>;
308 interrupts = <0x1c 0x2>;
309 interrupt-parent = <&mpic>;
310 };
311
312 mpic: pic@40000 {
313 clock-frequency = <0>;
314 interrupt-controller;
315 #address-cells = <0>;
316 #interrupt-cells = <2>;
317 reg = <0x40000 0x40000>;
318 compatible = "chrp,open-pic";
319 device_type = "open-pic";
320 };
321
322 global-utilities@e0000 {
323 compatible = "fsl,mpc8641-guts";
324 reg = <0xe0000 0x1000>;
325 fsl,has-rstcr;
326 };
327 };
328
329 pci0: pcie@fef08000 {
330 compatible = "fsl,mpc8641-pcie";
331 device_type = "pci";
332 #interrupt-cells = <1>;
333 #size-cells = <2>;
334 #address-cells = <3>;
335 reg = <0xfef08000 0x1000>;
336 bus-range = <0x0 0xff>;
337 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
338 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
339 clock-frequency = <33333333>;
340 interrupt-parent = <&mpic>;
341 interrupts = <0x18 0x2>;
342 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
343 interrupt-map = <
344 0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
345 0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
346 0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
347 0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
348 >;
349
350 pcie@0 {
351 reg = <0 0 0 0 0>;
352 #size-cells = <2>;
353 #address-cells = <3>;
354 device_type = "pci";
355 ranges = <0x02000000 0x0 0x80000000
356 0x02000000 0x0 0x80000000
357 0x0 0x40000000
358
359 0x01000000 0x0 0x00000000
360 0x01000000 0x0 0x00000000
361 0x0 0x00400000>;
362 };
363 };
364};
diff --git a/arch/powerpc/boot/dts/lite5200.dts b/arch/powerpc/boot/dts/lite5200.dts
index 3f7a5dce8de0..de30b3f9eb26 100644
--- a/arch/powerpc/boot/dts/lite5200.dts
+++ b/arch/powerpc/boot/dts/lite5200.dts
@@ -17,6 +17,7 @@
17 compatible = "fsl,lite5200"; 17 compatible = "fsl,lite5200";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -58,96 +59,74 @@
58 // 5200 interrupts are encoded into two levels; 59 // 5200 interrupts are encoded into two levels;
59 interrupt-controller; 60 interrupt-controller;
60 #interrupt-cells = <3>; 61 #interrupt-cells = <3>;
61 device_type = "interrupt-controller";
62 compatible = "fsl,mpc5200-pic"; 62 compatible = "fsl,mpc5200-pic";
63 reg = <0x500 0x80>; 63 reg = <0x500 0x80>;
64 }; 64 };
65 65
66 timer@600 { // General Purpose Timer 66 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200-gpt";
68 cell-index = <0>;
69 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
70 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
71 interrupt-parent = <&mpc5200_pic>;
72 fsl,has-wdt; 70 fsl,has-wdt;
73 }; 71 };
74 72
75 timer@610 { // General Purpose Timer 73 timer@610 { // General Purpose Timer
76 compatible = "fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200-gpt";
77 cell-index = <1>;
78 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
79 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
80 interrupt-parent = <&mpc5200_pic>;
81 }; 77 };
82 78
83 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
84 compatible = "fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200-gpt";
85 cell-index = <2>;
86 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
87 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
88 interrupt-parent = <&mpc5200_pic>;
89 }; 83 };
90 84
91 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
92 compatible = "fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200-gpt";
93 cell-index = <3>;
94 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
95 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
96 interrupt-parent = <&mpc5200_pic>;
97 }; 89 };
98 90
99 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
100 compatible = "fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200-gpt";
101 cell-index = <4>;
102 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
103 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
104 interrupt-parent = <&mpc5200_pic>;
105 }; 95 };
106 96
107 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200-gpt";
109 cell-index = <5>;
110 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
111 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
112 interrupt-parent = <&mpc5200_pic>;
113 }; 101 };
114 102
115 timer@660 { // General Purpose Timer 103 timer@660 { // General Purpose Timer
116 compatible = "fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200-gpt";
117 cell-index = <6>;
118 reg = <0x660 0x10>; 105 reg = <0x660 0x10>;
119 interrupts = <1 15 0>; 106 interrupts = <1 15 0>;
120 interrupt-parent = <&mpc5200_pic>;
121 }; 107 };
122 108
123 timer@670 { // General Purpose Timer 109 timer@670 { // General Purpose Timer
124 compatible = "fsl,mpc5200-gpt"; 110 compatible = "fsl,mpc5200-gpt";
125 cell-index = <7>;
126 reg = <0x670 0x10>; 111 reg = <0x670 0x10>;
127 interrupts = <1 16 0>; 112 interrupts = <1 16 0>;
128 interrupt-parent = <&mpc5200_pic>;
129 }; 113 };
130 114
131 rtc@800 { // Real time clock 115 rtc@800 { // Real time clock
132 compatible = "fsl,mpc5200-rtc"; 116 compatible = "fsl,mpc5200-rtc";
133 reg = <0x800 0x100>; 117 reg = <0x800 0x100>;
134 interrupts = <1 5 0 1 6 0>; 118 interrupts = <1 5 0 1 6 0>;
135 interrupt-parent = <&mpc5200_pic>;
136 }; 119 };
137 120
138 can@900 { 121 can@900 {
139 compatible = "fsl,mpc5200-mscan"; 122 compatible = "fsl,mpc5200-mscan";
140 cell-index = <0>;
141 interrupts = <2 17 0>; 123 interrupts = <2 17 0>;
142 interrupt-parent = <&mpc5200_pic>;
143 reg = <0x900 0x80>; 124 reg = <0x900 0x80>;
144 }; 125 };
145 126
146 can@980 { 127 can@980 {
147 compatible = "fsl,mpc5200-mscan"; 128 compatible = "fsl,mpc5200-mscan";
148 cell-index = <1>;
149 interrupts = <2 18 0>; 129 interrupts = <2 18 0>;
150 interrupt-parent = <&mpc5200_pic>;
151 reg = <0x980 0x80>; 130 reg = <0x980 0x80>;
152 }; 131 };
153 132
@@ -155,39 +134,33 @@
155 compatible = "fsl,mpc5200-gpio"; 134 compatible = "fsl,mpc5200-gpio";
156 reg = <0xb00 0x40>; 135 reg = <0xb00 0x40>;
157 interrupts = <1 7 0>; 136 interrupts = <1 7 0>;
158 interrupt-parent = <&mpc5200_pic>;
159 }; 137 };
160 138
161 gpio@c00 { 139 gpio@c00 {
162 compatible = "fsl,mpc5200-gpio-wkup"; 140 compatible = "fsl,mpc5200-gpio-wkup";
163 reg = <0xc00 0x40>; 141 reg = <0xc00 0x40>;
164 interrupts = <1 8 0 0 3 0>; 142 interrupts = <1 8 0 0 3 0>;
165 interrupt-parent = <&mpc5200_pic>;
166 }; 143 };
167 144
168 spi@f00 { 145 spi@f00 {
169 compatible = "fsl,mpc5200-spi"; 146 compatible = "fsl,mpc5200-spi";
170 reg = <0xf00 0x20>; 147 reg = <0xf00 0x20>;
171 interrupts = <2 13 0 2 14 0>; 148 interrupts = <2 13 0 2 14 0>;
172 interrupt-parent = <&mpc5200_pic>;
173 }; 149 };
174 150
175 usb@1000 { 151 usb@1000 {
176 compatible = "fsl,mpc5200-ohci","ohci-be"; 152 compatible = "fsl,mpc5200-ohci","ohci-be";
177 reg = <0x1000 0xff>; 153 reg = <0x1000 0xff>;
178 interrupts = <2 6 0>; 154 interrupts = <2 6 0>;
179 interrupt-parent = <&mpc5200_pic>;
180 }; 155 };
181 156
182 dma-controller@1200 { 157 dma-controller@1200 {
183 device_type = "dma-controller";
184 compatible = "fsl,mpc5200-bestcomm"; 158 compatible = "fsl,mpc5200-bestcomm";
185 reg = <0x1200 0x80>; 159 reg = <0x1200 0x80>;
186 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 160 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
187 3 4 0 3 5 0 3 6 0 3 7 0 161 3 4 0 3 5 0 3 6 0 3 7 0
188 3 8 0 3 9 0 3 10 0 3 11 0 162 3 8 0 3 9 0 3 10 0 3 11 0
189 3 12 0 3 13 0 3 14 0 3 15 0>; 163 3 12 0 3 13 0 3 14 0 3 15 0>;
190 interrupt-parent = <&mpc5200_pic>;
191 }; 164 };
192 165
193 xlb@1f00 { 166 xlb@1f00 {
@@ -196,13 +169,10 @@
196 }; 169 };
197 170
198 serial@2000 { // PSC1 171 serial@2000 { // PSC1
199 device_type = "serial";
200 compatible = "fsl,mpc5200-psc-uart"; 172 compatible = "fsl,mpc5200-psc-uart";
201 port-number = <0>; // Logical port assignment
202 cell-index = <0>; 173 cell-index = <0>;
203 reg = <0x2000 0x100>; 174 reg = <0x2000 0x100>;
204 interrupts = <2 1 0>; 175 interrupts = <2 1 0>;
205 interrupt-parent = <&mpc5200_pic>;
206 }; 176 };
207 177
208 // PSC2 in ac97 mode example 178 // PSC2 in ac97 mode example
@@ -211,7 +181,6 @@
211 // cell-index = <1>; 181 // cell-index = <1>;
212 // reg = <0x2200 0x100>; 182 // reg = <0x2200 0x100>;
213 // interrupts = <2 2 0>; 183 // interrupts = <2 2 0>;
214 // interrupt-parent = <&mpc5200_pic>;
215 //}; 184 //};
216 185
217 // PSC3 in CODEC mode example 186 // PSC3 in CODEC mode example
@@ -220,27 +189,22 @@
220 // cell-index = <2>; 189 // cell-index = <2>;
221 // reg = <0x2400 0x100>; 190 // reg = <0x2400 0x100>;
222 // interrupts = <2 3 0>; 191 // interrupts = <2 3 0>;
223 // interrupt-parent = <&mpc5200_pic>;
224 //}; 192 //};
225 193
226 // PSC4 in uart mode example 194 // PSC4 in uart mode example
227 //serial@2600 { // PSC4 195 //serial@2600 { // PSC4
228 // device_type = "serial";
229 // compatible = "fsl,mpc5200-psc-uart"; 196 // compatible = "fsl,mpc5200-psc-uart";
230 // cell-index = <3>; 197 // cell-index = <3>;
231 // reg = <0x2600 0x100>; 198 // reg = <0x2600 0x100>;
232 // interrupts = <2 11 0>; 199 // interrupts = <2 11 0>;
233 // interrupt-parent = <&mpc5200_pic>;
234 //}; 200 //};
235 201
236 // PSC5 in uart mode example 202 // PSC5 in uart mode example
237 //serial@2800 { // PSC5 203 //serial@2800 { // PSC5
238 // device_type = "serial";
239 // compatible = "fsl,mpc5200-psc-uart"; 204 // compatible = "fsl,mpc5200-psc-uart";
240 // cell-index = <4>; 205 // cell-index = <4>;
241 // reg = <0x2800 0x100>; 206 // reg = <0x2800 0x100>;
242 // interrupts = <2 12 0>; 207 // interrupts = <2 12 0>;
243 // interrupt-parent = <&mpc5200_pic>;
244 //}; 208 //};
245 209
246 // PSC6 in spi mode example 210 // PSC6 in spi mode example
@@ -249,16 +213,13 @@
249 // cell-index = <5>; 213 // cell-index = <5>;
250 // reg = <0x2c00 0x100>; 214 // reg = <0x2c00 0x100>;
251 // interrupts = <2 4 0>; 215 // interrupts = <2 4 0>;
252 // interrupt-parent = <&mpc5200_pic>;
253 //}; 216 //};
254 217
255 ethernet@3000 { 218 ethernet@3000 {
256 device_type = "network";
257 compatible = "fsl,mpc5200-fec"; 219 compatible = "fsl,mpc5200-fec";
258 reg = <0x3000 0x400>; 220 reg = <0x3000 0x400>;
259 local-mac-address = [ 00 00 00 00 00 00 ]; 221 local-mac-address = [ 00 00 00 00 00 00 ];
260 interrupts = <2 5 0>; 222 interrupts = <2 5 0>;
261 interrupt-parent = <&mpc5200_pic>;
262 phy-handle = <&phy0>; 223 phy-handle = <&phy0>;
263 }; 224 };
264 225
@@ -268,30 +229,24 @@
268 compatible = "fsl,mpc5200-mdio"; 229 compatible = "fsl,mpc5200-mdio";
269 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 230 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
270 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 231 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
271 interrupt-parent = <&mpc5200_pic>;
272 232
273 phy0: ethernet-phy@1 { 233 phy0: ethernet-phy@1 {
274 device_type = "ethernet-phy";
275 reg = <1>; 234 reg = <1>;
276 }; 235 };
277 }; 236 };
278 237
279 ata@3a00 { 238 ata@3a00 {
280 device_type = "ata";
281 compatible = "fsl,mpc5200-ata"; 239 compatible = "fsl,mpc5200-ata";
282 reg = <0x3a00 0x100>; 240 reg = <0x3a00 0x100>;
283 interrupts = <2 7 0>; 241 interrupts = <2 7 0>;
284 interrupt-parent = <&mpc5200_pic>;
285 }; 242 };
286 243
287 i2c@3d00 { 244 i2c@3d00 {
288 #address-cells = <1>; 245 #address-cells = <1>;
289 #size-cells = <0>; 246 #size-cells = <0>;
290 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 247 compatible = "fsl,mpc5200-i2c","fsl-i2c";
291 cell-index = <0>;
292 reg = <0x3d00 0x40>; 248 reg = <0x3d00 0x40>;
293 interrupts = <2 15 0>; 249 interrupts = <2 15 0>;
294 interrupt-parent = <&mpc5200_pic>;
295 fsl5200-clocking; 250 fsl5200-clocking;
296 }; 251 };
297 252
@@ -299,14 +254,12 @@
299 #address-cells = <1>; 254 #address-cells = <1>;
300 #size-cells = <0>; 255 #size-cells = <0>;
301 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 256 compatible = "fsl,mpc5200-i2c","fsl-i2c";
302 cell-index = <1>;
303 reg = <0x3d40 0x40>; 257 reg = <0x3d40 0x40>;
304 interrupts = <2 16 0>; 258 interrupts = <2 16 0>;
305 interrupt-parent = <&mpc5200_pic>;
306 fsl5200-clocking; 259 fsl5200-clocking;
307 }; 260 };
308 sram@8000 { 261 sram@8000 {
309 compatible = "fsl,mpc5200-sram","sram"; 262 compatible = "fsl,mpc5200-sram";
310 reg = <0x8000 0x4000>; 263 reg = <0x8000 0x4000>;
311 }; 264 };
312 }; 265 };
@@ -325,7 +278,6 @@
325 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 278 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
326 clock-frequency = <0>; // From boot loader 279 clock-frequency = <0>; // From boot loader
327 interrupts = <2 8 0 2 9 0 2 10 0>; 280 interrupts = <2 8 0 2 9 0 2 10 0>;
328 interrupt-parent = <&mpc5200_pic>;
329 bus-range = <0 0>; 281 bus-range = <0 0>;
330 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 282 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
331 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 283 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
index 63e3bb48e843..c63e3566479e 100644
--- a/arch/powerpc/boot/dts/lite5200b.dts
+++ b/arch/powerpc/boot/dts/lite5200b.dts
@@ -17,6 +17,7 @@
17 compatible = "fsl,lite5200b"; 17 compatible = "fsl,lite5200b";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -58,136 +59,112 @@
58 // 5200 interrupts are encoded into two levels; 59 // 5200 interrupts are encoded into two levels;
59 interrupt-controller; 60 interrupt-controller;
60 #interrupt-cells = <3>; 61 #interrupt-cells = <3>;
61 device_type = "interrupt-controller";
62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 62 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
63 reg = <0x500 0x80>; 63 reg = <0x500 0x80>;
64 }; 64 };
65 65
66 timer@600 { // General Purpose Timer 66 timer@600 { // General Purpose Timer
67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
68 cell-index = <0>;
69 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
70 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
71 interrupt-parent = <&mpc5200_pic>;
72 fsl,has-wdt; 70 fsl,has-wdt;
73 }; 71 };
74 72
75 timer@610 { // General Purpose Timer 73 timer@610 { // General Purpose Timer
76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
77 cell-index = <1>;
78 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
79 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
80 interrupt-parent = <&mpc5200_pic>;
81 }; 77 };
82 78
83 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 cell-index = <2>;
86 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
87 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
88 interrupt-parent = <&mpc5200_pic>;
89 }; 83 };
90 84
91 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 cell-index = <3>;
94 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
95 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
96 interrupt-parent = <&mpc5200_pic>;
97 }; 89 };
98 90
99 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
101 cell-index = <4>;
102 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
103 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
104 interrupt-parent = <&mpc5200_pic>;
105 }; 95 };
106 96
107 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 cell-index = <5>;
110 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
111 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
112 interrupt-parent = <&mpc5200_pic>;
113 }; 101 };
114 102
115 timer@660 { // General Purpose Timer 103 timer@660 { // General Purpose Timer
116 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
117 cell-index = <6>;
118 reg = <0x660 0x10>; 105 reg = <0x660 0x10>;
119 interrupts = <1 15 0>; 106 interrupts = <1 15 0>;
120 interrupt-parent = <&mpc5200_pic>;
121 }; 107 };
122 108
123 timer@670 { // General Purpose Timer 109 timer@670 { // General Purpose Timer
124 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 110 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
125 cell-index = <7>;
126 reg = <0x670 0x10>; 111 reg = <0x670 0x10>;
127 interrupts = <1 16 0>; 112 interrupts = <1 16 0>;
128 interrupt-parent = <&mpc5200_pic>;
129 }; 113 };
130 114
131 rtc@800 { // Real time clock 115 rtc@800 { // Real time clock
132 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 116 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
133 reg = <0x800 0x100>; 117 reg = <0x800 0x100>;
134 interrupts = <1 5 0 1 6 0>; 118 interrupts = <1 5 0 1 6 0>;
135 interrupt-parent = <&mpc5200_pic>;
136 }; 119 };
137 120
138 can@900 { 121 can@900 {
139 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 122 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
140 cell-index = <0>;
141 interrupts = <2 17 0>; 123 interrupts = <2 17 0>;
142 interrupt-parent = <&mpc5200_pic>;
143 reg = <0x900 0x80>; 124 reg = <0x900 0x80>;
144 }; 125 };
145 126
146 can@980 { 127 can@980 {
147 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 128 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
148 cell-index = <1>;
149 interrupts = <2 18 0>; 129 interrupts = <2 18 0>;
150 interrupt-parent = <&mpc5200_pic>;
151 reg = <0x980 0x80>; 130 reg = <0x980 0x80>;
152 }; 131 };
153 132
154 gpio@b00 { 133 gpio_simple: gpio@b00 {
155 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 134 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
156 reg = <0xb00 0x40>; 135 reg = <0xb00 0x40>;
157 interrupts = <1 7 0>; 136 interrupts = <1 7 0>;
158 interrupt-parent = <&mpc5200_pic>; 137 gpio-controller;
138 #gpio-cells = <2>;
159 }; 139 };
160 140
161 gpio@c00 { 141 gpio_wkup: gpio@c00 {
162 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 142 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
163 reg = <0xc00 0x40>; 143 reg = <0xc00 0x40>;
164 interrupts = <1 8 0 0 3 0>; 144 interrupts = <1 8 0 0 3 0>;
165 interrupt-parent = <&mpc5200_pic>; 145 gpio-controller;
146 #gpio-cells = <2>;
166 }; 147 };
167 148
168 spi@f00 { 149 spi@f00 {
169 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 150 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
170 reg = <0xf00 0x20>; 151 reg = <0xf00 0x20>;
171 interrupts = <2 13 0 2 14 0>; 152 interrupts = <2 13 0 2 14 0>;
172 interrupt-parent = <&mpc5200_pic>;
173 }; 153 };
174 154
175 usb@1000 { 155 usb@1000 {
176 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 156 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
177 reg = <0x1000 0xff>; 157 reg = <0x1000 0xff>;
178 interrupts = <2 6 0>; 158 interrupts = <2 6 0>;
179 interrupt-parent = <&mpc5200_pic>;
180 }; 159 };
181 160
182 dma-controller@1200 { 161 dma-controller@1200 {
183 device_type = "dma-controller";
184 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 162 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
185 reg = <0x1200 0x80>; 163 reg = <0x1200 0x80>;
186 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 164 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
187 3 4 0 3 5 0 3 6 0 3 7 0 165 3 4 0 3 5 0 3 6 0 3 7 0
188 3 8 0 3 9 0 3 10 0 3 11 0 166 3 8 0 3 9 0 3 10 0 3 11 0
189 3 12 0 3 13 0 3 14 0 3 15 0>; 167 3 12 0 3 13 0 3 14 0 3 15 0>;
190 interrupt-parent = <&mpc5200_pic>;
191 }; 168 };
192 169
193 xlb@1f00 { 170 xlb@1f00 {
@@ -196,13 +173,10 @@
196 }; 173 };
197 174
198 serial@2000 { // PSC1 175 serial@2000 { // PSC1
199 device_type = "serial";
200 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 176 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
201 port-number = <0>; // Logical port assignment
202 cell-index = <0>; 177 cell-index = <0>;
203 reg = <0x2000 0x100>; 178 reg = <0x2000 0x100>;
204 interrupts = <2 1 0>; 179 interrupts = <2 1 0>;
205 interrupt-parent = <&mpc5200_pic>;
206 }; 180 };
207 181
208 // PSC2 in ac97 mode example 182 // PSC2 in ac97 mode example
@@ -211,7 +185,6 @@
211 // cell-index = <1>; 185 // cell-index = <1>;
212 // reg = <0x2200 0x100>; 186 // reg = <0x2200 0x100>;
213 // interrupts = <2 2 0>; 187 // interrupts = <2 2 0>;
214 // interrupt-parent = <&mpc5200_pic>;
215 //}; 188 //};
216 189
217 // PSC3 in CODEC mode example 190 // PSC3 in CODEC mode example
@@ -220,27 +193,22 @@
220 // cell-index = <2>; 193 // cell-index = <2>;
221 // reg = <0x2400 0x100>; 194 // reg = <0x2400 0x100>;
222 // interrupts = <2 3 0>; 195 // interrupts = <2 3 0>;
223 // interrupt-parent = <&mpc5200_pic>;
224 //}; 196 //};
225 197
226 // PSC4 in uart mode example 198 // PSC4 in uart mode example
227 //serial@2600 { // PSC4 199 //serial@2600 { // PSC4
228 // device_type = "serial";
229 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 200 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
230 // cell-index = <3>; 201 // cell-index = <3>;
231 // reg = <0x2600 0x100>; 202 // reg = <0x2600 0x100>;
232 // interrupts = <2 11 0>; 203 // interrupts = <2 11 0>;
233 // interrupt-parent = <&mpc5200_pic>;
234 //}; 204 //};
235 205
236 // PSC5 in uart mode example 206 // PSC5 in uart mode example
237 //serial@2800 { // PSC5 207 //serial@2800 { // PSC5
238 // device_type = "serial";
239 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 208 // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
240 // cell-index = <4>; 209 // cell-index = <4>;
241 // reg = <0x2800 0x100>; 210 // reg = <0x2800 0x100>;
242 // interrupts = <2 12 0>; 211 // interrupts = <2 12 0>;
243 // interrupt-parent = <&mpc5200_pic>;
244 //}; 212 //};
245 213
246 // PSC6 in spi mode example 214 // PSC6 in spi mode example
@@ -249,49 +217,40 @@
249 // cell-index = <5>; 217 // cell-index = <5>;
250 // reg = <0x2c00 0x100>; 218 // reg = <0x2c00 0x100>;
251 // interrupts = <2 4 0>; 219 // interrupts = <2 4 0>;
252 // interrupt-parent = <&mpc5200_pic>;
253 //}; 220 //};
254 221
255 ethernet@3000 { 222 ethernet@3000 {
256 device_type = "network";
257 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 223 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
258 reg = <0x3000 0x400>; 224 reg = <0x3000 0x400>;
259 local-mac-address = [ 00 00 00 00 00 00 ]; 225 local-mac-address = [ 00 00 00 00 00 00 ];
260 interrupts = <2 5 0>; 226 interrupts = <2 5 0>;
261 interrupt-parent = <&mpc5200_pic>;
262 phy-handle = <&phy0>; 227 phy-handle = <&phy0>;
263 }; 228 };
264 229
265 mdio@3000 { 230 mdio@3000 {
266 #address-cells = <1>; 231 #address-cells = <1>;
267 #size-cells = <0>; 232 #size-cells = <0>;
268 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; 233 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
269 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 234 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
270 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 235 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
271 interrupt-parent = <&mpc5200_pic>;
272 236
273 phy0: ethernet-phy@0 { 237 phy0: ethernet-phy@0 {
274 device_type = "ethernet-phy";
275 reg = <0>; 238 reg = <0>;
276 }; 239 };
277 }; 240 };
278 241
279 ata@3a00 { 242 ata@3a00 {
280 device_type = "ata";
281 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 243 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
282 reg = <0x3a00 0x100>; 244 reg = <0x3a00 0x100>;
283 interrupts = <2 7 0>; 245 interrupts = <2 7 0>;
284 interrupt-parent = <&mpc5200_pic>;
285 }; 246 };
286 247
287 i2c@3d00 { 248 i2c@3d00 {
288 #address-cells = <1>; 249 #address-cells = <1>;
289 #size-cells = <0>; 250 #size-cells = <0>;
290 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 251 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
291 cell-index = <0>;
292 reg = <0x3d00 0x40>; 252 reg = <0x3d00 0x40>;
293 interrupts = <2 15 0>; 253 interrupts = <2 15 0>;
294 interrupt-parent = <&mpc5200_pic>;
295 fsl5200-clocking; 254 fsl5200-clocking;
296 }; 255 };
297 256
@@ -299,14 +258,13 @@
299 #address-cells = <1>; 258 #address-cells = <1>;
300 #size-cells = <0>; 259 #size-cells = <0>;
301 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 260 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
302 cell-index = <1>;
303 reg = <0x3d40 0x40>; 261 reg = <0x3d40 0x40>;
304 interrupts = <2 16 0>; 262 interrupts = <2 16 0>;
305 interrupt-parent = <&mpc5200_pic>;
306 fsl5200-clocking; 263 fsl5200-clocking;
307 }; 264 };
265
308 sram@8000 { 266 sram@8000 {
309 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; 267 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
310 reg = <0x8000 0x4000>; 268 reg = <0x8000 0x4000>;
311 }; 269 };
312 }; 270 };
@@ -330,7 +288,6 @@
330 0xc800 0 0 4 &mpc5200_pic 0 0 3>; 288 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
331 clock-frequency = <0>; // From boot loader 289 clock-frequency = <0>; // From boot loader
332 interrupts = <2 8 0 2 9 0 2 10 0>; 290 interrupts = <2 8 0 2 9 0 2 10 0>;
333 interrupt-parent = <&mpc5200_pic>;
334 bus-range = <0 0>; 291 bus-range = <0 0>;
335 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 292 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
336 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 293 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
new file mode 100644
index 000000000000..e297d8b41875
--- /dev/null
+++ b/arch/powerpc/boot/dts/media5200.dts
@@ -0,0 +1,318 @@
1/*
2 * Freescale Media5200 board Device Tree Source
3 *
4 * Copyright 2009 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca>
6 * Steven Cavanagh <scavanagh@secretlab.ca>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "fsl,media5200";
18 compatible = "fsl,media5200";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 aliases {
24 console = &console;
25 ethernet0 = &eth0;
26 };
27
28 chosen {
29 linux,stdout-path = &console;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,5200@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <32>;
40 i-cache-line-size = <32>;
41 d-cache-size = <0x4000>; // L1, 16K
42 i-cache-size = <0x4000>; // L1, 16K
43 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
44 bus-frequency = <132000000>; // 132 MHz
45 clock-frequency = <396000000>; // 396 MHz
46 };
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x00000000 0x08000000>; // 128MB RAM
52 };
53
54 soc@f0000000 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "fsl,mpc5200b-immr";
58 ranges = <0 0xf0000000 0x0000c000>;
59 reg = <0xf0000000 0x00000100>;
60 bus-frequency = <132000000>;// 132 MHz
61 system-frequency = <0>; // from bootloader
62
63 cdm@200 {
64 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
65 reg = <0x200 0x38>;
66 };
67
68 mpc5200_pic: interrupt-controller@500 {
69 // 5200 interrupts are encoded into two levels;
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
73 reg = <0x500 0x80>;
74 };
75
76 timer@600 { // General Purpose Timer
77 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78 reg = <0x600 0x10>;
79 interrupts = <1 9 0>;
80 fsl,has-wdt;
81 };
82
83 timer@610 { // General Purpose Timer
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x610 0x10>;
86 interrupts = <1 10 0>;
87 };
88
89 timer@620 { // General Purpose Timer
90 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
91 reg = <0x620 0x10>;
92 interrupts = <1 11 0>;
93 };
94
95 timer@630 { // General Purpose Timer
96 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
97 reg = <0x630 0x10>;
98 interrupts = <1 12 0>;
99 };
100
101 timer@640 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x640 0x10>;
104 interrupts = <1 13 0>;
105 };
106
107 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 reg = <0x650 0x10>;
110 interrupts = <1 14 0>;
111 };
112
113 timer@660 { // General Purpose Timer
114 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
115 reg = <0x660 0x10>;
116 interrupts = <1 15 0>;
117 };
118
119 timer@670 { // General Purpose Timer
120 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
121 reg = <0x670 0x10>;
122 interrupts = <1 16 0>;
123 };
124
125 rtc@800 { // Real time clock
126 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
127 reg = <0x800 0x100>;
128 interrupts = <1 5 0 1 6 0>;
129 };
130
131 can@900 {
132 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
133 interrupts = <2 17 0>;
134 reg = <0x900 0x80>;
135 };
136
137 can@980 {
138 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
139 interrupts = <2 18 0>;
140 reg = <0x980 0x80>;
141 };
142
143 gpio_simple: gpio@b00 {
144 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
145 reg = <0xb00 0x40>;
146 interrupts = <1 7 0>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 };
150
151 gpio_wkup: gpio@c00 {
152 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
153 reg = <0xc00 0x40>;
154 interrupts = <1 8 0 0 3 0>;
155 gpio-controller;
156 #gpio-cells = <2>;
157 };
158
159 spi@f00 {
160 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
161 reg = <0xf00 0x20>;
162 interrupts = <2 13 0 2 14 0>;
163 };
164
165 usb@1000 {
166 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
167 reg = <0x1000 0x100>;
168 interrupts = <2 6 0>;
169 };
170
171 dma-controller@1200 {
172 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
173 reg = <0x1200 0x80>;
174 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
175 3 4 0 3 5 0 3 6 0 3 7 0
176 3 8 0 3 9 0 3 10 0 3 11 0
177 3 12 0 3 13 0 3 14 0 3 15 0>;
178 };
179
180 xlb@1f00 {
181 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
182 reg = <0x1f00 0x100>;
183 };
184
185 // PSC6 in uart mode
186 console: serial@2c00 { // PSC6
187 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
188 cell-index = <5>;
189 port-number = <0>; // Logical port assignment
190 reg = <0x2c00 0x100>;
191 interrupts = <2 4 0>;
192 };
193
194 eth0: ethernet@3000 {
195 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
196 reg = <0x3000 0x400>;
197 local-mac-address = [ 00 00 00 00 00 00 ];
198 interrupts = <2 5 0>;
199 phy-handle = <&phy0>;
200 };
201
202 mdio@3000 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
206 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
207 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
208
209 phy0: ethernet-phy@0 {
210 reg = <0>;
211 };
212 };
213
214 ata@3a00 {
215 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
216 reg = <0x3a00 0x100>;
217 interrupts = <2 7 0>;
218 };
219
220 i2c@3d00 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
224 reg = <0x3d00 0x40>;
225 interrupts = <2 15 0>;
226 fsl5200-clocking;
227 };
228
229 i2c@3d40 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
233 reg = <0x3d40 0x40>;
234 interrupts = <2 16 0>;
235 fsl5200-clocking;
236 };
237
238 sram@8000 {
239 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
240 reg = <0x8000 0x4000>;
241 };
242 };
243
244 pci@f0000d00 {
245 #interrupt-cells = <1>;
246 #size-cells = <2>;
247 #address-cells = <3>;
248 device_type = "pci";
249 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
250 reg = <0xf0000d00 0x100>;
251 interrupt-map-mask = <0xf800 0 0 7>;
252 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
253 0xc000 0 0 2 &media5200_fpga 0 3
254 0xc000 0 0 3 &media5200_fpga 0 4
255 0xc000 0 0 4 &media5200_fpga 0 5
256
257 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
258 0xc800 0 0 2 &media5200_fpga 0 4
259 0xc800 0 0 3 &media5200_fpga 0 5
260 0xc800 0 0 4 &media5200_fpga 0 2
261
262 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
263 0xd000 0 0 2 &media5200_fpga 0 5
264
265 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
266 >;
267 clock-frequency = <0>; // From boot loader
268 interrupts = <2 8 0 2 9 0 2 10 0>;
269 interrupt-parent = <&mpc5200_pic>;
270 bus-range = <0 0>;
271 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
272 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
273 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
274 };
275
276 localbus {
277 compatible = "fsl,mpc5200b-lpb","simple-bus";
278 #address-cells = <2>;
279 #size-cells = <1>;
280
281 ranges = < 0 0 0xfc000000 0x02000000
282 1 0 0xfe000000 0x02000000
283 2 0 0xf0010000 0x00010000
284 3 0 0xf0020000 0x00010000 >;
285
286 flash@0,0 {
287 compatible = "amd,am29lv28ml", "cfi-flash";
288 reg = <0 0x0 0x2000000>; // 32 MB
289 bank-width = <4>; // Width in bytes of the flash bank
290 device-width = <2>; // Two devices on each bank
291 };
292
293 flash@1,0 {
294 compatible = "amd,am29lv28ml", "cfi-flash";
295 reg = <1 0 0x2000000>; // 32 MB
296 bank-width = <4>; // Width in bytes of the flash bank
297 device-width = <2>; // Two devices on each bank
298 };
299
300 media5200_fpga: fpga@2,0 {
301 compatible = "fsl,media5200-fpga";
302 interrupt-controller;
303 #interrupt-cells = <2>; // 0:bank 1:id; no type field
304 reg = <2 0 0x10000>;
305
306 interrupt-parent = <&mpc5200_pic>;
307 interrupts = <0 0 3 // IRQ bank 0
308 1 1 3>; // IRQ bank 1
309 };
310
311 uart@3,0 {
312 compatible = "ti,tl16c752bpt";
313 reg = <3 0 0x10000>;
314 interrupt-parent = <&media5200_fpga>;
315 interrupts = <0 0 0 1>; // 2 irqs
316 };
317 };
318};
diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
index 52ba6f98b273..7be8ca038676 100644
--- a/arch/powerpc/boot/dts/motionpro.dts
+++ b/arch/powerpc/boot/dts/motionpro.dts
@@ -17,6 +17,7 @@
17 compatible = "promess,motionpro"; 17 compatible = "promess,motionpro";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -66,7 +67,6 @@
66 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
67 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
68 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt; 70 fsl,has-wdt;
71 }; 71 };
72 72
@@ -74,35 +74,30 @@
74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 74 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
75 reg = <0x610 0x10>; 75 reg = <0x610 0x10>;
76 interrupts = <1 10 0>; 76 interrupts = <1 10 0>;
77 interrupt-parent = <&mpc5200_pic>;
78 }; 77 };
79 78
80 timer@620 { // General Purpose Timer 79 timer@620 { // General Purpose Timer
81 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 80 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
82 reg = <0x620 0x10>; 81 reg = <0x620 0x10>;
83 interrupts = <1 11 0>; 82 interrupts = <1 11 0>;
84 interrupt-parent = <&mpc5200_pic>;
85 }; 83 };
86 84
87 timer@630 { // General Purpose Timer 85 timer@630 { // General Purpose Timer
88 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
89 reg = <0x630 0x10>; 87 reg = <0x630 0x10>;
90 interrupts = <1 12 0>; 88 interrupts = <1 12 0>;
91 interrupt-parent = <&mpc5200_pic>;
92 }; 89 };
93 90
94 timer@640 { // General Purpose Timer 91 timer@640 { // General Purpose Timer
95 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 92 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
96 reg = <0x640 0x10>; 93 reg = <0x640 0x10>;
97 interrupts = <1 13 0>; 94 interrupts = <1 13 0>;
98 interrupt-parent = <&mpc5200_pic>;
99 }; 95 };
100 96
101 timer@650 { // General Purpose Timer 97 timer@650 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x650 0x10>; 99 reg = <0x650 0x10>;
104 interrupts = <1 14 0>; 100 interrupts = <1 14 0>;
105 interrupt-parent = <&mpc5200_pic>;
106 }; 101 };
107 102
108 motionpro-led@660 { // Motion-PRO status LED 103 motionpro-led@660 { // Motion-PRO status LED
@@ -110,7 +105,6 @@
110 label = "motionpro-statusled"; 105 label = "motionpro-statusled";
111 reg = <0x660 0x10>; 106 reg = <0x660 0x10>;
112 interrupts = <1 15 0>; 107 interrupts = <1 15 0>;
113 interrupt-parent = <&mpc5200_pic>;
114 blink-delay = <100>; // 100 msec 108 blink-delay = <100>; // 100 msec
115 }; 109 };
116 110
@@ -119,49 +113,46 @@
119 label = "motionpro-readyled"; 113 label = "motionpro-readyled";
120 reg = <0x670 0x10>; 114 reg = <0x670 0x10>;
121 interrupts = <1 16 0>; 115 interrupts = <1 16 0>;
122 interrupt-parent = <&mpc5200_pic>;
123 }; 116 };
124 117
125 rtc@800 { // Real time clock 118 rtc@800 { // Real time clock
126 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 119 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
127 reg = <0x800 0x100>; 120 reg = <0x800 0x100>;
128 interrupts = <1 5 0 1 6 0>; 121 interrupts = <1 5 0 1 6 0>;
129 interrupt-parent = <&mpc5200_pic>;
130 }; 122 };
131 123
132 can@980 { 124 can@980 {
133 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 125 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
134 interrupts = <2 18 0>; 126 interrupts = <2 18 0>;
135 interrupt-parent = <&mpc5200_pic>;
136 reg = <0x980 0x80>; 127 reg = <0x980 0x80>;
137 }; 128 };
138 129
139 gpio@b00 { 130 gpio_simple: gpio@b00 {
140 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 131 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
141 reg = <0xb00 0x40>; 132 reg = <0xb00 0x40>;
142 interrupts = <1 7 0>; 133 interrupts = <1 7 0>;
143 interrupt-parent = <&mpc5200_pic>; 134 gpio-controller;
135 #gpio-cells = <2>;
144 }; 136 };
145 137
146 gpio@c00 { 138 gpio_wkup: gpio@c00 {
147 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 139 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
148 reg = <0xc00 0x40>; 140 reg = <0xc00 0x40>;
149 interrupts = <1 8 0 0 3 0>; 141 interrupts = <1 8 0 0 3 0>;
150 interrupt-parent = <&mpc5200_pic>; 142 gpio-controller;
143 #gpio-cells = <2>;
151 }; 144 };
152 145
153 spi@f00 { 146 spi@f00 {
154 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 147 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
155 reg = <0xf00 0x20>; 148 reg = <0xf00 0x20>;
156 interrupts = <2 13 0 2 14 0>; 149 interrupts = <2 13 0 2 14 0>;
157 interrupt-parent = <&mpc5200_pic>;
158 }; 150 };
159 151
160 usb@1000 { 152 usb@1000 {
161 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 153 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
162 reg = <0x1000 0xff>; 154 reg = <0x1000 0xff>;
163 interrupts = <2 6 0>; 155 interrupts = <2 6 0>;
164 interrupt-parent = <&mpc5200_pic>;
165 }; 156 };
166 157
167 dma-controller@1200 { 158 dma-controller@1200 {
@@ -171,7 +162,6 @@
171 3 4 0 3 5 0 3 6 0 3 7 0 162 3 4 0 3 5 0 3 6 0 3 7 0
172 3 8 0 3 9 0 3 10 0 3 11 0 163 3 8 0 3 9 0 3 10 0 3 11 0
173 3 12 0 3 13 0 3 14 0 3 15 0>; 164 3 12 0 3 13 0 3 14 0 3 15 0>;
174 interrupt-parent = <&mpc5200_pic>;
175 }; 165 };
176 166
177 xlb@1f00 { 167 xlb@1f00 {
@@ -180,12 +170,9 @@
180 }; 170 };
181 171
182 serial@2000 { // PSC1 172 serial@2000 { // PSC1
183 device_type = "serial";
184 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 173 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
185 port-number = <0>; // Logical port assignment
186 reg = <0x2000 0x100>; 174 reg = <0x2000 0x100>;
187 interrupts = <2 1 0>; 175 interrupts = <2 1 0>;
188 interrupt-parent = <&mpc5200_pic>;
189 }; 176 };
190 177
191 // PSC2 in spi master mode 178 // PSC2 in spi master mode
@@ -194,26 +181,20 @@
194 cell-index = <1>; 181 cell-index = <1>;
195 reg = <0x2200 0x100>; 182 reg = <0x2200 0x100>;
196 interrupts = <2 2 0>; 183 interrupts = <2 2 0>;
197 interrupt-parent = <&mpc5200_pic>;
198 }; 184 };
199 185
200 // PSC5 in uart mode 186 // PSC5 in uart mode
201 serial@2800 { // PSC5 187 serial@2800 { // PSC5
202 device_type = "serial";
203 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 188 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
204 port-number = <4>; // Logical port assignment
205 reg = <0x2800 0x100>; 189 reg = <0x2800 0x100>;
206 interrupts = <2 12 0>; 190 interrupts = <2 12 0>;
207 interrupt-parent = <&mpc5200_pic>;
208 }; 191 };
209 192
210 ethernet@3000 { 193 ethernet@3000 {
211 device_type = "network";
212 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 194 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
213 reg = <0x3000 0x400>; 195 reg = <0x3000 0x400>;
214 local-mac-address = [ 00 00 00 00 00 00 ]; 196 local-mac-address = [ 00 00 00 00 00 00 ];
215 interrupts = <2 5 0>; 197 interrupts = <2 5 0>;
216 interrupt-parent = <&mpc5200_pic>;
217 phy-handle = <&phy0>; 198 phy-handle = <&phy0>;
218 }; 199 };
219 200
@@ -223,10 +204,8 @@
223 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 204 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
224 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 205 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
225 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 206 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
226 interrupt-parent = <&mpc5200_pic>;
227 207
228 phy0: ethernet-phy@2 { 208 phy0: ethernet-phy@2 {
229 device_type = "ethernet-phy";
230 reg = <2>; 209 reg = <2>;
231 }; 210 };
232 }; 211 };
@@ -235,7 +214,6 @@
235 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 214 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
236 reg = <0x3a00 0x100>; 215 reg = <0x3a00 0x100>;
237 interrupts = <2 7 0>; 216 interrupts = <2 7 0>;
238 interrupt-parent = <&mpc5200_pic>;
239 }; 217 };
240 218
241 i2c@3d40 { 219 i2c@3d40 {
@@ -244,7 +222,6 @@
244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 222 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
245 reg = <0x3d40 0x40>; 223 reg = <0x3d40 0x40>;
246 interrupts = <2 16 0>; 224 interrupts = <2 16 0>;
247 interrupt-parent = <&mpc5200_pic>;
248 fsl5200-clocking; 225 fsl5200-clocking;
249 226
250 rtc@68 { 227 rtc@68 {
@@ -259,8 +236,8 @@
259 }; 236 };
260 }; 237 };
261 238
262 lpb { 239 localbus {
263 compatible = "fsl,lpb"; 240 compatible = "fsl,mpc5200b-lpb","simple-bus";
264 #address-cells = <2>; 241 #address-cells = <2>;
265 #size-cells = <1>; 242 #size-cells = <1>;
266 ranges = <0 0 0xff000000 0x01000000 243 ranges = <0 0 0xff000000 0x01000000
@@ -273,7 +250,6 @@
273 compatible = "promess,motionpro-kollmorgen"; 250 compatible = "promess,motionpro-kollmorgen";
274 reg = <1 0 0x10000>; 251 reg = <1 0 0x10000>;
275 interrupts = <1 1 0>; 252 interrupts = <1 1 0>;
276 interrupt-parent = <&mpc5200_pic>;
277 }; 253 };
278 254
279 // 8-bit board CPLD on LocalPlus Bus CS2 255 // 8-bit board CPLD on LocalPlus Bus CS2
diff --git a/arch/powerpc/boot/dts/mpc8315erdb.dts b/arch/powerpc/boot/dts/mpc8315erdb.dts
index 71784165b77e..88d691cccb38 100644
--- a/arch/powerpc/boot/dts/mpc8315erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8315erdb.dts
@@ -22,6 +22,8 @@
22 serial0 = &serial0; 22 serial0 = &serial0;
23 serial1 = &serial1; 23 serial1 = &serial1;
24 pci0 = &pci0; 24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
25 }; 27 };
26 28
27 cpus { 29 cpus {
@@ -349,4 +351,66 @@
349 compatible = "fsl,mpc8349-pci"; 351 compatible = "fsl,mpc8349-pci";
350 device_type = "pci"; 352 device_type = "pci";
351 }; 353 };
354
355 pci1: pcie@e0009000 {
356 #address-cells = <3>;
357 #size-cells = <2>;
358 #interrupt-cells = <1>;
359 device_type = "pci";
360 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
361 reg = <0xe0009000 0x00001000>;
362 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
363 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
364 bus-range = <0 255>;
365 interrupt-map-mask = <0xf800 0 0 7>;
366 interrupt-map = <0 0 0 1 &ipic 1 8
367 0 0 0 2 &ipic 1 8
368 0 0 0 3 &ipic 1 8
369 0 0 0 4 &ipic 1 8>;
370 clock-frequency = <0>;
371
372 pcie@0 {
373 #address-cells = <3>;
374 #size-cells = <2>;
375 device_type = "pci";
376 reg = <0 0 0 0 0>;
377 ranges = <0x02000000 0 0xa0000000
378 0x02000000 0 0xa0000000
379 0 0x10000000
380 0x01000000 0 0x00000000
381 0x01000000 0 0x00000000
382 0 0x00800000>;
383 };
384 };
385
386 pci2: pcie@e000a000 {
387 #address-cells = <3>;
388 #size-cells = <2>;
389 #interrupt-cells = <1>;
390 device_type = "pci";
391 compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie";
392 reg = <0xe000a000 0x00001000>;
393 ranges = <0x02000000 0 0xc0000000 0xc0000000 0 0x10000000
394 0x01000000 0 0x00000000 0xd1000000 0 0x00800000>;
395 bus-range = <0 255>;
396 interrupt-map-mask = <0xf800 0 0 7>;
397 interrupt-map = <0 0 0 1 &ipic 2 8
398 0 0 0 2 &ipic 2 8
399 0 0 0 3 &ipic 2 8
400 0 0 0 4 &ipic 2 8>;
401 clock-frequency = <0>;
402
403 pcie@0 {
404 #address-cells = <3>;
405 #size-cells = <2>;
406 device_type = "pci";
407 reg = <0 0 0 0 0>;
408 ranges = <0x02000000 0 0xc0000000
409 0x02000000 0 0xc0000000
410 0 0x10000000
411 0x01000000 0 0x00000000
412 0x01000000 0 0x00000000
413 0 0x00800000>;
414 };
415 };
352}; 416};
diff --git a/arch/powerpc/boot/dts/mpc8377_mds.dts b/arch/powerpc/boot/dts/mpc8377_mds.dts
index 1d14d7052e6d..3e3ec8fdef49 100644
--- a/arch/powerpc/boot/dts/mpc8377_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8377_mds.dts
@@ -23,6 +23,8 @@
23 serial0 = &serial0; 23 serial0 = &serial0;
24 serial1 = &serial1; 24 serial1 = &serial1;
25 pci0 = &pci0; 25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
26 }; 28 };
27 29
28 cpus { 30 cpus {
@@ -311,12 +313,13 @@
311 fsl,descriptor-types-mask = <0x3ab0ebf>; 313 fsl,descriptor-types-mask = <0x3ab0ebf>;
312 }; 314 };
313 315
314 sdhc@2e000 { 316 sdhci@2e000 {
315 model = "eSDHC"; 317 compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
316 compatible = "fsl,esdhc";
317 reg = <0x2e000 0x1000>; 318 reg = <0x2e000 0x1000>;
318 interrupts = <42 0x8>; 319 interrupts = <42 0x8>;
319 interrupt-parent = <&ipic>; 320 interrupt-parent = <&ipic>;
321 /* Filled in by U-Boot */
322 clock-frequency = <0>;
320 }; 323 };
321 324
322 sata@18000 { 325 sata@18000 {
@@ -409,4 +412,66 @@
409 compatible = "fsl,mpc8349-pci"; 412 compatible = "fsl,mpc8349-pci";
410 device_type = "pci"; 413 device_type = "pci";
411 }; 414 };
415
416 pci1: pcie@e0009000 {
417 #address-cells = <3>;
418 #size-cells = <2>;
419 #interrupt-cells = <1>;
420 device_type = "pci";
421 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
422 reg = <0xe0009000 0x00001000>;
423 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
424 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
425 bus-range = <0 255>;
426 interrupt-map-mask = <0xf800 0 0 7>;
427 interrupt-map = <0 0 0 1 &ipic 1 8
428 0 0 0 2 &ipic 1 8
429 0 0 0 3 &ipic 1 8
430 0 0 0 4 &ipic 1 8>;
431 clock-frequency = <0>;
432
433 pcie@0 {
434 #address-cells = <3>;
435 #size-cells = <2>;
436 device_type = "pci";
437 reg = <0 0 0 0 0>;
438 ranges = <0x02000000 0 0xa8000000
439 0x02000000 0 0xa8000000
440 0 0x10000000
441 0x01000000 0 0x00000000
442 0x01000000 0 0x00000000
443 0 0x00800000>;
444 };
445 };
446
447 pci2: pcie@e000a000 {
448 #address-cells = <3>;
449 #size-cells = <2>;
450 #interrupt-cells = <1>;
451 device_type = "pci";
452 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
453 reg = <0xe000a000 0x00001000>;
454 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
455 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
456 bus-range = <0 255>;
457 interrupt-map-mask = <0xf800 0 0 7>;
458 interrupt-map = <0 0 0 1 &ipic 2 8
459 0 0 0 2 &ipic 2 8
460 0 0 0 3 &ipic 2 8
461 0 0 0 4 &ipic 2 8>;
462 clock-frequency = <0>;
463
464 pcie@0 {
465 #address-cells = <3>;
466 #size-cells = <2>;
467 device_type = "pci";
468 reg = <0 0 0 0 0>;
469 ranges = <0x02000000 0 0xc8000000
470 0x02000000 0 0xc8000000
471 0 0x10000000
472 0x01000000 0 0x00000000
473 0x01000000 0 0x00000000
474 0 0x00800000>;
475 };
476 };
412}; 477};
diff --git a/arch/powerpc/boot/dts/mpc8377_rdb.dts b/arch/powerpc/boot/dts/mpc8377_rdb.dts
index 9413af3b9925..fb1d884348ec 100644
--- a/arch/powerpc/boot/dts/mpc8377_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8377_rdb.dts
@@ -22,6 +22,8 @@
22 serial0 = &serial0; 22 serial0 = &serial0;
23 serial1 = &serial1; 23 serial1 = &serial1;
24 pci0 = &pci0; 24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
25 }; 27 };
26 28
27 cpus { 29 cpus {
@@ -107,6 +109,24 @@
107 reg = <0x200 0x100>; 109 reg = <0x200 0x100>;
108 }; 110 };
109 111
112 gpio1: gpio-controller@c00 {
113 #gpio-cells = <2>;
114 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
115 reg = <0xc00 0x100>;
116 interrupts = <74 0x8>;
117 interrupt-parent = <&ipic>;
118 gpio-controller;
119 };
120
121 gpio2: gpio-controller@d00 {
122 #gpio-cells = <2>;
123 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
124 reg = <0xd00 0x100>;
125 interrupts = <75 0x8>;
126 interrupt-parent = <&ipic>;
127 gpio-controller;
128 };
129
110 i2c@3000 { 130 i2c@3000 {
111 #address-cells = <1>; 131 #address-cells = <1>;
112 #size-cells = <0>; 132 #size-cells = <0>;
@@ -116,6 +136,17 @@
116 interrupts = <14 0x8>; 136 interrupts = <14 0x8>;
117 interrupt-parent = <&ipic>; 137 interrupt-parent = <&ipic>;
118 dfsrr; 138 dfsrr;
139
140 dtt@48 {
141 compatible = "national,lm75";
142 reg = <0x48>;
143 };
144
145 at24@50 {
146 compatible = "at24,24c256";
147 reg = <0x50>;
148 };
149
119 rtc@68 { 150 rtc@68 {
120 compatible = "dallas,ds1339"; 151 compatible = "dallas,ds1339";
121 reg = <0x68>; 152 reg = <0x68>;
@@ -289,6 +320,15 @@
289 fsl,descriptor-types-mask = <0x3ab0ebf>; 320 fsl,descriptor-types-mask = <0x3ab0ebf>;
290 }; 321 };
291 322
323 sdhci@2e000 {
324 compatible = "fsl,mpc8377-esdhc", "fsl,mpc8379-esdhc";
325 reg = <0x2e000 0x1000>;
326 interrupts = <42 0x8>;
327 interrupt-parent = <&ipic>;
328 /* Filled in by U-Boot */
329 clock-frequency = <0>;
330 };
331
292 sata@18000 { 332 sata@18000 {
293 compatible = "fsl,mpc8377-sata", "fsl,pq-sata"; 333 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
294 reg = <0x18000 0x1000>; 334 reg = <0x18000 0x1000>;
@@ -350,4 +390,66 @@
350 compatible = "fsl,mpc8349-pci"; 390 compatible = "fsl,mpc8349-pci";
351 device_type = "pci"; 391 device_type = "pci";
352 }; 392 };
393
394 pci1: pcie@e0009000 {
395 #address-cells = <3>;
396 #size-cells = <2>;
397 #interrupt-cells = <1>;
398 device_type = "pci";
399 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
400 reg = <0xe0009000 0x00001000>;
401 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
402 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
403 bus-range = <0 255>;
404 interrupt-map-mask = <0xf800 0 0 7>;
405 interrupt-map = <0 0 0 1 &ipic 1 8
406 0 0 0 2 &ipic 1 8
407 0 0 0 3 &ipic 1 8
408 0 0 0 4 &ipic 1 8>;
409 clock-frequency = <0>;
410
411 pcie@0 {
412 #address-cells = <3>;
413 #size-cells = <2>;
414 device_type = "pci";
415 reg = <0 0 0 0 0>;
416 ranges = <0x02000000 0 0xa8000000
417 0x02000000 0 0xa8000000
418 0 0x10000000
419 0x01000000 0 0x00000000
420 0x01000000 0 0x00000000
421 0 0x00800000>;
422 };
423 };
424
425 pci2: pcie@e000a000 {
426 #address-cells = <3>;
427 #size-cells = <2>;
428 #interrupt-cells = <1>;
429 device_type = "pci";
430 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
431 reg = <0xe000a000 0x00001000>;
432 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
433 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
434 bus-range = <0 255>;
435 interrupt-map-mask = <0xf800 0 0 7>;
436 interrupt-map = <0 0 0 1 &ipic 2 8
437 0 0 0 2 &ipic 2 8
438 0 0 0 3 &ipic 2 8
439 0 0 0 4 &ipic 2 8>;
440 clock-frequency = <0>;
441
442 pcie@0 {
443 #address-cells = <3>;
444 #size-cells = <2>;
445 device_type = "pci";
446 reg = <0 0 0 0 0>;
447 ranges = <0x02000000 0 0xc8000000
448 0x02000000 0 0xc8000000
449 0 0x10000000
450 0x01000000 0 0x00000000
451 0x01000000 0 0x00000000
452 0 0x00800000>;
453 };
454 };
353}; 455};
diff --git a/arch/powerpc/boot/dts/mpc8378_mds.dts b/arch/powerpc/boot/dts/mpc8378_mds.dts
index b85fc02682d2..c3b212cf9025 100644
--- a/arch/powerpc/boot/dts/mpc8378_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8378_mds.dts
@@ -23,6 +23,8 @@
23 serial0 = &serial0; 23 serial0 = &serial0;
24 serial1 = &serial1; 24 serial1 = &serial1;
25 pci0 = &pci0; 25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
26 }; 28 };
27 29
28 cpus { 30 cpus {
@@ -311,12 +313,13 @@
311 fsl,descriptor-types-mask = <0x3ab0ebf>; 313 fsl,descriptor-types-mask = <0x3ab0ebf>;
312 }; 314 };
313 315
314 sdhc@2e000 { 316 sdhci@2e000 {
315 model = "eSDHC"; 317 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
316 compatible = "fsl,esdhc";
317 reg = <0x2e000 0x1000>; 318 reg = <0x2e000 0x1000>;
318 interrupts = <42 0x8>; 319 interrupts = <42 0x8>;
319 interrupt-parent = <&ipic>; 320 interrupt-parent = <&ipic>;
321 /* Filled in by U-Boot */
322 clock-frequency = <0>;
320 }; 323 };
321 324
322 /* IPIC 325 /* IPIC
@@ -395,4 +398,66 @@
395 compatible = "fsl,mpc8349-pci"; 398 compatible = "fsl,mpc8349-pci";
396 device_type = "pci"; 399 device_type = "pci";
397 }; 400 };
401
402 pci1: pcie@e0009000 {
403 #address-cells = <3>;
404 #size-cells = <2>;
405 #interrupt-cells = <1>;
406 device_type = "pci";
407 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
408 reg = <0xe0009000 0x00001000>;
409 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
410 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
411 bus-range = <0 255>;
412 interrupt-map-mask = <0xf800 0 0 7>;
413 interrupt-map = <0 0 0 1 &ipic 1 8
414 0 0 0 2 &ipic 1 8
415 0 0 0 3 &ipic 1 8
416 0 0 0 4 &ipic 1 8>;
417 clock-frequency = <0>;
418
419 pcie@0 {
420 #address-cells = <3>;
421 #size-cells = <2>;
422 device_type = "pci";
423 reg = <0 0 0 0 0>;
424 ranges = <0x02000000 0 0xa8000000
425 0x02000000 0 0xa8000000
426 0 0x10000000
427 0x01000000 0 0x00000000
428 0x01000000 0 0x00000000
429 0 0x00800000>;
430 };
431 };
432
433 pci2: pcie@e000a000 {
434 #address-cells = <3>;
435 #size-cells = <2>;
436 #interrupt-cells = <1>;
437 device_type = "pci";
438 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
439 reg = <0xe000a000 0x00001000>;
440 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
441 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
442 bus-range = <0 255>;
443 interrupt-map-mask = <0xf800 0 0 7>;
444 interrupt-map = <0 0 0 1 &ipic 2 8
445 0 0 0 2 &ipic 2 8
446 0 0 0 3 &ipic 2 8
447 0 0 0 4 &ipic 2 8>;
448 clock-frequency = <0>;
449
450 pcie@0 {
451 #address-cells = <3>;
452 #size-cells = <2>;
453 device_type = "pci";
454 reg = <0 0 0 0 0>;
455 ranges = <0x02000000 0 0xc8000000
456 0x02000000 0 0xc8000000
457 0 0x10000000
458 0x01000000 0 0x00000000
459 0x01000000 0 0x00000000
460 0 0x00800000>;
461 };
462 };
398}; 463};
diff --git a/arch/powerpc/boot/dts/mpc8378_rdb.dts b/arch/powerpc/boot/dts/mpc8378_rdb.dts
index 23c10ce22c2c..37c8555cc8d4 100644
--- a/arch/powerpc/boot/dts/mpc8378_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8378_rdb.dts
@@ -22,6 +22,8 @@
22 serial0 = &serial0; 22 serial0 = &serial0;
23 serial1 = &serial1; 23 serial1 = &serial1;
24 pci0 = &pci0; 24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
25 }; 27 };
26 28
27 cpus { 29 cpus {
@@ -107,6 +109,24 @@
107 reg = <0x200 0x100>; 109 reg = <0x200 0x100>;
108 }; 110 };
109 111
112 gpio1: gpio-controller@c00 {
113 #gpio-cells = <2>;
114 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
115 reg = <0xc00 0x100>;
116 interrupts = <74 0x8>;
117 interrupt-parent = <&ipic>;
118 gpio-controller;
119 };
120
121 gpio2: gpio-controller@d00 {
122 #gpio-cells = <2>;
123 compatible = "fsl,mpc8378-gpio", "fsl,mpc8349-gpio";
124 reg = <0xd00 0x100>;
125 interrupts = <75 0x8>;
126 interrupt-parent = <&ipic>;
127 gpio-controller;
128 };
129
110 i2c@3000 { 130 i2c@3000 {
111 #address-cells = <1>; 131 #address-cells = <1>;
112 #size-cells = <0>; 132 #size-cells = <0>;
@@ -116,6 +136,17 @@
116 interrupts = <14 0x8>; 136 interrupts = <14 0x8>;
117 interrupt-parent = <&ipic>; 137 interrupt-parent = <&ipic>;
118 dfsrr; 138 dfsrr;
139
140 dtt@48 {
141 compatible = "national,lm75";
142 reg = <0x48>;
143 };
144
145 at24@50 {
146 compatible = "at24,24c256";
147 reg = <0x50>;
148 };
149
119 rtc@68 { 150 rtc@68 {
120 compatible = "dallas,ds1339"; 151 compatible = "dallas,ds1339";
121 reg = <0x68>; 152 reg = <0x68>;
@@ -287,6 +318,15 @@
287 fsl,descriptor-types-mask = <0x3ab0ebf>; 318 fsl,descriptor-types-mask = <0x3ab0ebf>;
288 }; 319 };
289 320
321 sdhci@2e000 {
322 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
323 reg = <0x2e000 0x1000>;
324 interrupts = <42 0x8>;
325 interrupt-parent = <&ipic>;
326 /* Filled in by U-Boot */
327 clock-frequency = <0>;
328 };
329
290 /* IPIC 330 /* IPIC
291 * interrupts cell = <intr #, sense> 331 * interrupts cell = <intr #, sense>
292 * sense values match linux IORESOURCE_IRQ_* defines: 332 * sense values match linux IORESOURCE_IRQ_* defines:
@@ -334,4 +374,66 @@
334 compatible = "fsl,mpc8349-pci"; 374 compatible = "fsl,mpc8349-pci";
335 device_type = "pci"; 375 device_type = "pci";
336 }; 376 };
377
378 pci1: pcie@e0009000 {
379 #address-cells = <3>;
380 #size-cells = <2>;
381 #interrupt-cells = <1>;
382 device_type = "pci";
383 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
384 reg = <0xe0009000 0x00001000>;
385 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
386 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
387 bus-range = <0 255>;
388 interrupt-map-mask = <0xf800 0 0 7>;
389 interrupt-map = <0 0 0 1 &ipic 1 8
390 0 0 0 2 &ipic 1 8
391 0 0 0 3 &ipic 1 8
392 0 0 0 4 &ipic 1 8>;
393 clock-frequency = <0>;
394
395 pcie@0 {
396 #address-cells = <3>;
397 #size-cells = <2>;
398 device_type = "pci";
399 reg = <0 0 0 0 0>;
400 ranges = <0x02000000 0 0xa8000000
401 0x02000000 0 0xa8000000
402 0 0x10000000
403 0x01000000 0 0x00000000
404 0x01000000 0 0x00000000
405 0 0x00800000>;
406 };
407 };
408
409 pci2: pcie@e000a000 {
410 #address-cells = <3>;
411 #size-cells = <2>;
412 #interrupt-cells = <1>;
413 device_type = "pci";
414 compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
415 reg = <0xe000a000 0x00001000>;
416 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
417 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
418 bus-range = <0 255>;
419 interrupt-map-mask = <0xf800 0 0 7>;
420 interrupt-map = <0 0 0 1 &ipic 2 8
421 0 0 0 2 &ipic 2 8
422 0 0 0 3 &ipic 2 8
423 0 0 0 4 &ipic 2 8>;
424 clock-frequency = <0>;
425
426 pcie@0 {
427 #address-cells = <3>;
428 #size-cells = <2>;
429 device_type = "pci";
430 reg = <0 0 0 0 0>;
431 ranges = <0x02000000 0 0xc8000000
432 0x02000000 0 0xc8000000
433 0 0x10000000
434 0x01000000 0 0x00000000
435 0x01000000 0 0x00000000
436 0 0x00800000>;
437 };
438 };
337}; 439};
diff --git a/arch/powerpc/boot/dts/mpc8379_mds.dts b/arch/powerpc/boot/dts/mpc8379_mds.dts
index acf06c438dbf..1b61cda1eb47 100644
--- a/arch/powerpc/boot/dts/mpc8379_mds.dts
+++ b/arch/powerpc/boot/dts/mpc8379_mds.dts
@@ -310,12 +310,13 @@
310 fsl,descriptor-types-mask = <0x3ab0ebf>; 310 fsl,descriptor-types-mask = <0x3ab0ebf>;
311 }; 311 };
312 312
313 sdhc@2e000 { 313 sdhci@2e000 {
314 model = "eSDHC"; 314 compatible = "fsl,mpc8379-esdhc";
315 compatible = "fsl,esdhc";
316 reg = <0x2e000 0x1000>; 315 reg = <0x2e000 0x1000>;
317 interrupts = <42 0x8>; 316 interrupts = <42 0x8>;
318 interrupt-parent = <&ipic>; 317 interrupt-parent = <&ipic>;
318 /* Filled in by U-Boot */
319 clock-frequency = <0>;
319 }; 320 };
320 321
321 sata@18000 { 322 sata@18000 {
diff --git a/arch/powerpc/boot/dts/mpc8379_rdb.dts b/arch/powerpc/boot/dts/mpc8379_rdb.dts
index 72cdc3c4c7e3..e2f98e6a51a2 100644
--- a/arch/powerpc/boot/dts/mpc8379_rdb.dts
+++ b/arch/powerpc/boot/dts/mpc8379_rdb.dts
@@ -107,6 +107,24 @@
107 reg = <0x200 0x100>; 107 reg = <0x200 0x100>;
108 }; 108 };
109 109
110 gpio1: gpio-controller@c00 {
111 #gpio-cells = <2>;
112 compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio";
113 reg = <0xc00 0x100>;
114 interrupts = <74 0x8>;
115 interrupt-parent = <&ipic>;
116 gpio-controller;
117 };
118
119 gpio2: gpio-controller@d00 {
120 #gpio-cells = <2>;
121 compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio";
122 reg = <0xd00 0x100>;
123 interrupts = <75 0x8>;
124 interrupt-parent = <&ipic>;
125 gpio-controller;
126 };
127
110 i2c@3000 { 128 i2c@3000 {
111 #address-cells = <1>; 129 #address-cells = <1>;
112 #size-cells = <0>; 130 #size-cells = <0>;
@@ -116,6 +134,17 @@
116 interrupts = <14 0x8>; 134 interrupts = <14 0x8>;
117 interrupt-parent = <&ipic>; 135 interrupt-parent = <&ipic>;
118 dfsrr; 136 dfsrr;
137
138 dtt@48 {
139 compatible = "national,lm75";
140 reg = <0x48>;
141 };
142
143 at24@50 {
144 compatible = "at24,24c256";
145 reg = <0x50>;
146 };
147
119 rtc@68 { 148 rtc@68 {
120 compatible = "dallas,ds1339"; 149 compatible = "dallas,ds1339";
121 reg = <0x68>; 150 reg = <0x68>;
@@ -288,6 +317,15 @@
288 fsl,descriptor-types-mask = <0x3ab0ebf>; 317 fsl,descriptor-types-mask = <0x3ab0ebf>;
289 }; 318 };
290 319
320 sdhci@2e000 {
321 compatible = "fsl,mpc8379-esdhc";
322 reg = <0x2e000 0x1000>;
323 interrupts = <42 0x8>;
324 interrupt-parent = <&ipic>;
325 /* Filled in by U-Boot */
326 clock-frequency = <0>;
327 };
328
291 sata@18000 { 329 sata@18000 {
292 compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; 330 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
293 reg = <0x18000 0x1000>; 331 reg = <0x18000 0x1000>;
diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
index be2c11ca0594..895834713894 100644
--- a/arch/powerpc/boot/dts/pcm030.dts
+++ b/arch/powerpc/boot/dts/pcm030.dts
@@ -19,6 +19,7 @@
19 compatible = "phytec,pcm030"; 19 compatible = "phytec,pcm030";
20 #address-cells = <1>; 20 #address-cells = <1>;
21 #size-cells = <1>; 21 #size-cells = <1>;
22 interrupt-parent = <&mpc5200_pic>;
22 23
23 cpus { 24 cpus {
24 #address-cells = <1>; 25 #address-cells = <1>;
@@ -29,26 +30,26 @@
29 reg = <0>; 30 reg = <0>;
30 d-cache-line-size = <32>; 31 d-cache-line-size = <32>;
31 i-cache-line-size = <32>; 32 i-cache-line-size = <32>;
32 d-cache-size = <0x4000>; /* L1, 16K */ 33 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; /* L1, 16K */ 34 i-cache-size = <0x4000>; // L1, 16K
34 timebase-frequency = <0>; /* From Bootloader */ 35 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; /* From Bootloader */ 36 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; /* From Bootloader */ 37 clock-frequency = <0>; // from bootloader
37 }; 38 };
38 }; 39 };
39 40
40 memory { 41 memory {
41 device_type = "memory"; 42 device_type = "memory";
42 reg = <0x00000000 0x04000000>; /* 64MB */ 43 reg = <0x00000000 0x04000000>; // 64MB
43 }; 44 };
44 45
45 soc5200@f0000000 { 46 soc5200@f0000000 {
46 #address-cells = <1>; 47 #address-cells = <1>;
47 #size-cells = <1>; 48 #size-cells = <1>;
48 compatible = "fsl,mpc5200b-immr"; 49 compatible = "fsl,mpc5200b-immr";
49 ranges = <0x0 0xf0000000 0x0000c000>; 50 ranges = <0 0xf0000000 0x0000c000>;
50 bus-frequency = <0>; /* From bootloader */ 51 bus-frequency = <0>; // from bootloader
51 system-frequency = <0>; /* From bootloader */ 52 system-frequency = <0>; // from bootloader
52 53
53 cdm@200 { 54 cdm@200 {
54 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
@@ -56,87 +57,70 @@
56 }; 57 };
57 58
58 mpc5200_pic: interrupt-controller@500 { 59 mpc5200_pic: interrupt-controller@500 {
59 /* 5200 interrupts are encoded into two levels; */ 60 // 5200 interrupts are encoded into two levels;
60 interrupt-controller; 61 interrupt-controller;
61 #interrupt-cells = <3>; 62 #interrupt-cells = <3>;
62 device_type = "interrupt-controller";
63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64 reg = <0x500 0x80>; 64 reg = <0x500 0x80>;
65 }; 65 };
66 66
67 timer@600 { /* General Purpose Timer */ 67 timer@600 { // General Purpose Timer
68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69 cell-index = <0>;
70 reg = <0x600 0x10>; 69 reg = <0x600 0x10>;
71 interrupts = <0x1 0x9 0x0>; 70 interrupts = <1 9 0>;
72 interrupt-parent = <&mpc5200_pic>;
73 fsl,has-wdt; 71 fsl,has-wdt;
74 }; 72 };
75 73
76 timer@610 { /* General Purpose Timer */ 74 timer@610 { // General Purpose Timer
77 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 75 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78 cell-index = <1>;
79 reg = <0x610 0x10>; 76 reg = <0x610 0x10>;
80 interrupts = <0x1 0xa 0x0>; 77 interrupts = <1 10 0>;
81 interrupt-parent = <&mpc5200_pic>;
82 }; 78 };
83 79
84 gpt2: timer@620 { /* General Purpose Timer in GPIO mode */ 80 gpt2: timer@620 { // General Purpose Timer in GPIO mode
85 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 81 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
86 cell-index = <2>;
87 reg = <0x620 0x10>; 82 reg = <0x620 0x10>;
88 interrupts = <0x1 0xb 0x0>; 83 interrupts = <1 11 0>;
89 interrupt-parent = <&mpc5200_pic>;
90 gpio-controller; 84 gpio-controller;
91 #gpio-cells = <2>; 85 #gpio-cells = <2>;
92 }; 86 };
93 87
94 gpt3: timer@630 { /* General Purpose Timer in GPIO mode */ 88 gpt3: timer@630 { // General Purpose Timer in GPIO mode
95 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 89 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
96 cell-index = <3>;
97 reg = <0x630 0x10>; 90 reg = <0x630 0x10>;
98 interrupts = <0x1 0xc 0x0>; 91 interrupts = <1 12 0>;
99 interrupt-parent = <&mpc5200_pic>;
100 gpio-controller; 92 gpio-controller;
101 #gpio-cells = <2>; 93 #gpio-cells = <2>;
102 }; 94 };
103 95
104 gpt4: timer@640 { /* General Purpose Timer in GPIO mode */ 96 gpt4: timer@640 { // General Purpose Timer in GPIO mode
105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 97 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
106 cell-index = <4>;
107 reg = <0x640 0x10>; 98 reg = <0x640 0x10>;
108 interrupts = <0x1 0xd 0x0>; 99 interrupts = <1 13 0>;
109 interrupt-parent = <&mpc5200_pic>;
110 gpio-controller; 100 gpio-controller;
111 #gpio-cells = <2>; 101 #gpio-cells = <2>;
112 }; 102 };
113 103
114 gpt5: timer@650 { /* General Purpose Timer in GPIO mode */ 104 gpt5: timer@650 { // General Purpose Timer in GPIO mode
115 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 105 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
116 cell-index = <5>;
117 reg = <0x650 0x10>; 106 reg = <0x650 0x10>;
118 interrupts = <0x1 0xe 0x0>; 107 interrupts = <1 14 0>;
119 interrupt-parent = <&mpc5200_pic>;
120 gpio-controller; 108 gpio-controller;
121 #gpio-cells = <2>; 109 #gpio-cells = <2>;
122 }; 110 };
123 111
124 gpt6: timer@660 { /* General Purpose Timer in GPIO mode */ 112 gpt6: timer@660 { // General Purpose Timer in GPIO mode
125 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 113 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
126 cell-index = <6>;
127 reg = <0x660 0x10>; 114 reg = <0x660 0x10>;
128 interrupts = <0x1 0xf 0x0>; 115 interrupts = <1 15 0>;
129 interrupt-parent = <&mpc5200_pic>;
130 gpio-controller; 116 gpio-controller;
131 #gpio-cells = <2>; 117 #gpio-cells = <2>;
132 }; 118 };
133 119
134 gpt7: timer@670 { /* General Purpose Timer in GPIO mode */ 120 gpt7: timer@670 { // General Purpose Timer in GPIO mode
135 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; 121 compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
136 cell-index = <7>;
137 reg = <0x670 0x10>; 122 reg = <0x670 0x10>;
138 interrupts = <0x1 0x10 0x0>; 123 interrupts = <1 16 0>;
139 interrupt-parent = <&mpc5200_pic>;
140 gpio-controller; 124 gpio-controller;
141 #gpio-cells = <2>; 125 #gpio-cells = <2>;
142 }; 126 };
@@ -144,40 +128,33 @@
144 rtc@800 { // Real time clock 128 rtc@800 { // Real time clock
145 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 129 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
146 reg = <0x800 0x100>; 130 reg = <0x800 0x100>;
147 interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>; 131 interrupts = <1 5 0 1 6 0>;
148 interrupt-parent = <&mpc5200_pic>;
149 }; 132 };
150 133
151 can@900 { 134 can@900 {
152 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 135 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
153 cell-index = <0>; 136 interrupts = <2 17 0>;
154 interrupts = <0x2 0x11 0x0>;
155 interrupt-parent = <&mpc5200_pic>;
156 reg = <0x900 0x80>; 137 reg = <0x900 0x80>;
157 }; 138 };
158 139
159 can@980 { 140 can@980 {
160 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 141 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
161 cell-index = <1>; 142 interrupts = <2 18 0>;
162 interrupts = <0x2 0x12 0x0>;
163 interrupt-parent = <&mpc5200_pic>;
164 reg = <0x980 0x80>; 143 reg = <0x980 0x80>;
165 }; 144 };
166 145
167 gpio_simple: gpio@b00 { 146 gpio_simple: gpio@b00 {
168 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 147 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
169 reg = <0xb00 0x40>; 148 reg = <0xb00 0x40>;
170 interrupts = <0x1 0x7 0x0>; 149 interrupts = <1 7 0>;
171 interrupt-parent = <&mpc5200_pic>;
172 gpio-controller; 150 gpio-controller;
173 #gpio-cells = <2>; 151 #gpio-cells = <2>;
174 }; 152 };
175 153
176 gpio_wkup: gpio-wkup@c00 { 154 gpio_wkup: gpio@c00 {
177 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 155 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
178 reg = <0xc00 0x40>; 156 reg = <0xc00 0x40>;
179 interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>; 157 interrupts = <1 8 0 0 3 0>;
180 interrupt-parent = <&mpc5200_pic>;
181 gpio-controller; 158 gpio-controller;
182 #gpio-cells = <2>; 159 #gpio-cells = <2>;
183 }; 160 };
@@ -185,26 +162,22 @@
185 spi@f00 { 162 spi@f00 {
186 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 163 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
187 reg = <0xf00 0x20>; 164 reg = <0xf00 0x20>;
188 interrupts = <0x2 0xd 0x0 0x2 0xe 0x0>; 165 interrupts = <2 13 0 2 14 0>;
189 interrupt-parent = <&mpc5200_pic>;
190 }; 166 };
191 167
192 usb@1000 { 168 usb@1000 {
193 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 169 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
194 reg = <0x1000 0xff>; 170 reg = <0x1000 0xff>;
195 interrupts = <0x2 0x6 0x0>; 171 interrupts = <2 6 0>;
196 interrupt-parent = <&mpc5200_pic>;
197 }; 172 };
198 173
199 dma-controller@1200 { 174 dma-controller@1200 {
200 device_type = "dma-controller";
201 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 175 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
202 reg = <0x1200 0x80>; 176 reg = <0x1200 0x80>;
203 interrupts = <0x3 0x0 0x0 0x3 0x1 0x0 0x3 0x2 0x0 0x3 0x3 0x0 177 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
204 0x3 0x4 0x0 0x3 0x5 0x0 0x3 0x6 0x0 0x3 0x7 0x0 178 3 4 0 3 5 0 3 6 0 3 7 0
205 0x3 0x8 0x0 0x3 0x9 0x0 0x3 0xa 0x0 0x3 0xb 0x0 179 3 8 0 3 9 0 3 10 0 3 11 0
206 0x3 0xc 0x0 0x3 0xd 0x0 0x3 0xe 0x0 0x3 0xf 0x0>; 180 3 12 0 3 13 0 3 14 0 3 15 0>;
207 interrupt-parent = <&mpc5200_pic>;
208 }; 181 };
209 182
210 xlb@1f00 { 183 xlb@1f00 {
@@ -213,24 +186,19 @@
213 }; 186 };
214 187
215 ac97@2000 { /* PSC1 in ac97 mode */ 188 ac97@2000 { /* PSC1 in ac97 mode */
216 device_type = "sound";
217 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; 189 compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
218 cell-index = <0>; 190 cell-index = <0>;
219 reg = <0x2000 0x100>; 191 reg = <0x2000 0x100>;
220 interrupts = <0x2 0x2 0x0>; 192 interrupts = <2 1 0>;
221 interrupt-parent = <&mpc5200_pic>;
222 }; 193 };
223 194
224 /* PSC2 port is used by CAN1/2 */ 195 /* PSC2 port is used by CAN1/2 */
225 196
226 serial@2400 { /* PSC3 in UART mode */ 197 serial@2400 { /* PSC3 in UART mode */
227 device_type = "serial";
228 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 198 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
229 port-number = <0>;
230 cell-index = <2>; 199 cell-index = <2>;
231 reg = <0x2400 0x100>; 200 reg = <0x2400 0x100>;
232 interrupts = <0x2 0x3 0x0>; 201 interrupts = <2 3 0>;
233 interrupt-parent = <&mpc5200_pic>;
234 }; 202 };
235 203
236 /* PSC4 is ??? */ 204 /* PSC4 is ??? */
@@ -238,55 +206,44 @@
238 /* PSC5 is ??? */ 206 /* PSC5 is ??? */
239 207
240 serial@2c00 { /* PSC6 in UART mode */ 208 serial@2c00 { /* PSC6 in UART mode */
241 device_type = "serial";
242 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; 209 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
243 port-number = <1>;
244 cell-index = <5>; 210 cell-index = <5>;
245 reg = <0x2c00 0x100>; 211 reg = <0x2c00 0x100>;
246 interrupts = <0x2 0x4 0x0>; 212 interrupts = <2 4 0>;
247 interrupt-parent = <&mpc5200_pic>;
248 }; 213 };
249 214
250 ethernet@3000 { 215 ethernet@3000 {
251 device_type = "network";
252 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 216 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
253 reg = <0x3000 0x400>; 217 reg = <0x3000 0x400>;
254 local-mac-address = [00 00 00 00 00 00]; 218 local-mac-address = [ 00 00 00 00 00 00 ];
255 interrupts = <0x2 0x5 0x0>; 219 interrupts = <2 5 0>;
256 interrupt-parent = <&mpc5200_pic>;
257 phy-handle = <&phy0>; 220 phy-handle = <&phy0>;
258 }; 221 };
259 222
260 mdio@3000 { 223 mdio@3000 {
261 #address-cells = <1>; 224 #address-cells = <1>;
262 #size-cells = <0>; 225 #size-cells = <0>;
263 compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; 226 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
264 reg = <0x3000 0x400>; /* fec range, since we need to setup fec interrupts */ 227 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
265 interrupts = <0x2 0x5 0x0>; /* these are for "mii command finished", not link changes & co. */ 228 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
266 interrupt-parent = <&mpc5200_pic>; 229
267 230 phy0: ethernet-phy@0 {
268 phy0:ethernet-phy@0 { 231 reg = <0>;
269 device_type = "ethernet-phy";
270 reg = <0x0>;
271 }; 232 };
272 }; 233 };
273 234
274 ata@3a00 { 235 ata@3a00 {
275 device_type = "ata";
276 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 236 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
277 reg = <0x3a00 0x100>; 237 reg = <0x3a00 0x100>;
278 interrupts = <0x2 0x7 0x0>; 238 interrupts = <2 7 0>;
279 interrupt-parent = <&mpc5200_pic>;
280 }; 239 };
281 240
282 i2c@3d00 { 241 i2c@3d00 {
283 #address-cells = <1>; 242 #address-cells = <1>;
284 #size-cells = <0>; 243 #size-cells = <0>;
285 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 244 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
286 cell-index = <0>;
287 reg = <0x3d00 0x40>; 245 reg = <0x3d00 0x40>;
288 interrupts = <0x2 0xf 0x0>; 246 interrupts = <2 15 0>;
289 interrupt-parent = <&mpc5200_pic>;
290 fsl5200-clocking; 247 fsl5200-clocking;
291 }; 248 };
292 249
@@ -294,10 +251,8 @@
294 #address-cells = <1>; 251 #address-cells = <1>;
295 #size-cells = <0>; 252 #size-cells = <0>;
296 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 253 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
297 cell-index = <1>;
298 reg = <0x3d40 0x40>; 254 reg = <0x3d40 0x40>;
299 interrupts = <0x2 0x10 0x0>; 255 interrupts = <2 16 0>;
300 interrupt-parent = <&mpc5200_pic>;
301 fsl5200-clocking; 256 fsl5200-clocking;
302 rtc@51 { 257 rtc@51 {
303 compatible = "nxp,pcf8563"; 258 compatible = "nxp,pcf8563";
@@ -307,7 +262,7 @@
307 }; 262 };
308 263
309 sram@8000 { 264 sram@8000 {
310 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; 265 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
311 reg = <0x8000 0x4000>; 266 reg = <0x8000 0x4000>;
312 }; 267 };
313 268
@@ -340,22 +295,21 @@
340 device_type = "pci"; 295 device_type = "pci";
341 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; 296 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
342 reg = <0xf0000d00 0x100>; 297 reg = <0xf0000d00 0x100>;
343 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 298 interrupt-map-mask = <0xf800 0 0 7>;
344 interrupt-map = <0xc000 0x0 0x0 0x1 &mpc5200_pic 0x0 0x0 0x3 /* 1st slot */ 299 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
345 0xc000 0x0 0x0 0x2 &mpc5200_pic 0x1 0x1 0x3 300 0xc000 0 0 2 &mpc5200_pic 1 1 3
346 0xc000 0x0 0x0 0x3 &mpc5200_pic 0x1 0x2 0x3 301 0xc000 0 0 3 &mpc5200_pic 1 2 3
347 0xc000 0x0 0x0 0x4 &mpc5200_pic 0x1 0x3 0x3 302 0xc000 0 0 4 &mpc5200_pic 1 3 3
348 303
349 0xc800 0x0 0x0 0x1 &mpc5200_pic 0x1 0x1 0x3 /* 2nd slot */ 304 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
350 0xc800 0x0 0x0 0x2 &mpc5200_pic 0x1 0x2 0x3 305 0xc800 0 0 2 &mpc5200_pic 1 2 3
351 0xc800 0x0 0x0 0x3 &mpc5200_pic 0x1 0x3 0x3 306 0xc800 0 0 3 &mpc5200_pic 1 3 3
352 0xc800 0x0 0x0 0x4 &mpc5200_pic 0x0 0x0 0x3>; 307 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
353 clock-frequency = <0>; // From boot loader 308 clock-frequency = <0>; // From boot loader
354 interrupts = <0x2 0x8 0x0 0x2 0x9 0x0 0x2 0xa 0x0>; 309 interrupts = <2 8 0 2 9 0 2 10 0>;
355 interrupt-parent = <&mpc5200_pic>;
356 bus-range = <0 0>; 310 bus-range = <0 0>;
357 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000 311 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
358 0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 312 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
359 0x01000000 0x0 0x00000000 0xb0000000 0x0 0x01000000>; 313 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
360 }; 314 };
361}; 315};
diff --git a/arch/powerpc/boot/dts/tqm5200.dts b/arch/powerpc/boot/dts/tqm5200.dts
index 906302e26a62..c9590b58b7b0 100644
--- a/arch/powerpc/boot/dts/tqm5200.dts
+++ b/arch/powerpc/boot/dts/tqm5200.dts
@@ -17,6 +17,7 @@
17 compatible = "tqc,tqm5200"; 17 compatible = "tqc,tqm5200";
18 #address-cells = <1>; 18 #address-cells = <1>;
19 #size-cells = <1>; 19 #size-cells = <1>;
20 interrupt-parent = <&mpc5200_pic>;
20 21
21 cpus { 22 cpus {
22 #address-cells = <1>; 23 #address-cells = <1>;
@@ -66,36 +67,33 @@
66 compatible = "fsl,mpc5200-gpt"; 67 compatible = "fsl,mpc5200-gpt";
67 reg = <0x600 0x10>; 68 reg = <0x600 0x10>;
68 interrupts = <1 9 0>; 69 interrupts = <1 9 0>;
69 interrupt-parent = <&mpc5200_pic>;
70 fsl,has-wdt; 70 fsl,has-wdt;
71 }; 71 };
72 72
73 can@900 { 73 can@900 {
74 compatible = "fsl,mpc5200-mscan"; 74 compatible = "fsl,mpc5200-mscan";
75 interrupts = <2 17 0>; 75 interrupts = <2 17 0>;
76 interrupt-parent = <&mpc5200_pic>;
77 reg = <0x900 0x80>; 76 reg = <0x900 0x80>;
78 }; 77 };
79 78
80 can@980 { 79 can@980 {
81 compatible = "fsl,mpc5200-mscan"; 80 compatible = "fsl,mpc5200-mscan";
82 interrupts = <2 18 0>; 81 interrupts = <2 18 0>;
83 interrupt-parent = <&mpc5200_pic>;
84 reg = <0x980 0x80>; 82 reg = <0x980 0x80>;
85 }; 83 };
86 84
87 gpio@b00 { 85 gpio_simple: gpio@b00 {
88 compatible = "fsl,mpc5200-gpio"; 86 compatible = "fsl,mpc5200-gpio";
89 reg = <0xb00 0x40>; 87 reg = <0xb00 0x40>;
90 interrupts = <1 7 0>; 88 interrupts = <1 7 0>;
91 interrupt-parent = <&mpc5200_pic>; 89 gpio-controller;
90 #gpio-cells = <2>;
92 }; 91 };
93 92
94 usb@1000 { 93 usb@1000 {
95 compatible = "fsl,mpc5200-ohci","ohci-be"; 94 compatible = "fsl,mpc5200-ohci","ohci-be";
96 reg = <0x1000 0xff>; 95 reg = <0x1000 0xff>;
97 interrupts = <2 6 0>; 96 interrupts = <2 6 0>;
98 interrupt-parent = <&mpc5200_pic>;
99 }; 97 };
100 98
101 dma-controller@1200 { 99 dma-controller@1200 {
@@ -105,7 +103,6 @@
105 3 4 0 3 5 0 3 6 0 3 7 0 103 3 4 0 3 5 0 3 6 0 3 7 0
106 3 8 0 3 9 0 3 10 0 3 11 0 104 3 8 0 3 9 0 3 10 0 3 11 0
107 3 12 0 3 13 0 3 14 0 3 15 0>; 105 3 12 0 3 13 0 3 14 0 3 15 0>;
108 interrupt-parent = <&mpc5200_pic>;
109 }; 106 };
110 107
111 xlb@1f00 { 108 xlb@1f00 {
@@ -114,39 +111,28 @@
114 }; 111 };
115 112
116 serial@2000 { // PSC1 113 serial@2000 { // PSC1
117 device_type = "serial";
118 compatible = "fsl,mpc5200-psc-uart"; 114 compatible = "fsl,mpc5200-psc-uart";
119 port-number = <0>; // Logical port assignment
120 reg = <0x2000 0x100>; 115 reg = <0x2000 0x100>;
121 interrupts = <2 1 0>; 116 interrupts = <2 1 0>;
122 interrupt-parent = <&mpc5200_pic>;
123 }; 117 };
124 118
125 serial@2200 { // PSC2 119 serial@2200 { // PSC2
126 device_type = "serial";
127 compatible = "fsl,mpc5200-psc-uart"; 120 compatible = "fsl,mpc5200-psc-uart";
128 port-number = <1>; // Logical port assignment
129 reg = <0x2200 0x100>; 121 reg = <0x2200 0x100>;
130 interrupts = <2 2 0>; 122 interrupts = <2 2 0>;
131 interrupt-parent = <&mpc5200_pic>;
132 }; 123 };
133 124
134 serial@2400 { // PSC3 125 serial@2400 { // PSC3
135 device_type = "serial";
136 compatible = "fsl,mpc5200-psc-uart"; 126 compatible = "fsl,mpc5200-psc-uart";
137 port-number = <2>; // Logical port assignment
138 reg = <0x2400 0x100>; 127 reg = <0x2400 0x100>;
139 interrupts = <2 3 0>; 128 interrupts = <2 3 0>;
140 interrupt-parent = <&mpc5200_pic>;
141 }; 129 };
142 130
143 ethernet@3000 { 131 ethernet@3000 {
144 device_type = "network";
145 compatible = "fsl,mpc5200-fec"; 132 compatible = "fsl,mpc5200-fec";
146 reg = <0x3000 0x400>; 133 reg = <0x3000 0x400>;
147 local-mac-address = [ 00 00 00 00 00 00 ]; 134 local-mac-address = [ 00 00 00 00 00 00 ];
148 interrupts = <2 5 0>; 135 interrupts = <2 5 0>;
149 interrupt-parent = <&mpc5200_pic>;
150 phy-handle = <&phy0>; 136 phy-handle = <&phy0>;
151 }; 137 };
152 138
@@ -156,10 +142,8 @@
156 compatible = "fsl,mpc5200-mdio"; 142 compatible = "fsl,mpc5200-mdio";
157 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 143 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
158 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 144 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
159 interrupt-parent = <&mpc5200_pic>;
160 145
161 phy0: ethernet-phy@0 { 146 phy0: ethernet-phy@0 {
162 device_type = "ethernet-phy";
163 reg = <0>; 147 reg = <0>;
164 }; 148 };
165 }; 149 };
@@ -168,7 +152,6 @@
168 compatible = "fsl,mpc5200-ata"; 152 compatible = "fsl,mpc5200-ata";
169 reg = <0x3a00 0x100>; 153 reg = <0x3a00 0x100>;
170 interrupts = <2 7 0>; 154 interrupts = <2 7 0>;
171 interrupt-parent = <&mpc5200_pic>;
172 }; 155 };
173 156
174 i2c@3d40 { 157 i2c@3d40 {
@@ -177,7 +160,6 @@
177 compatible = "fsl,mpc5200-i2c","fsl-i2c"; 160 compatible = "fsl,mpc5200-i2c","fsl-i2c";
178 reg = <0x3d40 0x40>; 161 reg = <0x3d40 0x40>;
179 interrupts = <2 16 0>; 162 interrupts = <2 16 0>;
180 interrupt-parent = <&mpc5200_pic>;
181 fsl5200-clocking; 163 fsl5200-clocking;
182 164
183 rtc@68 { 165 rtc@68 {
@@ -192,9 +174,8 @@
192 }; 174 };
193 }; 175 };
194 176
195 lpb { 177 localbus {
196 model = "fsl,lpb"; 178 compatible = "fsl,mpc5200-lpb","simple-bus";
197 compatible = "fsl,lpb";
198 #address-cells = <2>; 179 #address-cells = <2>;
199 #size-cells = <1>; 180 #size-cells = <1>;
200 ranges = <0 0 0xfc000000 0x02000000>; 181 ranges = <0 0 0xfc000000 0x02000000>;
@@ -223,7 +204,6 @@
223 0xc000 0 0 4 &mpc5200_pic 0 0 3>; 204 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
224 clock-frequency = <0>; // From boot loader 205 clock-frequency = <0>; // From boot loader
225 interrupts = <2 8 0 2 9 0 2 10 0>; 206 interrupts = <2 8 0 2 9 0 2 10 0>;
226 interrupt-parent = <&mpc5200_pic>;
227 bus-range = <0 0>; 207 bus-range = <0 0>;
228 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 208 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
229 0x02000000 0 0x90000000 0x90000000 0 0x10000000 209 0x02000000 0 0x90000000 0x90000000 0 0x10000000
diff --git a/arch/powerpc/boot/dts/tqm8540.dts b/arch/powerpc/boot/dts/tqm8540.dts
index a693f01c21aa..39e55ab82b89 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -84,6 +84,11 @@
84 interrupt-parent = <&mpic>; 84 interrupt-parent = <&mpic>;
85 dfsrr; 85 dfsrr;
86 86
87 dtt@50 {
88 compatible = "national,lm75";
89 reg = <0x50>;
90 };
91
87 rtc@68 { 92 rtc@68 {
88 compatible = "dallas,ds1337"; 93 compatible = "dallas,ds1337";
89 reg = <0x68>; 94 reg = <0x68>;
diff --git a/arch/powerpc/boot/dts/tqm8541.dts b/arch/powerpc/boot/dts/tqm8541.dts
index 9e3f5f0dde20..58ae8bc58817 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -83,6 +83,11 @@
83 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
84 dfsrr; 84 dfsrr;
85 85
86 dtt@50 {
87 compatible = "national,lm75";
88 reg = <0x50>;
89 };
90
86 rtc@68 { 91 rtc@68 {
87 compatible = "dallas,ds1337"; 92 compatible = "dallas,ds1337";
88 reg = <0x68>; 93 reg = <0x68>;
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index 15086eb65c50..bff380a25aa6 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -85,6 +85,11 @@
85 interrupt-parent = <&mpic>; 85 interrupt-parent = <&mpic>;
86 dfsrr; 86 dfsrr;
87 87
88 dtt@50 {
89 compatible = "national,lm75";
90 reg = <0x50>;
91 };
92
88 rtc@68 { 93 rtc@68 {
89 compatible = "dallas,ds1337"; 94 compatible = "dallas,ds1337";
90 reg = <0x68>; 95 reg = <0x68>;
@@ -365,14 +370,14 @@
365 can0@2,0 { 370 can0@2,0 {
366 compatible = "intel,82527"; // Bosch CC770 371 compatible = "intel,82527"; // Bosch CC770
367 reg = <2 0x0 0x100>; 372 reg = <2 0x0 0x100>;
368 interrupts = <4 0>; 373 interrupts = <4 1>;
369 interrupt-parent = <&mpic>; 374 interrupt-parent = <&mpic>;
370 }; 375 };
371 376
372 can1@2,100 { 377 can1@2,100 {
373 compatible = "intel,82527"; // Bosch CC770 378 compatible = "intel,82527"; // Bosch CC770
374 reg = <2 0x100 0x100>; 379 reg = <2 0x100 0x100>;
375 interrupts = <4 0>; 380 interrupts = <4 1>;
376 interrupt-parent = <&mpic>; 381 interrupt-parent = <&mpic>;
377 }; 382 };
378 383
diff --git a/arch/powerpc/boot/dts/tqm8548.dts b/arch/powerpc/boot/dts/tqm8548.dts
index b7b65f5e79b6..112ac90f2ea7 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -85,6 +85,11 @@
85 interrupt-parent = <&mpic>; 85 interrupt-parent = <&mpic>;
86 dfsrr; 86 dfsrr;
87 87
88 dtt@50 {
89 compatible = "national,lm75";
90 reg = <0x50>;
91 };
92
88 rtc@68 { 93 rtc@68 {
89 compatible = "dallas,ds1337"; 94 compatible = "dallas,ds1337";
90 reg = <0x68>; 95 reg = <0x68>;
@@ -365,14 +370,14 @@
365 can0@2,0 { 370 can0@2,0 {
366 compatible = "intel,82527"; // Bosch CC770 371 compatible = "intel,82527"; // Bosch CC770
367 reg = <2 0x0 0x100>; 372 reg = <2 0x0 0x100>;
368 interrupts = <4 0>; 373 interrupts = <4 1>;
369 interrupt-parent = <&mpic>; 374 interrupt-parent = <&mpic>;
370 }; 375 };
371 376
372 can1@2,100 { 377 can1@2,100 {
373 compatible = "intel,82527"; // Bosch CC770 378 compatible = "intel,82527"; // Bosch CC770
374 reg = <2 0x100 0x100>; 379 reg = <2 0x100 0x100>;
375 interrupts = <4 0>; 380 interrupts = <4 1>;
376 interrupt-parent = <&mpic>; 381 interrupt-parent = <&mpic>;
377 }; 382 };
378 383
diff --git a/arch/powerpc/boot/dts/tqm8555.dts b/arch/powerpc/boot/dts/tqm8555.dts
index cf92b4e7945e..4b7da890c03b 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -83,6 +83,11 @@
83 interrupt-parent = <&mpic>; 83 interrupt-parent = <&mpic>;
84 dfsrr; 84 dfsrr;
85 85
86 dtt@50 {
87 compatible = "national,lm75";
88 reg = <0x50>;
89 };
90
86 rtc@68 { 91 rtc@68 {
87 compatible = "dallas,ds1337"; 92 compatible = "dallas,ds1337";
88 reg = <0x68>; 93 reg = <0x68>;
diff --git a/arch/powerpc/boot/dts/tqm8560.dts b/arch/powerpc/boot/dts/tqm8560.dts
index 9e1ab2d2f669..3fa552f31edb 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -85,6 +85,11 @@
85 interrupt-parent = <&mpic>; 85 interrupt-parent = <&mpic>;
86 dfsrr; 86 dfsrr;
87 87
88 dtt@50 {
89 compatible = "national,lm75";
90 reg = <0x50>;
91 };
92
88 rtc@68 { 93 rtc@68 {
89 compatible = "dallas,ds1337"; 94 compatible = "dallas,ds1337";
90 reg = <0x68>; 95 reg = <0x68>;
@@ -335,14 +340,14 @@
335 can0@2,0 { 340 can0@2,0 {
336 compatible = "intel,82527"; // Bosch CC770 341 compatible = "intel,82527"; // Bosch CC770
337 reg = <2 0x0 0x100>; 342 reg = <2 0x0 0x100>;
338 interrupts = <4 0>; 343 interrupts = <4 1>;
339 interrupt-parent = <&mpic>; 344 interrupt-parent = <&mpic>;
340 }; 345 };
341 346
342 can1@2,100 { 347 can1@2,100 {
343 compatible = "intel,82527"; // Bosch CC770 348 compatible = "intel,82527"; // Bosch CC770
344 reg = <2 0x100 0x100>; 349 reg = <2 0x100 0x100>;
345 interrupts = <4 0>; 350 interrupts = <4 1>;
346 interrupt-parent = <&mpic>; 351 interrupt-parent = <&mpic>;
347 }; 352 };
348 }; 353 };
diff --git a/arch/powerpc/boot/serial.c b/arch/powerpc/boot/serial.c
index 8b3607cb53fb..f2156f07571f 100644
--- a/arch/powerpc/boot/serial.c
+++ b/arch/powerpc/boot/serial.c
@@ -117,7 +117,8 @@ int serial_console_init(void)
117 if (devp == NULL) 117 if (devp == NULL)
118 goto err_out; 118 goto err_out;
119 119
120 if (dt_is_compatible(devp, "ns16550")) 120 if (dt_is_compatible(devp, "ns16550") ||
121 dt_is_compatible(devp, "pnpPNP,501"))
121 rc = ns16550_console_init(devp, &serial_cd); 122 rc = ns16550_console_init(devp, &serial_cd);
122 else if (dt_is_compatible(devp, "marvell,mv64360-mpsc")) 123 else if (dt_is_compatible(devp, "marvell,mv64360-mpsc"))
123 rc = mpsc_console_init(devp, &serial_cd); 124 rc = mpsc_console_init(devp, &serial_cd);
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index 965c237c122d..6170bbf339a3 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -186,6 +186,9 @@ cuboot*)
186 *-mpc85*|*-tqm85*|*-sbc85*) 186 *-mpc85*|*-tqm85*|*-sbc85*)
187 platformo=$object/cuboot-85xx.o 187 platformo=$object/cuboot-85xx.o
188 ;; 188 ;;
189 *-amigaone)
190 link_address='0x800000'
191 ;;
189 esac 192 esac
190 ;; 193 ;;
191ps3) 194ps3)
diff --git a/arch/powerpc/configs/86xx/gef_sbc310_defconfig b/arch/powerpc/configs/86xx/gef_sbc310_defconfig
new file mode 100644
index 000000000000..bd236b3d915a
--- /dev/null
+++ b/arch/powerpc/configs/86xx/gef_sbc310_defconfig
@@ -0,0 +1,1613 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29-rc3
4# Wed Jan 28 23:05:34 2009
5#
6# CONFIG_PPC64 is not set
7
8#
9# Processor support
10#
11CONFIG_6xx=y
12# CONFIG_PPC_85xx is not set
13# CONFIG_PPC_8xx is not set
14# CONFIG_40x is not set
15# CONFIG_44x is not set
16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y
18# CONFIG_PHYS_64BIT is not set
19CONFIG_ALTIVEC=y
20CONFIG_PPC_STD_MMU=y
21CONFIG_PPC_STD_MMU_32=y
22# CONFIG_PPC_MM_SLICES is not set
23CONFIG_SMP=y
24CONFIG_NR_CPUS=2
25CONFIG_PPC32=y
26CONFIG_WORD_SIZE=32
27# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
28CONFIG_MMU=y
29CONFIG_GENERIC_CMOS_UPDATE=y
30CONFIG_GENERIC_TIME=y
31CONFIG_GENERIC_TIME_VSYSCALL=y
32CONFIG_GENERIC_CLOCKEVENTS=y
33CONFIG_GENERIC_HARDIRQS=y
34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
35CONFIG_IRQ_PER_CPU=y
36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
38CONFIG_LOCKDEP_SUPPORT=y
39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
40CONFIG_GENERIC_LOCKBREAK=y
41CONFIG_ARCH_HAS_ILOG2_U32=y
42CONFIG_GENERIC_HWEIGHT=y
43CONFIG_GENERIC_CALIBRATE_DELAY=y
44CONFIG_GENERIC_FIND_NEXT_BIT=y
45CONFIG_GENERIC_GPIO=y
46# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
47CONFIG_PPC=y
48CONFIG_EARLY_PRINTK=y
49CONFIG_GENERIC_NVRAM=y
50CONFIG_SCHED_OMIT_FRAME_POINTER=y
51CONFIG_ARCH_MAY_HAVE_PC_FDC=y
52CONFIG_PPC_OF=y
53CONFIG_OF=y
54CONFIG_PPC_UDBG_16550=y
55CONFIG_GENERIC_TBSYNC=y
56CONFIG_AUDIT_ARCH=y
57CONFIG_GENERIC_BUG=y
58CONFIG_DEFAULT_UIMAGE=y
59# CONFIG_PPC_DCR_NATIVE is not set
60# CONFIG_PPC_DCR_MMIO is not set
61CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
62
63#
64# General setup
65#
66CONFIG_EXPERIMENTAL=y
67CONFIG_LOCK_KERNEL=y
68CONFIG_INIT_ENV_ARG_LIMIT=32
69CONFIG_LOCALVERSION=""
70CONFIG_LOCALVERSION_AUTO=y
71CONFIG_SWAP=y
72CONFIG_SYSVIPC=y
73CONFIG_SYSVIPC_SYSCTL=y
74CONFIG_POSIX_MQUEUE=y
75CONFIG_BSD_PROCESS_ACCT=y
76CONFIG_BSD_PROCESS_ACCT_V3=y
77# CONFIG_TASKSTATS is not set
78# CONFIG_AUDIT is not set
79
80#
81# RCU Subsystem
82#
83CONFIG_CLASSIC_RCU=y
84# CONFIG_TREE_RCU is not set
85# CONFIG_PREEMPT_RCU is not set
86# CONFIG_TREE_RCU_TRACE is not set
87# CONFIG_PREEMPT_RCU_TRACE is not set
88CONFIG_IKCONFIG=y
89CONFIG_IKCONFIG_PROC=y
90CONFIG_LOG_BUF_SHIFT=14
91# CONFIG_GROUP_SCHED is not set
92# CONFIG_CGROUPS is not set
93CONFIG_SYSFS_DEPRECATED=y
94CONFIG_SYSFS_DEPRECATED_V2=y
95CONFIG_RELAY=y
96# CONFIG_NAMESPACES is not set
97CONFIG_BLK_DEV_INITRD=y
98CONFIG_INITRAMFS_SOURCE=""
99# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
100CONFIG_SYSCTL=y
101CONFIG_EMBEDDED=y
102CONFIG_SYSCTL_SYSCALL=y
103CONFIG_KALLSYMS=y
104# CONFIG_KALLSYMS_EXTRA_PASS is not set
105CONFIG_HOTPLUG=y
106CONFIG_PRINTK=y
107CONFIG_BUG=y
108CONFIG_ELF_CORE=y
109CONFIG_COMPAT_BRK=y
110CONFIG_BASE_FULL=y
111CONFIG_FUTEX=y
112CONFIG_ANON_INODES=y
113CONFIG_EPOLL=y
114CONFIG_SIGNALFD=y
115CONFIG_TIMERFD=y
116CONFIG_EVENTFD=y
117CONFIG_SHMEM=y
118CONFIG_AIO=y
119CONFIG_VM_EVENT_COUNTERS=y
120CONFIG_PCI_QUIRKS=y
121CONFIG_SLAB=y
122# CONFIG_SLUB is not set
123# CONFIG_SLOB is not set
124# CONFIG_PROFILING is not set
125CONFIG_HAVE_OPROFILE=y
126# CONFIG_KPROBES is not set
127CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
128CONFIG_HAVE_IOREMAP_PROT=y
129CONFIG_HAVE_KPROBES=y
130CONFIG_HAVE_KRETPROBES=y
131CONFIG_HAVE_ARCH_TRACEHOOK=y
132CONFIG_USE_GENERIC_SMP_HELPERS=y
133# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
134CONFIG_SLABINFO=y
135CONFIG_RT_MUTEXES=y
136CONFIG_BASE_SMALL=0
137CONFIG_MODULES=y
138# CONFIG_MODULE_FORCE_LOAD is not set
139CONFIG_MODULE_UNLOAD=y
140# CONFIG_MODULE_FORCE_UNLOAD is not set
141# CONFIG_MODVERSIONS is not set
142# CONFIG_MODULE_SRCVERSION_ALL is not set
143CONFIG_STOP_MACHINE=y
144CONFIG_BLOCK=y
145# CONFIG_LBD is not set
146# CONFIG_BLK_DEV_IO_TRACE is not set
147# CONFIG_BLK_DEV_BSG is not set
148# CONFIG_BLK_DEV_INTEGRITY is not set
149
150#
151# IO Schedulers
152#
153CONFIG_IOSCHED_NOOP=y
154CONFIG_IOSCHED_AS=y
155CONFIG_IOSCHED_DEADLINE=y
156CONFIG_IOSCHED_CFQ=y
157# CONFIG_DEFAULT_AS is not set
158# CONFIG_DEFAULT_DEADLINE is not set
159CONFIG_DEFAULT_CFQ=y
160# CONFIG_DEFAULT_NOOP is not set
161CONFIG_DEFAULT_IOSCHED="cfq"
162# CONFIG_FREEZER is not set
163CONFIG_PPC_MSI_BITMAP=y
164
165#
166# Platform support
167#
168CONFIG_PPC_MULTIPLATFORM=y
169CONFIG_CLASSIC32=y
170# CONFIG_PPC_CHRP is not set
171# CONFIG_MPC5121_ADS is not set
172# CONFIG_MPC5121_GENERIC is not set
173# CONFIG_PPC_MPC52xx is not set
174# CONFIG_PPC_PMAC is not set
175# CONFIG_PPC_CELL is not set
176# CONFIG_PPC_CELL_NATIVE is not set
177# CONFIG_PPC_82xx is not set
178# CONFIG_PQ2ADS is not set
179# CONFIG_PPC_83xx is not set
180CONFIG_PPC_86xx=y
181# CONFIG_MPC8641_HPCN is not set
182# CONFIG_SBC8641D is not set
183# CONFIG_MPC8610_HPCD is not set
184CONFIG_GEF_SBC310=y
185# CONFIG_GEF_SBC610 is not set
186CONFIG_MPC8641=y
187# CONFIG_IPIC is not set
188CONFIG_MPIC=y
189# CONFIG_MPIC_WEIRD is not set
190# CONFIG_PPC_I8259 is not set
191# CONFIG_PPC_RTAS is not set
192# CONFIG_MMIO_NVRAM is not set
193# CONFIG_PPC_MPC106 is not set
194# CONFIG_PPC_970_NAP is not set
195# CONFIG_PPC_INDIRECT_IO is not set
196# CONFIG_GENERIC_IOMAP is not set
197# CONFIG_CPU_FREQ is not set
198# CONFIG_TAU is not set
199# CONFIG_QUICC_ENGINE is not set
200# CONFIG_FSL_ULI1575 is not set
201# CONFIG_MPC8xxx_GPIO is not set
202# CONFIG_SIMPLE_GPIO is not set
203
204#
205# Kernel options
206#
207# CONFIG_HIGHMEM is not set
208CONFIG_TICK_ONESHOT=y
209# CONFIG_NO_HZ is not set
210CONFIG_HIGH_RES_TIMERS=y
211CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
212# CONFIG_HZ_100 is not set
213# CONFIG_HZ_250 is not set
214# CONFIG_HZ_300 is not set
215CONFIG_HZ_1000=y
216CONFIG_HZ=1000
217CONFIG_SCHED_HRTICK=y
218# CONFIG_PREEMPT_NONE is not set
219# CONFIG_PREEMPT_VOLUNTARY is not set
220CONFIG_PREEMPT=y
221CONFIG_BINFMT_ELF=y
222# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
223# CONFIG_HAVE_AOUT is not set
224CONFIG_BINFMT_MISC=y
225# CONFIG_IOMMU_HELPER is not set
226CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
227CONFIG_ARCH_HAS_WALK_MEMORY=y
228CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
229# CONFIG_KEXEC is not set
230# CONFIG_CRASH_DUMP is not set
231CONFIG_IRQ_ALL_CPUS=y
232CONFIG_ARCH_FLATMEM_ENABLE=y
233CONFIG_ARCH_POPULATES_NODE_MAP=y
234CONFIG_SELECT_MEMORY_MODEL=y
235CONFIG_FLATMEM_MANUAL=y
236# CONFIG_DISCONTIGMEM_MANUAL is not set
237# CONFIG_SPARSEMEM_MANUAL is not set
238CONFIG_FLATMEM=y
239CONFIG_FLAT_NODE_MEM_MAP=y
240CONFIG_PAGEFLAGS_EXTENDED=y
241CONFIG_SPLIT_PTLOCK_CPUS=4
242CONFIG_MIGRATION=y
243# CONFIG_PHYS_ADDR_T_64BIT is not set
244CONFIG_ZONE_DMA_FLAG=1
245CONFIG_BOUNCE=y
246CONFIG_VIRT_TO_BUS=y
247CONFIG_UNEVICTABLE_LRU=y
248CONFIG_PPC_4K_PAGES=y
249# CONFIG_PPC_16K_PAGES is not set
250# CONFIG_PPC_64K_PAGES is not set
251CONFIG_FORCE_MAX_ZONEORDER=11
252# CONFIG_PROC_DEVICETREE is not set
253# CONFIG_CMDLINE_BOOL is not set
254CONFIG_EXTRA_TARGETS=""
255# CONFIG_PM is not set
256CONFIG_SECCOMP=y
257CONFIG_ISA_DMA_API=y
258
259#
260# Bus options
261#
262CONFIG_ZONE_DMA=y
263CONFIG_GENERIC_ISA_DMA=y
264CONFIG_PPC_INDIRECT_PCI=y
265CONFIG_FSL_SOC=y
266CONFIG_FSL_PCI=y
267CONFIG_PPC_PCI_CHOICE=y
268CONFIG_PCI=y
269CONFIG_PCI_DOMAINS=y
270CONFIG_PCI_SYSCALL=y
271CONFIG_PCIEPORTBUS=y
272CONFIG_PCIEAER=y
273# CONFIG_PCIEASPM is not set
274CONFIG_ARCH_SUPPORTS_MSI=y
275CONFIG_PCI_MSI=y
276# CONFIG_PCI_LEGACY is not set
277# CONFIG_PCI_STUB is not set
278# CONFIG_PCCARD is not set
279# CONFIG_HOTPLUG_PCI is not set
280# CONFIG_HAS_RAPIDIO is not set
281
282#
283# Advanced setup
284#
285# CONFIG_ADVANCED_OPTIONS is not set
286
287#
288# Default settings for advanced configuration options are used
289#
290CONFIG_LOWMEM_SIZE=0x30000000
291CONFIG_LOWMEM_CAM_NUM=3
292CONFIG_PAGE_OFFSET=0xc0000000
293CONFIG_KERNEL_START=0xc0000000
294CONFIG_PHYSICAL_START=0x00000000
295CONFIG_TASK_SIZE=0xc0000000
296CONFIG_NET=y
297
298#
299# Networking options
300#
301CONFIG_COMPAT_NET_DEV_OPS=y
302CONFIG_PACKET=y
303CONFIG_PACKET_MMAP=y
304CONFIG_UNIX=y
305CONFIG_XFRM=y
306CONFIG_XFRM_USER=m
307# CONFIG_XFRM_SUB_POLICY is not set
308# CONFIG_XFRM_MIGRATE is not set
309# CONFIG_XFRM_STATISTICS is not set
310CONFIG_XFRM_IPCOMP=m
311CONFIG_NET_KEY=m
312# CONFIG_NET_KEY_MIGRATE is not set
313CONFIG_INET=y
314CONFIG_IP_MULTICAST=y
315CONFIG_IP_ADVANCED_ROUTER=y
316CONFIG_ASK_IP_FIB_HASH=y
317# CONFIG_IP_FIB_TRIE is not set
318CONFIG_IP_FIB_HASH=y
319CONFIG_IP_MULTIPLE_TABLES=y
320CONFIG_IP_ROUTE_MULTIPATH=y
321CONFIG_IP_ROUTE_VERBOSE=y
322CONFIG_IP_PNP=y
323CONFIG_IP_PNP_DHCP=y
324CONFIG_IP_PNP_BOOTP=y
325CONFIG_IP_PNP_RARP=y
326CONFIG_NET_IPIP=m
327CONFIG_NET_IPGRE=m
328CONFIG_NET_IPGRE_BROADCAST=y
329CONFIG_IP_MROUTE=y
330CONFIG_IP_PIMSM_V1=y
331CONFIG_IP_PIMSM_V2=y
332# CONFIG_ARPD is not set
333CONFIG_SYN_COOKIES=y
334CONFIG_INET_AH=m
335CONFIG_INET_ESP=m
336CONFIG_INET_IPCOMP=m
337CONFIG_INET_XFRM_TUNNEL=m
338CONFIG_INET_TUNNEL=m
339CONFIG_INET_XFRM_MODE_TRANSPORT=y
340CONFIG_INET_XFRM_MODE_TUNNEL=y
341# CONFIG_INET_XFRM_MODE_BEET is not set
342CONFIG_INET_LRO=y
343CONFIG_INET_DIAG=y
344CONFIG_INET_TCP_DIAG=y
345# CONFIG_TCP_CONG_ADVANCED is not set
346CONFIG_TCP_CONG_CUBIC=y
347CONFIG_DEFAULT_TCP_CONG="cubic"
348# CONFIG_TCP_MD5SIG is not set
349CONFIG_IPV6=m
350# CONFIG_IPV6_PRIVACY is not set
351# CONFIG_IPV6_ROUTER_PREF is not set
352# CONFIG_IPV6_OPTIMISTIC_DAD is not set
353CONFIG_INET6_AH=m
354CONFIG_INET6_ESP=m
355CONFIG_INET6_IPCOMP=m
356# CONFIG_IPV6_MIP6 is not set
357CONFIG_INET6_XFRM_TUNNEL=m
358CONFIG_INET6_TUNNEL=m
359CONFIG_INET6_XFRM_MODE_TRANSPORT=m
360CONFIG_INET6_XFRM_MODE_TUNNEL=m
361CONFIG_INET6_XFRM_MODE_BEET=m
362# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
363CONFIG_IPV6_SIT=m
364CONFIG_IPV6_NDISC_NODETYPE=y
365CONFIG_IPV6_TUNNEL=m
366# CONFIG_IPV6_MULTIPLE_TABLES is not set
367# CONFIG_IPV6_MROUTE is not set
368# CONFIG_NETWORK_SECMARK is not set
369# CONFIG_NETFILTER is not set
370# CONFIG_IP_DCCP is not set
371# CONFIG_IP_SCTP is not set
372# CONFIG_TIPC is not set
373# CONFIG_ATM is not set
374# CONFIG_BRIDGE is not set
375# CONFIG_NET_DSA is not set
376# CONFIG_VLAN_8021Q is not set
377# CONFIG_DECNET is not set
378# CONFIG_LLC2 is not set
379# CONFIG_IPX is not set
380# CONFIG_ATALK is not set
381# CONFIG_X25 is not set
382# CONFIG_LAPB is not set
383# CONFIG_ECONET is not set
384# CONFIG_WAN_ROUTER is not set
385# CONFIG_NET_SCHED is not set
386# CONFIG_DCB is not set
387
388#
389# Network testing
390#
391CONFIG_NET_PKTGEN=m
392# CONFIG_HAMRADIO is not set
393# CONFIG_CAN is not set
394# CONFIG_IRDA is not set
395# CONFIG_BT is not set
396# CONFIG_AF_RXRPC is not set
397# CONFIG_PHONET is not set
398CONFIG_FIB_RULES=y
399# CONFIG_WIRELESS is not set
400# CONFIG_WIMAX is not set
401# CONFIG_RFKILL is not set
402# CONFIG_NET_9P is not set
403
404#
405# Device Drivers
406#
407
408#
409# Generic Driver Options
410#
411CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
412CONFIG_STANDALONE=y
413CONFIG_PREVENT_FIRMWARE_BUILD=y
414# CONFIG_FW_LOADER is not set
415# CONFIG_SYS_HYPERVISOR is not set
416# CONFIG_CONNECTOR is not set
417CONFIG_MTD=y
418# CONFIG_MTD_DEBUG is not set
419CONFIG_MTD_CONCAT=y
420CONFIG_MTD_PARTITIONS=y
421# CONFIG_MTD_TESTS is not set
422# CONFIG_MTD_REDBOOT_PARTS is not set
423# CONFIG_MTD_CMDLINE_PARTS is not set
424CONFIG_MTD_OF_PARTS=y
425# CONFIG_MTD_AR7_PARTS is not set
426
427#
428# User Modules And Translation Layers
429#
430CONFIG_MTD_CHAR=y
431CONFIG_MTD_BLKDEVS=y
432CONFIG_MTD_BLOCK=y
433# CONFIG_FTL is not set
434# CONFIG_NFTL is not set
435# CONFIG_INFTL is not set
436# CONFIG_RFD_FTL is not set
437# CONFIG_SSFDC is not set
438# CONFIG_MTD_OOPS is not set
439
440#
441# RAM/ROM/Flash chip drivers
442#
443CONFIG_MTD_CFI=y
444CONFIG_MTD_JEDECPROBE=y
445CONFIG_MTD_GEN_PROBE=y
446# CONFIG_MTD_CFI_ADV_OPTIONS is not set
447CONFIG_MTD_MAP_BANK_WIDTH_1=y
448CONFIG_MTD_MAP_BANK_WIDTH_2=y
449CONFIG_MTD_MAP_BANK_WIDTH_4=y
450# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
451# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
452# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
453CONFIG_MTD_CFI_I1=y
454CONFIG_MTD_CFI_I2=y
455# CONFIG_MTD_CFI_I4 is not set
456# CONFIG_MTD_CFI_I8 is not set
457CONFIG_MTD_CFI_INTELEXT=y
458CONFIG_MTD_CFI_AMDSTD=y
459# CONFIG_MTD_CFI_STAA is not set
460CONFIG_MTD_CFI_UTIL=y
461# CONFIG_MTD_RAM is not set
462# CONFIG_MTD_ROM is not set
463# CONFIG_MTD_ABSENT is not set
464
465#
466# Mapping drivers for chip access
467#
468# CONFIG_MTD_COMPLEX_MAPPINGS is not set
469# CONFIG_MTD_PHYSMAP is not set
470CONFIG_MTD_PHYSMAP_OF=y
471# CONFIG_MTD_INTEL_VR_NOR is not set
472# CONFIG_MTD_PLATRAM is not set
473
474#
475# Self-contained MTD device drivers
476#
477# CONFIG_MTD_PMC551 is not set
478# CONFIG_MTD_SLRAM is not set
479# CONFIG_MTD_PHRAM is not set
480# CONFIG_MTD_MTDRAM is not set
481# CONFIG_MTD_BLOCK2MTD is not set
482
483#
484# Disk-On-Chip Device Drivers
485#
486# CONFIG_MTD_DOC2000 is not set
487# CONFIG_MTD_DOC2001 is not set
488# CONFIG_MTD_DOC2001PLUS is not set
489# CONFIG_MTD_NAND is not set
490# CONFIG_MTD_ONENAND is not set
491
492#
493# LPDDR flash memory drivers
494#
495# CONFIG_MTD_LPDDR is not set
496# CONFIG_MTD_QINFO_PROBE is not set
497
498#
499# UBI - Unsorted block images
500#
501# CONFIG_MTD_UBI is not set
502CONFIG_OF_DEVICE=y
503CONFIG_OF_GPIO=y
504CONFIG_OF_I2C=y
505# CONFIG_PARPORT is not set
506CONFIG_BLK_DEV=y
507# CONFIG_BLK_DEV_FD is not set
508# CONFIG_BLK_CPQ_DA is not set
509# CONFIG_BLK_CPQ_CISS_DA is not set
510# CONFIG_BLK_DEV_DAC960 is not set
511# CONFIG_BLK_DEV_UMEM is not set
512# CONFIG_BLK_DEV_COW_COMMON is not set
513CONFIG_BLK_DEV_LOOP=m
514CONFIG_BLK_DEV_CRYPTOLOOP=m
515CONFIG_BLK_DEV_NBD=m
516# CONFIG_BLK_DEV_SX8 is not set
517# CONFIG_BLK_DEV_UB is not set
518CONFIG_BLK_DEV_RAM=y
519CONFIG_BLK_DEV_RAM_COUNT=16
520CONFIG_BLK_DEV_RAM_SIZE=131072
521# CONFIG_BLK_DEV_XIP is not set
522# CONFIG_CDROM_PKTCDVD is not set
523# CONFIG_ATA_OVER_ETH is not set
524# CONFIG_BLK_DEV_HD is not set
525CONFIG_MISC_DEVICES=y
526# CONFIG_PHANTOM is not set
527# CONFIG_SGI_IOC4 is not set
528# CONFIG_TIFM_CORE is not set
529# CONFIG_ICS932S401 is not set
530# CONFIG_ENCLOSURE_SERVICES is not set
531# CONFIG_HP_ILO is not set
532# CONFIG_C2PORT is not set
533
534#
535# EEPROM support
536#
537# CONFIG_EEPROM_AT24 is not set
538# CONFIG_EEPROM_LEGACY is not set
539# CONFIG_EEPROM_93CX6 is not set
540CONFIG_HAVE_IDE=y
541# CONFIG_IDE is not set
542
543#
544# SCSI device support
545#
546# CONFIG_RAID_ATTRS is not set
547CONFIG_SCSI=y
548CONFIG_SCSI_DMA=y
549# CONFIG_SCSI_TGT is not set
550# CONFIG_SCSI_NETLINK is not set
551CONFIG_SCSI_PROC_FS=y
552
553#
554# SCSI support type (disk, tape, CD-ROM)
555#
556CONFIG_BLK_DEV_SD=y
557CONFIG_CHR_DEV_ST=y
558# CONFIG_CHR_DEV_OSST is not set
559CONFIG_BLK_DEV_SR=y
560# CONFIG_BLK_DEV_SR_VENDOR is not set
561# CONFIG_CHR_DEV_SG is not set
562# CONFIG_CHR_DEV_SCH is not set
563
564#
565# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
566#
567# CONFIG_SCSI_MULTI_LUN is not set
568# CONFIG_SCSI_CONSTANTS is not set
569# CONFIG_SCSI_LOGGING is not set
570# CONFIG_SCSI_SCAN_ASYNC is not set
571CONFIG_SCSI_WAIT_SCAN=m
572
573#
574# SCSI Transports
575#
576# CONFIG_SCSI_SPI_ATTRS is not set
577# CONFIG_SCSI_FC_ATTRS is not set
578# CONFIG_SCSI_ISCSI_ATTRS is not set
579# CONFIG_SCSI_SAS_LIBSAS is not set
580# CONFIG_SCSI_SRP_ATTRS is not set
581CONFIG_SCSI_LOWLEVEL=y
582# CONFIG_ISCSI_TCP is not set
583# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
584# CONFIG_SCSI_3W_9XXX is not set
585# CONFIG_SCSI_ACARD is not set
586# CONFIG_SCSI_AACRAID is not set
587# CONFIG_SCSI_AIC7XXX is not set
588# CONFIG_SCSI_AIC7XXX_OLD is not set
589# CONFIG_SCSI_AIC79XX is not set
590# CONFIG_SCSI_AIC94XX is not set
591# CONFIG_SCSI_DPT_I2O is not set
592# CONFIG_SCSI_ADVANSYS is not set
593# CONFIG_SCSI_ARCMSR is not set
594# CONFIG_MEGARAID_NEWGEN is not set
595# CONFIG_MEGARAID_LEGACY is not set
596# CONFIG_MEGARAID_SAS is not set
597# CONFIG_SCSI_HPTIOP is not set
598# CONFIG_SCSI_BUSLOGIC is not set
599# CONFIG_LIBFC is not set
600# CONFIG_FCOE is not set
601# CONFIG_SCSI_DMX3191D is not set
602# CONFIG_SCSI_EATA is not set
603# CONFIG_SCSI_FUTURE_DOMAIN is not set
604# CONFIG_SCSI_GDTH is not set
605# CONFIG_SCSI_IPS is not set
606# CONFIG_SCSI_INITIO is not set
607# CONFIG_SCSI_INIA100 is not set
608# CONFIG_SCSI_MVSAS is not set
609# CONFIG_SCSI_STEX is not set
610# CONFIG_SCSI_SYM53C8XX_2 is not set
611# CONFIG_SCSI_IPR is not set
612# CONFIG_SCSI_QLOGIC_1280 is not set
613# CONFIG_SCSI_QLA_FC is not set
614# CONFIG_SCSI_QLA_ISCSI is not set
615# CONFIG_SCSI_LPFC is not set
616# CONFIG_SCSI_DC395x is not set
617# CONFIG_SCSI_DC390T is not set
618# CONFIG_SCSI_NSP32 is not set
619# CONFIG_SCSI_DEBUG is not set
620# CONFIG_SCSI_SRP is not set
621# CONFIG_SCSI_DH is not set
622CONFIG_ATA=y
623# CONFIG_ATA_NONSTANDARD is not set
624CONFIG_SATA_PMP=y
625# CONFIG_SATA_AHCI is not set
626CONFIG_SATA_SIL24=y
627# CONFIG_SATA_FSL is not set
628# CONFIG_ATA_SFF is not set
629# CONFIG_MD is not set
630# CONFIG_FUSION is not set
631
632#
633# IEEE 1394 (FireWire) support
634#
635
636#
637# Enable only one of the two stacks, unless you know what you are doing
638#
639# CONFIG_FIREWIRE is not set
640# CONFIG_IEEE1394 is not set
641# CONFIG_I2O is not set
642# CONFIG_MACINTOSH_DRIVERS is not set
643CONFIG_NETDEVICES=y
644CONFIG_DUMMY=m
645CONFIG_BONDING=m
646# CONFIG_MACVLAN is not set
647# CONFIG_EQUALIZER is not set
648CONFIG_TUN=m
649# CONFIG_VETH is not set
650# CONFIG_ARCNET is not set
651CONFIG_PHYLIB=y
652
653#
654# MII PHY device drivers
655#
656# CONFIG_MARVELL_PHY is not set
657# CONFIG_DAVICOM_PHY is not set
658# CONFIG_QSEMI_PHY is not set
659# CONFIG_LXT_PHY is not set
660# CONFIG_CICADA_PHY is not set
661# CONFIG_VITESSE_PHY is not set
662# CONFIG_SMSC_PHY is not set
663# CONFIG_BROADCOM_PHY is not set
664# CONFIG_ICPLUS_PHY is not set
665# CONFIG_REALTEK_PHY is not set
666# CONFIG_NATIONAL_PHY is not set
667# CONFIG_STE10XP is not set
668# CONFIG_LSI_ET1011C_PHY is not set
669# CONFIG_FIXED_PHY is not set
670# CONFIG_MDIO_BITBANG is not set
671CONFIG_NET_ETHERNET=y
672CONFIG_MII=y
673# CONFIG_HAPPYMEAL is not set
674# CONFIG_SUNGEM is not set
675# CONFIG_CASSINI is not set
676# CONFIG_NET_VENDOR_3COM is not set
677# CONFIG_NET_TULIP is not set
678# CONFIG_HP100 is not set
679# CONFIG_IBM_NEW_EMAC_ZMII is not set
680# CONFIG_IBM_NEW_EMAC_RGMII is not set
681# CONFIG_IBM_NEW_EMAC_TAH is not set
682# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
683# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
684# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
685# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
686# CONFIG_NET_PCI is not set
687# CONFIG_B44 is not set
688# CONFIG_ATL2 is not set
689CONFIG_NETDEV_1000=y
690# CONFIG_ACENIC is not set
691# CONFIG_DL2K is not set
692# CONFIG_E1000 is not set
693# CONFIG_E1000E is not set
694# CONFIG_IP1000 is not set
695# CONFIG_IGB is not set
696# CONFIG_NS83820 is not set
697# CONFIG_HAMACHI is not set
698# CONFIG_YELLOWFIN is not set
699# CONFIG_R8169 is not set
700# CONFIG_SIS190 is not set
701# CONFIG_SKGE is not set
702# CONFIG_SKY2 is not set
703# CONFIG_VIA_VELOCITY is not set
704# CONFIG_TIGON3 is not set
705# CONFIG_BNX2 is not set
706CONFIG_GIANFAR=y
707# CONFIG_MV643XX_ETH is not set
708# CONFIG_QLA3XXX is not set
709# CONFIG_ATL1 is not set
710# CONFIG_ATL1E is not set
711# CONFIG_JME is not set
712# CONFIG_NETDEV_10000 is not set
713# CONFIG_TR is not set
714
715#
716# Wireless LAN
717#
718# CONFIG_WLAN_PRE80211 is not set
719# CONFIG_WLAN_80211 is not set
720# CONFIG_IWLWIFI_LEDS is not set
721
722#
723# Enable WiMAX (Networking options) to see the WiMAX drivers
724#
725
726#
727# USB Network Adapters
728#
729# CONFIG_USB_CATC is not set
730# CONFIG_USB_KAWETH is not set
731# CONFIG_USB_PEGASUS is not set
732# CONFIG_USB_RTL8150 is not set
733# CONFIG_USB_USBNET is not set
734# CONFIG_WAN is not set
735# CONFIG_FDDI is not set
736# CONFIG_HIPPI is not set
737CONFIG_PPP=m
738CONFIG_PPP_MULTILINK=y
739CONFIG_PPP_FILTER=y
740CONFIG_PPP_ASYNC=m
741CONFIG_PPP_SYNC_TTY=m
742CONFIG_PPP_DEFLATE=m
743CONFIG_PPP_BSDCOMP=m
744# CONFIG_PPP_MPPE is not set
745CONFIG_PPPOE=m
746# CONFIG_PPPOL2TP is not set
747CONFIG_SLIP=m
748CONFIG_SLIP_COMPRESSED=y
749CONFIG_SLHC=m
750CONFIG_SLIP_SMART=y
751CONFIG_SLIP_MODE_SLIP6=y
752# CONFIG_NET_FC is not set
753CONFIG_NETCONSOLE=y
754# CONFIG_NETCONSOLE_DYNAMIC is not set
755CONFIG_NETPOLL=y
756CONFIG_NETPOLL_TRAP=y
757CONFIG_NET_POLL_CONTROLLER=y
758# CONFIG_ISDN is not set
759# CONFIG_PHONE is not set
760
761#
762# Input device support
763#
764CONFIG_INPUT=y
765# CONFIG_INPUT_FF_MEMLESS is not set
766# CONFIG_INPUT_POLLDEV is not set
767
768#
769# Userland interfaces
770#
771CONFIG_INPUT_MOUSEDEV=y
772CONFIG_INPUT_MOUSEDEV_PSAUX=y
773CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
774CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
775# CONFIG_INPUT_JOYDEV is not set
776# CONFIG_INPUT_EVDEV is not set
777# CONFIG_INPUT_EVBUG is not set
778
779#
780# Input Device Drivers
781#
782# CONFIG_INPUT_KEYBOARD is not set
783# CONFIG_INPUT_MOUSE is not set
784# CONFIG_INPUT_JOYSTICK is not set
785# CONFIG_INPUT_TABLET is not set
786# CONFIG_INPUT_TOUCHSCREEN is not set
787# CONFIG_INPUT_MISC is not set
788
789#
790# Hardware I/O ports
791#
792# CONFIG_SERIO is not set
793# CONFIG_GAMEPORT is not set
794
795#
796# Character devices
797#
798CONFIG_VT=y
799CONFIG_CONSOLE_TRANSLATIONS=y
800CONFIG_VT_CONSOLE=y
801CONFIG_HW_CONSOLE=y
802# CONFIG_VT_HW_CONSOLE_BINDING is not set
803CONFIG_DEVKMEM=y
804# CONFIG_SERIAL_NONSTANDARD is not set
805# CONFIG_NOZOMI is not set
806
807#
808# Serial drivers
809#
810CONFIG_SERIAL_8250=y
811CONFIG_SERIAL_8250_CONSOLE=y
812# CONFIG_SERIAL_8250_PCI is not set
813CONFIG_SERIAL_8250_NR_UARTS=2
814CONFIG_SERIAL_8250_RUNTIME_UARTS=2
815# CONFIG_SERIAL_8250_EXTENDED is not set
816
817#
818# Non-8250 serial port support
819#
820# CONFIG_SERIAL_UARTLITE is not set
821CONFIG_SERIAL_CORE=y
822CONFIG_SERIAL_CORE_CONSOLE=y
823# CONFIG_SERIAL_JSM is not set
824# CONFIG_SERIAL_OF_PLATFORM is not set
825CONFIG_UNIX98_PTYS=y
826# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
827# CONFIG_LEGACY_PTYS is not set
828# CONFIG_HVC_UDBG is not set
829# CONFIG_IPMI_HANDLER is not set
830CONFIG_HW_RANDOM=y
831CONFIG_NVRAM=y
832# CONFIG_R3964 is not set
833# CONFIG_APPLICOM is not set
834# CONFIG_RAW_DRIVER is not set
835# CONFIG_TCG_TPM is not set
836CONFIG_DEVPORT=y
837CONFIG_I2C=y
838CONFIG_I2C_BOARDINFO=y
839CONFIG_I2C_CHARDEV=y
840CONFIG_I2C_HELPER_AUTO=y
841
842#
843# I2C Hardware Bus support
844#
845
846#
847# PC SMBus host controller drivers
848#
849# CONFIG_I2C_ALI1535 is not set
850# CONFIG_I2C_ALI1563 is not set
851# CONFIG_I2C_ALI15X3 is not set
852# CONFIG_I2C_AMD756 is not set
853# CONFIG_I2C_AMD8111 is not set
854# CONFIG_I2C_I801 is not set
855# CONFIG_I2C_ISCH is not set
856# CONFIG_I2C_PIIX4 is not set
857# CONFIG_I2C_NFORCE2 is not set
858# CONFIG_I2C_SIS5595 is not set
859# CONFIG_I2C_SIS630 is not set
860# CONFIG_I2C_SIS96X is not set
861# CONFIG_I2C_VIA is not set
862# CONFIG_I2C_VIAPRO is not set
863
864#
865# I2C system bus drivers (mostly embedded / system-on-chip)
866#
867# CONFIG_I2C_GPIO is not set
868CONFIG_I2C_MPC=y
869# CONFIG_I2C_OCORES is not set
870# CONFIG_I2C_SIMTEC is not set
871
872#
873# External I2C/SMBus adapter drivers
874#
875# CONFIG_I2C_PARPORT_LIGHT is not set
876# CONFIG_I2C_TAOS_EVM is not set
877# CONFIG_I2C_TINY_USB is not set
878
879#
880# Graphics adapter I2C/DDC channel drivers
881#
882# CONFIG_I2C_VOODOO3 is not set
883
884#
885# Other I2C/SMBus bus drivers
886#
887# CONFIG_I2C_PCA_PLATFORM is not set
888# CONFIG_I2C_STUB is not set
889
890#
891# Miscellaneous I2C Chip support
892#
893CONFIG_DS1682=y
894# CONFIG_SENSORS_PCF8574 is not set
895# CONFIG_PCF8575 is not set
896# CONFIG_SENSORS_PCA9539 is not set
897# CONFIG_SENSORS_PCF8591 is not set
898# CONFIG_SENSORS_MAX6875 is not set
899# CONFIG_SENSORS_TSL2550 is not set
900# CONFIG_I2C_DEBUG_CORE is not set
901# CONFIG_I2C_DEBUG_ALGO is not set
902# CONFIG_I2C_DEBUG_BUS is not set
903# CONFIG_I2C_DEBUG_CHIP is not set
904# CONFIG_SPI is not set
905CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
906CONFIG_ARCH_REQUIRE_GPIOLIB=y
907CONFIG_GPIOLIB=y
908CONFIG_GPIO_SYSFS=y
909
910#
911# Memory mapped GPIO expanders:
912#
913# CONFIG_GPIO_XILINX is not set
914
915#
916# I2C GPIO expanders:
917#
918# CONFIG_GPIO_MAX732X is not set
919# CONFIG_GPIO_PCA953X is not set
920# CONFIG_GPIO_PCF857X is not set
921
922#
923# PCI GPIO expanders:
924#
925# CONFIG_GPIO_BT8XX is not set
926
927#
928# SPI GPIO expanders:
929#
930# CONFIG_W1 is not set
931# CONFIG_POWER_SUPPLY is not set
932CONFIG_HWMON=y
933# CONFIG_HWMON_VID is not set
934# CONFIG_SENSORS_AD7414 is not set
935# CONFIG_SENSORS_AD7418 is not set
936# CONFIG_SENSORS_ADM1021 is not set
937# CONFIG_SENSORS_ADM1025 is not set
938# CONFIG_SENSORS_ADM1026 is not set
939# CONFIG_SENSORS_ADM1029 is not set
940# CONFIG_SENSORS_ADM1031 is not set
941# CONFIG_SENSORS_ADM9240 is not set
942# CONFIG_SENSORS_ADT7462 is not set
943# CONFIG_SENSORS_ADT7470 is not set
944# CONFIG_SENSORS_ADT7473 is not set
945# CONFIG_SENSORS_ADT7475 is not set
946# CONFIG_SENSORS_ATXP1 is not set
947# CONFIG_SENSORS_DS1621 is not set
948# CONFIG_SENSORS_I5K_AMB is not set
949# CONFIG_SENSORS_F71805F is not set
950# CONFIG_SENSORS_F71882FG is not set
951# CONFIG_SENSORS_F75375S is not set
952# CONFIG_SENSORS_GL518SM is not set
953# CONFIG_SENSORS_GL520SM is not set
954# CONFIG_SENSORS_IT87 is not set
955# CONFIG_SENSORS_LM63 is not set
956# CONFIG_SENSORS_LM75 is not set
957# CONFIG_SENSORS_LM77 is not set
958# CONFIG_SENSORS_LM78 is not set
959# CONFIG_SENSORS_LM80 is not set
960# CONFIG_SENSORS_LM83 is not set
961# CONFIG_SENSORS_LM85 is not set
962# CONFIG_SENSORS_LM87 is not set
963CONFIG_SENSORS_LM90=y
964CONFIG_SENSORS_LM92=y
965# CONFIG_SENSORS_LM93 is not set
966# CONFIG_SENSORS_LTC4245 is not set
967# CONFIG_SENSORS_MAX1619 is not set
968# CONFIG_SENSORS_MAX6650 is not set
969# CONFIG_SENSORS_PC87360 is not set
970# CONFIG_SENSORS_PC87427 is not set
971# CONFIG_SENSORS_SIS5595 is not set
972# CONFIG_SENSORS_DME1737 is not set
973# CONFIG_SENSORS_SMSC47M1 is not set
974# CONFIG_SENSORS_SMSC47M192 is not set
975# CONFIG_SENSORS_SMSC47B397 is not set
976# CONFIG_SENSORS_ADS7828 is not set
977# CONFIG_SENSORS_THMC50 is not set
978# CONFIG_SENSORS_VIA686A is not set
979# CONFIG_SENSORS_VT1211 is not set
980# CONFIG_SENSORS_VT8231 is not set
981# CONFIG_SENSORS_W83781D is not set
982# CONFIG_SENSORS_W83791D is not set
983# CONFIG_SENSORS_W83792D is not set
984# CONFIG_SENSORS_W83793 is not set
985# CONFIG_SENSORS_W83L785TS is not set
986# CONFIG_SENSORS_W83L786NG is not set
987# CONFIG_SENSORS_W83627HF is not set
988# CONFIG_SENSORS_W83627EHF is not set
989# CONFIG_HWMON_DEBUG_CHIP is not set
990# CONFIG_THERMAL is not set
991# CONFIG_THERMAL_HWMON is not set
992CONFIG_WATCHDOG=y
993# CONFIG_WATCHDOG_NOWAYOUT is not set
994
995#
996# Watchdog Device Drivers
997#
998# CONFIG_SOFT_WATCHDOG is not set
999# CONFIG_ALIM7101_WDT is not set
1000CONFIG_GEF_WDT=y
1001# CONFIG_8xxx_WDT is not set
1002
1003#
1004# PCI-based Watchdog Cards
1005#
1006# CONFIG_PCIPCWATCHDOG is not set
1007# CONFIG_WDTPCI is not set
1008
1009#
1010# USB-based Watchdog Cards
1011#
1012# CONFIG_USBPCWATCHDOG is not set
1013CONFIG_SSB_POSSIBLE=y
1014
1015#
1016# Sonics Silicon Backplane
1017#
1018# CONFIG_SSB is not set
1019
1020#
1021# Multifunction device drivers
1022#
1023# CONFIG_MFD_CORE is not set
1024# CONFIG_MFD_SM501 is not set
1025# CONFIG_HTC_PASIC3 is not set
1026# CONFIG_TPS65010 is not set
1027# CONFIG_TWL4030_CORE is not set
1028# CONFIG_MFD_TMIO is not set
1029# CONFIG_PMIC_DA903X is not set
1030# CONFIG_MFD_WM8400 is not set
1031# CONFIG_MFD_WM8350_I2C is not set
1032# CONFIG_MFD_PCF50633 is not set
1033# CONFIG_REGULATOR is not set
1034
1035#
1036# Multimedia devices
1037#
1038
1039#
1040# Multimedia core support
1041#
1042# CONFIG_VIDEO_DEV is not set
1043# CONFIG_DVB_CORE is not set
1044# CONFIG_VIDEO_MEDIA is not set
1045
1046#
1047# Multimedia drivers
1048#
1049CONFIG_DAB=y
1050# CONFIG_USB_DABUSB is not set
1051
1052#
1053# Graphics support
1054#
1055# CONFIG_AGP is not set
1056# CONFIG_DRM is not set
1057# CONFIG_VGASTATE is not set
1058CONFIG_VIDEO_OUTPUT_CONTROL=m
1059# CONFIG_FB is not set
1060# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1061
1062#
1063# Display device support
1064#
1065# CONFIG_DISPLAY_SUPPORT is not set
1066
1067#
1068# Console display driver support
1069#
1070CONFIG_VGA_CONSOLE=y
1071# CONFIG_VGACON_SOFT_SCROLLBACK is not set
1072CONFIG_DUMMY_CONSOLE=y
1073# CONFIG_SOUND is not set
1074CONFIG_HID_SUPPORT=y
1075CONFIG_HID=y
1076# CONFIG_HID_DEBUG is not set
1077# CONFIG_HIDRAW is not set
1078
1079#
1080# USB Input Devices
1081#
1082CONFIG_USB_HID=y
1083# CONFIG_HID_PID is not set
1084# CONFIG_USB_HIDDEV is not set
1085
1086#
1087# Special HID drivers
1088#
1089CONFIG_HID_COMPAT=y
1090CONFIG_HID_A4TECH=y
1091CONFIG_HID_APPLE=y
1092CONFIG_HID_BELKIN=y
1093CONFIG_HID_CHERRY=y
1094CONFIG_HID_CHICONY=y
1095CONFIG_HID_CYPRESS=y
1096CONFIG_HID_EZKEY=y
1097CONFIG_HID_GYRATION=y
1098CONFIG_HID_LOGITECH=y
1099# CONFIG_LOGITECH_FF is not set
1100# CONFIG_LOGIRUMBLEPAD2_FF is not set
1101CONFIG_HID_MICROSOFT=y
1102CONFIG_HID_MONTEREY=y
1103# CONFIG_HID_NTRIG is not set
1104CONFIG_HID_PANTHERLORD=y
1105# CONFIG_PANTHERLORD_FF is not set
1106CONFIG_HID_PETALYNX=y
1107CONFIG_HID_SAMSUNG=y
1108CONFIG_HID_SONY=y
1109CONFIG_HID_SUNPLUS=y
1110# CONFIG_GREENASIA_FF is not set
1111# CONFIG_HID_TOPSEED is not set
1112# CONFIG_THRUSTMASTER_FF is not set
1113# CONFIG_ZEROPLUS_FF is not set
1114CONFIG_USB_SUPPORT=y
1115CONFIG_USB_ARCH_HAS_HCD=y
1116CONFIG_USB_ARCH_HAS_OHCI=y
1117CONFIG_USB_ARCH_HAS_EHCI=y
1118CONFIG_USB=y
1119# CONFIG_USB_DEBUG is not set
1120# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1121
1122#
1123# Miscellaneous USB options
1124#
1125# CONFIG_USB_DEVICEFS is not set
1126# CONFIG_USB_DEVICE_CLASS is not set
1127# CONFIG_USB_DYNAMIC_MINORS is not set
1128# CONFIG_USB_OTG is not set
1129# CONFIG_USB_OTG_WHITELIST is not set
1130# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1131# CONFIG_USB_MON is not set
1132# CONFIG_USB_WUSB is not set
1133# CONFIG_USB_WUSB_CBAF is not set
1134
1135#
1136# USB Host Controller Drivers
1137#
1138# CONFIG_USB_C67X00_HCD is not set
1139CONFIG_USB_EHCI_HCD=y
1140# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
1141# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1142# CONFIG_USB_EHCI_FSL is not set
1143# CONFIG_USB_EHCI_HCD_PPC_OF is not set
1144# CONFIG_USB_OXU210HP_HCD is not set
1145# CONFIG_USB_ISP116X_HCD is not set
1146# CONFIG_USB_ISP1760_HCD is not set
1147CONFIG_USB_OHCI_HCD=y
1148# CONFIG_USB_OHCI_HCD_PPC_OF is not set
1149# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1150# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1151CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1152# CONFIG_USB_UHCI_HCD is not set
1153# CONFIG_USB_SL811_HCD is not set
1154# CONFIG_USB_R8A66597_HCD is not set
1155# CONFIG_USB_WHCI_HCD is not set
1156# CONFIG_USB_HWA_HCD is not set
1157
1158#
1159# USB Device Class drivers
1160#
1161# CONFIG_USB_ACM is not set
1162# CONFIG_USB_PRINTER is not set
1163# CONFIG_USB_WDM is not set
1164# CONFIG_USB_TMC is not set
1165
1166#
1167# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
1168#
1169
1170#
1171# see USB_STORAGE Help for more information
1172#
1173CONFIG_USB_STORAGE=y
1174# CONFIG_USB_STORAGE_DEBUG is not set
1175# CONFIG_USB_STORAGE_DATAFAB is not set
1176# CONFIG_USB_STORAGE_FREECOM is not set
1177# CONFIG_USB_STORAGE_ISD200 is not set
1178# CONFIG_USB_STORAGE_USBAT is not set
1179# CONFIG_USB_STORAGE_SDDR09 is not set
1180# CONFIG_USB_STORAGE_SDDR55 is not set
1181# CONFIG_USB_STORAGE_JUMPSHOT is not set
1182# CONFIG_USB_STORAGE_ALAUDA is not set
1183# CONFIG_USB_STORAGE_ONETOUCH is not set
1184# CONFIG_USB_STORAGE_KARMA is not set
1185# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1186# CONFIG_USB_LIBUSUAL is not set
1187
1188#
1189# USB Imaging devices
1190#
1191# CONFIG_USB_MDC800 is not set
1192# CONFIG_USB_MICROTEK is not set
1193
1194#
1195# USB port drivers
1196#
1197# CONFIG_USB_SERIAL is not set
1198
1199#
1200# USB Miscellaneous drivers
1201#
1202# CONFIG_USB_EMI62 is not set
1203# CONFIG_USB_EMI26 is not set
1204# CONFIG_USB_ADUTUX is not set
1205# CONFIG_USB_SEVSEG is not set
1206# CONFIG_USB_RIO500 is not set
1207# CONFIG_USB_LEGOTOWER is not set
1208# CONFIG_USB_LCD is not set
1209# CONFIG_USB_BERRY_CHARGE is not set
1210# CONFIG_USB_LED is not set
1211# CONFIG_USB_CYPRESS_CY7C63 is not set
1212# CONFIG_USB_CYTHERM is not set
1213# CONFIG_USB_PHIDGET is not set
1214# CONFIG_USB_IDMOUSE is not set
1215# CONFIG_USB_FTDI_ELAN is not set
1216# CONFIG_USB_APPLEDISPLAY is not set
1217# CONFIG_USB_SISUSBVGA is not set
1218# CONFIG_USB_LD is not set
1219# CONFIG_USB_TRANCEVIBRATOR is not set
1220# CONFIG_USB_IOWARRIOR is not set
1221# CONFIG_USB_ISIGHTFW is not set
1222# CONFIG_USB_VST is not set
1223# CONFIG_USB_GADGET is not set
1224
1225#
1226# OTG and related infrastructure
1227#
1228# CONFIG_USB_GPIO_VBUS is not set
1229# CONFIG_UWB is not set
1230# CONFIG_MMC is not set
1231# CONFIG_MEMSTICK is not set
1232# CONFIG_NEW_LEDS is not set
1233# CONFIG_ACCESSIBILITY is not set
1234# CONFIG_INFINIBAND is not set
1235# CONFIG_EDAC is not set
1236CONFIG_RTC_LIB=y
1237CONFIG_RTC_CLASS=y
1238CONFIG_RTC_HCTOSYS=y
1239CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1240# CONFIG_RTC_DEBUG is not set
1241
1242#
1243# RTC interfaces
1244#
1245CONFIG_RTC_INTF_SYSFS=y
1246# CONFIG_RTC_INTF_PROC is not set
1247CONFIG_RTC_INTF_DEV=y
1248# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1249# CONFIG_RTC_DRV_TEST is not set
1250
1251#
1252# I2C RTC drivers
1253#
1254# CONFIG_RTC_DRV_DS1307 is not set
1255# CONFIG_RTC_DRV_DS1374 is not set
1256# CONFIG_RTC_DRV_DS1672 is not set
1257# CONFIG_RTC_DRV_MAX6900 is not set
1258# CONFIG_RTC_DRV_RS5C372 is not set
1259# CONFIG_RTC_DRV_ISL1208 is not set
1260# CONFIG_RTC_DRV_X1205 is not set
1261# CONFIG_RTC_DRV_PCF8563 is not set
1262# CONFIG_RTC_DRV_PCF8583 is not set
1263# CONFIG_RTC_DRV_M41T80 is not set
1264# CONFIG_RTC_DRV_S35390A is not set
1265# CONFIG_RTC_DRV_FM3130 is not set
1266CONFIG_RTC_DRV_RX8581=y
1267
1268#
1269# SPI RTC drivers
1270#
1271
1272#
1273# Platform RTC drivers
1274#
1275# CONFIG_RTC_DRV_CMOS is not set
1276# CONFIG_RTC_DRV_DS1286 is not set
1277# CONFIG_RTC_DRV_DS1511 is not set
1278# CONFIG_RTC_DRV_DS1553 is not set
1279# CONFIG_RTC_DRV_DS1742 is not set
1280# CONFIG_RTC_DRV_STK17TA8 is not set
1281# CONFIG_RTC_DRV_M48T86 is not set
1282# CONFIG_RTC_DRV_M48T35 is not set
1283# CONFIG_RTC_DRV_M48T59 is not set
1284# CONFIG_RTC_DRV_BQ4802 is not set
1285# CONFIG_RTC_DRV_V3020 is not set
1286
1287#
1288# on-CPU RTC drivers
1289#
1290# CONFIG_RTC_DRV_PPC is not set
1291# CONFIG_DMADEVICES is not set
1292# CONFIG_UIO is not set
1293# CONFIG_STAGING is not set
1294
1295#
1296# File systems
1297#
1298CONFIG_EXT2_FS=y
1299CONFIG_EXT2_FS_XATTR=y
1300CONFIG_EXT2_FS_POSIX_ACL=y
1301# CONFIG_EXT2_FS_SECURITY is not set
1302# CONFIG_EXT2_FS_XIP is not set
1303CONFIG_EXT3_FS=y
1304CONFIG_EXT3_FS_XATTR=y
1305CONFIG_EXT3_FS_POSIX_ACL=y
1306# CONFIG_EXT3_FS_SECURITY is not set
1307# CONFIG_EXT4_FS is not set
1308CONFIG_JBD=y
1309CONFIG_FS_MBCACHE=y
1310# CONFIG_REISERFS_FS is not set
1311# CONFIG_JFS_FS is not set
1312CONFIG_FS_POSIX_ACL=y
1313CONFIG_FILE_LOCKING=y
1314# CONFIG_XFS_FS is not set
1315# CONFIG_OCFS2_FS is not set
1316# CONFIG_BTRFS_FS is not set
1317CONFIG_DNOTIFY=y
1318CONFIG_INOTIFY=y
1319CONFIG_INOTIFY_USER=y
1320# CONFIG_QUOTA is not set
1321# CONFIG_AUTOFS_FS is not set
1322# CONFIG_AUTOFS4_FS is not set
1323# CONFIG_FUSE_FS is not set
1324
1325#
1326# CD-ROM/DVD Filesystems
1327#
1328CONFIG_ISO9660_FS=y
1329CONFIG_JOLIET=y
1330CONFIG_ZISOFS=y
1331CONFIG_UDF_FS=y
1332CONFIG_UDF_NLS=y
1333
1334#
1335# DOS/FAT/NT Filesystems
1336#
1337CONFIG_FAT_FS=y
1338CONFIG_MSDOS_FS=y
1339CONFIG_VFAT_FS=y
1340CONFIG_FAT_DEFAULT_CODEPAGE=850
1341CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1342# CONFIG_NTFS_FS is not set
1343
1344#
1345# Pseudo filesystems
1346#
1347CONFIG_PROC_FS=y
1348CONFIG_PROC_KCORE=y
1349CONFIG_PROC_SYSCTL=y
1350CONFIG_PROC_PAGE_MONITOR=y
1351CONFIG_SYSFS=y
1352CONFIG_TMPFS=y
1353# CONFIG_TMPFS_POSIX_ACL is not set
1354# CONFIG_HUGETLB_PAGE is not set
1355# CONFIG_CONFIGFS_FS is not set
1356CONFIG_MISC_FILESYSTEMS=y
1357# CONFIG_ADFS_FS is not set
1358# CONFIG_AFFS_FS is not set
1359# CONFIG_HFS_FS is not set
1360# CONFIG_HFSPLUS_FS is not set
1361# CONFIG_BEFS_FS is not set
1362# CONFIG_BFS_FS is not set
1363# CONFIG_EFS_FS is not set
1364CONFIG_JFFS2_FS=y
1365CONFIG_JFFS2_FS_DEBUG=0
1366CONFIG_JFFS2_FS_WRITEBUFFER=y
1367# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1368# CONFIG_JFFS2_SUMMARY is not set
1369# CONFIG_JFFS2_FS_XATTR is not set
1370# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1371CONFIG_JFFS2_ZLIB=y
1372# CONFIG_JFFS2_LZO is not set
1373CONFIG_JFFS2_RTIME=y
1374# CONFIG_JFFS2_RUBIN is not set
1375# CONFIG_CRAMFS is not set
1376# CONFIG_SQUASHFS is not set
1377# CONFIG_VXFS_FS is not set
1378# CONFIG_MINIX_FS is not set
1379# CONFIG_OMFS_FS is not set
1380# CONFIG_HPFS_FS is not set
1381# CONFIG_QNX4FS_FS is not set
1382# CONFIG_ROMFS_FS is not set
1383# CONFIG_SYSV_FS is not set
1384# CONFIG_UFS_FS is not set
1385CONFIG_NETWORK_FILESYSTEMS=y
1386CONFIG_NFS_FS=y
1387CONFIG_NFS_V3=y
1388# CONFIG_NFS_V3_ACL is not set
1389CONFIG_NFS_V4=y
1390CONFIG_ROOT_NFS=y
1391# CONFIG_NFSD is not set
1392CONFIG_LOCKD=y
1393CONFIG_LOCKD_V4=y
1394CONFIG_NFS_COMMON=y
1395CONFIG_SUNRPC=y
1396CONFIG_SUNRPC_GSS=y
1397# CONFIG_SUNRPC_REGISTER_V4 is not set
1398CONFIG_RPCSEC_GSS_KRB5=y
1399# CONFIG_RPCSEC_GSS_SPKM3 is not set
1400# CONFIG_SMB_FS is not set
1401CONFIG_CIFS=m
1402# CONFIG_CIFS_STATS is not set
1403# CONFIG_CIFS_WEAK_PW_HASH is not set
1404CONFIG_CIFS_XATTR=y
1405CONFIG_CIFS_POSIX=y
1406# CONFIG_CIFS_DEBUG2 is not set
1407# CONFIG_CIFS_EXPERIMENTAL is not set
1408# CONFIG_NCP_FS is not set
1409# CONFIG_CODA_FS is not set
1410# CONFIG_AFS_FS is not set
1411
1412#
1413# Partition Types
1414#
1415# CONFIG_PARTITION_ADVANCED is not set
1416CONFIG_MSDOS_PARTITION=y
1417CONFIG_NLS=y
1418CONFIG_NLS_DEFAULT="iso8859-1"
1419CONFIG_NLS_CODEPAGE_437=m
1420CONFIG_NLS_CODEPAGE_737=m
1421CONFIG_NLS_CODEPAGE_775=m
1422CONFIG_NLS_CODEPAGE_850=m
1423CONFIG_NLS_CODEPAGE_852=m
1424CONFIG_NLS_CODEPAGE_855=m
1425CONFIG_NLS_CODEPAGE_857=m
1426CONFIG_NLS_CODEPAGE_860=m
1427CONFIG_NLS_CODEPAGE_861=m
1428CONFIG_NLS_CODEPAGE_862=m
1429CONFIG_NLS_CODEPAGE_863=m
1430CONFIG_NLS_CODEPAGE_864=m
1431CONFIG_NLS_CODEPAGE_865=m
1432CONFIG_NLS_CODEPAGE_866=m
1433CONFIG_NLS_CODEPAGE_869=m
1434CONFIG_NLS_CODEPAGE_936=m
1435CONFIG_NLS_CODEPAGE_950=m
1436CONFIG_NLS_CODEPAGE_932=m
1437CONFIG_NLS_CODEPAGE_949=m
1438CONFIG_NLS_CODEPAGE_874=m
1439CONFIG_NLS_ISO8859_8=m
1440CONFIG_NLS_CODEPAGE_1250=m
1441CONFIG_NLS_CODEPAGE_1251=m
1442CONFIG_NLS_ASCII=m
1443CONFIG_NLS_ISO8859_1=m
1444CONFIG_NLS_ISO8859_2=m
1445CONFIG_NLS_ISO8859_3=m
1446CONFIG_NLS_ISO8859_4=m
1447CONFIG_NLS_ISO8859_5=m
1448CONFIG_NLS_ISO8859_6=m
1449CONFIG_NLS_ISO8859_7=m
1450CONFIG_NLS_ISO8859_9=m
1451CONFIG_NLS_ISO8859_13=m
1452CONFIG_NLS_ISO8859_14=m
1453CONFIG_NLS_ISO8859_15=m
1454CONFIG_NLS_KOI8_R=m
1455CONFIG_NLS_KOI8_U=m
1456CONFIG_NLS_UTF8=m
1457# CONFIG_DLM is not set
1458
1459#
1460# Library routines
1461#
1462CONFIG_BITREVERSE=y
1463CONFIG_GENERIC_FIND_LAST_BIT=y
1464CONFIG_CRC_CCITT=y
1465# CONFIG_CRC16 is not set
1466CONFIG_CRC_T10DIF=y
1467CONFIG_CRC_ITU_T=y
1468CONFIG_CRC32=y
1469# CONFIG_CRC7 is not set
1470CONFIG_LIBCRC32C=y
1471CONFIG_ZLIB_INFLATE=y
1472CONFIG_ZLIB_DEFLATE=y
1473CONFIG_PLIST=y
1474CONFIG_HAS_IOMEM=y
1475CONFIG_HAS_IOPORT=y
1476CONFIG_HAS_DMA=y
1477CONFIG_HAVE_LMB=y
1478
1479#
1480# Kernel hacking
1481#
1482# CONFIG_PRINTK_TIME is not set
1483CONFIG_ENABLE_WARN_DEPRECATED=y
1484CONFIG_ENABLE_MUST_CHECK=y
1485CONFIG_FRAME_WARN=1024
1486CONFIG_MAGIC_SYSRQ=y
1487# CONFIG_UNUSED_SYMBOLS is not set
1488# CONFIG_DEBUG_FS is not set
1489# CONFIG_HEADERS_CHECK is not set
1490# CONFIG_DEBUG_KERNEL is not set
1491# CONFIG_DEBUG_BUGVERBOSE is not set
1492# CONFIG_DEBUG_MEMORY_INIT is not set
1493# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1494# CONFIG_LATENCYTOP is not set
1495CONFIG_SYSCTL_SYSCALL_CHECK=y
1496CONFIG_HAVE_FUNCTION_TRACER=y
1497CONFIG_HAVE_DYNAMIC_FTRACE=y
1498CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1499
1500#
1501# Tracers
1502#
1503# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1504# CONFIG_SAMPLES is not set
1505CONFIG_HAVE_ARCH_KGDB=y
1506CONFIG_PRINT_STACK_DEPTH=64
1507# CONFIG_IRQSTACKS is not set
1508# CONFIG_BOOTX_TEXT is not set
1509# CONFIG_PPC_EARLY_DEBUG is not set
1510
1511#
1512# Security options
1513#
1514# CONFIG_KEYS is not set
1515# CONFIG_SECURITY is not set
1516# CONFIG_SECURITYFS is not set
1517# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1518CONFIG_CRYPTO=y
1519
1520#
1521# Crypto core or helper
1522#
1523# CONFIG_CRYPTO_FIPS is not set
1524CONFIG_CRYPTO_ALGAPI=y
1525CONFIG_CRYPTO_ALGAPI2=y
1526CONFIG_CRYPTO_AEAD=m
1527CONFIG_CRYPTO_AEAD2=y
1528CONFIG_CRYPTO_BLKCIPHER=y
1529CONFIG_CRYPTO_BLKCIPHER2=y
1530CONFIG_CRYPTO_HASH=y
1531CONFIG_CRYPTO_HASH2=y
1532CONFIG_CRYPTO_RNG2=y
1533CONFIG_CRYPTO_MANAGER=y
1534CONFIG_CRYPTO_MANAGER2=y
1535# CONFIG_CRYPTO_GF128MUL is not set
1536# CONFIG_CRYPTO_NULL is not set
1537# CONFIG_CRYPTO_CRYPTD is not set
1538CONFIG_CRYPTO_AUTHENC=m
1539# CONFIG_CRYPTO_TEST is not set
1540
1541#
1542# Authenticated Encryption with Associated Data
1543#
1544# CONFIG_CRYPTO_CCM is not set
1545# CONFIG_CRYPTO_GCM is not set
1546# CONFIG_CRYPTO_SEQIV is not set
1547
1548#
1549# Block modes
1550#
1551CONFIG_CRYPTO_CBC=y
1552# CONFIG_CRYPTO_CTR is not set
1553# CONFIG_CRYPTO_CTS is not set
1554# CONFIG_CRYPTO_ECB is not set
1555# CONFIG_CRYPTO_LRW is not set
1556# CONFIG_CRYPTO_PCBC is not set
1557# CONFIG_CRYPTO_XTS is not set
1558
1559#
1560# Hash modes
1561#
1562CONFIG_CRYPTO_HMAC=m
1563# CONFIG_CRYPTO_XCBC is not set
1564
1565#
1566# Digest
1567#
1568CONFIG_CRYPTO_CRC32C=y
1569# CONFIG_CRYPTO_MD4 is not set
1570CONFIG_CRYPTO_MD5=y
1571# CONFIG_CRYPTO_MICHAEL_MIC is not set
1572# CONFIG_CRYPTO_RMD128 is not set
1573# CONFIG_CRYPTO_RMD160 is not set
1574# CONFIG_CRYPTO_RMD256 is not set
1575# CONFIG_CRYPTO_RMD320 is not set
1576CONFIG_CRYPTO_SHA1=m
1577# CONFIG_CRYPTO_SHA256 is not set
1578# CONFIG_CRYPTO_SHA512 is not set
1579# CONFIG_CRYPTO_TGR192 is not set
1580# CONFIG_CRYPTO_WP512 is not set
1581
1582#
1583# Ciphers
1584#
1585# CONFIG_CRYPTO_AES is not set
1586# CONFIG_CRYPTO_ANUBIS is not set
1587# CONFIG_CRYPTO_ARC4 is not set
1588# CONFIG_CRYPTO_BLOWFISH is not set
1589# CONFIG_CRYPTO_CAMELLIA is not set
1590# CONFIG_CRYPTO_CAST5 is not set
1591# CONFIG_CRYPTO_CAST6 is not set
1592CONFIG_CRYPTO_DES=y
1593# CONFIG_CRYPTO_FCRYPT is not set
1594# CONFIG_CRYPTO_KHAZAD is not set
1595# CONFIG_CRYPTO_SALSA20 is not set
1596# CONFIG_CRYPTO_SEED is not set
1597# CONFIG_CRYPTO_SERPENT is not set
1598# CONFIG_CRYPTO_TEA is not set
1599# CONFIG_CRYPTO_TWOFISH is not set
1600
1601#
1602# Compression
1603#
1604CONFIG_CRYPTO_DEFLATE=m
1605# CONFIG_CRYPTO_LZO is not set
1606
1607#
1608# Random Number Generation
1609#
1610# CONFIG_CRYPTO_ANSI_CPRNG is not set
1611# CONFIG_CRYPTO_HW is not set
1612# CONFIG_PPC_CLOCK is not set
1613# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/amigaone_defconfig b/arch/powerpc/configs/amigaone_defconfig
new file mode 100644
index 000000000000..b63cc38df6b1
--- /dev/null
+++ b/arch/powerpc/configs/amigaone_defconfig
@@ -0,0 +1,1636 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29-rc3
4# Sun Feb 1 14:22:42 2009
5#
6# CONFIG_PPC64 is not set
7
8#
9# Processor support
10#
11CONFIG_6xx=y
12# CONFIG_PPC_85xx is not set
13# CONFIG_PPC_8xx is not set
14# CONFIG_40x is not set
15# CONFIG_44x is not set
16# CONFIG_E200 is not set
17CONFIG_PPC_FPU=y
18CONFIG_ALTIVEC=y
19CONFIG_PPC_STD_MMU=y
20CONFIG_PPC_STD_MMU_32=y
21# CONFIG_PPC_MM_SLICES is not set
22# CONFIG_SMP is not set
23CONFIG_NOT_COHERENT_CACHE=y
24CONFIG_CHECK_CACHE_COHERENCY=y
25CONFIG_PPC32=y
26CONFIG_WORD_SIZE=32
27# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
28CONFIG_MMU=y
29CONFIG_GENERIC_CMOS_UPDATE=y
30CONFIG_GENERIC_TIME=y
31CONFIG_GENERIC_TIME_VSYSCALL=y
32CONFIG_GENERIC_CLOCKEVENTS=y
33CONFIG_GENERIC_HARDIRQS=y
34# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
35CONFIG_IRQ_PER_CPU=y
36CONFIG_STACKTRACE_SUPPORT=y
37CONFIG_HAVE_LATENCYTOP_SUPPORT=y
38CONFIG_LOCKDEP_SUPPORT=y
39CONFIG_RWSEM_XCHGADD_ALGORITHM=y
40CONFIG_ARCH_HAS_ILOG2_U32=y
41CONFIG_GENERIC_HWEIGHT=y
42CONFIG_GENERIC_CALIBRATE_DELAY=y
43CONFIG_GENERIC_FIND_NEXT_BIT=y
44# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
45CONFIG_PPC=y
46CONFIG_EARLY_PRINTK=y
47CONFIG_GENERIC_NVRAM=y
48CONFIG_SCHED_OMIT_FRAME_POINTER=y
49CONFIG_ARCH_MAY_HAVE_PC_FDC=y
50CONFIG_PPC_OF=y
51CONFIG_OF=y
52CONFIG_PPC_UDBG_16550=y
53# CONFIG_GENERIC_TBSYNC is not set
54CONFIG_AUDIT_ARCH=y
55CONFIG_GENERIC_BUG=y
56CONFIG_DEFAULT_UIMAGE=y
57# CONFIG_PPC_DCR_NATIVE is not set
58# CONFIG_PPC_DCR_MMIO is not set
59CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
60
61#
62# General setup
63#
64CONFIG_EXPERIMENTAL=y
65CONFIG_BROKEN_ON_SMP=y
66CONFIG_INIT_ENV_ARG_LIMIT=32
67CONFIG_LOCALVERSION=""
68# CONFIG_LOCALVERSION_AUTO is not set
69CONFIG_SWAP=y
70CONFIG_SYSVIPC=y
71CONFIG_SYSVIPC_SYSCTL=y
72CONFIG_POSIX_MQUEUE=y
73# CONFIG_BSD_PROCESS_ACCT is not set
74# CONFIG_TASKSTATS is not set
75# CONFIG_AUDIT is not set
76
77#
78# RCU Subsystem
79#
80CONFIG_CLASSIC_RCU=y
81# CONFIG_TREE_RCU is not set
82# CONFIG_PREEMPT_RCU is not set
83# CONFIG_TREE_RCU_TRACE is not set
84# CONFIG_PREEMPT_RCU_TRACE is not set
85CONFIG_IKCONFIG=y
86CONFIG_IKCONFIG_PROC=y
87CONFIG_LOG_BUF_SHIFT=15
88# CONFIG_GROUP_SCHED is not set
89# CONFIG_CGROUPS is not set
90CONFIG_SYSFS_DEPRECATED=y
91CONFIG_SYSFS_DEPRECATED_V2=y
92# CONFIG_RELAY is not set
93CONFIG_NAMESPACES=y
94# CONFIG_UTS_NS is not set
95# CONFIG_IPC_NS is not set
96# CONFIG_USER_NS is not set
97# CONFIG_PID_NS is not set
98# CONFIG_NET_NS is not set
99CONFIG_BLK_DEV_INITRD=y
100CONFIG_INITRAMFS_SOURCE=""
101CONFIG_CC_OPTIMIZE_FOR_SIZE=y
102CONFIG_SYSCTL=y
103# CONFIG_EMBEDDED is not set
104CONFIG_SYSCTL_SYSCALL=y
105CONFIG_KALLSYMS=y
106# CONFIG_KALLSYMS_ALL is not set
107# CONFIG_KALLSYMS_EXTRA_PASS is not set
108CONFIG_HOTPLUG=y
109CONFIG_PRINTK=y
110CONFIG_BUG=y
111CONFIG_ELF_CORE=y
112CONFIG_PCSPKR_PLATFORM=y
113# CONFIG_COMPAT_BRK is not set
114CONFIG_BASE_FULL=y
115CONFIG_FUTEX=y
116CONFIG_ANON_INODES=y
117CONFIG_EPOLL=y
118CONFIG_SIGNALFD=y
119CONFIG_TIMERFD=y
120CONFIG_EVENTFD=y
121CONFIG_SHMEM=y
122CONFIG_AIO=y
123CONFIG_VM_EVENT_COUNTERS=y
124CONFIG_PCI_QUIRKS=y
125CONFIG_SLUB_DEBUG=y
126# CONFIG_SLAB is not set
127CONFIG_SLUB=y
128# CONFIG_SLOB is not set
129# CONFIG_PROFILING is not set
130CONFIG_HAVE_OPROFILE=y
131# CONFIG_KPROBES is not set
132CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
133CONFIG_HAVE_IOREMAP_PROT=y
134CONFIG_HAVE_KPROBES=y
135CONFIG_HAVE_KRETPROBES=y
136CONFIG_HAVE_ARCH_TRACEHOOK=y
137# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
138CONFIG_SLABINFO=y
139CONFIG_RT_MUTEXES=y
140CONFIG_BASE_SMALL=0
141CONFIG_MODULES=y
142# CONFIG_MODULE_FORCE_LOAD is not set
143CONFIG_MODULE_UNLOAD=y
144CONFIG_MODULE_FORCE_UNLOAD=y
145# CONFIG_MODVERSIONS is not set
146# CONFIG_MODULE_SRCVERSION_ALL is not set
147CONFIG_BLOCK=y
148CONFIG_LBD=y
149# CONFIG_BLK_DEV_IO_TRACE is not set
150# CONFIG_BLK_DEV_BSG is not set
151# CONFIG_BLK_DEV_INTEGRITY is not set
152
153#
154# IO Schedulers
155#
156CONFIG_IOSCHED_NOOP=y
157CONFIG_IOSCHED_AS=y
158CONFIG_IOSCHED_DEADLINE=y
159CONFIG_IOSCHED_CFQ=y
160CONFIG_DEFAULT_AS=y
161# CONFIG_DEFAULT_DEADLINE is not set
162# CONFIG_DEFAULT_CFQ is not set
163# CONFIG_DEFAULT_NOOP is not set
164CONFIG_DEFAULT_IOSCHED="anticipatory"
165# CONFIG_FREEZER is not set
166
167#
168# Platform support
169#
170CONFIG_PPC_MULTIPLATFORM=y
171CONFIG_CLASSIC32=y
172# CONFIG_PPC_CHRP is not set
173# CONFIG_MPC5121_ADS is not set
174# CONFIG_MPC5121_GENERIC is not set
175# CONFIG_PPC_MPC52xx is not set
176# CONFIG_PPC_PMAC is not set
177# CONFIG_PPC_CELL is not set
178# CONFIG_PPC_CELL_NATIVE is not set
179# CONFIG_PPC_82xx is not set
180# CONFIG_PQ2ADS is not set
181# CONFIG_PPC_83xx is not set
182# CONFIG_PPC_86xx is not set
183# CONFIG_EMBEDDED6xx is not set
184CONFIG_AMIGAONE=y
185# CONFIG_IPIC is not set
186# CONFIG_MPIC is not set
187# CONFIG_MPIC_WEIRD is not set
188CONFIG_PPC_I8259=y
189# CONFIG_PPC_RTAS is not set
190# CONFIG_MMIO_NVRAM is not set
191# CONFIG_PPC_MPC106 is not set
192# CONFIG_PPC_970_NAP is not set
193# CONFIG_PPC_INDIRECT_IO is not set
194# CONFIG_GENERIC_IOMAP is not set
195# CONFIG_CPU_FREQ is not set
196# CONFIG_TAU is not set
197# CONFIG_FSL_ULI1575 is not set
198# CONFIG_SIMPLE_GPIO is not set
199
200#
201# Kernel options
202#
203CONFIG_HIGHMEM=y
204CONFIG_TICK_ONESHOT=y
205CONFIG_NO_HZ=y
206CONFIG_HIGH_RES_TIMERS=y
207CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
208# CONFIG_HZ_100 is not set
209CONFIG_HZ_250=y
210# CONFIG_HZ_300 is not set
211# CONFIG_HZ_1000 is not set
212CONFIG_HZ=250
213CONFIG_SCHED_HRTICK=y
214CONFIG_PREEMPT_NONE=y
215# CONFIG_PREEMPT_VOLUNTARY is not set
216# CONFIG_PREEMPT is not set
217CONFIG_BINFMT_ELF=y
218# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
219# CONFIG_HAVE_AOUT is not set
220CONFIG_BINFMT_MISC=y
221# CONFIG_IOMMU_HELPER is not set
222CONFIG_PPC_NEED_DMA_SYNC_OPS=y
223CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
224CONFIG_ARCH_HAS_WALK_MEMORY=y
225CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
226# CONFIG_KEXEC is not set
227# CONFIG_CRASH_DUMP is not set
228CONFIG_ARCH_FLATMEM_ENABLE=y
229CONFIG_ARCH_POPULATES_NODE_MAP=y
230CONFIG_SELECT_MEMORY_MODEL=y
231CONFIG_FLATMEM_MANUAL=y
232# CONFIG_DISCONTIGMEM_MANUAL is not set
233# CONFIG_SPARSEMEM_MANUAL is not set
234CONFIG_FLATMEM=y
235CONFIG_FLAT_NODE_MEM_MAP=y
236CONFIG_PAGEFLAGS_EXTENDED=y
237CONFIG_SPLIT_PTLOCK_CPUS=4
238# CONFIG_MIGRATION is not set
239# CONFIG_PHYS_ADDR_T_64BIT is not set
240CONFIG_ZONE_DMA_FLAG=1
241CONFIG_BOUNCE=y
242CONFIG_VIRT_TO_BUS=y
243CONFIG_UNEVICTABLE_LRU=y
244CONFIG_PPC_4K_PAGES=y
245# CONFIG_PPC_16K_PAGES is not set
246# CONFIG_PPC_64K_PAGES is not set
247CONFIG_FORCE_MAX_ZONEORDER=11
248CONFIG_PROC_DEVICETREE=y
249# CONFIG_CMDLINE_BOOL is not set
250CONFIG_EXTRA_TARGETS=""
251# CONFIG_PM is not set
252CONFIG_SECCOMP=y
253CONFIG_ISA_DMA_API=y
254
255#
256# Bus options
257#
258CONFIG_ZONE_DMA=y
259CONFIG_GENERIC_ISA_DMA=y
260CONFIG_PPC_INDIRECT_PCI=y
261CONFIG_PCI=y
262CONFIG_PCI_DOMAINS=y
263CONFIG_PCI_SYSCALL=y
264# CONFIG_PCIEPORTBUS is not set
265CONFIG_ARCH_SUPPORTS_MSI=y
266# CONFIG_PCI_MSI is not set
267# CONFIG_PCI_LEGACY is not set
268# CONFIG_PCI_DEBUG is not set
269# CONFIG_PCI_STUB is not set
270# CONFIG_PCCARD is not set
271# CONFIG_HOTPLUG_PCI is not set
272# CONFIG_HAS_RAPIDIO is not set
273
274#
275# Advanced setup
276#
277# CONFIG_ADVANCED_OPTIONS is not set
278
279#
280# Default settings for advanced configuration options are used
281#
282CONFIG_LOWMEM_SIZE=0x30000000
283CONFIG_PAGE_OFFSET=0xc0000000
284CONFIG_KERNEL_START=0xc0000000
285CONFIG_PHYSICAL_START=0x00000000
286CONFIG_TASK_SIZE=0xc0000000
287CONFIG_CONSISTENT_START=0xff100000
288CONFIG_CONSISTENT_SIZE=0x00200000
289CONFIG_NET=y
290
291#
292# Networking options
293#
294CONFIG_COMPAT_NET_DEV_OPS=y
295CONFIG_PACKET=y
296# CONFIG_PACKET_MMAP is not set
297CONFIG_UNIX=y
298# CONFIG_NET_KEY is not set
299CONFIG_INET=y
300CONFIG_IP_MULTICAST=y
301# CONFIG_IP_ADVANCED_ROUTER is not set
302CONFIG_IP_FIB_HASH=y
303# CONFIG_IP_PNP is not set
304# CONFIG_NET_IPIP is not set
305# CONFIG_NET_IPGRE is not set
306# CONFIG_IP_MROUTE is not set
307# CONFIG_ARPD is not set
308CONFIG_SYN_COOKIES=y
309# CONFIG_INET_AH is not set
310# CONFIG_INET_ESP is not set
311# CONFIG_INET_IPCOMP is not set
312# CONFIG_INET_XFRM_TUNNEL is not set
313# CONFIG_INET_TUNNEL is not set
314# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
315# CONFIG_INET_XFRM_MODE_TUNNEL is not set
316# CONFIG_INET_XFRM_MODE_BEET is not set
317# CONFIG_INET_LRO is not set
318CONFIG_INET_DIAG=y
319CONFIG_INET_TCP_DIAG=y
320# CONFIG_TCP_CONG_ADVANCED is not set
321CONFIG_TCP_CONG_CUBIC=y
322CONFIG_DEFAULT_TCP_CONG="cubic"
323# CONFIG_TCP_MD5SIG is not set
324# CONFIG_IPV6 is not set
325# CONFIG_NETWORK_SECMARK is not set
326CONFIG_NETFILTER=y
327# CONFIG_NETFILTER_DEBUG is not set
328# CONFIG_NETFILTER_ADVANCED is not set
329
330#
331# Core Netfilter Configuration
332#
333CONFIG_NETFILTER_NETLINK=m
334CONFIG_NETFILTER_NETLINK_LOG=m
335CONFIG_NF_CONNTRACK=m
336CONFIG_NF_CONNTRACK_FTP=m
337CONFIG_NF_CONNTRACK_IRC=m
338CONFIG_NF_CONNTRACK_SIP=m
339CONFIG_NF_CT_NETLINK=m
340CONFIG_NETFILTER_XTABLES=m
341# CONFIG_NETFILTER_XT_TARGET_MARK is not set
342# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
343# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
344# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
345# CONFIG_NETFILTER_XT_MATCH_MARK is not set
346# CONFIG_NETFILTER_XT_MATCH_STATE is not set
347# CONFIG_IP_VS is not set
348
349#
350# IP: Netfilter Configuration
351#
352CONFIG_NF_DEFRAG_IPV4=m
353CONFIG_NF_CONNTRACK_IPV4=m
354CONFIG_NF_CONNTRACK_PROC_COMPAT=y
355CONFIG_IP_NF_IPTABLES=m
356CONFIG_IP_NF_FILTER=m
357CONFIG_IP_NF_TARGET_REJECT=m
358CONFIG_IP_NF_TARGET_LOG=m
359# CONFIG_IP_NF_TARGET_ULOG is not set
360CONFIG_NF_NAT=m
361CONFIG_NF_NAT_NEEDED=y
362CONFIG_IP_NF_TARGET_MASQUERADE=m
363CONFIG_NF_NAT_FTP=m
364CONFIG_NF_NAT_IRC=m
365# CONFIG_NF_NAT_TFTP is not set
366# CONFIG_NF_NAT_AMANDA is not set
367# CONFIG_NF_NAT_PPTP is not set
368# CONFIG_NF_NAT_H323 is not set
369CONFIG_NF_NAT_SIP=m
370# CONFIG_IP_NF_MANGLE is not set
371# CONFIG_IP_DCCP is not set
372# CONFIG_IP_SCTP is not set
373# CONFIG_TIPC is not set
374# CONFIG_ATM is not set
375# CONFIG_BRIDGE is not set
376# CONFIG_NET_DSA is not set
377# CONFIG_VLAN_8021Q is not set
378# CONFIG_DECNET is not set
379# CONFIG_LLC2 is not set
380# CONFIG_IPX is not set
381# CONFIG_ATALK is not set
382# CONFIG_X25 is not set
383# CONFIG_LAPB is not set
384# CONFIG_ECONET is not set
385# CONFIG_WAN_ROUTER is not set
386# CONFIG_NET_SCHED is not set
387# CONFIG_DCB is not set
388
389#
390# Network testing
391#
392# CONFIG_NET_PKTGEN is not set
393# CONFIG_HAMRADIO is not set
394# CONFIG_CAN is not set
395# CONFIG_IRDA is not set
396# CONFIG_BT is not set
397# CONFIG_AF_RXRPC is not set
398# CONFIG_PHONET is not set
399# CONFIG_WIRELESS is not set
400# CONFIG_WIMAX is not set
401# CONFIG_RFKILL is not set
402# CONFIG_NET_9P is not set
403
404#
405# Device Drivers
406#
407
408#
409# Generic Driver Options
410#
411CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
412# CONFIG_STANDALONE is not set
413CONFIG_PREVENT_FIRMWARE_BUILD=y
414CONFIG_FW_LOADER=y
415CONFIG_FIRMWARE_IN_KERNEL=y
416CONFIG_EXTRA_FIRMWARE=""
417# CONFIG_DEBUG_DRIVER is not set
418# CONFIG_DEBUG_DEVRES is not set
419# CONFIG_SYS_HYPERVISOR is not set
420# CONFIG_CONNECTOR is not set
421# CONFIG_MTD is not set
422CONFIG_OF_DEVICE=y
423CONFIG_OF_I2C=y
424CONFIG_PARPORT=y
425CONFIG_PARPORT_PC=y
426# CONFIG_PARPORT_SERIAL is not set
427CONFIG_PARPORT_PC_FIFO=y
428# CONFIG_PARPORT_PC_SUPERIO is not set
429# CONFIG_PARPORT_GSC is not set
430# CONFIG_PARPORT_AX88796 is not set
431# CONFIG_PARPORT_1284 is not set
432CONFIG_BLK_DEV=y
433CONFIG_BLK_DEV_FD=y
434# CONFIG_PARIDE is not set
435# CONFIG_BLK_CPQ_DA is not set
436# CONFIG_BLK_CPQ_CISS_DA is not set
437# CONFIG_BLK_DEV_DAC960 is not set
438# CONFIG_BLK_DEV_UMEM is not set
439# CONFIG_BLK_DEV_COW_COMMON is not set
440CONFIG_BLK_DEV_LOOP=y
441# CONFIG_BLK_DEV_CRYPTOLOOP is not set
442# CONFIG_BLK_DEV_NBD is not set
443# CONFIG_BLK_DEV_SX8 is not set
444# CONFIG_BLK_DEV_UB is not set
445CONFIG_BLK_DEV_RAM=y
446CONFIG_BLK_DEV_RAM_COUNT=16
447CONFIG_BLK_DEV_RAM_SIZE=4096
448# CONFIG_BLK_DEV_XIP is not set
449# CONFIG_CDROM_PKTCDVD is not set
450# CONFIG_ATA_OVER_ETH is not set
451# CONFIG_BLK_DEV_HD is not set
452CONFIG_MISC_DEVICES=y
453# CONFIG_PHANTOM is not set
454# CONFIG_SGI_IOC4 is not set
455# CONFIG_TIFM_CORE is not set
456# CONFIG_ICS932S401 is not set
457# CONFIG_ENCLOSURE_SERVICES is not set
458# CONFIG_HP_ILO is not set
459# CONFIG_C2PORT is not set
460
461#
462# EEPROM support
463#
464# CONFIG_EEPROM_AT24 is not set
465# CONFIG_EEPROM_LEGACY is not set
466# CONFIG_EEPROM_93CX6 is not set
467CONFIG_HAVE_IDE=y
468CONFIG_IDE=y
469
470#
471# Please see Documentation/ide/ide.txt for help/info on IDE drives
472#
473CONFIG_IDE_TIMINGS=y
474CONFIG_IDE_ATAPI=y
475# CONFIG_BLK_DEV_IDE_SATA is not set
476CONFIG_IDE_GD=y
477CONFIG_IDE_GD_ATA=y
478# CONFIG_IDE_GD_ATAPI is not set
479CONFIG_BLK_DEV_IDECD=y
480CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
481# CONFIG_BLK_DEV_IDETAPE is not set
482# CONFIG_IDE_TASK_IOCTL is not set
483CONFIG_IDE_PROC_FS=y
484
485#
486# IDE chipset support/bugfixes
487#
488# CONFIG_BLK_DEV_PLATFORM is not set
489CONFIG_BLK_DEV_IDEDMA_SFF=y
490
491#
492# PCI IDE chipsets support
493#
494CONFIG_BLK_DEV_IDEPCI=y
495# CONFIG_IDEPCI_PCIBUS_ORDER is not set
496# CONFIG_BLK_DEV_OFFBOARD is not set
497CONFIG_BLK_DEV_GENERIC=y
498# CONFIG_BLK_DEV_OPTI621 is not set
499CONFIG_BLK_DEV_IDEDMA_PCI=y
500# CONFIG_BLK_DEV_AEC62XX is not set
501# CONFIG_BLK_DEV_ALI15X3 is not set
502# CONFIG_BLK_DEV_AMD74XX is not set
503# CONFIG_BLK_DEV_CMD64X is not set
504# CONFIG_BLK_DEV_TRIFLEX is not set
505# CONFIG_BLK_DEV_CS5520 is not set
506# CONFIG_BLK_DEV_CS5530 is not set
507# CONFIG_BLK_DEV_HPT366 is not set
508# CONFIG_BLK_DEV_JMICRON is not set
509# CONFIG_BLK_DEV_SC1200 is not set
510# CONFIG_BLK_DEV_PIIX is not set
511# CONFIG_BLK_DEV_IT8172 is not set
512# CONFIG_BLK_DEV_IT8213 is not set
513# CONFIG_BLK_DEV_IT821X is not set
514# CONFIG_BLK_DEV_NS87415 is not set
515# CONFIG_BLK_DEV_PDC202XX_OLD is not set
516# CONFIG_BLK_DEV_PDC202XX_NEW is not set
517# CONFIG_BLK_DEV_SVWKS is not set
518CONFIG_BLK_DEV_SIIMAGE=y
519# CONFIG_BLK_DEV_SL82C105 is not set
520# CONFIG_BLK_DEV_SLC90E66 is not set
521# CONFIG_BLK_DEV_TRM290 is not set
522CONFIG_BLK_DEV_VIA82CXXX=y
523# CONFIG_BLK_DEV_TC86C001 is not set
524CONFIG_BLK_DEV_IDEDMA=y
525
526#
527# SCSI device support
528#
529# CONFIG_RAID_ATTRS is not set
530CONFIG_SCSI=y
531CONFIG_SCSI_DMA=y
532# CONFIG_SCSI_TGT is not set
533# CONFIG_SCSI_NETLINK is not set
534CONFIG_SCSI_PROC_FS=y
535
536#
537# SCSI support type (disk, tape, CD-ROM)
538#
539CONFIG_BLK_DEV_SD=y
540CONFIG_CHR_DEV_ST=y
541# CONFIG_CHR_DEV_OSST is not set
542CONFIG_BLK_DEV_SR=y
543CONFIG_BLK_DEV_SR_VENDOR=y
544CONFIG_CHR_DEV_SG=y
545# CONFIG_CHR_DEV_SCH is not set
546
547#
548# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
549#
550# CONFIG_SCSI_MULTI_LUN is not set
551CONFIG_SCSI_CONSTANTS=y
552# CONFIG_SCSI_LOGGING is not set
553# CONFIG_SCSI_SCAN_ASYNC is not set
554CONFIG_SCSI_WAIT_SCAN=m
555
556#
557# SCSI Transports
558#
559CONFIG_SCSI_SPI_ATTRS=y
560# CONFIG_SCSI_FC_ATTRS is not set
561# CONFIG_SCSI_ISCSI_ATTRS is not set
562# CONFIG_SCSI_SAS_LIBSAS is not set
563# CONFIG_SCSI_SRP_ATTRS is not set
564CONFIG_SCSI_LOWLEVEL=y
565# CONFIG_ISCSI_TCP is not set
566# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
567# CONFIG_SCSI_3W_9XXX is not set
568# CONFIG_SCSI_ACARD is not set
569# CONFIG_SCSI_AACRAID is not set
570# CONFIG_SCSI_AIC7XXX is not set
571# CONFIG_SCSI_AIC7XXX_OLD is not set
572# CONFIG_SCSI_AIC79XX is not set
573# CONFIG_SCSI_AIC94XX is not set
574# CONFIG_SCSI_DPT_I2O is not set
575# CONFIG_SCSI_ADVANSYS is not set
576# CONFIG_SCSI_ARCMSR is not set
577# CONFIG_MEGARAID_NEWGEN is not set
578# CONFIG_MEGARAID_LEGACY is not set
579# CONFIG_MEGARAID_SAS is not set
580# CONFIG_SCSI_HPTIOP is not set
581# CONFIG_SCSI_BUSLOGIC is not set
582# CONFIG_LIBFC is not set
583# CONFIG_FCOE is not set
584# CONFIG_SCSI_DMX3191D is not set
585# CONFIG_SCSI_EATA is not set
586# CONFIG_SCSI_FUTURE_DOMAIN is not set
587# CONFIG_SCSI_GDTH is not set
588# CONFIG_SCSI_IPS is not set
589# CONFIG_SCSI_INITIO is not set
590# CONFIG_SCSI_INIA100 is not set
591# CONFIG_SCSI_PPA is not set
592# CONFIG_SCSI_IMM is not set
593# CONFIG_SCSI_MVSAS is not set
594# CONFIG_SCSI_STEX is not set
595CONFIG_SCSI_SYM53C8XX_2=y
596CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0
597CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
598CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
599# CONFIG_SCSI_SYM53C8XX_MMIO is not set
600# CONFIG_SCSI_QLOGIC_1280 is not set
601# CONFIG_SCSI_QLA_FC is not set
602# CONFIG_SCSI_QLA_ISCSI is not set
603# CONFIG_SCSI_LPFC is not set
604# CONFIG_SCSI_DC395x is not set
605# CONFIG_SCSI_DC390T is not set
606# CONFIG_SCSI_NSP32 is not set
607# CONFIG_SCSI_DEBUG is not set
608# CONFIG_SCSI_SRP is not set
609# CONFIG_SCSI_DH is not set
610# CONFIG_ATA is not set
611# CONFIG_MD is not set
612# CONFIG_FUSION is not set
613
614#
615# IEEE 1394 (FireWire) support
616#
617
618#
619# Enable only one of the two stacks, unless you know what you are doing
620#
621# CONFIG_FIREWIRE is not set
622# CONFIG_IEEE1394 is not set
623# CONFIG_I2O is not set
624# CONFIG_MACINTOSH_DRIVERS is not set
625CONFIG_NETDEVICES=y
626# CONFIG_DUMMY is not set
627# CONFIG_BONDING is not set
628# CONFIG_MACVLAN is not set
629# CONFIG_EQUALIZER is not set
630# CONFIG_TUN is not set
631# CONFIG_VETH is not set
632# CONFIG_ARCNET is not set
633CONFIG_PHYLIB=y
634
635#
636# MII PHY device drivers
637#
638# CONFIG_MARVELL_PHY is not set
639# CONFIG_DAVICOM_PHY is not set
640# CONFIG_QSEMI_PHY is not set
641# CONFIG_LXT_PHY is not set
642# CONFIG_CICADA_PHY is not set
643# CONFIG_VITESSE_PHY is not set
644# CONFIG_SMSC_PHY is not set
645# CONFIG_BROADCOM_PHY is not set
646# CONFIG_ICPLUS_PHY is not set
647# CONFIG_REALTEK_PHY is not set
648# CONFIG_NATIONAL_PHY is not set
649# CONFIG_STE10XP is not set
650# CONFIG_LSI_ET1011C_PHY is not set
651# CONFIG_FIXED_PHY is not set
652# CONFIG_MDIO_BITBANG is not set
653CONFIG_NET_ETHERNET=y
654CONFIG_MII=y
655# CONFIG_HAPPYMEAL is not set
656# CONFIG_SUNGEM is not set
657# CONFIG_CASSINI is not set
658CONFIG_NET_VENDOR_3COM=y
659CONFIG_VORTEX=y
660# CONFIG_TYPHOON is not set
661# CONFIG_NET_TULIP is not set
662# CONFIG_HP100 is not set
663# CONFIG_IBM_NEW_EMAC_ZMII is not set
664# CONFIG_IBM_NEW_EMAC_RGMII is not set
665# CONFIG_IBM_NEW_EMAC_TAH is not set
666# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
667# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
668# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
669# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
670CONFIG_NET_PCI=y
671# CONFIG_PCNET32 is not set
672# CONFIG_AMD8111_ETH is not set
673# CONFIG_ADAPTEC_STARFIRE is not set
674# CONFIG_B44 is not set
675# CONFIG_FORCEDETH is not set
676# CONFIG_E100 is not set
677# CONFIG_FEALNX is not set
678# CONFIG_NATSEMI is not set
679# CONFIG_NE2K_PCI is not set
680CONFIG_8139CP=y
681CONFIG_8139TOO=y
682CONFIG_8139TOO_PIO=y
683# CONFIG_8139TOO_TUNE_TWISTER is not set
684# CONFIG_8139TOO_8129 is not set
685# CONFIG_8139_OLD_RX_RESET is not set
686# CONFIG_R6040 is not set
687# CONFIG_SIS900 is not set
688# CONFIG_EPIC100 is not set
689# CONFIG_SMSC9420 is not set
690# CONFIG_SUNDANCE is not set
691# CONFIG_TLAN is not set
692# CONFIG_VIA_RHINE is not set
693# CONFIG_SC92031 is not set
694# CONFIG_NET_POCKET is not set
695# CONFIG_ATL2 is not set
696# CONFIG_NETDEV_1000 is not set
697# CONFIG_NETDEV_10000 is not set
698# CONFIG_TR is not set
699
700#
701# Wireless LAN
702#
703# CONFIG_WLAN_PRE80211 is not set
704# CONFIG_WLAN_80211 is not set
705# CONFIG_IWLWIFI_LEDS is not set
706
707#
708# Enable WiMAX (Networking options) to see the WiMAX drivers
709#
710
711#
712# USB Network Adapters
713#
714# CONFIG_USB_CATC is not set
715# CONFIG_USB_KAWETH is not set
716# CONFIG_USB_PEGASUS is not set
717# CONFIG_USB_RTL8150 is not set
718# CONFIG_USB_USBNET is not set
719# CONFIG_WAN is not set
720# CONFIG_FDDI is not set
721# CONFIG_HIPPI is not set
722# CONFIG_PLIP is not set
723CONFIG_PPP=m
724CONFIG_PPP_MULTILINK=y
725CONFIG_PPP_FILTER=y
726CONFIG_PPP_ASYNC=m
727CONFIG_PPP_SYNC_TTY=m
728CONFIG_PPP_DEFLATE=m
729CONFIG_PPP_BSDCOMP=m
730CONFIG_PPP_MPPE=m
731CONFIG_PPPOE=m
732# CONFIG_PPPOL2TP is not set
733# CONFIG_SLIP is not set
734CONFIG_SLHC=m
735# CONFIG_NET_FC is not set
736# CONFIG_NETCONSOLE is not set
737# CONFIG_NETPOLL is not set
738# CONFIG_NET_POLL_CONTROLLER is not set
739# CONFIG_ISDN is not set
740# CONFIG_PHONE is not set
741
742#
743# Input device support
744#
745CONFIG_INPUT=y
746# CONFIG_INPUT_FF_MEMLESS is not set
747# CONFIG_INPUT_POLLDEV is not set
748
749#
750# Userland interfaces
751#
752CONFIG_INPUT_MOUSEDEV=y
753CONFIG_INPUT_MOUSEDEV_PSAUX=y
754CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
755CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
756# CONFIG_INPUT_JOYDEV is not set
757CONFIG_INPUT_EVDEV=y
758# CONFIG_INPUT_EVBUG is not set
759
760#
761# Input Device Drivers
762#
763CONFIG_INPUT_KEYBOARD=y
764CONFIG_KEYBOARD_ATKBD=y
765# CONFIG_KEYBOARD_SUNKBD is not set
766# CONFIG_KEYBOARD_LKKBD is not set
767# CONFIG_KEYBOARD_XTKBD is not set
768# CONFIG_KEYBOARD_NEWTON is not set
769# CONFIG_KEYBOARD_STOWAWAY is not set
770CONFIG_INPUT_MOUSE=y
771CONFIG_MOUSE_PS2=y
772CONFIG_MOUSE_PS2_ALPS=y
773CONFIG_MOUSE_PS2_LOGIPS2PP=y
774CONFIG_MOUSE_PS2_SYNAPTICS=y
775CONFIG_MOUSE_PS2_LIFEBOOK=y
776CONFIG_MOUSE_PS2_TRACKPOINT=y
777# CONFIG_MOUSE_PS2_ELANTECH is not set
778# CONFIG_MOUSE_PS2_TOUCHKIT is not set
779# CONFIG_MOUSE_SERIAL is not set
780# CONFIG_MOUSE_APPLETOUCH is not set
781# CONFIG_MOUSE_BCM5974 is not set
782# CONFIG_MOUSE_VSXXXAA is not set
783# CONFIG_INPUT_JOYSTICK is not set
784# CONFIG_INPUT_TABLET is not set
785# CONFIG_INPUT_TOUCHSCREEN is not set
786CONFIG_INPUT_MISC=y
787CONFIG_INPUT_PCSPKR=y
788# CONFIG_INPUT_ATI_REMOTE is not set
789# CONFIG_INPUT_ATI_REMOTE2 is not set
790# CONFIG_INPUT_KEYSPAN_REMOTE is not set
791# CONFIG_INPUT_POWERMATE is not set
792# CONFIG_INPUT_YEALINK is not set
793# CONFIG_INPUT_CM109 is not set
794CONFIG_INPUT_UINPUT=y
795
796#
797# Hardware I/O ports
798#
799CONFIG_SERIO=y
800CONFIG_SERIO_I8042=y
801CONFIG_SERIO_SERPORT=y
802# CONFIG_SERIO_PARKBD is not set
803# CONFIG_SERIO_PCIPS2 is not set
804CONFIG_SERIO_LIBPS2=y
805# CONFIG_SERIO_RAW is not set
806# CONFIG_SERIO_XILINX_XPS_PS2 is not set
807# CONFIG_GAMEPORT is not set
808
809#
810# Character devices
811#
812CONFIG_VT=y
813CONFIG_CONSOLE_TRANSLATIONS=y
814CONFIG_VT_CONSOLE=y
815CONFIG_HW_CONSOLE=y
816# CONFIG_VT_HW_CONSOLE_BINDING is not set
817CONFIG_DEVKMEM=y
818# CONFIG_SERIAL_NONSTANDARD is not set
819# CONFIG_NOZOMI is not set
820
821#
822# Serial drivers
823#
824CONFIG_SERIAL_8250=y
825CONFIG_SERIAL_8250_CONSOLE=y
826CONFIG_SERIAL_8250_PCI=y
827CONFIG_SERIAL_8250_NR_UARTS=4
828CONFIG_SERIAL_8250_RUNTIME_UARTS=4
829# CONFIG_SERIAL_8250_EXTENDED is not set
830
831#
832# Non-8250 serial port support
833#
834# CONFIG_SERIAL_UARTLITE is not set
835CONFIG_SERIAL_CORE=y
836CONFIG_SERIAL_CORE_CONSOLE=y
837# CONFIG_SERIAL_JSM is not set
838# CONFIG_SERIAL_OF_PLATFORM is not set
839CONFIG_UNIX98_PTYS=y
840# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
841CONFIG_LEGACY_PTYS=y
842CONFIG_LEGACY_PTY_COUNT=256
843# CONFIG_PRINTER is not set
844# CONFIG_PPDEV is not set
845# CONFIG_HVC_UDBG is not set
846# CONFIG_IPMI_HANDLER is not set
847# CONFIG_HW_RANDOM is not set
848# CONFIG_NVRAM is not set
849# CONFIG_R3964 is not set
850# CONFIG_APPLICOM is not set
851# CONFIG_RAW_DRIVER is not set
852# CONFIG_TCG_TPM is not set
853CONFIG_DEVPORT=y
854CONFIG_I2C=y
855CONFIG_I2C_BOARDINFO=y
856# CONFIG_I2C_CHARDEV is not set
857CONFIG_I2C_HELPER_AUTO=y
858CONFIG_I2C_ALGOBIT=y
859
860#
861# I2C Hardware Bus support
862#
863
864#
865# PC SMBus host controller drivers
866#
867# CONFIG_I2C_ALI1535 is not set
868# CONFIG_I2C_ALI1563 is not set
869# CONFIG_I2C_ALI15X3 is not set
870# CONFIG_I2C_AMD756 is not set
871# CONFIG_I2C_AMD8111 is not set
872# CONFIG_I2C_I801 is not set
873# CONFIG_I2C_ISCH is not set
874# CONFIG_I2C_PIIX4 is not set
875# CONFIG_I2C_NFORCE2 is not set
876# CONFIG_I2C_SIS5595 is not set
877# CONFIG_I2C_SIS630 is not set
878# CONFIG_I2C_SIS96X is not set
879# CONFIG_I2C_VIA is not set
880# CONFIG_I2C_VIAPRO is not set
881
882#
883# I2C system bus drivers (mostly embedded / system-on-chip)
884#
885# CONFIG_I2C_MPC is not set
886# CONFIG_I2C_OCORES is not set
887# CONFIG_I2C_SIMTEC is not set
888
889#
890# External I2C/SMBus adapter drivers
891#
892# CONFIG_I2C_PARPORT is not set
893# CONFIG_I2C_PARPORT_LIGHT is not set
894# CONFIG_I2C_TAOS_EVM is not set
895# CONFIG_I2C_TINY_USB is not set
896
897#
898# Graphics adapter I2C/DDC channel drivers
899#
900# CONFIG_I2C_VOODOO3 is not set
901
902#
903# Other I2C/SMBus bus drivers
904#
905# CONFIG_I2C_PCA_PLATFORM is not set
906# CONFIG_I2C_STUB is not set
907
908#
909# Miscellaneous I2C Chip support
910#
911# CONFIG_DS1682 is not set
912# CONFIG_SENSORS_PCF8574 is not set
913# CONFIG_PCF8575 is not set
914# CONFIG_SENSORS_PCA9539 is not set
915# CONFIG_SENSORS_PCF8591 is not set
916# CONFIG_SENSORS_MAX6875 is not set
917# CONFIG_SENSORS_TSL2550 is not set
918# CONFIG_I2C_DEBUG_CORE is not set
919# CONFIG_I2C_DEBUG_ALGO is not set
920# CONFIG_I2C_DEBUG_BUS is not set
921# CONFIG_I2C_DEBUG_CHIP is not set
922# CONFIG_SPI is not set
923CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
924# CONFIG_GPIOLIB is not set
925# CONFIG_W1 is not set
926# CONFIG_POWER_SUPPLY is not set
927# CONFIG_HWMON is not set
928# CONFIG_THERMAL is not set
929# CONFIG_THERMAL_HWMON is not set
930# CONFIG_WATCHDOG is not set
931CONFIG_SSB_POSSIBLE=y
932
933#
934# Sonics Silicon Backplane
935#
936# CONFIG_SSB is not set
937
938#
939# Multifunction device drivers
940#
941# CONFIG_MFD_CORE is not set
942# CONFIG_MFD_SM501 is not set
943# CONFIG_HTC_PASIC3 is not set
944# CONFIG_TWL4030_CORE is not set
945# CONFIG_MFD_TMIO is not set
946# CONFIG_PMIC_DA903X is not set
947# CONFIG_MFD_WM8400 is not set
948# CONFIG_MFD_WM8350_I2C is not set
949# CONFIG_MFD_PCF50633 is not set
950# CONFIG_REGULATOR is not set
951
952#
953# Multimedia devices
954#
955
956#
957# Multimedia core support
958#
959# CONFIG_VIDEO_DEV is not set
960# CONFIG_DVB_CORE is not set
961# CONFIG_VIDEO_MEDIA is not set
962
963#
964# Multimedia drivers
965#
966# CONFIG_DAB is not set
967
968#
969# Graphics support
970#
971# CONFIG_AGP is not set
972# CONFIG_DRM is not set
973# CONFIG_VGASTATE is not set
974# CONFIG_VIDEO_OUTPUT_CONTROL is not set
975CONFIG_FB=y
976CONFIG_FIRMWARE_EDID=y
977CONFIG_FB_DDC=y
978# CONFIG_FB_BOOT_VESA_SUPPORT is not set
979CONFIG_FB_CFB_FILLRECT=y
980CONFIG_FB_CFB_COPYAREA=y
981CONFIG_FB_CFB_IMAGEBLIT=y
982# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
983# CONFIG_FB_SYS_FILLRECT is not set
984# CONFIG_FB_SYS_COPYAREA is not set
985# CONFIG_FB_SYS_IMAGEBLIT is not set
986# CONFIG_FB_FOREIGN_ENDIAN is not set
987# CONFIG_FB_SYS_FOPS is not set
988# CONFIG_FB_SVGALIB is not set
989CONFIG_FB_MACMODES=y
990CONFIG_FB_BACKLIGHT=y
991CONFIG_FB_MODE_HELPERS=y
992CONFIG_FB_TILEBLITTING=y
993
994#
995# Frame buffer hardware drivers
996#
997# CONFIG_FB_CIRRUS is not set
998# CONFIG_FB_PM2 is not set
999# CONFIG_FB_CYBER2000 is not set
1000# CONFIG_FB_OF is not set
1001# CONFIG_FB_CT65550 is not set
1002# CONFIG_FB_ASILIANT is not set
1003# CONFIG_FB_IMSTT is not set
1004# CONFIG_FB_VGA16 is not set
1005# CONFIG_FB_S1D13XXX is not set
1006# CONFIG_FB_NVIDIA is not set
1007# CONFIG_FB_RIVA is not set
1008# CONFIG_FB_MATROX is not set
1009CONFIG_FB_RADEON=y
1010CONFIG_FB_RADEON_I2C=y
1011CONFIG_FB_RADEON_BACKLIGHT=y
1012# CONFIG_FB_RADEON_DEBUG is not set
1013# CONFIG_FB_ATY128 is not set
1014# CONFIG_FB_ATY is not set
1015# CONFIG_FB_S3 is not set
1016# CONFIG_FB_SAVAGE is not set
1017# CONFIG_FB_SIS is not set
1018# CONFIG_FB_VIA is not set
1019# CONFIG_FB_NEOMAGIC is not set
1020# CONFIG_FB_KYRO is not set
1021CONFIG_FB_3DFX=y
1022# CONFIG_FB_3DFX_ACCEL is not set
1023# CONFIG_FB_VOODOO1 is not set
1024# CONFIG_FB_VT8623 is not set
1025# CONFIG_FB_TRIDENT is not set
1026# CONFIG_FB_ARK is not set
1027# CONFIG_FB_PM3 is not set
1028# CONFIG_FB_CARMINE is not set
1029# CONFIG_FB_IBM_GXT4500 is not set
1030# CONFIG_FB_VIRTUAL is not set
1031# CONFIG_FB_METRONOME is not set
1032# CONFIG_FB_MB862XX is not set
1033CONFIG_BACKLIGHT_LCD_SUPPORT=y
1034CONFIG_LCD_CLASS_DEVICE=m
1035# CONFIG_LCD_ILI9320 is not set
1036# CONFIG_LCD_PLATFORM is not set
1037CONFIG_BACKLIGHT_CLASS_DEVICE=y
1038CONFIG_BACKLIGHT_GENERIC=y
1039
1040#
1041# Display device support
1042#
1043CONFIG_DISPLAY_SUPPORT=m
1044
1045#
1046# Display hardware drivers
1047#
1048
1049#
1050# Console display driver support
1051#
1052CONFIG_VGA_CONSOLE=y
1053# CONFIG_VGACON_SOFT_SCROLLBACK is not set
1054CONFIG_DUMMY_CONSOLE=y
1055CONFIG_FRAMEBUFFER_CONSOLE=y
1056# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
1057# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
1058# CONFIG_FONTS is not set
1059CONFIG_FONT_8x8=y
1060CONFIG_FONT_8x16=y
1061CONFIG_LOGO=y
1062CONFIG_LOGO_LINUX_MONO=y
1063CONFIG_LOGO_LINUX_VGA16=y
1064CONFIG_LOGO_LINUX_CLUT224=y
1065# CONFIG_SOUND is not set
1066CONFIG_HID_SUPPORT=y
1067CONFIG_HID=y
1068# CONFIG_HID_DEBUG is not set
1069# CONFIG_HIDRAW is not set
1070
1071#
1072# USB Input Devices
1073#
1074CONFIG_USB_HID=y
1075# CONFIG_HID_PID is not set
1076# CONFIG_USB_HIDDEV is not set
1077
1078#
1079# Special HID drivers
1080#
1081CONFIG_HID_COMPAT=y
1082CONFIG_HID_A4TECH=y
1083CONFIG_HID_APPLE=y
1084CONFIG_HID_BELKIN=y
1085CONFIG_HID_CHERRY=y
1086CONFIG_HID_CHICONY=y
1087CONFIG_HID_CYPRESS=y
1088CONFIG_HID_EZKEY=y
1089CONFIG_HID_GYRATION=y
1090CONFIG_HID_LOGITECH=y
1091# CONFIG_LOGITECH_FF is not set
1092# CONFIG_LOGIRUMBLEPAD2_FF is not set
1093CONFIG_HID_MICROSOFT=y
1094CONFIG_HID_MONTEREY=y
1095CONFIG_HID_NTRIG=y
1096CONFIG_HID_PANTHERLORD=y
1097# CONFIG_PANTHERLORD_FF is not set
1098CONFIG_HID_PETALYNX=y
1099CONFIG_HID_SAMSUNG=y
1100CONFIG_HID_SONY=y
1101CONFIG_HID_SUNPLUS=y
1102# CONFIG_GREENASIA_FF is not set
1103CONFIG_HID_TOPSEED=y
1104# CONFIG_THRUSTMASTER_FF is not set
1105# CONFIG_ZEROPLUS_FF is not set
1106CONFIG_USB_SUPPORT=y
1107CONFIG_USB_ARCH_HAS_HCD=y
1108CONFIG_USB_ARCH_HAS_OHCI=y
1109CONFIG_USB_ARCH_HAS_EHCI=y
1110CONFIG_USB=y
1111# CONFIG_USB_DEBUG is not set
1112# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1113
1114#
1115# Miscellaneous USB options
1116#
1117CONFIG_USB_DEVICEFS=y
1118CONFIG_USB_DEVICE_CLASS=y
1119# CONFIG_USB_DYNAMIC_MINORS is not set
1120# CONFIG_USB_OTG is not set
1121CONFIG_USB_MON=y
1122# CONFIG_USB_WUSB is not set
1123# CONFIG_USB_WUSB_CBAF is not set
1124
1125#
1126# USB Host Controller Drivers
1127#
1128# CONFIG_USB_C67X00_HCD is not set
1129# CONFIG_USB_EHCI_HCD is not set
1130# CONFIG_USB_OXU210HP_HCD is not set
1131# CONFIG_USB_ISP116X_HCD is not set
1132# CONFIG_USB_ISP1760_HCD is not set
1133CONFIG_USB_OHCI_HCD=y
1134# CONFIG_USB_OHCI_HCD_PPC_OF is not set
1135# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1136# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1137CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1138CONFIG_USB_UHCI_HCD=y
1139# CONFIG_USB_SL811_HCD is not set
1140# CONFIG_USB_R8A66597_HCD is not set
1141# CONFIG_USB_WHCI_HCD is not set
1142# CONFIG_USB_HWA_HCD is not set
1143
1144#
1145# USB Device Class drivers
1146#
1147# CONFIG_USB_ACM is not set
1148# CONFIG_USB_PRINTER is not set
1149# CONFIG_USB_WDM is not set
1150# CONFIG_USB_TMC is not set
1151
1152#
1153# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
1154#
1155
1156#
1157# see USB_STORAGE Help for more information
1158#
1159CONFIG_USB_STORAGE=m
1160# CONFIG_USB_STORAGE_DEBUG is not set
1161# CONFIG_USB_STORAGE_DATAFAB is not set
1162# CONFIG_USB_STORAGE_FREECOM is not set
1163# CONFIG_USB_STORAGE_ISD200 is not set
1164# CONFIG_USB_STORAGE_USBAT is not set
1165# CONFIG_USB_STORAGE_SDDR09 is not set
1166# CONFIG_USB_STORAGE_SDDR55 is not set
1167# CONFIG_USB_STORAGE_JUMPSHOT is not set
1168# CONFIG_USB_STORAGE_ALAUDA is not set
1169# CONFIG_USB_STORAGE_ONETOUCH is not set
1170# CONFIG_USB_STORAGE_KARMA is not set
1171# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1172# CONFIG_USB_LIBUSUAL is not set
1173
1174#
1175# USB Imaging devices
1176#
1177# CONFIG_USB_MDC800 is not set
1178# CONFIG_USB_MICROTEK is not set
1179
1180#
1181# USB port drivers
1182#
1183# CONFIG_USB_USS720 is not set
1184# CONFIG_USB_SERIAL is not set
1185
1186#
1187# USB Miscellaneous drivers
1188#
1189# CONFIG_USB_EMI62 is not set
1190# CONFIG_USB_EMI26 is not set
1191# CONFIG_USB_ADUTUX is not set
1192# CONFIG_USB_SEVSEG is not set
1193# CONFIG_USB_RIO500 is not set
1194# CONFIG_USB_LEGOTOWER is not set
1195# CONFIG_USB_LCD is not set
1196# CONFIG_USB_BERRY_CHARGE is not set
1197# CONFIG_USB_LED is not set
1198# CONFIG_USB_CYPRESS_CY7C63 is not set
1199# CONFIG_USB_CYTHERM is not set
1200# CONFIG_USB_PHIDGET is not set
1201# CONFIG_USB_IDMOUSE is not set
1202# CONFIG_USB_FTDI_ELAN is not set
1203# CONFIG_USB_APPLEDISPLAY is not set
1204# CONFIG_USB_LD is not set
1205# CONFIG_USB_TRANCEVIBRATOR is not set
1206# CONFIG_USB_IOWARRIOR is not set
1207# CONFIG_USB_TEST is not set
1208# CONFIG_USB_ISIGHTFW is not set
1209# CONFIG_USB_VST is not set
1210# CONFIG_USB_GADGET is not set
1211
1212#
1213# OTG and related infrastructure
1214#
1215# CONFIG_UWB is not set
1216# CONFIG_MMC is not set
1217# CONFIG_MEMSTICK is not set
1218# CONFIG_NEW_LEDS is not set
1219# CONFIG_ACCESSIBILITY is not set
1220# CONFIG_INFINIBAND is not set
1221# CONFIG_EDAC is not set
1222CONFIG_RTC_LIB=y
1223CONFIG_RTC_CLASS=y
1224CONFIG_RTC_HCTOSYS=y
1225CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1226# CONFIG_RTC_DEBUG is not set
1227
1228#
1229# RTC interfaces
1230#
1231CONFIG_RTC_INTF_SYSFS=y
1232CONFIG_RTC_INTF_PROC=y
1233CONFIG_RTC_INTF_DEV=y
1234# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1235# CONFIG_RTC_DRV_TEST is not set
1236
1237#
1238# I2C RTC drivers
1239#
1240# CONFIG_RTC_DRV_DS1307 is not set
1241# CONFIG_RTC_DRV_DS1374 is not set
1242# CONFIG_RTC_DRV_DS1672 is not set
1243# CONFIG_RTC_DRV_MAX6900 is not set
1244# CONFIG_RTC_DRV_RS5C372 is not set
1245# CONFIG_RTC_DRV_ISL1208 is not set
1246# CONFIG_RTC_DRV_X1205 is not set
1247# CONFIG_RTC_DRV_PCF8563 is not set
1248# CONFIG_RTC_DRV_PCF8583 is not set
1249# CONFIG_RTC_DRV_M41T80 is not set
1250# CONFIG_RTC_DRV_S35390A is not set
1251# CONFIG_RTC_DRV_FM3130 is not set
1252# CONFIG_RTC_DRV_RX8581 is not set
1253
1254#
1255# SPI RTC drivers
1256#
1257
1258#
1259# Platform RTC drivers
1260#
1261CONFIG_RTC_DRV_CMOS=y
1262# CONFIG_RTC_DRV_DS1286 is not set
1263# CONFIG_RTC_DRV_DS1511 is not set
1264# CONFIG_RTC_DRV_DS1553 is not set
1265# CONFIG_RTC_DRV_DS1742 is not set
1266# CONFIG_RTC_DRV_STK17TA8 is not set
1267# CONFIG_RTC_DRV_M48T86 is not set
1268# CONFIG_RTC_DRV_M48T35 is not set
1269# CONFIG_RTC_DRV_M48T59 is not set
1270# CONFIG_RTC_DRV_BQ4802 is not set
1271# CONFIG_RTC_DRV_V3020 is not set
1272
1273#
1274# on-CPU RTC drivers
1275#
1276# CONFIG_RTC_DRV_PPC is not set
1277# CONFIG_DMADEVICES is not set
1278# CONFIG_AUXDISPLAY is not set
1279# CONFIG_UIO is not set
1280# CONFIG_STAGING is not set
1281
1282#
1283# File systems
1284#
1285CONFIG_EXT2_FS=y
1286# CONFIG_EXT2_FS_XATTR is not set
1287# CONFIG_EXT2_FS_XIP is not set
1288CONFIG_EXT3_FS=y
1289CONFIG_EXT3_FS_XATTR=y
1290# CONFIG_EXT3_FS_POSIX_ACL is not set
1291# CONFIG_EXT3_FS_SECURITY is not set
1292CONFIG_EXT4_FS=y
1293# CONFIG_EXT4DEV_COMPAT is not set
1294CONFIG_EXT4_FS_XATTR=y
1295# CONFIG_EXT4_FS_POSIX_ACL is not set
1296# CONFIG_EXT4_FS_SECURITY is not set
1297CONFIG_JBD=y
1298CONFIG_JBD2=y
1299CONFIG_FS_MBCACHE=y
1300# CONFIG_REISERFS_FS is not set
1301# CONFIG_JFS_FS is not set
1302# CONFIG_FS_POSIX_ACL is not set
1303CONFIG_FILE_LOCKING=y
1304# CONFIG_XFS_FS is not set
1305# CONFIG_GFS2_FS is not set
1306# CONFIG_OCFS2_FS is not set
1307# CONFIG_BTRFS_FS is not set
1308CONFIG_DNOTIFY=y
1309CONFIG_INOTIFY=y
1310CONFIG_INOTIFY_USER=y
1311# CONFIG_QUOTA is not set
1312# CONFIG_AUTOFS_FS is not set
1313# CONFIG_AUTOFS4_FS is not set
1314# CONFIG_FUSE_FS is not set
1315
1316#
1317# CD-ROM/DVD Filesystems
1318#
1319CONFIG_ISO9660_FS=y
1320# CONFIG_JOLIET is not set
1321# CONFIG_ZISOFS is not set
1322# CONFIG_UDF_FS is not set
1323
1324#
1325# DOS/FAT/NT Filesystems
1326#
1327CONFIG_FAT_FS=m
1328CONFIG_MSDOS_FS=m
1329CONFIG_VFAT_FS=m
1330CONFIG_FAT_DEFAULT_CODEPAGE=437
1331CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1332# CONFIG_NTFS_FS is not set
1333
1334#
1335# Pseudo filesystems
1336#
1337CONFIG_PROC_FS=y
1338CONFIG_PROC_KCORE=y
1339CONFIG_PROC_SYSCTL=y
1340CONFIG_PROC_PAGE_MONITOR=y
1341CONFIG_SYSFS=y
1342CONFIG_TMPFS=y
1343# CONFIG_TMPFS_POSIX_ACL is not set
1344# CONFIG_HUGETLB_PAGE is not set
1345# CONFIG_CONFIGFS_FS is not set
1346CONFIG_MISC_FILESYSTEMS=y
1347# CONFIG_ADFS_FS is not set
1348CONFIG_AFFS_FS=m
1349# CONFIG_HFS_FS is not set
1350# CONFIG_HFSPLUS_FS is not set
1351# CONFIG_BEFS_FS is not set
1352# CONFIG_BFS_FS is not set
1353# CONFIG_EFS_FS is not set
1354# CONFIG_CRAMFS is not set
1355# CONFIG_SQUASHFS is not set
1356# CONFIG_VXFS_FS is not set
1357# CONFIG_MINIX_FS is not set
1358# CONFIG_OMFS_FS is not set
1359# CONFIG_HPFS_FS is not set
1360# CONFIG_QNX4FS_FS is not set
1361# CONFIG_ROMFS_FS is not set
1362# CONFIG_SYSV_FS is not set
1363# CONFIG_UFS_FS is not set
1364CONFIG_NETWORK_FILESYSTEMS=y
1365# CONFIG_NFS_FS is not set
1366# CONFIG_NFSD is not set
1367# CONFIG_SMB_FS is not set
1368# CONFIG_CIFS is not set
1369# CONFIG_NCP_FS is not set
1370# CONFIG_CODA_FS is not set
1371# CONFIG_AFS_FS is not set
1372
1373#
1374# Partition Types
1375#
1376CONFIG_PARTITION_ADVANCED=y
1377# CONFIG_ACORN_PARTITION is not set
1378# CONFIG_OSF_PARTITION is not set
1379CONFIG_AMIGA_PARTITION=y
1380# CONFIG_ATARI_PARTITION is not set
1381# CONFIG_MAC_PARTITION is not set
1382CONFIG_MSDOS_PARTITION=y
1383# CONFIG_BSD_DISKLABEL is not set
1384# CONFIG_MINIX_SUBPARTITION is not set
1385# CONFIG_SOLARIS_X86_PARTITION is not set
1386# CONFIG_UNIXWARE_DISKLABEL is not set
1387# CONFIG_LDM_PARTITION is not set
1388# CONFIG_SGI_PARTITION is not set
1389# CONFIG_ULTRIX_PARTITION is not set
1390# CONFIG_SUN_PARTITION is not set
1391# CONFIG_KARMA_PARTITION is not set
1392# CONFIG_EFI_PARTITION is not set
1393# CONFIG_SYSV68_PARTITION is not set
1394CONFIG_NLS=y
1395CONFIG_NLS_DEFAULT="iso8859-1"
1396# CONFIG_NLS_CODEPAGE_437 is not set
1397# CONFIG_NLS_CODEPAGE_737 is not set
1398# CONFIG_NLS_CODEPAGE_775 is not set
1399# CONFIG_NLS_CODEPAGE_850 is not set
1400# CONFIG_NLS_CODEPAGE_852 is not set
1401# CONFIG_NLS_CODEPAGE_855 is not set
1402# CONFIG_NLS_CODEPAGE_857 is not set
1403# CONFIG_NLS_CODEPAGE_860 is not set
1404# CONFIG_NLS_CODEPAGE_861 is not set
1405# CONFIG_NLS_CODEPAGE_862 is not set
1406# CONFIG_NLS_CODEPAGE_863 is not set
1407# CONFIG_NLS_CODEPAGE_864 is not set
1408# CONFIG_NLS_CODEPAGE_865 is not set
1409# CONFIG_NLS_CODEPAGE_866 is not set
1410# CONFIG_NLS_CODEPAGE_869 is not set
1411# CONFIG_NLS_CODEPAGE_936 is not set
1412# CONFIG_NLS_CODEPAGE_950 is not set
1413# CONFIG_NLS_CODEPAGE_932 is not set
1414# CONFIG_NLS_CODEPAGE_949 is not set
1415# CONFIG_NLS_CODEPAGE_874 is not set
1416# CONFIG_NLS_ISO8859_8 is not set
1417# CONFIG_NLS_CODEPAGE_1250 is not set
1418# CONFIG_NLS_CODEPAGE_1251 is not set
1419CONFIG_NLS_ASCII=y
1420CONFIG_NLS_ISO8859_1=m
1421# CONFIG_NLS_ISO8859_2 is not set
1422# CONFIG_NLS_ISO8859_3 is not set
1423# CONFIG_NLS_ISO8859_4 is not set
1424# CONFIG_NLS_ISO8859_5 is not set
1425# CONFIG_NLS_ISO8859_6 is not set
1426# CONFIG_NLS_ISO8859_7 is not set
1427# CONFIG_NLS_ISO8859_9 is not set
1428# CONFIG_NLS_ISO8859_13 is not set
1429# CONFIG_NLS_ISO8859_14 is not set
1430# CONFIG_NLS_ISO8859_15 is not set
1431# CONFIG_NLS_KOI8_R is not set
1432# CONFIG_NLS_KOI8_U is not set
1433# CONFIG_NLS_UTF8 is not set
1434# CONFIG_DLM is not set
1435
1436#
1437# Library routines
1438#
1439CONFIG_BITREVERSE=y
1440CONFIG_GENERIC_FIND_LAST_BIT=y
1441CONFIG_CRC_CCITT=m
1442CONFIG_CRC16=y
1443CONFIG_CRC_T10DIF=y
1444# CONFIG_CRC_ITU_T is not set
1445CONFIG_CRC32=y
1446# CONFIG_CRC7 is not set
1447# CONFIG_LIBCRC32C is not set
1448CONFIG_ZLIB_INFLATE=m
1449CONFIG_ZLIB_DEFLATE=m
1450CONFIG_PLIST=y
1451CONFIG_HAS_IOMEM=y
1452CONFIG_HAS_IOPORT=y
1453CONFIG_HAS_DMA=y
1454CONFIG_HAVE_LMB=y
1455
1456#
1457# Kernel hacking
1458#
1459# CONFIG_PRINTK_TIME is not set
1460CONFIG_ENABLE_WARN_DEPRECATED=y
1461CONFIG_ENABLE_MUST_CHECK=y
1462CONFIG_FRAME_WARN=1024
1463CONFIG_MAGIC_SYSRQ=y
1464# CONFIG_UNUSED_SYMBOLS is not set
1465# CONFIG_DEBUG_FS is not set
1466# CONFIG_HEADERS_CHECK is not set
1467CONFIG_DEBUG_KERNEL=y
1468# CONFIG_DEBUG_SHIRQ is not set
1469CONFIG_DETECT_SOFTLOCKUP=y
1470# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1471CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1472CONFIG_SCHED_DEBUG=y
1473# CONFIG_SCHEDSTATS is not set
1474# CONFIG_TIMER_STATS is not set
1475# CONFIG_DEBUG_OBJECTS is not set
1476# CONFIG_SLUB_DEBUG_ON is not set
1477# CONFIG_SLUB_STATS is not set
1478# CONFIG_DEBUG_RT_MUTEXES is not set
1479# CONFIG_RT_MUTEX_TESTER is not set
1480# CONFIG_DEBUG_SPINLOCK is not set
1481CONFIG_DEBUG_MUTEXES=y
1482CONFIG_DEBUG_SPINLOCK_SLEEP=y
1483# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1484# CONFIG_DEBUG_KOBJECT is not set
1485# CONFIG_DEBUG_HIGHMEM is not set
1486CONFIG_DEBUG_BUGVERBOSE=y
1487# CONFIG_DEBUG_INFO is not set
1488# CONFIG_DEBUG_VM is not set
1489# CONFIG_DEBUG_WRITECOUNT is not set
1490CONFIG_DEBUG_MEMORY_INIT=y
1491# CONFIG_DEBUG_LIST is not set
1492# CONFIG_DEBUG_SG is not set
1493# CONFIG_DEBUG_NOTIFIERS is not set
1494# CONFIG_BOOT_PRINTK_DELAY is not set
1495# CONFIG_RCU_TORTURE_TEST is not set
1496# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1497# CONFIG_BACKTRACE_SELF_TEST is not set
1498# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1499# CONFIG_FAULT_INJECTION is not set
1500# CONFIG_LATENCYTOP is not set
1501CONFIG_SYSCTL_SYSCALL_CHECK=y
1502CONFIG_HAVE_FUNCTION_TRACER=y
1503CONFIG_HAVE_DYNAMIC_FTRACE=y
1504CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1505
1506#
1507# Tracers
1508#
1509# CONFIG_FUNCTION_TRACER is not set
1510# CONFIG_SCHED_TRACER is not set
1511# CONFIG_CONTEXT_SWITCH_TRACER is not set
1512# CONFIG_BOOT_TRACER is not set
1513# CONFIG_TRACE_BRANCH_PROFILING is not set
1514# CONFIG_STACK_TRACER is not set
1515# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1516# CONFIG_SAMPLES is not set
1517CONFIG_HAVE_ARCH_KGDB=y
1518# CONFIG_KGDB is not set
1519CONFIG_PRINT_STACK_DEPTH=64
1520# CONFIG_DEBUG_STACKOVERFLOW is not set
1521# CONFIG_DEBUG_STACK_USAGE is not set
1522# CONFIG_DEBUG_PAGEALLOC is not set
1523# CONFIG_CODE_PATCHING_SELFTEST is not set
1524# CONFIG_FTR_FIXUP_SELFTEST is not set
1525# CONFIG_MSI_BITMAP_SELFTEST is not set
1526CONFIG_XMON=y
1527CONFIG_XMON_DEFAULT=y
1528CONFIG_XMON_DISASSEMBLY=y
1529CONFIG_DEBUGGER=y
1530CONFIG_IRQSTACKS=y
1531# CONFIG_BDI_SWITCH is not set
1532# CONFIG_BOOTX_TEXT is not set
1533# CONFIG_PPC_EARLY_DEBUG is not set
1534
1535#
1536# Security options
1537#
1538# CONFIG_KEYS is not set
1539# CONFIG_SECURITY is not set
1540# CONFIG_SECURITYFS is not set
1541# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1542CONFIG_CRYPTO=y
1543
1544#
1545# Crypto core or helper
1546#
1547# CONFIG_CRYPTO_FIPS is not set
1548CONFIG_CRYPTO_ALGAPI=m
1549CONFIG_CRYPTO_ALGAPI2=m
1550CONFIG_CRYPTO_AEAD2=m
1551CONFIG_CRYPTO_BLKCIPHER=m
1552CONFIG_CRYPTO_BLKCIPHER2=m
1553CONFIG_CRYPTO_HASH=m
1554CONFIG_CRYPTO_HASH2=m
1555CONFIG_CRYPTO_RNG2=m
1556CONFIG_CRYPTO_MANAGER=m
1557CONFIG_CRYPTO_MANAGER2=m
1558# CONFIG_CRYPTO_GF128MUL is not set
1559# CONFIG_CRYPTO_NULL is not set
1560# CONFIG_CRYPTO_CRYPTD is not set
1561# CONFIG_CRYPTO_AUTHENC is not set
1562# CONFIG_CRYPTO_TEST is not set
1563
1564#
1565# Authenticated Encryption with Associated Data
1566#
1567# CONFIG_CRYPTO_CCM is not set
1568# CONFIG_CRYPTO_GCM is not set
1569# CONFIG_CRYPTO_SEQIV is not set
1570
1571#
1572# Block modes
1573#
1574CONFIG_CRYPTO_CBC=m
1575# CONFIG_CRYPTO_CTR is not set
1576# CONFIG_CRYPTO_CTS is not set
1577CONFIG_CRYPTO_ECB=m
1578# CONFIG_CRYPTO_LRW is not set
1579CONFIG_CRYPTO_PCBC=m
1580# CONFIG_CRYPTO_XTS is not set
1581
1582#
1583# Hash modes
1584#
1585# CONFIG_CRYPTO_HMAC is not set
1586# CONFIG_CRYPTO_XCBC is not set
1587
1588#
1589# Digest
1590#
1591# CONFIG_CRYPTO_CRC32C is not set
1592# CONFIG_CRYPTO_MD4 is not set
1593# CONFIG_CRYPTO_MD5 is not set
1594# CONFIG_CRYPTO_MICHAEL_MIC is not set
1595# CONFIG_CRYPTO_RMD128 is not set
1596# CONFIG_CRYPTO_RMD160 is not set
1597# CONFIG_CRYPTO_RMD256 is not set
1598# CONFIG_CRYPTO_RMD320 is not set
1599CONFIG_CRYPTO_SHA1=m
1600# CONFIG_CRYPTO_SHA256 is not set
1601# CONFIG_CRYPTO_SHA512 is not set
1602# CONFIG_CRYPTO_TGR192 is not set
1603# CONFIG_CRYPTO_WP512 is not set
1604
1605#
1606# Ciphers
1607#
1608# CONFIG_CRYPTO_AES is not set
1609# CONFIG_CRYPTO_ANUBIS is not set
1610CONFIG_CRYPTO_ARC4=m
1611# CONFIG_CRYPTO_BLOWFISH is not set
1612# CONFIG_CRYPTO_CAMELLIA is not set
1613# CONFIG_CRYPTO_CAST5 is not set
1614# CONFIG_CRYPTO_CAST6 is not set
1615# CONFIG_CRYPTO_DES is not set
1616# CONFIG_CRYPTO_FCRYPT is not set
1617# CONFIG_CRYPTO_KHAZAD is not set
1618# CONFIG_CRYPTO_SALSA20 is not set
1619# CONFIG_CRYPTO_SEED is not set
1620# CONFIG_CRYPTO_SERPENT is not set
1621# CONFIG_CRYPTO_TEA is not set
1622# CONFIG_CRYPTO_TWOFISH is not set
1623
1624#
1625# Compression
1626#
1627# CONFIG_CRYPTO_DEFLATE is not set
1628# CONFIG_CRYPTO_LZO is not set
1629
1630#
1631# Random Number Generation
1632#
1633# CONFIG_CRYPTO_ANSI_CPRNG is not set
1634# CONFIG_CRYPTO_HW is not set
1635# CONFIG_PPC_CLOCK is not set
1636# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/include/asm/highmem.h b/arch/powerpc/include/asm/highmem.h
index 04e4a620952e..a286e47100b5 100644
--- a/arch/powerpc/include/asm/highmem.h
+++ b/arch/powerpc/include/asm/highmem.h
@@ -99,7 +99,7 @@ static inline void *kmap_atomic_prot(struct page *page, enum km_type type, pgpro
99#ifdef CONFIG_DEBUG_HIGHMEM 99#ifdef CONFIG_DEBUG_HIGHMEM
100 BUG_ON(!pte_none(*(kmap_pte-idx))); 100 BUG_ON(!pte_none(*(kmap_pte-idx)));
101#endif 101#endif
102 __set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot)); 102 __set_pte_at(&init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot), 1);
103 local_flush_tlb_page(NULL, vaddr); 103 local_flush_tlb_page(NULL, vaddr);
104 104
105 return (void*) vaddr; 105 return (void*) vaddr;
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 2740c44ff717..6c34a0df82fd 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -327,8 +327,6 @@ extern void __devinit smp_generic_take_timebase(void);
327 */ 327 */
328/* Print a boot progress message. */ 328/* Print a boot progress message. */
329void ppc64_boot_msg(unsigned int src, const char *msg); 329void ppc64_boot_msg(unsigned int src, const char *msg);
330/* Print a termination message (print only -- does not stop the kernel) */
331void ppc64_terminate_msg(unsigned int src, const char *msg);
332 330
333static inline void log_error(char *buf, unsigned int err_type, int fatal) 331static inline void log_error(char *buf, unsigned int err_type, int fatal)
334{ 332{
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index 820b5f0a35ce..98bd7c5fcd0e 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -429,10 +429,11 @@ extern int icache_44x_need_flush;
429#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE() 429#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
430#endif 430#endif
431 431
432#define _PAGE_HPTEFLAGS _PAGE_HASHPTE
433
432#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \ 434#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
433 _PAGE_SPECIAL) 435 _PAGE_SPECIAL)
434 436
435
436#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \ 437#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
437 _PAGE_WRITETHRU | _PAGE_ENDIAN | \ 438 _PAGE_WRITETHRU | _PAGE_ENDIAN | \
438 _PAGE_USER | _PAGE_ACCESSED | \ 439 _PAGE_USER | _PAGE_ACCESSED | \
@@ -668,44 +669,6 @@ static inline unsigned long long pte_update(pte_t *p,
668#endif /* CONFIG_PTE_64BIT */ 669#endif /* CONFIG_PTE_64BIT */
669 670
670/* 671/*
671 * set_pte stores a linux PTE into the linux page table.
672 * On machines which use an MMU hash table we avoid changing the
673 * _PAGE_HASHPTE bit.
674 */
675
676static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
677 pte_t *ptep, pte_t pte)
678{
679#if (_PAGE_HASHPTE != 0) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
680 pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
681#elif defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)
682#if _PAGE_HASHPTE != 0
683 if (pte_val(*ptep) & _PAGE_HASHPTE)
684 flush_hash_entry(mm, ptep, addr);
685#endif
686 __asm__ __volatile__("\
687 stw%U0%X0 %2,%0\n\
688 eieio\n\
689 stw%U0%X0 %L2,%1"
690 : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
691 : "r" (pte) : "memory");
692#else
693 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
694 | (pte_val(pte) & ~_PAGE_HASHPTE));
695#endif
696}
697
698
699static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
700 pte_t *ptep, pte_t pte)
701{
702#if defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP) && defined(CONFIG_DEBUG_VM)
703 WARN_ON(pte_present(*ptep));
704#endif
705 __set_pte_at(mm, addr, ptep, pte);
706}
707
708/*
709 * 2.6 calls this without flushing the TLB entry; this is wrong 672 * 2.6 calls this without flushing the TLB entry; this is wrong
710 * for our hash-based implementation, we fix that up here. 673 * for our hash-based implementation, we fix that up here.
711 */ 674 */
@@ -745,24 +708,14 @@ static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
745} 708}
746 709
747 710
748#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 711static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
749static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
750{ 712{
751 unsigned long bits = pte_val(entry) & 713 unsigned long bits = pte_val(entry) &
752 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW); 714 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW |
715 _PAGE_HWEXEC | _PAGE_EXEC);
753 pte_update(ptep, 0, bits); 716 pte_update(ptep, 0, bits);
754} 717}
755 718
756#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
757({ \
758 int __changed = !pte_same(*(__ptep), __entry); \
759 if (__changed) { \
760 __ptep_set_access_flags(__ptep, __entry, __dirty); \
761 flush_tlb_page_nohash(__vma, __address); \
762 } \
763 __changed; \
764})
765
766#define __HAVE_ARCH_PTE_SAME 719#define __HAVE_ARCH_PTE_SAME
767#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0) 720#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
768 721
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index b0f18be81d9f..c627877fcf16 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -125,6 +125,8 @@
125#define _PTEIDX_SECONDARY 0x8 125#define _PTEIDX_SECONDARY 0x8
126#define _PTEIDX_GROUP_IX 0x7 126#define _PTEIDX_GROUP_IX 0x7
127 127
128/* To make some generic powerpc code happy */
129#define _PAGE_HWEXEC 0
128 130
129/* 131/*
130 * POWER4 and newer have per page execute protection, older chips can only 132 * POWER4 and newer have per page execute protection, older chips can only
@@ -285,6 +287,10 @@ static inline unsigned long pte_update(struct mm_struct *mm,
285 : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY) 287 : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
286 : "cc" ); 288 : "cc" );
287 289
290 /* huge pages use the old page table lock */
291 if (!huge)
292 assert_pte_locked(mm, addr);
293
288 if (old & _PAGE_HASHPTE) 294 if (old & _PAGE_HASHPTE)
289 hpte_need_flush(mm, addr, ptep, old, huge); 295 hpte_need_flush(mm, addr, ptep, old, huge);
290 return old; 296 return old;
@@ -359,23 +365,11 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
359 pte_update(mm, addr, ptep, ~0UL, 0); 365 pte_update(mm, addr, ptep, ~0UL, 0);
360} 366}
361 367
362/*
363 * set_pte stores a linux PTE into the linux page table.
364 */
365static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
366 pte_t *ptep, pte_t pte)
367{
368 if (pte_present(*ptep))
369 pte_clear(mm, addr, ptep);
370 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
371 *ptep = pte;
372}
373 368
374/* Set the dirty and/or accessed bits atomically in a linux PTE, this 369/* Set the dirty and/or accessed bits atomically in a linux PTE, this
375 * function doesn't need to flush the hash entry 370 * function doesn't need to flush the hash entry
376 */ 371 */
377#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 372static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
378static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
379{ 373{
380 unsigned long bits = pte_val(entry) & 374 unsigned long bits = pte_val(entry) &
381 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); 375 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
@@ -392,15 +386,6 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
392 :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY) 386 :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
393 :"cc"); 387 :"cc");
394} 388}
395#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
396({ \
397 int __changed = !pte_same(*(__ptep), __entry); \
398 if (__changed) { \
399 __ptep_set_access_flags(__ptep, __entry, __dirty); \
400 flush_tlb_page_nohash(__vma, __address); \
401 } \
402 __changed; \
403})
404 389
405#define __HAVE_ARCH_PTE_SAME 390#define __HAVE_ARCH_PTE_SAME
406#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0) 391#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 07f55e601696..5c1c4880723c 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -6,7 +6,17 @@
6#include <asm/processor.h> /* For TASK_SIZE */ 6#include <asm/processor.h> /* For TASK_SIZE */
7#include <asm/mmu.h> 7#include <asm/mmu.h>
8#include <asm/page.h> 8#include <asm/page.h>
9
9struct mm_struct; 10struct mm_struct;
11
12#ifdef CONFIG_DEBUG_VM
13extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
14#else /* CONFIG_DEBUG_VM */
15static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
16{
17}
18#endif /* !CONFIG_DEBUG_VM */
19
10#endif /* !__ASSEMBLY__ */ 20#endif /* !__ASSEMBLY__ */
11 21
12#if defined(CONFIG_PPC64) 22#if defined(CONFIG_PPC64)
@@ -17,6 +27,80 @@ struct mm_struct;
17 27
18#ifndef __ASSEMBLY__ 28#ifndef __ASSEMBLY__
19 29
30/* Insert a PTE, top-level function is out of line. It uses an inline
31 * low level function in the respective pgtable-* files
32 */
33extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
34 pte_t pte);
35
36/* This low level function performs the actual PTE insertion
37 * Setting the PTE depends on the MMU type and other factors. It's
38 * an horrible mess that I'm not going to try to clean up now but
39 * I'm keeping it in one place rather than spread around
40 */
41static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
42 pte_t *ptep, pte_t pte, int percpu)
43{
44#if defined(CONFIG_PPC_STD_MMU_32) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
45 /* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
46 * helper pte_update() which does an atomic update. We need to do that
47 * because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
48 * per-CPU PTE such as a kmap_atomic, we do a simple update preserving
49 * the hash bits instead (ie, same as the non-SMP case)
50 */
51 if (percpu)
52 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
53 | (pte_val(pte) & ~_PAGE_HASHPTE));
54 else
55 pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
56
57#elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)
58 /* Second case is 32-bit with 64-bit PTE in SMP mode. In this case, we
59 * can just store as long as we do the two halves in the right order
60 * with a barrier in between. This is possible because we take care,
61 * in the hash code, to pre-invalidate if the PTE was already hashed,
62 * which synchronizes us with any concurrent invalidation.
63 * In the percpu case, we also fallback to the simple update preserving
64 * the hash bits
65 */
66 if (percpu) {
67 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
68 | (pte_val(pte) & ~_PAGE_HASHPTE));
69 return;
70 }
71#if _PAGE_HASHPTE != 0
72 if (pte_val(*ptep) & _PAGE_HASHPTE)
73 flush_hash_entry(mm, ptep, addr);
74#endif
75 __asm__ __volatile__("\
76 stw%U0%X0 %2,%0\n\
77 eieio\n\
78 stw%U0%X0 %L2,%1"
79 : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
80 : "r" (pte) : "memory");
81
82#elif defined(CONFIG_PPC_STD_MMU_32)
83 /* Third case is 32-bit hash table in UP mode, we need to preserve
84 * the _PAGE_HASHPTE bit since we may not have invalidated the previous
85 * translation in the hash yet (done in a subsequent flush_tlb_xxx())
86 * and see we need to keep track that this PTE needs invalidating
87 */
88 *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
89 | (pte_val(pte) & ~_PAGE_HASHPTE));
90
91#else
92 /* Anything else just stores the PTE normally. That covers all 64-bit
93 * cases, and 32-bit non-hash with 64-bit PTEs in UP mode
94 */
95 *ptep = pte;
96#endif
97}
98
99
100#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
101extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
102 pte_t *ptep, pte_t entry, int dirty);
103
20/* 104/*
21 * Macro to mark a page protection value as "uncacheable". 105 * Macro to mark a page protection value as "uncacheable".
22 */ 106 */
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 67453766bff1..597debe780bd 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -110,6 +110,7 @@
110#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ 110#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
111#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ 111#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
112#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */ 112#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */
113#define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */
113#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ 114#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
114#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */ 115#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
115#define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */ 116#define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 8d1a419df35d..d15992119085 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o \
61obj64-$(CONFIG_HIBERNATION) += swsusp_asm64.o 61obj64-$(CONFIG_HIBERNATION) += swsusp_asm64.o
62obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o 62obj-$(CONFIG_MODULES) += module.o module_$(CONFIG_WORD_SIZE).o
63obj-$(CONFIG_44x) += cpu_setup_44x.o 63obj-$(CONFIG_44x) += cpu_setup_44x.o
64obj-$(CONFIG_FSL_BOOKE) += cpu_setup_fsl_booke.o
64 65
65extra-$(CONFIG_PPC_STD_MMU) := head_32.o 66extra-$(CONFIG_PPC_STD_MMU) := head_32.o
66extra-$(CONFIG_PPC64) := head_64.o 67extra-$(CONFIG_PPC64) := head_64.o
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
new file mode 100644
index 000000000000..eb4b9adcedb4
--- /dev/null
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -0,0 +1,31 @@
1/*
2 * This file contains low level CPU setup functions.
3 * Kumar Gala <galak@kernel.crashing.org>
4 * Copyright 2009 Freescale Semiconductor, Inc.
5 *
6 * Based on cpu_setup_6xx code by
7 * Benjamin Herrenschmidt <benh@kernel.crashing.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 */
15
16#include <asm/processor.h>
17#include <asm/cputable.h>
18#include <asm/ppc_asm.h>
19
20_GLOBAL(__setup_cpu_e200)
21 /* enable dedicated debug exception handling resources (Debug APU) */
22 mfspr r3,SPRN_HID0
23 ori r3,r3,HID0_DAPUEN@l
24 mtspr SPRN_HID0,r3
25 b __setup_e200_ivors
26_GLOBAL(__setup_cpu_e500v1)
27_GLOBAL(__setup_cpu_e500v2)
28 b __setup_e500_ivors
29_GLOBAL(__setup_cpu_e500mc)
30 b __setup_e500mc_ivors
31
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 923f87aff20a..9fdf1b8027b5 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -35,6 +35,10 @@ const char *powerpc_base_platform;
35 * and ppc64 35 * and ppc64
36 */ 36 */
37#ifdef CONFIG_PPC32 37#ifdef CONFIG_PPC32
38extern void __setup_cpu_e200(unsigned long offset, struct cpu_spec* spec);
39extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec);
40extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec);
41extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec);
38extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec); 42extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
39extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec); 43extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
40extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec); 44extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
@@ -1687,6 +1691,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
1687 PPC_FEATURE_UNIFIED_CACHE, 1691 PPC_FEATURE_UNIFIED_CACHE,
1688 .mmu_features = MMU_FTR_TYPE_FSL_E, 1692 .mmu_features = MMU_FTR_TYPE_FSL_E,
1689 .dcache_bsize = 32, 1693 .dcache_bsize = 32,
1694 .cpu_setup = __setup_cpu_e200,
1690 .machine_check = machine_check_e200, 1695 .machine_check = machine_check_e200,
1691 .platform = "ppc5554", 1696 .platform = "ppc5554",
1692 } 1697 }
@@ -1706,6 +1711,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
1706 .num_pmcs = 4, 1711 .num_pmcs = 4,
1707 .oprofile_cpu_type = "ppc/e500", 1712 .oprofile_cpu_type = "ppc/e500",
1708 .oprofile_type = PPC_OPROFILE_FSL_EMB, 1713 .oprofile_type = PPC_OPROFILE_FSL_EMB,
1714 .cpu_setup = __setup_cpu_e500v1,
1709 .machine_check = machine_check_e500, 1715 .machine_check = machine_check_e500,
1710 .platform = "ppc8540", 1716 .platform = "ppc8540",
1711 }, 1717 },
@@ -1724,6 +1730,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
1724 .num_pmcs = 4, 1730 .num_pmcs = 4,
1725 .oprofile_cpu_type = "ppc/e500", 1731 .oprofile_cpu_type = "ppc/e500",
1726 .oprofile_type = PPC_OPROFILE_FSL_EMB, 1732 .oprofile_type = PPC_OPROFILE_FSL_EMB,
1733 .cpu_setup = __setup_cpu_e500v2,
1727 .machine_check = machine_check_e500, 1734 .machine_check = machine_check_e500,
1728 .platform = "ppc8548", 1735 .platform = "ppc8548",
1729 }, 1736 },
@@ -1739,6 +1746,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
1739 .num_pmcs = 4, 1746 .num_pmcs = 4,
1740 .oprofile_cpu_type = "ppc/e500", /* xxx - galak, e500mc? */ 1747 .oprofile_cpu_type = "ppc/e500", /* xxx - galak, e500mc? */
1741 .oprofile_type = PPC_OPROFILE_FSL_EMB, 1748 .oprofile_type = PPC_OPROFILE_FSL_EMB,
1749 .cpu_setup = __setup_cpu_e500mc,
1742 .machine_check = machine_check_e500, 1750 .machine_check = machine_check_e500,
1743 .platform = "ppce500mc", 1751 .platform = "ppce500mc",
1744 }, 1752 },
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index fce2df988504..bec18078239d 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -70,10 +70,10 @@
70 70
71/* only on e500mc/e200 */ 71/* only on e500mc/e200 */
72#define DEBUG_STACK_BASE dbgirq_ctx 72#define DEBUG_STACK_BASE dbgirq_ctx
73#ifdef CONFIG_PPC_E500MC 73#ifdef CONFIG_E200
74#define DEBUG_SPRG SPRN_SPRG9
75#else
76#define DEBUG_SPRG SPRN_SPRG6W 74#define DEBUG_SPRG SPRN_SPRG6W
75#else
76#define DEBUG_SPRG SPRN_SPRG9
77#endif 77#endif
78 78
79#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE) 79#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 36ffb3504a4f..64ecb1603a77 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -103,10 +103,15 @@ invstr: mflr r6 /* Make it accessible */
103 or r7,r7,r4 103 or r7,r7,r4
104 mtspr SPRN_MAS6,r7 104 mtspr SPRN_MAS6,r7
105 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */ 105 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
106#ifndef CONFIG_E200
107 mfspr r7,SPRN_MAS1 106 mfspr r7,SPRN_MAS1
108 andis. r7,r7,MAS1_VALID@h 107 andis. r7,r7,MAS1_VALID@h
109 bne match_TLB 108 bne match_TLB
109
110 mfspr r7,SPRN_MMUCFG
111 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
112 cmpwi r7,3
113 bne match_TLB /* skip if NPIDS != 3 */
114
110 mfspr r7,SPRN_PID1 115 mfspr r7,SPRN_PID1
111 slwi r7,r7,16 116 slwi r7,r7,16
112 or r7,r7,r4 117 or r7,r7,r4
@@ -120,7 +125,7 @@ invstr: mflr r6 /* Make it accessible */
120 or r7,r7,r4 125 or r7,r7,r4
121 mtspr SPRN_MAS6,r7 126 mtspr SPRN_MAS6,r7
122 tlbsx 0,r6 /* Fall through, we had to match */ 127 tlbsx 0,r6 /* Fall through, we had to match */
123#endif 128
124match_TLB: 129match_TLB:
125 mfspr r7,SPRN_MAS0 130 mfspr r7,SPRN_MAS0
126 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */ 131 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
@@ -215,14 +220,19 @@ skpinv: addi r6,r6,1 /* Increment */
215 220
216/* 4. Clear out PIDs & Search info */ 221/* 4. Clear out PIDs & Search info */
217 li r6,0 222 li r6,0
223 mtspr SPRN_MAS6,r6
218 mtspr SPRN_PID0,r6 224 mtspr SPRN_PID0,r6
219#ifndef CONFIG_E200 225
226 mfspr r7,SPRN_MMUCFG
227 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
228 cmpwi r7,3
229 bne 2f /* skip if NPIDS != 3 */
230
220 mtspr SPRN_PID1,r6 231 mtspr SPRN_PID1,r6
221 mtspr SPRN_PID2,r6 232 mtspr SPRN_PID2,r6
222#endif
223 mtspr SPRN_MAS6,r6
224 233
225/* 5. Invalidate mapping we started in */ 234/* 5. Invalidate mapping we started in */
2352:
226 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ 236 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
227 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 237 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
228 mtspr SPRN_MAS0,r7 238 mtspr SPRN_MAS0,r7
@@ -298,19 +308,7 @@ skpinv: addi r6,r6,1 /* Increment */
298 SET_IVOR(12, WatchdogTimer); 308 SET_IVOR(12, WatchdogTimer);
299 SET_IVOR(13, DataTLBError); 309 SET_IVOR(13, DataTLBError);
300 SET_IVOR(14, InstructionTLBError); 310 SET_IVOR(14, InstructionTLBError);
301 SET_IVOR(15, DebugDebug);
302#if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
303 SET_IVOR(15, DebugCrit); 311 SET_IVOR(15, DebugCrit);
304#endif
305 SET_IVOR(32, SPEUnavailable);
306 SET_IVOR(33, SPEFloatingPointData);
307 SET_IVOR(34, SPEFloatingPointRound);
308#ifndef CONFIG_E200
309 SET_IVOR(35, PerformanceMonitor);
310#endif
311#ifdef CONFIG_PPC_E500MC
312 SET_IVOR(36, Doorbell);
313#endif
314 312
315 /* Establish the interrupt vector base */ 313 /* Establish the interrupt vector base */
316 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ 314 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
@@ -329,12 +327,6 @@ skpinv: addi r6,r6,1 /* Increment */
329 oris r2,r2,HID0_DOZE@h 327 oris r2,r2,HID0_DOZE@h
330 mtspr SPRN_HID0, r2 328 mtspr SPRN_HID0, r2
331#endif 329#endif
332#ifdef CONFIG_E200
333 /* enable dedicated debug exception handling resources (Debug APU) */
334 mfspr r2,SPRN_HID0
335 ori r2,r2,HID0_DAPUEN@l
336 mtspr SPRN_HID0,r2
337#endif
338 330
339#if !defined(CONFIG_BDI_SWITCH) 331#if !defined(CONFIG_BDI_SWITCH)
340 /* 332 /*
@@ -706,15 +698,11 @@ interrupt_base:
706 /* Performance Monitor */ 698 /* Performance Monitor */
707 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD) 699 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
708 700
709#ifdef CONFIG_PPC_E500MC
710 EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_STD) 701 EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_STD)
711#endif
712 702
713 /* Debug Interrupt */ 703 /* Debug Interrupt */
714 DEBUG_DEBUG_EXCEPTION 704 DEBUG_DEBUG_EXCEPTION
715#if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
716 DEBUG_CRIT_EXCEPTION 705 DEBUG_CRIT_EXCEPTION
717#endif
718 706
719/* 707/*
720 * Local functions 708 * Local functions
@@ -897,6 +885,45 @@ KernelSPE:
897 * Global functions 885 * Global functions
898 */ 886 */
899 887
888/* Adjust or setup IVORs for e200 */
889_GLOBAL(__setup_e200_ivors)
890 li r3,DebugDebug@l
891 mtspr SPRN_IVOR15,r3
892 li r3,SPEUnavailable@l
893 mtspr SPRN_IVOR32,r3
894 li r3,SPEFloatingPointData@l
895 mtspr SPRN_IVOR33,r3
896 li r3,SPEFloatingPointRound@l
897 mtspr SPRN_IVOR34,r3
898 sync
899 blr
900
901/* Adjust or setup IVORs for e500v1/v2 */
902_GLOBAL(__setup_e500_ivors)
903 li r3,DebugCrit@l
904 mtspr SPRN_IVOR15,r3
905 li r3,SPEUnavailable@l
906 mtspr SPRN_IVOR32,r3
907 li r3,SPEFloatingPointData@l
908 mtspr SPRN_IVOR33,r3
909 li r3,SPEFloatingPointRound@l
910 mtspr SPRN_IVOR34,r3
911 li r3,PerformanceMonitor@l
912 mtspr SPRN_IVOR35,r3
913 sync
914 blr
915
916/* Adjust or setup IVORs for e500mc */
917_GLOBAL(__setup_e500mc_ivors)
918 li r3,DebugDebug@l
919 mtspr SPRN_IVOR15,r3
920 li r3,PerformanceMonitor@l
921 mtspr SPRN_IVOR35,r3
922 li r3,Doorbell@l
923 mtspr SPRN_IVOR36,r3
924 sync
925 blr
926
900/* 927/*
901 * extern void loadcam_entry(unsigned int index) 928 * extern void loadcam_entry(unsigned int index)
902 * 929 *
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 0f4181272311..2ad17315fc88 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -38,6 +38,7 @@
38#include <asm/eeh.h> 38#include <asm/eeh.h>
39 39
40static DEFINE_SPINLOCK(hose_spinlock); 40static DEFINE_SPINLOCK(hose_spinlock);
41LIST_HEAD(hose_list);
41 42
42/* XXX kill that some day ... */ 43/* XXX kill that some day ... */
43static int global_phb_number; /* Global phb counter */ 44static int global_phb_number; /* Global phb counter */
@@ -113,19 +114,24 @@ void pcibios_free_controller(struct pci_controller *phb)
113 kfree(phb); 114 kfree(phb);
114} 115}
115 116
117static resource_size_t pcibios_io_size(const struct pci_controller *hose)
118{
119#ifdef CONFIG_PPC64
120 return hose->pci_io_size;
121#else
122 return hose->io_resource.end - hose->io_resource.start + 1;
123#endif
124}
125
116int pcibios_vaddr_is_ioport(void __iomem *address) 126int pcibios_vaddr_is_ioport(void __iomem *address)
117{ 127{
118 int ret = 0; 128 int ret = 0;
119 struct pci_controller *hose; 129 struct pci_controller *hose;
120 unsigned long size; 130 resource_size_t size;
121 131
122 spin_lock(&hose_spinlock); 132 spin_lock(&hose_spinlock);
123 list_for_each_entry(hose, &hose_list, list_node) { 133 list_for_each_entry(hose, &hose_list, list_node) {
124#ifdef CONFIG_PPC64 134 size = pcibios_io_size(hose);
125 size = hose->pci_io_size;
126#else
127 size = hose->io_resource.end - hose->io_resource.start + 1;
128#endif
129 if (address >= hose->io_base_virt && 135 if (address >= hose->io_base_virt &&
130 address < (hose->io_base_virt + size)) { 136 address < (hose->io_base_virt + size)) {
131 ret = 1; 137 ret = 1;
@@ -136,6 +142,29 @@ int pcibios_vaddr_is_ioport(void __iomem *address)
136 return ret; 142 return ret;
137} 143}
138 144
145unsigned long pci_address_to_pio(phys_addr_t address)
146{
147 struct pci_controller *hose;
148 resource_size_t size;
149 unsigned long ret = ~0;
150
151 spin_lock(&hose_spinlock);
152 list_for_each_entry(hose, &hose_list, list_node) {
153 size = pcibios_io_size(hose);
154 if (address >= hose->io_base_phys &&
155 address < (hose->io_base_phys + size)) {
156 unsigned long base =
157 (unsigned long)hose->io_base_virt - _IO_BASE;
158 ret = base + (address - hose->io_base_phys);
159 break;
160 }
161 }
162 spin_unlock(&hose_spinlock);
163
164 return ret;
165}
166EXPORT_SYMBOL_GPL(pci_address_to_pio);
167
139/* 168/*
140 * Return the domain number for this bus. 169 * Return the domain number for this bus.
141 */ 170 */
diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c
index 132cd80afa21..c6368506455f 100644
--- a/arch/powerpc/kernel/pci_32.c
+++ b/arch/powerpc/kernel/pci_32.c
@@ -20,6 +20,7 @@
20#include <asm/prom.h> 20#include <asm/prom.h>
21#include <asm/sections.h> 21#include <asm/sections.h>
22#include <asm/pci-bridge.h> 22#include <asm/pci-bridge.h>
23#include <asm/ppc-pci.h>
23#include <asm/byteorder.h> 24#include <asm/byteorder.h>
24#include <asm/uaccess.h> 25#include <asm/uaccess.h>
25#include <asm/machdep.h> 26#include <asm/machdep.h>
@@ -43,8 +44,6 @@ static u8* pci_to_OF_bus_map;
43 */ 44 */
44static int pci_assign_all_buses; 45static int pci_assign_all_buses;
45 46
46LIST_HEAD(hose_list);
47
48static int pci_bus_count; 47static int pci_bus_count;
49 48
50/* This will remain NULL for now, until isa-bridge.c is made common 49/* This will remain NULL for now, until isa-bridge.c is made common
@@ -491,24 +490,6 @@ long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
491 return result; 490 return result;
492} 491}
493 492
494unsigned long pci_address_to_pio(phys_addr_t address)
495{
496 struct pci_controller *hose, *tmp;
497
498 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
499 unsigned int size = hose->io_resource.end -
500 hose->io_resource.start + 1;
501 if (address >= hose->io_base_phys &&
502 address < (hose->io_base_phys + size)) {
503 unsigned long base =
504 (unsigned long)hose->io_base_virt - _IO_BASE;
505 return base + (address - hose->io_base_phys);
506 }
507 }
508 return (unsigned int)-1;
509}
510EXPORT_SYMBOL(pci_address_to_pio);
511
512/* 493/*
513 * Null PCI config access functions, for the case when we can't 494 * Null PCI config access functions, for the case when we can't
514 * find a hose. 495 * find a hose.
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index ea8eda8c87cf..be574fc0d92f 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -43,8 +43,6 @@ unsigned long pci_probe_only = 1;
43unsigned long pci_io_base = ISA_IO_BASE; 43unsigned long pci_io_base = ISA_IO_BASE;
44EXPORT_SYMBOL(pci_io_base); 44EXPORT_SYMBOL(pci_io_base);
45 45
46LIST_HEAD(hose_list);
47
48static void fixup_broken_pcnet32(struct pci_dev* dev) 46static void fixup_broken_pcnet32(struct pci_dev* dev)
49{ 47{
50 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) { 48 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
@@ -524,23 +522,6 @@ int __devinit pcibios_map_io_space(struct pci_bus *bus)
524} 522}
525EXPORT_SYMBOL_GPL(pcibios_map_io_space); 523EXPORT_SYMBOL_GPL(pcibios_map_io_space);
526 524
527unsigned long pci_address_to_pio(phys_addr_t address)
528{
529 struct pci_controller *hose, *tmp;
530
531 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
532 if (address >= hose->io_base_phys &&
533 address < (hose->io_base_phys + hose->pci_io_size)) {
534 unsigned long base =
535 (unsigned long)hose->io_base_virt - _IO_BASE;
536 return base + (address - hose->io_base_phys);
537 }
538 }
539 return (unsigned int)-1;
540}
541EXPORT_SYMBOL_GPL(pci_address_to_pio);
542
543
544#define IOBASE_BRIDGE_NUMBER 0 525#define IOBASE_BRIDGE_NUMBER 0
545#define IOBASE_MEMORY 1 526#define IOBASE_MEMORY 1
546#define IOBASE_IO 2 527#define IOBASE_IO 2
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index f00f83109ab3..5ec6a9e23933 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -1075,11 +1075,6 @@ static void __init early_reserve_mem(void)
1075 DBG("reserving: %llx -> %llx\n", base, size); 1075 DBG("reserving: %llx -> %llx\n", base, size);
1076 lmb_reserve(base, size); 1076 lmb_reserve(base, size);
1077 } 1077 }
1078
1079#if 0
1080 DBG("memory reserved, lmbs :\n");
1081 lmb_dump_all();
1082#endif
1083} 1078}
1084 1079
1085#ifdef CONFIG_PHYP_DUMP 1080#ifdef CONFIG_PHYP_DUMP
@@ -1221,6 +1216,7 @@ void __init early_init_devtree(void *params)
1221 lmb_enforce_memory_limit(limit); 1216 lmb_enforce_memory_limit(limit);
1222 1217
1223 lmb_analyze(); 1218 lmb_analyze();
1219 lmb_dump_all();
1224 1220
1225 DBG("Phys. mem: %lx\n", lmb_phys_mem_size()); 1221 DBG("Phys. mem: %lx\n", lmb_phys_mem_size());
1226 1222
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 2d34196bba8c..73e16e298e28 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -578,13 +578,6 @@ void ppc64_boot_msg(unsigned int src, const char *msg)
578 printk("[boot]%04x %s\n", src, msg); 578 printk("[boot]%04x %s\n", src, msg);
579} 579}
580 580
581/* Print a termination message (print only -- does not stop the kernel) */
582void ppc64_terminate_msg(unsigned int src, const char *msg)
583{
584 ppc64_do_msg(PPC64_LINUX_FUNCTION|PPC64_TERM_MESSAGE|src, msg);
585 printk("[terminate]%04x %s\n", src, msg);
586}
587
588void cpu_die(void) 581void cpu_die(void)
589{ 582{
590 if (ppc_md.cpu_die) 583 if (ppc_md.cpu_die)
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index 91c7b8636b8a..76993941cac9 100644
--- a/arch/powerpc/mm/fault.c
+++ b/arch/powerpc/mm/fault.c
@@ -253,45 +253,33 @@ good_area:
253#endif /* CONFIG_8xx */ 253#endif /* CONFIG_8xx */
254 254
255 if (is_exec) { 255 if (is_exec) {
256#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) 256#ifdef CONFIG_PPC_STD_MMU
257 /* protection fault */ 257 /* Protection fault on exec go straight to failure on
258 * Hash based MMUs as they either don't support per-page
259 * execute permission, or if they do, it's handled already
260 * at the hash level. This test would probably have to
261 * be removed if we change the way this works to make hash
262 * processors use the same I/D cache coherency mechanism
263 * as embedded.
264 */
258 if (error_code & DSISR_PROTFAULT) 265 if (error_code & DSISR_PROTFAULT)
259 goto bad_area; 266 goto bad_area;
267#endif /* CONFIG_PPC_STD_MMU */
268
260 /* 269 /*
261 * Allow execution from readable areas if the MMU does not 270 * Allow execution from readable areas if the MMU does not
262 * provide separate controls over reading and executing. 271 * provide separate controls over reading and executing.
272 *
273 * Note: That code used to not be enabled for 4xx/BookE.
274 * It is now as I/D cache coherency for these is done at
275 * set_pte_at() time and I see no reason why the test
276 * below wouldn't be valid on those processors. This -may-
277 * break programs compiled with a really old ABI though.
263 */ 278 */
264 if (!(vma->vm_flags & VM_EXEC) && 279 if (!(vma->vm_flags & VM_EXEC) &&
265 (cpu_has_feature(CPU_FTR_NOEXECUTE) || 280 (cpu_has_feature(CPU_FTR_NOEXECUTE) ||
266 !(vma->vm_flags & (VM_READ | VM_WRITE)))) 281 !(vma->vm_flags & (VM_READ | VM_WRITE))))
267 goto bad_area; 282 goto bad_area;
268#else
269 pte_t *ptep;
270 pmd_t *pmdp;
271
272 /* Since 4xx/Book-E supports per-page execute permission,
273 * we lazily flush dcache to icache. */
274 ptep = NULL;
275 if (get_pteptr(mm, address, &ptep, &pmdp)) {
276 spinlock_t *ptl = pte_lockptr(mm, pmdp);
277 spin_lock(ptl);
278 if (pte_present(*ptep)) {
279 struct page *page = pte_page(*ptep);
280
281 if (!test_bit(PG_arch_1, &page->flags)) {
282 flush_dcache_icache_page(page);
283 set_bit(PG_arch_1, &page->flags);
284 }
285 pte_update(ptep, 0, _PAGE_HWEXEC |
286 _PAGE_ACCESSED);
287 local_flush_tlb_page(vma, address);
288 pte_unmap_unlock(ptep, ptl);
289 up_read(&mm->mmap_sem);
290 return 0;
291 }
292 pte_unmap_unlock(ptep, ptl);
293 }
294#endif
295 /* a write */ 283 /* a write */
296 } else if (is_write) { 284 } else if (is_write) {
297 if (!(vma->vm_flags & VM_WRITE)) 285 if (!(vma->vm_flags & VM_WRITE))
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index ea6e41e39d9f..3d8cf01582f5 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -56,10 +56,14 @@
56 56
57extern void loadcam_entry(unsigned int index); 57extern void loadcam_entry(unsigned int index);
58unsigned int tlbcam_index; 58unsigned int tlbcam_index;
59static unsigned long __cam0, __cam1, __cam2; 59static unsigned long cam[CONFIG_LOWMEM_CAM_NUM];
60 60
61#define NUM_TLBCAMS (16) 61#define NUM_TLBCAMS (16)
62 62
63#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
64#error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"
65#endif
66
63struct tlbcam TLBCAM[NUM_TLBCAMS]; 67struct tlbcam TLBCAM[NUM_TLBCAMS];
64 68
65struct tlbcamrange { 69struct tlbcamrange {
@@ -152,19 +156,19 @@ void invalidate_tlbcam_entry(int index)
152 loadcam_entry(index); 156 loadcam_entry(index);
153} 157}
154 158
155void __init cam_mapin_ram(unsigned long cam0, unsigned long cam1, 159unsigned long __init mmu_mapin_ram(void)
156 unsigned long cam2)
157{ 160{
158 settlbcam(0, PAGE_OFFSET, memstart_addr, cam0, _PAGE_KERNEL, 0); 161 unsigned long virt = PAGE_OFFSET;
159 tlbcam_index++; 162 phys_addr_t phys = memstart_addr;
160 if (cam1) { 163
161 tlbcam_index++; 164 while (cam[tlbcam_index] && tlbcam_index < ARRAY_SIZE(cam)) {
162 settlbcam(1, PAGE_OFFSET+cam0, memstart_addr+cam0, cam1, _PAGE_KERNEL, 0); 165 settlbcam(tlbcam_index, virt, phys, cam[tlbcam_index], _PAGE_KERNEL, 0);
163 } 166 virt += cam[tlbcam_index];
164 if (cam2) { 167 phys += cam[tlbcam_index];
165 tlbcam_index++; 168 tlbcam_index++;
166 settlbcam(2, PAGE_OFFSET+cam0+cam1, memstart_addr+cam0+cam1, cam2, _PAGE_KERNEL, 0);
167 } 169 }
170
171 return virt - PAGE_OFFSET;
168} 172}
169 173
170/* 174/*
@@ -175,51 +179,46 @@ void __init MMU_init_hw(void)
175 flush_instruction_cache(); 179 flush_instruction_cache();
176} 180}
177 181
178unsigned long __init mmu_mapin_ram(void)
179{
180 cam_mapin_ram(__cam0, __cam1, __cam2);
181
182 return __cam0 + __cam1 + __cam2;
183}
184
185
186void __init 182void __init
187adjust_total_lowmem(void) 183adjust_total_lowmem(void)
188{ 184{
189 phys_addr_t max_lowmem_size = __max_low_memory;
190 phys_addr_t cam_max_size = 0x10000000;
191 phys_addr_t ram; 185 phys_addr_t ram;
186 unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff;
187 char buf[ARRAY_SIZE(cam) * 5 + 1], *p = buf;
188 int i;
189 unsigned long virt = PAGE_OFFSET & 0xffffffffUL;
190 unsigned long phys = memstart_addr & 0xffffffffUL;
192 191
193 /* adjust CAM size to max_lowmem_size */ 192 /* Convert (4^max) kB to (2^max) bytes */
194 if (max_lowmem_size < cam_max_size) 193 max_cam = max_cam * 2 + 10;
195 cam_max_size = max_lowmem_size;
196 194
197 /* adjust lowmem size to max_lowmem_size */ 195 /* adjust lowmem size to __max_low_memory */
198 ram = min(max_lowmem_size, total_lowmem); 196 ram = min((phys_addr_t)__max_low_memory, (phys_addr_t)total_lowmem);
199 197
200 /* Calculate CAM values */ 198 /* Calculate CAM values */
201 __cam0 = 1UL << 2 * (__ilog2(ram) / 2); 199 __max_low_memory = 0;
202 if (__cam0 > cam_max_size) 200 for (i = 0; ram && i < ARRAY_SIZE(cam); i++) {
203 __cam0 = cam_max_size; 201 unsigned int camsize = __ilog2(ram) & ~1U;
204 ram -= __cam0; 202 unsigned int align = __ffs(virt | phys) & ~1U;
205 if (ram) { 203
206 __cam1 = 1UL << 2 * (__ilog2(ram) / 2); 204 if (camsize > align)
207 if (__cam1 > cam_max_size) 205 camsize = align;
208 __cam1 = cam_max_size; 206 if (camsize > max_cam)
209 ram -= __cam1; 207 camsize = max_cam;
210 } 208
211 if (ram) { 209 cam[i] = 1UL << camsize;
212 __cam2 = 1UL << 2 * (__ilog2(ram) / 2); 210 ram -= cam[i];
213 if (__cam2 > cam_max_size) 211 __max_low_memory += cam[i];
214 __cam2 = cam_max_size; 212 virt += cam[i];
215 ram -= __cam2; 213 phys += cam[i];
214
215 p += sprintf(p, "%lu/", cam[i] >> 20);
216 } 216 }
217 for (; i < ARRAY_SIZE(cam); i++)
218 p += sprintf(p, "0/");
219 p[-1] = '\0';
217 220
218 printk(KERN_INFO "Memory CAM mapping: CAM0=%ldMb, CAM1=%ldMb," 221 pr_info("Memory CAM mapping: %s Mb, residual: %ldMb\n", buf,
219 " CAM2=%ldMb residual: %ldMb\n", 222 (total_lowmem - __max_low_memory) >> 20);
220 __cam0 >> 20, __cam1 >> 20, __cam2 >> 20,
221 (long int)((total_lowmem - __cam0 - __cam1 - __cam2)
222 >> 20));
223 __max_low_memory = __cam0 + __cam1 + __cam2;
224 __initial_memory_limit_addr = memstart_addr + __max_low_memory; 223 __initial_memory_limit_addr = memstart_addr + __max_low_memory;
225} 224}
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index f00f09a77f12..f668fa9ba804 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -472,40 +472,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
472{ 472{
473#ifdef CONFIG_PPC_STD_MMU 473#ifdef CONFIG_PPC_STD_MMU
474 unsigned long access = 0, trap; 474 unsigned long access = 0, trap;
475#endif
476 unsigned long pfn = pte_pfn(pte);
477
478 /* handle i-cache coherency */
479 if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE) &&
480 !cpu_has_feature(CPU_FTR_NOEXECUTE) &&
481 pfn_valid(pfn)) {
482 struct page *page = pfn_to_page(pfn);
483#ifdef CONFIG_8xx
484 /* On 8xx, cache control instructions (particularly
485 * "dcbst" from flush_dcache_icache) fault as write
486 * operation if there is an unpopulated TLB entry
487 * for the address in question. To workaround that,
488 * we invalidate the TLB here, thus avoiding dcbst
489 * misbehaviour.
490 */
491 _tlbil_va(address, 0 /* 8xx doesn't care about PID */);
492#endif
493 /* The _PAGE_USER test should really be _PAGE_EXEC, but
494 * older glibc versions execute some code from no-exec
495 * pages, which for now we are supporting. If exec-only
496 * pages are ever implemented, this will have to change.
497 */
498 if (!PageReserved(page) && (pte_val(pte) & _PAGE_USER)
499 && !test_bit(PG_arch_1, &page->flags)) {
500 if (vma->vm_mm == current->active_mm) {
501 __flush_dcache_icache((void *) address);
502 } else
503 flush_dcache_icache_page(page);
504 set_bit(PG_arch_1, &page->flags);
505 }
506 }
507 475
508#ifdef CONFIG_PPC_STD_MMU
509 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */ 476 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
510 if (!pte_young(pte) || address >= TASK_SIZE) 477 if (!pte_young(pte) || address >= TASK_SIZE)
511 return; 478 return;
diff --git a/arch/powerpc/mm/mmap.c b/arch/powerpc/mm/mmap.c
index 86010fc7d3b1..7db8abc01ef8 100644
--- a/arch/powerpc/mm/mmap.c
+++ b/arch/powerpc/mm/mmap.c
@@ -48,12 +48,6 @@ static inline unsigned long mmap_base(void)
48 48
49static inline int mmap_is_legacy(void) 49static inline int mmap_is_legacy(void)
50{ 50{
51 /*
52 * Force standard allocation for 64 bit programs.
53 */
54 if (!test_thread_flag(TIF_32BIT))
55 return 1;
56
57 if (current->personality & ADDR_COMPAT_LAYOUT) 51 if (current->personality & ADDR_COMPAT_LAYOUT)
58 return 1; 52 return 1;
59 53
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 5ac08b8ab654..0507faa65478 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -158,35 +158,6 @@ static void unmap_cpu_from_node(unsigned long cpu)
158} 158}
159#endif /* CONFIG_HOTPLUG_CPU */ 159#endif /* CONFIG_HOTPLUG_CPU */
160 160
161static struct device_node * __cpuinit find_cpu_node(unsigned int cpu)
162{
163 unsigned int hw_cpuid = get_hard_smp_processor_id(cpu);
164 struct device_node *cpu_node = NULL;
165 const unsigned int *interrupt_server, *reg;
166 int len;
167
168 while ((cpu_node = of_find_node_by_type(cpu_node, "cpu")) != NULL) {
169 /* Try interrupt server first */
170 interrupt_server = of_get_property(cpu_node,
171 "ibm,ppc-interrupt-server#s", &len);
172
173 len = len / sizeof(u32);
174
175 if (interrupt_server && (len > 0)) {
176 while (len--) {
177 if (interrupt_server[len] == hw_cpuid)
178 return cpu_node;
179 }
180 } else {
181 reg = of_get_property(cpu_node, "reg", &len);
182 if (reg && (len > 0) && (reg[0] == hw_cpuid))
183 return cpu_node;
184 }
185 }
186
187 return NULL;
188}
189
190/* must hold reference to node during call */ 161/* must hold reference to node during call */
191static const int *of_get_associativity(struct device_node *dev) 162static const int *of_get_associativity(struct device_node *dev)
192{ 163{
@@ -290,7 +261,7 @@ static int __init find_min_common_depth(void)
290 ref_points = of_get_property(rtas_root, 261 ref_points = of_get_property(rtas_root,
291 "ibm,associativity-reference-points", &len); 262 "ibm,associativity-reference-points", &len);
292 263
293 if ((len >= 1) && ref_points) { 264 if ((len >= 2 * sizeof(unsigned int)) && ref_points) {
294 depth = ref_points[1]; 265 depth = ref_points[1];
295 } else { 266 } else {
296 dbg("NUMA: ibm,associativity-reference-points not found.\n"); 267 dbg("NUMA: ibm,associativity-reference-points not found.\n");
@@ -470,7 +441,7 @@ static int of_drconf_to_nid_single(struct of_drconf_cell *drmem,
470static int __cpuinit numa_setup_cpu(unsigned long lcpu) 441static int __cpuinit numa_setup_cpu(unsigned long lcpu)
471{ 442{
472 int nid = 0; 443 int nid = 0;
473 struct device_node *cpu = find_cpu_node(lcpu); 444 struct device_node *cpu = of_get_cpu_node(lcpu, NULL);
474 445
475 if (!cpu) { 446 if (!cpu) {
476 WARN_ON(1); 447 WARN_ON(1);
@@ -652,7 +623,7 @@ static int __init parse_numa_properties(void)
652 for_each_present_cpu(i) { 623 for_each_present_cpu(i) {
653 int nid; 624 int nid;
654 625
655 cpu = find_cpu_node(i); 626 cpu = of_get_cpu_node(i, NULL);
656 BUG_ON(!cpu); 627 BUG_ON(!cpu);
657 nid = of_node_to_nid_single(cpu); 628 nid = of_node_to_nid_single(cpu);
658 of_node_put(cpu); 629 of_node_put(cpu);
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index 6d94116fdea1..a27ded3adac5 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -1,5 +1,6 @@
1/* 1/*
2 * This file contains common routines for dealing with free of page tables 2 * This file contains common routines for dealing with free of page tables
3 * Along with common page table handling code
3 * 4 *
4 * Derived from arch/powerpc/mm/tlb_64.c: 5 * Derived from arch/powerpc/mm/tlb_64.c:
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
@@ -115,3 +116,133 @@ void pte_free_finish(void)
115 pte_free_submit(*batchp); 116 pte_free_submit(*batchp);
116 *batchp = NULL; 117 *batchp = NULL;
117} 118}
119
120/*
121 * Handle i/d cache flushing, called from set_pte_at() or ptep_set_access_flags()
122 */
123static pte_t do_dcache_icache_coherency(pte_t pte)
124{
125 unsigned long pfn = pte_pfn(pte);
126 struct page *page;
127
128 if (unlikely(!pfn_valid(pfn)))
129 return pte;
130 page = pfn_to_page(pfn);
131
132 if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)) {
133 pr_debug("do_dcache_icache_coherency... flushing\n");
134 flush_dcache_icache_page(page);
135 set_bit(PG_arch_1, &page->flags);
136 }
137 else
138 pr_debug("do_dcache_icache_coherency... already clean\n");
139 return __pte(pte_val(pte) | _PAGE_HWEXEC);
140}
141
142static inline int is_exec_fault(void)
143{
144 return current->thread.regs && TRAP(current->thread.regs) == 0x400;
145}
146
147/* We only try to do i/d cache coherency on stuff that looks like
148 * reasonably "normal" PTEs. We currently require a PTE to be present
149 * and we avoid _PAGE_SPECIAL and _PAGE_NO_CACHE
150 */
151static inline int pte_looks_normal(pte_t pte)
152{
153 return (pte_val(pte) &
154 (_PAGE_PRESENT | _PAGE_SPECIAL | _PAGE_NO_CACHE)) ==
155 (_PAGE_PRESENT);
156}
157
158#if defined(CONFIG_PPC_STD_MMU)
159/* Server-style MMU handles coherency when hashing if HW exec permission
160 * is supposed per page (currently 64-bit only). Else, we always flush
161 * valid PTEs in set_pte.
162 */
163static inline int pte_need_exec_flush(pte_t pte, int set_pte)
164{
165 return set_pte && pte_looks_normal(pte) &&
166 !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
167 cpu_has_feature(CPU_FTR_NOEXECUTE));
168}
169#elif _PAGE_HWEXEC == 0
170/* Embedded type MMU without HW exec support (8xx only so far), we flush
171 * the cache for any present PTE
172 */
173static inline int pte_need_exec_flush(pte_t pte, int set_pte)
174{
175 return set_pte && pte_looks_normal(pte);
176}
177#else
178/* Other embedded CPUs with HW exec support per-page, we flush on exec
179 * fault if HWEXEC is not set
180 */
181static inline int pte_need_exec_flush(pte_t pte, int set_pte)
182{
183 return pte_looks_normal(pte) && is_exec_fault() &&
184 !(pte_val(pte) & _PAGE_HWEXEC);
185}
186#endif
187
188/*
189 * set_pte stores a linux PTE into the linux page table.
190 */
191void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
192{
193#ifdef CONFIG_DEBUG_VM
194 WARN_ON(pte_present(*ptep));
195#endif
196 /* Note: mm->context.id might not yet have been assigned as
197 * this context might not have been activated yet when this
198 * is called.
199 */
200 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
201 if (pte_need_exec_flush(pte, 1))
202 pte = do_dcache_icache_coherency(pte);
203
204 /* Perform the setting of the PTE */
205 __set_pte_at(mm, addr, ptep, pte, 0);
206}
207
208/*
209 * This is called when relaxing access to a PTE. It's also called in the page
210 * fault path when we don't hit any of the major fault cases, ie, a minor
211 * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
212 * handled those two for us, we additionally deal with missing execute
213 * permission here on some processors
214 */
215int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
216 pte_t *ptep, pte_t entry, int dirty)
217{
218 int changed;
219 if (!dirty && pte_need_exec_flush(entry, 0))
220 entry = do_dcache_icache_coherency(entry);
221 changed = !pte_same(*(ptep), entry);
222 if (changed) {
223 assert_pte_locked(vma->vm_mm, address);
224 __ptep_set_access_flags(ptep, entry);
225 flush_tlb_page_nohash(vma, address);
226 }
227 return changed;
228}
229
230#ifdef CONFIG_DEBUG_VM
231void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
232{
233 pgd_t *pgd;
234 pud_t *pud;
235 pmd_t *pmd;
236
237 if (mm == &init_mm)
238 return;
239 pgd = mm->pgd + pgd_index(addr);
240 BUG_ON(pgd_none(*pgd));
241 pud = pud_offset(pgd, addr);
242 BUG_ON(pud_none(*pud));
243 pmd = pmd_offset(pud, addr);
244 BUG_ON(!pmd_present(*pmd));
245 BUG_ON(!spin_is_locked(pte_lockptr(mm, pmd)));
246}
247#endif /* CONFIG_DEBUG_VM */
248
diff --git a/arch/powerpc/platforms/52xx/Kconfig b/arch/powerpc/platforms/52xx/Kconfig
index 696a5ee4962d..0465e5b36e6a 100644
--- a/arch/powerpc/platforms/52xx/Kconfig
+++ b/arch/powerpc/platforms/52xx/Kconfig
@@ -21,7 +21,12 @@ config PPC_MPC5200_SIMPLE
21 and if there is a PCI bus node defined in the device tree. 21 and if there is a PCI bus node defined in the device tree.
22 22
23 Boards that are compatible with this generic platform support 23 Boards that are compatible with this generic platform support
24 are: 'tqc,tqm5200', 'promess,motionpro', 'schindler,cm5200'. 24 are:
25 intercontrol,digsy-mtc
26 phytec,pcm030
27 promess,motionpro
28 schindler,cm5200
29 tqc,tqm5200
25 30
26config PPC_EFIKA 31config PPC_EFIKA
27 bool "bPlan Efika 5k2. MPC5200B based computer" 32 bool "bPlan Efika 5k2. MPC5200B based computer"
@@ -35,6 +40,11 @@ config PPC_LITE5200
35 depends on PPC_MPC52xx 40 depends on PPC_MPC52xx
36 select DEFAULT_UIMAGE 41 select DEFAULT_UIMAGE
37 42
43config PPC_MEDIA5200
44 bool "Freescale Media5200 Eval Board"
45 depends on PPC_MPC52xx
46 select DEFAULT_UIMAGE
47
38config PPC_MPC5200_BUGFIX 48config PPC_MPC5200_BUGFIX
39 bool "MPC5200 (L25R) bugfix support" 49 bool "MPC5200 (L25R) bugfix support"
40 depends on PPC_MPC52xx 50 depends on PPC_MPC52xx
diff --git a/arch/powerpc/platforms/52xx/Makefile b/arch/powerpc/platforms/52xx/Makefile
index b8a52062738a..bfd4f52cf3dd 100644
--- a/arch/powerpc/platforms/52xx/Makefile
+++ b/arch/powerpc/platforms/52xx/Makefile
@@ -1,12 +1,13 @@
1# 1#
2# Makefile for 52xx based boards 2# Makefile for 52xx based boards
3# 3#
4obj-y += mpc52xx_pic.o mpc52xx_common.o 4obj-y += mpc52xx_pic.o mpc52xx_common.o mpc52xx_gpt.o
5obj-$(CONFIG_PCI) += mpc52xx_pci.o 5obj-$(CONFIG_PCI) += mpc52xx_pci.o
6 6
7obj-$(CONFIG_PPC_MPC5200_SIMPLE) += mpc5200_simple.o 7obj-$(CONFIG_PPC_MPC5200_SIMPLE) += mpc5200_simple.o
8obj-$(CONFIG_PPC_EFIKA) += efika.o 8obj-$(CONFIG_PPC_EFIKA) += efika.o
9obj-$(CONFIG_PPC_LITE5200) += lite5200.o 9obj-$(CONFIG_PPC_LITE5200) += lite5200.o
10obj-$(CONFIG_PPC_MEDIA5200) += media5200.o
10 11
11obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o 12obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o
12ifeq ($(CONFIG_PPC_LITE5200),y) 13ifeq ($(CONFIG_PPC_LITE5200),y)
diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c
new file mode 100644
index 000000000000..68e4f1696d14
--- /dev/null
+++ b/arch/powerpc/platforms/52xx/media5200.c
@@ -0,0 +1,273 @@
1/*
2 * Support for 'media5200-platform' compatible boards.
3 *
4 * Copyright (C) 2008 Secret Lab Technologies Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Description:
12 * This code implements support for the Freescape Media5200 platform
13 * (built around the MPC5200 SoC).
14 *
15 * Notable characteristic of the Media5200 is the presence of an FPGA
16 * that has all external IRQ lines routed through it. This file implements
17 * a cascaded interrupt controller driver which attaches itself to the
18 * Virtual IRQ subsystem after the primary mpc5200 interrupt controller
19 * is initialized.
20 *
21 */
22
23#undef DEBUG
24
25#include <linux/irq.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <asm/time.h>
29#include <asm/prom.h>
30#include <asm/machdep.h>
31#include <asm/mpc52xx.h>
32
33static struct of_device_id mpc5200_gpio_ids[] __initdata = {
34 { .compatible = "fsl,mpc5200-gpio", },
35 { .compatible = "mpc5200-gpio", },
36 {}
37};
38
39/* FPGA register set */
40#define MEDIA5200_IRQ_ENABLE (0x40c)
41#define MEDIA5200_IRQ_STATUS (0x410)
42#define MEDIA5200_NUM_IRQS (6)
43#define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS)
44
45struct media5200_irq {
46 void __iomem *regs;
47 spinlock_t lock;
48 struct irq_host *irqhost;
49};
50struct media5200_irq media5200_irq;
51
52static void media5200_irq_unmask(unsigned int virq)
53{
54 unsigned long flags;
55 u32 val;
56
57 spin_lock_irqsave(&media5200_irq.lock, flags);
58 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
59 val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq);
60 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
61 spin_unlock_irqrestore(&media5200_irq.lock, flags);
62}
63
64static void media5200_irq_mask(unsigned int virq)
65{
66 unsigned long flags;
67 u32 val;
68
69 spin_lock_irqsave(&media5200_irq.lock, flags);
70 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
71 val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq));
72 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
73 spin_unlock_irqrestore(&media5200_irq.lock, flags);
74}
75
76static struct irq_chip media5200_irq_chip = {
77 .typename = "Media5200 FPGA",
78 .unmask = media5200_irq_unmask,
79 .mask = media5200_irq_mask,
80 .mask_ack = media5200_irq_mask,
81};
82
83void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
84{
85 int sub_virq, val;
86 u32 status, enable;
87
88 /* Mask off the cascaded IRQ */
89 spin_lock(&desc->lock);
90 desc->chip->mask(virq);
91 spin_unlock(&desc->lock);
92
93 /* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs
94 * are pending. 'ffs()' is 1 based */
95 status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
96 enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
97 val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
98 if (val) {
99 sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
100 /* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
101 * __func__, virq, status, enable, val - 1, sub_virq);
102 */
103 generic_handle_irq(sub_virq);
104 }
105
106 /* Processing done; can reenable the cascade now */
107 spin_lock(&desc->lock);
108 desc->chip->ack(virq);
109 if (!(desc->status & IRQ_DISABLED))
110 desc->chip->unmask(virq);
111 spin_unlock(&desc->lock);
112}
113
114static int media5200_irq_map(struct irq_host *h, unsigned int virq,
115 irq_hw_number_t hw)
116{
117 struct irq_desc *desc = get_irq_desc(virq);
118
119 pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
120 set_irq_chip_data(virq, &media5200_irq);
121 set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
122 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
123 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
124 desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL;
125
126 return 0;
127}
128
129static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct,
130 u32 *intspec, unsigned int intsize,
131 irq_hw_number_t *out_hwirq,
132 unsigned int *out_flags)
133{
134 if (intsize != 2)
135 return -1;
136
137 pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
138 *out_hwirq = intspec[1];
139 *out_flags = IRQ_TYPE_NONE;
140 return 0;
141}
142
143static struct irq_host_ops media5200_irq_ops = {
144 .map = media5200_irq_map,
145 .xlate = media5200_irq_xlate,
146};
147
148/*
149 * Setup Media5200 IRQ mapping
150 */
151static void __init media5200_init_irq(void)
152{
153 struct device_node *fpga_np;
154 int cascade_virq;
155
156 /* First setup the regular MPC5200 interrupt controller */
157 mpc52xx_init_irq();
158
159 /* Now find the FPGA IRQ */
160 fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
161 if (!fpga_np)
162 goto out;
163 pr_debug("%s: found fpga node: %s\n", __func__, fpga_np->full_name);
164
165 media5200_irq.regs = of_iomap(fpga_np, 0);
166 if (!media5200_irq.regs)
167 goto out;
168 pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
169
170 cascade_virq = irq_of_parse_and_map(fpga_np, 0);
171 if (!cascade_virq)
172 goto out;
173 pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);
174
175 /* Disable all FPGA IRQs */
176 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
177
178 spin_lock_init(&media5200_irq.lock);
179
180 media5200_irq.irqhost = irq_alloc_host(fpga_np, IRQ_HOST_MAP_LINEAR,
181 MEDIA5200_NUM_IRQS,
182 &media5200_irq_ops, -1);
183 if (!media5200_irq.irqhost)
184 goto out;
185 pr_debug("%s: allocated irqhost\n", __func__);
186
187 media5200_irq.irqhost->host_data = &media5200_irq;
188
189 set_irq_data(cascade_virq, &media5200_irq);
190 set_irq_chained_handler(cascade_virq, media5200_irq_cascade);
191
192 return;
193
194 out:
195 pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
196}
197
198/*
199 * Setup the architecture
200 */
201static void __init media5200_setup_arch(void)
202{
203
204 struct device_node *np;
205 struct mpc52xx_gpio __iomem *gpio;
206 u32 port_config;
207
208 if (ppc_md.progress)
209 ppc_md.progress("media5200_setup_arch()", 0);
210
211 /* Map important registers from the internal memory map */
212 mpc52xx_map_common_devices();
213
214 /* Some mpc5200 & mpc5200b related configuration */
215 mpc5200_setup_xlb_arbiter();
216
217 mpc52xx_setup_pci();
218
219 np = of_find_matching_node(NULL, mpc5200_gpio_ids);
220 gpio = of_iomap(np, 0);
221 of_node_put(np);
222 if (!gpio) {
223 printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
224 __func__);
225 return;
226 }
227
228 /* Set port config */
229 port_config = in_be32(&gpio->port_config);
230
231 port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */
232 port_config |= 0x01000000;
233
234 out_be32(&gpio->port_config, port_config);
235
236 /* Unmap zone */
237 iounmap(gpio);
238
239}
240
241/* list of the supported boards */
242static char *board[] __initdata = {
243 "fsl,media5200",
244 NULL
245};
246
247/*
248 * Called very early, MMU is off, device-tree isn't unflattened
249 */
250static int __init media5200_probe(void)
251{
252 unsigned long node = of_get_flat_dt_root();
253 int i = 0;
254
255 while (board[i]) {
256 if (of_flat_dt_is_compatible(node, board[i]))
257 break;
258 i++;
259 }
260
261 return (board[i] != NULL);
262}
263
264define_machine(media5200_platform) {
265 .name = "media5200-platform",
266 .probe = media5200_probe,
267 .setup_arch = media5200_setup_arch,
268 .init = mpc52xx_declare_of_platform_devices,
269 .init_IRQ = media5200_init_irq,
270 .get_irq = mpc52xx_get_irq,
271 .restart = mpc52xx_restart,
272 .calibrate_decr = generic_calibrate_decr,
273};
diff --git a/arch/powerpc/platforms/52xx/mpc5200_simple.c b/arch/powerpc/platforms/52xx/mpc5200_simple.c
index a3bda0b9f1ff..d5e1471e51f7 100644
--- a/arch/powerpc/platforms/52xx/mpc5200_simple.c
+++ b/arch/powerpc/platforms/52xx/mpc5200_simple.c
@@ -50,6 +50,7 @@ static void __init mpc5200_simple_setup_arch(void)
50 50
51/* list of the supported boards */ 51/* list of the supported boards */
52static char *board[] __initdata = { 52static char *board[] __initdata = {
53 "intercontrol,digsy-mtc",
53 "promess,motionpro", 54 "promess,motionpro",
54 "phytec,pcm030", 55 "phytec,pcm030",
55 "schindler,cm5200", 56 "schindler,cm5200",
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
index 07f89ae46d04..2b8d8ef32e4e 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpio.c
@@ -354,88 +354,6 @@ static struct of_platform_driver mpc52xx_simple_gpiochip_driver = {
354 .remove = mpc52xx_gpiochip_remove, 354 .remove = mpc52xx_gpiochip_remove,
355}; 355};
356 356
357/*
358 * GPIO LIB API implementation for gpt GPIOs.
359 *
360 * Each gpt only has a single GPIO.
361 */
362static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
363{
364 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
365 struct mpc52xx_gpt __iomem *regs = mm_gc->regs;
366
367 return (in_be32(&regs->status) & (1 << (31 - 23))) ? 1 : 0;
368}
369
370static void
371mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
372{
373 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
374 struct mpc52xx_gpt __iomem *regs = mm_gc->regs;
375
376 if (val)
377 out_be32(&regs->mode, 0x34);
378 else
379 out_be32(&regs->mode, 0x24);
380
381 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
382}
383
384static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
385{
386 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
387 struct mpc52xx_gpt __iomem *regs = mm_gc->regs;
388
389 out_be32(&regs->mode, 0x04);
390
391 return 0;
392}
393
394static int
395mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
396{
397 mpc52xx_gpt_gpio_set(gc, gpio, val);
398 pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
399
400 return 0;
401}
402
403static int __devinit mpc52xx_gpt_gpiochip_probe(struct of_device *ofdev,
404 const struct of_device_id *match)
405{
406 struct of_mm_gpio_chip *mmchip;
407 struct of_gpio_chip *chip;
408
409 mmchip = kzalloc(sizeof(*mmchip), GFP_KERNEL);
410 if (!mmchip)
411 return -ENOMEM;
412
413 chip = &mmchip->of_gc;
414
415 chip->gpio_cells = 2;
416 chip->gc.ngpio = 1;
417 chip->gc.direction_input = mpc52xx_gpt_gpio_dir_in;
418 chip->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
419 chip->gc.get = mpc52xx_gpt_gpio_get;
420 chip->gc.set = mpc52xx_gpt_gpio_set;
421
422 return of_mm_gpiochip_add(ofdev->node, mmchip);
423}
424
425static const struct of_device_id mpc52xx_gpt_gpiochip_match[] = {
426 {
427 .compatible = "fsl,mpc5200-gpt-gpio",
428 },
429 {}
430};
431
432static struct of_platform_driver mpc52xx_gpt_gpiochip_driver = {
433 .name = "gpio_gpt",
434 .match_table = mpc52xx_gpt_gpiochip_match,
435 .probe = mpc52xx_gpt_gpiochip_probe,
436 .remove = mpc52xx_gpiochip_remove,
437};
438
439static int __init mpc52xx_gpio_init(void) 357static int __init mpc52xx_gpio_init(void)
440{ 358{
441 if (of_register_platform_driver(&mpc52xx_wkup_gpiochip_driver)) 359 if (of_register_platform_driver(&mpc52xx_wkup_gpiochip_driver))
@@ -444,9 +362,6 @@ static int __init mpc52xx_gpio_init(void)
444 if (of_register_platform_driver(&mpc52xx_simple_gpiochip_driver)) 362 if (of_register_platform_driver(&mpc52xx_simple_gpiochip_driver))
445 printk(KERN_ERR "Unable to register simple GPIO driver\n"); 363 printk(KERN_ERR "Unable to register simple GPIO driver\n");
446 364
447 if (of_register_platform_driver(&mpc52xx_gpt_gpiochip_driver))
448 printk(KERN_ERR "Unable to register gpt GPIO driver\n");
449
450 return 0; 365 return 0;
451} 366}
452 367
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
new file mode 100644
index 000000000000..cb038dc67a85
--- /dev/null
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -0,0 +1,435 @@
1/*
2 * MPC5200 General Purpose Timer device driver
3 *
4 * Copyright (c) 2009 Secret Lab Technologies Ltd.
5 * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This file is a driver for the the General Purpose Timer (gpt) devices
13 * found on the MPC5200 SoC. Each timer has an IO pin which can be used
14 * for GPIO or can be used to raise interrupts. The timer function can
15 * be used independently from the IO pin, or it can be used to control
16 * output signals or measure input signals.
17 *
18 * This driver supports the GPIO and IRQ controller functions of the GPT
19 * device. Timer functions are not yet supported, nor is the watchdog
20 * timer.
21 *
22 * To use the GPIO function, the following two properties must be added
23 * to the device tree node for the gpt device (typically in the .dts file
24 * for the board):
25 * gpio-controller;
26 * #gpio-cells = < 2 >;
27 * This driver will register the GPIO pin if it finds the gpio-controller
28 * property in the device tree.
29 *
30 * To use the IRQ controller function, the following two properties must
31 * be added to the device tree node for the gpt device:
32 * interrupt-controller;
33 * #interrupt-cells = < 1 >;
34 * The IRQ controller binding only uses one cell to specify the interrupt,
35 * and the IRQ flags are encoded in the cell. A cell is not used to encode
36 * the IRQ number because the GPT only has a single IRQ source. For flags,
37 * a value of '1' means rising edge sensitive and '2' means falling edge.
38 *
39 * The GPIO and the IRQ controller functions can be used at the same time,
40 * but in this use case the IO line will only work as an input. Trying to
41 * use it as a GPIO output will not work.
42 *
43 * When using the GPIO line as an output, it can either be driven as normal
44 * IO, or it can be an Open Collector (OC) output. At the moment it is the
45 * responsibility of either the bootloader or the platform setup code to set
46 * the output mode. This driver does not change the output mode setting.
47 */
48
49#include <linux/irq.h>
50#include <linux/interrupt.h>
51#include <linux/io.h>
52#include <linux/of.h>
53#include <linux/of_platform.h>
54#include <linux/of_gpio.h>
55#include <linux/kernel.h>
56#include <asm/mpc52xx.h>
57
58MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
59MODULE_AUTHOR("Sascha Hauer, Grant Likely");
60MODULE_LICENSE("GPL");
61
62/**
63 * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
64 * @dev: pointer to device structure
65 * @regs: virtual address of GPT registers
66 * @lock: spinlock to coordinate between different functions.
67 * @of_gc: of_gpio_chip instance structure; used when GPIO is enabled
68 * @irqhost: Pointer to irq_host instance; used when IRQ mode is supported
69 */
70struct mpc52xx_gpt_priv {
71 struct device *dev;
72 struct mpc52xx_gpt __iomem *regs;
73 spinlock_t lock;
74 struct irq_host *irqhost;
75
76#if defined(CONFIG_GPIOLIB)
77 struct of_gpio_chip of_gc;
78#endif
79};
80
81#define MPC52xx_GPT_MODE_MS_MASK (0x07)
82#define MPC52xx_GPT_MODE_MS_IC (0x01)
83#define MPC52xx_GPT_MODE_MS_OC (0x02)
84#define MPC52xx_GPT_MODE_MS_PWM (0x03)
85#define MPC52xx_GPT_MODE_MS_GPIO (0x04)
86
87#define MPC52xx_GPT_MODE_GPIO_MASK (0x30)
88#define MPC52xx_GPT_MODE_GPIO_OUT_LOW (0x20)
89#define MPC52xx_GPT_MODE_GPIO_OUT_HIGH (0x30)
90
91#define MPC52xx_GPT_MODE_IRQ_EN (0x0100)
92
93#define MPC52xx_GPT_MODE_ICT_MASK (0x030000)
94#define MPC52xx_GPT_MODE_ICT_RISING (0x010000)
95#define MPC52xx_GPT_MODE_ICT_FALLING (0x020000)
96#define MPC52xx_GPT_MODE_ICT_TOGGLE (0x030000)
97
98#define MPC52xx_GPT_STATUS_IRQMASK (0x000f)
99
100/* ---------------------------------------------------------------------
101 * Cascaded interrupt controller hooks
102 */
103
104static void mpc52xx_gpt_irq_unmask(unsigned int virq)
105{
106 struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
107 unsigned long flags;
108
109 spin_lock_irqsave(&gpt->lock, flags);
110 setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
111 spin_unlock_irqrestore(&gpt->lock, flags);
112}
113
114static void mpc52xx_gpt_irq_mask(unsigned int virq)
115{
116 struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
117 unsigned long flags;
118
119 spin_lock_irqsave(&gpt->lock, flags);
120 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
121 spin_unlock_irqrestore(&gpt->lock, flags);
122}
123
124static void mpc52xx_gpt_irq_ack(unsigned int virq)
125{
126 struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
127
128 out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
129}
130
131static int mpc52xx_gpt_irq_set_type(unsigned int virq, unsigned int flow_type)
132{
133 struct mpc52xx_gpt_priv *gpt = get_irq_chip_data(virq);
134 unsigned long flags;
135 u32 reg;
136
137 dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, virq, flow_type);
138
139 spin_lock_irqsave(&gpt->lock, flags);
140 reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
141 if (flow_type & IRQF_TRIGGER_RISING)
142 reg |= MPC52xx_GPT_MODE_ICT_RISING;
143 if (flow_type & IRQF_TRIGGER_FALLING)
144 reg |= MPC52xx_GPT_MODE_ICT_FALLING;
145 out_be32(&gpt->regs->mode, reg);
146 spin_unlock_irqrestore(&gpt->lock, flags);
147
148 return 0;
149}
150
151static struct irq_chip mpc52xx_gpt_irq_chip = {
152 .typename = "MPC52xx GPT",
153 .unmask = mpc52xx_gpt_irq_unmask,
154 .mask = mpc52xx_gpt_irq_mask,
155 .ack = mpc52xx_gpt_irq_ack,
156 .set_type = mpc52xx_gpt_irq_set_type,
157};
158
159void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc)
160{
161 struct mpc52xx_gpt_priv *gpt = get_irq_data(virq);
162 int sub_virq;
163 u32 status;
164
165 status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
166 if (status) {
167 sub_virq = irq_linear_revmap(gpt->irqhost, 0);
168 generic_handle_irq(sub_virq);
169 }
170}
171
172static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq,
173 irq_hw_number_t hw)
174{
175 struct mpc52xx_gpt_priv *gpt = h->host_data;
176
177 dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
178 set_irq_chip_data(virq, gpt);
179 set_irq_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
180
181 return 0;
182}
183
184static int mpc52xx_gpt_irq_xlate(struct irq_host *h, struct device_node *ct,
185 u32 *intspec, unsigned int intsize,
186 irq_hw_number_t *out_hwirq,
187 unsigned int *out_flags)
188{
189 struct mpc52xx_gpt_priv *gpt = h->host_data;
190
191 dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
192
193 if ((intsize < 1) || (intspec[0] < 1) || (intspec[0] > 3)) {
194 dev_err(gpt->dev, "bad irq specifier in %s\n", ct->full_name);
195 return -EINVAL;
196 }
197
198 *out_hwirq = 0; /* The GPT only has 1 IRQ line */
199 *out_flags = intspec[0];
200
201 return 0;
202}
203
204static struct irq_host_ops mpc52xx_gpt_irq_ops = {
205 .map = mpc52xx_gpt_irq_map,
206 .xlate = mpc52xx_gpt_irq_xlate,
207};
208
209static void
210mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
211{
212 int cascade_virq;
213 unsigned long flags;
214
215 /* Only setup cascaded IRQ if device tree claims the GPT is
216 * an interrupt controller */
217 if (!of_find_property(node, "interrupt-controller", NULL))
218 return;
219
220 cascade_virq = irq_of_parse_and_map(node, 0);
221
222 gpt->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR, 1,
223 &mpc52xx_gpt_irq_ops, -1);
224 if (!gpt->irqhost) {
225 dev_err(gpt->dev, "irq_alloc_host() failed\n");
226 return;
227 }
228
229 gpt->irqhost->host_data = gpt;
230
231 set_irq_data(cascade_virq, gpt);
232 set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
233
234 /* Set to Input Capture mode */
235 spin_lock_irqsave(&gpt->lock, flags);
236 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
237 MPC52xx_GPT_MODE_MS_IC);
238 spin_unlock_irqrestore(&gpt->lock, flags);
239
240 dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
241}
242
243
244/* ---------------------------------------------------------------------
245 * GPIOLIB hooks
246 */
247#if defined(CONFIG_GPIOLIB)
248static inline struct mpc52xx_gpt_priv *gc_to_mpc52xx_gpt(struct gpio_chip *gc)
249{
250 return container_of(to_of_gpio_chip(gc), struct mpc52xx_gpt_priv,of_gc);
251}
252
253static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
254{
255 struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
256
257 return (in_be32(&gpt->regs->status) >> 8) & 1;
258}
259
260static void
261mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
262{
263 struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
264 unsigned long flags;
265 u32 r;
266
267 dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
268 r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
269
270 spin_lock_irqsave(&gpt->lock, flags);
271 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
272 spin_unlock_irqrestore(&gpt->lock, flags);
273}
274
275static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
276{
277 struct mpc52xx_gpt_priv *gpt = gc_to_mpc52xx_gpt(gc);
278 unsigned long flags;
279
280 dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
281
282 spin_lock_irqsave(&gpt->lock, flags);
283 clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
284 spin_unlock_irqrestore(&gpt->lock, flags);
285
286 return 0;
287}
288
289static int
290mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
291{
292 mpc52xx_gpt_gpio_set(gc, gpio, val);
293 return 0;
294}
295
296static void
297mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
298{
299 int rc;
300
301 /* Only setup GPIO if the device tree claims the GPT is
302 * a GPIO controller */
303 if (!of_find_property(node, "gpio-controller", NULL))
304 return;
305
306 gpt->of_gc.gc.label = kstrdup(node->full_name, GFP_KERNEL);
307 if (!gpt->of_gc.gc.label) {
308 dev_err(gpt->dev, "out of memory\n");
309 return;
310 }
311
312 gpt->of_gc.gpio_cells = 2;
313 gpt->of_gc.gc.ngpio = 1;
314 gpt->of_gc.gc.direction_input = mpc52xx_gpt_gpio_dir_in;
315 gpt->of_gc.gc.direction_output = mpc52xx_gpt_gpio_dir_out;
316 gpt->of_gc.gc.get = mpc52xx_gpt_gpio_get;
317 gpt->of_gc.gc.set = mpc52xx_gpt_gpio_set;
318 gpt->of_gc.gc.base = -1;
319 gpt->of_gc.xlate = of_gpio_simple_xlate;
320 node->data = &gpt->of_gc;
321 of_node_get(node);
322
323 /* Setup external pin in GPIO mode */
324 clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
325 MPC52xx_GPT_MODE_MS_GPIO);
326
327 rc = gpiochip_add(&gpt->of_gc.gc);
328 if (rc)
329 dev_err(gpt->dev, "gpiochip_add() failed; rc=%i\n", rc);
330
331 dev_dbg(gpt->dev, "%s() complete.\n", __func__);
332}
333#else /* defined(CONFIG_GPIOLIB) */
334static void
335mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *p, struct device_node *np) { }
336#endif /* defined(CONFIG_GPIOLIB) */
337
338/***********************************************************************
339 * SYSFS attributes
340 */
341#if defined(CONFIG_SYSFS)
342static ssize_t mpc52xx_gpt_show_regs(struct device *dev,
343 struct device_attribute *attr, char *buf)
344{
345 struct mpc52xx_gpt_priv *gpt = dev_get_drvdata(dev);
346 int i, len = 0;
347 u32 __iomem *regs = (void __iomem *) gpt->regs;
348
349 for (i = 0; i < 4; i++)
350 len += sprintf(buf + len, "%.8x ", in_be32(regs + i));
351 len += sprintf(buf + len, "\n");
352
353 return len;
354}
355
356static struct device_attribute mpc52xx_gpt_attrib[] = {
357 __ATTR(regs, S_IRUGO | S_IWUSR, mpc52xx_gpt_show_regs, NULL),
358};
359
360static void mpc52xx_gpt_create_attribs(struct mpc52xx_gpt_priv *gpt)
361{
362 int i, err = 0;
363
364 for (i = 0; i < ARRAY_SIZE(mpc52xx_gpt_attrib); i++) {
365 err = device_create_file(gpt->dev, &mpc52xx_gpt_attrib[i]);
366 if (err)
367 dev_err(gpt->dev, "error creating attribute %i\n", i);
368 }
369
370}
371
372#else /* defined(CONFIG_SYSFS) */
373static void mpc52xx_gpt_create_attribs(struct mpc52xx_gpt_priv *) { return 0; }
374#endif /* defined(CONFIG_SYSFS) */
375
376/* ---------------------------------------------------------------------
377 * of_platform bus binding code
378 */
379static int __devinit mpc52xx_gpt_probe(struct of_device *ofdev,
380 const struct of_device_id *match)
381{
382 struct mpc52xx_gpt_priv *gpt;
383
384 gpt = kzalloc(sizeof *gpt, GFP_KERNEL);
385 if (!gpt)
386 return -ENOMEM;
387
388 spin_lock_init(&gpt->lock);
389 gpt->dev = &ofdev->dev;
390 gpt->regs = of_iomap(ofdev->node, 0);
391 if (!gpt->regs) {
392 kfree(gpt);
393 return -ENOMEM;
394 }
395
396 dev_set_drvdata(&ofdev->dev, gpt);
397
398 mpc52xx_gpt_create_attribs(gpt);
399 mpc52xx_gpt_gpio_setup(gpt, ofdev->node);
400 mpc52xx_gpt_irq_setup(gpt, ofdev->node);
401
402 return 0;
403}
404
405static int mpc52xx_gpt_remove(struct of_device *ofdev)
406{
407 return -EBUSY;
408}
409
410static const struct of_device_id mpc52xx_gpt_match[] = {
411 { .compatible = "fsl,mpc5200-gpt", },
412
413 /* Depreciated compatible values; don't use for new dts files */
414 { .compatible = "fsl,mpc5200-gpt-gpio", },
415 { .compatible = "mpc5200-gpt", },
416 {}
417};
418
419static struct of_platform_driver mpc52xx_gpt_driver = {
420 .name = "mpc52xx-gpt",
421 .match_table = mpc52xx_gpt_match,
422 .probe = mpc52xx_gpt_probe,
423 .remove = mpc52xx_gpt_remove,
424};
425
426static int __init mpc52xx_gpt_init(void)
427{
428 if (of_register_platform_driver(&mpc52xx_gpt_driver))
429 pr_err("error registering MPC52xx GPT driver\n");
430
431 return 0;
432}
433
434/* Make sure GPIOs and IRQs get set up before anyone tries to use them */
435subsys_initcall(mpc52xx_gpt_init);
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
index 0a093f03c758..480f806fd0a9 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
@@ -163,8 +163,6 @@ static void mpc52xx_extirq_mask(unsigned int virq)
163 irq = irq_map[virq].hwirq; 163 irq = irq_map[virq].hwirq;
164 l2irq = irq & MPC52xx_IRQ_L2_MASK; 164 l2irq = irq & MPC52xx_IRQ_L2_MASK;
165 165
166 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
167
168 io_be_clrbit(&intr->ctrl, 11 - l2irq); 166 io_be_clrbit(&intr->ctrl, 11 - l2irq);
169} 167}
170 168
@@ -176,8 +174,6 @@ static void mpc52xx_extirq_unmask(unsigned int virq)
176 irq = irq_map[virq].hwirq; 174 irq = irq_map[virq].hwirq;
177 l2irq = irq & MPC52xx_IRQ_L2_MASK; 175 l2irq = irq & MPC52xx_IRQ_L2_MASK;
178 176
179 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
180
181 io_be_setbit(&intr->ctrl, 11 - l2irq); 177 io_be_setbit(&intr->ctrl, 11 - l2irq);
182} 178}
183 179
@@ -189,17 +185,15 @@ static void mpc52xx_extirq_ack(unsigned int virq)
189 irq = irq_map[virq].hwirq; 185 irq = irq_map[virq].hwirq;
190 l2irq = irq & MPC52xx_IRQ_L2_MASK; 186 l2irq = irq & MPC52xx_IRQ_L2_MASK;
191 187
192 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
193
194 io_be_setbit(&intr->ctrl, 27-l2irq); 188 io_be_setbit(&intr->ctrl, 27-l2irq);
195} 189}
196 190
197static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type) 191static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
198{ 192{
199 struct irq_desc *desc = get_irq_desc(virq);
200 u32 ctrl_reg, type; 193 u32 ctrl_reg, type;
201 int irq; 194 int irq;
202 int l2irq; 195 int l2irq;
196 void *handler = handle_level_irq;
203 197
204 irq = irq_map[virq].hwirq; 198 irq = irq_map[virq].hwirq;
205 l2irq = irq & MPC52xx_IRQ_L2_MASK; 199 l2irq = irq & MPC52xx_IRQ_L2_MASK;
@@ -207,32 +201,21 @@ static int mpc52xx_extirq_set_type(unsigned int virq, unsigned int flow_type)
207 pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type); 201 pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type);
208 202
209 switch (flow_type) { 203 switch (flow_type) {
210 case IRQF_TRIGGER_HIGH: 204 case IRQF_TRIGGER_HIGH: type = 0; break;
211 type = 0; 205 case IRQF_TRIGGER_RISING: type = 1; handler = handle_edge_irq; break;
212 break; 206 case IRQF_TRIGGER_FALLING: type = 2; handler = handle_edge_irq; break;
213 case IRQF_TRIGGER_RISING: 207 case IRQF_TRIGGER_LOW: type = 3; break;
214 type = 1;
215 break;
216 case IRQF_TRIGGER_FALLING:
217 type = 2;
218 break;
219 case IRQF_TRIGGER_LOW:
220 type = 3;
221 break;
222 default: 208 default:
223 type = 0; 209 type = 0;
224 } 210 }
225 211
226 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
227 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
228 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
229 desc->status |= IRQ_LEVEL;
230
231 ctrl_reg = in_be32(&intr->ctrl); 212 ctrl_reg = in_be32(&intr->ctrl);
232 ctrl_reg &= ~(0x3 << (22 - (l2irq * 2))); 213 ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
233 ctrl_reg |= (type << (22 - (l2irq * 2))); 214 ctrl_reg |= (type << (22 - (l2irq * 2)));
234 out_be32(&intr->ctrl, ctrl_reg); 215 out_be32(&intr->ctrl, ctrl_reg);
235 216
217 __set_irq_handler_unlocked(virq, handler);
218
236 return 0; 219 return 0;
237} 220}
238 221
@@ -247,6 +230,11 @@ static struct irq_chip mpc52xx_extirq_irqchip = {
247/* 230/*
248 * Main interrupt irq_chip 231 * Main interrupt irq_chip
249 */ 232 */
233static int mpc52xx_null_set_type(unsigned int virq, unsigned int flow_type)
234{
235 return 0; /* Do nothing so that the sense mask will get updated */
236}
237
250static void mpc52xx_main_mask(unsigned int virq) 238static void mpc52xx_main_mask(unsigned int virq)
251{ 239{
252 int irq; 240 int irq;
@@ -255,8 +243,6 @@ static void mpc52xx_main_mask(unsigned int virq)
255 irq = irq_map[virq].hwirq; 243 irq = irq_map[virq].hwirq;
256 l2irq = irq & MPC52xx_IRQ_L2_MASK; 244 l2irq = irq & MPC52xx_IRQ_L2_MASK;
257 245
258 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
259
260 io_be_setbit(&intr->main_mask, 16 - l2irq); 246 io_be_setbit(&intr->main_mask, 16 - l2irq);
261} 247}
262 248
@@ -268,8 +254,6 @@ static void mpc52xx_main_unmask(unsigned int virq)
268 irq = irq_map[virq].hwirq; 254 irq = irq_map[virq].hwirq;
269 l2irq = irq & MPC52xx_IRQ_L2_MASK; 255 l2irq = irq & MPC52xx_IRQ_L2_MASK;
270 256
271 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
272
273 io_be_clrbit(&intr->main_mask, 16 - l2irq); 257 io_be_clrbit(&intr->main_mask, 16 - l2irq);
274} 258}
275 259
@@ -278,6 +262,7 @@ static struct irq_chip mpc52xx_main_irqchip = {
278 .mask = mpc52xx_main_mask, 262 .mask = mpc52xx_main_mask,
279 .mask_ack = mpc52xx_main_mask, 263 .mask_ack = mpc52xx_main_mask,
280 .unmask = mpc52xx_main_unmask, 264 .unmask = mpc52xx_main_unmask,
265 .set_type = mpc52xx_null_set_type,
281}; 266};
282 267
283/* 268/*
@@ -291,8 +276,6 @@ static void mpc52xx_periph_mask(unsigned int virq)
291 irq = irq_map[virq].hwirq; 276 irq = irq_map[virq].hwirq;
292 l2irq = irq & MPC52xx_IRQ_L2_MASK; 277 l2irq = irq & MPC52xx_IRQ_L2_MASK;
293 278
294 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
295
296 io_be_setbit(&intr->per_mask, 31 - l2irq); 279 io_be_setbit(&intr->per_mask, 31 - l2irq);
297} 280}
298 281
@@ -304,8 +287,6 @@ static void mpc52xx_periph_unmask(unsigned int virq)
304 irq = irq_map[virq].hwirq; 287 irq = irq_map[virq].hwirq;
305 l2irq = irq & MPC52xx_IRQ_L2_MASK; 288 l2irq = irq & MPC52xx_IRQ_L2_MASK;
306 289
307 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
308
309 io_be_clrbit(&intr->per_mask, 31 - l2irq); 290 io_be_clrbit(&intr->per_mask, 31 - l2irq);
310} 291}
311 292
@@ -314,6 +295,7 @@ static struct irq_chip mpc52xx_periph_irqchip = {
314 .mask = mpc52xx_periph_mask, 295 .mask = mpc52xx_periph_mask,
315 .mask_ack = mpc52xx_periph_mask, 296 .mask_ack = mpc52xx_periph_mask,
316 .unmask = mpc52xx_periph_unmask, 297 .unmask = mpc52xx_periph_unmask,
298 .set_type = mpc52xx_null_set_type,
317}; 299};
318 300
319/* 301/*
@@ -327,8 +309,6 @@ static void mpc52xx_sdma_mask(unsigned int virq)
327 irq = irq_map[virq].hwirq; 309 irq = irq_map[virq].hwirq;
328 l2irq = irq & MPC52xx_IRQ_L2_MASK; 310 l2irq = irq & MPC52xx_IRQ_L2_MASK;
329 311
330 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
331
332 io_be_setbit(&sdma->IntMask, l2irq); 312 io_be_setbit(&sdma->IntMask, l2irq);
333} 313}
334 314
@@ -340,8 +320,6 @@ static void mpc52xx_sdma_unmask(unsigned int virq)
340 irq = irq_map[virq].hwirq; 320 irq = irq_map[virq].hwirq;
341 l2irq = irq & MPC52xx_IRQ_L2_MASK; 321 l2irq = irq & MPC52xx_IRQ_L2_MASK;
342 322
343 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
344
345 io_be_clrbit(&sdma->IntMask, l2irq); 323 io_be_clrbit(&sdma->IntMask, l2irq);
346} 324}
347 325
@@ -353,8 +331,6 @@ static void mpc52xx_sdma_ack(unsigned int virq)
353 irq = irq_map[virq].hwirq; 331 irq = irq_map[virq].hwirq;
354 l2irq = irq & MPC52xx_IRQ_L2_MASK; 332 l2irq = irq & MPC52xx_IRQ_L2_MASK;
355 333
356 pr_debug("%s: irq=%x. l2=%d\n", __func__, irq, l2irq);
357
358 out_be32(&sdma->IntPend, 1 << l2irq); 334 out_be32(&sdma->IntPend, 1 << l2irq);
359} 335}
360 336
@@ -363,9 +339,19 @@ static struct irq_chip mpc52xx_sdma_irqchip = {
363 .mask = mpc52xx_sdma_mask, 339 .mask = mpc52xx_sdma_mask,
364 .unmask = mpc52xx_sdma_unmask, 340 .unmask = mpc52xx_sdma_unmask,
365 .ack = mpc52xx_sdma_ack, 341 .ack = mpc52xx_sdma_ack,
342 .set_type = mpc52xx_null_set_type,
366}; 343};
367 344
368/** 345/**
346 * mpc52xx_is_extirq - Returns true if hwirq number is for an external IRQ
347 */
348static int mpc52xx_is_extirq(int l1, int l2)
349{
350 return ((l1 == 0) && (l2 == 0)) ||
351 ((l1 == 1) && (l2 >= 1) && (l2 <= 3));
352}
353
354/**
369 * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property 355 * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property
370 */ 356 */
371static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct, 357static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
@@ -383,38 +369,23 @@ static int mpc52xx_irqhost_xlate(struct irq_host *h, struct device_node *ct,
383 369
384 intrvect_l1 = (int)intspec[0]; 370 intrvect_l1 = (int)intspec[0];
385 intrvect_l2 = (int)intspec[1]; 371 intrvect_l2 = (int)intspec[1];
386 intrvect_type = (int)intspec[2]; 372 intrvect_type = (int)intspec[2] & 0x3;
387 373
388 intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) & 374 intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) &
389 MPC52xx_IRQ_L1_MASK; 375 MPC52xx_IRQ_L1_MASK;
390 intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK; 376 intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK;
391 377
392 pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
393 intrvect_l2);
394
395 *out_hwirq = intrvect_linux; 378 *out_hwirq = intrvect_linux;
396 *out_flags = mpc52xx_map_senses[intrvect_type]; 379 *out_flags = IRQ_TYPE_LEVEL_LOW;
380 if (mpc52xx_is_extirq(intrvect_l1, intrvect_l2))
381 *out_flags = mpc52xx_map_senses[intrvect_type];
397 382
383 pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
384 intrvect_l2);
398 return 0; 385 return 0;
399} 386}
400 387
401/** 388/**
402 * mpc52xx_irqx_gettype - determine the IRQ sense type (level/edge)
403 *
404 * Only external IRQs need this.
405 */
406static int mpc52xx_irqx_gettype(int irq)
407{
408 int type;
409 u32 ctrl_reg;
410
411 ctrl_reg = in_be32(&intr->ctrl);
412 type = (ctrl_reg >> (22 - irq * 2)) & 0x3;
413
414 return mpc52xx_map_senses[type];
415}
416
417/**
418 * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure 389 * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure
419 */ 390 */
420static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq, 391static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
@@ -422,68 +393,46 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
422{ 393{
423 int l1irq; 394 int l1irq;
424 int l2irq; 395 int l2irq;
425 struct irq_chip *good_irqchip; 396 struct irq_chip *irqchip;
426 void *good_handle; 397 void *hndlr;
427 int type; 398 int type;
399 u32 reg;
428 400
429 l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET; 401 l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
430 l2irq = irq & MPC52xx_IRQ_L2_MASK; 402 l2irq = irq & MPC52xx_IRQ_L2_MASK;
431 403
432 /* 404 /*
433 * Most of ours IRQs will be level low 405 * External IRQs are handled differently by the hardware so they are
434 * Only external IRQs on some platform may be others 406 * handled by a dedicated irq_chip structure.
435 */ 407 */
436 type = IRQ_TYPE_LEVEL_LOW; 408 if (mpc52xx_is_extirq(l1irq, l2irq)) {
409 reg = in_be32(&intr->ctrl);
410 type = mpc52xx_map_senses[(reg >> (22 - l2irq * 2)) & 0x3];
411 if ((type == IRQ_TYPE_EDGE_FALLING) ||
412 (type == IRQ_TYPE_EDGE_RISING))
413 hndlr = handle_edge_irq;
414 else
415 hndlr = handle_level_irq;
416
417 set_irq_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
418 pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n",
419 __func__, l2irq, virq, (int)irq, type);
420 return 0;
421 }
437 422
423 /* It is an internal SOC irq. Choose the correct irq_chip */
438 switch (l1irq) { 424 switch (l1irq) {
439 case MPC52xx_IRQ_L1_CRIT: 425 case MPC52xx_IRQ_L1_MAIN: irqchip = &mpc52xx_main_irqchip; break;
440 pr_debug("%s: Critical. l2=%x\n", __func__, l2irq); 426 case MPC52xx_IRQ_L1_PERP: irqchip = &mpc52xx_periph_irqchip; break;
441 427 case MPC52xx_IRQ_L1_SDMA: irqchip = &mpc52xx_sdma_irqchip; break;
442 BUG_ON(l2irq != 0);
443
444 type = mpc52xx_irqx_gettype(l2irq);
445 good_irqchip = &mpc52xx_extirq_irqchip;
446 break;
447
448 case MPC52xx_IRQ_L1_MAIN:
449 pr_debug("%s: Main IRQ[1-3] l2=%x\n", __func__, l2irq);
450
451 if ((l2irq >= 1) && (l2irq <= 3)) {
452 type = mpc52xx_irqx_gettype(l2irq);
453 good_irqchip = &mpc52xx_extirq_irqchip;
454 } else {
455 good_irqchip = &mpc52xx_main_irqchip;
456 }
457 break;
458
459 case MPC52xx_IRQ_L1_PERP:
460 pr_debug("%s: Peripherals. l2=%x\n", __func__, l2irq);
461 good_irqchip = &mpc52xx_periph_irqchip;
462 break;
463
464 case MPC52xx_IRQ_L1_SDMA:
465 pr_debug("%s: SDMA. l2=%x\n", __func__, l2irq);
466 good_irqchip = &mpc52xx_sdma_irqchip;
467 break;
468
469 default: 428 default:
470 pr_err("%s: invalid virq requested (0x%x)\n", __func__, virq); 429 pr_err("%s: invalid irq: virq=%i, l1=%i, l2=%i\n",
430 __func__, virq, l1irq, l2irq);
471 return -EINVAL; 431 return -EINVAL;
472 } 432 }
473 433
474 switch (type) { 434 set_irq_chip_and_handler(virq, irqchip, handle_level_irq);
475 case IRQ_TYPE_EDGE_FALLING: 435 pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq);
476 case IRQ_TYPE_EDGE_RISING:
477 good_handle = handle_edge_irq;
478 break;
479 default:
480 good_handle = handle_level_irq;
481 }
482
483 set_irq_chip_and_handler(virq, good_irqchip, good_handle);
484
485 pr_debug("%s: virq=%x, hw=%x. type=%x\n", __func__, virq,
486 (int)irq, type);
487 436
488 return 0; 437 return 0;
489} 438}
@@ -522,6 +471,8 @@ void __init mpc52xx_init_irq(void)
522 panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. " 471 panic(__FILE__ ": find_and_map failed on 'mpc5200-bestcomm'. "
523 "Check node !"); 472 "Check node !");
524 473
474 pr_debug("MPC5200 IRQ controller mapped to 0x%p\n", intr);
475
525 /* Disable all interrupt sources. */ 476 /* Disable all interrupt sources. */
526 out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */ 477 out_be32(&sdma->IntPend, 0xffffffff); /* 1 means clear pending */
527 out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */ 478 out_be32(&sdma->IntMask, 0xffffffff); /* 1 means disabled */
@@ -613,8 +564,5 @@ unsigned int mpc52xx_get_irq(void)
613 } 564 }
614 } 565 }
615 566
616 pr_debug("%s: irq=%x. virq=%d\n", __func__, irq,
617 irq_linear_revmap(mpc52xx_irqhost, irq));
618
619 return irq_linear_revmap(mpc52xx_irqhost, irq); 567 return irq_linear_revmap(mpc52xx_irqhost, irq);
620} 568}
diff --git a/arch/powerpc/platforms/83xx/mpc831x_rdb.c b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
index 91a2c80b9d72..0b4f883b20eb 100644
--- a/arch/powerpc/platforms/83xx/mpc831x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc831x_rdb.c
@@ -38,6 +38,8 @@ static void __init mpc831x_rdb_setup_arch(void)
38#ifdef CONFIG_PCI 38#ifdef CONFIG_PCI
39 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") 39 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
40 mpc83xx_add_bridge(np); 40 mpc83xx_add_bridge(np);
41 for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
42 mpc83xx_add_bridge(np);
41#endif 43#endif
42 mpc831x_usb_cfg(); 44 mpc831x_usb_cfg();
43} 45}
diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c b/arch/powerpc/platforms/83xx/mpc837x_mds.c
index 530ef990ca7c..634785cc4523 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c
@@ -84,14 +84,10 @@ static void __init mpc837x_mds_setup_arch(void)
84 ppc_md.progress("mpc837x_mds_setup_arch()", 0); 84 ppc_md.progress("mpc837x_mds_setup_arch()", 0);
85 85
86#ifdef CONFIG_PCI 86#ifdef CONFIG_PCI
87 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") { 87 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
88 if (!of_device_is_available(np)) { 88 mpc83xx_add_bridge(np);
89 pr_warning("%s: disabled by the firmware.\n", 89 for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
90 np->full_name);
91 continue;
92 }
93 mpc83xx_add_bridge(np); 90 mpc83xx_add_bridge(np);
94 }
95#endif 91#endif
96 mpc837xmds_usb_cfg(); 92 mpc837xmds_usb_cfg();
97} 93}
diff --git a/arch/powerpc/platforms/83xx/mpc837x_rdb.c b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
index 1d096545322b..3d7b953d40e1 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_rdb.c
@@ -38,6 +38,8 @@ static void __init mpc837x_rdb_setup_arch(void)
38#ifdef CONFIG_PCI 38#ifdef CONFIG_PCI
39 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci") 39 for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
40 mpc83xx_add_bridge(np); 40 mpc83xx_add_bridge(np);
41 for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
42 mpc83xx_add_bridge(np);
41#endif 43#endif
42 mpc837x_usb_cfg(); 44 mpc837x_usb_cfg();
43} 45}
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 8e5693935975..fa276c689cf9 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -31,6 +31,14 @@ config MPC8610_HPCD
31 help 31 help
32 This option enables support for the MPC8610 HPCD board. 32 This option enables support for the MPC8610 HPCD board.
33 33
34config GEF_SBC310
35 bool "GE Fanuc SBC310"
36 select DEFAULT_UIMAGE
37 select GENERIC_GPIO
38 select ARCH_REQUIRE_GPIOLIB
39 help
40 This option enables support for GE Fanuc's SBC310.
41
34config GEF_SBC610 42config GEF_SBC610
35 bool "GE Fanuc SBC610" 43 bool "GE Fanuc SBC610"
36 select DEFAULT_UIMAGE 44 select DEFAULT_UIMAGE
@@ -48,7 +56,7 @@ config MPC8641
48 select FSL_PCI if PCI 56 select FSL_PCI if PCI
49 select PPC_UDBG_16550 57 select PPC_UDBG_16550
50 select MPIC 58 select MPIC
51 default y if MPC8641_HPCN || SBC8641D || GEF_SBC610 59 default y if MPC8641_HPCN || SBC8641D || GEF_SBC610 || GEF_SBC310
52 60
53config MPC8610 61config MPC8610
54 bool 62 bool
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index 31e540c2ebbc..7c080da4523a 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_SBC8641D) += sbc8641d.o
9obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o 9obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
10gef-gpio-$(CONFIG_GPIOLIB) += gef_gpio.o 10gef-gpio-$(CONFIG_GPIOLIB) += gef_gpio.o
11obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o gef_pic.o $(gef-gpio-y) 11obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o gef_pic.o $(gef-gpio-y)
12obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o gef_pic.o $(gef-gpio-y)
diff --git a/arch/powerpc/platforms/86xx/gef_gpio.c b/arch/powerpc/platforms/86xx/gef_gpio.c
index 85b2800f4cb7..b2ea8875adba 100644
--- a/arch/powerpc/platforms/86xx/gef_gpio.c
+++ b/arch/powerpc/platforms/86xx/gef_gpio.c
@@ -37,8 +37,6 @@
37#define GEF_GPIO_OVERRUN 0x1C 37#define GEF_GPIO_OVERRUN 0x1C
38#define GEF_GPIO_MODE 0x20 38#define GEF_GPIO_MODE 0x20
39 39
40#define NUM_GPIO 19
41
42static void _gef_gpio_set(void __iomem *reg, unsigned int offset, int value) 40static void _gef_gpio_set(void __iomem *reg, unsigned int offset, int value)
43{ 41{
44 unsigned int data; 42 unsigned int data;
@@ -103,10 +101,10 @@ static void gef_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
103static int __init gef_gpio_init(void) 101static int __init gef_gpio_init(void)
104{ 102{
105 struct device_node *np; 103 struct device_node *np;
104 int retval;
105 struct of_mm_gpio_chip *gef_gpio_chip;
106 106
107 for_each_compatible_node(np, NULL, "gef,sbc610-gpio") { 107 for_each_compatible_node(np, NULL, "gef,sbc610-gpio") {
108 int retval;
109 struct of_mm_gpio_chip *gef_gpio_chip;
110 108
111 pr_debug("%s: Initialising GEF GPIO\n", np->full_name); 109 pr_debug("%s: Initialising GEF GPIO\n", np->full_name);
112 110
@@ -120,7 +118,35 @@ static int __init gef_gpio_init(void)
120 118
121 /* Setup pointers to chip functions */ 119 /* Setup pointers to chip functions */
122 gef_gpio_chip->of_gc.gpio_cells = 2; 120 gef_gpio_chip->of_gc.gpio_cells = 2;
123 gef_gpio_chip->of_gc.gc.ngpio = NUM_GPIO; 121 gef_gpio_chip->of_gc.gc.ngpio = 19;
122 gef_gpio_chip->of_gc.gc.direction_input = gef_gpio_dir_in;
123 gef_gpio_chip->of_gc.gc.direction_output = gef_gpio_dir_out;
124 gef_gpio_chip->of_gc.gc.get = gef_gpio_get;
125 gef_gpio_chip->of_gc.gc.set = gef_gpio_set;
126
127 /* This function adds a memory mapped GPIO chip */
128 retval = of_mm_gpiochip_add(np, gef_gpio_chip);
129 if (retval) {
130 kfree(gef_gpio_chip);
131 pr_err("%s: Unable to add GPIO\n", np->full_name);
132 }
133 }
134
135 for_each_compatible_node(np, NULL, "gef,sbc310-gpio") {
136
137 pr_debug("%s: Initialising GEF GPIO\n", np->full_name);
138
139 /* Allocate chip structure */
140 gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
141 if (!gef_gpio_chip) {
142 pr_err("%s: Unable to allocate structure\n",
143 np->full_name);
144 continue;
145 }
146
147 /* Setup pointers to chip functions */
148 gef_gpio_chip->of_gc.gpio_cells = 2;
149 gef_gpio_chip->of_gc.gc.ngpio = 6;
124 gef_gpio_chip->of_gc.gc.direction_input = gef_gpio_dir_in; 150 gef_gpio_chip->of_gc.gc.direction_input = gef_gpio_dir_in;
125 gef_gpio_chip->of_gc.gc.direction_output = gef_gpio_dir_out; 151 gef_gpio_chip->of_gc.gc.direction_output = gef_gpio_dir_out;
126 gef_gpio_chip->of_gc.gc.get = gef_gpio_get; 152 gef_gpio_chip->of_gc.gc.get = gef_gpio_get;
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c b/arch/powerpc/platforms/86xx/gef_sbc310.c
new file mode 100644
index 000000000000..0f20172af84b
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -0,0 +1,230 @@
1/*
2 * GE Fanuc SBC310 board support
3 *
4 * Author: Martyn Welch <martyn.welch@gefanuc.com>
5 *
6 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 *
16 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
17 */
18
19#include <linux/stddef.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/kdev_t.h>
23#include <linux/delay.h>
24#include <linux/seq_file.h>
25#include <linux/of_platform.h>
26
27#include <asm/system.h>
28#include <asm/time.h>
29#include <asm/machdep.h>
30#include <asm/pci-bridge.h>
31#include <asm/mpc86xx.h>
32#include <asm/prom.h>
33#include <mm/mmu_decl.h>
34#include <asm/udbg.h>
35
36#include <asm/mpic.h>
37
38#include <sysdev/fsl_pci.h>
39#include <sysdev/fsl_soc.h>
40
41#include "mpc86xx.h"
42#include "gef_pic.h"
43
44#undef DEBUG
45
46#ifdef DEBUG
47#define DBG (fmt...) do { printk(KERN_ERR "SBC310: " fmt); } while (0)
48#else
49#define DBG (fmt...) do { } while (0)
50#endif
51
52void __iomem *sbc310_regs;
53
54static void __init gef_sbc310_init_irq(void)
55{
56 struct device_node *cascade_node = NULL;
57
58 mpc86xx_init_irq();
59
60 /*
61 * There is a simple interrupt handler in the main FPGA, this needs
62 * to be cascaded into the MPIC
63 */
64 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic");
65 if (!cascade_node) {
66 printk(KERN_WARNING "SBC310: No FPGA PIC\n");
67 return;
68 }
69
70 gef_pic_init(cascade_node);
71 of_node_put(cascade_node);
72}
73
74static void __init gef_sbc310_setup_arch(void)
75{
76 struct device_node *regs;
77#ifdef CONFIG_PCI
78 struct device_node *np;
79
80 for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
81 fsl_add_bridge(np, 1);
82 }
83#endif
84
85 printk(KERN_INFO "GE Fanuc Intelligent Platforms SBC310 6U VPX SBC\n");
86
87#ifdef CONFIG_SMP
88 mpc86xx_smp_init();
89#endif
90
91 /* Remap basic board registers */
92 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs");
93 if (regs) {
94 sbc310_regs = of_iomap(regs, 0);
95 if (sbc310_regs == NULL)
96 printk(KERN_WARNING "Unable to map board registers\n");
97 of_node_put(regs);
98 }
99}
100
101/* Return the PCB revision */
102static unsigned int gef_sbc310_get_board_id(void)
103{
104 unsigned int reg;
105
106 reg = ioread32(sbc310_regs);
107 return reg & 0xff;
108}
109
110/* Return the PCB revision */
111static unsigned int gef_sbc310_get_pcb_rev(void)
112{
113 unsigned int reg;
114
115 reg = ioread32(sbc310_regs);
116 return (reg >> 8) & 0xff;
117}
118
119/* Return the board (software) revision */
120static unsigned int gef_sbc310_get_board_rev(void)
121{
122 unsigned int reg;
123
124 reg = ioread32(sbc310_regs);
125 return (reg >> 16) & 0xff;
126}
127
128/* Return the FPGA revision */
129static unsigned int gef_sbc310_get_fpga_rev(void)
130{
131 unsigned int reg;
132
133 reg = ioread32(sbc310_regs);
134 return (reg >> 24) & 0xf;
135}
136
137static void gef_sbc310_show_cpuinfo(struct seq_file *m)
138{
139 uint svid = mfspr(SPRN_SVR);
140
141 seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
142
143 seq_printf(m, "Board ID\t: 0x%2.2x\n", gef_sbc310_get_board_id());
144 seq_printf(m, "Revision\t: %u%c\n", gef_sbc310_get_pcb_rev(),
145 ('A' + gef_sbc310_get_board_rev() - 1));
146 seq_printf(m, "FPGA Revision\t: %u\n", gef_sbc310_get_fpga_rev());
147
148 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
149
150}
151
152static void __init gef_sbc310_nec_fixup(struct pci_dev *pdev)
153{
154 unsigned int val;
155
156 printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
157
158 /* Ensure only ports 1 & 2 are enabled */
159 pci_read_config_dword(pdev, 0xe0, &val);
160 pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x2);
161
162 /* System clock is 48-MHz Oscillator and EHCI Enabled. */
163 pci_write_config_dword(pdev, 0xe4, 1 << 5);
164}
165DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
166 gef_sbc310_nec_fixup);
167
168/*
169 * Called very early, device-tree isn't unflattened
170 *
171 * This function is called to determine whether the BSP is compatible with the
172 * supplied device-tree, which is assumed to be the correct one for the actual
173 * board. It is expected thati, in the future, a kernel may support multiple
174 * boards.
175 */
176static int __init gef_sbc310_probe(void)
177{
178 unsigned long root = of_get_flat_dt_root();
179
180 if (of_flat_dt_is_compatible(root, "gef,sbc310"))
181 return 1;
182
183 return 0;
184}
185
186static long __init mpc86xx_time_init(void)
187{
188 unsigned int temp;
189
190 /* Set the time base to zero */
191 mtspr(SPRN_TBWL, 0);
192 mtspr(SPRN_TBWU, 0);
193
194 temp = mfspr(SPRN_HID0);
195 temp |= HID0_TBEN;
196 mtspr(SPRN_HID0, temp);
197 asm volatile("isync");
198
199 return 0;
200}
201
202static __initdata struct of_device_id of_bus_ids[] = {
203 { .compatible = "simple-bus", },
204 {},
205};
206
207static int __init declare_of_platform_devices(void)
208{
209 printk(KERN_DEBUG "Probe platform devices\n");
210 of_platform_bus_probe(NULL, of_bus_ids, NULL);
211
212 return 0;
213}
214machine_device_initcall(gef_sbc310, declare_of_platform_devices);
215
216define_machine(gef_sbc310) {
217 .name = "GE Fanuc SBC310",
218 .probe = gef_sbc310_probe,
219 .setup_arch = gef_sbc310_setup_arch,
220 .init_IRQ = gef_sbc310_init_irq,
221 .show_cpuinfo = gef_sbc310_show_cpuinfo,
222 .get_irq = mpic_get_irq,
223 .restart = fsl_rstcr_restart,
224 .time_init = mpc86xx_time_init,
225 .calibrate_decr = generic_calibrate_decr,
226 .progress = udbg_progress,
227#ifdef CONFIG_PCI
228 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
229#endif
230};
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 200b9cb900ea..b25404ca2216 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -28,6 +28,7 @@ source "arch/powerpc/platforms/86xx/Kconfig"
28source "arch/powerpc/platforms/embedded6xx/Kconfig" 28source "arch/powerpc/platforms/embedded6xx/Kconfig"
29source "arch/powerpc/platforms/44x/Kconfig" 29source "arch/powerpc/platforms/44x/Kconfig"
30source "arch/powerpc/platforms/40x/Kconfig" 30source "arch/powerpc/platforms/40x/Kconfig"
31source "arch/powerpc/platforms/amigaone/Kconfig"
31 32
32config PPC_NATIVE 33config PPC_NATIVE
33 bool 34 bool
diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile
index 8079e0b4fd69..f7419198e635 100644
--- a/arch/powerpc/platforms/Makefile
+++ b/arch/powerpc/platforms/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_PPC_PASEMI) += pasemi/
19obj-$(CONFIG_PPC_CELL) += cell/ 19obj-$(CONFIG_PPC_CELL) += cell/
20obj-$(CONFIG_PPC_PS3) += ps3/ 20obj-$(CONFIG_PPC_PS3) += ps3/
21obj-$(CONFIG_EMBEDDED6xx) += embedded6xx/ 21obj-$(CONFIG_EMBEDDED6xx) += embedded6xx/
22obj-$(CONFIG_AMIGAONE) += amigaone/
diff --git a/arch/powerpc/platforms/amigaone/Kconfig b/arch/powerpc/platforms/amigaone/Kconfig
new file mode 100644
index 000000000000..9276a96cedee
--- /dev/null
+++ b/arch/powerpc/platforms/amigaone/Kconfig
@@ -0,0 +1,18 @@
1config AMIGAONE
2 bool "Eyetech AmigaOne/MAI Teron"
3 depends on PPC32 && BROKEN_ON_SMP && PPC_MULTIPLATFORM
4 select PPC_I8259
5 select PPC_INDIRECT_PCI
6 select PPC_UDBG_16550
7 select PCI
8 select NOT_COHERENT_CACHE
9 select CHECK_CACHE_COHERENCY
10 select DEFAULT_UIMAGE
11 select PCSPKR_PLATFORM
12 help
13 Select AmigaOne for the following machines:
14 - AmigaOne SE/Teron CX (G3 only)
15 - AmigaOne XE/Teron PX
16 - uA1/Teron mini
17 More information is available at:
18 <http://amigaone-linux.sourceforge.net/>.
diff --git a/arch/powerpc/platforms/amigaone/Makefile b/arch/powerpc/platforms/amigaone/Makefile
new file mode 100644
index 000000000000..e6885b3b2ee7
--- /dev/null
+++ b/arch/powerpc/platforms/amigaone/Makefile
@@ -0,0 +1 @@
obj-y += setup.o
diff --git a/arch/powerpc/platforms/amigaone/setup.c b/arch/powerpc/platforms/amigaone/setup.c
new file mode 100644
index 000000000000..443035366c12
--- /dev/null
+++ b/arch/powerpc/platforms/amigaone/setup.c
@@ -0,0 +1,170 @@
1/*
2 * AmigaOne platform setup
3 *
4 * Copyright 2008 Gerhard Pircher (gerhard_pircher@gmx.net)
5 *
6 * Based on original amigaone_setup.c source code
7 * Copyright 2003 by Hans-Joerg Frieden and Thomas Frieden
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/kernel.h>
16#include <linux/seq_file.h>
17#include <linux/utsrelease.h>
18
19#include <asm/machdep.h>
20#include <asm/cputable.h>
21#include <asm/prom.h>
22#include <asm/pci-bridge.h>
23#include <asm/i8259.h>
24#include <asm/time.h>
25#include <asm/udbg.h>
26
27extern void __flush_disable_L1(void);
28
29void amigaone_show_cpuinfo(struct seq_file *m)
30{
31 seq_printf(m, "vendor\t\t: Eyetech Ltd.\n");
32}
33
34static int __init amigaone_add_bridge(struct device_node *dev)
35{
36 const u32 *cfg_addr, *cfg_data;
37 int len;
38 const int *bus_range;
39 struct pci_controller *hose;
40
41 printk(KERN_INFO "Adding PCI host bridge %s\n", dev->full_name);
42
43 cfg_addr = of_get_address(dev, 0, NULL, NULL);
44 cfg_data = of_get_address(dev, 1, NULL, NULL);
45 if ((cfg_addr == NULL) || (cfg_data == NULL))
46 return -ENODEV;
47
48 bus_range = of_get_property(dev, "bus-range", &len);
49 if ((bus_range == NULL) || (len < 2 * sizeof(int)))
50 printk(KERN_WARNING "Can't get bus-range for %s, assume"
51 " bus 0\n", dev->full_name);
52
53 hose = pcibios_alloc_controller(dev);
54 if (hose == NULL)
55 return -ENOMEM;
56
57 hose->first_busno = bus_range ? bus_range[0] : 0;
58 hose->last_busno = bus_range ? bus_range[1] : 0xff;
59
60 setup_indirect_pci(hose, cfg_addr[0], cfg_data[0], 0);
61
62 /* Interpret the "ranges" property */
63 /* This also maps the I/O region and sets isa_io/mem_base */
64 pci_process_bridge_OF_ranges(hose, dev, 1);
65
66 return 0;
67}
68
69void __init amigaone_setup_arch(void)
70{
71 struct device_node *np;
72 int phb = -ENODEV;
73
74 /* Lookup PCI host bridges. */
75 for_each_compatible_node(np, "pci", "mai-logic,articia-s")
76 phb = amigaone_add_bridge(np);
77
78 BUG_ON(phb != 0);
79
80 if (ppc_md.progress)
81 ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0);
82}
83
84void __init amigaone_init_IRQ(void)
85{
86 struct device_node *pic, *np = NULL;
87 const unsigned long *prop = NULL;
88 unsigned long int_ack = 0;
89
90 /* Search for ISA interrupt controller. */
91 pic = of_find_compatible_node(NULL, "interrupt-controller",
92 "pnpPNP,000");
93 BUG_ON(pic == NULL);
94
95 /* Look for interrupt acknowledge address in the PCI root node. */
96 np = of_find_compatible_node(NULL, "pci", "mai-logic,articia-s");
97 if (np) {
98 prop = of_get_property(np, "8259-interrupt-acknowledge", NULL);
99 if (prop)
100 int_ack = prop[0];
101 of_node_put(np);
102 }
103
104 if (int_ack == 0)
105 printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
106 " address, polling\n");
107
108 i8259_init(pic, int_ack);
109 ppc_md.get_irq = i8259_irq;
110 irq_set_default_host(i8259_get_host());
111}
112
113void __init amigaone_init(void)
114{
115 request_region(0x00, 0x20, "dma1");
116 request_region(0x40, 0x20, "timer");
117 request_region(0x80, 0x10, "dma page reg");
118 request_region(0xc0, 0x20, "dma2");
119}
120
121void amigaone_restart(char *cmd)
122{
123 local_irq_disable();
124
125 /* Flush and disable caches. */
126 __flush_disable_L1();
127
128 /* Set SRR0 to the reset vector and turn on MSR_IP. */
129 mtspr(SPRN_SRR0, 0xfff00100);
130 mtspr(SPRN_SRR1, MSR_IP);
131
132 /* Do an rfi to jump back to firmware. */
133 __asm__ __volatile__("rfi" : : : "memory");
134
135 /* Not reached. */
136 while (1);
137}
138
139static int __init amigaone_probe(void)
140{
141 unsigned long root = of_get_flat_dt_root();
142
143 if (of_flat_dt_is_compatible(root, "eyetech,amigaone")) {
144 /*
145 * Coherent memory access cause complete system lockup! Thus
146 * disable this CPU feature, even if the CPU needs it.
147 */
148 cur_cpu_spec->cpu_features &= ~CPU_FTR_NEED_COHERENT;
149
150 ISA_DMA_THRESHOLD = 0x00ffffff;
151 DMA_MODE_READ = 0x44;
152 DMA_MODE_WRITE = 0x48;
153
154 return 1;
155 }
156
157 return 0;
158}
159
160define_machine(amigaone) {
161 .name = "AmigaOne",
162 .probe = amigaone_probe,
163 .setup_arch = amigaone_setup_arch,
164 .init = amigaone_init,
165 .show_cpuinfo = amigaone_show_cpuinfo,
166 .init_IRQ = amigaone_init_IRQ,
167 .restart = amigaone_restart,
168 .calibrate_decr = generic_calibrate_decr,
169 .progress = udbg_progress,
170};
diff --git a/arch/powerpc/platforms/chrp/pegasos_eth.c b/arch/powerpc/platforms/chrp/pegasos_eth.c
index 130ff72d99dd..039fc8e82199 100644
--- a/arch/powerpc/platforms/chrp/pegasos_eth.c
+++ b/arch/powerpc/platforms/chrp/pegasos_eth.c
@@ -21,8 +21,8 @@
21#define PEGASOS2_SRAM_BASE (0xf2000000) 21#define PEGASOS2_SRAM_BASE (0xf2000000)
22#define PEGASOS2_SRAM_SIZE (256*1024) 22#define PEGASOS2_SRAM_SIZE (256*1024)
23 23
24#define PEGASOS2_SRAM_BASE_ETH0 (PEGASOS2_SRAM_BASE) 24#define PEGASOS2_SRAM_BASE_ETH_PORT0 (PEGASOS2_SRAM_BASE)
25#define PEGASOS2_SRAM_BASE_ETH1 (PEGASOS2_SRAM_BASE_ETH0 + (PEGASOS2_SRAM_SIZE / 2) ) 25#define PEGASOS2_SRAM_BASE_ETH_PORT1 (PEGASOS2_SRAM_BASE_ETH_PORT0 + (PEGASOS2_SRAM_SIZE / 2) )
26 26
27 27
28#define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4) 28#define PEGASOS2_SRAM_RXRING_SIZE (PEGASOS2_SRAM_SIZE/4)
@@ -47,75 +47,42 @@ static struct platform_device mv643xx_eth_shared_device = {
47 .resource = mv643xx_eth_shared_resources, 47 .resource = mv643xx_eth_shared_resources,
48}; 48};
49 49
50static struct resource mv643xx_eth0_resources[] = { 50static struct resource mv643xx_eth_port1_resources[] = {
51 [0] = { 51 [0] = {
52 .name = "eth0 irq", 52 .name = "eth port1 irq",
53 .start = 9, 53 .start = 9,
54 .end = 9, 54 .end = 9,
55 .flags = IORESOURCE_IRQ, 55 .flags = IORESOURCE_IRQ,
56 }, 56 },
57}; 57};
58 58
59 59static struct mv643xx_eth_platform_data eth_port1_pd = {
60static struct mv643xx_eth_platform_data eth0_pd = {
61 .shared = &mv643xx_eth_shared_device,
62 .port_number = 0,
63
64 .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH0,
65 .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
66 .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
67
68 .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH0 + PEGASOS2_SRAM_TXRING_SIZE,
69 .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
70 .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
71};
72
73static struct platform_device eth0_device = {
74 .name = MV643XX_ETH_NAME,
75 .id = 0,
76 .num_resources = ARRAY_SIZE(mv643xx_eth0_resources),
77 .resource = mv643xx_eth0_resources,
78 .dev = {
79 .platform_data = &eth0_pd,
80 },
81};
82
83static struct resource mv643xx_eth1_resources[] = {
84 [0] = {
85 .name = "eth1 irq",
86 .start = 9,
87 .end = 9,
88 .flags = IORESOURCE_IRQ,
89 },
90};
91
92static struct mv643xx_eth_platform_data eth1_pd = {
93 .shared = &mv643xx_eth_shared_device, 60 .shared = &mv643xx_eth_shared_device,
94 .port_number = 1, 61 .port_number = 1,
62 .phy_addr = MV643XX_ETH_PHY_ADDR(7),
95 63
96 .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH1, 64 .tx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1,
97 .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE, 65 .tx_sram_size = PEGASOS2_SRAM_TXRING_SIZE,
98 .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16, 66 .tx_queue_size = PEGASOS2_SRAM_TXRING_SIZE/16,
99 67
100 .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH1 + PEGASOS2_SRAM_TXRING_SIZE, 68 .rx_sram_addr = PEGASOS2_SRAM_BASE_ETH_PORT1 + PEGASOS2_SRAM_TXRING_SIZE,
101 .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE, 69 .rx_sram_size = PEGASOS2_SRAM_RXRING_SIZE,
102 .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16, 70 .rx_queue_size = PEGASOS2_SRAM_RXRING_SIZE/16,
103}; 71};
104 72
105static struct platform_device eth1_device = { 73static struct platform_device eth_port1_device = {
106 .name = MV643XX_ETH_NAME, 74 .name = MV643XX_ETH_NAME,
107 .id = 1, 75 .id = 1,
108 .num_resources = ARRAY_SIZE(mv643xx_eth1_resources), 76 .num_resources = ARRAY_SIZE(mv643xx_eth_port1_resources),
109 .resource = mv643xx_eth1_resources, 77 .resource = mv643xx_eth_port1_resources,
110 .dev = { 78 .dev = {
111 .platform_data = &eth1_pd, 79 .platform_data = &eth_port1_pd,
112 }, 80 },
113}; 81};
114 82
115static struct platform_device *mv643xx_eth_pd_devs[] __initdata = { 83static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
116 &mv643xx_eth_shared_device, 84 &mv643xx_eth_shared_device,
117 &eth0_device, 85 &eth_port1_device,
118 &eth1_device,
119}; 86};
120 87
121/***********/ 88/***********/
@@ -191,15 +158,10 @@ static int __init mv643xx_eth_add_pds(void)
191 158
192 if ( Enable_SRAM() < 0) 159 if ( Enable_SRAM() < 0)
193 { 160 {
194 eth0_pd.tx_sram_addr = 0; 161 eth_port1_pd.tx_sram_addr = 0;
195 eth0_pd.tx_sram_size = 0; 162 eth_port1_pd.tx_sram_size = 0;
196 eth0_pd.rx_sram_addr = 0; 163 eth_port1_pd.rx_sram_addr = 0;
197 eth0_pd.rx_sram_size = 0; 164 eth_port1_pd.rx_sram_size = 0;
198
199 eth1_pd.tx_sram_addr = 0;
200 eth1_pd.tx_sram_size = 0;
201 eth1_pd.rx_sram_addr = 0;
202 eth1_pd.rx_sram_size = 0;
203 165
204#ifdef BE_VERBOSE 166#ifdef BE_VERBOSE
205 printk("Pegasos II/Marvell MV64361: Can't enable the " 167 printk("Pegasos II/Marvell MV64361: Can't enable the "
diff --git a/arch/powerpc/platforms/pseries/eeh_driver.c b/arch/powerpc/platforms/pseries/eeh_driver.c
index 0ad56ff7b4a0..380420f8c400 100644
--- a/arch/powerpc/platforms/pseries/eeh_driver.c
+++ b/arch/powerpc/platforms/pseries/eeh_driver.c
@@ -79,6 +79,40 @@ static int irq_in_use(unsigned int irq)
79 return rc; 79 return rc;
80} 80}
81 81
82/**
83 * eeh_disable_irq - disable interrupt for the recovering device
84 */
85static void eeh_disable_irq(struct pci_dev *dev)
86{
87 struct device_node *dn = pci_device_to_OF_node(dev);
88
89 /* Don't disable MSI and MSI-X interrupts. They are
90 * effectively disabled by the DMA Stopped state
91 * when an EEH error occurs.
92 */
93 if (dev->msi_enabled || dev->msix_enabled)
94 return;
95
96 if (!irq_in_use(dev->irq))
97 return;
98
99 PCI_DN(dn)->eeh_mode |= EEH_MODE_IRQ_DISABLED;
100 disable_irq_nosync(dev->irq);
101}
102
103/**
104 * eeh_enable_irq - enable interrupt for the recovering device
105 */
106static void eeh_enable_irq(struct pci_dev *dev)
107{
108 struct device_node *dn = pci_device_to_OF_node(dev);
109
110 if ((PCI_DN(dn)->eeh_mode) & EEH_MODE_IRQ_DISABLED) {
111 PCI_DN(dn)->eeh_mode &= ~EEH_MODE_IRQ_DISABLED;
112 enable_irq(dev->irq);
113 }
114}
115
82/* ------------------------------------------------------- */ 116/* ------------------------------------------------------- */
83/** 117/**
84 * eeh_report_error - report pci error to each device driver 118 * eeh_report_error - report pci error to each device driver
@@ -98,11 +132,8 @@ static void eeh_report_error(struct pci_dev *dev, void *userdata)
98 if (!driver) 132 if (!driver)
99 return; 133 return;
100 134
101 if (irq_in_use (dev->irq)) { 135 eeh_disable_irq(dev);
102 struct device_node *dn = pci_device_to_OF_node(dev); 136
103 PCI_DN(dn)->eeh_mode |= EEH_MODE_IRQ_DISABLED;
104 disable_irq_nosync(dev->irq);
105 }
106 if (!driver->err_handler || 137 if (!driver->err_handler ||
107 !driver->err_handler->error_detected) 138 !driver->err_handler->error_detected)
108 return; 139 return;
@@ -147,15 +178,12 @@ static void eeh_report_reset(struct pci_dev *dev, void *userdata)
147{ 178{
148 enum pci_ers_result rc, *res = userdata; 179 enum pci_ers_result rc, *res = userdata;
149 struct pci_driver *driver = dev->driver; 180 struct pci_driver *driver = dev->driver;
150 struct device_node *dn = pci_device_to_OF_node(dev);
151 181
152 if (!driver) 182 if (!driver)
153 return; 183 return;
154 184
155 if ((PCI_DN(dn)->eeh_mode) & EEH_MODE_IRQ_DISABLED) { 185 eeh_enable_irq(dev);
156 PCI_DN(dn)->eeh_mode &= ~EEH_MODE_IRQ_DISABLED; 186
157 enable_irq(dev->irq);
158 }
159 if (!driver->err_handler || 187 if (!driver->err_handler ||
160 !driver->err_handler->slot_reset) 188 !driver->err_handler->slot_reset)
161 return; 189 return;
@@ -174,17 +202,14 @@ static void eeh_report_reset(struct pci_dev *dev, void *userdata)
174static void eeh_report_resume(struct pci_dev *dev, void *userdata) 202static void eeh_report_resume(struct pci_dev *dev, void *userdata)
175{ 203{
176 struct pci_driver *driver = dev->driver; 204 struct pci_driver *driver = dev->driver;
177 struct device_node *dn = pci_device_to_OF_node(dev);
178 205
179 dev->error_state = pci_channel_io_normal; 206 dev->error_state = pci_channel_io_normal;
180 207
181 if (!driver) 208 if (!driver)
182 return; 209 return;
183 210
184 if ((PCI_DN(dn)->eeh_mode) & EEH_MODE_IRQ_DISABLED) { 211 eeh_enable_irq(dev);
185 PCI_DN(dn)->eeh_mode &= ~EEH_MODE_IRQ_DISABLED; 212
186 enable_irq(dev->irq);
187 }
188 if (!driver->err_handler || 213 if (!driver->err_handler ||
189 !driver->err_handler->resume) 214 !driver->err_handler->resume)
190 return; 215 return;
@@ -208,15 +233,12 @@ static void eeh_report_failure(struct pci_dev *dev, void *userdata)
208 if (!driver) 233 if (!driver)
209 return; 234 return;
210 235
211 if (irq_in_use (dev->irq)) { 236 eeh_disable_irq(dev);
212 struct device_node *dn = pci_device_to_OF_node(dev); 237
213 PCI_DN(dn)->eeh_mode |= EEH_MODE_IRQ_DISABLED; 238 if (!driver->err_handler ||
214 disable_irq_nosync(dev->irq); 239 !driver->err_handler->error_detected)
215 }
216 if (!driver->err_handler)
217 return;
218 if (!driver->err_handler->error_detected)
219 return; 240 return;
241
220 driver->err_handler->error_detected(dev, pci_channel_io_perm_failure); 242 driver->err_handler->error_detected(dev, pci_channel_io_perm_failure);
221} 243}
222 244
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
index f15222bbe136..073b518338a3 100644
--- a/arch/powerpc/platforms/pseries/msi.c
+++ b/arch/powerpc/platforms/pseries/msi.c
@@ -71,11 +71,13 @@ static int rtas_change_msi(struct pci_dn *pdn, u32 func, u32 num_irqs)
71 } while (rtas_busy_delay(rc)); 71 } while (rtas_busy_delay(rc));
72 72
73 /* 73 /*
74 * If the RTAS call succeeded, check the number of irqs is actually 74 * If the RTAS call succeeded, return the number of irqs allocated.
75 * what we asked for. If not, return an error. 75 * If not, make sure we return a negative error code.
76 */ 76 */
77 if (rc == 0 && rtas_ret[0] != num_irqs) 77 if (rc == 0)
78 rc = -ENOSPC; 78 rc = rtas_ret[0];
79 else if (rc > 0)
80 rc = -rc;
79 81
80 pr_debug("rtas_msi: ibm,change_msi(func=%d,num=%d), got %d rc = %d\n", 82 pr_debug("rtas_msi: ibm,change_msi(func=%d,num=%d), got %d rc = %d\n",
81 func, num_irqs, rtas_ret[0], rc); 83 func, num_irqs, rtas_ret[0], rc);
@@ -91,7 +93,7 @@ static void rtas_disable_msi(struct pci_dev *pdev)
91 if (!pdn) 93 if (!pdn)
92 return; 94 return;
93 95
94 if (rtas_change_msi(pdn, RTAS_CHANGE_FN, 0)) 96 if (rtas_change_msi(pdn, RTAS_CHANGE_FN, 0) != 0)
95 pr_debug("rtas_msi: Setting MSIs to 0 failed!\n"); 97 pr_debug("rtas_msi: Setting MSIs to 0 failed!\n");
96} 98}
97 99
@@ -132,7 +134,7 @@ static void rtas_teardown_msi_irqs(struct pci_dev *pdev)
132 rtas_disable_msi(pdev); 134 rtas_disable_msi(pdev);
133} 135}
134 136
135static int check_req_msi(struct pci_dev *pdev, int nvec) 137static int check_req(struct pci_dev *pdev, int nvec, char *prop_name)
136{ 138{
137 struct device_node *dn; 139 struct device_node *dn;
138 struct pci_dn *pdn; 140 struct pci_dn *pdn;
@@ -144,24 +146,34 @@ static int check_req_msi(struct pci_dev *pdev, int nvec)
144 146
145 dn = pdn->node; 147 dn = pdn->node;
146 148
147 req_msi = of_get_property(dn, "ibm,req#msi", NULL); 149 req_msi = of_get_property(dn, prop_name, NULL);
148 if (!req_msi) { 150 if (!req_msi) {
149 pr_debug("rtas_msi: No ibm,req#msi on %s\n", dn->full_name); 151 pr_debug("rtas_msi: No %s on %s\n", prop_name, dn->full_name);
150 return -ENOENT; 152 return -ENOENT;
151 } 153 }
152 154
153 if (*req_msi < nvec) { 155 if (*req_msi < nvec) {
154 pr_debug("rtas_msi: ibm,req#msi requests < %d MSIs\n", nvec); 156 pr_debug("rtas_msi: %s requests < %d MSIs\n", prop_name, nvec);
155 return -ENOSPC; 157 return -ENOSPC;
156 } 158 }
157 159
158 return 0; 160 return 0;
159} 161}
160 162
163static int check_req_msi(struct pci_dev *pdev, int nvec)
164{
165 return check_req(pdev, nvec, "ibm,req#msi");
166}
167
168static int check_req_msix(struct pci_dev *pdev, int nvec)
169{
170 return check_req(pdev, nvec, "ibm,req#msi-x");
171}
172
161static int rtas_msi_check_device(struct pci_dev *pdev, int nvec, int type) 173static int rtas_msi_check_device(struct pci_dev *pdev, int nvec, int type)
162{ 174{
163 if (type == PCI_CAP_ID_MSIX) 175 if (type == PCI_CAP_ID_MSIX)
164 pr_debug("rtas_msi: MSI-X untested, trying anyway.\n"); 176 return check_req_msix(pdev, nvec);
165 177
166 return check_req_msi(pdev, nvec); 178 return check_req_msi(pdev, nvec);
167} 179}
@@ -185,21 +197,21 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
185 if (type == PCI_CAP_ID_MSI) { 197 if (type == PCI_CAP_ID_MSI) {
186 rc = rtas_change_msi(pdn, RTAS_CHANGE_MSI_FN, nvec); 198 rc = rtas_change_msi(pdn, RTAS_CHANGE_MSI_FN, nvec);
187 199
188 if (rc) { 200 if (rc < 0) {
189 pr_debug("rtas_msi: trying the old firmware call.\n"); 201 pr_debug("rtas_msi: trying the old firmware call.\n");
190 rc = rtas_change_msi(pdn, RTAS_CHANGE_FN, nvec); 202 rc = rtas_change_msi(pdn, RTAS_CHANGE_FN, nvec);
191 } 203 }
192 } else 204 } else
193 rc = rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec); 205 rc = rtas_change_msi(pdn, RTAS_CHANGE_MSIX_FN, nvec);
194 206
195 if (rc) { 207 if (rc != nvec) {
196 pr_debug("rtas_msi: rtas_change_msi() failed\n"); 208 pr_debug("rtas_msi: rtas_change_msi() failed\n");
197 return rc; 209 return rc;
198 } 210 }
199 211
200 i = 0; 212 i = 0;
201 list_for_each_entry(entry, &pdev->msi_list, list) { 213 list_for_each_entry(entry, &pdev->msi_list, list) {
202 hwirq = rtas_query_irq_number(pdn, i); 214 hwirq = rtas_query_irq_number(pdn, i++);
203 if (hwirq < 0) { 215 if (hwirq < 0) {
204 pr_debug("rtas_msi: error (%d) getting hwirq\n", rc); 216 pr_debug("rtas_msi: error (%d) getting hwirq\n", rc);
205 return hwirq; 217 return hwirq;
@@ -234,8 +246,8 @@ static void rtas_msi_pci_irq_fixup(struct pci_dev *pdev)
234 } 246 }
235 247
236 /* No MSI -> MSIs can't have been assigned by fw, leave LSI */ 248 /* No MSI -> MSIs can't have been assigned by fw, leave LSI */
237 if (check_req_msi(pdev, 1)) { 249 if (check_req_msi(pdev, 1) && check_req_msix(pdev, 1)) {
238 dev_dbg(&pdev->dev, "rtas_msi: no req#msi, nothing to do.\n"); 250 dev_dbg(&pdev->dev, "rtas_msi: no req#msi/x, nothing to do.\n");
239 return; 251 return;
240 } 252 }
241 253
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index 5e1ed3d60ee5..ad152a0e3946 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -137,11 +137,9 @@ EXPORT_SYMBOL_GPL(pcibios_add_pci_devices);
137struct pci_controller * __devinit init_phb_dynamic(struct device_node *dn) 137struct pci_controller * __devinit init_phb_dynamic(struct device_node *dn)
138{ 138{
139 struct pci_controller *phb; 139 struct pci_controller *phb;
140 int primary;
141 140
142 pr_debug("PCI: Initializing new hotplug PHB %s\n", dn->full_name); 141 pr_debug("PCI: Initializing new hotplug PHB %s\n", dn->full_name);
143 142
144 primary = list_empty(&hose_list);
145 phb = pcibios_alloc_controller(dn); 143 phb = pcibios_alloc_controller(dn);
146 if (!phb) 144 if (!phb)
147 return NULL; 145 return NULL;
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index f1c3395633b9..474d176a6ec3 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -129,7 +129,8 @@ void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src)
129 brg -= 4; 129 brg -= 4;
130 } 130 }
131 bp += brg; 131 bp += brg;
132 val = (((clk / rate) - 1) << 1) | CPM_BRG_EN | src; 132 /* Round the clock divider to the nearest integer. */
133 val = (((clk * 2 / rate) - 1) & ~1) | CPM_BRG_EN | src;
133 if (div16) 134 if (div16)
134 val |= CPM_BRG_DIV16; 135 val |= CPM_BRG_DIV16;
135 136
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 9817f63723dd..78021d8afc53 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1,12 +1,16 @@
1/* 1/*
2 * MPC83xx/85xx/86xx PCI/PCIE support routing. 2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
3 * 3 *
4 * Copyright 2007,2008 Freescale Semiconductor, Inc 4 * Copyright 2007-2009 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
5 * 6 *
6 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
7 * Recode: ZHANG WEI <wei.zhang@freescale.com> 8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
8 * Rewrite the routing for Frescale PCI and PCI Express 9 * Rewrite the routing for Frescale PCI and PCI Express
9 * Roy Zang <tie-fei.zang@freescale.com> 10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 * 14 *
11 * This program is free software; you can redistribute it and/or modify it 15 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the 16 * under the terms of the GNU General Public License as published by the
@@ -27,6 +31,29 @@
27#include <sysdev/fsl_soc.h> 31#include <sysdev/fsl_soc.h>
28#include <sysdev/fsl_pci.h> 32#include <sysdev/fsl_pci.h>
29 33
34static int fsl_pcie_bus_fixup;
35
36static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
37{
38 /* if we aren't a PCIe don't bother */
39 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
40 return;
41
42 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
43 fsl_pcie_bus_fixup = 1;
44 return;
45}
46
47static int __init fsl_pcie_check_link(struct pci_controller *hose)
48{
49 u32 val;
50
51 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
52 if (val < PCIE_LTSSM_L0)
53 return 1;
54 return 0;
55}
56
30#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx) 57#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
31static int __init setup_one_atmu(struct ccsr_pci __iomem *pci, 58static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
32 unsigned int index, const struct resource *res, 59 unsigned int index, const struct resource *res,
@@ -159,28 +186,6 @@ static void __init setup_pci_pcsrbar(struct pci_controller *hose)
159#endif 186#endif
160} 187}
161 188
162static int fsl_pcie_bus_fixup;
163
164static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
165{
166 /* if we aren't a PCIe don't bother */
167 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
168 return ;
169
170 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
171 fsl_pcie_bus_fixup = 1;
172 return ;
173}
174
175static int __init fsl_pcie_check_link(struct pci_controller *hose)
176{
177 u32 val;
178 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
179 if (val < PCIE_LTSSM_L0)
180 return 1;
181 return 0;
182}
183
184void fsl_pcibios_fixup_bus(struct pci_bus *bus) 189void fsl_pcibios_fixup_bus(struct pci_bus *bus)
185{ 190{
186 struct pci_controller *hose = (struct pci_controller *) bus->sysdata; 191 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
@@ -294,8 +299,184 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
294#endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */ 299#endif /* CONFIG_PPC_85xx || CONFIG_PPC_86xx */
295 300
296#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 301#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
302DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
303DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header);
304DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header);
305DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header);
306DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header);
307DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header);
308DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header);
309DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header);
310
311struct mpc83xx_pcie_priv {
312 void __iomem *cfg_type0;
313 void __iomem *cfg_type1;
314 u32 dev_base;
315};
316
317/*
318 * With the convention of u-boot, the PCIE outbound window 0 serves
319 * as configuration transactions outbound.
320 */
321#define PEX_OUTWIN0_BAR 0xCA4
322#define PEX_OUTWIN0_TAL 0xCA8
323#define PEX_OUTWIN0_TAH 0xCAC
324
325static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
326{
327 struct pci_controller *hose = bus->sysdata;
328
329 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
330 return PCIBIOS_DEVICE_NOT_FOUND;
331 /*
332 * Workaround for the HW bug: for Type 0 configure transactions the
333 * PCI-E controller does not check the device number bits and just
334 * assumes that the device number bits are 0.
335 */
336 if (bus->number == hose->first_busno ||
337 bus->primary == hose->first_busno) {
338 if (devfn & 0xf8)
339 return PCIBIOS_DEVICE_NOT_FOUND;
340 }
341
342 if (ppc_md.pci_exclude_device) {
343 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
344 return PCIBIOS_DEVICE_NOT_FOUND;
345 }
346
347 return PCIBIOS_SUCCESSFUL;
348}
349
350static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
351 unsigned int devfn, int offset)
352{
353 struct pci_controller *hose = bus->sysdata;
354 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
355 u8 bus_no = bus->number - hose->first_busno;
356 u32 dev_base = bus_no << 24 | devfn << 16;
357 int ret;
358
359 ret = mpc83xx_pcie_exclude_device(bus, devfn);
360 if (ret)
361 return NULL;
362
363 offset &= 0xfff;
364
365 /* Type 0 */
366 if (bus->number == hose->first_busno)
367 return pcie->cfg_type0 + offset;
368
369 if (pcie->dev_base == dev_base)
370 goto mapped;
371
372 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
373
374 pcie->dev_base = dev_base;
375mapped:
376 return pcie->cfg_type1 + offset;
377}
378
379static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
380 int offset, int len, u32 *val)
381{
382 void __iomem *cfg_addr;
383
384 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
385 if (!cfg_addr)
386 return PCIBIOS_DEVICE_NOT_FOUND;
387
388 switch (len) {
389 case 1:
390 *val = in_8(cfg_addr);
391 break;
392 case 2:
393 *val = in_le16(cfg_addr);
394 break;
395 default:
396 *val = in_le32(cfg_addr);
397 break;
398 }
399
400 return PCIBIOS_SUCCESSFUL;
401}
402
403static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
404 int offset, int len, u32 val)
405{
406 void __iomem *cfg_addr;
407
408 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
409 if (!cfg_addr)
410 return PCIBIOS_DEVICE_NOT_FOUND;
411
412 switch (len) {
413 case 1:
414 out_8(cfg_addr, val);
415 break;
416 case 2:
417 out_le16(cfg_addr, val);
418 break;
419 default:
420 out_le32(cfg_addr, val);
421 break;
422 }
423
424 return PCIBIOS_SUCCESSFUL;
425}
426
427static struct pci_ops mpc83xx_pcie_ops = {
428 .read = mpc83xx_pcie_read_config,
429 .write = mpc83xx_pcie_write_config,
430};
431
432static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
433 struct resource *reg)
434{
435 struct mpc83xx_pcie_priv *pcie;
436 u32 cfg_bar;
437 int ret = -ENOMEM;
438
439 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
440 if (!pcie)
441 return ret;
442
443 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
444 if (!pcie->cfg_type0)
445 goto err0;
446
447 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
448 if (!cfg_bar) {
449 /* PCI-E isn't configured. */
450 ret = -ENODEV;
451 goto err1;
452 }
453
454 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
455 if (!pcie->cfg_type1)
456 goto err1;
457
458 WARN_ON(hose->dn->data);
459 hose->dn->data = pcie;
460 hose->ops = &mpc83xx_pcie_ops;
461
462 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
463 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
464
465 if (fsl_pcie_check_link(hose))
466 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
467
468 return 0;
469err1:
470 iounmap(pcie->cfg_type0);
471err0:
472 kfree(pcie);
473 return ret;
474
475}
476
297int __init mpc83xx_add_bridge(struct device_node *dev) 477int __init mpc83xx_add_bridge(struct device_node *dev)
298{ 478{
479 int ret;
299 int len; 480 int len;
300 struct pci_controller *hose; 481 struct pci_controller *hose;
301 struct resource rsrc_reg; 482 struct resource rsrc_reg;
@@ -303,6 +484,11 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
303 const int *bus_range; 484 const int *bus_range;
304 int primary; 485 int primary;
305 486
487 if (!of_device_is_available(dev)) {
488 pr_warning("%s: disabled by the firmware.\n",
489 dev->full_name);
490 return -ENODEV;
491 }
306 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 492 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
307 493
308 /* Fetch host bridge registers address */ 494 /* Fetch host bridge registers address */
@@ -350,7 +536,14 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
350 hose->first_busno = bus_range ? bus_range[0] : 0; 536 hose->first_busno = bus_range ? bus_range[0] : 0;
351 hose->last_busno = bus_range ? bus_range[1] : 0xff; 537 hose->last_busno = bus_range ? bus_range[1] : 0xff;
352 538
353 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 4, 0); 539 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
540 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
541 if (ret)
542 goto err0;
543 } else {
544 setup_indirect_pci(hose, rsrc_cfg.start,
545 rsrc_cfg.start + 4, 0);
546 }
354 547
355 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 548 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
356 "Firmware bus number: %d->%d\n", 549 "Firmware bus number: %d->%d\n",
@@ -365,5 +558,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
365 pci_process_bridge_OF_ranges(hose, dev, primary); 558 pci_process_bridge_OF_ranges(hose, dev, primary);
366 559
367 return 0; 560 return 0;
561err0:
562 pcibios_free_controller(hose);
563 return ret;
368} 564}
369#endif /* CONFIG_PPC_83xx */ 565#endif /* CONFIG_PPC_83xx */
diff --git a/drivers/macintosh/therm_adt746x.c b/drivers/macintosh/therm_adt746x.c
index 82607add69a9..c0621d50c8a0 100644
--- a/drivers/macintosh/therm_adt746x.c
+++ b/drivers/macintosh/therm_adt746x.c
@@ -498,8 +498,8 @@ static ssize_t store_##name(struct device *dev, struct device_attribute *attr, c
498#define BUILD_STORE_FUNC_INT(name, data) \ 498#define BUILD_STORE_FUNC_INT(name, data) \
499static ssize_t store_##name(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) \ 499static ssize_t store_##name(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) \
500{ \ 500{ \
501 u32 val; \ 501 int val; \
502 val = simple_strtoul(buf, NULL, 10); \ 502 val = simple_strtol(buf, NULL, 10); \
503 if (val < 0 || val > 255) \ 503 if (val < 0 || val > 255) \
504 return -EINVAL; \ 504 return -EINVAL; \
505 printk(KERN_INFO "Setting specified fan speed to %d\n", val); \ 505 printk(KERN_INFO "Setting specified fan speed to %d\n", val); \
diff --git a/drivers/net/fec_mpc52xx.c b/drivers/net/fec_mpc52xx.c
index cd8e98b45ec5..049b0a7e01f3 100644
--- a/drivers/net/fec_mpc52xx.c
+++ b/drivers/net/fec_mpc52xx.c
@@ -1123,9 +1123,9 @@ static int mpc52xx_fec_of_resume(struct of_device *op)
1123#endif 1123#endif
1124 1124
1125static struct of_device_id mpc52xx_fec_match[] = { 1125static struct of_device_id mpc52xx_fec_match[] = {
1126 { .type = "network", .compatible = "fsl,mpc5200b-fec", }, 1126 { .compatible = "fsl,mpc5200b-fec", },
1127 { .type = "network", .compatible = "fsl,mpc5200-fec", }, 1127 { .compatible = "fsl,mpc5200-fec", },
1128 { .type = "network", .compatible = "mpc5200-fec", }, 1128 { .compatible = "mpc5200-fec", },
1129 { } 1129 { }
1130}; 1130};
1131 1131
diff --git a/drivers/serial/mpc52xx_uart.c b/drivers/serial/mpc52xx_uart.c
index 0c3a2ab1612c..7f72f8ceaa6f 100644
--- a/drivers/serial/mpc52xx_uart.c
+++ b/drivers/serial/mpc52xx_uart.c
@@ -50,8 +50,8 @@
50/* OF Platform device Usage : 50/* OF Platform device Usage :
51 * 51 *
52 * This driver is only used for PSCs configured in uart mode. The device 52 * This driver is only used for PSCs configured in uart mode. The device
53 * tree will have a node for each PSC in uart mode w/ device_type = "serial" 53 * tree will have a node for each PSC with "mpc52xx-psc-uart" in the compatible
54 * and "mpc52xx-psc-uart" in the compatible string 54 * list.
55 * 55 *
56 * By default, PSC devices are enumerated in the order they are found. However 56 * By default, PSC devices are enumerated in the order they are found. However
57 * a particular PSC number can be forces by adding 'device_no = <port#>' 57 * a particular PSC number can be forces by adding 'device_no = <port#>'
@@ -522,7 +522,7 @@ mpc52xx_uart_startup(struct uart_port *port)
522 522
523 /* Request IRQ */ 523 /* Request IRQ */
524 ret = request_irq(port->irq, mpc52xx_uart_int, 524 ret = request_irq(port->irq, mpc52xx_uart_int,
525 IRQF_DISABLED | IRQF_SAMPLE_RANDOM | IRQF_SHARED, 525 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
526 "mpc52xx_psc_uart", port); 526 "mpc52xx_psc_uart", port);
527 if (ret) 527 if (ret)
528 return ret; 528 return ret;
@@ -1212,30 +1212,18 @@ mpc52xx_uart_of_resume(struct of_device *op)
1212#endif 1212#endif
1213 1213
1214static void 1214static void
1215mpc52xx_uart_of_assign(struct device_node *np, int idx) 1215mpc52xx_uart_of_assign(struct device_node *np)
1216{ 1216{
1217 int free_idx = -1;
1218 int i; 1217 int i;
1219 1218
1220 /* Find the first free node */ 1219 /* Find the first free PSC number */
1221 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { 1220 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1222 if (mpc52xx_uart_nodes[i] == NULL) { 1221 if (mpc52xx_uart_nodes[i] == NULL) {
1223 free_idx = i; 1222 of_node_get(np);
1224 break; 1223 mpc52xx_uart_nodes[i] = np;
1224 return;
1225 } 1225 }
1226 } 1226 }
1227
1228 if ((idx < 0) || (idx >= MPC52xx_PSC_MAXNUM))
1229 idx = free_idx;
1230
1231 if (idx < 0)
1232 return; /* No free slot; abort */
1233
1234 of_node_get(np);
1235 /* If the slot is already occupied, then swap slots */
1236 if (mpc52xx_uart_nodes[idx] && (free_idx != -1))
1237 mpc52xx_uart_nodes[free_idx] = mpc52xx_uart_nodes[idx];
1238 mpc52xx_uart_nodes[idx] = np;
1239} 1227}
1240 1228
1241static void 1229static void
@@ -1243,23 +1231,17 @@ mpc52xx_uart_of_enumerate(void)
1243{ 1231{
1244 static int enum_done; 1232 static int enum_done;
1245 struct device_node *np; 1233 struct device_node *np;
1246 const unsigned int *devno;
1247 const struct of_device_id *match; 1234 const struct of_device_id *match;
1248 int i; 1235 int i;
1249 1236
1250 if (enum_done) 1237 if (enum_done)
1251 return; 1238 return;
1252 1239
1253 for_each_node_by_type(np, "serial") { 1240 /* Assign index to each PSC in device tree */
1241 for_each_matching_node(np, mpc52xx_uart_of_match) {
1254 match = of_match_node(mpc52xx_uart_of_match, np); 1242 match = of_match_node(mpc52xx_uart_of_match, np);
1255 if (!match)
1256 continue;
1257
1258 psc_ops = match->data; 1243 psc_ops = match->data;
1259 1244 mpc52xx_uart_of_assign(np);
1260 /* Is a particular device number requested? */
1261 devno = of_get_property(np, "port-number", NULL);
1262 mpc52xx_uart_of_assign(np, devno ? *devno : -1);
1263 } 1245 }
1264 1246
1265 enum_done = 1; 1247 enum_done = 1;
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 325c10ff6a2c..c7352f7195ee 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -772,7 +772,7 @@ config TXX9_WDT
772 772
773config GEF_WDT 773config GEF_WDT
774 tristate "GE Fanuc Watchdog Timer" 774 tristate "GE Fanuc Watchdog Timer"
775 depends on GEF_SBC610 775 depends on GEF_SBC610 || GEF_SBC310
776 ---help--- 776 ---help---
777 Watchdog timer found in a number of GE Fanuc single board computers. 777 Watchdog timer found in a number of GE Fanuc single board computers.
778 778
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 918391b4b109..807f1ad8b760 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2218,6 +2218,14 @@
2218#define PCI_DEVICE_ID_TDI_EHCI 0x0101 2218#define PCI_DEVICE_ID_TDI_EHCI 0x0101
2219 2219
2220#define PCI_VENDOR_ID_FREESCALE 0x1957 2220#define PCI_VENDOR_ID_FREESCALE 0x1957
2221#define PCI_DEVICE_ID_MPC8315E 0x00b4
2222#define PCI_DEVICE_ID_MPC8315 0x00b5
2223#define PCI_DEVICE_ID_MPC8314E 0x00b6
2224#define PCI_DEVICE_ID_MPC8314 0x00b7
2225#define PCI_DEVICE_ID_MPC8378E 0x00c4
2226#define PCI_DEVICE_ID_MPC8378 0x00c5
2227#define PCI_DEVICE_ID_MPC8377E 0x00c6
2228#define PCI_DEVICE_ID_MPC8377 0x00c7
2221#define PCI_DEVICE_ID_MPC8548E 0x0012 2229#define PCI_DEVICE_ID_MPC8548E 0x0012
2222#define PCI_DEVICE_ID_MPC8548 0x0013 2230#define PCI_DEVICE_ID_MPC8548 0x0013
2223#define PCI_DEVICE_ID_MPC8543E 0x0014 2231#define PCI_DEVICE_ID_MPC8543E 0x0014
diff --git a/lib/lmb.c b/lib/lmb.c
index 97e547037084..e4a6482d8b26 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -29,33 +29,33 @@ static int __init early_lmb(char *p)
29} 29}
30early_param("lmb", early_lmb); 30early_param("lmb", early_lmb);
31 31
32void lmb_dump_all(void) 32static void lmb_dump(struct lmb_region *region, char *name)
33{ 33{
34 unsigned long i; 34 unsigned long long base, size;
35 int i;
36
37 pr_info(" %s.cnt = 0x%lx\n", name, region->cnt);
38
39 for (i = 0; i < region->cnt; i++) {
40 base = region->region[i].base;
41 size = region->region[i].size;
42
43 pr_info(" %s[0x%x]\t0x%016llx - 0x%016llx, 0x%llx bytes\n",
44 name, i, base, base + size - 1, size);
45 }
46}
35 47
48void lmb_dump_all(void)
49{
36 if (!lmb_debug) 50 if (!lmb_debug)
37 return; 51 return;
38 52
39 pr_info("lmb_dump_all:\n"); 53 pr_info("LMB configuration:\n");
40 pr_info(" memory.cnt = 0x%lx\n", lmb.memory.cnt); 54 pr_info(" rmo_size = 0x%llx\n", (unsigned long long)lmb.rmo_size);
41 pr_info(" memory.size = 0x%llx\n", 55 pr_info(" memory.size = 0x%llx\n", (unsigned long long)lmb.memory.size);
42 (unsigned long long)lmb.memory.size);
43 for (i=0; i < lmb.memory.cnt ;i++) {
44 pr_info(" memory.region[0x%lx].base = 0x%llx\n",
45 i, (unsigned long long)lmb.memory.region[i].base);
46 pr_info(" .size = 0x%llx\n",
47 (unsigned long long)lmb.memory.region[i].size);
48 }
49 56
50 pr_info(" reserved.cnt = 0x%lx\n", lmb.reserved.cnt); 57 lmb_dump(&lmb.memory, "memory");
51 pr_info(" reserved.size = 0x%llx\n", 58 lmb_dump(&lmb.reserved, "reserved");
52 (unsigned long long)lmb.memory.size);
53 for (i=0; i < lmb.reserved.cnt ;i++) {
54 pr_info(" reserved.region[0x%lx].base = 0x%llx\n",
55 i, (unsigned long long)lmb.reserved.region[i].base);
56 pr_info(" .size = 0x%llx\n",
57 (unsigned long long)lmb.reserved.region[i].size);
58 }
59} 59}
60 60
61static unsigned long lmb_addrs_overlap(u64 base1, u64 size1, u64 base2, 61static unsigned long lmb_addrs_overlap(u64 base1, u64 size1, u64 base2,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 10:06:12 -0500