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-rw-r--r--Documentation/feature-removal-schedule.txt12
-rw-r--r--arch/arm/mach-pxa/Kconfig9
-rw-r--r--arch/arm/mach-pxa/Makefile1
-rw-r--r--arch/arm/mach-pxa/corgi_lcd.c288
-rw-r--r--arch/arm/mach-pxa/corgi_ssp.c274
-rw-r--r--arch/arm/mach-pxa/include/mach/corgi.h1
-rw-r--r--arch/arm/mach-pxa/sharpsl.h23
7 files changed, 0 insertions, 608 deletions
diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt
index 05df0b7514b6..6237d74be86d 100644
--- a/Documentation/feature-removal-schedule.txt
+++ b/Documentation/feature-removal-schedule.txt
@@ -531,18 +531,6 @@ Who: Eric Miao <eric.y.miao@gmail.com>
531 531
532---------------------------- 532----------------------------
533 533
534What: corgi_ssp and corgi_ts driver
535When: 2.6.35
536Files: arch/arm/mach-pxa/corgi_ssp.c, drivers/input/touchscreen/corgi_ts.c
537Why: The corgi touchscreen is now deprecated in favour of the generic
538 ads7846.c driver. The noise reduction technique used in corgi_ts.c,
539 that's to wait till vsync before ADC sampling, is also integrated into
540 ads7846 driver now. Provided that the original driver is not generic
541 and is difficult to maintain, it will be removed later.
542Who: Eric Miao <eric.y.miao@gmail.com>
543
544----------------------------
545
546What: capifs 534What: capifs
547When: February 2011 535When: February 2011
548Files: drivers/isdn/capi/capifs.* 536Files: drivers/isdn/capi/capifs.*
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 5b6ee46fa7f6..089579fda6c5 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -461,15 +461,6 @@ config SHARPSL_PM_MAX1111
461 select HWMON 461 select HWMON
462 select SENSORS_MAX1111 462 select SENSORS_MAX1111
463 463
464config CORGI_SSP_DEPRECATED
465 bool
466 select PXA_SSP
467 select PXA_SSP_LEGACY
468 help
469 This option will include corgi_ssp.c and corgi_lcd.c
470 that corgi_ts.c and other legacy drivers (corgi_bl.c
471 and sharpsl_pm.c) may depend on.
472
473config MACH_POODLE 464config MACH_POODLE
474 bool "Enable Sharp SL-5600 (Poodle) Support" 465 bool "Enable Sharp SL-5600 (Poodle) Support"
475 depends on PXA_SHARPSL 466 depends on PXA_SHARPSL
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 86bc87b7f2dd..a83aff386fba 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -80,7 +80,6 @@ obj-$(CONFIG_MACH_PALMLD) += palmld.o
80obj-$(CONFIG_PALM_TREO) += palmtreo.o 80obj-$(CONFIG_PALM_TREO) += palmtreo.o
81obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o 81obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o
82obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o 82obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o
83obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o
84obj-$(CONFIG_MACH_POODLE) += poodle.o 83obj-$(CONFIG_MACH_POODLE) += poodle.o
85obj-$(CONFIG_MACH_TOSA) += tosa.o 84obj-$(CONFIG_MACH_TOSA) += tosa.o
86obj-$(CONFIG_MACH_ICONTROL) += icontrol.o mxm8x10.o 85obj-$(CONFIG_MACH_ICONTROL) += icontrol.o mxm8x10.o
diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c
deleted file mode 100644
index d9b96319d498..000000000000
--- a/arch/arm/mach-pxa/corgi_lcd.c
+++ /dev/null
@@ -1,288 +0,0 @@
1/*
2 * linux/arch/arm/mach-pxa/corgi_lcd.c
3 *
4 * Corgi/Spitz LCD Specific Code
5 *
6 * Copyright (C) 2005 Richard Purdie
7 *
8 * Connectivity:
9 * Corgi - LCD to ATI Imageon w100 (Wallaby)
10 * Spitz - LCD to PXA Framebuffer
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18#include <linux/delay.h>
19#include <linux/kernel.h>
20#include <linux/platform_device.h>
21#include <linux/module.h>
22#include <linux/string.h>
23#include <mach/corgi.h>
24#include <mach/hardware.h>
25#include <mach/sharpsl.h>
26#include <mach/spitz.h>
27#include <asm/hardware/scoop.h>
28#include <asm/mach/sharpsl_param.h>
29#include "generic.h"
30
31/* Register Addresses */
32#define RESCTL_ADRS 0x00
33#define PHACTRL_ADRS 0x01
34#define DUTYCTRL_ADRS 0x02
35#define POWERREG0_ADRS 0x03
36#define POWERREG1_ADRS 0x04
37#define GPOR3_ADRS 0x05
38#define PICTRL_ADRS 0x06
39#define POLCTRL_ADRS 0x07
40
41/* Register Bit Definitions */
42#define RESCTL_QVGA 0x01
43#define RESCTL_VGA 0x00
44
45#define POWER1_VW_ON 0x01 /* VW Supply FET ON */
46#define POWER1_GVSS_ON 0x02 /* GVSS(-8V) Power Supply ON */
47#define POWER1_VDD_ON 0x04 /* VDD(8V),SVSS(-4V) Power Supply ON */
48
49#define POWER1_VW_OFF 0x00 /* VW Supply FET OFF */
50#define POWER1_GVSS_OFF 0x00 /* GVSS(-8V) Power Supply OFF */
51#define POWER1_VDD_OFF 0x00 /* VDD(8V),SVSS(-4V) Power Supply OFF */
52
53#define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */
54#define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */
55#define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */
56#define POWER0_COM_ON 0x08 /* COM Power Supply ON */
57#define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */
58
59#define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */
60#define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */
61#define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */
62
63#define PICTRL_INIT_STATE 0x01
64#define PICTRL_INIOFF 0x02
65#define PICTRL_POWER_DOWN 0x04
66#define PICTRL_COM_SIGNAL_OFF 0x08
67#define PICTRL_DAC_SIGNAL_OFF 0x10
68
69#define POLCTRL_SYNC_POL_FALL 0x01
70#define POLCTRL_EN_POL_FALL 0x02
71#define POLCTRL_DATA_POL_FALL 0x04
72#define POLCTRL_SYNC_ACT_H 0x08
73#define POLCTRL_EN_ACT_L 0x10
74
75#define POLCTRL_SYNC_POL_RISE 0x00
76#define POLCTRL_EN_POL_RISE 0x00
77#define POLCTRL_DATA_POL_RISE 0x00
78#define POLCTRL_SYNC_ACT_L 0x00
79#define POLCTRL_EN_ACT_H 0x00
80
81#define PHACTRL_PHASE_MANUAL 0x01
82#define DEFAULT_PHAD_QVGA (9)
83#define DEFAULT_COMADJ (125)
84
85/*
86 * This is only a psuedo I2C interface. We can't use the standard kernel
87 * routines as the interface is write only. We just assume the data is acked...
88 */
89static void lcdtg_ssp_i2c_send(u8 data)
90{
91 corgi_ssp_lcdtg_send(POWERREG0_ADRS, data);
92 udelay(10);
93}
94
95static void lcdtg_i2c_send_bit(u8 data)
96{
97 lcdtg_ssp_i2c_send(data);
98 lcdtg_ssp_i2c_send(data | POWER0_COM_DCLK);
99 lcdtg_ssp_i2c_send(data);
100}
101
102static void lcdtg_i2c_send_start(u8 base)
103{
104 lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
105 lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
106 lcdtg_ssp_i2c_send(base);
107}
108
109static void lcdtg_i2c_send_stop(u8 base)
110{
111 lcdtg_ssp_i2c_send(base);
112 lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK);
113 lcdtg_ssp_i2c_send(base | POWER0_COM_DCLK | POWER0_COM_DOUT);
114}
115
116static void lcdtg_i2c_send_byte(u8 base, u8 data)
117{
118 int i;
119 for (i = 0; i < 8; i++) {
120 if (data & 0x80)
121 lcdtg_i2c_send_bit(base | POWER0_COM_DOUT);
122 else
123 lcdtg_i2c_send_bit(base);
124 data <<= 1;
125 }
126}
127
128static void lcdtg_i2c_wait_ack(u8 base)
129{
130 lcdtg_i2c_send_bit(base);
131}
132
133static void lcdtg_set_common_voltage(u8 base_data, u8 data)
134{
135 /* Set Common Voltage to M62332FP via I2C */
136 lcdtg_i2c_send_start(base_data);
137 lcdtg_i2c_send_byte(base_data, 0x9c);
138 lcdtg_i2c_wait_ack(base_data);
139 lcdtg_i2c_send_byte(base_data, 0x00);
140 lcdtg_i2c_wait_ack(base_data);
141 lcdtg_i2c_send_byte(base_data, data);
142 lcdtg_i2c_wait_ack(base_data);
143 lcdtg_i2c_send_stop(base_data);
144}
145
146/* Set Phase Adjust */
147static void lcdtg_set_phadadj(int mode)
148{
149 int adj;
150 switch(mode) {
151 case 480:
152 case 640:
153 /* Setting for VGA */
154 adj = sharpsl_param.phadadj;
155 if (adj < 0) {
156 adj = PHACTRL_PHASE_MANUAL;
157 } else {
158 adj = ((adj & 0x0f) << 1) | PHACTRL_PHASE_MANUAL;
159 }
160 break;
161 case 240:
162 case 320:
163 default:
164 /* Setting for QVGA */
165 adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL;
166 break;
167 }
168
169 corgi_ssp_lcdtg_send(PHACTRL_ADRS, adj);
170}
171
172static int lcd_inited;
173
174void corgi_lcdtg_hw_init(int mode)
175{
176 if (!lcd_inited) {
177 int comadj;
178
179 /* Initialize Internal Logic & Port */
180 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE
181 | PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF);
182
183 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF
184 | POWER0_COM_OFF | POWER0_VCC5_OFF);
185
186 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
187
188 /* VDD(+8V), SVSS(-4V) ON */
189 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
190 mdelay(3);
191
192 /* DAC ON */
193 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
194 | POWER0_COM_OFF | POWER0_VCC5_OFF);
195
196 /* INIB = H, INI = L */
197 /* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */
198 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF);
199
200 /* Set Common Voltage */
201 comadj = sharpsl_param.comadj;
202 if (comadj < 0)
203 comadj = DEFAULT_COMADJ;
204 lcdtg_set_common_voltage((POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF), comadj);
205
206 /* VCC5 ON, DAC ON */
207 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON |
208 POWER0_COM_OFF | POWER0_VCC5_ON);
209
210 /* GVSS(-8V) ON, VDD ON */
211 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
212 mdelay(2);
213
214 /* COM SIGNAL ON (PICTL[3] = L) */
215 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIT_STATE);
216
217 /* COM ON, DAC ON, VCC5_ON */
218 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON
219 | POWER0_COM_ON | POWER0_VCC5_ON);
220
221 /* VW ON, GVSS ON, VDD ON */
222 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON);
223
224 /* Signals output enable */
225 corgi_ssp_lcdtg_send(PICTRL_ADRS, 0);
226
227 /* Set Phase Adjust */
228 lcdtg_set_phadadj(mode);
229
230 /* Initialize for Input Signals from ATI */
231 corgi_ssp_lcdtg_send(POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE
232 | POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H);
233 udelay(1000);
234
235 lcd_inited=1;
236 } else {
237 lcdtg_set_phadadj(mode);
238 }
239
240 switch(mode) {
241 case 480:
242 case 640:
243 /* Set Lcd Resolution (VGA) */
244 corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_VGA);
245 break;
246 case 240:
247 case 320:
248 default:
249 /* Set Lcd Resolution (QVGA) */
250 corgi_ssp_lcdtg_send(RESCTL_ADRS, RESCTL_QVGA);
251 break;
252 }
253}
254
255void corgi_lcdtg_suspend(void)
256{
257 /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */
258 mdelay(34);
259
260 /* (1)VW OFF */
261 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON);
262
263 /* (2)COM OFF */
264 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_COM_SIGNAL_OFF);
265 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON);
266
267 /* (3)Set Common Voltage Bias 0V */
268 lcdtg_set_common_voltage(POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON, 0);
269
270 /* (4)GVSS OFF */
271 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON);
272
273 /* (5)VCC5 OFF */
274 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF);
275
276 /* (6)Set PDWN, INIOFF, DACOFF */
277 corgi_ssp_lcdtg_send(PICTRL_ADRS, PICTRL_INIOFF | PICTRL_DAC_SIGNAL_OFF |
278 PICTRL_POWER_DOWN | PICTRL_COM_SIGNAL_OFF);
279
280 /* (7)DAC OFF */
281 corgi_ssp_lcdtg_send(POWERREG0_ADRS, POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF);
282
283 /* (8)VDD OFF */
284 corgi_ssp_lcdtg_send(POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF);
285
286 lcd_inited = 0;
287}
288
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c
deleted file mode 100644
index 9347254f8bcf..000000000000
--- a/arch/arm/mach-pxa/corgi_ssp.c
+++ /dev/null
@@ -1,274 +0,0 @@
1/*
2 * SSP control code for Sharp Corgi devices
3 *
4 * Copyright (c) 2004-2005 Richard Purdie
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/sched.h>
16#include <linux/delay.h>
17#include <linux/platform_device.h>
18#include <mach/hardware.h>
19#include <asm/mach-types.h>
20
21#include <mach/ssp.h>
22#include <mach/pxa2xx-gpio.h>
23#include <mach/regs-ssp.h>
24#include "sharpsl.h"
25
26static DEFINE_SPINLOCK(corgi_ssp_lock);
27static struct ssp_dev corgi_ssp_dev;
28static struct ssp_state corgi_ssp_state;
29static struct corgissp_machinfo *ssp_machinfo;
30
31/*
32 * There are three devices connected to the SSP interface:
33 * 1. A touchscreen controller (TI ADS7846 compatible)
34 * 2. An LCD controller (with some Backlight functionality)
35 * 3. A battery monitoring IC (Maxim MAX1111)
36 *
37 * Each device uses a different speed/mode of communication.
38 *
39 * The touchscreen is very sensitive and the most frequently used
40 * so the port is left configured for this.
41 *
42 * Devices are selected using Chip Selects on GPIOs.
43 */
44
45/*
46 * ADS7846 Routines
47 */
48unsigned long corgi_ssp_ads7846_putget(ulong data)
49{
50 unsigned long flag;
51 u32 ret = 0;
52
53 spin_lock_irqsave(&corgi_ssp_lock, flag);
54 if (ssp_machinfo->cs_ads7846 >= 0)
55 GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
56
57 ssp_write_word(&corgi_ssp_dev,data);
58 ssp_read_word(&corgi_ssp_dev, &ret);
59
60 if (ssp_machinfo->cs_ads7846 >= 0)
61 GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
62 spin_unlock_irqrestore(&corgi_ssp_lock, flag);
63
64 return ret;
65}
66
67/*
68 * NOTE: These functions should always be called in interrupt context
69 * and use the _lock and _unlock functions. They are very time sensitive.
70 */
71void corgi_ssp_ads7846_lock(void)
72{
73 spin_lock(&corgi_ssp_lock);
74 if (ssp_machinfo->cs_ads7846 >= 0)
75 GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
76}
77
78void corgi_ssp_ads7846_unlock(void)
79{
80 if (ssp_machinfo->cs_ads7846 >= 0)
81 GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846);
82 spin_unlock(&corgi_ssp_lock);
83}
84
85void corgi_ssp_ads7846_put(ulong data)
86{
87 ssp_write_word(&corgi_ssp_dev,data);
88}
89
90unsigned long corgi_ssp_ads7846_get(void)
91{
92 u32 ret = 0;
93 ssp_read_word(&corgi_ssp_dev, &ret);
94 return ret;
95}
96
97EXPORT_SYMBOL(corgi_ssp_ads7846_putget);
98EXPORT_SYMBOL(corgi_ssp_ads7846_lock);
99EXPORT_SYMBOL(corgi_ssp_ads7846_unlock);
100EXPORT_SYMBOL(corgi_ssp_ads7846_put);
101EXPORT_SYMBOL(corgi_ssp_ads7846_get);
102
103
104/*
105 * LCD/Backlight Routines
106 */
107unsigned long corgi_ssp_dac_put(ulong data)
108{
109 unsigned long flag, sscr1 = SSCR1_SPH;
110 u32 tmp;
111
112 spin_lock_irqsave(&corgi_ssp_lock, flag);
113
114 if (machine_is_spitz() || machine_is_akita() || machine_is_borzoi())
115 sscr1 = 0;
116
117 ssp_disable(&corgi_ssp_dev);
118 ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), sscr1, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_lcdcon));
119 ssp_enable(&corgi_ssp_dev);
120
121 if (ssp_machinfo->cs_lcdcon >= 0)
122 GPCR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
123 ssp_write_word(&corgi_ssp_dev,data);
124 /* Read null data back from device to prevent SSP overflow */
125 ssp_read_word(&corgi_ssp_dev, &tmp);
126 if (ssp_machinfo->cs_lcdcon >= 0)
127 GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon);
128
129 ssp_disable(&corgi_ssp_dev);
130 ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
131 ssp_enable(&corgi_ssp_dev);
132
133 spin_unlock_irqrestore(&corgi_ssp_lock, flag);
134
135 return 0;
136}
137
138void corgi_ssp_lcdtg_send(u8 adrs, u8 data)
139{
140 corgi_ssp_dac_put(((adrs & 0x07) << 5) | (data & 0x1f));
141}
142
143void corgi_ssp_blduty_set(int duty)
144{
145 corgi_ssp_lcdtg_send(0x02,duty);
146}
147
148EXPORT_SYMBOL(corgi_ssp_lcdtg_send);
149EXPORT_SYMBOL(corgi_ssp_blduty_set);
150
151/*
152 * Max1111 Routines
153 */
154int corgi_ssp_max1111_get(ulong data)
155{
156 unsigned long flag;
157 long voltage = 0, voltage1 = 0, voltage2 = 0;
158
159 spin_lock_irqsave(&corgi_ssp_lock, flag);
160 if (ssp_machinfo->cs_max1111 >= 0)
161 GPCR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
162 ssp_disable(&corgi_ssp_dev);
163 ssp_config(&corgi_ssp_dev, (SSCR0_Motorola | (SSCR0_DSS & 0x07 )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_max1111));
164 ssp_enable(&corgi_ssp_dev);
165
166 udelay(1);
167
168 /* TB1/RB1 */
169 ssp_write_word(&corgi_ssp_dev,data);
170 ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1); /* null read */
171
172 /* TB12/RB2 */
173 ssp_write_word(&corgi_ssp_dev,0);
174 ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1);
175
176 /* TB13/RB3*/
177 ssp_write_word(&corgi_ssp_dev,0);
178 ssp_read_word(&corgi_ssp_dev, (u32*)&voltage2);
179
180 ssp_disable(&corgi_ssp_dev);
181 ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
182 ssp_enable(&corgi_ssp_dev);
183 if (ssp_machinfo->cs_max1111 >= 0)
184 GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111);
185 spin_unlock_irqrestore(&corgi_ssp_lock, flag);
186
187 if (voltage1 & 0xc0 || voltage2 & 0x3f)
188 voltage = -1;
189 else
190 voltage = ((voltage1 << 2) & 0xfc) | ((voltage2 >> 6) & 0x03);
191
192 return voltage;
193}
194
195EXPORT_SYMBOL(corgi_ssp_max1111_get);
196
197/*
198 * Support Routines
199 */
200
201void __init corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo)
202{
203 ssp_machinfo = machinfo;
204}
205
206static int __devinit corgi_ssp_probe(struct platform_device *dev)
207{
208 int ret;
209
210 /* Chip Select - Disable All */
211 if (ssp_machinfo->cs_lcdcon >= 0)
212 pxa_gpio_mode(ssp_machinfo->cs_lcdcon | GPIO_OUT | GPIO_DFLT_HIGH);
213 if (ssp_machinfo->cs_max1111 >= 0)
214 pxa_gpio_mode(ssp_machinfo->cs_max1111 | GPIO_OUT | GPIO_DFLT_HIGH);
215 if (ssp_machinfo->cs_ads7846 >= 0)
216 pxa_gpio_mode(ssp_machinfo->cs_ads7846 | GPIO_OUT | GPIO_DFLT_HIGH);
217
218 ret = ssp_init(&corgi_ssp_dev, ssp_machinfo->port, 0);
219
220 if (ret)
221 printk(KERN_ERR "Unable to register SSP handler!\n");
222 else {
223 ssp_disable(&corgi_ssp_dev);
224 ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846));
225 ssp_enable(&corgi_ssp_dev);
226 }
227
228 return ret;
229}
230
231static int corgi_ssp_remove(struct platform_device *dev)
232{
233 ssp_exit(&corgi_ssp_dev);
234 return 0;
235}
236
237static int corgi_ssp_suspend(struct platform_device *dev, pm_message_t state)
238{
239 ssp_flush(&corgi_ssp_dev);
240 ssp_save_state(&corgi_ssp_dev,&corgi_ssp_state);
241
242 return 0;
243}
244
245static int corgi_ssp_resume(struct platform_device *dev)
246{
247 if (ssp_machinfo->cs_lcdcon >= 0)
248 GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon); /* High - Disable LCD Control/Timing Gen */
249 if (ssp_machinfo->cs_max1111 >= 0)
250 GPSR(ssp_machinfo->cs_max1111) = GPIO_bit(ssp_machinfo->cs_max1111); /* High - Disable MAX1111*/
251 if (ssp_machinfo->cs_ads7846 >= 0)
252 GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); /* High - Disable ADS7846*/
253 ssp_restore_state(&corgi_ssp_dev,&corgi_ssp_state);
254 ssp_enable(&corgi_ssp_dev);
255
256 return 0;
257}
258
259static struct platform_driver corgissp_driver = {
260 .probe = corgi_ssp_probe,
261 .remove = corgi_ssp_remove,
262 .suspend = corgi_ssp_suspend,
263 .resume = corgi_ssp_resume,
264 .driver = {
265 .name = "corgi-ssp",
266 },
267};
268
269int __init corgi_ssp_init(void)
270{
271 return platform_driver_register(&corgissp_driver);
272}
273
274arch_initcall(corgi_ssp_init);
diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h
index 7239281788de..585970ef08ce 100644
--- a/arch/arm/mach-pxa/include/mach/corgi.h
+++ b/arch/arm/mach-pxa/include/mach/corgi.h
@@ -113,7 +113,6 @@
113 * Shared data structures 113 * Shared data structures
114 */ 114 */
115extern struct platform_device corgiscoop_device; 115extern struct platform_device corgiscoop_device;
116extern struct platform_device corgissp_device;
117 116
118#endif /* __ASM_ARCH_CORGI_H */ 117#endif /* __ASM_ARCH_CORGI_H */
119 118
diff --git a/arch/arm/mach-pxa/sharpsl.h b/arch/arm/mach-pxa/sharpsl.h
index 1439785d3979..0cc1203c5bef 100644
--- a/arch/arm/mach-pxa/sharpsl.h
+++ b/arch/arm/mach-pxa/sharpsl.h
@@ -10,29 +10,6 @@
10#include <mach/sharpsl_pm.h> 10#include <mach/sharpsl_pm.h>
11 11
12/* 12/*
13 * SharpSL SSP Driver
14 */
15struct corgissp_machinfo {
16 int port;
17 int cs_lcdcon;
18 int cs_ads7846;
19 int cs_max1111;
20 int clk_lcdcon;
21 int clk_ads7846;
22 int clk_max1111;
23};
24
25void corgi_ssp_set_machinfo(struct corgissp_machinfo *machinfo);
26
27
28/*
29 * SharpSL/Corgi LCD Driver
30 */
31void corgi_lcdtg_suspend(void);
32void corgi_lcdtg_hw_init(int mode);
33
34
35/*
36 * SharpSL Battery/PM Driver 13 * SharpSL Battery/PM Driver
37 */ 14 */
38#define READ_GPIO_BIT(x) (GPLR(x) & GPIO_bit(x)) 15#define READ_GPIO_BIT(x) (GPLR(x) & GPIO_bit(x))
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-12 15:57:35 -0400