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-rw-r--r--arch/mips/pci/ops-vr41xx.c6
-rw-r--r--arch/mips/pci/pci-vr41xx.c88
-rw-r--r--arch/mips/pci/pci-vr41xx.h69
-rw-r--r--include/asm-mips/vr41xx/pci.h90
-rw-r--r--include/asm-mips/vr41xx/vr41xx.h70
5 files changed, 181 insertions, 142 deletions
diff --git a/arch/mips/pci/ops-vr41xx.c b/arch/mips/pci/ops-vr41xx.c
index 44654605e461..430429b22ae1 100644
--- a/arch/mips/pci/ops-vr41xx.c
+++ b/arch/mips/pci/ops-vr41xx.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2001-2003 MontaVista Software Inc. 4 * Copyright (C) 2001-2003 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com> 5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6 * Copyright (C) 2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 6 * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -29,8 +29,8 @@
29 29
30#include <asm/io.h> 30#include <asm/io.h>
31 31
32#define PCICONFDREG KSEG1ADDR(0x0f000c14) 32#define PCICONFDREG (void __iomem *)KSEG1ADDR(0x0f000c14)
33#define PCICONFAREG KSEG1ADDR(0x0f000c18) 33#define PCICONFAREG (void __iomem *)KSEG1ADDR(0x0f000c18)
34 34
35static inline int set_pci_configuration_address(unsigned char number, 35static inline int set_pci_configuration_address(unsigned char number,
36 unsigned int devfn, int where) 36 unsigned int devfn, int where)
diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c
index f3ccbf7fada4..91df4da7ddb9 100644
--- a/arch/mips/pci/pci-vr41xx.c
+++ b/arch/mips/pci/pci-vr41xx.c
@@ -3,8 +3,8 @@
3 * 3 *
4 * Copyright (C) 2001-2003 MontaVista Software Inc. 4 * Copyright (C) 2001-2003 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com> 5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6 * Copyright (C) 2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 6 * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
@@ -31,12 +31,18 @@
31 31
32#include <asm/cpu.h> 32#include <asm/cpu.h>
33#include <asm/io.h> 33#include <asm/io.h>
34#include <asm/vr41xx/pci.h>
34#include <asm/vr41xx/vr41xx.h> 35#include <asm/vr41xx/vr41xx.h>
35 36
36#include "pci-vr41xx.h" 37#include "pci-vr41xx.h"
37 38
38extern struct pci_ops vr41xx_pci_ops; 39extern struct pci_ops vr41xx_pci_ops;
39 40
41static void __iomem *pciu_base;
42
43#define pciu_read(offset) readl(pciu_base + (offset))
44#define pciu_write(offset, value) writel((value), pciu_base + (offset))
45
40static struct pci_master_address_conversion pci_master_memory1 = { 46static struct pci_master_address_conversion pci_master_memory1 = {
41 .bus_base_address = PCI_MASTER_MEM1_BUS_BASE_ADDRESS, 47 .bus_base_address = PCI_MASTER_MEM1_BUS_BASE_ADDRESS,
42 .address_mask = PCI_MASTER_MEM1_ADDRESS_MASK, 48 .address_mask = PCI_MASTER_MEM1_ADDRESS_MASK,
@@ -113,6 +119,15 @@ static int __init vr41xx_pciu_init(void)
113 119
114 setup = &vr41xx_pci_controller_unit_setup; 120 setup = &vr41xx_pci_controller_unit_setup;
115 121
122 if (request_mem_region(PCIU_BASE, PCIU_SIZE, "PCIU") == NULL)
123 return -EBUSY;
124
125 pciu_base = ioremap(PCIU_BASE, PCIU_SIZE);
126 if (pciu_base == NULL) {
127 release_mem_region(PCIU_BASE, PCIU_SIZE);
128 return -EBUSY;
129 }
130
116 /* Disable PCI interrupt */ 131 /* Disable PCI interrupt */
117 vr41xx_disable_pciint(); 132 vr41xx_disable_pciint();
118 133
@@ -129,14 +144,14 @@ static int __init vr41xx_pciu_init(void)
129 pci_clock_max = PCI_CLOCK_MAX; 144 pci_clock_max = PCI_CLOCK_MAX;
130 vtclock = vr41xx_get_vtclock_frequency(); 145 vtclock = vr41xx_get_vtclock_frequency();
131 if (vtclock < pci_clock_max) 146 if (vtclock < pci_clock_max)
132 writel(EQUAL_VTCLOCK, PCICLKSELREG); 147 pciu_write(PCICLKSELREG, EQUAL_VTCLOCK);
133 else if ((vtclock / 2) < pci_clock_max) 148 else if ((vtclock / 2) < pci_clock_max)
134 writel(HALF_VTCLOCK, PCICLKSELREG); 149 pciu_write(PCICLKSELREG, HALF_VTCLOCK);
135 else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 && 150 else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 &&
136 (vtclock / 3) < pci_clock_max) 151 (vtclock / 3) < pci_clock_max)
137 writel(ONE_THIRD_VTCLOCK, PCICLKSELREG); 152 pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK);
138 else if ((vtclock / 4) < pci_clock_max) 153 else if ((vtclock / 4) < pci_clock_max)
139 writel(QUARTER_VTCLOCK, PCICLKSELREG); 154 pciu_write(PCICLKSELREG, QUARTER_VTCLOCK);
140 else { 155 else {
141 printk(KERN_ERR "PCI Clock is over 33MHz.\n"); 156 printk(KERN_ERR "PCI Clock is over 33MHz.\n");
142 return -EINVAL; 157 return -EINVAL;
@@ -151,11 +166,11 @@ static int __init vr41xx_pciu_init(void)
151 MASTER_MSK(master->address_mask) | 166 MASTER_MSK(master->address_mask) |
152 WINEN | 167 WINEN |
153 PCIA(master->pci_base_address); 168 PCIA(master->pci_base_address);
154 writel(val, PCIMMAW1REG); 169 pciu_write(PCIMMAW1REG, val);
155 } else { 170 } else {
156 val = readl(PCIMMAW1REG); 171 val = pciu_read(PCIMMAW1REG);
157 val &= ~WINEN; 172 val &= ~WINEN;
158 writel(val, PCIMMAW1REG); 173 pciu_write(PCIMMAW1REG, val);
159 } 174 }
160 175
161 if (setup->master_memory2 != NULL) { 176 if (setup->master_memory2 != NULL) {
@@ -164,11 +179,11 @@ static int __init vr41xx_pciu_init(void)
164 MASTER_MSK(master->address_mask) | 179 MASTER_MSK(master->address_mask) |
165 WINEN | 180 WINEN |
166 PCIA(master->pci_base_address); 181 PCIA(master->pci_base_address);
167 writel(val, PCIMMAW2REG); 182 pciu_write(PCIMMAW2REG, val);
168 } else { 183 } else {
169 val = readl(PCIMMAW2REG); 184 val = pciu_read(PCIMMAW2REG);
170 val &= ~WINEN; 185 val &= ~WINEN;
171 writel(val, PCIMMAW2REG); 186 pciu_write(PCIMMAW2REG, val);
172 } 187 }
173 188
174 if (setup->target_memory1 != NULL) { 189 if (setup->target_memory1 != NULL) {
@@ -176,11 +191,11 @@ static int __init vr41xx_pciu_init(void)
176 val = TARGET_MSK(target->address_mask) | 191 val = TARGET_MSK(target->address_mask) |
177 WINEN | 192 WINEN |
178 ITA(target->bus_base_address); 193 ITA(target->bus_base_address);
179 writel(val, PCITAW1REG); 194 pciu_write(PCITAW1REG, val);
180 } else { 195 } else {
181 val = readl(PCITAW1REG); 196 val = pciu_read(PCITAW1REG);
182 val &= ~WINEN; 197 val &= ~WINEN;
183 writel(val, PCITAW1REG); 198 pciu_write(PCITAW1REG, val);
184 } 199 }
185 200
186 if (setup->target_memory2 != NULL) { 201 if (setup->target_memory2 != NULL) {
@@ -188,11 +203,11 @@ static int __init vr41xx_pciu_init(void)
188 val = TARGET_MSK(target->address_mask) | 203 val = TARGET_MSK(target->address_mask) |
189 WINEN | 204 WINEN |
190 ITA(target->bus_base_address); 205 ITA(target->bus_base_address);
191 writel(val, PCITAW2REG); 206 pciu_write(PCITAW2REG, val);
192 } else { 207 } else {
193 val = readl(PCITAW2REG); 208 val = pciu_read(PCITAW2REG);
194 val &= ~WINEN; 209 val &= ~WINEN;
195 writel(val, PCITAW2REG); 210 pciu_write(PCITAW2REG, val);
196 } 211 }
197 212
198 if (setup->master_io != NULL) { 213 if (setup->master_io != NULL) {
@@ -201,50 +216,50 @@ static int __init vr41xx_pciu_init(void)
201 MASTER_MSK(master->address_mask) | 216 MASTER_MSK(master->address_mask) |
202 WINEN | 217 WINEN |
203 PCIIA(master->pci_base_address); 218 PCIIA(master->pci_base_address);
204 writel(val, PCIMIOAWREG); 219 pciu_write(PCIMIOAWREG, val);
205 } else { 220 } else {
206 val = readl(PCIMIOAWREG); 221 val = pciu_read(PCIMIOAWREG);
207 val &= ~WINEN; 222 val &= ~WINEN;
208 writel(val, PCIMIOAWREG); 223 pciu_write(PCIMIOAWREG, val);
209 } 224 }
210 225
211 if (setup->exclusive_access == CANNOT_LOCK_FROM_DEVICE) 226 if (setup->exclusive_access == CANNOT_LOCK_FROM_DEVICE)
212 writel(UNLOCK, PCIEXACCREG); 227 pciu_write(PCIEXACCREG, UNLOCK);
213 else 228 else
214 writel(0, PCIEXACCREG); 229 pciu_write(PCIEXACCREG, 0);
215 230
216 if (current_cpu_data.cputype == CPU_VR4122) 231 if (current_cpu_data.cputype == CPU_VR4122)
217 writel(TRDYV(setup->wait_time_limit_from_irdy_to_trdy), PCITRDYVREG); 232 pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy));
218 233
219 writel(MLTIM(setup->master_latency_timer), LATTIMEREG); 234 pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer));
220 235
221 if (setup->mailbox != NULL) { 236 if (setup->mailbox != NULL) {
222 mailbox = setup->mailbox; 237 mailbox = setup->mailbox;
223 val = MBADD(mailbox->base_address) | TYPE_32BITSPACE | 238 val = MBADD(mailbox->base_address) | TYPE_32BITSPACE |
224 MSI_MEMORY | PREF_APPROVAL; 239 MSI_MEMORY | PREF_APPROVAL;
225 writel(val, MAILBAREG); 240 pciu_write(MAILBAREG, val);
226 } 241 }
227 242
228 if (setup->target_window1) { 243 if (setup->target_window1) {
229 window = setup->target_window1; 244 window = setup->target_window1;
230 val = PMBA(window->base_address) | TYPE_32BITSPACE | 245 val = PMBA(window->base_address) | TYPE_32BITSPACE |
231 MSI_MEMORY | PREF_APPROVAL; 246 MSI_MEMORY | PREF_APPROVAL;
232 writel(val, PCIMBA1REG); 247 pciu_write(PCIMBA1REG, val);
233 } 248 }
234 249
235 if (setup->target_window2) { 250 if (setup->target_window2) {
236 window = setup->target_window2; 251 window = setup->target_window2;
237 val = PMBA(window->base_address) | TYPE_32BITSPACE | 252 val = PMBA(window->base_address) | TYPE_32BITSPACE |
238 MSI_MEMORY | PREF_APPROVAL; 253 MSI_MEMORY | PREF_APPROVAL;
239 writel(val, PCIMBA2REG); 254 pciu_write(PCIMBA2REG, val);
240 } 255 }
241 256
242 val = readl(RETVALREG); 257 val = pciu_read(RETVALREG);
243 val &= ~RTYVAL_MASK; 258 val &= ~RTYVAL_MASK;
244 val |= RTYVAL(setup->retry_limit); 259 val |= RTYVAL(setup->retry_limit);
245 writel(val, RETVALREG); 260 pciu_write(RETVALREG, val);
246 261
247 val = readl(PCIAPCNTREG); 262 val = pciu_read(PCIAPCNTREG);
248 val &= ~(TKYGNT | PAPC); 263 val &= ~(TKYGNT | PAPC);
249 264
250 switch (setup->arbiter_priority_control) { 265 switch (setup->arbiter_priority_control) {
@@ -262,15 +277,16 @@ static int __init vr41xx_pciu_init(void)
262 if (setup->take_away_gnt_mode == PCI_TAKE_AWAY_GNT_ENABLE) 277 if (setup->take_away_gnt_mode == PCI_TAKE_AWAY_GNT_ENABLE)
263 val |= TKYGNT_ENABLE; 278 val |= TKYGNT_ENABLE;
264 279
265 writel(val, PCIAPCNTREG); 280 pciu_write(PCIAPCNTREG, val);
266 281
267 writel(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 282 pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
268 PCI_COMMAND_PARITY | PCI_COMMAND_SERR, COMMANDREG); 283 PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
284 PCI_COMMAND_SERR);
269 285
270 /* Clear bus error */ 286 /* Clear bus error */
271 readl(BUSERRADREG); 287 pciu_read(BUSERRADREG);
272 288
273 writel(BLOODY_CONFIG_DONE, PCIENREG); 289 pciu_write(PCIENREG, PCIU_CONFIG_DONE);
274 290
275 if (setup->mem_resource != NULL) 291 if (setup->mem_resource != NULL)
276 vr41xx_pci_controller.mem_resource = setup->mem_resource; 292 vr41xx_pci_controller.mem_resource = setup->mem_resource;
diff --git a/arch/mips/pci/pci-vr41xx.h b/arch/mips/pci/pci-vr41xx.h
index 23815c8b903c..e087ec55641d 100644
--- a/arch/mips/pci/pci-vr41xx.h
+++ b/arch/mips/pci/pci-vr41xx.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * Copyright (C) 2002 MontaVista Software Inc. 4 * Copyright (C) 2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com> 5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6 * Copyright (C) 2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> 6 * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
@@ -22,11 +22,14 @@
22#ifndef __PCI_VR41XX_H 22#ifndef __PCI_VR41XX_H
23#define __PCI_VR41XX_H 23#define __PCI_VR41XX_H
24 24
25#define PCIMMAW1REG KSEG1ADDR(0x0f000c00) 25#define PCIU_BASE 0x0f000c00UL
26#define PCIMMAW2REG KSEG1ADDR(0x0f000c04) 26#define PCIU_SIZE 0x200UL
27#define PCITAW1REG KSEG1ADDR(0x0f000c08) 27
28#define PCITAW2REG KSEG1ADDR(0x0f000c0c) 28#define PCIMMAW1REG 0x00
29#define PCIMIOAWREG KSEG1ADDR(0x0f000c10) 29#define PCIMMAW2REG 0x04
30#define PCITAW1REG 0x08
31#define PCITAW2REG 0x0c
32#define PCIMIOAWREG 0x10
30 #define IBA(addr) ((addr) & 0xff000000U) 33 #define IBA(addr) ((addr) & 0xff000000U)
31 #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U) 34 #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
32 #define PCIA(addr) (((addr) >> 24) & 0x000000ffU) 35 #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
@@ -34,13 +37,13 @@
34 #define ITA(addr) (((addr) >> 24) & 0x000000ffU) 37 #define ITA(addr) (((addr) >> 24) & 0x000000ffU)
35 #define PCIIA(addr) (((addr) >> 24) & 0x000000ffU) 38 #define PCIIA(addr) (((addr) >> 24) & 0x000000ffU)
36 #define WINEN 0x1000U 39 #define WINEN 0x1000U
37#define PCICONFDREG KSEG1ADDR(0x0f000c14) 40#define PCICONFDREG 0x14
38#define PCICONFAREG KSEG1ADDR(0x0f000c18) 41#define PCICONFAREG 0x18
39#define PCIMAILREG KSEG1ADDR(0x0f000c1c) 42#define PCIMAILREG 0x1c
40#define BUSERRADREG KSEG1ADDR(0x0f000c24) 43#define BUSERRADREG 0x24
41 #define EA(reg) ((reg) &0xfffffffc) 44 #define EA(reg) ((reg) &0xfffffffc)
42 45
43#define INTCNTSTAREG KSEG1ADDR(0x0f000c28) 46#define INTCNTSTAREG 0x28
44 #define MABTCLR 0x80000000U 47 #define MABTCLR 0x80000000U
45 #define TRDYCLR 0x40000000U 48 #define TRDYCLR 0x40000000U
46 #define PARCLR 0x20000000U 49 #define PARCLR 0x20000000U
@@ -67,34 +70,34 @@
67 #define MABORT 0x00000002U 70 #define MABORT 0x00000002U
68 #define TABORT 0x00000001U 71 #define TABORT 0x00000001U
69 72
70#define PCIEXACCREG KSEG1ADDR(0x0f000c2c) 73#define PCIEXACCREG 0x2c
71 #define UNLOCK 0x2U 74 #define UNLOCK 0x2U
72 #define EAREQ 0x1U 75 #define EAREQ 0x1U
73#define PCIRECONTREG KSEG1ADDR(0x0f000c30) 76#define PCIRECONTREG 0x30
74 #define RTRYCNT(reg) ((reg) & 0x000000ffU) 77 #define RTRYCNT(reg) ((reg) & 0x000000ffU)
75#define PCIENREG KSEG1ADDR(0x0f000c34) 78#define PCIENREG 0x34
76 #define BLOODY_CONFIG_DONE 0x4U 79 #define PCIU_CONFIG_DONE 0x4U
77#define PCICLKSELREG KSEG1ADDR(0x0f000c38) 80#define PCICLKSELREG 0x38
78 #define EQUAL_VTCLOCK 0x2U 81 #define EQUAL_VTCLOCK 0x2U
79 #define HALF_VTCLOCK 0x0U 82 #define HALF_VTCLOCK 0x0U
80 #define ONE_THIRD_VTCLOCK 0x3U 83 #define ONE_THIRD_VTCLOCK 0x3U
81 #define QUARTER_VTCLOCK 0x1U 84 #define QUARTER_VTCLOCK 0x1U
82#define PCITRDYVREG KSEG1ADDR(0x0f000c3c) 85#define PCITRDYVREG 0x3c
83 #define TRDYV(val) ((uint32_t)(val) & 0xffU) 86 #define TRDYV(val) ((uint32_t)(val) & 0xffU)
84#define PCICLKRUNREG KSEG1ADDR(0x0f000c60) 87#define PCICLKRUNREG 0x60
85 88
86#define VENDORIDREG KSEG1ADDR(0x0f000d00) 89#define VENDORIDREG 0x100
87#define DEVICEIDREG KSEG1ADDR(0x0f000d00) 90#define DEVICEIDREG 0x100
88#define COMMANDREG KSEG1ADDR(0x0f000d04) 91#define COMMANDREG 0x104
89#define STATUSREG KSEG1ADDR(0x0f000d04) 92#define STATUSREG 0x104
90#define REVIDREG KSEG1ADDR(0x0f000d08) 93#define REVIDREG 0x108
91#define CLASSREG KSEG1ADDR(0x0f000d08) 94#define CLASSREG 0x108
92#define CACHELSREG KSEG1ADDR(0x0f000d0c) 95#define CACHELSREG 0x10c
93#define LATTIMEREG KSEG1ADDR(0x0f000d0c) 96#define LATTIMEREG 0x10c
94 #define MLTIM(val) (((uint32_t)(val) << 7) & 0xff00U) 97 #define MLTIM(val) (((uint32_t)(val) << 7) & 0xff00U)
95#define MAILBAREG KSEG1ADDR(0x0f000d10) 98#define MAILBAREG 0x110
96#define PCIMBA1REG KSEG1ADDR(0x0f000d14) 99#define PCIMBA1REG 0x114
97#define PCIMBA2REG KSEG1ADDR(0x0f000d18) 100#define PCIMBA2REG 0x118
98 #define MBADD(base) ((base) & 0xfffff800U) 101 #define MBADD(base) ((base) & 0xfffff800U)
99 #define PMBA(base) ((base) & 0xffe00000U) 102 #define PMBA(base) ((base) & 0xffe00000U)
100 #define PREF 0x8U 103 #define PREF 0x8U
@@ -104,10 +107,10 @@
104 #define TYPE_32BITSPACE 0x0U 107 #define TYPE_32BITSPACE 0x0U
105 #define MSI 0x1U 108 #define MSI 0x1U
106 #define MSI_MEMORY 0x0U 109 #define MSI_MEMORY 0x0U
107#define INTLINEREG KSEG1ADDR(0x0f000d3c) 110#define INTLINEREG 0x13c
108#define INTPINREG KSEG1ADDR(0x0f000d3c) 111#define INTPINREG 0x13c
109#define RETVALREG KSEG1ADDR(0x0f000d40) 112#define RETVALREG 0x140
110#define PCIAPCNTREG KSEG1ADDR(0x0f000d40) 113#define PCIAPCNTREG 0x140
111 #define TKYGNT 0x04000000U 114 #define TKYGNT 0x04000000U
112 #define TKYGNT_ENABLE 0x04000000U 115 #define TKYGNT_ENABLE 0x04000000U
113 #define TKYGNT_DISABLE 0x00000000U 116 #define TKYGNT_DISABLE 0x00000000U
diff --git a/include/asm-mips/vr41xx/pci.h b/include/asm-mips/vr41xx/pci.h
new file mode 100644
index 000000000000..c473aa78d1d4
--- /dev/null
+++ b/include/asm-mips/vr41xx/pci.h
@@ -0,0 +1,90 @@
1/*
2 * Include file for NEC VR4100 series PCI Control Unit.
3 *
4 * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __NEC_VR41XX_PCI_H
21#define __NEC_VR41XX_PCI_H
22
23#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU
24
25struct pci_master_address_conversion {
26 uint32_t bus_base_address;
27 uint32_t address_mask;
28 uint32_t pci_base_address;
29};
30
31struct pci_target_address_conversion {
32 uint32_t address_mask;
33 uint32_t bus_base_address;
34};
35
36typedef enum {
37 CANNOT_LOCK_FROM_DEVICE,
38 CAN_LOCK_FROM_DEVICE,
39} pci_exclusive_access_t;
40
41struct pci_mailbox_address {
42 uint32_t base_address;
43};
44
45struct pci_target_address_window {
46 uint32_t base_address;
47};
48
49typedef enum {
50 PCI_ARBITRATION_MODE_FAIR,
51 PCI_ARBITRATION_MODE_ALTERNATE_0,
52 PCI_ARBITRATION_MODE_ALTERNATE_B,
53} pci_arbiter_priority_control_t;
54
55typedef enum {
56 PCI_TAKE_AWAY_GNT_DISABLE,
57 PCI_TAKE_AWAY_GNT_ENABLE,
58} pci_take_away_gnt_mode_t;
59
60struct pci_controller_unit_setup {
61 struct pci_master_address_conversion *master_memory1;
62 struct pci_master_address_conversion *master_memory2;
63
64 struct pci_target_address_conversion *target_memory1;
65 struct pci_target_address_conversion *target_memory2;
66
67 struct pci_master_address_conversion *master_io;
68
69 pci_exclusive_access_t exclusive_access;
70
71 uint32_t pci_clock_max;
72 uint8_t wait_time_limit_from_irdy_to_trdy; /* Only VR4122 is supported */
73
74 struct pci_mailbox_address *mailbox;
75 struct pci_target_address_window *target_window1;
76 struct pci_target_address_window *target_window2;
77
78 uint8_t master_latency_timer;
79 uint8_t retry_limit;
80
81 pci_arbiter_priority_control_t arbiter_priority_control;
82 pci_take_away_gnt_mode_t take_away_gnt_mode;
83
84 struct resource *mem_resource;
85 struct resource *io_resource;
86};
87
88extern void vr41xx_pciu_setup(struct pci_controller_unit_setup *setup);
89
90#endif /* __NEC_VR41XX_PCI_H */
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h
index 50a3874622a7..ad0d1ea144f0 100644
--- a/include/asm-mips/vr41xx/vr41xx.h
+++ b/include/asm-mips/vr41xx/vr41xx.h
@@ -231,74 +231,4 @@ enum {
231 DATA_HIGH 231 DATA_HIGH
232}; 232};
233 233
234/*
235 * PCI Control Unit
236 */
237#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU
238
239struct pci_master_address_conversion {
240 uint32_t bus_base_address;
241 uint32_t address_mask;
242 uint32_t pci_base_address;
243};
244
245struct pci_target_address_conversion {
246 uint32_t address_mask;
247 uint32_t bus_base_address;
248};
249
250typedef enum {
251 CANNOT_LOCK_FROM_DEVICE,
252 CAN_LOCK_FROM_DEVICE,
253} pci_exclusive_access_t;
254
255struct pci_mailbox_address {
256 uint32_t base_address;
257};
258
259struct pci_target_address_window {
260 uint32_t base_address;
261};
262
263typedef enum {
264 PCI_ARBITRATION_MODE_FAIR,
265 PCI_ARBITRATION_MODE_ALTERNATE_0,
266 PCI_ARBITRATION_MODE_ALTERNATE_B,
267} pci_arbiter_priority_control_t;
268
269typedef enum {
270 PCI_TAKE_AWAY_GNT_DISABLE,
271 PCI_TAKE_AWAY_GNT_ENABLE,
272} pci_take_away_gnt_mode_t;
273
274struct pci_controller_unit_setup {
275 struct pci_master_address_conversion *master_memory1;
276 struct pci_master_address_conversion *master_memory2;
277
278 struct pci_target_address_conversion *target_memory1;
279 struct pci_target_address_conversion *target_memory2;
280
281 struct pci_master_address_conversion *master_io;
282
283 pci_exclusive_access_t exclusive_access;
284
285 uint32_t pci_clock_max;
286 uint8_t wait_time_limit_from_irdy_to_trdy; /* Only VR4122 is supported */
287
288 struct pci_mailbox_address *mailbox;
289 struct pci_target_address_window *target_window1;
290 struct pci_target_address_window *target_window2;
291
292 uint8_t master_latency_timer;
293 uint8_t retry_limit;
294
295 pci_arbiter_priority_control_t arbiter_priority_control;
296 pci_take_away_gnt_mode_t take_away_gnt_mode;
297
298 struct resource *mem_resource;
299 struct resource *io_resource;
300};
301
302extern void vr41xx_pciu_setup(struct pci_controller_unit_setup *setup);
303
304#endif /* __NEC_VR41XX_H */ 234#endif /* __NEC_VR41XX_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 12:18:25 -0500