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-rw-r--r--arch/arm/plat-s3c64xx/Kconfig1
-rw-r--r--arch/arm/plat-s3c64xx/s3c6400-clock.c241
2 files changed, 40 insertions, 202 deletions
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig
index e6da87a5885c..bec12242706b 100644
--- a/arch/arm/plat-s3c64xx/Kconfig
+++ b/arch/arm/plat-s3c64xx/Kconfig
@@ -13,6 +13,7 @@ config PLAT_S3C64XX
13 select ARM_VIC 13 select ARM_VIC
14 select NO_IOPORT 14 select NO_IOPORT
15 select ARCH_REQUIRE_GPIOLIB 15 select ARCH_REQUIRE_GPIOLIB
16 select SAMSUNG_CLKSRC
16 select S3C_GPIO_TRACK 17 select S3C_GPIO_TRACK
17 select S3C_GPIO_PULL_UPDOWN 18 select S3C_GPIO_PULL_UPDOWN
18 select S3C_GPIO_CFG_S3C24XX 19 select S3C_GPIO_CFG_S3C24XX
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 6fde910e414c..20af0c29979a 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -29,6 +29,7 @@
29 29
30#include <plat/regs-clock.h> 30#include <plat/regs-clock.h>
31#include <plat/clock.h> 31#include <plat/clock.h>
32#include <plat/clock-clksrc.h>
32#include <plat/cpu.h> 33#include <plat/cpu.h>
33#include <plat/pll.h> 34#include <plat/pll.h>
34 35
@@ -48,22 +49,6 @@ static struct clk clk_ext_xtal_mux = {
48#define clk_fout_mpll clk_mpll 49#define clk_fout_mpll clk_mpll
49#define clk_fout_epll clk_epll 50#define clk_fout_epll clk_epll
50 51
51struct clk_sources {
52 unsigned int nr_sources;
53 struct clk **sources;
54};
55
56struct clksrc_clk {
57 struct clk clk;
58 unsigned int mask;
59 unsigned int shift;
60
61 struct clk_sources *sources;
62
63 unsigned int divider_shift;
64 void __iomem *reg_divider;
65};
66
67static struct clk clk_fout_apll = { 52static struct clk clk_fout_apll = {
68 .name = "fout_apll", 53 .name = "fout_apll",
69 .id = -1, 54 .id = -1,
@@ -74,7 +59,7 @@ static struct clk *clk_src_apll_list[] = {
74 [1] = &clk_fout_apll, 59 [1] = &clk_fout_apll,
75}; 60};
76 61
77static struct clk_sources clk_src_apll = { 62static struct clksrc_sources clk_src_apll = {
78 .sources = clk_src_apll_list, 63 .sources = clk_src_apll_list,
79 .nr_sources = ARRAY_SIZE(clk_src_apll_list), 64 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
80}; 65};
@@ -84,8 +69,7 @@ static struct clksrc_clk clk_mout_apll = {
84 .name = "mout_apll", 69 .name = "mout_apll",
85 .id = -1, 70 .id = -1,
86 }, 71 },
87 .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT, 72 .reg_src = { S3C_CLK_SRC, 0, 1 },
88 .mask = S3C6400_CLKSRC_APLL_MOUT,
89 .sources = &clk_src_apll, 73 .sources = &clk_src_apll,
90}; 74};
91 75
@@ -94,7 +78,7 @@ static struct clk *clk_src_epll_list[] = {
94 [1] = &clk_fout_epll, 78 [1] = &clk_fout_epll,
95}; 79};
96 80
97static struct clk_sources clk_src_epll = { 81static struct clksrc_sources clk_src_epll = {
98 .sources = clk_src_epll_list, 82 .sources = clk_src_epll_list,
99 .nr_sources = ARRAY_SIZE(clk_src_epll_list), 83 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
100}; 84};
@@ -104,8 +88,7 @@ static struct clksrc_clk clk_mout_epll = {
104 .name = "mout_epll", 88 .name = "mout_epll",
105 .id = -1, 89 .id = -1,
106 }, 90 },
107 .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT, 91 .reg_src = { S3C_CLK_SRC, 2, 1 },
108 .mask = S3C6400_CLKSRC_EPLL_MOUT,
109 .sources = &clk_src_epll, 92 .sources = &clk_src_epll,
110}; 93};
111 94
@@ -114,7 +97,7 @@ static struct clk *clk_src_mpll_list[] = {
114 [1] = &clk_fout_mpll, 97 [1] = &clk_fout_mpll,
115}; 98};
116 99
117static struct clk_sources clk_src_mpll = { 100static struct clksrc_sources clk_src_mpll = {
118 .sources = clk_src_mpll_list, 101 .sources = clk_src_mpll_list,
119 .nr_sources = ARRAY_SIZE(clk_src_mpll_list), 102 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
120}; 103};
@@ -124,8 +107,7 @@ static struct clksrc_clk clk_mout_mpll = {
124 .name = "mout_mpll", 107 .name = "mout_mpll",
125 .id = -1, 108 .id = -1,
126 }, 109 },
127 .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT, 110 .reg_src = { S3C_CLK_SRC, 1, 1 },
128 .mask = S3C6400_CLKSRC_MPLL_MOUT,
129 .sources = &clk_src_mpll, 111 .sources = &clk_src_mpll,
130}; 112};
131 113
@@ -214,7 +196,7 @@ static struct clk *clkset_spi_mmc_list[] = {
214 &clk_27m, 196 &clk_27m,
215}; 197};
216 198
217static struct clk_sources clkset_spi_mmc = { 199static struct clksrc_sources clkset_spi_mmc = {
218 .sources = clkset_spi_mmc_list, 200 .sources = clkset_spi_mmc_list,
219 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), 201 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
220}; 202};
@@ -226,7 +208,7 @@ static struct clk *clkset_irda_list[] = {
226 &clk_27m, 208 &clk_27m,
227}; 209};
228 210
229static struct clk_sources clkset_irda = { 211static struct clksrc_sources clkset_irda = {
230 .sources = clkset_irda_list, 212 .sources = clkset_irda_list,
231 .nr_sources = ARRAY_SIZE(clkset_irda_list), 213 .nr_sources = ARRAY_SIZE(clkset_irda_list),
232}; 214};
@@ -238,7 +220,7 @@ static struct clk *clkset_uart_list[] = {
238 NULL 220 NULL
239}; 221};
240 222
241static struct clk_sources clkset_uart = { 223static struct clksrc_sources clkset_uart = {
242 .sources = clkset_uart_list, 224 .sources = clkset_uart_list,
243 .nr_sources = ARRAY_SIZE(clkset_uart_list), 225 .nr_sources = ARRAY_SIZE(clkset_uart_list),
244}; 226};
@@ -250,7 +232,7 @@ static struct clk *clkset_uhost_list[] = {
250 &clk_fin_epll, 232 &clk_fin_epll,
251}; 233};
252 234
253static struct clk_sources clkset_uhost = { 235static struct clksrc_sources clkset_uhost = {
254 .sources = clkset_uhost_list, 236 .sources = clkset_uhost_list,
255 .nr_sources = ARRAY_SIZE(clkset_uhost_list), 237 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
256}; 238};
@@ -265,94 +247,6 @@ static struct clk_sources clkset_uhost = {
265 * have a common parent divisor so are not included here. 247 * have a common parent divisor so are not included here.
266 */ 248 */
267 249
268static inline struct clksrc_clk *to_clksrc(struct clk *clk)
269{
270 return container_of(clk, struct clksrc_clk, clk);
271}
272
273static unsigned long s3c64xx_getrate_clksrc(struct clk *clk)
274{
275 struct clksrc_clk *sclk = to_clksrc(clk);
276 unsigned long rate = clk_get_rate(clk->parent);
277 u32 clkdiv = __raw_readl(sclk->reg_divider);
278
279 clkdiv >>= sclk->divider_shift;
280 clkdiv &= 0xf;
281 clkdiv++;
282
283 rate /= clkdiv;
284 return rate;
285}
286
287static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate)
288{
289 struct clksrc_clk *sclk = to_clksrc(clk);
290 void __iomem *reg = sclk->reg_divider;
291 unsigned int div;
292 u32 val;
293
294 rate = clk_round_rate(clk, rate);
295 div = clk_get_rate(clk->parent) / rate;
296 if (div > 16)
297 return -EINVAL;
298
299 val = __raw_readl(reg);
300 val &= ~(0xf << sclk->divider_shift);
301 val |= (div - 1) << sclk->divider_shift;
302 __raw_writel(val, reg);
303
304 return 0;
305}
306
307static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent)
308{
309 struct clksrc_clk *sclk = to_clksrc(clk);
310 struct clk_sources *srcs = sclk->sources;
311 u32 clksrc = __raw_readl(S3C_CLK_SRC);
312 int src_nr = -1;
313 int ptr;
314
315 for (ptr = 0; ptr < srcs->nr_sources; ptr++)
316 if (srcs->sources[ptr] == parent) {
317 src_nr = ptr;
318 break;
319 }
320
321 if (src_nr >= 0) {
322 clksrc &= ~sclk->mask;
323 clksrc |= src_nr << sclk->shift;
324
325 __raw_writel(clksrc, S3C_CLK_SRC);
326
327 clk->parent = parent;
328 return 0;
329 }
330
331 return -EINVAL;
332}
333
334static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk,
335 unsigned long rate)
336{
337 unsigned long parent_rate = clk_get_rate(clk->parent);
338 int div;
339
340 if (rate > parent_rate)
341 rate = parent_rate;
342 else {
343 div = parent_rate / rate;
344
345 if (div == 0)
346 div = 1;
347 if (div > 16)
348 div = 16;
349
350 rate = parent_rate / div;
351 }
352
353 return rate;
354}
355
356/* clocks that feed other parts of the clock source tree */ 250/* clocks that feed other parts of the clock source tree */
357 251
358static struct clk clk_iis_cd0 = { 252static struct clk clk_iis_cd0 = {
@@ -378,7 +272,7 @@ static struct clk *clkset_audio0_list[] = {
378 [4] = &clk_pcm_cd, 272 [4] = &clk_pcm_cd,
379}; 273};
380 274
381static struct clk_sources clkset_audio0 = { 275static struct clksrc_sources clkset_audio0 = {
382 .sources = clkset_audio0_list, 276 .sources = clkset_audio0_list,
383 .nr_sources = ARRAY_SIZE(clkset_audio0_list), 277 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
384}; 278};
@@ -391,7 +285,7 @@ static struct clk *clkset_audio1_list[] = {
391 [4] = &clk_pcm_cd, 285 [4] = &clk_pcm_cd,
392}; 286};
393 287
394static struct clk_sources clkset_audio1 = { 288static struct clksrc_sources clkset_audio1 = {
395 .sources = clkset_audio1_list, 289 .sources = clkset_audio1_list,
396 .nr_sources = ARRAY_SIZE(clkset_audio1_list), 290 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
397}; 291};
@@ -400,7 +294,7 @@ static struct clk *clkset_camif_list[] = {
400 &clk_h2, 294 &clk_h2,
401}; 295};
402 296
403static struct clk_sources clkset_camif = { 297static struct clksrc_sources clkset_camif = {
404 .sources = clkset_camif_list, 298 .sources = clkset_camif_list,
405 .nr_sources = ARRAY_SIZE(clkset_camif_list), 299 .nr_sources = ARRAY_SIZE(clkset_camif_list),
406}; 300};
@@ -413,11 +307,9 @@ static struct clksrc_clk clksrcs[] = {
413 .ctrlbit = S3C_CLKCON_SCLK_MMC0, 307 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
414 .enable = s3c64xx_sclk_ctrl, 308 .enable = s3c64xx_sclk_ctrl,
415 }, 309 },
416 .shift = S3C6400_CLKSRC_MMC0_SHIFT, 310 .reg_src = { S3C_CLK_SRC, 18, 2 },
417 .mask = S3C6400_CLKSRC_MMC0_MASK, 311 .reg_div = { S3C_CLK_DIV1, 0, 4 },
418 .sources = &clkset_spi_mmc, 312 .sources = &clkset_spi_mmc,
419 .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT,
420 .reg_divider = S3C_CLK_DIV1,
421 }, { 313 }, {
422 .clk = { 314 .clk = {
423 .name = "mmc_bus", 315 .name = "mmc_bus",
@@ -425,11 +317,9 @@ static struct clksrc_clk clksrcs[] = {
425 .ctrlbit = S3C_CLKCON_SCLK_MMC1, 317 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
426 .enable = s3c64xx_sclk_ctrl, 318 .enable = s3c64xx_sclk_ctrl,
427 }, 319 },
428 .shift = S3C6400_CLKSRC_MMC1_SHIFT, 320 .reg_src = { S3C_CLK_SRC, 20, 2 },
429 .mask = S3C6400_CLKSRC_MMC1_MASK, 321 .reg_div = { S3C_CLK_DIV1, 4, 4 },
430 .sources = &clkset_spi_mmc, 322 .sources = &clkset_spi_mmc,
431 .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT,
432 .reg_divider = S3C_CLK_DIV1,
433 }, { 323 }, {
434 .clk = { 324 .clk = {
435 .name = "mmc_bus", 325 .name = "mmc_bus",
@@ -437,11 +327,9 @@ static struct clksrc_clk clksrcs[] = {
437 .ctrlbit = S3C_CLKCON_SCLK_MMC2, 327 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
438 .enable = s3c64xx_sclk_ctrl, 328 .enable = s3c64xx_sclk_ctrl,
439 }, 329 },
440 .shift = S3C6400_CLKSRC_MMC2_SHIFT, 330 .reg_src = { S3C_CLK_SRC, 22, 2 },
441 .mask = S3C6400_CLKSRC_MMC2_MASK, 331 .reg_div = { S3C_CLK_DIV1, 8, 4 },
442 .sources = &clkset_spi_mmc, 332 .sources = &clkset_spi_mmc,
443 .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT,
444 .reg_divider = S3C_CLK_DIV1,
445 }, { 333 }, {
446 .clk = { 334 .clk = {
447 .name = "usb-bus-host", 335 .name = "usb-bus-host",
@@ -449,11 +337,9 @@ static struct clksrc_clk clksrcs[] = {
449 .ctrlbit = S3C_CLKCON_SCLK_UHOST, 337 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
450 .enable = s3c64xx_sclk_ctrl, 338 .enable = s3c64xx_sclk_ctrl,
451 }, 339 },
452 .shift = S3C6400_CLKSRC_UHOST_SHIFT, 340 .reg_src = { S3C_CLK_SRC, 5, 2 },
453 .mask = S3C6400_CLKSRC_UHOST_MASK, 341 .reg_div = { S3C_CLK_DIV1, 20, 4 },
454 .sources = &clkset_uhost, 342 .sources = &clkset_uhost,
455 .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT,
456 .reg_divider = S3C_CLK_DIV1,
457 }, { 343 }, {
458 .clk = { 344 .clk = {
459 .name = "uclk1", 345 .name = "uclk1",
@@ -461,11 +347,9 @@ static struct clksrc_clk clksrcs[] = {
461 .ctrlbit = S3C_CLKCON_SCLK_UART, 347 .ctrlbit = S3C_CLKCON_SCLK_UART,
462 .enable = s3c64xx_sclk_ctrl, 348 .enable = s3c64xx_sclk_ctrl,
463 }, 349 },
464 .shift = S3C6400_CLKSRC_UART_SHIFT, 350 .reg_src = { S3C_CLK_SRC, 13, 1 },
465 .mask = S3C6400_CLKSRC_UART_MASK, 351 .reg_div = { S3C_CLK_DIV2, 16, 4 },
466 .sources = &clkset_uart, 352 .sources = &clkset_uart,
467 .divider_shift = S3C6400_CLKDIV2_UART_SHIFT,
468 .reg_divider = S3C_CLK_DIV2,
469 }, { 353 }, {
470/* Where does UCLK0 come from? */ 354/* Where does UCLK0 come from? */
471 .clk = { 355 .clk = {
@@ -474,11 +358,9 @@ static struct clksrc_clk clksrcs[] = {
474 .ctrlbit = S3C_CLKCON_SCLK_SPI0, 358 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
475 .enable = s3c64xx_sclk_ctrl, 359 .enable = s3c64xx_sclk_ctrl,
476 }, 360 },
477 .shift = S3C6400_CLKSRC_SPI0_SHIFT, 361 .reg_src = { S3C_CLK_SRC, 14, 2 },
478 .mask = S3C6400_CLKSRC_SPI0_MASK, 362 .reg_div = { S3C_CLK_DIV2, 0, 4 },
479 .sources = &clkset_spi_mmc, 363 .sources = &clkset_spi_mmc,
480 .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT,
481 .reg_divider = S3C_CLK_DIV2,
482 }, { 364 }, {
483 .clk = { 365 .clk = {
484 .name = "spi-bus", 366 .name = "spi-bus",
@@ -486,11 +368,9 @@ static struct clksrc_clk clksrcs[] = {
486 .ctrlbit = S3C_CLKCON_SCLK_SPI1, 368 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
487 .enable = s3c64xx_sclk_ctrl, 369 .enable = s3c64xx_sclk_ctrl,
488 }, 370 },
489 .shift = S3C6400_CLKSRC_SPI1_SHIFT, 371 .reg_src = { S3C_CLK_SRC, 16, 2 },
490 .mask = S3C6400_CLKSRC_SPI1_MASK, 372 .reg_div = { S3C_CLK_DIV2, 4, 4 },
491 .sources = &clkset_spi_mmc, 373 .sources = &clkset_spi_mmc,
492 .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT,
493 .reg_divider = S3C_CLK_DIV2,
494 }, { 374 }, {
495 .clk = { 375 .clk = {
496 .name = "audio-bus", 376 .name = "audio-bus",
@@ -498,11 +378,9 @@ static struct clksrc_clk clksrcs[] = {
498 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, 378 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
499 .enable = s3c64xx_sclk_ctrl, 379 .enable = s3c64xx_sclk_ctrl,
500 }, 380 },
501 .shift = S3C6400_CLKSRC_AUDIO0_SHIFT, 381 .reg_src = { S3C_CLK_SRC, 7, 3 },
502 .mask = S3C6400_CLKSRC_AUDIO0_MASK, 382 .reg_div = { S3C_CLK_DIV2, 8, 4 },
503 .sources = &clkset_audio0, 383 .sources = &clkset_audio0,
504 .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT,
505 .reg_divider = S3C_CLK_DIV2,
506 }, { 384 }, {
507 .clk = { 385 .clk = {
508 .name = "audio-bus", 386 .name = "audio-bus",
@@ -510,11 +388,9 @@ static struct clksrc_clk clksrcs[] = {
510 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, 388 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
511 .enable = s3c64xx_sclk_ctrl, 389 .enable = s3c64xx_sclk_ctrl,
512 }, 390 },
513 .shift = S3C6400_CLKSRC_AUDIO1_SHIFT, 391 .reg_src = { S3C_CLK_SRC, 10, 3 },
514 .mask = S3C6400_CLKSRC_AUDIO1_MASK, 392 .reg_div = { S3C_CLK_DIV2, 12, 4 },
515 .sources = &clkset_audio1, 393 .sources = &clkset_audio1,
516 .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT,
517 .reg_divider = S3C_CLK_DIV2,
518 }, { 394 }, {
519 .clk = { 395 .clk = {
520 .name = "irda-bus", 396 .name = "irda-bus",
@@ -522,11 +398,9 @@ static struct clksrc_clk clksrcs[] = {
522 .ctrlbit = S3C_CLKCON_SCLK_IRDA, 398 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
523 .enable = s3c64xx_sclk_ctrl, 399 .enable = s3c64xx_sclk_ctrl,
524 }, 400 },
525 .shift = S3C6400_CLKSRC_IRDA_SHIFT, 401 .reg_src = { S3C_CLK_SRC, 24, 2 },
526 .mask = S3C6400_CLKSRC_IRDA_MASK, 402 .reg_div = { S3C_CLK_DIV2, 20, 4 },
527 .sources = &clkset_irda, 403 .sources = &clkset_irda,
528 .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT,
529 .reg_divider = S3C_CLK_DIV2,
530 }, { 404 }, {
531 .clk = { 405 .clk = {
532 .name = "camera", 406 .name = "camera",
@@ -534,11 +408,9 @@ static struct clksrc_clk clksrcs[] = {
534 .ctrlbit = S3C_CLKCON_SCLK_CAM, 408 .ctrlbit = S3C_CLKCON_SCLK_CAM,
535 .enable = s3c64xx_sclk_ctrl, 409 .enable = s3c64xx_sclk_ctrl,
536 }, 410 },
537 .shift = 0, 411 .reg_div = { S3C_CLK_DIV0, 20, 4 },
538 .mask = 0, 412 .reg_src = { NULL, 0, 0 },
539 .sources = &clkset_camif, 413 .sources = &clkset_camif,
540 .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT,
541 .reg_divider = S3C_CLK_DIV0,
542 }, 414 },
543}; 415};
544 416
@@ -550,27 +422,6 @@ static struct clksrc_clk *init_parents[] = {
550 &clk_mout_mpll, 422 &clk_mout_mpll,
551}; 423};
552 424
553static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk)
554{
555 struct clk_sources *srcs = clk->sources;
556 u32 clksrc = __raw_readl(S3C_CLK_SRC);
557
558 clksrc &= clk->mask;
559 clksrc >>= clk->shift;
560
561 if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
562 printk(KERN_ERR "%s: bad source %d\n",
563 clk->clk.name, clksrc);
564 return;
565 }
566
567 clk->clk.parent = srcs->sources[clksrc];
568
569 printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
570 clk->clk.name, clk->clk.parent->name, clksrc,
571 clk_get_rate(&clk->clk));
572}
573
574#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 425#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
575 426
576void __init_or_cpufreq s3c6400_setup_clocks(void) 427void __init_or_cpufreq s3c6400_setup_clocks(void)
@@ -629,10 +480,10 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
629 clk_f.rate = fclk; 480 clk_f.rate = fclk;
630 481
631 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) 482 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
632 s3c6400_set_clksrc(init_parents[ptr]); 483 s3c_set_clksrc(init_parents[ptr]);
633 484
634 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) 485 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
635 s3c6400_set_clksrc(&clksrcs[ptr]); 486 s3c_set_clksrc(&clksrcs[ptr]);
636} 487}
637 488
638static struct clk *clks[] __initdata = { 489static struct clk *clks[] __initdata = {
@@ -675,19 +526,5 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit)
675 } 526 }
676 } 527 }
677 528
678 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) { 529 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
679 clkp = &clksrcs[ptr].clk;
680
681 /* all clksrc clocks have these */
682 clkp->get_rate = s3c64xx_getrate_clksrc;
683 clkp->set_rate = s3c64xx_setrate_clksrc;
684 clkp->set_parent = s3c64xx_setparent_clksrc;
685 clkp->round_rate = s3c64xx_roundrate_clksrc;
686
687 ret = s3c24xx_register_clock(clkp);
688 if (ret < 0) {
689 printk(KERN_ERR "Failed to register clock %s (%d)\n",
690 clkp->name, ret);
691 }
692 }
693} 530}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 19:31:47 -0500