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-rw-r--r--drivers/char/drm/r300_cmdbuf.c24
-rw-r--r--drivers/char/drm/r300_reg.h224
2 files changed, 189 insertions, 59 deletions
diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c
index 329733a48b64..702df45320f7 100644
--- a/drivers/char/drm/r300_cmdbuf.c
+++ b/drivers/char/drm/r300_cmdbuf.c
@@ -190,7 +190,7 @@ void r300_init_reg_flags(struct drm_device *dev)
190 ADD_RANGE(0x42C0, 2); 190 ADD_RANGE(0x42C0, 2);
191 ADD_RANGE(R300_RS_CNTL_0, 2); 191 ADD_RANGE(R300_RS_CNTL_0, 2);
192 192
193 ADD_RANGE(0x43A4, 2); 193 ADD_RANGE(R300_SC_HYPERZ, 2);
194 ADD_RANGE(0x43E8, 1); 194 ADD_RANGE(0x43E8, 1);
195 195
196 ADD_RANGE(0x46A4, 5); 196 ADD_RANGE(0x46A4, 5);
@@ -209,14 +209,12 @@ void r300_init_reg_flags(struct drm_device *dev)
209 ADD_RANGE(0x4E50, 9); 209 ADD_RANGE(0x4E50, 9);
210 ADD_RANGE(0x4E88, 1); 210 ADD_RANGE(0x4E88, 1);
211 ADD_RANGE(0x4EA0, 2); 211 ADD_RANGE(0x4EA0, 2);
212 ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3); 212 ADD_RANGE(R300_ZB_CNTL, 3);
213 ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4); 213 ADD_RANGE(R300_ZB_FORMAT, 4);
214 ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ 214 ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
215 ADD_RANGE(R300_RB3D_DEPTHPITCH, 1); 215 ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
216 ADD_RANGE(0x4F28, 1); 216 ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
217 ADD_RANGE(0x4F30, 2); 217 ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
218 ADD_RANGE(0x4F44, 1);
219 ADD_RANGE(0x4F54, 1);
220 218
221 ADD_RANGE(R300_TX_FILTER_0, 16); 219 ADD_RANGE(R300_TX_FILTER_0, 16);
222 ADD_RANGE(R300_TX_FILTER1_0, 16); 220 ADD_RANGE(R300_TX_FILTER1_0, 16);
@@ -229,7 +227,7 @@ void r300_init_reg_flags(struct drm_device *dev)
229 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); 227 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
230 228
231 /* Sporadic registers used as primitives are emitted */ 229 /* Sporadic registers used as primitives are emitted */
232 ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1); 230 ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
233 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1); 231 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
234 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8); 232 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
235 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8); 233 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
@@ -243,6 +241,7 @@ void r300_init_reg_flags(struct drm_device *dev)
243 ADD_RANGE(R500_RS_INST_0, 16); 241 ADD_RANGE(R500_RS_INST_0, 16);
244 ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2); 242 ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
245 ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2); 243 ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
244 ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
246 } else { 245 } else {
247 ADD_RANGE(R300_PFS_CNTL_0, 3); 246 ADD_RANGE(R300_PFS_CNTL_0, 3);
248 ADD_RANGE(R300_PFS_NODE_0, 4); 247 ADD_RANGE(R300_PFS_NODE_0, 4);
@@ -719,8 +718,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
719 BEGIN_RING(6); 718 BEGIN_RING(6);
720 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 719 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
721 OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A); 720 OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
722 OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 721 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
723 OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03); 722 OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE|
723 R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
724 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0)); 724 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
725 OUT_RING(0x0); 725 OUT_RING(0x0);
726 ADVANCE_RING(); 726 ADVANCE_RING();
diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h
index a883d10c40b1..a6802f26afc4 100644
--- a/drivers/char/drm/r300_reg.h
+++ b/drivers/char/drm/r300_reg.h
@@ -702,6 +702,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
702# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) 702# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11)
703/* END: Rasterization / Interpolators - many guesses */ 703/* END: Rasterization / Interpolators - many guesses */
704 704
705/* Hierarchical Z Enable */
706#define R300_SC_HYPERZ 0x43a4
707# define R300_SC_HYPERZ_DISABLE (0 << 0)
708# define R300_SC_HYPERZ_ENABLE (1 << 0)
709# define R300_SC_HYPERZ_MIN (0 << 1)
710# define R300_SC_HYPERZ_MAX (1 << 1)
711# define R300_SC_HYPERZ_ADJ_256 (0 << 2)
712# define R300_SC_HYPERZ_ADJ_128 (1 << 2)
713# define R300_SC_HYPERZ_ADJ_64 (2 << 2)
714# define R300_SC_HYPERZ_ADJ_32 (3 << 2)
715# define R300_SC_HYPERZ_ADJ_16 (4 << 2)
716# define R300_SC_HYPERZ_ADJ_8 (5 << 2)
717# define R300_SC_HYPERZ_ADJ_4 (6 << 2)
718# define R300_SC_HYPERZ_ADJ_2 (7 << 2)
719# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)
720# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)
721# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)
722# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)
723
724#define R300_SC_EDGERULE 0x43a8
725
705/* BEGIN: Scissors and cliprects */ 726/* BEGIN: Scissors and cliprects */
706 727
707/* There are four clipping rectangles. Their corner coordinates are inclusive. 728/* There are four clipping rectangles. Their corner coordinates are inclusive.
@@ -1355,19 +1376,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1355 * for this. 1376 * for this.
1356 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd 1377 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
1357 */ 1378 */
1358#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00 1379#define R300_ZB_CNTL 0x4F00
1359# define R300_RB3D_Z_DISABLED_1 0x00000010 1380# define R300_STENCIL_ENABLE (1 << 0)
1360# define R300_RB3D_Z_DISABLED_2 0x00000014 1381# define R300_Z_ENABLE (1 << 1)
1361# define R300_RB3D_Z_TEST 0x00000012 1382# define R300_Z_WRITE_ENABLE (1 << 2)
1362# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 1383# define R300_Z_SIGNED_COMPARE (1 << 3)
1363# define R300_RB3D_Z_WRITE_ONLY 0x00000006 1384# define R300_STENCIL_FRONT_BACK (1 << 4)
1364 1385
1365# define R300_RB3D_Z_TEST 0x00000012 1386#define R300_ZB_ZSTENCILCNTL 0x4f04
1366# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
1367# define R300_RB3D_Z_WRITE_ONLY 0x00000006
1368# define R300_RB3D_STENCIL_ENABLE 0x00000001
1369
1370#define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04
1371 /* functions */ 1387 /* functions */
1372# define R300_ZS_NEVER 0 1388# define R300_ZS_NEVER 0
1373# define R300_ZS_LESS 1 1389# define R300_ZS_LESS 1
@@ -1387,52 +1403,166 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
1387# define R300_ZS_INVERT 5 1403# define R300_ZS_INVERT 5
1388# define R300_ZS_INCR_WRAP 6 1404# define R300_ZS_INCR_WRAP 6
1389# define R300_ZS_DECR_WRAP 7 1405# define R300_ZS_DECR_WRAP 7
1406# define R300_Z_FUNC_SHIFT 0
1390 /* front and back refer to operations done for front 1407 /* front and back refer to operations done for front
1391 and back faces, i.e. separate stencil function support */ 1408 and back faces, i.e. separate stencil function support */
1392# define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0 1409# define R300_S_FRONT_FUNC_SHIFT 3
1393# define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3 1410# define R300_S_FRONT_SFAIL_OP_SHIFT 6
1394# define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6 1411# define R300_S_FRONT_ZPASS_OP_SHIFT 9
1395# define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9 1412# define R300_S_FRONT_ZFAIL_OP_SHIFT 12
1396# define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12 1413# define R300_S_BACK_FUNC_SHIFT 15
1397# define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15 1414# define R300_S_BACK_SFAIL_OP_SHIFT 18
1398# define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18 1415# define R300_S_BACK_ZPASS_OP_SHIFT 21
1399# define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21 1416# define R300_S_BACK_ZFAIL_OP_SHIFT 24
1400# define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24 1417
1401 1418#define R300_ZB_STENCILREFMASK 0x4f08
1402#define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08 1419# define R300_STENCILREF_SHIFT 0
1403# define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0 1420# define R300_STENCILREF_MASK 0x000000ff
1404# define R300_RB3D_ZS2_STENCIL_MASK 0xFF 1421# define R300_STENCILMASK_SHIFT 8
1405# define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8 1422# define R300_STENCILMASK_MASK 0x0000ff00
1406# define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16 1423# define R300_STENCILWRITEMASK_SHIFT 16
1424# define R300_STENCILWRITEMASK_MASK 0x00ff0000
1407 1425
1408/* gap */ 1426/* gap */
1409 1427
1410#define R300_RB3D_ZSTENCIL_FORMAT 0x4F10 1428#define R300_ZB_FORMAT 0x4f10
1411# define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1429# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
1412# define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1430# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
1413 /* 16 bit format or some aditional bit ? */ 1431# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
1414# define R300_DEPTH_FORMAT_UNK32 (32 << 0) 1432/* reserved up to (15 << 0) */
1433# define R300_INVERT_13E3_LEADING_ONES (0 << 4)
1434# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
1415 1435
1416#define R300_RB3D_EARLY_Z 0x4F14 1436#define R300_ZB_ZTOP 0x4F14
1417# define R300_EARLY_Z_DISABLE (0 << 0) 1437# define R300_ZTOP_DISABLE (0 << 0)
1418# define R300_EARLY_Z_ENABLE (1 << 0) 1438# define R300_ZTOP_ENABLE (1 << 0)
1419 1439
1420/* gap */ 1440/* gap */
1421 1441
1422#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */ 1442#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
1423# define R300_RB3D_ZCACHE_UNKNOWN_01 0x1 1443# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
1424# define R300_RB3D_ZCACHE_UNKNOWN_03 0x3 1444# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
1445# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
1446# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
1447# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
1448# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
1449
1450#define R300_ZB_BW_CNTL 0x4f1c
1451# define R300_HIZ_DISABLE (0 << 0)
1452# define R300_HIZ_ENABLE (1 << 0)
1453# define R300_HIZ_MIN (0 << 1)
1454# define R300_HIZ_MAX (1 << 1)
1455# define R300_FAST_FILL_DISABLE (0 << 2)
1456# define R300_FAST_FILL_ENABLE (1 << 2)
1457# define R300_RD_COMP_DISABLE (0 << 3)
1458# define R300_RD_COMP_ENABLE (1 << 3)
1459# define R300_WR_COMP_DISABLE (0 << 4)
1460# define R300_WR_COMP_ENABLE (1 << 4)
1461# define R300_ZB_CB_CLEAR_RMW (0 << 5)
1462# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
1463# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
1464# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
1465
1466# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
1467# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
1468# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
1469# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
1470
1471# define R500_BMASK_ENABLE (0 << 10)
1472# define R500_BMASK_DISABLE (1 << 10)
1473# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
1474# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
1475# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
1476# define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
1477# define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
1478# define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
1479# define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
1480# define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
1481# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
1482# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
1483# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
1484# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
1485# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
1486# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
1487# define R500_PEQ_PACKING_DISABLE (0 << 18)
1488# define R500_PEQ_PACKING_ENABLE (1 << 18)
1489# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
1490# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
1491
1425 1492
1426/* gap */ 1493/* gap */
1427 1494
1428#define R300_RB3D_DEPTHOFFSET 0x4F20 1495/* Z Buffer Address Offset.
1429#define R300_RB3D_DEPTHPITCH 0x4F24 1496 * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
1430# define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ 1497 */
1431# define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ 1498#define R300_ZB_DEPTHOFFSET 0x4f20
1432# define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */ 1499
1433# define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ 1500/* Z Buffer Pitch and Endian Control */
1434# define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ 1501#define R300_ZB_DEPTHPITCH 0x4f24
1435# define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ 1502# define R300_DEPTHPITCH_MASK 0x00003FFC
1503# define R300_DEPTHMACROTILE_DISABLE (0 << 16)
1504# define R300_DEPTHMACROTILE_ENABLE (1 << 16)
1505# define R300_DEPTHMICROTILE_LINEAR (0 << 17)
1506# define R300_DEPTHMICROTILE_TILED (1 << 17)
1507# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
1508# define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
1509# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
1510# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
1511# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
1512
1513/* Z Buffer Clear Value */
1514#define R300_ZB_DEPTHCLEARVALUE 0x4f28
1515
1516#define R300_ZB_ZMASK_OFFSET 0x4f30
1517#define R300_ZB_ZMASK_PITCH 0x4f34
1518#define R300_ZB_ZMASK_WRINDEX 0x4f38
1519#define R300_ZB_ZMASK_DWORD 0x4f3c
1520#define R300_ZB_ZMASK_RDINDEX 0x4f40
1521
1522/* Hierarchical Z Memory Offset */
1523#define R300_ZB_HIZ_OFFSET 0x4f44
1524
1525/* Hierarchical Z Write Index */
1526#define R300_ZB_HIZ_WRINDEX 0x4f48
1527
1528/* Hierarchical Z Data */
1529#define R300_ZB_HIZ_DWORD 0x4f4c
1530
1531/* Hierarchical Z Read Index */
1532#define R300_ZB_HIZ_RDINDEX 0x4f50
1533
1534/* Hierarchical Z Pitch */
1535#define R300_ZB_HIZ_PITCH 0x4f54
1536
1537/* Z Buffer Z Pass Counter Data */
1538#define R300_ZB_ZPASS_DATA 0x4f58
1539
1540/* Z Buffer Z Pass Counter Address */
1541#define R300_ZB_ZPASS_ADDR 0x4f5c
1542
1543/* Depth buffer X and Y coordinate offset */
1544#define R300_ZB_DEPTHXY_OFFSET 0x4f60
1545# define R300_DEPTHX_OFFSET_SHIFT 1
1546# define R300_DEPTHX_OFFSET_MASK 0x000007FE
1547# define R300_DEPTHY_OFFSET_SHIFT 17
1548# define R300_DEPTHY_OFFSET_MASK 0x07FE0000
1549
1550/* Sets the fifo sizes */
1551#define R500_ZB_FIFO_SIZE 0x4fd0
1552# define R500_OP_FIFO_SIZE_FULL (0 << 0)
1553# define R500_OP_FIFO_SIZE_HALF (1 << 0)
1554# define R500_OP_FIFO_SIZE_QUATER (2 << 0)
1555# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
1556
1557/* Stencil Reference Value and Mask for backfacing quads */
1558/* R300_ZB_STENCILREFMASK handles front face */
1559#define R500_ZB_STENCILREFMASK_BF 0x4fd4
1560# define R500_STENCILREF_SHIFT 0
1561# define R500_STENCILREF_MASK 0x000000ff
1562# define R500_STENCILMASK_SHIFT 8
1563# define R500_STENCILMASK_MASK 0x0000ff00
1564# define R500_STENCILWRITEMASK_SHIFT 16
1565# define R500_STENCILWRITEMASK_MASK 0x00ff0000
1436 1566
1437/* BEGIN: Vertex program instruction set */ 1567/* BEGIN: Vertex program instruction set */
1438 1568