diff options
-rw-r--r-- | drivers/pci/intr_remapping.c | 15 | ||||
-rw-r--r-- | include/linux/intel-iommu.h | 2 |
2 files changed, 17 insertions, 0 deletions
diff --git a/drivers/pci/intr_remapping.c b/drivers/pci/intr_remapping.c index c26633d7e7da..ef25caade54b 100644 --- a/drivers/pci/intr_remapping.c +++ b/drivers/pci/intr_remapping.c | |||
@@ -415,12 +415,27 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) | |||
415 | 415 | ||
416 | /* Set interrupt-remapping table pointer */ | 416 | /* Set interrupt-remapping table pointer */ |
417 | cmd = iommu->gcmd | DMA_GCMD_SIRTP; | 417 | cmd = iommu->gcmd | DMA_GCMD_SIRTP; |
418 | iommu->gcmd |= DMA_GCMD_SIRTP; | ||
418 | writel(cmd, iommu->reg + DMAR_GCMD_REG); | 419 | writel(cmd, iommu->reg + DMAR_GCMD_REG); |
419 | 420 | ||
420 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | 421 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
421 | readl, (sts & DMA_GSTS_IRTPS), sts); | 422 | readl, (sts & DMA_GSTS_IRTPS), sts); |
422 | spin_unlock_irqrestore(&iommu->register_lock, flags); | 423 | spin_unlock_irqrestore(&iommu->register_lock, flags); |
423 | 424 | ||
425 | if (mode == 0) { | ||
426 | spin_lock_irqsave(&iommu->register_lock, flags); | ||
427 | |||
428 | /* enable comaptiblity format interrupt pass through */ | ||
429 | cmd = iommu->gcmd | DMA_GCMD_CFI; | ||
430 | iommu->gcmd |= DMA_GCMD_CFI; | ||
431 | writel(cmd, iommu->reg + DMAR_GCMD_REG); | ||
432 | |||
433 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | ||
434 | readl, (sts & DMA_GSTS_CFIS), sts); | ||
435 | |||
436 | spin_unlock_irqrestore(&iommu->register_lock, flags); | ||
437 | } | ||
438 | |||
424 | /* | 439 | /* |
425 | * global invalidation of interrupt entry cache before enabling | 440 | * global invalidation of interrupt entry cache before enabling |
426 | * interrupt-remapping. | 441 | * interrupt-remapping. |
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index 3771cd1f876e..aa8c53171233 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h | |||
@@ -164,6 +164,7 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) | |||
164 | #define DMA_GCMD_QIE (((u32)1) << 26) | 164 | #define DMA_GCMD_QIE (((u32)1) << 26) |
165 | #define DMA_GCMD_SIRTP (((u32)1) << 24) | 165 | #define DMA_GCMD_SIRTP (((u32)1) << 24) |
166 | #define DMA_GCMD_IRE (((u32) 1) << 25) | 166 | #define DMA_GCMD_IRE (((u32) 1) << 25) |
167 | #define DMA_GCMD_CFI (((u32) 1) << 23) | ||
167 | 168 | ||
168 | /* GSTS_REG */ | 169 | /* GSTS_REG */ |
169 | #define DMA_GSTS_TES (((u32)1) << 31) | 170 | #define DMA_GSTS_TES (((u32)1) << 31) |
@@ -174,6 +175,7 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) | |||
174 | #define DMA_GSTS_QIES (((u32)1) << 26) | 175 | #define DMA_GSTS_QIES (((u32)1) << 26) |
175 | #define DMA_GSTS_IRTPS (((u32)1) << 24) | 176 | #define DMA_GSTS_IRTPS (((u32)1) << 24) |
176 | #define DMA_GSTS_IRES (((u32)1) << 25) | 177 | #define DMA_GSTS_IRES (((u32)1) << 25) |
178 | #define DMA_GSTS_CFIS (((u32)1) << 23) | ||
177 | 179 | ||
178 | /* CCMD_REG */ | 180 | /* CCMD_REG */ |
179 | #define DMA_CCMD_ICC (((u64)1) << 63) | 181 | #define DMA_CCMD_ICC (((u64)1) << 63) |