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-rw-r--r--arch/mips/Kconfig19
-rw-r--r--arch/mips/Makefile7
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-tx4938.c92
-rw-r--r--arch/mips/pci/ops-tx4938.c198
-rw-r--r--arch/mips/tx4938/Kconfig24
-rw-r--r--arch/mips/tx4938/common/Makefile11
-rw-r--r--arch/mips/tx4938/common/dbgio.c50
-rw-r--r--arch/mips/tx4938/common/irq.c424
-rw-r--r--arch/mips/tx4938/common/irq_handler.S84
-rw-r--r--arch/mips/tx4938/common/prom.c129
-rw-r--r--arch/mips/tx4938/common/rtc_rx5c348.c202
-rw-r--r--arch/mips/tx4938/common/setup.c91
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/Makefile9
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/irq.c244
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/prom.c78
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/setup.c1035
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c219
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c159
-rw-r--r--include/asm-mips/bootinfo.h1
-rw-r--r--include/asm-mips/tx4938/rbtx4938.h207
-rw-r--r--include/asm-mips/tx4938/spi.h74
-rw-r--r--include/asm-mips/tx4938/tx4938.h706
-rw-r--r--include/asm-mips/tx4938/tx4938_mips.h54
24 files changed, 4118 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 338c21f3efd3..1f53fe8a89f1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -695,6 +695,24 @@ config SOC_AU1500
695config SOC_AU1550 695config SOC_AU1550
696 bool "SOC_AU1550" 696 bool "SOC_AU1550"
697 697
698config TOSHIBA_RBTX4938
699 bool "Support for Toshiba RBTX4938 board"
700 select HAVE_STD_PC_SERIAL_PORT
701 select DMA_NONCOHERENT
702 select GENERIC_ISA_DMA
703 select HAS_TXX9_SERIAL
704 select HW_HAS_PCI
705 select I8259
706 select ISA
707 select SWAP_IO_SPACE
708 select SYS_SUPPORTS_32BIT_KERNEL
709 select SYS_SUPPORTS_LITTLE_ENDIAN
710 select SYS_SUPPORTS_BIG_ENDIAN
711 select TOSHIBA_BOARDS
712 help
713 This Toshiba board is based on the TX4938 processor. Say Y here to
714 support this machine type
715
698endchoice 716endchoice
699 717
700choice 718choice
@@ -837,6 +855,7 @@ config TOSHIBA_FPCIB0
837 855
838source "arch/mips/sgi-ip27/Kconfig" 856source "arch/mips/sgi-ip27/Kconfig"
839source "arch/mips/sibyte/Kconfig" 857source "arch/mips/sibyte/Kconfig"
858source "arch/mips/tx4938/Kconfig"
840source "arch/mips/philips/pnx8550/common/Kconfig" 859source "arch/mips/philips/pnx8550/common/Kconfig"
841 860
842config RWSEM_GENERIC_SPINLOCK 861config RWSEM_GENERIC_SPINLOCK
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 9c91e70d8ee2..3dc2fb81fb28 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -690,6 +690,13 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/toshiba_rbtx4927/
690core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/ 690core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/tx4927/common/
691load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000 691load-$(CONFIG_TOSHIBA_RBTX4927) += 0xffffffff80020000
692 692
693#
694# Toshiba RBTX4938 board
695#
696core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/toshiba_rbtx4938/
697core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/tx4938/common/
698load-$(CONFIG_TOSHIBA_RBTX4938) += 0xffffffff80100000
699
693cflags-y += -Iinclude/asm-mips/mach-generic 700cflags-y += -Iinclude/asm-mips/mach-generic
694drivers-$(CONFIG_PCI) += arch/mips/pci/ 701drivers-$(CONFIG_PCI) += arch/mips/pci/
695 702
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index ea8438b81fed..6956de95a7e8 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -52,5 +52,6 @@ obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
52obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o 52obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
53obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o 53obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o
54obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o 54obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o
55obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
55obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 56obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
56obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 57obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c
new file mode 100644
index 000000000000..f455520ada88
--- /dev/null
+++ b/arch/mips/pci/fixup-tx4938.c
@@ -0,0 +1,92 @@
1/*
2 * Toshiba rbtx4938 pci routines
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16
17#include <asm/tx4938/rbtx4938.h>
18
19extern struct pci_controller tx4938_pci_controller[];
20
21int pci_get_irq(struct pci_dev *dev, int pin)
22{
23 int irq = pin;
24 u8 slot = PCI_SLOT(dev->devfn);
25 struct pci_controller *controller = (struct pci_controller *)dev->sysdata;
26
27 if (controller == &tx4938_pci_controller[1]) {
28 /* TX4938 PCIC1 */
29 switch (slot) {
30 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
31 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL)
32 return RBTX4938_IRQ_IRC + TX4938_IR_ETH0;
33 break;
34 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
35 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL)
36 return RBTX4938_IRQ_IRC + TX4938_IR_ETH1;
37 break;
38 }
39 return 0;
40 }
41
42 /* IRQ rotation */
43 irq--; /* 0-3 */
44 if (dev->bus->parent == NULL &&
45 (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) {
46 /* PCI CardSlot (IDSEL=A23) */
47 /* PCIA => PCIA (IDSEL=A23) */
48 irq = (irq + 0 + slot) % 4;
49 } else {
50 /* PCI Backplane */
51 irq = (irq + 33 - slot) % 4;
52 }
53 irq++; /* 1-4 */
54
55 switch (irq) {
56 case 1:
57 irq = RBTX4938_IRQ_IOC_PCIA;
58 break;
59 case 2:
60 irq = RBTX4938_IRQ_IOC_PCIB;
61 break;
62 case 3:
63 irq = RBTX4938_IRQ_IOC_PCIC;
64 break;
65 case 4:
66 irq = RBTX4938_IRQ_IOC_PCID;
67 break;
68 }
69 return irq;
70}
71
72int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
73{
74 unsigned char irq = 0;
75
76 irq = pci_get_irq(dev, pin);
77
78 printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n",
79 dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn),
80 PCI_FUNC(dev->devfn), irq);
81
82 return irq;
83}
84
85/*
86 * Do platform specific device initialization at pci_enable_device() time
87 */
88int pcibios_plat_dev_init(struct pci_dev *dev)
89{
90 return 0;
91}
92
diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c
new file mode 100644
index 000000000000..4c0dcfce5297
--- /dev/null
+++ b/arch/mips/pci/ops-tx4938.c
@@ -0,0 +1,198 @@
1/*
2 * Define the pci_ops for the Toshiba rbtx4938
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16
17#include <asm/addrspace.h>
18#include <asm/tx4938/rbtx4938.h>
19
20/* initialize in setup */
21struct resource pci_io_resource = {
22 .name = "pci IO space",
23 .start = 0,
24 .end = 0,
25 .flags = IORESOURCE_IO
26};
27
28/* initialize in setup */
29struct resource pci_mem_resource = {
30 .name = "pci memory space",
31 .start = 0,
32 .end = 0,
33 .flags = IORESOURCE_MEM
34};
35
36struct resource tx4938_pcic1_pci_io_resource = {
37 .name = "PCI1 IO",
38 .start = 0,
39 .end = 0,
40 .flags = IORESOURCE_IO
41};
42struct resource tx4938_pcic1_pci_mem_resource = {
43 .name = "PCI1 mem",
44 .start = 0,
45 .end = 0,
46 .flags = IORESOURCE_MEM
47};
48
49static int mkaddr(int bus, int dev_fn, int where, int *flagsp)
50{
51 if (bus > 0) {
52 /* Type 1 configuration */
53 tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
54 ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
55 } else {
56 if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0))
57 return -1;
58
59 /* Type 0 configuration */
60 tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
61 ((dev_fn & 0xff) << 0x08) | (where & 0xfc);
62 }
63 /* clear M_ABORT and Disable M_ABORT Int. */
64 tx4938_pcicptr->pcistatus =
65 (tx4938_pcicptr->pcistatus & 0x0000ffff) |
66 (PCI_STATUS_REC_MASTER_ABORT << 16);
67 tx4938_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
68
69 return 0;
70}
71
72static int check_abort(int flags)
73{
74 int code = PCIBIOS_SUCCESSFUL;
75 /* wait write cycle completion before checking error status */
76 while (tx4938_pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB)
77 ;
78 if (tx4938_pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
79 tx4938_pcicptr->pcistatus =
80 (tx4938_pcicptr->
81 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
82 << 16);
83 tx4938_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
84 code = PCIBIOS_DEVICE_NOT_FOUND;
85 }
86 return code;
87}
88
89static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
90 int where, int size, u32 * val)
91{
92 int flags, retval, dev, busno, func;
93
94 dev = PCI_SLOT(devfn);
95 func = PCI_FUNC(devfn);
96
97 /* check if the bus is top-level */
98 if (bus->parent != NULL)
99 busno = bus->number;
100 else {
101 busno = 0;
102 }
103
104 if (mkaddr(busno, devfn, where, &flags))
105 return -1;
106
107 switch (size) {
108 case 1:
109 *val = *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
110#ifdef __BIG_ENDIAN
111 ((where & 3) ^ 3));
112#else
113 (where & 3));
114#endif
115 break;
116 case 2:
117 *val = *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
118#ifdef __BIG_ENDIAN
119 ((where & 3) ^ 2));
120#else
121 (where & 3));
122#endif
123 break;
124 case 4:
125 *val = tx4938_pcicptr->g2pcfgdata;
126 break;
127 }
128
129 retval = check_abort(flags);
130 if (retval == PCIBIOS_DEVICE_NOT_FOUND)
131 *val = 0xffffffff;
132
133 return retval;
134}
135
136static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where,
137 int size, u32 val)
138{
139 int flags, dev, busno, func;
140
141 busno = bus->number;
142 dev = PCI_SLOT(devfn);
143 func = PCI_FUNC(devfn);
144
145 /* check if the bus is top-level */
146 if (bus->parent != NULL) {
147 busno = bus->number;
148 } else {
149 busno = 0;
150 }
151
152 if (mkaddr(busno, devfn, where, &flags))
153 return -1;
154
155 switch (size) {
156 case 1:
157 *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
158#ifdef __BIG_ENDIAN
159 ((where & 3) ^ 3)) = val;
160#else
161 (where & 3)) = val;
162#endif
163 break;
164 case 2:
165 *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata |
166#ifdef __BIG_ENDIAN
167 ((where & 0x3) ^ 0x2)) = val;
168#else
169 (where & 3)) = val;
170#endif
171 break;
172 case 4:
173 tx4938_pcicptr->g2pcfgdata = val;
174 break;
175 }
176
177 return check_abort(flags);
178}
179
180struct pci_ops tx4938_pci_ops = {
181 tx4938_pcibios_read_config,
182 tx4938_pcibios_write_config
183};
184
185struct pci_controller tx4938_pci_controller[] = {
186 /* h/w only supports devices 0x00 to 0x14 */
187 {
188 .pci_ops = &tx4938_pci_ops,
189 .io_resource = &pci_io_resource,
190 .mem_resource = &pci_mem_resource,
191 },
192 /* h/w only supports devices 0x00 to 0x14 */
193 {
194 .pci_ops = &tx4938_pci_ops,
195 .io_resource = &tx4938_pcic1_pci_io_resource,
196 .mem_resource = &tx4938_pcic1_pci_mem_resource,
197 }
198};
diff --git a/arch/mips/tx4938/Kconfig b/arch/mips/tx4938/Kconfig
new file mode 100644
index 000000000000..d90e9cd85138
--- /dev/null
+++ b/arch/mips/tx4938/Kconfig
@@ -0,0 +1,24 @@
1if TOSHIBA_RBTX4938
2
3comment "Multiplex Pin Select"
4choice
5 prompt "PIO[58:61]"
6 default TOSHIBA_RBTX4938_MPLEX_PIO58_61
7
8config TOSHIBA_RBTX4938_MPLEX_PIO58_61
9 bool "PIO"
10config TOSHIBA_RBTX4938_MPLEX_NAND
11 bool "NAND"
12config TOSHIBA_RBTX4938_MPLEX_ATA
13 bool "ATA"
14
15endchoice
16
17config TX4938_NAND_BOOT
18 depends on EXPERIMENTAL && TOSHIBA_RBTX4938_MPLEX_NAND
19 bool "NAND Boot Support (EXPERIMENTAL)"
20 help
21 This is only for Toshiba RBTX4938 reference board, which has NAND IPL.
22 Select this option if you need to use NAND boot.
23
24endif
diff --git a/arch/mips/tx4938/common/Makefile b/arch/mips/tx4938/common/Makefile
new file mode 100644
index 000000000000..74c95c5bcdbf
--- /dev/null
+++ b/arch/mips/tx4938/common/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for common code for Toshiba TX4927 based systems
3#
4# Note! Dependencies are done automagically by 'make dep', which also
5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file).
7#
8
9obj-y += prom.o setup.o irq.o irq_handler.o rtc_rx5c348.o
10obj-$(CONFIG_KGDB) += dbgio.o
11
diff --git a/arch/mips/tx4938/common/dbgio.c b/arch/mips/tx4938/common/dbgio.c
new file mode 100644
index 000000000000..bea59ff1842a
--- /dev/null
+++ b/arch/mips/tx4938/common/dbgio.c
@@ -0,0 +1,50 @@
1/*
2 * linux/arch/mips/tx4938/common/dbgio.c
3 *
4 * kgdb interface for gdb
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * Copyright 2005 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
24 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
25 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 * Support for TX4938 in 2.6 - Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp>
32 */
33
34#include <asm/mipsregs.h>
35#include <asm/system.h>
36#include <asm/tx4938/tx4938_mips.h>
37
38extern u8 txx9_sio_kdbg_rd(void);
39extern int txx9_sio_kdbg_wr( u8 ch );
40
41u8 getDebugChar(void)
42{
43 return (txx9_sio_kdbg_rd());
44}
45
46int putDebugChar(u8 byte)
47{
48 return (txx9_sio_kdbg_wr(byte));
49}
50
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c
new file mode 100644
index 000000000000..4f90d7faf634
--- /dev/null
+++ b/arch/mips/tx4938/common/irq.c
@@ -0,0 +1,424 @@
1/*
2 * linux/arch/mps/tx4938/common/irq.c
3 *
4 * Common tx4938 irq handler
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14#include <linux/errno.h>
15#include <linux/init.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/signal.h>
19#include <linux/sched.h>
20#include <linux/types.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/timex.h>
24#include <linux/slab.h>
25#include <linux/random.h>
26#include <linux/irq.h>
27#include <asm/bitops.h>
28#include <asm/bootinfo.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/mipsregs.h>
32#include <asm/system.h>
33#include <asm/tx4938/rbtx4938.h>
34
35/**********************************************************************************/
36/* Forwad definitions for all pic's */
37/**********************************************************************************/
38
39static unsigned int tx4938_irq_cp0_startup(unsigned int irq);
40static void tx4938_irq_cp0_shutdown(unsigned int irq);
41static void tx4938_irq_cp0_enable(unsigned int irq);
42static void tx4938_irq_cp0_disable(unsigned int irq);
43static void tx4938_irq_cp0_mask_and_ack(unsigned int irq);
44static void tx4938_irq_cp0_end(unsigned int irq);
45
46static unsigned int tx4938_irq_pic_startup(unsigned int irq);
47static void tx4938_irq_pic_shutdown(unsigned int irq);
48static void tx4938_irq_pic_enable(unsigned int irq);
49static void tx4938_irq_pic_disable(unsigned int irq);
50static void tx4938_irq_pic_mask_and_ack(unsigned int irq);
51static void tx4938_irq_pic_end(unsigned int irq);
52
53/**********************************************************************************/
54/* Kernel structs for all pic's */
55/**********************************************************************************/
56DEFINE_SPINLOCK(tx4938_cp0_lock);
57DEFINE_SPINLOCK(tx4938_pic_lock);
58
59#define TX4938_CP0_NAME "TX4938-CP0"
60static struct hw_interrupt_type tx4938_irq_cp0_type = {
61 .typename = TX4938_CP0_NAME,
62 .startup = tx4938_irq_cp0_startup,
63 .shutdown = tx4938_irq_cp0_shutdown,
64 .enable = tx4938_irq_cp0_enable,
65 .disable = tx4938_irq_cp0_disable,
66 .ack = tx4938_irq_cp0_mask_and_ack,
67 .end = tx4938_irq_cp0_end,
68 .set_affinity = NULL
69};
70
71#define TX4938_PIC_NAME "TX4938-PIC"
72static struct hw_interrupt_type tx4938_irq_pic_type = {
73 .typename = TX4938_PIC_NAME,
74 .startup = tx4938_irq_pic_startup,
75 .shutdown = tx4938_irq_pic_shutdown,
76 .enable = tx4938_irq_pic_enable,
77 .disable = tx4938_irq_pic_disable,
78 .ack = tx4938_irq_pic_mask_and_ack,
79 .end = tx4938_irq_pic_end,
80 .set_affinity = NULL
81};
82
83static struct irqaction tx4938_irq_pic_action = {
84 .handler = no_action,
85 .flags = 0,
86 .mask = CPU_MASK_NONE,
87 .name = TX4938_PIC_NAME
88};
89
90/**********************************************************************************/
91/* Functions for cp0 */
92/**********************************************************************************/
93
94#define tx4938_irq_cp0_mask(irq) ( 1 << ( irq-TX4938_IRQ_CP0_BEG+8 ) )
95
96static void __init
97tx4938_irq_cp0_init(void)
98{
99 int i;
100
101 for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) {
102 irq_desc[i].status = IRQ_DISABLED;
103 irq_desc[i].action = 0;
104 irq_desc[i].depth = 1;
105 irq_desc[i].handler = &tx4938_irq_cp0_type;
106 }
107
108 return;
109}
110
111static unsigned int
112tx4938_irq_cp0_startup(unsigned int irq)
113{
114 tx4938_irq_cp0_enable(irq);
115
116 return (0);
117}
118
119static void
120tx4938_irq_cp0_shutdown(unsigned int irq)
121{
122 tx4938_irq_cp0_disable(irq);
123}
124
125static void
126tx4938_irq_cp0_enable(unsigned int irq)
127{
128 unsigned long flags;
129
130 spin_lock_irqsave(&tx4938_cp0_lock, flags);
131
132 set_c0_status(tx4938_irq_cp0_mask(irq));
133
134 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
135}
136
137static void
138tx4938_irq_cp0_disable(unsigned int irq)
139{
140 unsigned long flags;
141
142 spin_lock_irqsave(&tx4938_cp0_lock, flags);
143
144 clear_c0_status(tx4938_irq_cp0_mask(irq));
145
146 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
147
148 return;
149}
150
151static void
152tx4938_irq_cp0_mask_and_ack(unsigned int irq)
153{
154 tx4938_irq_cp0_disable(irq);
155
156 return;
157}
158
159static void
160tx4938_irq_cp0_end(unsigned int irq)
161{
162 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
163 tx4938_irq_cp0_enable(irq);
164 }
165
166 return;
167}
168
169/**********************************************************************************/
170/* Functions for pic */
171/**********************************************************************************/
172
173u32
174tx4938_irq_pic_addr(int irq)
175{
176 /* MVMCP -- need to formulize this */
177 irq -= TX4938_IRQ_PIC_BEG;
178
179 switch (irq) {
180 case 17:
181 case 16:
182 case 1:
183 case 0:{
184 return (TX4938_MKA(TX4938_IRC_IRLVL0));
185 }
186 case 19:
187 case 18:
188 case 3:
189 case 2:{
190 return (TX4938_MKA(TX4938_IRC_IRLVL1));
191 }
192 case 21:
193 case 20:
194 case 5:
195 case 4:{
196 return (TX4938_MKA(TX4938_IRC_IRLVL2));
197 }
198 case 23:
199 case 22:
200 case 7:
201 case 6:{
202 return (TX4938_MKA(TX4938_IRC_IRLVL3));
203 }
204 case 25:
205 case 24:
206 case 9:
207 case 8:{
208 return (TX4938_MKA(TX4938_IRC_IRLVL4));
209 }
210 case 27:
211 case 26:
212 case 11:
213 case 10:{
214 return (TX4938_MKA(TX4938_IRC_IRLVL5));
215 }
216 case 29:
217 case 28:
218 case 13:
219 case 12:{
220 return (TX4938_MKA(TX4938_IRC_IRLVL6));
221 }
222 case 31:
223 case 30:
224 case 15:
225 case 14:{
226 return (TX4938_MKA(TX4938_IRC_IRLVL7));
227 }
228 }
229
230 return (0);
231}
232
233u32
234tx4938_irq_pic_mask(int irq)
235{
236 /* MVMCP -- need to formulize this */
237 irq -= TX4938_IRQ_PIC_BEG;
238
239 switch (irq) {
240 case 31:
241 case 29:
242 case 27:
243 case 25:
244 case 23:
245 case 21:
246 case 19:
247 case 17:{
248 return (0x07000000);
249 }
250 case 30:
251 case 28:
252 case 26:
253 case 24:
254 case 22:
255 case 20:
256 case 18:
257 case 16:{
258 return (0x00070000);
259 }
260 case 15:
261 case 13:
262 case 11:
263 case 9:
264 case 7:
265 case 5:
266 case 3:
267 case 1:{
268 return (0x00000700);
269 }
270 case 14:
271 case 12:
272 case 10:
273 case 8:
274 case 6:
275 case 4:
276 case 2:
277 case 0:{
278 return (0x00000007);
279 }
280 }
281 return (0x00000000);
282}
283
284static void
285tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
286{
287 unsigned long val = 0;
288
289 val = TX4938_RD(pic_reg);
290 val &= (~clr_bits);
291 val |= (set_bits);
292 TX4938_WR(pic_reg, val);
293 mmiowb();
294 TX4938_RD(pic_reg);
295
296 return;
297}
298
299static void __init
300tx4938_irq_pic_init(void)
301{
302 unsigned long flags;
303 int i;
304
305 for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) {
306 irq_desc[i].status = IRQ_DISABLED;
307 irq_desc[i].action = 0;
308 irq_desc[i].depth = 2;
309 irq_desc[i].handler = &tx4938_irq_pic_type;
310 }
311
312 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
313
314 spin_lock_irqsave(&tx4938_pic_lock, flags);
315
316 TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
317 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */
318
319 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
320
321 return;
322}
323
324static unsigned int
325tx4938_irq_pic_startup(unsigned int irq)
326{
327 tx4938_irq_pic_enable(irq);
328
329 return (0);
330}
331
332static void
333tx4938_irq_pic_shutdown(unsigned int irq)
334{
335 tx4938_irq_pic_disable(irq);
336
337 return;
338}
339
340static void
341tx4938_irq_pic_enable(unsigned int irq)
342{
343 unsigned long flags;
344
345 spin_lock_irqsave(&tx4938_pic_lock, flags);
346
347 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0,
348 tx4938_irq_pic_mask(irq));
349
350 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
351
352 return;
353}
354
355static void
356tx4938_irq_pic_disable(unsigned int irq)
357{
358 unsigned long flags;
359
360 spin_lock_irqsave(&tx4938_pic_lock, flags);
361
362 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq),
363 tx4938_irq_pic_mask(irq), 0);
364
365 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
366
367 return;
368}
369
370static void
371tx4938_irq_pic_mask_and_ack(unsigned int irq)
372{
373 tx4938_irq_pic_disable(irq);
374
375 return;
376}
377
378static void
379tx4938_irq_pic_end(unsigned int irq)
380{
381 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
382 tx4938_irq_pic_enable(irq);
383 }
384
385 return;
386}
387
388/**********************************************************************************/
389/* Main init functions */
390/**********************************************************************************/
391
392void __init
393tx4938_irq_init(void)
394{
395 extern asmlinkage void tx4938_irq_handler(void);
396
397 tx4938_irq_cp0_init();
398 tx4938_irq_pic_init();
399 set_except_vector(0, tx4938_irq_handler);
400
401 return;
402}
403
404int
405tx4938_irq_nested(void)
406{
407 int sw_irq = 0;
408 u32 level2;
409
410 level2 = TX4938_RD(0xff1ff6a0);
411 if ((level2 & 0x10000) == 0) {
412 level2 &= 0x1f;
413 sw_irq = TX4938_IRQ_PIC_BEG + level2;
414 if (sw_irq == 26) {
415 {
416 extern int toshiba_rbtx4938_irq_nested(int sw_irq);
417 sw_irq = toshiba_rbtx4938_irq_nested(sw_irq);
418 }
419 }
420 }
421
422 wbflush();
423 return (sw_irq);
424}
diff --git a/arch/mips/tx4938/common/irq_handler.S b/arch/mips/tx4938/common/irq_handler.S
new file mode 100644
index 000000000000..1b2f72bac42d
--- /dev/null
+++ b/arch/mips/tx4938/common/irq_handler.S
@@ -0,0 +1,84 @@
1/*
2 * linux/arch/mips/tx4938/common/handler.S
3 *
4 * Primary interrupt handler for tx4938 based systems
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14#include <asm/asm.h>
15#include <asm/mipsregs.h>
16#include <asm/addrspace.h>
17#include <asm/regdef.h>
18#include <asm/stackframe.h>
19#include <asm/tx4938/rbtx4938.h>
20
21
22 .align 5
23 NESTED(tx4938_irq_handler, PT_SIZE, sp)
24 SAVE_ALL
25 CLI
26 .set at
27
28 mfc0 t0, CP0_CAUSE
29 mfc0 t1, CP0_STATUS
30 and t0, t1
31
32 andi t1, t0, STATUSF_IP7 /* cpu timer */
33 bnez t1, ll_ip7
34
35 /* IP6..IP3 multiplexed -- do not use */
36
37 andi t1, t0, STATUSF_IP2 /* tx4938 pic */
38 bnez t1, ll_ip2
39
40 andi t1, t0, STATUSF_IP1 /* user line 1 */
41 bnez t1, ll_ip1
42
43 andi t1, t0, STATUSF_IP0 /* user line 0 */
44 bnez t1, ll_ip0
45
46 .set reorder
47
48 nop
49 END(tx4938_irq_handler)
50
51 .align 5
52
53
54ll_ip7:
55 li a0, TX4938_IRQ_CPU_TIMER
56 move a1, sp
57 jal do_IRQ
58 j ret_from_irq
59
60
61ll_ip2:
62 jal tx4938_irq_nested
63 nop
64 beqz v0, goto_spurious_interrupt
65 nop
66 move a0, v0
67 move a1, sp
68 jal do_IRQ
69 j ret_from_irq
70
71goto_spurious_interrupt:
72 j ret_from_irq
73
74ll_ip1:
75 li a0, TX4938_IRQ_USER1
76 move a1, sp
77 jal do_IRQ
78 j ret_from_irq
79
80ll_ip0:
81 li a0, TX4938_IRQ_USER0
82 move a1, sp
83 jal do_IRQ
84 j ret_from_irq
diff --git a/arch/mips/tx4938/common/prom.c b/arch/mips/tx4938/common/prom.c
new file mode 100644
index 000000000000..3189a65f7d7e
--- /dev/null
+++ b/arch/mips/tx4938/common/prom.c
@@ -0,0 +1,129 @@
1/*
2 * linux/arch/mips/tx4938/common/prom.c
3 *
4 * common tx4938 memory interface
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/sched.h>
18#include <linux/bootmem.h>
19
20#include <asm/addrspace.h>
21#include <asm/bootinfo.h>
22#include <asm/tx4938/tx4938.h>
23
24static unsigned int __init
25tx4938_process_sdccr(u64 * addr)
26{
27 u64 val;
28 unsigned int sdccr_ce;
29 unsigned int sdccr_rs;
30 unsigned int sdccr_cs;
31 unsigned int sdccr_mw;
32 unsigned int rs = 0;
33 unsigned int cs = 0;
34 unsigned int mw = 0;
35 unsigned int bc = 4;
36 unsigned int msize = 0;
37
38 val = (*((vu64 *) (addr)));
39
40 /* MVMCP -- need #defs for these bits masks */
41 sdccr_ce = ((val & (1 << 10)) >> 10);
42 sdccr_rs = ((val & (3 << 5)) >> 5);
43 sdccr_cs = ((val & (7 << 2)) >> 2);
44 sdccr_mw = ((val & (1 << 0)) >> 0);
45
46 if (sdccr_ce) {
47 switch (sdccr_rs) {
48 case 0:{
49 rs = 2048;
50 break;
51 }
52 case 1:{
53 rs = 4096;
54 break;
55 }
56 case 2:{
57 rs = 8192;
58 break;
59 }
60 default:{
61 rs = 0;
62 break;
63 }
64 }
65 switch (sdccr_cs) {
66 case 0:{
67 cs = 256;
68 break;
69 }
70 case 1:{
71 cs = 512;
72 break;
73 }
74 case 2:{
75 cs = 1024;
76 break;
77 }
78 case 3:{
79 cs = 2048;
80 break;
81 }
82 case 4:{
83 cs = 4096;
84 break;
85 }
86 default:{
87 cs = 0;
88 break;
89 }
90 }
91 switch (sdccr_mw) {
92 case 0:{
93 mw = 8;
94 break;
95 } /* 8 bytes = 64 bits */
96 case 1:{
97 mw = 4;
98 break;
99 } /* 4 bytes = 32 bits */
100 }
101 }
102
103 /* bytes per chip MB per chip bank count */
104 msize = (((rs * cs * mw) / (1024 * 1024)) * (bc));
105
106 /* MVMCP -- bc hard coded to 4 from table 9.3.1 */
107 /* boad supports bc=2 but no way to detect */
108
109 return (msize);
110}
111
112unsigned int __init
113tx4938_get_mem_size(void)
114{
115 unsigned int c0;
116 unsigned int c1;
117 unsigned int c2;
118 unsigned int c3;
119 unsigned int total;
120
121 /* MVMCP -- need #defs for these registers */
122 c0 = tx4938_process_sdccr((u64 *) 0xff1f8000);
123 c1 = tx4938_process_sdccr((u64 *) 0xff1f8008);
124 c2 = tx4938_process_sdccr((u64 *) 0xff1f8010);
125 c3 = tx4938_process_sdccr((u64 *) 0xff1f8018);
126 total = c0 + c1 + c2 + c3;
127
128 return (total);
129}
diff --git a/arch/mips/tx4938/common/rtc_rx5c348.c b/arch/mips/tx4938/common/rtc_rx5c348.c
new file mode 100644
index 000000000000..d249edbb6af4
--- /dev/null
+++ b/arch/mips/tx4938/common/rtc_rx5c348.c
@@ -0,0 +1,202 @@
1/*
2 * RTC routines for RICOH Rx5C348 SPI chip.
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/string.h>
15#include <linux/rtc.h>
16#include <linux/time.h>
17#include <asm/time.h>
18#include <asm/tx4938/spi.h>
19
20#define EPOCH 2000
21
22/* registers */
23#define Rx5C348_REG_SECOND 0
24#define Rx5C348_REG_MINUTE 1
25#define Rx5C348_REG_HOUR 2
26#define Rx5C348_REG_WEEK 3
27#define Rx5C348_REG_DAY 4
28#define Rx5C348_REG_MONTH 5
29#define Rx5C348_REG_YEAR 6
30#define Rx5C348_REG_ADJUST 7
31#define Rx5C348_REG_ALARM_W_MIN 8
32#define Rx5C348_REG_ALARM_W_HOUR 9
33#define Rx5C348_REG_ALARM_W_WEEK 10
34#define Rx5C348_REG_ALARM_D_MIN 11
35#define Rx5C348_REG_ALARM_D_HOUR 12
36#define Rx5C348_REG_CTL1 14
37#define Rx5C348_REG_CTL2 15
38
39/* register bits */
40#define Rx5C348_BIT_PM 0x20 /* REG_HOUR */
41#define Rx5C348_BIT_Y2K 0x80 /* REG_MONTH */
42#define Rx5C348_BIT_24H 0x20 /* REG_CTL1 */
43#define Rx5C348_BIT_XSTP 0x10 /* REG_CTL2 */
44
45/* commands */
46#define Rx5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */
47#define Rx5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */
48#define Rx5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */
49#define Rx5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */
50
51static struct spi_dev_desc srtc_dev_desc = {
52 .baud = 1000000, /* 1.0Mbps @ Vdd 2.0V */
53 .tcss = 31,
54 .tcsh = 1,
55 .tcsr = 62,
56 /* 31us for Tcss (62us for Tcsr) is required for carry operation) */
57 .byteorder = 1, /* MSB-First */
58 .polarity = 0, /* High-Active */
59 .phase = 1, /* Shift-Then-Sample */
60
61};
62static int srtc_chipid;
63static int srtc_24h;
64
65static inline int
66spi_rtc_io(unsigned char *inbuf, unsigned char *outbuf, unsigned int count)
67{
68 unsigned char *inbufs[1], *outbufs[1];
69 unsigned int incounts[2], outcounts[2];
70 inbufs[0] = inbuf;
71 incounts[0] = count;
72 incounts[1] = 0;
73 outbufs[0] = outbuf;
74 outcounts[0] = count;
75 outcounts[1] = 0;
76 return txx9_spi_io(srtc_chipid, &srtc_dev_desc,
77 inbufs, incounts, outbufs, outcounts, 0);
78}
79
80/*
81 * Conversion between binary and BCD.
82 */
83#ifndef BCD_TO_BIN
84#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
85#endif
86
87#ifndef BIN_TO_BCD
88#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
89#endif
90
91/* RTC-dependent code for time.c */
92
93static int
94rtc_rx5c348_set_time(unsigned long t)
95{
96 unsigned char inbuf[8];
97 struct rtc_time tm;
98 u8 year, month, day, hour, minute, second, century;
99
100 /* convert */
101 to_tm(t, &tm);
102
103 year = tm.tm_year % 100;
104 month = tm.tm_mon+1; /* tm_mon starts from 0 to 11 */
105 day = tm.tm_mday;
106 hour = tm.tm_hour;
107 minute = tm.tm_min;
108 second = tm.tm_sec;
109 century = tm.tm_year / 100;
110
111 inbuf[0] = Rx5C348_CMD_MW(Rx5C348_REG_SECOND);
112 BIN_TO_BCD(second);
113 inbuf[1] = second;
114 BIN_TO_BCD(minute);
115 inbuf[2] = minute;
116
117 if (srtc_24h) {
118 BIN_TO_BCD(hour);
119 inbuf[3] = hour;
120 } else {
121 /* hour 0 is AM12, noon is PM12 */
122 inbuf[3] = 0;
123 if (hour >= 12)
124 inbuf[3] = Rx5C348_BIT_PM;
125 hour = (hour + 11) % 12 + 1;
126 BIN_TO_BCD(hour);
127 inbuf[3] |= hour;
128 }
129 inbuf[4] = 0; /* ignore week */
130 BIN_TO_BCD(day);
131 inbuf[5] = day;
132 BIN_TO_BCD(month);
133 inbuf[6] = month;
134 if (century >= 20)
135 inbuf[6] |= Rx5C348_BIT_Y2K;
136 BIN_TO_BCD(year);
137 inbuf[7] = year;
138 /* write in one transfer to avoid data inconsistency */
139 return spi_rtc_io(inbuf, NULL, 8);
140}
141
142static unsigned long
143rtc_rx5c348_get_time(void)
144{
145 unsigned char inbuf[8], outbuf[8];
146 unsigned int year, month, day, hour, minute, second;
147
148 inbuf[0] = Rx5C348_CMD_MR(Rx5C348_REG_SECOND);
149 memset(inbuf + 1, 0, 7);
150 /* read in one transfer to avoid data inconsistency */
151 if (spi_rtc_io(inbuf, outbuf, 8))
152 return 0;
153 second = outbuf[1];
154 BCD_TO_BIN(second);
155 minute = outbuf[2];
156 BCD_TO_BIN(minute);
157 if (srtc_24h) {
158 hour = outbuf[3];
159 BCD_TO_BIN(hour);
160 } else {
161 hour = outbuf[3] & ~Rx5C348_BIT_PM;
162 BCD_TO_BIN(hour);
163 hour %= 12;
164 if (outbuf[3] & Rx5C348_BIT_PM)
165 hour += 12;
166 }
167 day = outbuf[5];
168 BCD_TO_BIN(day);
169 month = outbuf[6] & ~Rx5C348_BIT_Y2K;
170 BCD_TO_BIN(month);
171 year = outbuf[7];
172 BCD_TO_BIN(year);
173 year += EPOCH;
174
175 return mktime(year, month, day, hour, minute, second);
176}
177
178void __init
179rtc_rx5c348_init(int chipid)
180{
181 unsigned char inbuf[2], outbuf[2];
182 srtc_chipid = chipid;
183 /* turn on RTC if it is not on */
184 inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL2);
185 inbuf[1] = 0;
186 spi_rtc_io(inbuf, outbuf, 2);
187 if (outbuf[1] & Rx5C348_BIT_XSTP) {
188 inbuf[0] = Rx5C348_CMD_W(Rx5C348_REG_CTL2);
189 inbuf[1] = 0;
190 spi_rtc_io(inbuf, NULL, 2);
191 }
192
193 inbuf[0] = Rx5C348_CMD_R(Rx5C348_REG_CTL1);
194 inbuf[1] = 0;
195 spi_rtc_io(inbuf, outbuf, 2);
196 if (outbuf[1] & Rx5C348_BIT_24H)
197 srtc_24h = 1;
198
199 /* set the function pointers */
200 rtc_get_time = rtc_rx5c348_get_time;
201 rtc_set_time = rtc_rx5c348_set_time;
202}
diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c
new file mode 100644
index 000000000000..fc992953bf95
--- /dev/null
+++ b/arch/mips/tx4938/common/setup.c
@@ -0,0 +1,91 @@
1/*
2 * linux/arch/mips/tx4938/common/setup.c
3 *
4 * common tx4938 setup routines
5 *
6 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
7 * terms of the GNU General Public License version 2. This program is
8 * licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
12 */
13
14#include <linux/errno.h>
15#include <linux/init.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/signal.h>
19#include <linux/sched.h>
20#include <linux/types.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/timex.h>
24#include <linux/slab.h>
25#include <linux/random.h>
26#include <linux/irq.h>
27#include <asm/bitops.h>
28#include <asm/bootinfo.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/mipsregs.h>
32#include <asm/system.h>
33#include <asm/time.h>
34#include <asm/time.h>
35#include <asm/tx4938/rbtx4938.h>
36
37extern void toshiba_rbtx4938_setup(void);
38extern void rbtx4938_time_init(void);
39
40void __init tx4938_setup(void);
41void __init tx4938_time_init(void);
42void __init tx4938_timer_setup(struct irqaction *irq);
43void dump_cp0(char *key);
44
45void (*__wbflush) (void);
46
47static void
48tx4938_write_buffer_flush(void)
49{
50 mmiowb();
51
52 __asm__ __volatile__(
53 ".set push\n\t"
54 ".set noreorder\n\t"
55 "lw $0,%0\n\t"
56 "nop\n\t"
57 ".set pop"
58 : /* no output */
59 : "m" (*(int *)KSEG1)
60 : "memory");
61}
62
63void __init
64plat_setup(void)
65{
66 board_time_init = tx4938_time_init;
67 board_timer_setup = tx4938_timer_setup;
68 __wbflush = tx4938_write_buffer_flush;
69 toshiba_rbtx4938_setup();
70}
71
72void __init
73tx4938_time_init(void)
74{
75 rbtx4938_time_init();
76}
77
78void __init
79tx4938_timer_setup(struct irqaction *irq)
80{
81 u32 count;
82 u32 c1;
83 u32 c2;
84
85 setup_irq(TX4938_IRQ_CPU_TIMER, irq);
86
87 c1 = read_c0_count();
88 count = c1 + (mips_hpt_frequency / HZ);
89 write_c0_compare(count);
90 c2 = read_c0_count();
91}
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/Makefile b/arch/mips/tx4938/toshiba_rbtx4938/Makefile
new file mode 100644
index 000000000000..226941279d75
--- /dev/null
+++ b/arch/mips/tx4938/toshiba_rbtx4938/Makefile
@@ -0,0 +1,9 @@
1#
2# Makefile for common code for Toshiba TX4927 based systems
3#
4# Note! Dependencies are done automagically by 'make dep', which also
5# removes any old dependencies. DON'T put your own dependencies here
6# unless it's something special (ie not a .c file).
7#
8
9obj-y += prom.o setup.o irq.o spi_eeprom.o spi_txx9.o
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
new file mode 100644
index 000000000000..230f5a93c2e6
--- /dev/null
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -0,0 +1,244 @@
1/*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c
3 *
4 * Toshiba RBTX4938 specific interrupt handlers
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14
15/*
16IRQ Device
17
1816 TX4938-CP0/00 Software 0
1917 TX4938-CP0/01 Software 1
2018 TX4938-CP0/02 Cascade TX4938-CP0
2119 TX4938-CP0/03 Multiplexed -- do not use
2220 TX4938-CP0/04 Multiplexed -- do not use
2321 TX4938-CP0/05 Multiplexed -- do not use
2422 TX4938-CP0/06 Multiplexed -- do not use
2523 TX4938-CP0/07 CPU TIMER
26
2724 TX4938-PIC/00
2825 TX4938-PIC/01
2926 TX4938-PIC/02 Cascade RBTX4938-IOC
3027 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet
3128 TX4938-PIC/04
3229 TX4938-PIC/05 TX4938 ETH1
3330 TX4938-PIC/06 TX4938 ETH0
3431 TX4938-PIC/07
3532 TX4938-PIC/08 TX4938 SIO 0
3633 TX4938-PIC/09 TX4938 SIO 1
3734 TX4938-PIC/10 TX4938 DMA0
3835 TX4938-PIC/11 TX4938 DMA1
3936 TX4938-PIC/12 TX4938 DMA2
4037 TX4938-PIC/13 TX4938 DMA3
4138 TX4938-PIC/14
4239 TX4938-PIC/15
4340 TX4938-PIC/16 TX4938 PCIC
4441 TX4938-PIC/17 TX4938 TMR0
4542 TX4938-PIC/18 TX4938 TMR1
4643 TX4938-PIC/19 TX4938 TMR2
4744 TX4938-PIC/20
4845 TX4938-PIC/21
4946 TX4938-PIC/22 TX4938 PCIERR
5047 TX4938-PIC/23
5148 TX4938-PIC/24
5249 TX4938-PIC/25
5350 TX4938-PIC/26
5451 TX4938-PIC/27
5552 TX4938-PIC/28
5653 TX4938-PIC/29
5754 TX4938-PIC/30
5855 TX4938-PIC/31 TX4938 SPI
59
6056 RBTX4938-IOC/00 PCI-D
6157 RBTX4938-IOC/01 PCI-C
6258 RBTX4938-IOC/02 PCI-B
6359 RBTX4938-IOC/03 PCI-A
6460 RBTX4938-IOC/04 RTC
6561 RBTX4938-IOC/05 ATA
6662 RBTX4938-IOC/06 MODEM
6763 RBTX4938-IOC/07 SWINT
68*/
69#include <linux/init.h>
70#include <linux/kernel.h>
71#include <linux/types.h>
72#include <linux/mm.h>
73#include <linux/swap.h>
74#include <linux/ioport.h>
75#include <linux/sched.h>
76#include <linux/interrupt.h>
77#include <linux/pci.h>
78#include <linux/timex.h>
79#include <asm/bootinfo.h>
80#include <asm/page.h>
81#include <asm/io.h>
82#include <asm/irq.h>
83#include <asm/processor.h>
84#include <asm/ptrace.h>
85#include <asm/reboot.h>
86#include <asm/time.h>
87#include <linux/version.h>
88#include <linux/bootmem.h>
89#include <asm/tx4938/rbtx4938.h>
90
91static unsigned int toshiba_rbtx4938_irq_ioc_startup(unsigned int irq);
92static void toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq);
93static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
94static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
95static void toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq);
96static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq);
97
98DEFINE_SPINLOCK(toshiba_rbtx4938_ioc_lock);
99
100#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
101static struct hw_interrupt_type toshiba_rbtx4938_irq_ioc_type = {
102 .typename = TOSHIBA_RBTX4938_IOC_NAME,
103 .startup = toshiba_rbtx4938_irq_ioc_startup,
104 .shutdown = toshiba_rbtx4938_irq_ioc_shutdown,
105 .enable = toshiba_rbtx4938_irq_ioc_enable,
106 .disable = toshiba_rbtx4938_irq_ioc_disable,
107 .ack = toshiba_rbtx4938_irq_ioc_mask_and_ack,
108 .end = toshiba_rbtx4938_irq_ioc_end,
109 .set_affinity = NULL
110};
111
112#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
113#define TOSHIBA_RBTX4938_IOC_INTR_STAT 0xb7f0200a
114
115int
116toshiba_rbtx4938_irq_nested(int sw_irq)
117{
118 u8 level3;
119
120 level3 = reg_rd08(TOSHIBA_RBTX4938_IOC_INTR_STAT) & 0xff;
121 if (level3) {
122 /* must use fls so onboard ATA has priority */
123 sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1;
124 }
125
126 wbflush();
127 return sw_irq;
128}
129
130static struct irqaction toshiba_rbtx4938_irq_ioc_action = {
131 .handler = no_action,
132 .flags = 0,
133 .mask = CPU_MASK_NONE,
134 .name = TOSHIBA_RBTX4938_IOC_NAME,
135};
136
137/**********************************************************************************/
138/* Functions for ioc */
139/**********************************************************************************/
140static void __init
141toshiba_rbtx4938_irq_ioc_init(void)
142{
143 int i;
144
145 for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG;
146 i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) {
147 irq_desc[i].status = IRQ_DISABLED;
148 irq_desc[i].action = 0;
149 irq_desc[i].depth = 3;
150 irq_desc[i].handler = &toshiba_rbtx4938_irq_ioc_type;
151 }
152
153 setup_irq(RBTX4938_IRQ_IOCINT,
154 &toshiba_rbtx4938_irq_ioc_action);
155}
156
157static unsigned int
158toshiba_rbtx4938_irq_ioc_startup(unsigned int irq)
159{
160 toshiba_rbtx4938_irq_ioc_enable(irq);
161
162 return 0;
163}
164
165static void
166toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq)
167{
168 toshiba_rbtx4938_irq_ioc_disable(irq);
169}
170
171static void
172toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
173{
174 unsigned long flags;
175 volatile unsigned char v;
176
177 spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
178
179 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
180 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
181 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
182 mmiowb();
183 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
184
185 spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
186}
187
188static void
189toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
190{
191 unsigned long flags;
192 volatile unsigned char v;
193
194 spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
195
196 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
197 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
198 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
199 mmiowb();
200 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
201
202 spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
203}
204
205static void
206toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq)
207{
208 toshiba_rbtx4938_irq_ioc_disable(irq);
209}
210
211static void
212toshiba_rbtx4938_irq_ioc_end(unsigned int irq)
213{
214 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
215 toshiba_rbtx4938_irq_ioc_enable(irq);
216 }
217}
218
219extern void __init txx9_spi_irqinit(int irc_irq);
220
221void __init arch_init_irq(void)
222{
223 extern void tx4938_irq_init(void);
224
225 /* Now, interrupt control disabled, */
226 /* all IRC interrupts are masked, */
227 /* all IRC interrupt mode are Low Active. */
228
229 /* mask all IOC interrupts */
230 *rbtx4938_imask_ptr = 0;
231
232 /* clear SoftInt interrupts */
233 *rbtx4938_softint_ptr = 0;
234 tx4938_irq_init();
235 toshiba_rbtx4938_irq_ioc_init();
236 /* Onboard 10M Ether: High Active */
237 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000040);
238
239 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_SPI_SEL) {
240 txx9_spi_irqinit(RBTX4938_IRQ_IRC_SPI);
241 }
242
243 wbflush();
244}
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/prom.c b/arch/mips/tx4938/toshiba_rbtx4938/prom.c
new file mode 100644
index 000000000000..7df8b32ba265
--- /dev/null
+++ b/arch/mips/tx4938/toshiba_rbtx4938/prom.c
@@ -0,0 +1,78 @@
1/*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/prom.c
3 *
4 * rbtx4938 specific prom routines
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14
15#include <linux/config.h>
16#include <linux/init.h>
17#include <linux/mm.h>
18#include <linux/sched.h>
19#include <linux/bootmem.h>
20
21#include <asm/addrspace.h>
22#include <asm/bootinfo.h>
23#include <asm/tx4938/tx4938.h>
24
25void __init prom_init_cmdline(void)
26{
27 int argc = (int) fw_arg0;
28 char **argv = (char **) fw_arg1;
29 int i;
30
31 /* ignore all built-in args if any f/w args given */
32 if (argc > 1) {
33 *arcs_cmdline = '\0';
34 }
35
36 for (i = 1; i < argc; i++) {
37 if (i != 1) {
38 strcat(arcs_cmdline, " ");
39 }
40 strcat(arcs_cmdline, argv[i]);
41 }
42}
43
44void __init prom_init(void)
45{
46 extern int tx4938_get_mem_size(void);
47 int msize;
48#ifndef CONFIG_TX4938_NAND_BOOT
49 prom_init_cmdline();
50#endif
51 mips_machgroup = MACH_GROUP_TOSHIBA;
52 mips_machtype = MACH_TOSHIBA_RBTX4938;
53
54 msize = tx4938_get_mem_size();
55 add_memory_region(0, msize << 20, BOOT_MEM_RAM);
56
57 return;
58}
59
60unsigned long __init prom_free_prom_memory(void)
61{
62 return 0;
63}
64
65void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
66{
67 return;
68}
69
70const char *get_system_type(void)
71{
72 return "Toshiba RBTX4938";
73}
74
75char * __init prom_getcmdline(void)
76{
77 return &(arcs_cmdline[0]);
78}
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
new file mode 100644
index 000000000000..9f1dcc8ca5a3
--- /dev/null
+++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
@@ -0,0 +1,1035 @@
1/*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c
3 *
4 * Setup pointers to hardware-dependent routines.
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14#include <linux/config.h>
15#include <linux/init.h>
16#include <linux/types.h>
17#include <linux/ioport.h>
18#include <linux/proc_fs.h>
19#include <linux/delay.h>
20#include <linux/interrupt.h>
21#include <linux/console.h>
22#include <linux/pci.h>
23#include <asm/wbflush.h>
24#include <asm/reboot.h>
25#include <asm/irq.h>
26#include <asm/time.h>
27#include <asm/uaccess.h>
28#include <asm/io.h>
29#include <asm/bootinfo.h>
30#include <asm/tx4938/rbtx4938.h>
31#ifdef CONFIG_SERIAL_TXX9
32#include <linux/tty.h>
33#include <linux/serial.h>
34#include <linux/serial_core.h>
35#endif
36
37extern void rbtx4938_time_init(void) __init;
38extern char * __init prom_getcmdline(void);
39static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
40
41/* These functions are used for rebooting or halting the machine*/
42extern void rbtx4938_machine_restart(char *command);
43extern void rbtx4938_machine_halt(void);
44extern void rbtx4938_machine_power_off(void);
45
46/* clocks */
47unsigned int txx9_master_clock;
48unsigned int txx9_cpu_clock;
49unsigned int txx9_gbus_clock;
50
51unsigned long rbtx4938_ce_base[8];
52unsigned long rbtx4938_ce_size[8];
53int txboard_pci66_mode;
54static int tx4938_pcic_trdyto; /* default: disabled */
55static int tx4938_pcic_retryto; /* default: disabled */
56static int tx4938_ccfg_toeon = 1;
57
58struct tx4938_pcic_reg *pcicptrs[4] = {
59 tx4938_pcicptr /* default setting for TX4938 */
60};
61
62static struct {
63 unsigned long base;
64 unsigned long size;
65} phys_regions[16] __initdata;
66static int num_phys_regions __initdata;
67
68#define PHYS_REGION_MINSIZE 0x10000
69
70void rbtx4938_machine_halt(void)
71{
72 printk(KERN_NOTICE "System Halted\n");
73 local_irq_disable();
74
75 while (1)
76 __asm__(".set\tmips3\n\t"
77 "wait\n\t"
78 ".set\tmips0");
79}
80
81void rbtx4938_machine_power_off(void)
82{
83 rbtx4938_machine_halt();
84 /* no return */
85}
86
87void rbtx4938_machine_restart(char *command)
88{
89 local_irq_disable();
90
91 printk("Rebooting...");
92 *rbtx4938_softresetlock_ptr = 1;
93 *rbtx4938_sfvol_ptr = 1;
94 *rbtx4938_softreset_ptr = 1;
95 wbflush();
96
97 while(1);
98}
99
100void __init
101txboard_add_phys_region(unsigned long base, unsigned long size)
102{
103 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
104 printk("phys_region overflow\n");
105 return;
106 }
107 phys_regions[num_phys_regions].base = base;
108 phys_regions[num_phys_regions].size = size;
109 num_phys_regions++;
110}
111unsigned long __init
112txboard_find_free_phys_region(unsigned long begin, unsigned long end,
113 unsigned long size)
114{
115 unsigned long base;
116 int i;
117
118 for (base = begin / size * size; base < end; base += size) {
119 for (i = 0; i < num_phys_regions; i++) {
120 if (phys_regions[i].size &&
121 base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
122 base + (size - 1) >= phys_regions[i].base)
123 break;
124 }
125 if (i == num_phys_regions)
126 return base;
127 }
128 return 0;
129}
130unsigned long __init
131txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
132 unsigned long *size)
133{
134 unsigned long sz, base;
135 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
136 base = txboard_find_free_phys_region(begin, end, sz);
137 if (base) {
138 *size = sz;
139 return base;
140 }
141 }
142 return 0;
143}
144unsigned long __init
145txboard_request_phys_region_range(unsigned long begin, unsigned long end,
146 unsigned long size)
147{
148 unsigned long base;
149 base = txboard_find_free_phys_region(begin, end, size);
150 if (base)
151 txboard_add_phys_region(base, size);
152 return base;
153}
154unsigned long __init
155txboard_request_phys_region(unsigned long size)
156{
157 unsigned long base;
158 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
159 base = txboard_find_free_phys_region(begin, end, size);
160 if (base)
161 txboard_add_phys_region(base, size);
162 return base;
163}
164unsigned long __init
165txboard_request_phys_region_shrink(unsigned long *size)
166{
167 unsigned long base;
168 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
169 base = txboard_find_free_phys_region_shrink(begin, end, size);
170 if (base)
171 txboard_add_phys_region(base, *size);
172 return base;
173}
174
175#ifdef CONFIG_PCI
176void __init
177tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr,
178 struct pci_controller *channel,
179 unsigned long pci_io_base,
180 int extarb)
181{
182 int i;
183
184 /* Disable All Initiator Space */
185 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
186 TX4938_PCIC_PCICCFG_G2PMEN(1)|
187 TX4938_PCIC_PCICCFG_G2PMEN(2)|
188 TX4938_PCIC_PCICCFG_G2PIOEN);
189
190 /* GB->PCI mappings */
191 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
192 pcicptr->g2piogbase = pci_io_base |
193#ifdef __BIG_ENDIAN
194 TX4938_PCIC_G2PIOGBASE_ECHG
195#else
196 TX4938_PCIC_G2PIOGBASE_BSDIS
197#endif
198 ;
199 pcicptr->g2piopbase = 0;
200 for (i = 0; i < 3; i++) {
201 pcicptr->g2pmmask[i] = 0;
202 pcicptr->g2pmgbase[i] = 0;
203 pcicptr->g2pmpbase[i] = 0;
204 }
205 if (channel->mem_resource->end) {
206 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
207 pcicptr->g2pmgbase[0] = channel->mem_resource->start |
208#ifdef __BIG_ENDIAN
209 TX4938_PCIC_G2PMnGBASE_ECHG
210#else
211 TX4938_PCIC_G2PMnGBASE_BSDIS
212#endif
213 ;
214 pcicptr->g2pmpbase[0] = channel->mem_resource->start;
215 }
216 /* PCI->GB mappings (I/O 256B) */
217 pcicptr->p2giopbase = 0; /* 256B */
218 pcicptr->p2giogbase = 0;
219 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
220 pcicptr->p2gm0plbase = 0;
221 pcicptr->p2gm0pubase = 0;
222 pcicptr->p2gmgbase[0] = 0 |
223 TX4938_PCIC_P2GMnGBASE_TMEMEN |
224#ifdef __BIG_ENDIAN
225 TX4938_PCIC_P2GMnGBASE_TECHG
226#else
227 TX4938_PCIC_P2GMnGBASE_TBSDIS
228#endif
229 ;
230 /* PCI->GB mappings (MEM 16MB) */
231 pcicptr->p2gm1plbase = 0xffffffff;
232 pcicptr->p2gm1pubase = 0xffffffff;
233 pcicptr->p2gmgbase[1] = 0;
234 /* PCI->GB mappings (MEM 1MB) */
235 pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */
236 pcicptr->p2gmgbase[2] = 0;
237
238 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
239 /* Enable Initiator Memory Space */
240 if (channel->mem_resource->end)
241 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
242 /* Enable Initiator I/O Space */
243 if (channel->io_resource->end)
244 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
245 /* Enable Initiator Config */
246 pcicptr->pciccfg |=
247 TX4938_PCIC_PCICCFG_ICAEN |
248 TX4938_PCIC_PCICCFG_TCAR;
249
250 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
251 pcicptr->pcicfg1 = 0;
252
253 pcicptr->g2ptocnt &= ~0xffff;
254
255 if (tx4938_pcic_trdyto >= 0) {
256 pcicptr->g2ptocnt &= ~0xff;
257 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
258 }
259
260 if (tx4938_pcic_retryto >= 0) {
261 pcicptr->g2ptocnt &= ~0xff00;
262 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
263 }
264
265 /* Clear All Local Bus Status */
266 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
267 /* Enable All Local Bus Interrupts */
268 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
269 /* Clear All Initiator Status */
270 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
271 /* Enable All Initiator Interrupts */
272 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
273 /* Clear All PCI Status Error */
274 pcicptr->pcistatus =
275 (pcicptr->pcistatus & 0x0000ffff) |
276 (TX4938_PCIC_PCISTATUS_ALL << 16);
277 /* Enable All PCI Status Error Interrupts */
278 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
279
280 if (!extarb) {
281 /* Reset Bus Arbiter */
282 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
283 pcicptr->pbabm = 0;
284 /* Enable Bus Arbiter */
285 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
286 }
287
288 /* PCIC Int => IRC IRQ16 */
289 pcicptr->pcicfg2 =
290 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
291
292 pcicptr->pcistatus = PCI_COMMAND_MASTER |
293 PCI_COMMAND_MEMORY |
294 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
295}
296
297int __init
298tx4938_report_pciclk(void)
299{
300 unsigned long pcode = TX4938_REV_PCODE();
301 int pciclk = 0;
302 printk("TX%lx PCIC --%s PCICLK:",
303 pcode,
304 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
305 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
306
307 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
308 case TX4938_CCFG_PCIDIVMODE_4:
309 pciclk = txx9_cpu_clock / 4; break;
310 case TX4938_CCFG_PCIDIVMODE_4_5:
311 pciclk = txx9_cpu_clock * 2 / 9; break;
312 case TX4938_CCFG_PCIDIVMODE_5:
313 pciclk = txx9_cpu_clock / 5; break;
314 case TX4938_CCFG_PCIDIVMODE_5_5:
315 pciclk = txx9_cpu_clock * 2 / 11; break;
316 case TX4938_CCFG_PCIDIVMODE_8:
317 pciclk = txx9_cpu_clock / 8; break;
318 case TX4938_CCFG_PCIDIVMODE_9:
319 pciclk = txx9_cpu_clock / 9; break;
320 case TX4938_CCFG_PCIDIVMODE_10:
321 pciclk = txx9_cpu_clock / 10; break;
322 case TX4938_CCFG_PCIDIVMODE_11:
323 pciclk = txx9_cpu_clock / 11; break;
324 }
325 printk("Internal(%dMHz)", pciclk / 1000000);
326 } else {
327 printk("External");
328 pciclk = -1;
329 }
330 printk("\n");
331 return pciclk;
332}
333
334void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
335{
336 pcicptrs[ch] = pcicptr;
337}
338
339struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
340{
341 return pcicptrs[ch];
342}
343
344static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
345 int top_bus, int busnr, int devfn)
346{
347 static struct pci_dev dev;
348 static struct pci_bus bus;
349
350 dev.sysdata = (void *)hose;
351 dev.devfn = devfn;
352 bus.number = busnr;
353 bus.ops = hose->pci_ops;
354 bus.parent = NULL;
355 dev.bus = &bus;
356
357 return &dev;
358}
359
360#define EARLY_PCI_OP(rw, size, type) \
361static int early_##rw##_config_##size(struct pci_controller *hose, \
362 int top_bus, int bus, int devfn, int offset, type value) \
363{ \
364 return pci_##rw##_config_##size( \
365 fake_pci_dev(hose, top_bus, bus, devfn), \
366 offset, value); \
367}
368
369EARLY_PCI_OP(read, word, u16 *)
370
371int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
372{
373 u32 pci_devfn;
374 unsigned short vid;
375 int devfn_start = 0;
376 int devfn_stop = 0xff;
377 int cap66 = -1;
378 u16 stat;
379
380 printk("PCI: Checking 66MHz capabilities...\n");
381
382 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
383 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
384 PCI_VENDOR_ID, &vid);
385
386 if (vid == 0xffff) continue;
387
388 /* check 66MHz capability */
389 if (cap66 < 0)
390 cap66 = 1;
391 if (cap66) {
392 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
393 PCI_STATUS, &stat);
394 if (!(stat & PCI_STATUS_66MHZ)) {
395 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
396 current_bus, pci_devfn);
397 cap66 = 0;
398 break;
399 }
400 }
401 }
402 return cap66 > 0;
403}
404
405int __init
406tx4938_pciclk66_setup(void)
407{
408 int pciclk;
409
410 /* Assert M66EN */
411 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
412 /* Double PCICLK (if possible) */
413 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
414 unsigned int pcidivmode =
415 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
416 switch (pcidivmode) {
417 case TX4938_CCFG_PCIDIVMODE_8:
418 case TX4938_CCFG_PCIDIVMODE_4:
419 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
420 pciclk = txx9_cpu_clock / 4;
421 break;
422 case TX4938_CCFG_PCIDIVMODE_9:
423 case TX4938_CCFG_PCIDIVMODE_4_5:
424 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
425 pciclk = txx9_cpu_clock * 2 / 9;
426 break;
427 case TX4938_CCFG_PCIDIVMODE_10:
428 case TX4938_CCFG_PCIDIVMODE_5:
429 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
430 pciclk = txx9_cpu_clock / 5;
431 break;
432 case TX4938_CCFG_PCIDIVMODE_11:
433 case TX4938_CCFG_PCIDIVMODE_5_5:
434 default:
435 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
436 pciclk = txx9_cpu_clock * 2 / 11;
437 break;
438 }
439 tx4938_ccfgptr->ccfg =
440 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
441 | pcidivmode;
442 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
443 (unsigned long)tx4938_ccfgptr->ccfg);
444 } else {
445 pciclk = -1;
446 }
447 return pciclk;
448}
449
450extern struct pci_controller tx4938_pci_controller[];
451static int __init tx4938_pcibios_init(void)
452{
453 unsigned long mem_base[2];
454 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
455 unsigned long io_base[2];
456 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
457 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
458 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
459
460 PCIBIOS_MIN_IO = 0x00001000UL;
461 PCIBIOS_MIN_MEM = 0x01000000UL;
462
463 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
464 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
465
466 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
467 (unsigned short)(tx4938_pcicptr->pciid >> 16),
468 (unsigned short)(tx4938_pcicptr->pciid & 0xffff),
469 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
470 extarb ? "External" : "Internal");
471
472 /* setup PCI area */
473 tx4938_pci_controller[0].io_resource->start = io_base[0];
474 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
475 tx4938_pci_controller[0].mem_resource->start = mem_base[0];
476 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
477
478 set_tx4938_pcicptr(0, tx4938_pcicptr);
479
480 register_pci_controller(&tx4938_pci_controller[0]);
481
482 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
483 printk("TX4938_CCFG_PCI66 already configured\n");
484 txboard_pci66_mode = -1; /* already configured */
485 }
486
487 /* Reset PCI Bus */
488 *rbtx4938_pcireset_ptr = 0;
489 /* Reset PCIC */
490 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
491 if (txboard_pci66_mode > 0)
492 tx4938_pciclk66_setup();
493 mdelay(10);
494 /* clear PCIC reset */
495 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
496 *rbtx4938_pcireset_ptr = 1;
497 wbflush();
498 tx4938_report_pcic_status1(tx4938_pcicptr);
499
500 tx4938_report_pciclk();
501 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
502 if (txboard_pci66_mode == 0 &&
503 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
504 /* Reset PCI Bus */
505 *rbtx4938_pcireset_ptr = 0;
506 /* Reset PCIC */
507 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
508 tx4938_pciclk66_setup();
509 mdelay(10);
510 /* clear PCIC reset */
511 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
512 *rbtx4938_pcireset_ptr = 1;
513 wbflush();
514 /* Reinitialize PCIC */
515 tx4938_report_pciclk();
516 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
517 }
518
519 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]);
520 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]);
521 /* Reset PCIC1 */
522 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST;
523 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
524 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD))
525 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66;
526 else
527 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66;
528 mdelay(10);
529 /* clear PCIC1 reset */
530 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
531 tx4938_report_pcic_status1(tx4938_pcic1ptr);
532
533 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x",
534 (unsigned short)(tx4938_pcic1ptr->pciid >> 16),
535 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff),
536 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff));
537 printk("%s PCICLK:%dMHz\n",
538 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
539 txx9_gbus_clock /
540 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
541 1000000);
542
543 /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */
544 tx4938_pci_controller[1].io_resource->start =
545 io_base[1] - io_base[0];
546 tx4938_pci_controller[1].io_resource->end =
547 io_base[1] - io_base[0] + io_size[1] - 1;
548 tx4938_pci_controller[1].mem_resource->start = mem_base[1];
549 tx4938_pci_controller[1].mem_resource->end =
550 mem_base[1] + mem_size[1] - 1;
551 set_tx4938_pcicptr(1, tx4938_pcic1ptr);
552
553 register_pci_controller(&tx4938_pci_controller[1]);
554
555 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
556
557 /* map ioport 0 to PCI I/O space address 0 */
558 set_io_port_base(KSEG1 + io_base[0]);
559
560 return 0;
561}
562
563arch_initcall(tx4938_pcibios_init);
564
565#endif /* CONFIG_PCI */
566
567/* SPI support */
568
569/* chip select for SPI devices */
570#define SEEPROM1_CS 7 /* PIO7 */
571#define SEEPROM2_CS 0 /* IOC */
572#define SEEPROM3_CS 1 /* IOC */
573#define SRTC_CS 2 /* IOC */
574
575static int rbtx4938_spi_cs_func(int chipid, int on)
576{
577 unsigned char bit;
578 switch (chipid) {
579 case RBTX4938_SEEPROM1_CHIPID:
580 if (on)
581 tx4938_pioptr->dout &= ~(1 << SEEPROM1_CS);
582 else
583 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
584 return 0;
585 break;
586 case RBTX4938_SEEPROM2_CHIPID:
587 bit = (1 << SEEPROM2_CS);
588 break;
589 case RBTX4938_SEEPROM3_CHIPID:
590 bit = (1 << SEEPROM3_CS);
591 break;
592 case RBTX4938_SRTC_CHIPID:
593 bit = (1 << SRTC_CS);
594 break;
595 default:
596 return -ENODEV;
597 }
598 /* bit1,2,4 are low active, bit3 is high active */
599 *rbtx4938_spics_ptr =
600 (*rbtx4938_spics_ptr & ~bit) |
601 ((on ? (bit ^ 0x0b) : ~(bit ^ 0x0b)) & bit);
602 return 0;
603}
604
605#ifdef CONFIG_PCI
606extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
607
608int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr)
609{
610 struct pci_controller *channel = (struct pci_controller *)dev->bus->sysdata;
611 static unsigned char dat[17];
612 static int read_dat = 0;
613 int ch = 0;
614
615 if (channel != &tx4938_pci_controller[1])
616 return -ENODEV;
617 /* TX4938 PCIC1 */
618 switch (PCI_SLOT(dev->devfn)) {
619 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
620 ch = 0;
621 break;
622 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
623 ch = 1;
624 break;
625 default:
626 return -ENODEV;
627 }
628 if (!read_dat) {
629 unsigned char sum;
630 int i;
631 read_dat = 1;
632 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
633 if (spi_eeprom_read(RBTX4938_SEEPROM1_CHIPID,
634 0, dat, sizeof(dat))) {
635 printk(KERN_ERR "seeprom: read error.\n");
636 } else {
637 if (strcmp(dat, "MAC") != 0)
638 printk(KERN_WARNING "seeprom: bad signature.\n");
639 for (i = 0, sum = 0; i < sizeof(dat); i++)
640 sum += dat[i];
641 if (sum)
642 printk(KERN_WARNING "seeprom: bad checksum.\n");
643 }
644 }
645 memcpy(addr, &dat[4 + 6 * ch], 6);
646 return 0;
647}
648#endif /* CONFIG_PCI */
649
650extern void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on));
651static void __init rbtx4938_spi_setup(void)
652{
653 /* set SPI_SEL */
654 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL;
655 /* chip selects for SPI devices */
656 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
657 tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
658 txx9_spi_init(TX4938_SPI_REG, rbtx4938_spi_cs_func);
659}
660
661static struct resource rbtx4938_fpga_resource;
662
663static char pcode_str[8];
664static struct resource tx4938_reg_resource = {
665 pcode_str, TX4938_REG_BASE, TX4938_REG_BASE+TX4938_REG_SIZE, IORESOURCE_MEM
666};
667
668void __init tx4938_board_setup(void)
669{
670 int i;
671 unsigned long divmode;
672 int cpuclk = 0;
673 unsigned long pcode = TX4938_REV_PCODE();
674
675 ioport_resource.start = 0x1000;
676 ioport_resource.end = 0xffffffff;
677 iomem_resource.start = 0x1000;
678 iomem_resource.end = 0xffffffff; /* expand to 4GB */
679
680 sprintf(pcode_str, "TX%lx", pcode);
681 /* SDRAMC,EBUSC are configured by PROM */
682 for (i = 0; i < 8; i++) {
683 if (!(tx4938_ebuscptr->cr[i] & 0x8))
684 continue; /* disabled */
685 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
686 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i));
687 }
688
689 /* clocks */
690 if (txx9_master_clock) {
691 /* calculate gbus_clock and cpu_clock from master_clock */
692 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
693 switch (divmode) {
694 case TX4938_CCFG_DIVMODE_8:
695 case TX4938_CCFG_DIVMODE_10:
696 case TX4938_CCFG_DIVMODE_12:
697 case TX4938_CCFG_DIVMODE_16:
698 case TX4938_CCFG_DIVMODE_18:
699 txx9_gbus_clock = txx9_master_clock * 4; break;
700 default:
701 txx9_gbus_clock = txx9_master_clock;
702 }
703 switch (divmode) {
704 case TX4938_CCFG_DIVMODE_2:
705 case TX4938_CCFG_DIVMODE_8:
706 cpuclk = txx9_gbus_clock * 2; break;
707 case TX4938_CCFG_DIVMODE_2_5:
708 case TX4938_CCFG_DIVMODE_10:
709 cpuclk = txx9_gbus_clock * 5 / 2; break;
710 case TX4938_CCFG_DIVMODE_3:
711 case TX4938_CCFG_DIVMODE_12:
712 cpuclk = txx9_gbus_clock * 3; break;
713 case TX4938_CCFG_DIVMODE_4:
714 case TX4938_CCFG_DIVMODE_16:
715 cpuclk = txx9_gbus_clock * 4; break;
716 case TX4938_CCFG_DIVMODE_4_5:
717 case TX4938_CCFG_DIVMODE_18:
718 cpuclk = txx9_gbus_clock * 9 / 2; break;
719 }
720 txx9_cpu_clock = cpuclk;
721 } else {
722 if (txx9_cpu_clock == 0) {
723 txx9_cpu_clock = 300000000; /* 300MHz */
724 }
725 /* calculate gbus_clock and master_clock from cpu_clock */
726 cpuclk = txx9_cpu_clock;
727 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
728 switch (divmode) {
729 case TX4938_CCFG_DIVMODE_2:
730 case TX4938_CCFG_DIVMODE_8:
731 txx9_gbus_clock = cpuclk / 2; break;
732 case TX4938_CCFG_DIVMODE_2_5:
733 case TX4938_CCFG_DIVMODE_10:
734 txx9_gbus_clock = cpuclk * 2 / 5; break;
735 case TX4938_CCFG_DIVMODE_3:
736 case TX4938_CCFG_DIVMODE_12:
737 txx9_gbus_clock = cpuclk / 3; break;
738 case TX4938_CCFG_DIVMODE_4:
739 case TX4938_CCFG_DIVMODE_16:
740 txx9_gbus_clock = cpuclk / 4; break;
741 case TX4938_CCFG_DIVMODE_4_5:
742 case TX4938_CCFG_DIVMODE_18:
743 txx9_gbus_clock = cpuclk * 2 / 9; break;
744 }
745 switch (divmode) {
746 case TX4938_CCFG_DIVMODE_8:
747 case TX4938_CCFG_DIVMODE_10:
748 case TX4938_CCFG_DIVMODE_12:
749 case TX4938_CCFG_DIVMODE_16:
750 case TX4938_CCFG_DIVMODE_18:
751 txx9_master_clock = txx9_gbus_clock / 4; break;
752 default:
753 txx9_master_clock = txx9_gbus_clock;
754 }
755 }
756 /* change default value to udelay/mdelay take reasonable time */
757 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
758
759 /* CCFG */
760 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
761 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
762 /* clear PCIC1 reset */
763 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
764 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
765
766 /* enable Timeout BusError */
767 if (tx4938_ccfg_toeon)
768 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE;
769
770 /* DMA selection */
771 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL;
772
773 /* Use external clock for external arbiter */
774 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB))
775 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL;
776
777 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n",
778 pcode_str,
779 cpuclk / 1000000, txx9_master_clock / 1000000,
780 (unsigned long)tx4938_ccfgptr->crir,
781 tx4938_ccfgptr->ccfg,
782 tx4938_ccfgptr->pcfg);
783
784 printk("%s SDRAMC --", pcode_str);
785 for (i = 0; i < 4; i++) {
786 unsigned long long cr = tx4938_sdramcptr->cr[i];
787 unsigned long ram_base, ram_size;
788 if (!((unsigned long)cr & 0x00000400))
789 continue; /* disabled */
790 ram_base = (unsigned long)(cr >> 49) << 21;
791 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
792 if (ram_base >= 0x20000000)
793 continue; /* high memory (ignore) */
794 printk(" CR%d:%016Lx", i, cr);
795 txboard_add_phys_region(ram_base, ram_size);
796 }
797 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
798
799 /* SRAM */
800 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) {
801 unsigned int size = 0x800;
802 unsigned long base =
803 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
804 txboard_add_phys_region(base, size);
805 }
806
807 /* IRC */
808 /* disable interrupt control */
809 tx4938_ircptr->cer = 0;
810
811 /* TMR */
812 /* disable all timers */
813 for (i = 0; i < TX4938_NR_TMR; i++) {
814 tx4938_tmrptr(i)->tcr = 0x00000020;
815 tx4938_tmrptr(i)->tisr = 0;
816 tx4938_tmrptr(i)->cpra = 0xffffffff;
817 tx4938_tmrptr(i)->itmr = 0;
818 tx4938_tmrptr(i)->ccdr = 0;
819 tx4938_tmrptr(i)->pgmr = 0;
820 }
821
822 /* enable DMA */
823 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
824 TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
825
826 /* PIO */
827 tx4938_pioptr->maskcpu = 0;
828 tx4938_pioptr->maskext = 0;
829
830 /* TX4938 internal registers */
831 if (request_resource(&iomem_resource, &tx4938_reg_resource))
832 printk("request resource for internal registers failed\n");
833}
834
835#ifdef CONFIG_PCI
836static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr)
837{
838 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
839 unsigned long g2pstatus = pcicptr->g2pstatus;
840 unsigned long pcicstatus = pcicptr->pcicstatus;
841 static struct {
842 unsigned long flag;
843 const char *str;
844 } pcistat_tbl[] = {
845 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
846 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
847 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
848 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
849 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
850 { PCI_STATUS_PARITY, "MasterParityError" },
851 }, g2pstat_tbl[] = {
852 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
853 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
854 }, pcicstat_tbl[] = {
855 { TX4938_PCIC_PCICSTATUS_PME, "PME" },
856 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
857 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
858 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
859 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
860 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
861 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
862 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
863 };
864 int i;
865
866 printk("pcistat:%04x(", pcistatus);
867 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
868 if (pcistatus & pcistat_tbl[i].flag)
869 printk("%s ", pcistat_tbl[i].str);
870 printk("), g2pstatus:%08lx(", g2pstatus);
871 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
872 if (g2pstatus & g2pstat_tbl[i].flag)
873 printk("%s ", g2pstat_tbl[i].str);
874 printk("), pcicstatus:%08lx(", pcicstatus);
875 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
876 if (pcicstatus & pcicstat_tbl[i].flag)
877 printk("%s ", pcicstat_tbl[i].str);
878 printk(")\n");
879}
880
881void tx4938_report_pcic_status(void)
882{
883 int i;
884 struct tx4938_pcic_reg *pcicptr;
885 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
886 tx4938_report_pcic_status1(pcicptr);
887}
888
889#endif /* CONFIG_PCI */
890
891/* We use onchip r4k counter or TMR timer as our system wide timer
892 * interrupt running at 100HZ. */
893
894extern void __init rtc_rx5c348_init(int chipid);
895void __init rbtx4938_time_init(void)
896{
897 rtc_rx5c348_init(RBTX4938_SRTC_CHIPID);
898 mips_hpt_frequency = txx9_cpu_clock / 2;
899}
900
901void __init toshiba_rbtx4938_setup(void)
902{
903 unsigned long long pcfg;
904 char *argptr;
905
906 iomem_resource.end = 0xffffffff; /* 4GB */
907
908 if (txx9_master_clock == 0)
909 txx9_master_clock = 25000000; /* 25MHz */
910 tx4938_board_setup();
911 /* setup irq stuff */
912 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000000); /* irq trigger */
913 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM1), 0x00000000); /* irq trigger */
914 /* setup serial stuff */
915 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
916 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
917
918#ifndef CONFIG_PCI
919 set_io_port_base(RBTX4938_ETHER_BASE);
920#endif
921
922#ifdef CONFIG_SERIAL_TXX9
923 {
924 extern int early_serial_txx9_setup(struct uart_port *port);
925 int i;
926 struct uart_port req;
927 for(i = 0; i < 2; i++) {
928 memset(&req, 0, sizeof(req));
929 req.line = i;
930 req.iotype = UPIO_MEM;
931 req.membase = (char *)(0xff1ff300 + i * 0x100);
932 req.mapbase = 0xff1ff300 + i * 0x100;
933 req.irq = 32 + i;
934 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
935 req.uartclk = 50000000;
936 early_serial_txx9_setup(&req);
937 }
938 }
939#ifdef CONFIG_SERIAL_TXX9_CONSOLE
940 argptr = prom_getcmdline();
941 if (strstr(argptr, "console=") == NULL) {
942 strcat(argptr, " console=ttyS0,38400");
943 }
944#endif
945#endif
946
947#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
948 printk("PIOSEL: disabling both ata and nand selection\n");
949 local_irq_disable();
950 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
951#endif
952
953#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
954 printk("PIOSEL: enabling nand selection\n");
955 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL;
956 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL;
957#endif
958
959#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
960 printk("PIOSEL: enabling ata selection\n");
961 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL;
962 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL;
963#endif
964
965#ifdef CONFIG_IP_PNP
966 argptr = prom_getcmdline();
967 if (strstr(argptr, "ip=") == NULL) {
968 strcat(argptr, " ip=any");
969 }
970#endif
971
972
973#ifdef CONFIG_FB
974 {
975 conswitchp = &dummy_con;
976 }
977#endif
978
979 rbtx4938_spi_setup();
980 pcfg = tx4938_ccfgptr->pcfg; /* updated */
981 /* fixup piosel */
982 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
983 TX4938_PCFG_ATA_SEL) {
984 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
985 }
986 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
987 TX4938_PCFG_NDF_SEL) {
988 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
989 }
990 else {
991 *rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
992 }
993
994 rbtx4938_fpga_resource.name = "FPGA Registers";
995 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
996 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
997 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
998 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
999 printk("request resource for fpga failed\n");
1000
1001 /* disable all OnBoard I/O interrupts */
1002 *rbtx4938_imask_ptr = 0;
1003
1004 _machine_restart = rbtx4938_machine_restart;
1005 _machine_halt = rbtx4938_machine_halt;
1006 _machine_power_off = rbtx4938_machine_power_off;
1007
1008 *rbtx4938_led_ptr = 0xff;
1009 printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
1010 printk(" DIPSW:%02x,%02x\n",
1011 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
1012}
1013
1014#ifdef CONFIG_PROC_FS
1015extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid);
1016static int __init tx4938_spi_proc_setup(void)
1017{
1018 struct proc_dir_entry *tx4938_spi_eeprom_dir;
1019
1020 tx4938_spi_eeprom_dir = proc_mkdir("spi_eeprom", 0);
1021
1022 if (!tx4938_spi_eeprom_dir)
1023 return -ENOMEM;
1024
1025 /* don't allow user access to RBTX4938_SEEPROM1_CHIPID
1026 * as it contains eth0 and eth1 MAC addresses
1027 */
1028 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM2_CHIPID);
1029 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM3_CHIPID);
1030
1031 return 0;
1032}
1033
1034__initcall(tx4938_spi_proc_setup);
1035#endif
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c b/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c
new file mode 100644
index 000000000000..951a208ee9b3
--- /dev/null
+++ b/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c
@@ -0,0 +1,219 @@
1/*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/spi_eeprom.c
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/config.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/proc_fs.h>
16#include <linux/spinlock.h>
17#include <asm/tx4938/spi.h>
18#include <asm/tx4938/tx4938.h>
19
20/* ATMEL 250x0 instructions */
21#define ATMEL_WREN 0x06
22#define ATMEL_WRDI 0x04
23#define ATMEL_RDSR 0x05
24#define ATMEL_WRSR 0x01
25#define ATMEL_READ 0x03
26#define ATMEL_WRITE 0x02
27
28#define ATMEL_SR_BSY 0x01
29#define ATMEL_SR_WEN 0x02
30#define ATMEL_SR_BP0 0x04
31#define ATMEL_SR_BP1 0x08
32
33DEFINE_SPINLOCK(spi_eeprom_lock);
34
35static struct spi_dev_desc seeprom_dev_desc = {
36 .baud = 1500000, /* 1.5Mbps */
37 .tcss = 1,
38 .tcsh = 1,
39 .tcsr = 1,
40 .byteorder = 1, /* MSB-First */
41 .polarity = 0, /* High-Active */
42 .phase = 0, /* Sample-Then-Shift */
43
44};
45static inline int
46spi_eeprom_io(int chipid,
47 unsigned char **inbufs, unsigned int *incounts,
48 unsigned char **outbufs, unsigned int *outcounts)
49{
50 return txx9_spi_io(chipid, &seeprom_dev_desc,
51 inbufs, incounts, outbufs, outcounts, 0);
52}
53
54int spi_eeprom_write_enable(int chipid, int enable)
55{
56 unsigned char inbuf[1];
57 unsigned char *inbufs[1];
58 unsigned int incounts[2];
59 unsigned long flags;
60 int stat;
61 inbuf[0] = enable ? ATMEL_WREN : ATMEL_WRDI;
62 inbufs[0] = inbuf;
63 incounts[0] = sizeof(inbuf);
64 incounts[1] = 0;
65 spin_lock_irqsave(&spi_eeprom_lock, flags);
66 stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL);
67 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
68 return stat;
69}
70
71static int spi_eeprom_read_status_nolock(int chipid)
72{
73 unsigned char inbuf[2], outbuf[2];
74 unsigned char *inbufs[1], *outbufs[1];
75 unsigned int incounts[2], outcounts[2];
76 int stat;
77 inbuf[0] = ATMEL_RDSR;
78 inbuf[1] = 0;
79 inbufs[0] = inbuf;
80 incounts[0] = sizeof(inbuf);
81 incounts[1] = 0;
82 outbufs[0] = outbuf;
83 outcounts[0] = sizeof(outbuf);
84 outcounts[1] = 0;
85 stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts);
86 if (stat < 0)
87 return stat;
88 return outbuf[1];
89}
90
91int spi_eeprom_read_status(int chipid)
92{
93 unsigned long flags;
94 int stat;
95 spin_lock_irqsave(&spi_eeprom_lock, flags);
96 stat = spi_eeprom_read_status_nolock(chipid);
97 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
98 return stat;
99}
100
101int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len)
102{
103 unsigned char inbuf[2];
104 unsigned char *inbufs[2], *outbufs[2];
105 unsigned int incounts[2], outcounts[3];
106 unsigned long flags;
107 int stat;
108 inbuf[0] = ATMEL_READ;
109 inbuf[1] = address;
110 inbufs[0] = inbuf;
111 inbufs[1] = NULL;
112 incounts[0] = sizeof(inbuf);
113 incounts[1] = 0;
114 outbufs[0] = NULL;
115 outbufs[1] = buf;
116 outcounts[0] = 2;
117 outcounts[1] = len;
118 outcounts[2] = 0;
119 spin_lock_irqsave(&spi_eeprom_lock, flags);
120 stat = spi_eeprom_io(chipid, inbufs, incounts, outbufs, outcounts);
121 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
122 return stat;
123}
124
125int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len)
126{
127 unsigned char inbuf[2];
128 unsigned char *inbufs[2];
129 unsigned int incounts[3];
130 unsigned long flags;
131 int i, stat;
132
133 if (address / 8 != (address + len - 1) / 8)
134 return -EINVAL;
135 stat = spi_eeprom_write_enable(chipid, 1);
136 if (stat < 0)
137 return stat;
138 stat = spi_eeprom_read_status(chipid);
139 if (stat < 0)
140 return stat;
141 if (!(stat & ATMEL_SR_WEN))
142 return -EPERM;
143
144 inbuf[0] = ATMEL_WRITE;
145 inbuf[1] = address;
146 inbufs[0] = inbuf;
147 inbufs[1] = buf;
148 incounts[0] = sizeof(inbuf);
149 incounts[1] = len;
150 incounts[2] = 0;
151 spin_lock_irqsave(&spi_eeprom_lock, flags);
152 stat = spi_eeprom_io(chipid, inbufs, incounts, NULL, NULL);
153 if (stat < 0)
154 goto unlock_return;
155
156 /* write start. max 10ms */
157 for (i = 10; i > 0; i--) {
158 int stat = spi_eeprom_read_status_nolock(chipid);
159 if (stat < 0)
160 goto unlock_return;
161 if (!(stat & ATMEL_SR_BSY))
162 break;
163 mdelay(1);
164 }
165 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
166 if (i == 0)
167 return -EIO;
168 return len;
169 unlock_return:
170 spin_unlock_irqrestore(&spi_eeprom_lock, flags);
171 return stat;
172}
173
174#ifdef CONFIG_PROC_FS
175#define MAX_SIZE 0x80 /* for ATMEL 25010 */
176static int spi_eeprom_read_proc(char *page, char **start, off_t off,
177 int count, int *eof, void *data)
178{
179 unsigned int size = MAX_SIZE;
180 if (spi_eeprom_read((int)data, 0, (unsigned char *)page, size) < 0)
181 size = 0;
182 return size;
183}
184
185static int spi_eeprom_write_proc(struct file *file, const char *buffer,
186 unsigned long count, void *data)
187{
188 unsigned int size = MAX_SIZE;
189 int i;
190 if (file->f_pos >= size)
191 return -EIO;
192 if (file->f_pos + count > size)
193 count = size - file->f_pos;
194 for (i = 0; i < count; i += 8) {
195 int len = count - i < 8 ? count - i : 8;
196 if (spi_eeprom_write((int)data, file->f_pos,
197 (unsigned char *)buffer, len) < 0) {
198 count = -EIO;
199 break;
200 }
201 buffer += len;
202 file->f_pos += len;
203 }
204 return count;
205}
206
207__init void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid)
208{
209 struct proc_dir_entry *entry;
210 char name[128];
211 sprintf(name, "seeprom-%d", chipid);
212 entry = create_proc_entry(name, 0600, dir);
213 if (entry) {
214 entry->read_proc = spi_eeprom_read_proc;
215 entry->write_proc = spi_eeprom_write_proc;
216 entry->data = (void *)chipid;
217 }
218}
219#endif /* CONFIG_PROC_FS */
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c b/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
new file mode 100644
index 000000000000..fae3136f462d
--- /dev/null
+++ b/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
@@ -0,0 +1,159 @@
1/*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/errno.h>
15#include <linux/interrupt.h>
16#include <linux/module.h>
17#include <linux/sched.h>
18#include <linux/spinlock.h>
19#include <linux/wait.h>
20#include <asm/tx4938/spi.h>
21#include <asm/tx4938/tx4938.h>
22
23static int (*txx9_spi_cs_func)(int chipid, int on);
24static DEFINE_SPINLOCK(txx9_spi_lock);
25
26extern unsigned int txx9_gbus_clock;
27
28#define SPI_FIFO_SIZE 4
29
30void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on))
31{
32 txx9_spi_cs_func = cs_func;
33 /* enter config mode */
34 tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
35}
36
37static DECLARE_WAIT_QUEUE_HEAD(txx9_spi_wait);
38static void txx9_spi_interrupt(int irq, void *dev_id, struct pt_regs *regs)
39{
40 /* disable rx intr */
41 tx4938_spiptr->cr0 &= ~TXx9_SPCR0_RBSIE;
42 wake_up(&txx9_spi_wait);
43}
44static struct irqaction txx9_spi_action = {
45 txx9_spi_interrupt, 0, 0, "spi", NULL, NULL,
46};
47
48void __init txx9_spi_irqinit(int irc_irq)
49{
50 setup_irq(irc_irq, &txx9_spi_action);
51}
52
53int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
54 unsigned char **inbufs, unsigned int *incounts,
55 unsigned char **outbufs, unsigned int *outcounts,
56 int cansleep)
57{
58 unsigned int incount, outcount;
59 unsigned char *inp, *outp;
60 int ret;
61 unsigned long flags;
62
63 spin_lock_irqsave(&txx9_spi_lock, flags);
64 if ((tx4938_spiptr->mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE) {
65 spin_unlock_irqrestore(&txx9_spi_lock, flags);
66 return -EBUSY;
67 }
68 /* enter config mode */
69 tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
70 tx4938_spiptr->cr0 =
71 (desc->byteorder ? TXx9_SPCR0_SBOS : 0) |
72 (desc->polarity ? TXx9_SPCR0_SPOL : 0) |
73 (desc->phase ? TXx9_SPCR0_SPHA : 0) |
74 0x08;
75 tx4938_spiptr->cr1 =
76 (((TXX9_IMCLK + desc->baud) / (2 * desc->baud) - 1) << 8) |
77 0x08 /* 8 bit only */;
78 /* enter active mode */
79 tx4938_spiptr->mcr = TXx9_SPMCR_ACTIVE;
80 spin_unlock_irqrestore(&txx9_spi_lock, flags);
81
82 /* CS ON */
83 if ((ret = txx9_spi_cs_func(chipid, 1)) < 0) {
84 spin_unlock_irqrestore(&txx9_spi_lock, flags);
85 return ret;
86 }
87 udelay(desc->tcss);
88
89 /* do scatter IO */
90 inp = inbufs ? *inbufs : NULL;
91 outp = outbufs ? *outbufs : NULL;
92 incount = 0;
93 outcount = 0;
94 while (1) {
95 unsigned char data;
96 unsigned int count;
97 int i;
98 if (!incount) {
99 incount = incounts ? *incounts++ : 0;
100 inp = (incount && inbufs) ? *inbufs++ : NULL;
101 }
102 if (!outcount) {
103 outcount = outcounts ? *outcounts++ : 0;
104 outp = (outcount && outbufs) ? *outbufs++ : NULL;
105 }
106 if (!inp && !outp)
107 break;
108 count = SPI_FIFO_SIZE;
109 if (incount)
110 count = min(count, incount);
111 if (outcount)
112 count = min(count, outcount);
113
114 /* now tx must be idle... */
115 while (!(tx4938_spiptr->sr & TXx9_SPSR_SIDLE))
116 ;
117
118 tx4938_spiptr->cr0 =
119 (tx4938_spiptr->cr0 & ~TXx9_SPCR0_RXIFL_MASK) |
120 ((count - 1) << 12);
121 if (cansleep) {
122 /* enable rx intr */
123 tx4938_spiptr->cr0 |= TXx9_SPCR0_RBSIE;
124 }
125 /* send */
126 for (i = 0; i < count; i++)
127 tx4938_spiptr->dr = inp ? *inp++ : 0;
128 /* wait all rx data */
129 if (cansleep) {
130 wait_event(txx9_spi_wait,
131 tx4938_spiptr->sr & TXx9_SPSR_SRRDY);
132 } else {
133 while (!(tx4938_spiptr->sr & TXx9_SPSR_RBSI))
134 ;
135 }
136 /* receive */
137 for (i = 0; i < count; i++) {
138 data = tx4938_spiptr->dr;
139 if (outp)
140 *outp++ = data;
141 }
142 if (incount)
143 incount -= count;
144 if (outcount)
145 outcount -= count;
146 }
147
148 /* CS OFF */
149 udelay(desc->tcsh);
150 txx9_spi_cs_func(chipid, 0);
151 udelay(desc->tcsr);
152
153 spin_lock_irqsave(&txx9_spi_lock, flags);
154 /* enter config mode */
155 tx4938_spiptr->mcr = TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR;
156 spin_unlock_irqrestore(&txx9_spi_lock, flags);
157
158 return 0;
159}
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index 3870a76efc3b..14fc88f27226 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -161,6 +161,7 @@
161#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */ 161#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */
162#define MACH_TOSHIBA_RBTX4927 4 162#define MACH_TOSHIBA_RBTX4927 4
163#define MACH_TOSHIBA_RBTX4937 5 163#define MACH_TOSHIBA_RBTX4937 5
164#define MACH_TOSHIBA_RBTX4938 6
164 165
165#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \ 166#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \
166 "RBTX4927", "RBTX4937" } 167 "RBTX4927", "RBTX4937" }
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
new file mode 100644
index 000000000000..0fbedafdcea8
--- /dev/null
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -0,0 +1,207 @@
1/*
2 * linux/include/asm-mips/tx4938/rbtx4938.h
3 * Definitions for TX4937/TX4938
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#ifndef __ASM_TX_BOARDS_RBTX4938_H
13#define __ASM_TX_BOARDS_RBTX4938_H
14
15#include <asm/addrspace.h>
16#include <asm/tx4938/tx4938.h>
17
18/* CS */
19#define RBTX4938_CE0 0x1c000000 /* 64M */
20#define RBTX4938_CE2 0x17f00000 /* 1M */
21
22/* Address map */
23#define RBTX4938_FPGA_REG_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000000)
24#define RBTX4938_FPGA_REV_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000002)
25#define RBTX4938_CONFIG1_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000004)
26#define RBTX4938_CONFIG2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000006)
27#define RBTX4938_CONFIG3_ADDR (KSEG1 + RBTX4938_CE2 + 0x00000008)
28#define RBTX4938_LED_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001000)
29#define RBTX4938_DIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001002)
30#define RBTX4938_BDIPSW_ADDR (KSEG1 + RBTX4938_CE2 + 0x00001004)
31#define RBTX4938_IMASK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002000)
32#define RBTX4938_IMASK2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002002)
33#define RBTX4938_INTPOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002004)
34#define RBTX4938_ISTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002006)
35#define RBTX4938_ISTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x00002008)
36#define RBTX4938_IMSTAT_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200a)
37#define RBTX4938_IMSTAT2_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000200c)
38#define RBTX4938_SOFTINT_ADDR (KSEG1 + RBTX4938_CE2 + 0x00003000)
39#define RBTX4938_PIOSEL_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005000)
40#define RBTX4938_SPICS_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005002)
41#define RBTX4938_SFPWR_ADDR (KSEG1 + RBTX4938_CE2 + 0x00005008)
42#define RBTX4938_SFVOL_ADDR (KSEG1 + RBTX4938_CE2 + 0x0000500a)
43#define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000)
44#define RBTX4938_SOFTRESETLOCK_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007002)
45#define RBTX4938_PCIRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007004)
46#define RBTX4938_ETHER_BASE (KSEG1 + RBTX4938_CE2 + 0x00020000)
47
48/* Ethernet port address (Jumperless Mode (W12:Open)) */
49#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
50
51/* bits for ISTAT/IMASK/IMSTAT */
52#define RBTX4938_INTB_PCID 0
53#define RBTX4938_INTB_PCIC 1
54#define RBTX4938_INTB_PCIB 2
55#define RBTX4938_INTB_PCIA 3
56#define RBTX4938_INTB_RTC 4
57#define RBTX4938_INTB_ATA 5
58#define RBTX4938_INTB_MODEM 6
59#define RBTX4938_INTB_SWINT 7
60#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID)
61#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC)
62#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB)
63#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA)
64#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC)
65#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA)
66#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
67#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
68
69#define rbtx4938_fpga_rev_ptr \
70 ((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR)
71#define rbtx4938_led_ptr \
72 ((volatile unsigned char *)RBTX4938_LED_ADDR)
73#define rbtx4938_dipsw_ptr \
74 ((volatile unsigned char *)RBTX4938_DIPSW_ADDR)
75#define rbtx4938_bdipsw_ptr \
76 ((volatile unsigned char *)RBTX4938_BDIPSW_ADDR)
77#define rbtx4938_imask_ptr \
78 ((volatile unsigned char *)RBTX4938_IMASK_ADDR)
79#define rbtx4938_imask2_ptr \
80 ((volatile unsigned char *)RBTX4938_IMASK2_ADDR)
81#define rbtx4938_intpol_ptr \
82 ((volatile unsigned char *)RBTX4938_INTPOL_ADDR)
83#define rbtx4938_istat_ptr \
84 ((volatile unsigned char *)RBTX4938_ISTAT_ADDR)
85#define rbtx4938_istat2_ptr \
86 ((volatile unsigned char *)RBTX4938_ISTAT2_ADDR)
87#define rbtx4938_imstat_ptr \
88 ((volatile unsigned char *)RBTX4938_IMSTAT_ADDR)
89#define rbtx4938_imstat2_ptr \
90 ((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR)
91#define rbtx4938_softint_ptr \
92 ((volatile unsigned char *)RBTX4938_SOFTINT_ADDR)
93#define rbtx4938_piosel_ptr \
94 ((volatile unsigned char *)RBTX4938_PIOSEL_ADDR)
95#define rbtx4938_spics_ptr \
96 ((volatile unsigned char *)RBTX4938_SPICS_ADDR)
97#define rbtx4938_sfpwr_ptr \
98 ((volatile unsigned char *)RBTX4938_SFPWR_ADDR)
99#define rbtx4938_sfvol_ptr \
100 ((volatile unsigned char *)RBTX4938_SFVOL_ADDR)
101#define rbtx4938_softreset_ptr \
102 ((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR)
103#define rbtx4938_softresetlock_ptr \
104 ((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR)
105#define rbtx4938_pcireset_ptr \
106 ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
107
108/* SPI */
109#define RBTX4938_SEEPROM1_CHIPID 0
110#define RBTX4938_SEEPROM2_CHIPID 1
111#define RBTX4938_SEEPROM3_CHIPID 2
112#define RBTX4938_SRTC_CHIPID 3
113
114/*
115 * IRQ mappings
116 */
117
118#define RBTX4938_SOFT_INT0 0 /* not used */
119#define RBTX4938_SOFT_INT1 1 /* not used */
120#define RBTX4938_IRC_INT 2
121#define RBTX4938_TIMER_INT 7
122
123/* These are the virtual IRQ numbers, we divide all IRQ's into
124 * 'spaces', the 'space' determines where and how to enable/disable
125 * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
126 * IRQ hardware is supported.
127 */
128#define RBTX4938_NR_IRQ_LOCAL 8
129#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */
130#define RBTX4938_NR_IRQ_IOC 8
131
132#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */
133#define MI8259_IRQ_ISA_RAW_END 15
134#define TX4938_IRQ_CP0_RAW_BEG 0 /* tx4938 cpu built-in cp0 */
135#define TX4938_IRQ_CP0_RAW_END 7
136#define TX4938_IRQ_PIC_RAW_BEG 0 /* tx4938 cpu build-in pic */
137#define TX4938_IRQ_PIC_RAW_END 31
138
139#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */
140#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */
141
142#define TX4938_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG) /* 16 */
143#define TX4938_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END) /* 23 */
144
145#define TX4938_IRQ_PIC_BEG ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG) /* 24 */
146#define TX4938_IRQ_PIC_END ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END) /* 55 */
147#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2)
148#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2)
149#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0)
150#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1)
151#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7)
152
153#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0
154#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7
155
156#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */
157#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */
158#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG
159#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL)
160#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC)
161#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
162
163#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0)
164#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1)
165#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT)
166#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT)
167#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
168#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
169#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
170#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
171#define RBTX4938_IRQ_IRC_DMA(ch,n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n))
172#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
173#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
174#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
175#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
176#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
177#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
178#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
179#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
180#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
181#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
182#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
183#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
184#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
185#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
186#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
187#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
188#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
189#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
190#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
191
192
193/* IOC (PCI, etc) */
194#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC)
195/* Onboard 10M Ether */
196#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1)
197
198#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
199#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
200
201/* IRCR : Int. Control */
202#define TX4938_IRCR_LOW 0x00000000
203#define TX4938_IRCR_HIGH 0x00000001
204#define TX4938_IRCR_DOWN 0x00000002
205#define TX4938_IRCR_UP 0x00000003
206
207#endif /* __ASM_TX_BOARDS_RBTX4938_H */
diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h
new file mode 100644
index 000000000000..0dbbab820a5a
--- /dev/null
+++ b/include/asm-mips/tx4938/spi.h
@@ -0,0 +1,74 @@
1/*
2 * linux/include/asm-mips/tx4938/spi.h
3 * Definitions for TX4937/TX4938 SPI
4 *
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14#ifndef __ASM_TX_BOARDS_TX4938_SPI_H
15#define __ASM_TX_BOARDS_TX4938_SPI_H
16
17/* SPI */
18struct spi_dev_desc {
19 unsigned int baud;
20 unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */
21 unsigned int byteorder:1; /* 0:LSB-First, 1:MSB-First */
22 unsigned int polarity:1; /* 0:High-Active */
23 unsigned int phase:1; /* 0:Sample-Then-Shift */
24};
25
26extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init;
27extern void txx9_spi_irqinit(int irc_irq) __init;
28extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
29 unsigned char **inbufs, unsigned int *incounts,
30 unsigned char **outbufs, unsigned int *outcounts,
31 int cansleep);
32extern int spi_eeprom_write_enable(int chipid, int enable);
33extern int spi_eeprom_read_status(int chipid);
34extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
35extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len);
36extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init;
37
38#define TXX9_IMCLK (txx9_gbus_clock / 2)
39
40/*
41* SPI
42*/
43
44/* SPMCR : SPI Master Control */
45#define TXx9_SPMCR_OPMODE 0xc0
46#define TXx9_SPMCR_CONFIG 0x40
47#define TXx9_SPMCR_ACTIVE 0x80
48#define TXx9_SPMCR_SPSTP 0x02
49#define TXx9_SPMCR_BCLR 0x01
50
51/* SPCR0 : SPI Status */
52#define TXx9_SPCR0_TXIFL_MASK 0xc000
53#define TXx9_SPCR0_RXIFL_MASK 0x3000
54#define TXx9_SPCR0_SIDIE 0x0800
55#define TXx9_SPCR0_SOEIE 0x0400
56#define TXx9_SPCR0_RBSIE 0x0200
57#define TXx9_SPCR0_TBSIE 0x0100
58#define TXx9_SPCR0_IFSPSE 0x0010
59#define TXx9_SPCR0_SBOS 0x0004
60#define TXx9_SPCR0_SPHA 0x0002
61#define TXx9_SPCR0_SPOL 0x0001
62
63/* SPSR : SPI Status */
64#define TXx9_SPSR_TBSI 0x8000
65#define TXx9_SPSR_RBSI 0x4000
66#define TXx9_SPSR_TBS_MASK 0x3800
67#define TXx9_SPSR_RBS_MASK 0x0700
68#define TXx9_SPSR_SPOE 0x0080
69#define TXx9_SPSR_IFSD 0x0008
70#define TXx9_SPSR_SIDLE 0x0004
71#define TXx9_SPSR_STRDY 0x0002
72#define TXx9_SPSR_SRRDY 0x0001
73
74#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
new file mode 100644
index 000000000000..e25b1a0975cb
--- /dev/null
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -0,0 +1,706 @@
1/*
2 * linux/include/asm-mips/tx4938/tx4938.h
3 * Definitions for TX4937/TX4938
4 * Copyright (C) 2000-2001 Toshiba Corporation
5 *
6 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
7 * terms of the GNU General Public License version 2. This program is
8 * licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
12 */
13#ifndef __ASM_TX_BOARDS_TX4938_H
14#define __ASM_TX_BOARDS_TX4938_H
15
16#include <asm/tx4938/tx4938_mips.h>
17
18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
19#define tx4938_write_nfmc(b,addr) (*(volatile unsigned int *)(addr)) = (b)
20
21#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG
22
23#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC)
24#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR)
25
26#define TX4938_PCIIO_0 0x10000000
27#define TX4938_PCIIO_1 0x01010000
28#define TX4938_PCIMEM_0 0x08000000
29#define TX4938_PCIMEM_1 0x11000000
30
31#define TX4938_PCIIO_SIZE_0 0x01000000
32#define TX4938_PCIIO_SIZE_1 0x00010000
33#define TX4938_PCIMEM_SIZE_0 0x08000000
34#define TX4938_PCIMEM_SIZE_1 0x00010000
35
36#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
37#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
38
39/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
40#define TX4938_NDFMC_REG (TX4938_REG_BASE + 0x5000)
41#define TX4938_SRAMC_REG (TX4938_REG_BASE + 0x6000)
42#define TX4938_PCIC1_REG (TX4938_REG_BASE + 0x7000)
43#define TX4938_SDRAMC_REG (TX4938_REG_BASE + 0x8000)
44#define TX4938_EBUSC_REG (TX4938_REG_BASE + 0x9000)
45#define TX4938_DMA_REG(ch) (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
46#define TX4938_PCIC_REG (TX4938_REG_BASE + 0xd000)
47#define TX4938_CCFG_REG (TX4938_REG_BASE + 0xe000)
48#define TX4938_NR_TMR 3
49#define TX4938_TMR_REG(ch) ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
50#define TX4938_NR_SIO 2
51#define TX4938_SIO_REG(ch) ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
52#define TX4938_PIO_REG (TX4938_REG_BASE + 0xf500)
53#define TX4938_IRC_REG (TX4938_REG_BASE + 0xf600)
54#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
55#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
56
57#ifndef _LANGUAGE_ASSEMBLY
58#include <asm/byteorder.h>
59
60#define TX4938_MKA(x) ((u32)( ((u32)(TX4938_REG_BASE)) | ((u32)(x)) ))
61
62#define TX4938_RD08( reg ) (*(vu08*)(reg))
63#define TX4938_WR08( reg, val ) ((*(vu08*)(reg))=(val))
64
65#define TX4938_RD16( reg ) (*(vu16*)(reg))
66#define TX4938_WR16( reg, val ) ((*(vu16*)(reg))=(val))
67
68#define TX4938_RD32( reg ) (*(vu32*)(reg))
69#define TX4938_WR32( reg, val ) ((*(vu32*)(reg))=(val))
70
71#define TX4938_RD64( reg ) (*(vu64*)(reg))
72#define TX4938_WR64( reg, val ) ((*(vu64*)(reg))=(val))
73
74#define TX4938_RD( reg ) TX4938_RD32( reg )
75#define TX4938_WR( reg, val ) TX4938_WR32( reg, val )
76
77#endif /* !__ASSEMBLY__ */
78
79#ifdef __ASSEMBLY__
80#define _CONST64(c) c
81#else
82#define _CONST64(c) c##ull
83
84#include <asm/byteorder.h>
85
86#ifdef __BIG_ENDIAN
87#define endian_def_l2(e1,e2) \
88 volatile unsigned long e1,e2
89#define endian_def_s2(e1,e2) \
90 volatile unsigned short e1,e2
91#define endian_def_sb2(e1,e2,e3) \
92 volatile unsigned short e1;volatile unsigned char e2,e3
93#define endian_def_b2s(e1,e2,e3) \
94 volatile unsigned char e1,e2;volatile unsigned short e3
95#define endian_def_b4(e1,e2,e3,e4) \
96 volatile unsigned char e1,e2,e3,e4
97#else
98#define endian_def_l2(e1,e2) \
99 volatile unsigned long e2,e1
100#define endian_def_s2(e1,e2) \
101 volatile unsigned short e2,e1
102#define endian_def_sb2(e1,e2,e3) \
103 volatile unsigned char e3,e2;volatile unsigned short e1
104#define endian_def_b2s(e1,e2,e3) \
105 volatile unsigned short e3;volatile unsigned char e2,e1
106#define endian_def_b4(e1,e2,e3,e4) \
107 volatile unsigned char e4,e3,e2,e1
108#endif
109
110
111struct tx4938_sdramc_reg {
112 volatile unsigned long long cr[4];
113 volatile unsigned long long unused0[4];
114 volatile unsigned long long tr;
115 volatile unsigned long long unused1[2];
116 volatile unsigned long long cmd;
117 volatile unsigned long long sfcmd;
118};
119
120struct tx4938_ebusc_reg {
121 volatile unsigned long long cr[8];
122};
123
124struct tx4938_dma_reg {
125 struct tx4938_dma_ch_reg {
126 volatile unsigned long long cha;
127 volatile unsigned long long sar;
128 volatile unsigned long long dar;
129 endian_def_l2(unused0, cntr);
130 endian_def_l2(unused1, sair);
131 endian_def_l2(unused2, dair);
132 endian_def_l2(unused3, ccr);
133 endian_def_l2(unused4, csr);
134 } ch[4];
135 volatile unsigned long long dbr[8];
136 volatile unsigned long long tdhr;
137 volatile unsigned long long midr;
138 endian_def_l2(unused0, mcr);
139};
140
141struct tx4938_pcic_reg {
142 volatile unsigned long pciid;
143 volatile unsigned long pcistatus;
144 volatile unsigned long pciccrev;
145 volatile unsigned long pcicfg1;
146 volatile unsigned long p2gm0plbase; /* +10 */
147 volatile unsigned long p2gm0pubase;
148 volatile unsigned long p2gm1plbase;
149 volatile unsigned long p2gm1pubase;
150 volatile unsigned long p2gm2pbase; /* +20 */
151 volatile unsigned long p2giopbase;
152 volatile unsigned long unused0;
153 volatile unsigned long pcisid;
154 volatile unsigned long unused1; /* +30 */
155 volatile unsigned long pcicapptr;
156 volatile unsigned long unused2;
157 volatile unsigned long pcicfg2;
158 volatile unsigned long g2ptocnt; /* +40 */
159 volatile unsigned long unused3[15];
160 volatile unsigned long g2pstatus; /* +80 */
161 volatile unsigned long g2pmask;
162 volatile unsigned long pcisstatus;
163 volatile unsigned long pcimask;
164 volatile unsigned long p2gcfg; /* +90 */
165 volatile unsigned long p2gstatus;
166 volatile unsigned long p2gmask;
167 volatile unsigned long p2gccmd;
168 volatile unsigned long unused4[24]; /* +a0 */
169 volatile unsigned long pbareqport; /* +100 */
170 volatile unsigned long pbacfg;
171 volatile unsigned long pbastatus;
172 volatile unsigned long pbamask;
173 volatile unsigned long pbabm; /* +110 */
174 volatile unsigned long pbacreq;
175 volatile unsigned long pbacgnt;
176 volatile unsigned long pbacstate;
177 volatile unsigned long long g2pmgbase[3]; /* +120 */
178 volatile unsigned long long g2piogbase;
179 volatile unsigned long g2pmmask[3]; /* +140 */
180 volatile unsigned long g2piomask;
181 volatile unsigned long long g2pmpbase[3]; /* +150 */
182 volatile unsigned long long g2piopbase;
183 volatile unsigned long pciccfg; /* +170 */
184 volatile unsigned long pcicstatus;
185 volatile unsigned long pcicmask;
186 volatile unsigned long unused5;
187 volatile unsigned long long p2gmgbase[3]; /* +180 */
188 volatile unsigned long long p2giogbase;
189 volatile unsigned long g2pcfgadrs; /* +1a0 */
190 volatile unsigned long g2pcfgdata;
191 volatile unsigned long unused6[8];
192 volatile unsigned long g2pintack;
193 volatile unsigned long g2pspc;
194 volatile unsigned long unused7[12]; /* +1d0 */
195 volatile unsigned long long pdmca; /* +200 */
196 volatile unsigned long long pdmga;
197 volatile unsigned long long pdmpa;
198 volatile unsigned long long pdmctr;
199 volatile unsigned long long pdmcfg; /* +220 */
200 volatile unsigned long long pdmsts;
201};
202
203struct tx4938_aclc_reg {
204 volatile unsigned long acctlen;
205 volatile unsigned long acctldis;
206 volatile unsigned long acregacc;
207 volatile unsigned long unused0;
208 volatile unsigned long acintsts;
209 volatile unsigned long acintmsts;
210 volatile unsigned long acinten;
211 volatile unsigned long acintdis;
212 volatile unsigned long acsemaph;
213 volatile unsigned long unused1[7];
214 volatile unsigned long acgpidat;
215 volatile unsigned long acgpodat;
216 volatile unsigned long acslten;
217 volatile unsigned long acsltdis;
218 volatile unsigned long acfifosts;
219 volatile unsigned long unused2[11];
220 volatile unsigned long acdmasts;
221 volatile unsigned long acdmasel;
222 volatile unsigned long unused3[6];
223 volatile unsigned long acaudodat;
224 volatile unsigned long acsurrdat;
225 volatile unsigned long accentdat;
226 volatile unsigned long aclfedat;
227 volatile unsigned long acaudiat;
228 volatile unsigned long unused4;
229 volatile unsigned long acmodoat;
230 volatile unsigned long acmodidat;
231 volatile unsigned long unused5[15];
232 volatile unsigned long acrevid;
233};
234
235
236struct tx4938_tmr_reg {
237 volatile unsigned long tcr;
238 volatile unsigned long tisr;
239 volatile unsigned long cpra;
240 volatile unsigned long cprb;
241 volatile unsigned long itmr;
242 volatile unsigned long unused0[3];
243 volatile unsigned long ccdr;
244 volatile unsigned long unused1[3];
245 volatile unsigned long pgmr;
246 volatile unsigned long unused2[3];
247 volatile unsigned long wtmr;
248 volatile unsigned long unused3[43];
249 volatile unsigned long trr;
250};
251
252struct tx4938_sio_reg {
253 volatile unsigned long lcr;
254 volatile unsigned long dicr;
255 volatile unsigned long disr;
256 volatile unsigned long cisr;
257 volatile unsigned long fcr;
258 volatile unsigned long flcr;
259 volatile unsigned long bgr;
260 volatile unsigned long tfifo;
261 volatile unsigned long rfifo;
262};
263
264struct tx4938_pio_reg {
265 volatile unsigned long dout;
266 volatile unsigned long din;
267 volatile unsigned long dir;
268 volatile unsigned long od;
269 volatile unsigned long flag[2];
270 volatile unsigned long pol;
271 volatile unsigned long intc;
272 volatile unsigned long maskcpu;
273 volatile unsigned long maskext;
274};
275struct tx4938_irc_reg {
276 volatile unsigned long cer;
277 volatile unsigned long cr[2];
278 volatile unsigned long unused0;
279 volatile unsigned long ilr[8];
280 volatile unsigned long unused1[4];
281 volatile unsigned long imr;
282 volatile unsigned long unused2[7];
283 volatile unsigned long scr;
284 volatile unsigned long unused3[7];
285 volatile unsigned long ssr;
286 volatile unsigned long unused4[7];
287 volatile unsigned long csr;
288};
289
290struct tx4938_ndfmc_reg {
291 endian_def_l2(unused0, dtr);
292 endian_def_l2(unused1, mcr);
293 endian_def_l2(unused2, sr);
294 endian_def_l2(unused3, isr);
295 endian_def_l2(unused4, imr);
296 endian_def_l2(unused5, spr);
297 endian_def_l2(unused6, rstr);
298};
299
300struct tx4938_spi_reg {
301 volatile unsigned long mcr;
302 volatile unsigned long cr0;
303 volatile unsigned long cr1;
304 volatile unsigned long fs;
305 volatile unsigned long unused1;
306 volatile unsigned long sr;
307 volatile unsigned long dr;
308 volatile unsigned long unused2;
309};
310
311struct tx4938_sramc_reg {
312 volatile unsigned long long cr;
313};
314
315struct tx4938_ccfg_reg {
316 volatile unsigned long long ccfg;
317 volatile unsigned long long crir;
318 volatile unsigned long long pcfg;
319 volatile unsigned long long tear;
320 volatile unsigned long long clkctr;
321 volatile unsigned long long unused0;
322 volatile unsigned long long garbc;
323 volatile unsigned long long unused1;
324 volatile unsigned long long unused2;
325 volatile unsigned long long ramp;
326 volatile unsigned long long unused3;
327 volatile unsigned long long jmpadr;
328};
329
330#undef endian_def_l2
331#undef endian_def_s2
332#undef endian_def_sb2
333#undef endian_def_b2s
334#undef endian_def_b4
335
336#endif /* __ASSEMBLY__ */
337
338/*
339 * NDFMC
340 */
341
342/* NDFMCR : NDFMC Mode Control */
343#define TX4938_NDFMCR_WE 0x80
344#define TX4938_NDFMCR_ECC_ALL 0x60
345#define TX4938_NDFMCR_ECC_RESET 0x60
346#define TX4938_NDFMCR_ECC_READ 0x40
347#define TX4938_NDFMCR_ECC_ON 0x20
348#define TX4938_NDFMCR_ECC_OFF 0x00
349#define TX4938_NDFMCR_CE 0x10
350#define TX4938_NDFMCR_BSPRT 0x04
351#define TX4938_NDFMCR_ALE 0x02
352#define TX4938_NDFMCR_CLE 0x01
353
354/* NDFMCR : NDFMC Status */
355#define TX4938_NDFSR_BUSY 0x80
356
357/* NDFMCR : NDFMC Reset */
358#define TX4938_NDFRSTR_RST 0x01
359
360/*
361 * IRC
362 */
363
364#define TX4938_IR_ECCERR 0
365#define TX4938_IR_WTOERR 1
366#define TX4938_NUM_IR_INT 6
367#define TX4938_IR_INT(n) (2 + (n))
368#define TX4938_NUM_IR_SIO 2
369#define TX4938_IR_SIO(n) (8 + (n))
370#define TX4938_NUM_IR_DMA 4
371#define TX4938_IR_DMA(ch,n) ((ch ? 27 : 10) + (n)) /* 10-13,27-30 */
372#define TX4938_IR_PIO 14
373#define TX4938_IR_PDMAC 15
374#define TX4938_IR_PCIC 16
375#define TX4938_NUM_IR_TMR 3
376#define TX4938_IR_TMR(n) (17 + (n))
377#define TX4938_IR_NDFMC 21
378#define TX4938_IR_PCIERR 22
379#define TX4938_IR_PCIPME 23
380#define TX4938_IR_ACLC 24
381#define TX4938_IR_ACLCPME 25
382#define TX4938_IR_PCIC1 26
383#define TX4938_IR_SPI 31
384#define TX4938_NUM_IR 32
385/* multiplex */
386#define TX4938_IR_ETH0 TX4938_IR_INT(4)
387#define TX4938_IR_ETH1 TX4938_IR_INT(3)
388
389/*
390 * CCFG
391 */
392/* CCFG : Chip Configuration */
393#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000)
394#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000)
395#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000)
396#define TX4938_CCFG_TINTDIS 0x01000000
397#define TX4938_CCFG_PCI66 0x00800000
398#define TX4938_CCFG_PCIMODE 0x00400000
399#define TX4938_CCFG_PCI1_66 0x00200000
400#define TX4938_CCFG_DIVMODE_MASK 0x001e0000
401#define TX4938_CCFG_DIVMODE_2 (0x4 << 17)
402#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
403#define TX4938_CCFG_DIVMODE_3 (0x5 << 17)
404#define TX4938_CCFG_DIVMODE_4 (0x6 << 17)
405#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
406#define TX4938_CCFG_DIVMODE_8 (0x0 << 17)
407#define TX4938_CCFG_DIVMODE_10 (0xb << 17)
408#define TX4938_CCFG_DIVMODE_12 (0x1 << 17)
409#define TX4938_CCFG_DIVMODE_16 (0x2 << 17)
410#define TX4938_CCFG_DIVMODE_18 (0x9 << 17)
411#define TX4938_CCFG_BEOW 0x00010000
412#define TX4938_CCFG_WR 0x00008000
413#define TX4938_CCFG_TOE 0x00004000
414#define TX4938_CCFG_PCIXARB 0x00002000
415#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00
416#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10)
417#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10)
418#define TX4938_CCFG_PCIDIVMODE_5 (0x5 << 10)
419#define TX4938_CCFG_PCIDIVMODE_5_5 (0x7 << 10)
420#define TX4938_CCFG_PCIDIVMODE_8 (0x0 << 10)
421#define TX4938_CCFG_PCIDIVMODE_9 (0x2 << 10)
422#define TX4938_CCFG_PCIDIVMODE_10 (0x4 << 10)
423#define TX4938_CCFG_PCIDIVMODE_11 (0x6 << 10)
424#define TX4938_CCFG_PCI1DMD 0x00000100
425#define TX4938_CCFG_SYSSP_MASK 0x000000c0
426#define TX4938_CCFG_ENDIAN 0x00000004
427#define TX4938_CCFG_HALT 0x00000002
428#define TX4938_CCFG_ACEHOLD 0x00000001
429
430/* PCFG : Pin Configuration */
431#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000)
432#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000)
433#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000)
434#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000)
435#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000)
436#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000)
437#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000
438#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
439#define TX4938_PCFG_SYSCLKEN 0x08000000
440#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
441#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
442#define TX4938_PCFG_PCICLKEN_ALL 0x003f0000
443#define TX4938_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
444#define TX4938_PCFG_SEL2 0x00000200
445#define TX4938_PCFG_SEL1 0x00000100
446#define TX4938_PCFG_DMASEL_ALL 0x0000000f
447#define TX4938_PCFG_DMASEL0_DRQ0 0x00000000
448#define TX4938_PCFG_DMASEL0_SIO1 0x00000001
449#define TX4938_PCFG_DMASEL1_DRQ1 0x00000000
450#define TX4938_PCFG_DMASEL1_SIO1 0x00000002
451#define TX4938_PCFG_DMASEL2_DRQ2 0x00000000
452#define TX4938_PCFG_DMASEL2_SIO0 0x00000004
453#define TX4938_PCFG_DMASEL3_DRQ3 0x00000000
454#define TX4938_PCFG_DMASEL3_SIO0 0x00000008
455
456/* CLKCTR : Clock Control */
457#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000)
458#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000)
459#define TX4938_CLKCTR_ETH1CKD 0x80000000
460#define TX4938_CLKCTR_ETH0CKD 0x40000000
461#define TX4938_CLKCTR_SPICKD 0x20000000
462#define TX4938_CLKCTR_SRAMCKD 0x10000000
463#define TX4938_CLKCTR_PCIC1CKD 0x08000000
464#define TX4938_CLKCTR_DMA1CKD 0x04000000
465#define TX4938_CLKCTR_ACLCKD 0x02000000
466#define TX4938_CLKCTR_PIOCKD 0x01000000
467#define TX4938_CLKCTR_DMACKD 0x00800000
468#define TX4938_CLKCTR_PCICKD 0x00400000
469#define TX4938_CLKCTR_TM0CKD 0x00100000
470#define TX4938_CLKCTR_TM1CKD 0x00080000
471#define TX4938_CLKCTR_TM2CKD 0x00040000
472#define TX4938_CLKCTR_SIO0CKD 0x00020000
473#define TX4938_CLKCTR_SIO1CKD 0x00010000
474#define TX4938_CLKCTR_ETH1RST 0x00008000
475#define TX4938_CLKCTR_ETH0RST 0x00004000
476#define TX4938_CLKCTR_SPIRST 0x00002000
477#define TX4938_CLKCTR_SRAMRST 0x00001000
478#define TX4938_CLKCTR_PCIC1RST 0x00000800
479#define TX4938_CLKCTR_DMA1RST 0x00000400
480#define TX4938_CLKCTR_ACLRST 0x00000200
481#define TX4938_CLKCTR_PIORST 0x00000100
482#define TX4938_CLKCTR_DMARST 0x00000080
483#define TX4938_CLKCTR_PCIRST 0x00000040
484#define TX4938_CLKCTR_TM0RST 0x00000010
485#define TX4938_CLKCTR_TM1RST 0x00000008
486#define TX4938_CLKCTR_TM2RST 0x00000004
487#define TX4938_CLKCTR_SIO0RST 0x00000002
488#define TX4938_CLKCTR_SIO1RST 0x00000001
489
490/* bits for G2PSTATUS/G2PMASK */
491#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003
492#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002
493#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001
494
495/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
496#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900
497
498/* bits for PBACFG */
499#define TX4938_PCIC_PBACFG_FIXPA 0x00000008
500#define TX4938_PCIC_PBACFG_RPBA 0x00000004
501#define TX4938_PCIC_PBACFG_PBAEN 0x00000002
502#define TX4938_PCIC_PBACFG_BMCEN 0x00000001
503
504/* bits for G2PMnGBASE */
505#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
506#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
507
508/* bits for G2PIOGBASE */
509#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
510#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
511
512/* bits for PCICSTATUS/PCICMASK */
513#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8
514#define TX4938_PCIC_PCICSTATUS_PME 0x00000400
515#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200
516#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100
517#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080
518#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020
519#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010
520#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008
521#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002
522#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001
523
524/* bits for PCICCFG */
525#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000
526#define TX4938_PCIC_PCICCFG_HRST 0x00000800
527#define TX4938_PCIC_PCICCFG_SRST 0x00000400
528#define TX4938_PCIC_PCICCFG_IRBER 0x00000200
529#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch))
530#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100
531#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080
532#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040
533#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020
534#define TX4938_PCIC_PCICCFG_TCAR 0x00000010
535#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008
536
537/* bits for P2GMnGBASE */
538#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
539#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
540#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
541
542/* bits for P2GIOGBASE */
543#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
544#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
545#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
546
547#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
548#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32)
549
550/* bits for PDMCFG */
551#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000
552#define TX4938_PCIC_PDMCFG_EXFER 0x00100000
553#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800
554#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11)
555#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11)
556#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11)
557#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11)
558#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11)
559#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11)
560#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11)
561#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11)
562#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400
563#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200
564#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100
565#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080
566#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040
567#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020
568#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
569#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
570#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
571#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
572#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002
573#define TX4938_PCIC_PDMCFG_CHRST 0x00000001
574
575/* bits for PDMSTS */
576#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
577#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
578#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
579#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000
580#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800
581#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400
582#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200
583#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100
584#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080
585#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040
586#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020
587#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008
588#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004
589#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002
590#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001
591#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0
592#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f
593
594/*
595 * DMA
596 */
597/* bits for MCR */
598#define TX4938_DMA_MCR_EIS(ch) (0x10000000<<(ch))
599#define TX4938_DMA_MCR_DIS(ch) (0x01000000<<(ch))
600#define TX4938_DMA_MCR_RSFIF 0x00000080
601#define TX4938_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
602#define TX4938_DMA_MCR_RPRT 0x00000002
603#define TX4938_DMA_MCR_MSTEN 0x00000001
604
605/* bits for CCRn */
606#define TX4938_DMA_CCR_IMMCHN 0x20000000
607#define TX4938_DMA_CCR_USEXFSZ 0x10000000
608#define TX4938_DMA_CCR_LE 0x08000000
609#define TX4938_DMA_CCR_DBINH 0x04000000
610#define TX4938_DMA_CCR_SBINH 0x02000000
611#define TX4938_DMA_CCR_CHRST 0x01000000
612#define TX4938_DMA_CCR_RVBYTE 0x00800000
613#define TX4938_DMA_CCR_ACKPOL 0x00400000
614#define TX4938_DMA_CCR_REQPL 0x00200000
615#define TX4938_DMA_CCR_EGREQ 0x00100000
616#define TX4938_DMA_CCR_CHDN 0x00080000
617#define TX4938_DMA_CCR_DNCTL 0x00060000
618#define TX4938_DMA_CCR_EXTRQ 0x00010000
619#define TX4938_DMA_CCR_INTRQD 0x0000e000
620#define TX4938_DMA_CCR_INTENE 0x00001000
621#define TX4938_DMA_CCR_INTENC 0x00000800
622#define TX4938_DMA_CCR_INTENT 0x00000400
623#define TX4938_DMA_CCR_CHNEN 0x00000200
624#define TX4938_DMA_CCR_XFACT 0x00000100
625#define TX4938_DMA_CCR_SMPCHN 0x00000020
626#define TX4938_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
627#define TX4938_DMA_CCR_XFSZ_1W TX4938_DMA_CCR_XFSZ(2)
628#define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3)
629#define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4)
630#define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5)
631#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
632#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
633#define TX4938_DMA_CCR_MEMIO 0x00000002
634#define TX4938_DMA_CCR_SNGAD 0x00000001
635
636/* bits for CSRn */
637#define TX4938_DMA_CSR_CHNEN 0x00000400
638#define TX4938_DMA_CSR_STLXFER 0x00000200
639#define TX4938_DMA_CSR_CHNACT 0x00000100
640#define TX4938_DMA_CSR_ABCHC 0x00000080
641#define TX4938_DMA_CSR_NCHNC 0x00000040
642#define TX4938_DMA_CSR_NTRNFC 0x00000020
643#define TX4938_DMA_CSR_EXTDN 0x00000010
644#define TX4938_DMA_CSR_CFERR 0x00000008
645#define TX4938_DMA_CSR_CHERR 0x00000004
646#define TX4938_DMA_CSR_DESERR 0x00000002
647#define TX4938_DMA_CSR_SORERR 0x00000001
648
649/* TX4938 Interrupt Controller (32-bit registers) */
650#define TX4938_IRC_BASE 0xf510
651#define TX4938_IRC_IRFLAG0 0xf510
652#define TX4938_IRC_IRFLAG1 0xf514
653#define TX4938_IRC_IRPOL 0xf518
654#define TX4938_IRC_IRRCNT 0xf51c
655#define TX4938_IRC_IRMASKINT 0xf520
656#define TX4938_IRC_IRMASKEXT 0xf524
657#define TX4938_IRC_IRDEN 0xf600
658#define TX4938_IRC_IRDM0 0xf604
659#define TX4938_IRC_IRDM1 0xf608
660#define TX4938_IRC_IRLVL0 0xf610
661#define TX4938_IRC_IRLVL1 0xf614
662#define TX4938_IRC_IRLVL2 0xf618
663#define TX4938_IRC_IRLVL3 0xf61c
664#define TX4938_IRC_IRLVL4 0xf620
665#define TX4938_IRC_IRLVL5 0xf624
666#define TX4938_IRC_IRLVL6 0xf628
667#define TX4938_IRC_IRLVL7 0xf62c
668#define TX4938_IRC_IRMSK 0xf640
669#define TX4938_IRC_IREDC 0xf660
670#define TX4938_IRC_IRPND 0xf680
671#define TX4938_IRC_IRCS 0xf6a0
672#define TX4938_IRC_LIMIT 0xf6ff
673
674
675#ifndef __ASSEMBLY__
676
677#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
678#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
679#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
680#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
681#define tx4938_ircptr ((struct tx4938_irc_reg *)TX4938_IRC_REG)
682#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
683#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
684#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
685#define tx4938_tmrptr(ch) ((struct tx4938_tmr_reg *)TX4938_TMR_REG(ch))
686#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
687#define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG)
688#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
689#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG)
690#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
691
692
693#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff)
694#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16)
695
696#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
697#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
698
699#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
700#define TX4938_EBUSC_SIZE(ch) \
701 (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
702
703
704#endif /* !__ASSEMBLY__ */
705
706#endif
diff --git a/include/asm-mips/tx4938/tx4938_mips.h b/include/asm-mips/tx4938/tx4938_mips.h
new file mode 100644
index 000000000000..cf89b205f103
--- /dev/null
+++ b/include/asm-mips/tx4938/tx4938_mips.h
@@ -0,0 +1,54 @@
1/*
2 * linux/include/asm-mips/tx4938/tx4938_bitmask.h
3 * Generic bitmask definitions
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12
13#ifndef TX4938_TX4938_MIPS_H
14#define TX4938_TX4938_MIPS_H
15#ifndef __ASSEMBLY__
16
17#define reg_rd08(r) ((u8 )(*((vu8 *)(r))))
18#define reg_rd16(r) ((u16)(*((vu16*)(r))))
19#define reg_rd32(r) ((u32)(*((vu32*)(r))))
20#define reg_rd64(r) ((u64)(*((vu64*)(r))))
21
22#define reg_wr08(r,v) ((*((vu8 *)(r)))=((u8 )(v)))
23#define reg_wr16(r,v) ((*((vu16*)(r)))=((u16)(v)))
24#define reg_wr32(r,v) ((*((vu32*)(r)))=((u32)(v)))
25#define reg_wr64(r,v) ((*((vu64*)(r)))=((u64)(v)))
26
27typedef volatile __signed char vs8;
28typedef volatile unsigned char vu8;
29
30typedef volatile __signed short vs16;
31typedef volatile unsigned short vu16;
32
33typedef volatile __signed int vs32;
34typedef volatile unsigned int vu32;
35
36typedef s8 s08;
37typedef vs8 vs08;
38
39typedef u8 u08;
40typedef vu8 vu08;
41
42#if (_MIPS_SZLONG == 64)
43
44typedef volatile __signed__ long vs64;
45typedef volatile unsigned long vu64;
46
47#else
48
49typedef volatile __signed__ long long vs64;
50typedef volatile unsigned long long vu64;
51
52#endif
53#endif
54#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 20:30:27 -0500