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-rw-r--r--drivers/net/sfc/falcon_hwdefs.h40
-rw-r--r--drivers/net/sfc/falcon_xmac.c248
-rw-r--r--drivers/net/sfc/mac.h4
-rw-r--r--drivers/net/sfc/sfe4001.c7
4 files changed, 129 insertions, 170 deletions
diff --git a/drivers/net/sfc/falcon_hwdefs.h b/drivers/net/sfc/falcon_hwdefs.h
index 626735e73429..7c784f71f185 100644
--- a/drivers/net/sfc/falcon_hwdefs.h
+++ b/drivers/net/sfc/falcon_hwdefs.h
@@ -493,18 +493,8 @@
493#define MAC_MCAST_HASH_REG0_KER 0xca0 493#define MAC_MCAST_HASH_REG0_KER 0xca0
494#define MAC_MCAST_HASH_REG1_KER 0xcb0 494#define MAC_MCAST_HASH_REG1_KER 0xcb0
495 495
496/* GMAC registers */
497#define FALCON_GMAC_REGBANK 0xe00
498#define FALCON_GMAC_REGBANK_SIZE 0x200
499#define FALCON_GMAC_REG_SIZE 0x10
500
501/* XMAC registers */
502#define FALCON_XMAC_REGBANK 0x1200
503#define FALCON_XMAC_REGBANK_SIZE 0x200
504#define FALCON_XMAC_REG_SIZE 0x10
505
506/* XGMAC address register low */ 496/* XGMAC address register low */
507#define XM_ADR_LO_REG_MAC 0x00 497#define XM_ADR_LO_REG 0x1200
508#define XM_ADR_3_LBN 24 498#define XM_ADR_3_LBN 24
509#define XM_ADR_3_WIDTH 8 499#define XM_ADR_3_WIDTH 8
510#define XM_ADR_2_LBN 16 500#define XM_ADR_2_LBN 16
@@ -515,14 +505,14 @@
515#define XM_ADR_0_WIDTH 8 505#define XM_ADR_0_WIDTH 8
516 506
517/* XGMAC address register high */ 507/* XGMAC address register high */
518#define XM_ADR_HI_REG_MAC 0x01 508#define XM_ADR_HI_REG 0x1210
519#define XM_ADR_5_LBN 8 509#define XM_ADR_5_LBN 8
520#define XM_ADR_5_WIDTH 8 510#define XM_ADR_5_WIDTH 8
521#define XM_ADR_4_LBN 0 511#define XM_ADR_4_LBN 0
522#define XM_ADR_4_WIDTH 8 512#define XM_ADR_4_WIDTH 8
523 513
524/* XGMAC global configuration */ 514/* XGMAC global configuration */
525#define XM_GLB_CFG_REG_MAC 0x02 515#define XM_GLB_CFG_REG 0x1220
526#define XM_RX_STAT_EN_LBN 11 516#define XM_RX_STAT_EN_LBN 11
527#define XM_RX_STAT_EN_WIDTH 1 517#define XM_RX_STAT_EN_WIDTH 1
528#define XM_TX_STAT_EN_LBN 10 518#define XM_TX_STAT_EN_LBN 10
@@ -535,7 +525,7 @@
535#define XM_CORE_RST_WIDTH 1 525#define XM_CORE_RST_WIDTH 1
536 526
537/* XGMAC transmit configuration */ 527/* XGMAC transmit configuration */
538#define XM_TX_CFG_REG_MAC 0x03 528#define XM_TX_CFG_REG 0x1230
539#define XM_IPG_LBN 16 529#define XM_IPG_LBN 16
540#define XM_IPG_WIDTH 4 530#define XM_IPG_WIDTH 4
541#define XM_FCNTL_LBN 10 531#define XM_FCNTL_LBN 10
@@ -550,7 +540,7 @@
550#define XM_TXEN_WIDTH 1 540#define XM_TXEN_WIDTH 1
551 541
552/* XGMAC receive configuration */ 542/* XGMAC receive configuration */
553#define XM_RX_CFG_REG_MAC 0x04 543#define XM_RX_CFG_REG 0x1240
554#define XM_PASS_CRC_ERR_LBN 25 544#define XM_PASS_CRC_ERR_LBN 25
555#define XM_PASS_CRC_ERR_WIDTH 1 545#define XM_PASS_CRC_ERR_WIDTH 1
556#define XM_ACPT_ALL_MCAST_LBN 11 546#define XM_ACPT_ALL_MCAST_LBN 11
@@ -563,7 +553,7 @@
563#define XM_RXEN_WIDTH 1 553#define XM_RXEN_WIDTH 1
564 554
565/* XGMAC management interrupt mask register */ 555/* XGMAC management interrupt mask register */
566#define XM_MGT_INT_MSK_REG_MAC_B0 0x5 556#define XM_MGT_INT_MSK_REG_B0 0x1250
567#define XM_MSK_PRMBLE_ERR_LBN 2 557#define XM_MSK_PRMBLE_ERR_LBN 2
568#define XM_MSK_PRMBLE_ERR_WIDTH 1 558#define XM_MSK_PRMBLE_ERR_WIDTH 1
569#define XM_MSK_RMTFLT_LBN 1 559#define XM_MSK_RMTFLT_LBN 1
@@ -572,29 +562,29 @@
572#define XM_MSK_LCLFLT_WIDTH 1 562#define XM_MSK_LCLFLT_WIDTH 1
573 563
574/* XGMAC flow control register */ 564/* XGMAC flow control register */
575#define XM_FC_REG_MAC 0x7 565#define XM_FC_REG 0x1270
576#define XM_PAUSE_TIME_LBN 16 566#define XM_PAUSE_TIME_LBN 16
577#define XM_PAUSE_TIME_WIDTH 16 567#define XM_PAUSE_TIME_WIDTH 16
578#define XM_DIS_FCNTL_LBN 0 568#define XM_DIS_FCNTL_LBN 0
579#define XM_DIS_FCNTL_WIDTH 1 569#define XM_DIS_FCNTL_WIDTH 1
580 570
581/* XGMAC pause time count register */ 571/* XGMAC pause time count register */
582#define XM_PAUSE_TIME_REG_MAC 0x9 572#define XM_PAUSE_TIME_REG 0x1290
583 573
584/* XGMAC transmit parameter register */ 574/* XGMAC transmit parameter register */
585#define XM_TX_PARAM_REG_MAC 0x0d 575#define XM_TX_PARAM_REG 0x012d0
586#define XM_TX_JUMBO_MODE_LBN 31 576#define XM_TX_JUMBO_MODE_LBN 31
587#define XM_TX_JUMBO_MODE_WIDTH 1 577#define XM_TX_JUMBO_MODE_WIDTH 1
588#define XM_MAX_TX_FRM_SIZE_LBN 16 578#define XM_MAX_TX_FRM_SIZE_LBN 16
589#define XM_MAX_TX_FRM_SIZE_WIDTH 14 579#define XM_MAX_TX_FRM_SIZE_WIDTH 14
590 580
591/* XGMAC receive parameter register */ 581/* XGMAC receive parameter register */
592#define XM_RX_PARAM_REG_MAC 0x0e 582#define XM_RX_PARAM_REG 0x12e0
593#define XM_MAX_RX_FRM_SIZE_LBN 0 583#define XM_MAX_RX_FRM_SIZE_LBN 0
594#define XM_MAX_RX_FRM_SIZE_WIDTH 14 584#define XM_MAX_RX_FRM_SIZE_WIDTH 14
595 585
596/* XGMAC management interrupt status register */ 586/* XGMAC management interrupt status register */
597#define XM_MGT_INT_REG_MAC_B0 0x0f 587#define XM_MGT_INT_REG_B0 0x12f0
598#define XM_PRMBLE_ERR 2 588#define XM_PRMBLE_ERR 2
599#define XM_PRMBLE_WIDTH 1 589#define XM_PRMBLE_WIDTH 1
600#define XM_RMTFLT_LBN 1 590#define XM_RMTFLT_LBN 1
@@ -603,7 +593,7 @@
603#define XM_LCLFLT_WIDTH 1 593#define XM_LCLFLT_WIDTH 1
604 594
605/* XGXS/XAUI powerdown/reset register */ 595/* XGXS/XAUI powerdown/reset register */
606#define XX_PWR_RST_REG_MAC 0x10 596#define XX_PWR_RST_REG 0x1300
607 597
608#define XX_PWRDND_EN_LBN 15 598#define XX_PWRDND_EN_LBN 15
609#define XX_PWRDND_EN_WIDTH 1 599#define XX_PWRDND_EN_WIDTH 1
@@ -633,7 +623,7 @@
633#define XX_RST_XX_EN_WIDTH 1 623#define XX_RST_XX_EN_WIDTH 1
634 624
635/* XGXS/XAUI powerdown/reset control register */ 625/* XGXS/XAUI powerdown/reset control register */
636#define XX_SD_CTL_REG_MAC 0x11 626#define XX_SD_CTL_REG 0x1310
637#define XX_HIDRVD_LBN 15 627#define XX_HIDRVD_LBN 15
638#define XX_HIDRVD_WIDTH 1 628#define XX_HIDRVD_WIDTH 1
639#define XX_LODRVD_LBN 14 629#define XX_LODRVD_LBN 14
@@ -659,7 +649,7 @@
659#define XX_LPBKA_LBN 0 649#define XX_LPBKA_LBN 0
660#define XX_LPBKA_WIDTH 1 650#define XX_LPBKA_WIDTH 1
661 651
662#define XX_TXDRV_CTL_REG_MAC 0x12 652#define XX_TXDRV_CTL_REG 0x1320
663#define XX_DEQD_LBN 28 653#define XX_DEQD_LBN 28
664#define XX_DEQD_WIDTH 4 654#define XX_DEQD_WIDTH 4
665#define XX_DEQC_LBN 24 655#define XX_DEQC_LBN 24
@@ -678,7 +668,7 @@
678#define XX_DTXA_WIDTH 4 668#define XX_DTXA_WIDTH 4
679 669
680/* XAUI XGXS core status register */ 670/* XAUI XGXS core status register */
681#define XX_CORE_STAT_REG_MAC 0x16 671#define XX_CORE_STAT_REG 0x1360
682#define XX_FORCE_SIG_LBN 24 672#define XX_FORCE_SIG_LBN 24
683#define XX_FORCE_SIG_WIDTH 8 673#define XX_FORCE_SIG_WIDTH 8
684#define XX_FORCE_SIG_DECODE_FORCED 0xff 674#define XX_FORCE_SIG_DECODE_FORCED 0xff
diff --git a/drivers/net/sfc/falcon_xmac.c b/drivers/net/sfc/falcon_xmac.c
index 5620d9d13925..a9ae06a2ae2d 100644
--- a/drivers/net/sfc/falcon_xmac.c
+++ b/drivers/net/sfc/falcon_xmac.c
@@ -23,48 +23,20 @@
23 23
24/************************************************************************** 24/**************************************************************************
25 * 25 *
26 * MAC register access
27 *
28 **************************************************************************/
29
30/* Offset of an XMAC register within Falcon */
31#define FALCON_XMAC_REG(mac_reg) \
32 (FALCON_XMAC_REGBANK + ((mac_reg) * FALCON_XMAC_REG_SIZE))
33
34void falcon_xmac_writel(struct efx_nic *efx,
35 efx_dword_t *value, unsigned int mac_reg)
36{
37 efx_oword_t temp;
38
39 EFX_POPULATE_OWORD_1(temp, MAC_DATA, EFX_DWORD_FIELD(*value, MAC_DATA));
40 falcon_write(efx, &temp, FALCON_XMAC_REG(mac_reg));
41}
42
43void falcon_xmac_readl(struct efx_nic *efx,
44 efx_dword_t *value, unsigned int mac_reg)
45{
46 efx_oword_t temp;
47
48 falcon_read(efx, &temp, FALCON_XMAC_REG(mac_reg));
49 EFX_POPULATE_DWORD_1(*value, MAC_DATA, EFX_OWORD_FIELD(temp, MAC_DATA));
50}
51
52/**************************************************************************
53 *
54 * MAC operations 26 * MAC operations
55 * 27 *
56 *************************************************************************/ 28 *************************************************************************/
57static int falcon_reset_xmac(struct efx_nic *efx) 29static int falcon_reset_xmac(struct efx_nic *efx)
58{ 30{
59 efx_dword_t reg; 31 efx_oword_t reg;
60 int count; 32 int count;
61 33
62 EFX_POPULATE_DWORD_1(reg, XM_CORE_RST, 1); 34 EFX_POPULATE_OWORD_1(reg, XM_CORE_RST, 1);
63 falcon_xmac_writel(efx, &reg, XM_GLB_CFG_REG_MAC); 35 falcon_write(efx, &reg, XM_GLB_CFG_REG);
64 36
65 for (count = 0; count < 10000; count++) { /* wait upto 100ms */ 37 for (count = 0; count < 10000; count++) { /* wait upto 100ms */
66 falcon_xmac_readl(efx, &reg, XM_GLB_CFG_REG_MAC); 38 falcon_read(efx, &reg, XM_GLB_CFG_REG);
67 if (EFX_DWORD_FIELD(reg, XM_CORE_RST) == 0) 39 if (EFX_OWORD_FIELD(reg, XM_CORE_RST) == 0)
68 return 0; 40 return 0;
69 udelay(10); 41 udelay(10);
70 } 42 }
@@ -76,25 +48,25 @@ static int falcon_reset_xmac(struct efx_nic *efx)
76/* Configure the XAUI driver that is an output from Falcon */ 48/* Configure the XAUI driver that is an output from Falcon */
77static void falcon_setup_xaui(struct efx_nic *efx) 49static void falcon_setup_xaui(struct efx_nic *efx)
78{ 50{
79 efx_dword_t sdctl, txdrv; 51 efx_oword_t sdctl, txdrv;
80 52
81 /* Move the XAUI into low power, unless there is no PHY, in 53 /* Move the XAUI into low power, unless there is no PHY, in
82 * which case the XAUI will have to drive a cable. */ 54 * which case the XAUI will have to drive a cable. */
83 if (efx->phy_type == PHY_TYPE_NONE) 55 if (efx->phy_type == PHY_TYPE_NONE)
84 return; 56 return;
85 57
86 falcon_xmac_readl(efx, &sdctl, XX_SD_CTL_REG_MAC); 58 falcon_read(efx, &sdctl, XX_SD_CTL_REG);
87 EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT); 59 EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);
88 EFX_SET_DWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT); 60 EFX_SET_OWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);
89 EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT); 61 EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);
90 EFX_SET_DWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT); 62 EFX_SET_OWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);
91 EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT); 63 EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);
92 EFX_SET_DWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT); 64 EFX_SET_OWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);
93 EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT); 65 EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);
94 EFX_SET_DWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT); 66 EFX_SET_OWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);
95 falcon_xmac_writel(efx, &sdctl, XX_SD_CTL_REG_MAC); 67 falcon_write(efx, &sdctl, XX_SD_CTL_REG);
96 68
97 EFX_POPULATE_DWORD_8(txdrv, 69 EFX_POPULATE_OWORD_8(txdrv,
98 XX_DEQD, XX_TXDRV_DEQ_DEFAULT, 70 XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
99 XX_DEQC, XX_TXDRV_DEQ_DEFAULT, 71 XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
100 XX_DEQB, XX_TXDRV_DEQ_DEFAULT, 72 XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
@@ -103,67 +75,67 @@ static void falcon_setup_xaui(struct efx_nic *efx)
103 XX_DTXC, XX_TXDRV_DTX_DEFAULT, 75 XX_DTXC, XX_TXDRV_DTX_DEFAULT,
104 XX_DTXB, XX_TXDRV_DTX_DEFAULT, 76 XX_DTXB, XX_TXDRV_DTX_DEFAULT,
105 XX_DTXA, XX_TXDRV_DTX_DEFAULT); 77 XX_DTXA, XX_TXDRV_DTX_DEFAULT);
106 falcon_xmac_writel(efx, &txdrv, XX_TXDRV_CTL_REG_MAC); 78 falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG);
107} 79}
108 80
109static void falcon_hold_xaui_in_rst(struct efx_nic *efx) 81static void falcon_hold_xaui_in_rst(struct efx_nic *efx)
110{ 82{
111 efx_dword_t reg; 83 efx_oword_t reg;
112 84
113 EFX_ZERO_DWORD(reg); 85 EFX_ZERO_OWORD(reg);
114 EFX_SET_DWORD_FIELD(reg, XX_PWRDNA_EN, 1); 86 EFX_SET_OWORD_FIELD(reg, XX_PWRDNA_EN, 1);
115 EFX_SET_DWORD_FIELD(reg, XX_PWRDNB_EN, 1); 87 EFX_SET_OWORD_FIELD(reg, XX_PWRDNB_EN, 1);
116 EFX_SET_DWORD_FIELD(reg, XX_PWRDNC_EN, 1); 88 EFX_SET_OWORD_FIELD(reg, XX_PWRDNC_EN, 1);
117 EFX_SET_DWORD_FIELD(reg, XX_PWRDND_EN, 1); 89 EFX_SET_OWORD_FIELD(reg, XX_PWRDND_EN, 1);
118 EFX_SET_DWORD_FIELD(reg, XX_RSTPLLAB_EN, 1); 90 EFX_SET_OWORD_FIELD(reg, XX_RSTPLLAB_EN, 1);
119 EFX_SET_DWORD_FIELD(reg, XX_RSTPLLCD_EN, 1); 91 EFX_SET_OWORD_FIELD(reg, XX_RSTPLLCD_EN, 1);
120 EFX_SET_DWORD_FIELD(reg, XX_RESETA_EN, 1); 92 EFX_SET_OWORD_FIELD(reg, XX_RESETA_EN, 1);
121 EFX_SET_DWORD_FIELD(reg, XX_RESETB_EN, 1); 93 EFX_SET_OWORD_FIELD(reg, XX_RESETB_EN, 1);
122 EFX_SET_DWORD_FIELD(reg, XX_RESETC_EN, 1); 94 EFX_SET_OWORD_FIELD(reg, XX_RESETC_EN, 1);
123 EFX_SET_DWORD_FIELD(reg, XX_RESETD_EN, 1); 95 EFX_SET_OWORD_FIELD(reg, XX_RESETD_EN, 1);
124 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1); 96 EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1);
125 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1); 97 EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1);
126 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC); 98 falcon_write(efx, &reg, XX_PWR_RST_REG);
127 udelay(10); 99 udelay(10);
128} 100}
129 101
130static int _falcon_reset_xaui_a(struct efx_nic *efx) 102static int _falcon_reset_xaui_a(struct efx_nic *efx)
131{ 103{
132 efx_dword_t reg; 104 efx_oword_t reg;
133 105
134 falcon_hold_xaui_in_rst(efx); 106 falcon_hold_xaui_in_rst(efx);
135 falcon_xmac_readl(efx, &reg, XX_PWR_RST_REG_MAC); 107 falcon_read(efx, &reg, XX_PWR_RST_REG);
136 108
137 /* Follow the RAMBUS XAUI data reset sequencing 109 /* Follow the RAMBUS XAUI data reset sequencing
138 * Channels A and B first: power down, reset PLL, reset, clear 110 * Channels A and B first: power down, reset PLL, reset, clear
139 */ 111 */
140 EFX_SET_DWORD_FIELD(reg, XX_PWRDNA_EN, 0); 112 EFX_SET_OWORD_FIELD(reg, XX_PWRDNA_EN, 0);
141 EFX_SET_DWORD_FIELD(reg, XX_PWRDNB_EN, 0); 113 EFX_SET_OWORD_FIELD(reg, XX_PWRDNB_EN, 0);
142 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC); 114 falcon_write(efx, &reg, XX_PWR_RST_REG);
143 udelay(10); 115 udelay(10);
144 116
145 EFX_SET_DWORD_FIELD(reg, XX_RSTPLLAB_EN, 0); 117 EFX_SET_OWORD_FIELD(reg, XX_RSTPLLAB_EN, 0);
146 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC); 118 falcon_write(efx, &reg, XX_PWR_RST_REG);
147 udelay(10); 119 udelay(10);
148 120
149 EFX_SET_DWORD_FIELD(reg, XX_RESETA_EN, 0); 121 EFX_SET_OWORD_FIELD(reg, XX_RESETA_EN, 0);
150 EFX_SET_DWORD_FIELD(reg, XX_RESETB_EN, 0); 122 EFX_SET_OWORD_FIELD(reg, XX_RESETB_EN, 0);
151 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC); 123 falcon_write(efx, &reg, XX_PWR_RST_REG);
152 udelay(10); 124 udelay(10);
153 125
154 /* Channels C and D: power down, reset PLL, reset, clear */ 126 /* Channels C and D: power down, reset PLL, reset, clear */
155 EFX_SET_DWORD_FIELD(reg, XX_PWRDNC_EN, 0); 127 EFX_SET_OWORD_FIELD(reg, XX_PWRDNC_EN, 0);
156 EFX_SET_DWORD_FIELD(reg, XX_PWRDND_EN, 0); 128 EFX_SET_OWORD_FIELD(reg, XX_PWRDND_EN, 0);
157 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC); 129 falcon_write(efx, &reg, XX_PWR_RST_REG);
158 udelay(10); 130 udelay(10);
159 131
160 EFX_SET_DWORD_FIELD(reg, XX_RSTPLLCD_EN, 0); 132 EFX_SET_OWORD_FIELD(reg, XX_RSTPLLCD_EN, 0);
161 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC); 133 falcon_write(efx, &reg, XX_PWR_RST_REG);
162 udelay(10); 134 udelay(10);
163 135
164 EFX_SET_DWORD_FIELD(reg, XX_RESETC_EN, 0); 136 EFX_SET_OWORD_FIELD(reg, XX_RESETC_EN, 0);
165 EFX_SET_DWORD_FIELD(reg, XX_RESETD_EN, 0); 137 EFX_SET_OWORD_FIELD(reg, XX_RESETD_EN, 0);
166 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC); 138 falcon_write(efx, &reg, XX_PWR_RST_REG);
167 udelay(10); 139 udelay(10);
168 140
169 /* Setup XAUI */ 141 /* Setup XAUI */
@@ -171,8 +143,8 @@ static int _falcon_reset_xaui_a(struct efx_nic *efx)
171 udelay(10); 143 udelay(10);
172 144
173 /* Take XGXS out of reset */ 145 /* Take XGXS out of reset */
174 EFX_ZERO_DWORD(reg); 146 EFX_ZERO_OWORD(reg);
175 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC); 147 falcon_write(efx, &reg, XX_PWR_RST_REG);
176 udelay(10); 148 udelay(10);
177 149
178 return 0; 150 return 0;
@@ -180,16 +152,16 @@ static int _falcon_reset_xaui_a(struct efx_nic *efx)
180 152
181static int _falcon_reset_xaui_b(struct efx_nic *efx) 153static int _falcon_reset_xaui_b(struct efx_nic *efx)
182{ 154{
183 efx_dword_t reg; 155 efx_oword_t reg;
184 int count; 156 int count;
185 157
186 EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1); 158 EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1);
187 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC); 159 falcon_write(efx, &reg, XX_PWR_RST_REG);
188 160
189 /* Give some time for the link to establish */ 161 /* Give some time for the link to establish */
190 for (count = 0; count < 1000; count++) { /* wait upto 10ms */ 162 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
191 falcon_xmac_readl(efx, &reg, XX_PWR_RST_REG_MAC); 163 falcon_read(efx, &reg, XX_PWR_RST_REG);
192 if (EFX_DWORD_FIELD(reg, XX_RST_XX_EN) == 0) { 164 if (EFX_OWORD_FIELD(reg, XX_RST_XX_EN) == 0) {
193 falcon_setup_xaui(efx); 165 falcon_setup_xaui(efx);
194 return 0; 166 return 0;
195 } 167 }
@@ -215,17 +187,17 @@ int falcon_reset_xaui(struct efx_nic *efx)
215 187
216static bool falcon_xgmii_status(struct efx_nic *efx) 188static bool falcon_xgmii_status(struct efx_nic *efx)
217{ 189{
218 efx_dword_t reg; 190 efx_oword_t reg;
219 191
220 if (falcon_rev(efx) < FALCON_REV_B0) 192 if (falcon_rev(efx) < FALCON_REV_B0)
221 return true; 193 return true;
222 194
223 /* The ISR latches, so clear it and re-read */ 195 /* The ISR latches, so clear it and re-read */
224 falcon_xmac_readl(efx, &reg, XM_MGT_INT_REG_MAC_B0); 196 falcon_read(efx, &reg, XM_MGT_INT_REG_B0);
225 falcon_xmac_readl(efx, &reg, XM_MGT_INT_REG_MAC_B0); 197 falcon_read(efx, &reg, XM_MGT_INT_REG_B0);
226 198
227 if (EFX_DWORD_FIELD(reg, XM_LCLFLT) || 199 if (EFX_OWORD_FIELD(reg, XM_LCLFLT) ||
228 EFX_DWORD_FIELD(reg, XM_RMTFLT)) { 200 EFX_OWORD_FIELD(reg, XM_RMTFLT)) {
229 EFX_INFO(efx, "MGT_INT: "EFX_DWORD_FMT"\n", EFX_DWORD_VAL(reg)); 201 EFX_INFO(efx, "MGT_INT: "EFX_DWORD_FMT"\n", EFX_DWORD_VAL(reg));
230 return false; 202 return false;
231 } 203 }
@@ -235,19 +207,19 @@ static bool falcon_xgmii_status(struct efx_nic *efx)
235 207
236static void falcon_mask_status_intr(struct efx_nic *efx, bool enable) 208static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
237{ 209{
238 efx_dword_t reg; 210 efx_oword_t reg;
239 211
240 if ((falcon_rev(efx) < FALCON_REV_B0) || LOOPBACK_INTERNAL(efx)) 212 if ((falcon_rev(efx) < FALCON_REV_B0) || LOOPBACK_INTERNAL(efx))
241 return; 213 return;
242 214
243 /* Flush the ISR */ 215 /* Flush the ISR */
244 if (enable) 216 if (enable)
245 falcon_xmac_readl(efx, &reg, XM_MGT_INT_REG_MAC_B0); 217 falcon_read(efx, &reg, XM_MGT_INT_REG_B0);
246 218
247 EFX_POPULATE_DWORD_2(reg, 219 EFX_POPULATE_OWORD_2(reg,
248 XM_MSK_RMTFLT, !enable, 220 XM_MSK_RMTFLT, !enable,
249 XM_MSK_LCLFLT, !enable); 221 XM_MSK_LCLFLT, !enable);
250 falcon_xmac_writel(efx, &reg, XM_MGT_INT_MSK_REG_MAC_B0); 222 falcon_write(efx, &reg, XM_MGT_INT_MSK_REG_B0);
251} 223}
252 224
253int falcon_init_xmac(struct efx_nic *efx) 225int falcon_init_xmac(struct efx_nic *efx)
@@ -281,7 +253,7 @@ int falcon_init_xmac(struct efx_nic *efx)
281 253
282bool falcon_xaui_link_ok(struct efx_nic *efx) 254bool falcon_xaui_link_ok(struct efx_nic *efx)
283{ 255{
284 efx_dword_t reg; 256 efx_oword_t reg;
285 bool align_done, link_ok = false; 257 bool align_done, link_ok = false;
286 int sync_status; 258 int sync_status;
287 259
@@ -289,18 +261,18 @@ bool falcon_xaui_link_ok(struct efx_nic *efx)
289 return true; 261 return true;
290 262
291 /* Read link status */ 263 /* Read link status */
292 falcon_xmac_readl(efx, &reg, XX_CORE_STAT_REG_MAC); 264 falcon_read(efx, &reg, XX_CORE_STAT_REG);
293 265
294 align_done = EFX_DWORD_FIELD(reg, XX_ALIGN_DONE); 266 align_done = EFX_OWORD_FIELD(reg, XX_ALIGN_DONE);
295 sync_status = EFX_DWORD_FIELD(reg, XX_SYNC_STAT); 267 sync_status = EFX_OWORD_FIELD(reg, XX_SYNC_STAT);
296 if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED)) 268 if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))
297 link_ok = true; 269 link_ok = true;
298 270
299 /* Clear link status ready for next read */ 271 /* Clear link status ready for next read */
300 EFX_SET_DWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET); 272 EFX_SET_OWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);
301 EFX_SET_DWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET); 273 EFX_SET_OWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);
302 EFX_SET_DWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET); 274 EFX_SET_OWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);
303 falcon_xmac_writel(efx, &reg, XX_CORE_STAT_REG_MAC); 275 falcon_write(efx, &reg, XX_CORE_STAT_REG);
304 276
305 /* If the link is up, then check the phy side of the xaui link 277 /* If the link is up, then check the phy side of the xaui link
306 * (error conditions from the wire side propoagate back through 278 * (error conditions from the wire side propoagate back through
@@ -321,7 +293,7 @@ bool falcon_xaui_link_ok(struct efx_nic *efx)
321static void falcon_reconfigure_xmac_core(struct efx_nic *efx) 293static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
322{ 294{
323 unsigned int max_frame_len; 295 unsigned int max_frame_len;
324 efx_dword_t reg; 296 efx_oword_t reg;
325 bool rx_fc = !!(efx->flow_control & EFX_FC_RX); 297 bool rx_fc = !!(efx->flow_control & EFX_FC_RX);
326 298
327 /* Configure MAC - cut-thru mode is hard wired on */ 299 /* Configure MAC - cut-thru mode is hard wired on */
@@ -329,7 +301,7 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
329 XM_RX_JUMBO_MODE, 1, 301 XM_RX_JUMBO_MODE, 1,
330 XM_TX_STAT_EN, 1, 302 XM_TX_STAT_EN, 1,
331 XM_RX_STAT_EN, 1); 303 XM_RX_STAT_EN, 1);
332 falcon_xmac_writel(efx, &reg, XM_GLB_CFG_REG_MAC); 304 falcon_write(efx, &reg, XM_GLB_CFG_REG);
333 305
334 /* Configure TX */ 306 /* Configure TX */
335 EFX_POPULATE_DWORD_6(reg, 307 EFX_POPULATE_DWORD_6(reg,
@@ -339,7 +311,7 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
339 XM_TXCRC, 1, 311 XM_TXCRC, 1,
340 XM_FCNTL, 1, 312 XM_FCNTL, 1,
341 XM_IPG, 0x3); 313 XM_IPG, 0x3);
342 falcon_xmac_writel(efx, &reg, XM_TX_CFG_REG_MAC); 314 falcon_write(efx, &reg, XM_TX_CFG_REG);
343 315
344 /* Configure RX */ 316 /* Configure RX */
345 EFX_POPULATE_DWORD_5(reg, 317 EFX_POPULATE_DWORD_5(reg,
@@ -348,21 +320,21 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
348 XM_ACPT_ALL_MCAST, 1, 320 XM_ACPT_ALL_MCAST, 1,
349 XM_ACPT_ALL_UCAST, efx->promiscuous, 321 XM_ACPT_ALL_UCAST, efx->promiscuous,
350 XM_PASS_CRC_ERR, 1); 322 XM_PASS_CRC_ERR, 1);
351 falcon_xmac_writel(efx, &reg, XM_RX_CFG_REG_MAC); 323 falcon_write(efx, &reg, XM_RX_CFG_REG);
352 324
353 /* Set frame length */ 325 /* Set frame length */
354 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu); 326 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
355 EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len); 327 EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len);
356 falcon_xmac_writel(efx, &reg, XM_RX_PARAM_REG_MAC); 328 falcon_write(efx, &reg, XM_RX_PARAM_REG);
357 EFX_POPULATE_DWORD_2(reg, 329 EFX_POPULATE_DWORD_2(reg,
358 XM_MAX_TX_FRM_SIZE, max_frame_len, 330 XM_MAX_TX_FRM_SIZE, max_frame_len,
359 XM_TX_JUMBO_MODE, 1); 331 XM_TX_JUMBO_MODE, 1);
360 falcon_xmac_writel(efx, &reg, XM_TX_PARAM_REG_MAC); 332 falcon_write(efx, &reg, XM_TX_PARAM_REG);
361 333
362 EFX_POPULATE_DWORD_2(reg, 334 EFX_POPULATE_DWORD_2(reg,
363 XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */ 335 XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
364 XM_DIS_FCNTL, !rx_fc); 336 XM_DIS_FCNTL, !rx_fc);
365 falcon_xmac_writel(efx, &reg, XM_FC_REG_MAC); 337 falcon_write(efx, &reg, XM_FC_REG);
366 338
367 /* Set MAC address */ 339 /* Set MAC address */
368 EFX_POPULATE_DWORD_4(reg, 340 EFX_POPULATE_DWORD_4(reg,
@@ -370,16 +342,16 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
370 XM_ADR_1, efx->net_dev->dev_addr[1], 342 XM_ADR_1, efx->net_dev->dev_addr[1],
371 XM_ADR_2, efx->net_dev->dev_addr[2], 343 XM_ADR_2, efx->net_dev->dev_addr[2],
372 XM_ADR_3, efx->net_dev->dev_addr[3]); 344 XM_ADR_3, efx->net_dev->dev_addr[3]);
373 falcon_xmac_writel(efx, &reg, XM_ADR_LO_REG_MAC); 345 falcon_write(efx, &reg, XM_ADR_LO_REG);
374 EFX_POPULATE_DWORD_2(reg, 346 EFX_POPULATE_DWORD_2(reg,
375 XM_ADR_4, efx->net_dev->dev_addr[4], 347 XM_ADR_4, efx->net_dev->dev_addr[4],
376 XM_ADR_5, efx->net_dev->dev_addr[5]); 348 XM_ADR_5, efx->net_dev->dev_addr[5]);
377 falcon_xmac_writel(efx, &reg, XM_ADR_HI_REG_MAC); 349 falcon_write(efx, &reg, XM_ADR_HI_REG);
378} 350}
379 351
380static void falcon_reconfigure_xgxs_core(struct efx_nic *efx) 352static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
381{ 353{
382 efx_dword_t reg; 354 efx_oword_t reg;
383 bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS); 355 bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
384 bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI); 356 bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
385 bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII); 357 bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
@@ -390,44 +362,44 @@ static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
390 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback; 362 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
391 bool reset_xgxs; 363 bool reset_xgxs;
392 364
393 falcon_xmac_readl(efx, &reg, XX_CORE_STAT_REG_MAC); 365 falcon_read(efx, &reg, XX_CORE_STAT_REG);
394 old_xgxs_loopback = EFX_DWORD_FIELD(reg, XX_XGXS_LB_EN); 366 old_xgxs_loopback = EFX_OWORD_FIELD(reg, XX_XGXS_LB_EN);
395 old_xgmii_loopback = EFX_DWORD_FIELD(reg, XX_XGMII_LB_EN); 367 old_xgmii_loopback = EFX_OWORD_FIELD(reg, XX_XGMII_LB_EN);
396 368
397 falcon_xmac_readl(efx, &reg, XX_SD_CTL_REG_MAC); 369 falcon_read(efx, &reg, XX_SD_CTL_REG);
398 old_xaui_loopback = EFX_DWORD_FIELD(reg, XX_LPBKA); 370 old_xaui_loopback = EFX_OWORD_FIELD(reg, XX_LPBKA);
399 371
400 /* The PHY driver may have turned XAUI off */ 372 /* The PHY driver may have turned XAUI off */
401 reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) || 373 reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
402 (xaui_loopback != old_xaui_loopback) || 374 (xaui_loopback != old_xaui_loopback) ||
403 (xgmii_loopback != old_xgmii_loopback)); 375 (xgmii_loopback != old_xgmii_loopback));
404 if (reset_xgxs) { 376 if (reset_xgxs) {
405 falcon_xmac_readl(efx, &reg, XX_PWR_RST_REG_MAC); 377 falcon_read(efx, &reg, XX_PWR_RST_REG);
406 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1); 378 EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1);
407 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1); 379 EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1);
408 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC); 380 falcon_write(efx, &reg, XX_PWR_RST_REG);
409 udelay(1); 381 udelay(1);
410 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSTX_EN, 0); 382 EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSTX_EN, 0);
411 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSRX_EN, 0); 383 EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSRX_EN, 0);
412 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC); 384 falcon_write(efx, &reg, XX_PWR_RST_REG);
413 udelay(1); 385 udelay(1);
414 } 386 }
415 } 387 }
416 388
417 falcon_xmac_readl(efx, &reg, XX_CORE_STAT_REG_MAC); 389 falcon_read(efx, &reg, XX_CORE_STAT_REG);
418 EFX_SET_DWORD_FIELD(reg, XX_FORCE_SIG, 390 EFX_SET_OWORD_FIELD(reg, XX_FORCE_SIG,
419 (xgxs_loopback || xaui_loopback) ? 391 (xgxs_loopback || xaui_loopback) ?
420 XX_FORCE_SIG_DECODE_FORCED : 0); 392 XX_FORCE_SIG_DECODE_FORCED : 0);
421 EFX_SET_DWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback); 393 EFX_SET_OWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback);
422 EFX_SET_DWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback); 394 EFX_SET_OWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback);
423 falcon_xmac_writel(efx, &reg, XX_CORE_STAT_REG_MAC); 395 falcon_write(efx, &reg, XX_CORE_STAT_REG);
424 396
425 falcon_xmac_readl(efx, &reg, XX_SD_CTL_REG_MAC); 397 falcon_read(efx, &reg, XX_SD_CTL_REG);
426 EFX_SET_DWORD_FIELD(reg, XX_LPBKD, xaui_loopback); 398 EFX_SET_OWORD_FIELD(reg, XX_LPBKD, xaui_loopback);
427 EFX_SET_DWORD_FIELD(reg, XX_LPBKC, xaui_loopback); 399 EFX_SET_OWORD_FIELD(reg, XX_LPBKC, xaui_loopback);
428 EFX_SET_DWORD_FIELD(reg, XX_LPBKB, xaui_loopback); 400 EFX_SET_OWORD_FIELD(reg, XX_LPBKB, xaui_loopback);
429 EFX_SET_DWORD_FIELD(reg, XX_LPBKA, xaui_loopback); 401 EFX_SET_OWORD_FIELD(reg, XX_LPBKA, xaui_loopback);
430 falcon_xmac_writel(efx, &reg, XX_SD_CTL_REG_MAC); 402 falcon_write(efx, &reg, XX_SD_CTL_REG);
431} 403}
432 404
433 405
diff --git a/drivers/net/sfc/mac.h b/drivers/net/sfc/mac.h
index edd07d4dee18..a31571c69137 100644
--- a/drivers/net/sfc/mac.h
+++ b/drivers/net/sfc/mac.h
@@ -13,10 +13,6 @@
13 13
14#include "net_driver.h" 14#include "net_driver.h"
15 15
16extern void falcon_xmac_writel(struct efx_nic *efx,
17 efx_dword_t *value, unsigned int mac_reg);
18extern void falcon_xmac_readl(struct efx_nic *efx,
19 efx_dword_t *value, unsigned int mac_reg);
20extern int falcon_init_xmac(struct efx_nic *efx); 16extern int falcon_init_xmac(struct efx_nic *efx);
21extern void falcon_reconfigure_xmac(struct efx_nic *efx); 17extern void falcon_reconfigure_xmac(struct efx_nic *efx);
22extern void falcon_update_stats_xmac(struct efx_nic *efx); 18extern void falcon_update_stats_xmac(struct efx_nic *efx);
diff --git a/drivers/net/sfc/sfe4001.c b/drivers/net/sfc/sfe4001.c
index d90fab59f83e..b7005da55d5e 100644
--- a/drivers/net/sfc/sfe4001.c
+++ b/drivers/net/sfc/sfe4001.c
@@ -19,6 +19,7 @@
19#include "boards.h" 19#include "boards.h"
20#include "falcon.h" 20#include "falcon.h"
21#include "falcon_hwdefs.h" 21#include "falcon_hwdefs.h"
22#include "falcon_io.h"
22#include "mac.h" 23#include "mac.h"
23 24
24/************************************************************************** 25/**************************************************************************
@@ -128,17 +129,17 @@ static int sfe4001_poweron(struct efx_nic *efx)
128 unsigned int i, j; 129 unsigned int i, j;
129 int rc; 130 int rc;
130 u8 out; 131 u8 out;
131 efx_dword_t reg; 132 efx_oword_t reg;
132 133
133 /* Ensure that XGXS and XAUI SerDes are held in reset */ 134 /* Ensure that XGXS and XAUI SerDes are held in reset */
134 EFX_POPULATE_DWORD_7(reg, XX_PWRDNA_EN, 1, 135 EFX_POPULATE_OWORD_7(reg, XX_PWRDNA_EN, 1,
135 XX_PWRDNB_EN, 1, 136 XX_PWRDNB_EN, 1,
136 XX_RSTPLLAB_EN, 1, 137 XX_RSTPLLAB_EN, 1,
137 XX_RESETA_EN, 1, 138 XX_RESETA_EN, 1,
138 XX_RESETB_EN, 1, 139 XX_RESETB_EN, 1,
139 XX_RSTXGXSRX_EN, 1, 140 XX_RSTXGXSRX_EN, 1,
140 XX_RSTXGXSTX_EN, 1); 141 XX_RSTXGXSTX_EN, 1);
141 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC); 142 falcon_write(efx, &reg, XX_PWR_RST_REG);
142 udelay(10); 143 udelay(10);
143 144
144 /* Clear any previous over-temperature alert */ 145 /* Clear any previous over-temperature alert */
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 10:40:15 -0400