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authorSonic Zhang <sonic.zhang@analog.com>2012-06-13 04:22:43 -0400
committerWolfram Sang <w.sang@pengutronix.de>2012-07-13 02:36:07 -0400
commit2ee74eb95cf36b1a69e483f9ba2191bd8022b2c1 (patch)
tree9b7c67eec08cb2d43118cf570758e69fa2a1ab2f /virt
parenta25733d6f6968240042ac94dc93c7ae3c9e8d68b (diff)
i2c: i2c-bfin-twi: Tighten condition when failing I2C transfer if MEN bit is reset unexpectedly.
In order to mark I2C transfer fail when MEN bit in I2C controller is reset unexpectedly in MCOMP interrupt, interrupt status bits XMTSERV or RCVSERV should be checked. Master Transfer Complete (MCOMP). [1] The initiated master transfer has completed. In the absence of a repeat start, the bus has been released. [0] The completion of a transfer has not been detected. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> [wsa: fixed spaces around operators and typo in commit message] Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Diffstat (limited to 'virt')
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