diff options
author | Thomas Renninger <trenn@suse.de> | 2011-07-21 05:54:54 -0400 |
---|---|---|
committer | Dominik Brodowski <linux@dominikbrodowski.net> | 2011-07-29 13:37:27 -0400 |
commit | 029e9f73667f9b4661ac9886f706d75d26850260 (patch) | |
tree | 4dd812e1de53d07695ce9b889482b032471a6889 /tools | |
parent | 8fb2e440b223b966f74a04a48f6f71f288fa671b (diff) |
cpupower: Do detect IDA (opportunistic processor performance) via cpuid
IA32-Intel Devel guide Volume 3A - 14.3.2.1
-------------------------------------------
...
Opportunistic processor performance operation can be disabled by setting bit 38 of
IA32_MISC_ENABLES. This mechanism is intended for BIOS only. If
IA32_MISC_ENABLES[38] is set, CPUID.06H:EAX[1] will return 0.
Better detect things via cpuid, this cleans up the code a bit
and the MSR parts were not working correctly anyway.
Signed-off-by: Thomas Renninger <trenn@suse.de>
CC: lenb@kernel.org
CC: linux@dominikbrodowski.net
CC: cpufreq@vger.kernel.org
Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
Diffstat (limited to 'tools')
-rw-r--r-- | tools/power/cpupower/utils/helpers/cpuid.c | 6 | ||||
-rw-r--r-- | tools/power/cpupower/utils/helpers/helpers.h | 9 | ||||
-rw-r--r-- | tools/power/cpupower/utils/helpers/misc.c | 12 | ||||
-rw-r--r-- | tools/power/cpupower/utils/helpers/msr.c | 23 |
4 files changed, 9 insertions, 41 deletions
diff --git a/tools/power/cpupower/utils/helpers/cpuid.c b/tools/power/cpupower/utils/helpers/cpuid.c index a97f091fcf2b..906895d21cce 100644 --- a/tools/power/cpupower/utils/helpers/cpuid.c +++ b/tools/power/cpupower/utils/helpers/cpuid.c | |||
@@ -131,6 +131,12 @@ out: | |||
131 | } | 131 | } |
132 | 132 | ||
133 | if (cpu_info->vendor == X86_VENDOR_INTEL) { | 133 | if (cpu_info->vendor == X86_VENDOR_INTEL) { |
134 | if (cpuid_level >= 6 && | ||
135 | (cpuid_eax(6) & (1 << 1))) | ||
136 | cpu_info->caps |= CPUPOWER_CAP_INTEL_IDA; | ||
137 | } | ||
138 | |||
139 | if (cpu_info->vendor == X86_VENDOR_INTEL) { | ||
134 | /* Intel's perf-bias MSR support */ | 140 | /* Intel's perf-bias MSR support */ |
135 | if (cpuid_level >= 6 && (cpuid_ecx(6) & (1 << 3))) | 141 | if (cpuid_level >= 6 && (cpuid_ecx(6) & (1 << 3))) |
136 | cpu_info->caps |= CPUPOWER_CAP_PERF_BIAS; | 142 | cpu_info->caps |= CPUPOWER_CAP_PERF_BIAS; |
diff --git a/tools/power/cpupower/utils/helpers/helpers.h b/tools/power/cpupower/utils/helpers/helpers.h index 9125a551ac1d..592ee362b877 100644 --- a/tools/power/cpupower/utils/helpers/helpers.h +++ b/tools/power/cpupower/utils/helpers/helpers.h | |||
@@ -58,6 +58,7 @@ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL, | |||
58 | #define CPUPOWER_CAP_PERF_BIAS 0x00000008 | 58 | #define CPUPOWER_CAP_PERF_BIAS 0x00000008 |
59 | #define CPUPOWER_CAP_HAS_TURBO_RATIO 0x00000010 | 59 | #define CPUPOWER_CAP_HAS_TURBO_RATIO 0x00000010 |
60 | #define CPUPOWER_CAP_IS_SNB 0x00000011 | 60 | #define CPUPOWER_CAP_IS_SNB 0x00000011 |
61 | #define CPUPOWER_CAP_INTEL_IDA 0x00000012 | ||
61 | 62 | ||
62 | #define MAX_HW_PSTATES 10 | 63 | #define MAX_HW_PSTATES 10 |
63 | 64 | ||
@@ -115,9 +116,6 @@ extern int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val); | |||
115 | extern int msr_intel_get_perf_bias(unsigned int cpu); | 116 | extern int msr_intel_get_perf_bias(unsigned int cpu); |
116 | extern unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu); | 117 | extern unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu); |
117 | 118 | ||
118 | extern int msr_intel_has_boost_support(unsigned int cpu); | ||
119 | extern int msr_intel_boost_is_active(unsigned int cpu); | ||
120 | |||
121 | /* Read/Write msr ****************************/ | 119 | /* Read/Write msr ****************************/ |
122 | 120 | ||
123 | /* PCI stuff ****************************/ | 121 | /* PCI stuff ****************************/ |
@@ -163,11 +161,6 @@ static inline int msr_intel_get_perf_bias(unsigned int cpu) | |||
163 | static inline unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu) | 161 | static inline unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu) |
164 | { return 0; }; | 162 | { return 0; }; |
165 | 163 | ||
166 | static inline int msr_intel_has_boost_support(unsigned int cpu) | ||
167 | { return -1; }; | ||
168 | static inline int msr_intel_boost_is_active(unsigned int cpu) | ||
169 | { return -1; }; | ||
170 | |||
171 | /* Read/Write msr ****************************/ | 164 | /* Read/Write msr ****************************/ |
172 | 165 | ||
173 | static inline int cpufreq_has_boost_support(unsigned int cpu, int *support, | 166 | static inline int cpufreq_has_boost_support(unsigned int cpu, int *support, |
diff --git a/tools/power/cpupower/utils/helpers/misc.c b/tools/power/cpupower/utils/helpers/misc.c index e8b3140cc6b8..1609243f5c64 100644 --- a/tools/power/cpupower/utils/helpers/misc.c +++ b/tools/power/cpupower/utils/helpers/misc.c | |||
@@ -20,16 +20,8 @@ int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active, | |||
20 | if (ret <= 0) | 20 | if (ret <= 0) |
21 | return ret; | 21 | return ret; |
22 | *support = 1; | 22 | *support = 1; |
23 | } else if (cpupower_cpu_info.vendor == X86_VENDOR_INTEL) { | 23 | } else if (cpupower_cpu_info.caps & CPUPOWER_CAP_INTEL_IDA) |
24 | ret = msr_intel_has_boost_support(cpu); | 24 | *support = *active = 1; |
25 | if (ret <= 0) | ||
26 | return ret; | ||
27 | *support = ret; | ||
28 | ret = msr_intel_boost_is_active(cpu); | ||
29 | if (ret <= 0) | ||
30 | return ret; | ||
31 | *active = ret; | ||
32 | } | ||
33 | return 0; | 25 | return 0; |
34 | } | 26 | } |
35 | #endif /* #if defined(__i386__) || defined(__x86_64__) */ | 27 | #endif /* #if defined(__i386__) || defined(__x86_64__) */ |
diff --git a/tools/power/cpupower/utils/helpers/msr.c b/tools/power/cpupower/utils/helpers/msr.c index 7869ca64dfd3..31a4b24a8bc6 100644 --- a/tools/power/cpupower/utils/helpers/msr.c +++ b/tools/power/cpupower/utils/helpers/msr.c | |||
@@ -72,29 +72,6 @@ int write_msr(int cpu, unsigned int idx, unsigned long long val) | |||
72 | return -1; | 72 | return -1; |
73 | } | 73 | } |
74 | 74 | ||
75 | int msr_intel_has_boost_support(unsigned int cpu) | ||
76 | { | ||
77 | unsigned long long misc_enables; | ||
78 | int ret; | ||
79 | |||
80 | ret = read_msr(cpu, MSR_IA32_MISC_ENABLES, &misc_enables); | ||
81 | if (ret) | ||
82 | return ret; | ||
83 | |||
84 | return (misc_enables >> 38) & 0x1; | ||
85 | } | ||
86 | |||
87 | int msr_intel_boost_is_active(unsigned int cpu) | ||
88 | { | ||
89 | unsigned long long perf_status; | ||
90 | int ret; | ||
91 | |||
92 | ret = read_msr(cpu, MSR_IA32_PERF_STATUS, &perf_status); | ||
93 | if (ret) | ||
94 | return ret; | ||
95 | return (perf_status >> 32) & 0x1; | ||
96 | } | ||
97 | |||
98 | int msr_intel_get_perf_bias(unsigned int cpu) | 75 | int msr_intel_get_perf_bias(unsigned int cpu) |
99 | { | 76 | { |
100 | unsigned long long val; | 77 | unsigned long long val; |