litmus-rt.git - The LITMUS^RT kernel.

diff options

author	Arnd Bergmann <arnd@arndb.de>	2013-04-19 16:50:41 -0400
committer	Arnd Bergmann <arnd@arndb.de>	2013-04-19 16:50:52 -0400
commit	f54ae513d3d39b60bcc2ef446f1219f501d859bf (patch)
tree	a60c22feaee5265fa9b017bc504793ae1b531972 /tools/perf/util/scripting-engines/trace-event-perl.c
parent	1b361942b53c33f38d55065c13785aadb5103a18 (diff)
parent	e34d3865ee4a71195f91b23fd09e2619a5f727d3 (diff)

Merge branch 'spear/dwdma' into late/cleanup

This is a series originally prepared for inclusion in 3.9, which did not work out because of dependencies on the dmaengine driver. All the changes for the dmaengine code are merged in 3.9 now, so we can finally do the switchover and remove the now unnecessary dma definitions for spear13xx from the platform code. The dma platform_data actually made up the majority of the spear13xx platform code overall, so moving that into device tree files makes the code substantially smaller. * spear/dwdma: ata: arasan: remove the need for platform_data ARM: SPEAr13xx: Pass generic DW DMAC platform data from DT serial: pl011: use generic DMA slave configuration if possible spi: pl022: use generic DMA slave configuration if possible Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-perl.c')

0 files changed, 0 insertions, 0 deletions

/****************************************************************************** * * This file is provided under a dual BSD/GPLv2 license. When using or * redistributing this file, you may do so under either license. * * GPL LICENSE SUMMARY * * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of version 2 of the GNU General Public License as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, * USA * * The full GNU General Public License is included in this distribution * in the file called LICENSE.GPL. * * Contact Information: * James P. Ketrenos <ipw2100-admin@linux.intel.com> * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 * * BSD LICENSE * * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * * Neither the name Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * *****************************************************************************/ /* * Please use this file (iwl-3945-hw.h) only for hardware-related definitions. * Please use iwl-3945-commands.h for uCode API definitions. * Please use iwl-3945.h for driver implementation definitions. */ #ifndef __iwl_3945_hw__ #define __iwl_3945_hw__ /* * uCode queue management definitions ... * Queue #4 is the command queue for 3945 and 4965. */ #define IWL_CMD_QUEUE_NUM 4 /* Tx rates */ #define IWL_CCK_RATES 4 #define IWL_OFDM_RATES 8 #define IWL_HT_RATES 0 #define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES) /* Time constants */ #define SHORT_SLOT_TIME 9 #define LONG_SLOT_TIME 20 /* RSSI to dBm */ #define IWL_RSSI_OFFSET 95 /* * EEPROM related constants, enums, and structures. */ /* * EEPROM access time values: * * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG, * then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit * CSR_EEPROM_REG_BIT_CMD (0x2). * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. */ #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ #define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */ /* * Regulatory channel usage flags in EEPROM struct iwl_eeprom_channel.flags. * * IBSS and/or AP operation is allowed *only* on those channels with * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because * RADAR detection is not supported by the 3945 driver, but is a * requirement for establishing a new network for legal operation on channels * requiring RADAR detection or restricting ACTIVE scanning. * * NOTE: "WIDE" flag indicates that 20 MHz channel is supported; * 3945 does not support FAT 40 MHz-wide channels. * * NOTE: Using a channel inappropriately will result in a uCode error! */ enum { EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ /* Bit 2 Reserved */ EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel (not used) */ EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ }; /* SKU Capabilities */ #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0) #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1) #define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7) /* *regulatory* channel data from eeprom, one for each channel */ struct iwl3945_eeprom_channel { u8 flags; /* flags copied from EEPROM */ s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */ } __attribute__ ((packed)); /* * Mapping of a Tx power level, at factory calibration temperature, * to a radio/DSP gain table index. * One for each of 5 "sample" power levels in each band. * v_det is measured at the factory, using the 3945's built-in power amplifier * (PA) output voltage detector. This same detector is used during Tx of * long packets in normal operation to provide feedback as to proper output * level. * Data copied from EEPROM. * DO NOT ALTER THIS STRUCTURE!!! */ struct iwl3945_eeprom_txpower_sample { u8 gain_index; /* index into power (gain) setup table ... */ s8 power; /* ... for this pwr level for this chnl group */ u16 v_det; /* PA output voltage */ } __attribute__ ((packed)); /* * Mappings of Tx power levels -> nominal radio/DSP gain table indexes. * One for each channel group (a.k.a. "band") (1 for BG, 4 for A). * Tx power setup code interpolates between the 5 "sample" power levels * to determine the nominal setup for a requested power level. * Data copied from EEPROM. * DO NOT ALTER THIS STRUCTURE!!! */ struct iwl3945_eeprom_txpower_group { struct iwl3945_eeprom_txpower_sample samples[5]; /* 5 power levels */ s32 a, b, c, d, e; /* coefficients for voltage->power * formula (signed) */ s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on * frequency (signed) */ s8 saturation_power; /* highest power possible by h/w in this * band */ u8 group_channel; /* "representative" channel # in this band */ s16 temperature; /* h/w temperature at factory calib this band * (signed) */ } __attribute__ ((packed)); /* * Temperature-based Tx-power compensation data, not band-specific. * These coefficients are use to modify a/b/c/d/e coeffs based on * difference between current temperature and factory calib temperature. * Data copied from EEPROM. */ struct iwl3945_eeprom_temperature_corr { u32 Ta; u32 Tb; u32 Tc; u32 Td; u32 Te; } __attribute__ ((packed)); /* * EEPROM map */ struct iwl3945_eeprom { u8 reserved0[16]; #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ u16 device_id; /* abs.ofs: 16 */ u8 reserved1[2]; #define EEPROM_PMC (2*0x0A) /* 2 bytes */ u16 pmc; /* abs.ofs: 20 */ u8 reserved2[20]; #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ u8 mac_address[6]; /* abs.ofs: 42 */ u8 reserved3[58]; #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ u16 board_revision; /* abs.ofs: 106 */ u8 reserved4[11]; #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ u8 board_pba_number[9]; /* abs.ofs: 119 */ u8 reserved5[8]; #define EEPROM_VERSION (2*0x44) /* 2 bytes */ u16 version; /* abs.ofs: 136 */ #define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */ u8 sku_cap; /* abs.ofs: 138 */ #define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */ u8 leds_mode; /* abs.ofs: 139 */ #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ u16 oem_mode; #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */ u16 wowlan_mode; /* abs.ofs: 142 */ #define EEPROM_LEDS_TIME_INTERVAL (2*0x48) /* 2 bytes */ u16 leds_time_interval; /* abs.ofs: 144 */ #define EEPROM_LEDS_OFF_TIME (2*0x49) /* 1 bytes */ u8 leds_off_time; /* abs.ofs: 146 */ #define EEPROM_LEDS_ON_TIME (2*0x49+1) /* 1 bytes */ u8 leds_on_time; /* abs.ofs: 147 */ #define EEPROM_ALMGOR_M_VERSION (2*0x4A) /* 1 bytes */ u8 almgor_m_version; /* abs.ofs: 148 */ #define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */ u8 antenna_switch_type; /* abs.ofs: 149 */ u8 reserved6[42]; #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */ u8 sku_id[4]; /* abs.ofs: 192 */ /* * Per-channel regulatory data. * * Each channel that *might* be supported by 3945 or 4965 has a fixed location * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory * txpower (MSB). * * Entries immediately below are for 20 MHz channel width. FAT (40 MHz) * channels (only for 4965, not supported by 3945) appear later in the EEPROM. * * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */ u16 band_1_count; /* abs.ofs: 196 */ #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */ struct iwl3945_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */ /* * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, * 5.0 GHz channels 7, 8, 11, 12, 16 * (4915-5080MHz) (none of these is ever supported) */ #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */ u16 band_2_count; /* abs.ofs: 226 */ #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */ struct iwl3945_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */ /* * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 * (5170-5320MHz) */ #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */ u16 band_3_count; /* abs.ofs: 254 */ #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */ struct iwl3945_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */ /* * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 * (5500-5700MHz) */ #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */ u16 band_4_count; /* abs.ofs: 280 */ #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */ struct iwl3945_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */ /* * 5.7 GHz channels 145, 149, 153, 157, 161, 165 * (5725-5825MHz) */ #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */ u16 band_5_count; /* abs.ofs: 304 */ #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */ struct iwl3945_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */ u8 reserved9[194]; /* * 3945 Txpower calibration data. */ #define EEPROM_TXPOWER_CALIB_GROUP0 0x200 #define EEPROM_TXPOWER_CALIB_GROUP1 0x240 #define EEPROM_TXPOWER_CALIB_GROUP2 0x280 #define EEPROM_TXPOWER_CALIB_GROUP3 0x2c0 #define EEPROM_TXPOWER_CALIB_GROUP4 0x300 #define IWL_NUM_TX_CALIB_GROUPS 5 struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS]; /* abs.ofs: 512 */ #define EEPROM_CALIB_TEMPERATURE_CORRECT 0x340 struct iwl3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */ u8 reserved16[172]; /* fill out to full 1024 byte block */ } __attribute__ ((packed)); #define IWL_EEPROM_IMAGE_SIZE 1024 /* End of EEPROM */ #include "iwl-3945-commands.h" #define PCI_LINK_CTRL 0x0F0 #define PCI_POWER_SOURCE 0x0C8 #define PCI_REG_WUM8 0x0E8 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) /*=== CSR (control and status registers) ===*/ #define CSR_BASE (0x000) #define CSR_SW_VER (CSR_BASE+0x000) #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ #define CSR_GP_CNTRL (CSR_BASE+0x024) /* * Hardware revision info * Bit fields: * 31-8: Reserved * 7-4: Type of device: 0x0 = 4965, 0xd = 3945 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D * 1-0: "Dash" value, as in A-1, etc. */ #define CSR_HW_REV (CSR_BASE+0x028) /* EEPROM reads */ #define CSR_EEPROM_REG (CSR_BASE+0x02c) #define CSR_EEPROM_GP (CSR_BASE+0x030) #define CSR_GP_UCODE (CSR_BASE+0x044) #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) /* Analog phase-lock-loop configuration (3945 only) * Set bit 24. */ #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) /* Bits for CSR_HW_IF_CONFIG_REG */ #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100) #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200) #define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400) #define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800) #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), * acknowledged (reset) by host writing "1" to flagged bits. */ #define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */ #define CSR_INT_BIT_HW_ERR (1<<29) /* DMA hardware error FH_INT[31] */ #define CSR_INT_BIT_DNLD (1<<28) /* uCode Download */ #define CSR_INT_BIT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */ #define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */ #define CSR_INT_BIT_SW_ERR (1<<25) /* uCode error */ #define CSR_INT_BIT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */ #define CSR_INT_BIT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */ #define CSR_INT_BIT_SW_RX (1<<3) /* Rx, command responses, 3945 */ #define CSR_INT_BIT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */ #define CSR_INT_BIT_ALIVE (1<<0) /* uCode interrupts once it initializes */ #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \


context:
space:
mode: