diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-08-07 11:47:00 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-08-07 11:47:00 -0400 |
commit | e669830526a0abaf301bf408df69cde33901ac63 (patch) | |
tree | 0b6043375006d1754bbd1ab2370b0a0536546cc9 /sound | |
parent | ebb067d2f4e2db59b076f9c9cba0375a8ad1e07c (diff) | |
parent | 475d5928b79bb78326a645863d46ff95c5e25e5a (diff) |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for 3.17. It contains:
- misc Cavium Octeon, BCM47xx, BCM63xx and Alchemy updates
- MIPS ptrace updates and cleanups
- various fixes that will also go to -stable
- a number of cleanups and small non-critical fixes.
- NUMA support for the Loongson 3.
- more support for MSA
- support for MAAR
- various FP enhancements and fixes"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits)
MIPS: jz4740: remove unnecessary null test before debugfs_remove
MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursive
MIPS: ZBOOT: implement stack protector in compressed boot phase
MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT
MIPS: Bonito64: remove a duplicate define
MIPS: Malta: initialise MAARs
MIPS: Initialise MAARs
MIPS: detect presence of MAARs
MIPS: define MAAR register accessors & bits
MIPS: mark MSA experimental
MIPS: Don't build MSA support unless it can be used
MIPS: consistently clear MSA flags when starting & copying threads
MIPS: 16 byte align MSA vector context
MIPS: disable preemption whilst initialising MSA
MIPS: ensure MSA gets disabled during boot
MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains
MIPS: fix MSA context for tasks which don't use FP first
MIPS: init upper 64b of vector registers when MSA is first used
MIPS: save/disable MSA in lose_fpu
MIPS: preserve scalar FP CSR when switching vector context
...
Diffstat (limited to 'sound')
-rw-r--r-- | sound/soc/au1x/psc-ac97.c | 140 | ||||
-rw-r--r-- | sound/soc/au1x/psc-i2s.c | 100 | ||||
-rw-r--r-- | sound/soc/au1x/psc.h | 22 |
3 files changed, 131 insertions, 131 deletions
diff --git a/sound/soc/au1x/psc-ac97.c b/sound/soc/au1x/psc-ac97.c index 986dcec79fa0..84f31e1f9d24 100644 --- a/sound/soc/au1x/psc-ac97.c +++ b/sound/soc/au1x/psc-ac97.c | |||
@@ -79,28 +79,28 @@ static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97, | |||
79 | unsigned short retry, tmo; | 79 | unsigned short retry, tmo; |
80 | unsigned long data; | 80 | unsigned long data; |
81 | 81 | ||
82 | au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); | 82 | __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); |
83 | au_sync(); | 83 | wmb(); /* drain writebuffer */ |
84 | 84 | ||
85 | retry = AC97_RW_RETRIES; | 85 | retry = AC97_RW_RETRIES; |
86 | do { | 86 | do { |
87 | mutex_lock(&pscdata->lock); | 87 | mutex_lock(&pscdata->lock); |
88 | 88 | ||
89 | au_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg), | 89 | __raw_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg), |
90 | AC97_CDC(pscdata)); | 90 | AC97_CDC(pscdata)); |
91 | au_sync(); | 91 | wmb(); /* drain writebuffer */ |
92 | 92 | ||
93 | tmo = 20; | 93 | tmo = 20; |
94 | do { | 94 | do { |
95 | udelay(21); | 95 | udelay(21); |
96 | if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) | 96 | if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) |
97 | break; | 97 | break; |
98 | } while (--tmo); | 98 | } while (--tmo); |
99 | 99 | ||
100 | data = au_readl(AC97_CDC(pscdata)); | 100 | data = __raw_readl(AC97_CDC(pscdata)); |
101 | 101 | ||
102 | au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); | 102 | __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); |
103 | au_sync(); | 103 | wmb(); /* drain writebuffer */ |
104 | 104 | ||
105 | mutex_unlock(&pscdata->lock); | 105 | mutex_unlock(&pscdata->lock); |
106 | 106 | ||
@@ -119,26 +119,26 @@ static void au1xpsc_ac97_write(struct snd_ac97 *ac97, unsigned short reg, | |||
119 | struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97); | 119 | struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97); |
120 | unsigned int tmo, retry; | 120 | unsigned int tmo, retry; |
121 | 121 | ||
122 | au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); | 122 | __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); |
123 | au_sync(); | 123 | wmb(); /* drain writebuffer */ |
124 | 124 | ||
125 | retry = AC97_RW_RETRIES; | 125 | retry = AC97_RW_RETRIES; |
126 | do { | 126 | do { |
127 | mutex_lock(&pscdata->lock); | 127 | mutex_lock(&pscdata->lock); |
128 | 128 | ||
129 | au_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff), | 129 | __raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff), |
130 | AC97_CDC(pscdata)); | 130 | AC97_CDC(pscdata)); |
131 | au_sync(); | 131 | wmb(); /* drain writebuffer */ |
132 | 132 | ||
133 | tmo = 20; | 133 | tmo = 20; |
134 | do { | 134 | do { |
135 | udelay(21); | 135 | udelay(21); |
136 | if (au_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) | 136 | if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) |
137 | break; | 137 | break; |
138 | } while (--tmo); | 138 | } while (--tmo); |
139 | 139 | ||
140 | au_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); | 140 | __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); |
141 | au_sync(); | 141 | wmb(); /* drain writebuffer */ |
142 | 142 | ||
143 | mutex_unlock(&pscdata->lock); | 143 | mutex_unlock(&pscdata->lock); |
144 | } while (--retry && !tmo); | 144 | } while (--retry && !tmo); |
@@ -149,11 +149,11 @@ static void au1xpsc_ac97_warm_reset(struct snd_ac97 *ac97) | |||
149 | { | 149 | { |
150 | struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97); | 150 | struct au1xpsc_audio_data *pscdata = ac97_to_pscdata(ac97); |
151 | 151 | ||
152 | au_writel(PSC_AC97RST_SNC, AC97_RST(pscdata)); | 152 | __raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata)); |
153 | au_sync(); | 153 | wmb(); /* drain writebuffer */ |
154 | msleep(10); | 154 | msleep(10); |
155 | au_writel(0, AC97_RST(pscdata)); | 155 | __raw_writel(0, AC97_RST(pscdata)); |
156 | au_sync(); | 156 | wmb(); /* drain writebuffer */ |
157 | } | 157 | } |
158 | 158 | ||
159 | static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97) | 159 | static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97) |
@@ -162,25 +162,25 @@ static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97) | |||
162 | int i; | 162 | int i; |
163 | 163 | ||
164 | /* disable PSC during cold reset */ | 164 | /* disable PSC during cold reset */ |
165 | au_writel(0, AC97_CFG(au1xpsc_ac97_workdata)); | 165 | __raw_writel(0, AC97_CFG(au1xpsc_ac97_workdata)); |
166 | au_sync(); | 166 | wmb(); /* drain writebuffer */ |
167 | au_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata)); | 167 | __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata)); |
168 | au_sync(); | 168 | wmb(); /* drain writebuffer */ |
169 | 169 | ||
170 | /* issue cold reset */ | 170 | /* issue cold reset */ |
171 | au_writel(PSC_AC97RST_RST, AC97_RST(pscdata)); | 171 | __raw_writel(PSC_AC97RST_RST, AC97_RST(pscdata)); |
172 | au_sync(); | 172 | wmb(); /* drain writebuffer */ |
173 | msleep(500); | 173 | msleep(500); |
174 | au_writel(0, AC97_RST(pscdata)); | 174 | __raw_writel(0, AC97_RST(pscdata)); |
175 | au_sync(); | 175 | wmb(); /* drain writebuffer */ |
176 | 176 | ||
177 | /* enable PSC */ | 177 | /* enable PSC */ |
178 | au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata)); | 178 | __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata)); |
179 | au_sync(); | 179 | wmb(); /* drain writebuffer */ |
180 | 180 | ||
181 | /* wait for PSC to indicate it's ready */ | 181 | /* wait for PSC to indicate it's ready */ |
182 | i = 1000; | 182 | i = 1000; |
183 | while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i)) | 183 | while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i)) |
184 | msleep(1); | 184 | msleep(1); |
185 | 185 | ||
186 | if (i == 0) { | 186 | if (i == 0) { |
@@ -189,12 +189,12 @@ static void au1xpsc_ac97_cold_reset(struct snd_ac97 *ac97) | |||
189 | } | 189 | } |
190 | 190 | ||
191 | /* enable the ac97 function */ | 191 | /* enable the ac97 function */ |
192 | au_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); | 192 | __raw_writel(pscdata->cfg | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); |
193 | au_sync(); | 193 | wmb(); /* drain writebuffer */ |
194 | 194 | ||
195 | /* wait for AC97 core to become ready */ | 195 | /* wait for AC97 core to become ready */ |
196 | i = 1000; | 196 | i = 1000; |
197 | while (!((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i)) | 197 | while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && (--i)) |
198 | msleep(1); | 198 | msleep(1); |
199 | if (i == 0) | 199 | if (i == 0) |
200 | printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n"); | 200 | printk(KERN_ERR "au1xpsc-ac97: AC97 ctrl not ready\n"); |
@@ -218,8 +218,8 @@ static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream, | |||
218 | 218 | ||
219 | chans = params_channels(params); | 219 | chans = params_channels(params); |
220 | 220 | ||
221 | r = ro = au_readl(AC97_CFG(pscdata)); | 221 | r = ro = __raw_readl(AC97_CFG(pscdata)); |
222 | stat = au_readl(AC97_STAT(pscdata)); | 222 | stat = __raw_readl(AC97_STAT(pscdata)); |
223 | 223 | ||
224 | /* already active? */ | 224 | /* already active? */ |
225 | if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) { | 225 | if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) { |
@@ -252,28 +252,28 @@ static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream, | |||
252 | mutex_lock(&pscdata->lock); | 252 | mutex_lock(&pscdata->lock); |
253 | 253 | ||
254 | /* disable AC97 device controller first... */ | 254 | /* disable AC97 device controller first... */ |
255 | au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); | 255 | __raw_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); |
256 | au_sync(); | 256 | wmb(); /* drain writebuffer */ |
257 | 257 | ||
258 | /* ...wait for it... */ | 258 | /* ...wait for it... */ |
259 | t = 100; | 259 | t = 100; |
260 | while ((au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t) | 260 | while ((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t) |
261 | msleep(1); | 261 | msleep(1); |
262 | 262 | ||
263 | if (!t) | 263 | if (!t) |
264 | printk(KERN_ERR "PSC-AC97: can't disable!\n"); | 264 | printk(KERN_ERR "PSC-AC97: can't disable!\n"); |
265 | 265 | ||
266 | /* ...write config... */ | 266 | /* ...write config... */ |
267 | au_writel(r, AC97_CFG(pscdata)); | 267 | __raw_writel(r, AC97_CFG(pscdata)); |
268 | au_sync(); | 268 | wmb(); /* drain writebuffer */ |
269 | 269 | ||
270 | /* ...enable the AC97 controller again... */ | 270 | /* ...enable the AC97 controller again... */ |
271 | au_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); | 271 | __raw_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); |
272 | au_sync(); | 272 | wmb(); /* drain writebuffer */ |
273 | 273 | ||
274 | /* ...and wait for ready bit */ | 274 | /* ...and wait for ready bit */ |
275 | t = 100; | 275 | t = 100; |
276 | while ((!(au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t) | 276 | while ((!(__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t) |
277 | msleep(1); | 277 | msleep(1); |
278 | 278 | ||
279 | if (!t) | 279 | if (!t) |
@@ -300,21 +300,21 @@ static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream, | |||
300 | switch (cmd) { | 300 | switch (cmd) { |
301 | case SNDRV_PCM_TRIGGER_START: | 301 | case SNDRV_PCM_TRIGGER_START: |
302 | case SNDRV_PCM_TRIGGER_RESUME: | 302 | case SNDRV_PCM_TRIGGER_RESUME: |
303 | au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata)); | 303 | __raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata)); |
304 | au_sync(); | 304 | wmb(); /* drain writebuffer */ |
305 | au_writel(AC97PCR_START(stype), AC97_PCR(pscdata)); | 305 | __raw_writel(AC97PCR_START(stype), AC97_PCR(pscdata)); |
306 | au_sync(); | 306 | wmb(); /* drain writebuffer */ |
307 | break; | 307 | break; |
308 | case SNDRV_PCM_TRIGGER_STOP: | 308 | case SNDRV_PCM_TRIGGER_STOP: |
309 | case SNDRV_PCM_TRIGGER_SUSPEND: | 309 | case SNDRV_PCM_TRIGGER_SUSPEND: |
310 | au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata)); | 310 | __raw_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata)); |
311 | au_sync(); | 311 | wmb(); /* drain writebuffer */ |
312 | 312 | ||
313 | while (au_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype)) | 313 | while (__raw_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype)) |
314 | asm volatile ("nop"); | 314 | asm volatile ("nop"); |
315 | 315 | ||
316 | au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata)); | 316 | __raw_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata)); |
317 | au_sync(); | 317 | wmb(); /* drain writebuffer */ |
318 | 318 | ||
319 | break; | 319 | break; |
320 | default: | 320 | default: |
@@ -398,13 +398,13 @@ static int au1xpsc_ac97_drvprobe(struct platform_device *pdev) | |||
398 | PSC_AC97CFG_DE_ENABLE; | 398 | PSC_AC97CFG_DE_ENABLE; |
399 | 399 | ||
400 | /* preserve PSC clock source set up by platform */ | 400 | /* preserve PSC clock source set up by platform */ |
401 | sel = au_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK; | 401 | sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK; |
402 | au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); | 402 | __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); |
403 | au_sync(); | 403 | wmb(); /* drain writebuffer */ |
404 | au_writel(0, PSC_SEL(wd)); | 404 | __raw_writel(0, PSC_SEL(wd)); |
405 | au_sync(); | 405 | wmb(); /* drain writebuffer */ |
406 | au_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd)); | 406 | __raw_writel(PSC_SEL_PS_AC97MODE | sel, PSC_SEL(wd)); |
407 | au_sync(); | 407 | wmb(); /* drain writebuffer */ |
408 | 408 | ||
409 | /* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */ | 409 | /* name the DAI like this device instance ("au1xpsc-ac97.PSCINDEX") */ |
410 | memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template, | 410 | memcpy(&wd->dai_drv, &au1xpsc_ac97_dai_template, |
@@ -433,10 +433,10 @@ static int au1xpsc_ac97_drvremove(struct platform_device *pdev) | |||
433 | snd_soc_unregister_component(&pdev->dev); | 433 | snd_soc_unregister_component(&pdev->dev); |
434 | 434 | ||
435 | /* disable PSC completely */ | 435 | /* disable PSC completely */ |
436 | au_writel(0, AC97_CFG(wd)); | 436 | __raw_writel(0, AC97_CFG(wd)); |
437 | au_sync(); | 437 | wmb(); /* drain writebuffer */ |
438 | au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); | 438 | __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); |
439 | au_sync(); | 439 | wmb(); /* drain writebuffer */ |
440 | 440 | ||
441 | au1xpsc_ac97_workdata = NULL; /* MDEV */ | 441 | au1xpsc_ac97_workdata = NULL; /* MDEV */ |
442 | 442 | ||
@@ -449,12 +449,12 @@ static int au1xpsc_ac97_drvsuspend(struct device *dev) | |||
449 | struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); | 449 | struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); |
450 | 450 | ||
451 | /* save interesting registers and disable PSC */ | 451 | /* save interesting registers and disable PSC */ |
452 | wd->pm[0] = au_readl(PSC_SEL(wd)); | 452 | wd->pm[0] = __raw_readl(PSC_SEL(wd)); |
453 | 453 | ||
454 | au_writel(0, AC97_CFG(wd)); | 454 | __raw_writel(0, AC97_CFG(wd)); |
455 | au_sync(); | 455 | wmb(); /* drain writebuffer */ |
456 | au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); | 456 | __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); |
457 | au_sync(); | 457 | wmb(); /* drain writebuffer */ |
458 | 458 | ||
459 | return 0; | 459 | return 0; |
460 | } | 460 | } |
@@ -464,8 +464,8 @@ static int au1xpsc_ac97_drvresume(struct device *dev) | |||
464 | struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); | 464 | struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); |
465 | 465 | ||
466 | /* restore PSC clock config */ | 466 | /* restore PSC clock config */ |
467 | au_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd)); | 467 | __raw_writel(wd->pm[0] | PSC_SEL_PS_AC97MODE, PSC_SEL(wd)); |
468 | au_sync(); | 468 | wmb(); /* drain writebuffer */ |
469 | 469 | ||
470 | /* after this point the ac97 core will cold-reset the codec. | 470 | /* after this point the ac97 core will cold-reset the codec. |
471 | * During cold-reset the PSC is reinitialized and the last | 471 | * During cold-reset the PSC is reinitialized and the last |
diff --git a/sound/soc/au1x/psc-i2s.c b/sound/soc/au1x/psc-i2s.c index fe923a7bdc39..814beffc56f2 100644 --- a/sound/soc/au1x/psc-i2s.c +++ b/sound/soc/au1x/psc-i2s.c | |||
@@ -120,10 +120,10 @@ static int au1xpsc_i2s_hw_params(struct snd_pcm_substream *substream, | |||
120 | unsigned long stat; | 120 | unsigned long stat; |
121 | 121 | ||
122 | /* check if the PSC is already streaming data */ | 122 | /* check if the PSC is already streaming data */ |
123 | stat = au_readl(I2S_STAT(pscdata)); | 123 | stat = __raw_readl(I2S_STAT(pscdata)); |
124 | if (stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB)) { | 124 | if (stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB)) { |
125 | /* reject parameters not currently set up in hardware */ | 125 | /* reject parameters not currently set up in hardware */ |
126 | cfgbits = au_readl(I2S_CFG(pscdata)); | 126 | cfgbits = __raw_readl(I2S_CFG(pscdata)); |
127 | if ((PSC_I2SCFG_GET_LEN(cfgbits) != params->msbits) || | 127 | if ((PSC_I2SCFG_GET_LEN(cfgbits) != params->msbits) || |
128 | (params_rate(params) != pscdata->rate)) | 128 | (params_rate(params) != pscdata->rate)) |
129 | return -EINVAL; | 129 | return -EINVAL; |
@@ -149,33 +149,33 @@ static int au1xpsc_i2s_configure(struct au1xpsc_audio_data *pscdata) | |||
149 | unsigned long tmo; | 149 | unsigned long tmo; |
150 | 150 | ||
151 | /* bring PSC out of sleep, and configure I2S unit */ | 151 | /* bring PSC out of sleep, and configure I2S unit */ |
152 | au_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata)); | 152 | __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata)); |
153 | au_sync(); | 153 | wmb(); /* drain writebuffer */ |
154 | 154 | ||
155 | tmo = 1000000; | 155 | tmo = 1000000; |
156 | while (!(au_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo) | 156 | while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_SR) && tmo) |
157 | tmo--; | 157 | tmo--; |
158 | 158 | ||
159 | if (!tmo) | 159 | if (!tmo) |
160 | goto psc_err; | 160 | goto psc_err; |
161 | 161 | ||
162 | au_writel(0, I2S_CFG(pscdata)); | 162 | __raw_writel(0, I2S_CFG(pscdata)); |
163 | au_sync(); | 163 | wmb(); /* drain writebuffer */ |
164 | au_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata)); | 164 | __raw_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata)); |
165 | au_sync(); | 165 | wmb(); /* drain writebuffer */ |
166 | 166 | ||
167 | /* wait for I2S controller to become ready */ | 167 | /* wait for I2S controller to become ready */ |
168 | tmo = 1000000; | 168 | tmo = 1000000; |
169 | while (!(au_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo) | 169 | while (!(__raw_readl(I2S_STAT(pscdata)) & PSC_I2SSTAT_DR) && tmo) |
170 | tmo--; | 170 | tmo--; |
171 | 171 | ||
172 | if (tmo) | 172 | if (tmo) |
173 | return 0; | 173 | return 0; |
174 | 174 | ||
175 | psc_err: | 175 | psc_err: |
176 | au_writel(0, I2S_CFG(pscdata)); | 176 | __raw_writel(0, I2S_CFG(pscdata)); |
177 | au_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata)); | 177 | __raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata)); |
178 | au_sync(); | 178 | wmb(); /* drain writebuffer */ |
179 | return -ETIMEDOUT; | 179 | return -ETIMEDOUT; |
180 | } | 180 | } |
181 | 181 | ||
@@ -187,26 +187,26 @@ static int au1xpsc_i2s_start(struct au1xpsc_audio_data *pscdata, int stype) | |||
187 | ret = 0; | 187 | ret = 0; |
188 | 188 | ||
189 | /* if both TX and RX are idle, configure the PSC */ | 189 | /* if both TX and RX are idle, configure the PSC */ |
190 | stat = au_readl(I2S_STAT(pscdata)); | 190 | stat = __raw_readl(I2S_STAT(pscdata)); |
191 | if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) { | 191 | if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) { |
192 | ret = au1xpsc_i2s_configure(pscdata); | 192 | ret = au1xpsc_i2s_configure(pscdata); |
193 | if (ret) | 193 | if (ret) |
194 | goto out; | 194 | goto out; |
195 | } | 195 | } |
196 | 196 | ||
197 | au_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata)); | 197 | __raw_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata)); |
198 | au_sync(); | 198 | wmb(); /* drain writebuffer */ |
199 | au_writel(I2SPCR_START(stype), I2S_PCR(pscdata)); | 199 | __raw_writel(I2SPCR_START(stype), I2S_PCR(pscdata)); |
200 | au_sync(); | 200 | wmb(); /* drain writebuffer */ |
201 | 201 | ||
202 | /* wait for start confirmation */ | 202 | /* wait for start confirmation */ |
203 | tmo = 1000000; | 203 | tmo = 1000000; |
204 | while (!(au_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo) | 204 | while (!(__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo) |
205 | tmo--; | 205 | tmo--; |
206 | 206 | ||
207 | if (!tmo) { | 207 | if (!tmo) { |
208 | au_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); | 208 | __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); |
209 | au_sync(); | 209 | wmb(); /* drain writebuffer */ |
210 | ret = -ETIMEDOUT; | 210 | ret = -ETIMEDOUT; |
211 | } | 211 | } |
212 | out: | 212 | out: |
@@ -217,21 +217,21 @@ static int au1xpsc_i2s_stop(struct au1xpsc_audio_data *pscdata, int stype) | |||
217 | { | 217 | { |
218 | unsigned long tmo, stat; | 218 | unsigned long tmo, stat; |
219 | 219 | ||
220 | au_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); | 220 | __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); |
221 | au_sync(); | 221 | wmb(); /* drain writebuffer */ |
222 | 222 | ||
223 | /* wait for stop confirmation */ | 223 | /* wait for stop confirmation */ |
224 | tmo = 1000000; | 224 | tmo = 1000000; |
225 | while ((au_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo) | 225 | while ((__raw_readl(I2S_STAT(pscdata)) & I2SSTAT_BUSY(stype)) && tmo) |
226 | tmo--; | 226 | tmo--; |
227 | 227 | ||
228 | /* if both TX and RX are idle, disable PSC */ | 228 | /* if both TX and RX are idle, disable PSC */ |
229 | stat = au_readl(I2S_STAT(pscdata)); | 229 | stat = __raw_readl(I2S_STAT(pscdata)); |
230 | if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) { | 230 | if (!(stat & (PSC_I2SSTAT_TB | PSC_I2SSTAT_RB))) { |
231 | au_writel(0, I2S_CFG(pscdata)); | 231 | __raw_writel(0, I2S_CFG(pscdata)); |
232 | au_sync(); | 232 | wmb(); /* drain writebuffer */ |
233 | au_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata)); | 233 | __raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata)); |
234 | au_sync(); | 234 | wmb(); /* drain writebuffer */ |
235 | } | 235 | } |
236 | return 0; | 236 | return 0; |
237 | } | 237 | } |
@@ -332,12 +332,12 @@ static int au1xpsc_i2s_drvprobe(struct platform_device *pdev) | |||
332 | /* preserve PSC clock source set up by platform (dev.platform_data | 332 | /* preserve PSC clock source set up by platform (dev.platform_data |
333 | * is already occupied by soc layer) | 333 | * is already occupied by soc layer) |
334 | */ | 334 | */ |
335 | sel = au_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK; | 335 | sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK; |
336 | au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); | 336 | __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); |
337 | au_sync(); | 337 | wmb(); /* drain writebuffer */ |
338 | au_writel(PSC_SEL_PS_I2SMODE | sel, PSC_SEL(wd)); | 338 | __raw_writel(PSC_SEL_PS_I2SMODE | sel, PSC_SEL(wd)); |
339 | au_writel(0, I2S_CFG(wd)); | 339 | __raw_writel(0, I2S_CFG(wd)); |
340 | au_sync(); | 340 | wmb(); /* drain writebuffer */ |
341 | 341 | ||
342 | /* preconfigure: set max rx/tx fifo depths */ | 342 | /* preconfigure: set max rx/tx fifo depths */ |
343 | wd->cfg |= PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8; | 343 | wd->cfg |= PSC_I2SCFG_RT_FIFO8 | PSC_I2SCFG_TT_FIFO8; |
@@ -364,10 +364,10 @@ static int au1xpsc_i2s_drvremove(struct platform_device *pdev) | |||
364 | 364 | ||
365 | snd_soc_unregister_component(&pdev->dev); | 365 | snd_soc_unregister_component(&pdev->dev); |
366 | 366 | ||
367 | au_writel(0, I2S_CFG(wd)); | 367 | __raw_writel(0, I2S_CFG(wd)); |
368 | au_sync(); | 368 | wmb(); /* drain writebuffer */ |
369 | au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); | 369 | __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); |
370 | au_sync(); | 370 | wmb(); /* drain writebuffer */ |
371 | 371 | ||
372 | return 0; | 372 | return 0; |
373 | } | 373 | } |
@@ -378,12 +378,12 @@ static int au1xpsc_i2s_drvsuspend(struct device *dev) | |||
378 | struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); | 378 | struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); |
379 | 379 | ||
380 | /* save interesting register and disable PSC */ | 380 | /* save interesting register and disable PSC */ |
381 | wd->pm[0] = au_readl(PSC_SEL(wd)); | 381 | wd->pm[0] = __raw_readl(PSC_SEL(wd)); |
382 | 382 | ||
383 | au_writel(0, I2S_CFG(wd)); | 383 | __raw_writel(0, I2S_CFG(wd)); |
384 | au_sync(); | 384 | wmb(); /* drain writebuffer */ |
385 | au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); | 385 | __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); |
386 | au_sync(); | 386 | wmb(); /* drain writebuffer */ |
387 | 387 | ||
388 | return 0; | 388 | return 0; |
389 | } | 389 | } |
@@ -393,12 +393,12 @@ static int au1xpsc_i2s_drvresume(struct device *dev) | |||
393 | struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); | 393 | struct au1xpsc_audio_data *wd = dev_get_drvdata(dev); |
394 | 394 | ||
395 | /* select I2S mode and PSC clock */ | 395 | /* select I2S mode and PSC clock */ |
396 | au_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); | 396 | __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); |
397 | au_sync(); | 397 | wmb(); /* drain writebuffer */ |
398 | au_writel(0, PSC_SEL(wd)); | 398 | __raw_writel(0, PSC_SEL(wd)); |
399 | au_sync(); | 399 | wmb(); /* drain writebuffer */ |
400 | au_writel(wd->pm[0], PSC_SEL(wd)); | 400 | __raw_writel(wd->pm[0], PSC_SEL(wd)); |
401 | au_sync(); | 401 | wmb(); /* drain writebuffer */ |
402 | 402 | ||
403 | return 0; | 403 | return 0; |
404 | } | 404 | } |
diff --git a/sound/soc/au1x/psc.h b/sound/soc/au1x/psc.h index b16b2e02e0c9..74dffeb641fa 100644 --- a/sound/soc/au1x/psc.h +++ b/sound/soc/au1x/psc.h | |||
@@ -27,16 +27,16 @@ struct au1xpsc_audio_data { | |||
27 | }; | 27 | }; |
28 | 28 | ||
29 | /* easy access macros */ | 29 | /* easy access macros */ |
30 | #define PSC_CTRL(x) ((unsigned long)((x)->mmio) + PSC_CTRL_OFFSET) | 30 | #define PSC_CTRL(x) ((x)->mmio + PSC_CTRL_OFFSET) |
31 | #define PSC_SEL(x) ((unsigned long)((x)->mmio) + PSC_SEL_OFFSET) | 31 | #define PSC_SEL(x) ((x)->mmio + PSC_SEL_OFFSET) |
32 | #define I2S_STAT(x) ((unsigned long)((x)->mmio) + PSC_I2SSTAT_OFFSET) | 32 | #define I2S_STAT(x) ((x)->mmio + PSC_I2SSTAT_OFFSET) |
33 | #define I2S_CFG(x) ((unsigned long)((x)->mmio) + PSC_I2SCFG_OFFSET) | 33 | #define I2S_CFG(x) ((x)->mmio + PSC_I2SCFG_OFFSET) |
34 | #define I2S_PCR(x) ((unsigned long)((x)->mmio) + PSC_I2SPCR_OFFSET) | 34 | #define I2S_PCR(x) ((x)->mmio + PSC_I2SPCR_OFFSET) |
35 | #define AC97_CFG(x) ((unsigned long)((x)->mmio) + PSC_AC97CFG_OFFSET) | 35 | #define AC97_CFG(x) ((x)->mmio + PSC_AC97CFG_OFFSET) |
36 | #define AC97_CDC(x) ((unsigned long)((x)->mmio) + PSC_AC97CDC_OFFSET) | 36 | #define AC97_CDC(x) ((x)->mmio + PSC_AC97CDC_OFFSET) |
37 | #define AC97_EVNT(x) ((unsigned long)((x)->mmio) + PSC_AC97EVNT_OFFSET) | 37 | #define AC97_EVNT(x) ((x)->mmio + PSC_AC97EVNT_OFFSET) |
38 | #define AC97_PCR(x) ((unsigned long)((x)->mmio) + PSC_AC97PCR_OFFSET) | 38 | #define AC97_PCR(x) ((x)->mmio + PSC_AC97PCR_OFFSET) |
39 | #define AC97_RST(x) ((unsigned long)((x)->mmio) + PSC_AC97RST_OFFSET) | 39 | #define AC97_RST(x) ((x)->mmio + PSC_AC97RST_OFFSET) |
40 | #define AC97_STAT(x) ((unsigned long)((x)->mmio) + PSC_AC97STAT_OFFSET) | 40 | #define AC97_STAT(x) ((x)->mmio + PSC_AC97STAT_OFFSET) |
41 | 41 | ||
42 | #endif | 42 | #endif |