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authorM R Swami Reddy <mr.swami.reddy@ti.com>2012-03-30 06:33:43 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-04-01 06:35:41 -0400
commitdbf7a733f5fb9da9de750716ec7c7615c30cbfb8 (patch)
tree0039fbd28df66cc0f26b564918f3d5867727361f /sound
parent30d436a64415e6d01b8696d6288abe7ad0b383b5 (diff)
ASoC: Support TI LM49453 Audio driver
Signed-off-by: M R Swami Reddy <mr.swami.reddy@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/codecs/Kconfig4
-rw-r--r--sound/soc/codecs/Makefile4
-rw-r--r--sound/soc/codecs/lm49453.c1554
-rw-r--r--sound/soc/codecs/lm49453.h380
4 files changed, 1941 insertions, 1 deletions
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index e314a66b30cd..2e51eb08b303 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -37,6 +37,7 @@ config SND_SOC_ALL_CODECS
37 select SND_SOC_DFBMCS320 37 select SND_SOC_DFBMCS320
38 select SND_SOC_JZ4740_CODEC 38 select SND_SOC_JZ4740_CODEC
39 select SND_SOC_LM4857 if I2C 39 select SND_SOC_LM4857 if I2C
40 select SND_SOC_LM49453 if I2C
40 select SND_SOC_MAX98088 if I2C 41 select SND_SOC_MAX98088 if I2C
41 select SND_SOC_MAX98095 if I2C 42 select SND_SOC_MAX98095 if I2C
42 select SND_SOC_MAX9850 if I2C 43 select SND_SOC_MAX9850 if I2C
@@ -218,6 +219,9 @@ config SND_SOC_DFBMCS320
218config SND_SOC_DMIC 219config SND_SOC_DMIC
219 tristate 220 tristate
220 221
222config SND_SOC_LM49453
223 tristate
224
221config SND_SOC_MAX98088 225config SND_SOC_MAX98088
222 tristate 226 tristate
223 227
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 9108ee992395..db61c4499715 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -25,6 +25,7 @@ snd-soc-dmic-objs := dmic.o
25snd-soc-jz4740-codec-objs := jz4740.o 25snd-soc-jz4740-codec-objs := jz4740.o
26snd-soc-l3-objs := l3.o 26snd-soc-l3-objs := l3.o
27snd-soc-lm4857-objs := lm4857.o 27snd-soc-lm4857-objs := lm4857.o
28snd-soc-lm49453-objs := lm49453.o
28snd-soc-max9768-objs := max9768.o 29snd-soc-max9768-objs := max9768.o
29snd-soc-max98088-objs := max98088.o 30snd-soc-max98088-objs := max98088.o
30snd-soc-max98095-objs := max98095.o 31snd-soc-max98095-objs := max98095.o
@@ -129,9 +130,10 @@ obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o
129obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o 130obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o
130obj-$(CONFIG_SND_SOC_DFBMCS320) += snd-soc-dfbmcs320.o 131obj-$(CONFIG_SND_SOC_DFBMCS320) += snd-soc-dfbmcs320.o
131obj-$(CONFIG_SND_SOC_DMIC) += snd-soc-dmic.o 132obj-$(CONFIG_SND_SOC_DMIC) += snd-soc-dmic.o
133obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o
132obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o 134obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o
133obj-$(CONFIG_SND_SOC_LM4857) += snd-soc-lm4857.o 135obj-$(CONFIG_SND_SOC_LM4857) += snd-soc-lm4857.o
134obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o 136obj-$(CONFIG_SND_SOC_LM49453) += snd-soc-lm49453.o
135obj-$(CONFIG_SND_SOC_MAX9768) += snd-soc-max9768.o 137obj-$(CONFIG_SND_SOC_MAX9768) += snd-soc-max9768.o
136obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o 138obj-$(CONFIG_SND_SOC_MAX98088) += snd-soc-max98088.o
137obj-$(CONFIG_SND_SOC_MAX98095) += snd-soc-max98095.o 139obj-$(CONFIG_SND_SOC_MAX98095) += snd-soc-max98095.o
diff --git a/sound/soc/codecs/lm49453.c b/sound/soc/codecs/lm49453.c
new file mode 100644
index 000000000000..744063da40d5
--- /dev/null
+++ b/sound/soc/codecs/lm49453.c
@@ -0,0 +1,1554 @@
1/*
2 * lm49453.c - LM49453 ALSA Soc Audio driver
3 *
4 * Copyright (c) 2012 Texas Instruments, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * Initially based on sound/soc/codecs/wm8350.c
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/version.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/regmap.h>
22#include <linux/slab.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/soc-dapm.h>
28#include <sound/tlv.h>
29#include <sound/jack.h>
30#include <sound/initval.h>
31#include <asm/div64.h>
32#include "lm49453.h"
33
34static struct reg_default lm49453_reg_defs[] = {
35 { 0, 0x00 },
36 { 1, 0x00 },
37 { 2, 0x00 },
38 { 3, 0x00 },
39 { 4, 0x00 },
40 { 5, 0x00 },
41 { 6, 0x00 },
42 { 7, 0x00 },
43 { 8, 0x00 },
44 { 9, 0x00 },
45 { 10, 0x00 },
46 { 11, 0x00 },
47 { 12, 0x00 },
48 { 13, 0x00 },
49 { 14, 0x00 },
50 { 15, 0x00 },
51 { 16, 0x00 },
52 { 17, 0x00 },
53 { 18, 0x00 },
54 { 19, 0x00 },
55 { 20, 0x00 },
56 { 21, 0x00 },
57 { 22, 0x00 },
58 { 23, 0x00 },
59 { 32, 0x00 },
60 { 33, 0x00 },
61 { 35, 0x00 },
62 { 36, 0x00 },
63 { 37, 0x00 },
64 { 46, 0x00 },
65 { 48, 0x00 },
66 { 49, 0x00 },
67 { 51, 0x00 },
68 { 56, 0x00 },
69 { 58, 0x00 },
70 { 59, 0x00 },
71 { 60, 0x00 },
72 { 61, 0x00 },
73 { 62, 0x00 },
74 { 63, 0x00 },
75 { 64, 0x00 },
76 { 65, 0x00 },
77 { 66, 0x00 },
78 { 67, 0x00 },
79 { 68, 0x00 },
80 { 69, 0x00 },
81 { 70, 0x00 },
82 { 71, 0x00 },
83 { 72, 0x00 },
84 { 73, 0x00 },
85 { 74, 0x00 },
86 { 75, 0x00 },
87 { 76, 0x00 },
88 { 77, 0x00 },
89 { 78, 0x00 },
90 { 79, 0x00 },
91 { 80, 0x00 },
92 { 81, 0x00 },
93 { 82, 0x00 },
94 { 83, 0x00 },
95 { 85, 0x00 },
96 { 85, 0x00 },
97 { 86, 0x00 },
98 { 87, 0x00 },
99 { 88, 0x00 },
100 { 89, 0x00 },
101 { 90, 0x00 },
102 { 91, 0x00 },
103 { 92, 0x00 },
104 { 93, 0x00 },
105 { 94, 0x00 },
106 { 95, 0x00 },
107 { 96, 0x01 },
108 { 97, 0x00 },
109 { 98, 0x00 },
110 { 99, 0x00 },
111 { 100, 0x00 },
112 { 101, 0x00 },
113 { 102, 0x00 },
114 { 103, 0x01 },
115 { 105, 0x01 },
116 { 106, 0x00 },
117 { 107, 0x01 },
118 { 107, 0x00 },
119 { 108, 0x00 },
120 { 109, 0x00 },
121 { 110, 0x00 },
122 { 111, 0x02 },
123 { 112, 0x02 },
124 { 113, 0x00 },
125 { 121, 0x80 },
126 { 122, 0xBB },
127 { 123, 0x80 },
128 { 124, 0xBB },
129 { 128, 0x00 },
130 { 130, 0x00 },
131 { 131, 0x00 },
132 { 132, 0x00 },
133 { 133, 0x0A },
134 { 134, 0x0A },
135 { 135, 0x0A },
136 { 136, 0x0F },
137 { 137, 0x00 },
138 { 138, 0x73 },
139 { 139, 0x33 },
140 { 140, 0x73 },
141 { 141, 0x33 },
142 { 142, 0x73 },
143 { 143, 0x33 },
144 { 144, 0x73 },
145 { 145, 0x33 },
146 { 146, 0x73 },
147 { 147, 0x33 },
148 { 148, 0x73 },
149 { 149, 0x33 },
150 { 150, 0x73 },
151 { 151, 0x33 },
152 { 152, 0x00 },
153 { 153, 0x00 },
154 { 154, 0x00 },
155 { 155, 0x00 },
156 { 176, 0x00 },
157 { 177, 0x00 },
158 { 178, 0x00 },
159 { 179, 0x00 },
160 { 180, 0x00 },
161 { 181, 0x00 },
162 { 182, 0x00 },
163 { 183, 0x00 },
164 { 184, 0x00 },
165 { 185, 0x00 },
166 { 186, 0x00 },
167 { 189, 0x00 },
168 { 188, 0x00 },
169 { 194, 0x00 },
170 { 195, 0x00 },
171 { 196, 0x00 },
172 { 197, 0x00 },
173 { 200, 0x00 },
174 { 201, 0x00 },
175 { 202, 0x00 },
176 { 203, 0x00 },
177 { 204, 0x00 },
178 { 205, 0x00 },
179 { 208, 0x00 },
180 { 209, 0x00 },
181 { 210, 0x00 },
182 { 211, 0x00 },
183 { 213, 0x00 },
184 { 214, 0x00 },
185 { 215, 0x00 },
186 { 216, 0x00 },
187 { 217, 0x00 },
188 { 218, 0x00 },
189 { 219, 0x00 },
190 { 221, 0x00 },
191 { 222, 0x00 },
192 { 224, 0x00 },
193 { 225, 0x00 },
194 { 226, 0x00 },
195 { 227, 0x00 },
196 { 228, 0x00 },
197 { 229, 0x00 },
198 { 230, 0x13 },
199 { 231, 0x00 },
200 { 232, 0x80 },
201 { 233, 0x0C },
202 { 234, 0xDD },
203 { 235, 0x00 },
204 { 236, 0x04 },
205 { 237, 0x00 },
206 { 238, 0x00 },
207 { 239, 0x00 },
208 { 240, 0x00 },
209 { 241, 0x00 },
210 { 242, 0x00 },
211 { 243, 0x00 },
212 { 244, 0x00 },
213 { 245, 0x00 },
214 { 248, 0x00 },
215 { 249, 0x00 },
216 { 254, 0x00 },
217 { 255, 0x00 },
218};
219
220/* codec private data */
221struct lm49453_priv {
222 struct regmap *regmap;
223 int fs_rate;
224};
225
226/* capture path controls */
227
228static const char *lm49453_mic2mode_text[] = {"Single Ended", "Differential"};
229
230static const SOC_ENUM_SINGLE_DECL(lm49453_mic2mode_enum, LM49453_P0_MICR_REG, 5,
231 lm49453_mic2mode_text);
232
233static const char *lm49453_dmic_cfg_text[] = {"DMICDAT1", "DMICDAT2"};
234
235static const SOC_ENUM_SINGLE_DECL(lm49453_dmic12_cfg_enum,
236 LM49453_P0_DIGITAL_MIC1_CONFIG_REG,
237 7, lm49453_dmic_cfg_text);
238
239static const SOC_ENUM_SINGLE_DECL(lm49453_dmic34_cfg_enum,
240 LM49453_P0_DIGITAL_MIC2_CONFIG_REG,
241 7, lm49453_dmic_cfg_text);
242
243/* MUX Controls */
244static const char *lm49453_adcl_mux_text[] = { "MIC1", "Aux_L" };
245
246static const char *lm49453_adcr_mux_text[] = { "MIC2", "Aux_R" };
247
248static const struct soc_enum lm49453_adcl_enum =
249 SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 0,
250 ARRAY_SIZE(lm49453_adcl_mux_text),
251 lm49453_adcl_mux_text);
252
253static const struct soc_enum lm49453_adcr_enum =
254 SOC_ENUM_SINGLE(LM49453_P0_ANALOG_MIXER_ADC_REG, 1,
255 ARRAY_SIZE(lm49453_adcr_mux_text),
256 lm49453_adcr_mux_text);
257
258static const struct snd_kcontrol_new lm49453_adcl_mux_control =
259 SOC_DAPM_ENUM("ADC Left Mux", lm49453_adcl_enum);
260
261static const struct snd_kcontrol_new lm49453_adcr_mux_control =
262 SOC_DAPM_ENUM("ADC Right Mux", lm49453_adcr_enum);
263
264static const struct snd_kcontrol_new lm49453_headset_left_mixer[] = {
265SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPL1_REG, 0, 1, 0),
266SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPL1_REG, 1, 1, 0),
267SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPL1_REG, 2, 1, 0),
268SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPL1_REG, 3, 1, 0),
269SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPL1_REG, 4, 1, 0),
270SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPL1_REG, 5, 1, 0),
271SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPL1_REG, 6, 1, 0),
272SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPL1_REG, 7, 1, 0),
273SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPL2_REG, 0, 1, 0),
274SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPL2_REG, 1, 1, 0),
275SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPL2_REG, 2, 1, 0),
276SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPL2_REG, 3, 1, 0),
277SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPL2_REG, 4, 1, 0),
278SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPL2_REG, 5, 1, 0),
279SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPL2_REG, 6, 1, 0),
280SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPL2_REG, 7, 1, 0),
281SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 0, 0, 0),
282};
283
284static const struct snd_kcontrol_new lm49453_headset_right_mixer[] = {
285SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPR1_REG, 0, 1, 0),
286SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPR1_REG, 1, 1, 0),
287SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPR1_REG, 2, 1, 0),
288SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPR1_REG, 3, 1, 0),
289SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPR1_REG, 4, 1, 0),
290SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPR1_REG, 5, 1, 0),
291SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPR1_REG, 6, 1, 0),
292SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPR1_REG, 7, 1, 0),
293SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPR2_REG, 0, 1, 0),
294SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPR2_REG, 1, 1, 0),
295SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHPR2_REG, 2, 1, 0),
296SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHPR2_REG, 3, 1, 0),
297SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHPR2_REG, 4, 1, 0),
298SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPR2_REG, 5, 1, 0),
299SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHPR2_REG, 6, 1, 0),
300SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHPR2_REG, 7, 1, 0),
301SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 1, 0, 0),
302};
303
304static const struct snd_kcontrol_new lm49453_speaker_left_mixer[] = {
305SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSL1_REG, 0, 1, 0),
306SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSL1_REG, 1, 1, 0),
307SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSL1_REG, 2, 1, 0),
308SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSL1_REG, 3, 1, 0),
309SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSL1_REG, 4, 1, 0),
310SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSL1_REG, 5, 1, 0),
311SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSL1_REG, 6, 1, 0),
312SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSL1_REG, 7, 1, 0),
313SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSL2_REG, 0, 1, 0),
314SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSL2_REG, 1, 1, 0),
315SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSL2_REG, 2, 1, 0),
316SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSL2_REG, 3, 1, 0),
317SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSL2_REG, 4, 1, 0),
318SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSL2_REG, 5, 1, 0),
319SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSL2_REG, 6, 1, 0),
320SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSL2_REG, 7, 1, 0),
321SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 2, 0, 0),
322};
323
324static const struct snd_kcontrol_new lm49453_speaker_right_mixer[] = {
325SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLSR1_REG, 0, 1, 0),
326SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLSR1_REG, 1, 1, 0),
327SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLSR1_REG, 2, 1, 0),
328SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLSR1_REG, 3, 1, 0),
329SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLSR1_REG, 4, 1, 0),
330SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLSR1_REG, 5, 1, 0),
331SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLSR1_REG, 6, 1, 0),
332SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLSR1_REG, 7, 1, 0),
333SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLSR2_REG, 0, 1, 0),
334SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLSR2_REG, 1, 1, 0),
335SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLSR2_REG, 2, 1, 0),
336SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLSR2_REG, 3, 1, 0),
337SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLSR2_REG, 4, 1, 0),
338SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSR2_REG, 5, 1, 0),
339SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLSR2_REG, 6, 1, 0),
340SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLSR2_REG, 7, 1, 0),
341SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 3, 0, 0),
342};
343
344static const struct snd_kcontrol_new lm49453_haptic_left_mixer[] = {
345SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAL1_REG, 0, 1, 0),
346SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAL1_REG, 1, 1, 0),
347SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAL1_REG, 2, 1, 0),
348SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAL1_REG, 3, 1, 0),
349SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAL1_REG, 4, 1, 0),
350SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAL1_REG, 5, 1, 0),
351SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAL1_REG, 6, 1, 0),
352SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAL1_REG, 7, 1, 0),
353SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAL2_REG, 0, 1, 0),
354SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAL2_REG, 1, 1, 0),
355SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAL2_REG, 2, 1, 0),
356SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAL2_REG, 3, 1, 0),
357SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAL2_REG, 4, 1, 0),
358SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAL2_REG, 5, 1, 0),
359SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAL2_REG, 6, 1, 0),
360SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAL2_REG, 7, 1, 0),
361SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 4, 0, 0),
362};
363
364static const struct snd_kcontrol_new lm49453_haptic_right_mixer[] = {
365SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHAR1_REG, 0, 1, 0),
366SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHAR1_REG, 1, 1, 0),
367SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHAR1_REG, 2, 1, 0),
368SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHAR1_REG, 3, 1, 0),
369SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHAR1_REG, 4, 1, 0),
370SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHAR1_REG, 5, 1, 0),
371SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHAR1_REG, 6, 1, 0),
372SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHAR1_REG, 7, 1, 0),
373SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHAR2_REG, 0, 1, 0),
374SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHAR2_REG, 1, 1, 0),
375SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACHAR2_REG, 2, 1, 0),
376SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACHAR2_REG, 3, 1, 0),
377SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACHAR2_REG, 4, 1, 0),
378SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAR2_REG, 5, 1, 0),
379SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACHAR2_REG, 6, 1, 0),
380SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACHAR2_REG, 7, 1, 0),
381SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 5, 0, 0),
382};
383
384static const struct snd_kcontrol_new lm49453_lineout_left_mixer[] = {
385SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOL1_REG, 0, 1, 0),
386SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOL1_REG, 1, 1, 0),
387SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOL1_REG, 2, 1, 0),
388SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOL1_REG, 3, 1, 0),
389SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOL1_REG, 4, 1, 0),
390SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOL1_REG, 5, 1, 0),
391SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOL1_REG, 6, 1, 0),
392SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOL1_REG, 7, 1, 0),
393SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOL2_REG, 0, 1, 0),
394SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOL2_REG, 1, 1, 0),
395SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOL2_REG, 2, 1, 0),
396SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOL2_REG, 3, 1, 0),
397SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOL2_REG, 4, 1, 0),
398SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOL2_REG, 5, 1, 0),
399SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOL2_REG, 6, 1, 0),
400SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOL2_REG, 7, 1, 0),
401SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 6, 0, 0),
402};
403
404static const struct snd_kcontrol_new lm49453_lineout_right_mixer[] = {
405SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACLOR1_REG, 0, 1, 0),
406SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACLOR1_REG, 1, 1, 0),
407SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACLOR1_REG, 2, 1, 0),
408SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACLOR1_REG, 3, 1, 0),
409SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACLOR1_REG, 4, 1, 0),
410SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACLOR1_REG, 5, 1, 0),
411SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACLOR1_REG, 6, 1, 0),
412SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACLOR1_REG, 7, 1, 0),
413SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACLOR2_REG, 0, 1, 0),
414SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACLOR2_REG, 1, 1, 0),
415SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_DACLOR2_REG, 2, 1, 0),
416SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_DACLOR2_REG, 3, 1, 0),
417SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_DACLOR2_REG, 4, 1, 0),
418SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOR2_REG, 5, 1, 0),
419SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_DACLOR2_REG, 6, 1, 0),
420SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_DACLOR2_REG, 7, 1, 0),
421SOC_DAPM_SINGLE("Sidetone Switch", LM49453_P0_STN_SEL_REG, 7, 0, 0),
422};
423
424static const struct snd_kcontrol_new lm49453_port1_tx1_mixer[] = {
425SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX1_REG, 0, 1, 0),
426SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX1_REG, 1, 1, 0),
427SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX1_REG, 2, 1, 0),
428SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX1_REG, 3, 1, 0),
429SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX1_REG, 4, 1, 0),
430SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX1_REG, 5, 1, 0),
431SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT1_TX1_REG, 6, 1, 0),
432SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT1_TX1_REG, 7, 1, 0),
433};
434
435static const struct snd_kcontrol_new lm49453_port1_tx2_mixer[] = {
436SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX2_REG, 0, 1, 0),
437SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX2_REG, 1, 1, 0),
438SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX2_REG, 2, 1, 0),
439SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX2_REG, 3, 1, 0),
440SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX2_REG, 4, 1, 0),
441SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX2_REG, 5, 1, 0),
442SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT1_TX2_REG, 6, 1, 0),
443SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT1_TX2_REG, 7, 1, 0),
444};
445
446static const struct snd_kcontrol_new lm49453_port1_tx3_mixer[] = {
447SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX3_REG, 0, 1, 0),
448SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX3_REG, 1, 1, 0),
449SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX3_REG, 2, 1, 0),
450SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX3_REG, 3, 1, 0),
451SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX3_REG, 4, 1, 0),
452SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX3_REG, 5, 1, 0),
453SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_PORT1_TX3_REG, 6, 1, 0),
454};
455
456static const struct snd_kcontrol_new lm49453_port1_tx4_mixer[] = {
457SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX4_REG, 0, 1, 0),
458SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX4_REG, 1, 1, 0),
459SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX4_REG, 2, 1, 0),
460SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX4_REG, 3, 1, 0),
461SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX4_REG, 4, 1, 0),
462SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX4_REG, 5, 1, 0),
463SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_PORT1_TX4_REG, 6, 1, 0),
464};
465
466static const struct snd_kcontrol_new lm49453_port1_tx5_mixer[] = {
467SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX5_REG, 0, 1, 0),
468SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX5_REG, 1, 1, 0),
469SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX5_REG, 2, 1, 0),
470SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX5_REG, 3, 1, 0),
471SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX5_REG, 4, 1, 0),
472SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX5_REG, 5, 1, 0),
473SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_PORT1_TX5_REG, 6, 1, 0),
474};
475
476static const struct snd_kcontrol_new lm49453_port1_tx6_mixer[] = {
477SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX6_REG, 0, 1, 0),
478SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX6_REG, 1, 1, 0),
479SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX6_REG, 2, 1, 0),
480SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX6_REG, 3, 1, 0),
481SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX6_REG, 4, 1, 0),
482SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX6_REG, 5, 1, 0),
483SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_PORT1_TX6_REG, 6, 1, 0),
484};
485
486static const struct snd_kcontrol_new lm49453_port1_tx7_mixer[] = {
487SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX7_REG, 0, 1, 0),
488SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX7_REG, 1, 1, 0),
489SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX7_REG, 2, 1, 0),
490SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX7_REG, 3, 1, 0),
491SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX7_REG, 4, 1, 0),
492SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX7_REG, 5, 1, 0),
493SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_PORT1_TX7_REG, 6, 1, 0),
494};
495
496static const struct snd_kcontrol_new lm49453_port1_tx8_mixer[] = {
497SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT1_TX8_REG, 0, 1, 0),
498SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT1_TX8_REG, 1, 1, 0),
499SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT1_TX8_REG, 2, 1, 0),
500SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT1_TX8_REG, 3, 1, 0),
501SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT1_TX8_REG, 4, 1, 0),
502SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX8_REG, 5, 1, 0),
503SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_PORT1_TX8_REG, 6, 1, 0),
504};
505
506static const struct snd_kcontrol_new lm49453_port2_tx1_mixer[] = {
507SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX1_REG, 0, 1, 0),
508SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX1_REG, 1, 1, 0),
509SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX1_REG, 2, 1, 0),
510SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX1_REG, 3, 1, 0),
511SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX1_REG, 4, 1, 0),
512SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX1_REG, 5, 1, 0),
513SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_PORT2_TX1_REG, 6, 1, 0),
514SOC_DAPM_SINGLE("Port2_1 Switch", LM49453_P0_PORT2_TX1_REG, 7, 1, 0),
515};
516
517static const struct snd_kcontrol_new lm49453_port2_tx2_mixer[] = {
518SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_PORT2_TX2_REG, 0, 1, 0),
519SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_PORT2_TX2_REG, 1, 1, 0),
520SOC_DAPM_SINGLE("DMIC2L Switch", LM49453_P0_PORT2_TX2_REG, 2, 1, 0),
521SOC_DAPM_SINGLE("DMIC2R Switch", LM49453_P0_PORT2_TX2_REG, 3, 1, 0),
522SOC_DAPM_SINGLE("ADCL Switch", LM49453_P0_PORT2_TX2_REG, 4, 1, 0),
523SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX2_REG, 5, 1, 0),
524SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_PORT2_TX2_REG, 6, 1, 0),
525SOC_DAPM_SINGLE("Port2_2 Switch", LM49453_P0_PORT2_TX2_REG, 7, 1, 0),
526};
527
528/* TLV Declarations */
529static const DECLARE_TLV_DB_SCALE(digital_tlv, -7650, 150, 1);
530static const DECLARE_TLV_DB_SCALE(port_tlv, 0, 600, 0);
531
532static const struct snd_kcontrol_new lm49453_sidetone_mixer_controls[] = {
533/* Sidetone supports mono only */
534SOC_DAPM_SINGLE_TLV("Sidetone ADCL Volume", LM49453_P0_STN_VOL_ADCL_REG,
535 0, 0x3F, 0, digital_tlv),
536SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG,
537 0, 0x3F, 0, digital_tlv),
538SOC_DAPM_SINGLE_TLV("Sidetone DMIC1L Volume", LM49453_P0_STN_VOL_DMIC1L_REG,
539 0, 0x3F, 0, digital_tlv),
540SOC_DAPM_SINGLE_TLV("Sidetone DMIC1R Volume", LM49453_P0_STN_VOL_DMIC1R_REG,
541 0, 0x3F, 0, digital_tlv),
542SOC_DAPM_SINGLE_TLV("Sidetone DMIC2L Volume", LM49453_P0_STN_VOL_DMIC2L_REG,
543 0, 0x3F, 0, digital_tlv),
544SOC_DAPM_SINGLE_TLV("Sidetone DMIC2R Volume", LM49453_P0_STN_VOL_DMIC2R_REG,
545 0, 0x3F, 0, digital_tlv),
546};
547
548static const struct snd_kcontrol_new lm49453_snd_controls[] = {
549 /* mic1 and mic2 supports mono only */
550 SOC_SINGLE_TLV("Mic1 Volume", LM49453_P0_ADC_LEVELL_REG, 0, 6,
551 0, digital_tlv),
552 SOC_SINGLE_TLV("Mic2 Volume", LM49453_P0_ADC_LEVELR_REG, 0, 6,
553 0, digital_tlv),
554
555 SOC_DOUBLE_R_TLV("DMIC1 Volume", LM49453_P0_DMIC1_LEVELL_REG,
556 LM49453_P0_DMIC1_LEVELR_REG, 0, 6, 0, digital_tlv),
557 SOC_DOUBLE_R_TLV("DMIC2 Volume", LM49453_P0_DMIC2_LEVELL_REG,
558 LM49453_P0_DMIC2_LEVELR_REG, 0, 6, 0, digital_tlv),
559
560 SOC_DAPM_ENUM("Mic2Mode", lm49453_mic2mode_enum),
561 SOC_DAPM_ENUM("DMIC12 SRC", lm49453_dmic12_cfg_enum),
562 SOC_DAPM_ENUM("DMIC34 SRC", lm49453_dmic34_cfg_enum),
563
564 /* Capture path filter enable */
565 SOC_SINGLE("DMIC1 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
566 0, 1, 0),
567 SOC_SINGLE("DMIC2 HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
568 1, 1, 0),
569 SOC_SINGLE("ADC HPFilter Switch", LM49453_P0_ADC_FX_ENABLES_REG,
570 2, 1, 0),
571
572 SOC_DOUBLE_R_TLV("DAC HP Volume", LM49453_P0_DAC_HP_LEVELL_REG,
573 LM49453_P0_DAC_HP_LEVELR_REG, 0, 6, 0, digital_tlv),
574 SOC_DOUBLE_R_TLV("DAC LO Volume", LM49453_P0_DAC_LO_LEVELL_REG,
575 LM49453_P0_DAC_LO_LEVELR_REG, 0, 6, 0, digital_tlv),
576 SOC_DOUBLE_R_TLV("DAC LS Volume", LM49453_P0_DAC_LS_LEVELL_REG,
577 LM49453_P0_DAC_LS_LEVELR_REG, 0, 6, 0, digital_tlv),
578 SOC_DOUBLE_R_TLV("DAC HA Volume", LM49453_P0_DAC_HA_LEVELL_REG,
579 LM49453_P0_DAC_HA_LEVELR_REG, 0, 6, 0, digital_tlv),
580
581 SOC_SINGLE_TLV("EP Volume", LM49453_P0_DAC_LS_LEVELL_REG,
582 0, 6, 0, digital_tlv),
583
584 SOC_SINGLE_TLV("PORT1_1_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
585 0, 3, 0, port_tlv),
586 SOC_SINGLE_TLV("PORT1_2_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
587 2, 3, 0, port_tlv),
588 SOC_SINGLE_TLV("PORT1_3_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
589 4, 3, 0, port_tlv),
590 SOC_SINGLE_TLV("PORT1_4_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL1_REG,
591 6, 3, 0, port_tlv),
592 SOC_SINGLE_TLV("PORT1_5_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
593 0, 3, 0, port_tlv),
594 SOC_SINGLE_TLV("PORT1_6_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
595 2, 3, 0, port_tlv),
596 SOC_SINGLE_TLV("PORT1_7_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
597 4, 3, 0, port_tlv),
598 SOC_SINGLE_TLV("PORT1_8_RX_LVL Volume", LM49453_P0_PORT1_RX_LVL2_REG,
599 6, 3, 0, port_tlv),
600
601 SOC_SINGLE_TLV("PORT2_1_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
602 0, 3, 0, port_tlv),
603 SOC_SINGLE_TLV("PORT2_2_RX_LVL Volume", LM49453_P0_PORT2_RX_LVL_REG,
604 2, 3, 0, port_tlv),
605
606 SOC_SINGLE("Port1 Playback Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
607 1, 1, 0),
608 SOC_SINGLE("Port2 Playback Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
609 1, 1, 0),
610 SOC_SINGLE("Port1 Capture Switch", LM49453_P0_AUDIO_PORT1_BASIC_REG,
611 2, 1, 0),
612 SOC_SINGLE("Port2 Capture Switch", LM49453_P0_AUDIO_PORT2_BASIC_REG,
613 2, 1, 0)
614
615};
616
617/* DAPM widgets */
618static const struct snd_soc_dapm_widget lm49453_dapm_widgets[] = {
619
620 /* All end points HP,EP, LS, Lineout and Haptic */
621 SND_SOC_DAPM_OUTPUT("HPOUTL"),
622 SND_SOC_DAPM_OUTPUT("HPOUTR"),
623 SND_SOC_DAPM_OUTPUT("EPOUT"),
624 SND_SOC_DAPM_OUTPUT("LSOUTL"),
625 SND_SOC_DAPM_OUTPUT("LSOUTR"),
626 SND_SOC_DAPM_OUTPUT("LOOUTR"),
627 SND_SOC_DAPM_OUTPUT("LOOUTL"),
628 SND_SOC_DAPM_OUTPUT("HAOUTL"),
629 SND_SOC_DAPM_OUTPUT("HAOUTR"),
630
631 SND_SOC_DAPM_INPUT("AMIC1"),
632 SND_SOC_DAPM_INPUT("AMIC2"),
633 SND_SOC_DAPM_INPUT("DMIC1DAT"),
634 SND_SOC_DAPM_INPUT("DMIC2DAT"),
635 SND_SOC_DAPM_INPUT("AUXL"),
636 SND_SOC_DAPM_INPUT("AUXR"),
637
638 SND_SOC_DAPM_PGA("PORT1_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
639 SND_SOC_DAPM_PGA("PORT1_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
640 SND_SOC_DAPM_PGA("PORT1_3_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
641 SND_SOC_DAPM_PGA("PORT1_4_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
642 SND_SOC_DAPM_PGA("PORT1_5_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
643 SND_SOC_DAPM_PGA("PORT1_6_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
644 SND_SOC_DAPM_PGA("PORT1_7_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
645 SND_SOC_DAPM_PGA("PORT1_8_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
646 SND_SOC_DAPM_PGA("PORT2_1_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
647 SND_SOC_DAPM_PGA("PORT2_2_RX", SND_SOC_NOPM, 0, 0, NULL, 0),
648
649 SND_SOC_DAPM_SUPPLY("AMIC1Bias", LM49453_P0_MICL_REG, 6, 0, NULL, 0),
650 SND_SOC_DAPM_SUPPLY("AMIC2Bias", LM49453_P0_MICR_REG, 6, 0, NULL, 0),
651
652 /* playback path driver enables */
653 SND_SOC_DAPM_OUT_DRV("Headset Switch",
654 LM49453_P0_PMC_SETUP_REG, 0, 0, NULL, 0),
655 SND_SOC_DAPM_OUT_DRV("Earpiece Switch",
656 LM49453_P0_EP_REG, 0, 0, NULL, 0),
657 SND_SOC_DAPM_OUT_DRV("Speaker Left Switch",
658 LM49453_P0_DIS_PKVL_FB_REG, 0, 1, NULL, 0),
659 SND_SOC_DAPM_OUT_DRV("Speaker Right Switch",
660 LM49453_P0_DIS_PKVL_FB_REG, 1, 1, NULL, 0),
661 SND_SOC_DAPM_OUT_DRV("Haptic Left Switch",
662 LM49453_P0_DIS_PKVL_FB_REG, 2, 1, NULL, 0),
663 SND_SOC_DAPM_OUT_DRV("Haptic Right Switch",
664 LM49453_P0_DIS_PKVL_FB_REG, 3, 1, NULL, 0),
665
666 /* DAC */
667 SND_SOC_DAPM_DAC("HPL DAC", "Headset", SND_SOC_NOPM, 0, 0),
668 SND_SOC_DAPM_DAC("HPR DAC", "Headset", SND_SOC_NOPM, 0, 0),
669 SND_SOC_DAPM_DAC("LSL DAC", "Speaker", SND_SOC_NOPM, 0, 0),
670 SND_SOC_DAPM_DAC("LSR DAC", "Speaker", SND_SOC_NOPM, 0, 0),
671 SND_SOC_DAPM_DAC("HAL DAC", "Haptic", SND_SOC_NOPM, 0, 0),
672 SND_SOC_DAPM_DAC("HAR DAC", "Haptic", SND_SOC_NOPM, 0, 0),
673 SND_SOC_DAPM_DAC("LOL DAC", "Lineout", SND_SOC_NOPM, 0, 0),
674 SND_SOC_DAPM_DAC("LOR DAC", "Lineout", SND_SOC_NOPM, 0, 0),
675
676
677 SND_SOC_DAPM_PGA("AUXL Input",
678 LM49453_P0_ANALOG_MIXER_ADC_REG, 2, 0, NULL, 0),
679 SND_SOC_DAPM_PGA("AUXR Input",
680 LM49453_P0_ANALOG_MIXER_ADC_REG, 3, 0, NULL, 0),
681
682 SND_SOC_DAPM_PGA("Sidetone", SND_SOC_NOPM, 0, 0, NULL, 0),
683
684 /* ADC */
685 SND_SOC_DAPM_ADC("DMIC1 Left", "Capture", SND_SOC_NOPM, 1, 0),
686 SND_SOC_DAPM_ADC("DMIC1 Right", "Capture", SND_SOC_NOPM, 1, 0),
687 SND_SOC_DAPM_ADC("DMIC2 Left", "Capture", SND_SOC_NOPM, 1, 0),
688 SND_SOC_DAPM_ADC("DMIC2 Right", "Capture", SND_SOC_NOPM, 1, 0),
689
690 SND_SOC_DAPM_ADC("ADC Left", "Capture", SND_SOC_NOPM, 1, 0),
691 SND_SOC_DAPM_ADC("ADC Right", "Capture", SND_SOC_NOPM, 0, 0),
692
693 SND_SOC_DAPM_MUX("ADCL Mux", SND_SOC_NOPM, 0, 0,
694 &lm49453_adcl_mux_control),
695 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
696 &lm49453_adcr_mux_control),
697
698 SND_SOC_DAPM_MUX("Mic1 Input",
699 SND_SOC_NOPM, 0, 0, &lm49453_adcl_mux_control),
700
701 SND_SOC_DAPM_MUX("Mic2 Input",
702 SND_SOC_NOPM, 0, 0, &lm49453_adcr_mux_control),
703
704 /* AIF */
705 SND_SOC_DAPM_AIF_IN("PORT1_SDI", NULL, 0,
706 LM49453_P0_PULL_CONFIG1_REG, 2, 0),
707 SND_SOC_DAPM_AIF_IN("PORT2_SDI", NULL, 0,
708 LM49453_P0_PULL_CONFIG1_REG, 6, 0),
709
710 SND_SOC_DAPM_AIF_OUT("PORT1_SDO", NULL, 0,
711 LM49453_P0_PULL_CONFIG1_REG, 3, 0),
712 SND_SOC_DAPM_AIF_OUT("PORT2_SDO", NULL, 0,
713 LM49453_P0_PULL_CONFIG1_REG, 7, 0),
714
715 /* Port1 TX controls */
716 SND_SOC_DAPM_OUT_DRV("P1_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
717 SND_SOC_DAPM_OUT_DRV("P1_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
718 SND_SOC_DAPM_OUT_DRV("P1_3_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
719 SND_SOC_DAPM_OUT_DRV("P1_4_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
720 SND_SOC_DAPM_OUT_DRV("P1_5_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
721 SND_SOC_DAPM_OUT_DRV("P1_6_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
722 SND_SOC_DAPM_OUT_DRV("P1_7_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
723 SND_SOC_DAPM_OUT_DRV("P1_8_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
724
725 /* Port2 TX controls */
726 SND_SOC_DAPM_OUT_DRV("P2_1_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
727 SND_SOC_DAPM_OUT_DRV("P2_2_TX", SND_SOC_NOPM, 0, 0, NULL, 0),
728
729 /* Sidetone Mixer */
730 SND_SOC_DAPM_MIXER("Sidetone Mixer", SND_SOC_NOPM, 0, 0,
731 lm49453_sidetone_mixer_controls,
732 ARRAY_SIZE(lm49453_sidetone_mixer_controls)),
733
734 /* DAC MIXERS */
735 SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0,
736 lm49453_headset_left_mixer,
737 ARRAY_SIZE(lm49453_headset_left_mixer)),
738 SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0,
739 lm49453_headset_right_mixer,
740 ARRAY_SIZE(lm49453_headset_right_mixer)),
741 SND_SOC_DAPM_MIXER("LOL Mixer", SND_SOC_NOPM, 0, 0,
742 lm49453_lineout_left_mixer,
743 ARRAY_SIZE(lm49453_lineout_left_mixer)),
744 SND_SOC_DAPM_MIXER("LOR Mixer", SND_SOC_NOPM, 0, 0,
745 lm49453_lineout_right_mixer,
746 ARRAY_SIZE(lm49453_lineout_right_mixer)),
747 SND_SOC_DAPM_MIXER("LSL Mixer", SND_SOC_NOPM, 0, 0,
748 lm49453_speaker_left_mixer,
749 ARRAY_SIZE(lm49453_speaker_left_mixer)),
750 SND_SOC_DAPM_MIXER("LSR Mixer", SND_SOC_NOPM, 0, 0,
751 lm49453_speaker_right_mixer,
752 ARRAY_SIZE(lm49453_speaker_right_mixer)),
753 SND_SOC_DAPM_MIXER("HAL Mixer", SND_SOC_NOPM, 0, 0,
754 lm49453_haptic_left_mixer,
755 ARRAY_SIZE(lm49453_haptic_left_mixer)),
756 SND_SOC_DAPM_MIXER("HAR Mixer", SND_SOC_NOPM, 0, 0,
757 lm49453_haptic_right_mixer,
758 ARRAY_SIZE(lm49453_haptic_right_mixer)),
759
760 /* Capture Mixer */
761 SND_SOC_DAPM_MIXER("Port1_1 Mixer", SND_SOC_NOPM, 0, 0,
762 lm49453_port1_tx1_mixer,
763 ARRAY_SIZE(lm49453_port1_tx1_mixer)),
764 SND_SOC_DAPM_MIXER("Port1_2 Mixer", SND_SOC_NOPM, 0, 0,
765 lm49453_port1_tx2_mixer,
766 ARRAY_SIZE(lm49453_port1_tx2_mixer)),
767 SND_SOC_DAPM_MIXER("Port1_3 Mixer", SND_SOC_NOPM, 0, 0,
768 lm49453_port1_tx3_mixer,
769 ARRAY_SIZE(lm49453_port1_tx3_mixer)),
770 SND_SOC_DAPM_MIXER("Port1_4 Mixer", SND_SOC_NOPM, 0, 0,
771 lm49453_port1_tx4_mixer,
772 ARRAY_SIZE(lm49453_port1_tx4_mixer)),
773 SND_SOC_DAPM_MIXER("Port1_5 Mixer", SND_SOC_NOPM, 0, 0,
774 lm49453_port1_tx5_mixer,
775 ARRAY_SIZE(lm49453_port1_tx5_mixer)),
776 SND_SOC_DAPM_MIXER("Port1_6 Mixer", SND_SOC_NOPM, 0, 0,
777 lm49453_port1_tx6_mixer,
778 ARRAY_SIZE(lm49453_port1_tx6_mixer)),
779 SND_SOC_DAPM_MIXER("Port1_7 Mixer", SND_SOC_NOPM, 0, 0,
780 lm49453_port1_tx7_mixer,
781 ARRAY_SIZE(lm49453_port1_tx7_mixer)),
782 SND_SOC_DAPM_MIXER("Port1_8 Mixer", SND_SOC_NOPM, 0, 0,
783 lm49453_port1_tx8_mixer,
784 ARRAY_SIZE(lm49453_port1_tx8_mixer)),
785
786 SND_SOC_DAPM_MIXER("Port2_1 Mixer", SND_SOC_NOPM, 0, 0,
787 lm49453_port2_tx1_mixer,
788 ARRAY_SIZE(lm49453_port2_tx1_mixer)),
789 SND_SOC_DAPM_MIXER("Port2_2 Mixer", SND_SOC_NOPM, 0, 0,
790 lm49453_port2_tx2_mixer,
791 ARRAY_SIZE(lm49453_port2_tx2_mixer)),
792};
793
794static const struct snd_soc_dapm_route lm49453_audio_map[] = {
795 /* Port SDI mapping */
796 { "PORT1_1_RX", "Port1 Playback Switch", "PORT1_SDI" },
797 { "PORT1_2_RX", "Port1 Playback Switch", "PORT1_SDI" },
798 { "PORT1_3_RX", "Port1 Playback Switch", "PORT1_SDI" },
799 { "PORT1_4_RX", "Port1 Playback Switch", "PORT1_SDI" },
800 { "PORT1_5_RX", "Port1 Playback Switch", "PORT1_SDI" },
801 { "PORT1_6_RX", "Port1 Playback Switch", "PORT1_SDI" },
802 { "PORT1_7_RX", "Port1 Playback Switch", "PORT1_SDI" },
803 { "PORT1_8_RX", "Port1 Playback Switch", "PORT1_SDI" },
804
805 { "PORT2_1_RX", "Port2 Playback Switch", "PORT2_SDI" },
806 { "PORT2_2_RX", "Port2 Playback Switch", "PORT2_SDI" },
807
808 /* HP mapping */
809 { "HPL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
810 { "HPL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
811 { "HPL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
812 { "HPL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
813 { "HPL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
814 { "HPL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
815 { "HPL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
816 { "HPL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
817
818 { "HPL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
819 { "HPL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
820
821 { "HPL Mixer", "ADCL Switch", "ADC Left" },
822 { "HPL Mixer", "ADCR Switch", "ADC Right" },
823 { "HPL Mixer", "DMIC1L Switch", "DMIC1 Left" },
824 { "HPL Mixer", "DMIC1R Switch", "DMIC1 Right" },
825 { "HPL Mixer", "DMIC2L Switch", "DMIC2 Left" },
826 { "HPL Mixer", "DMIC2R Switch", "DMIC2 Right" },
827 { "HPL Mixer", "Sidetone Switch", "Sidetone" },
828
829 { "HPL DAC", NULL, "HPL Mixer" },
830
831 { "HPR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
832 { "HPR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
833 { "HPR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
834 { "HPR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
835 { "HPR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
836 { "HPR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
837 { "HPR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
838 { "HPR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
839
840 /* Port 2 */
841 { "HPR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
842 { "HPR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
843
844 { "HPR Mixer", "ADCL Switch", "ADC Left" },
845 { "HPR Mixer", "ADCR Switch", "ADC Right" },
846 { "HPR Mixer", "DMIC1L Switch", "DMIC1 Left" },
847 { "HPR Mixer", "DMIC1R Switch", "DMIC1 Right" },
848 { "HPR Mixer", "DMIC2L Switch", "DMIC2 Left" },
849 { "HPR Mixer", "DMIC2L Switch", "DMIC2 Right" },
850 { "HPR Mixer", "Sidetone Switch", "Sidetone" },
851
852 { "HPR DAC", NULL, "HPR Mixer" },
853
854 { "HPOUTL", "Headset Switch", "HPL DAC"},
855 { "HPOUTR", "Headset Switch", "HPR DAC"},
856
857 /* EP map */
858 { "EPOUT", "Earpiece Switch", "HPL DAC" },
859
860 /* Speaker map */
861 { "LSL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
862 { "LSL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
863 { "LSL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
864 { "LSL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
865 { "LSL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
866 { "LSL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
867 { "LSL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
868 { "LSL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
869
870 /* Port 2 */
871 { "LSL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
872 { "LSL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
873
874 { "LSL Mixer", "ADCL Switch", "ADC Left" },
875 { "LSL Mixer", "ADCR Switch", "ADC Right" },
876 { "LSL Mixer", "DMIC1L Switch", "DMIC1 Left" },
877 { "LSL Mixer", "DMIC1R Switch", "DMIC1 Right" },
878 { "LSL Mixer", "DMIC2L Switch", "DMIC2 Left" },
879 { "LSL Mixer", "DMIC2R Switch", "DMIC2 Right" },
880 { "LSL Mixer", "Sidetone Switch", "Sidetone" },
881
882 { "LSL DAC", NULL, "LSL Mixer" },
883
884 { "LSR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
885 { "LSR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
886 { "LSR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
887 { "LSR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
888 { "LSR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
889 { "LSR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
890 { "LSR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
891 { "LSR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
892
893 /* Port 2 */
894 { "LSR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
895 { "LSR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
896
897 { "LSR Mixer", "ADCL Switch", "ADC Left" },
898 { "LSR Mixer", "ADCR Switch", "ADC Right" },
899 { "LSR Mixer", "DMIC1L Switch", "DMIC1 Left" },
900 { "LSR Mixer", "DMIC1R Switch", "DMIC1 Right" },
901 { "LSR Mixer", "DMIC2L Switch", "DMIC2 Left" },
902 { "LSR Mixer", "DMIC2R Switch", "DMIC2 Right" },
903 { "LSR Mixer", "Sidetone Switch", "Sidetone" },
904
905 { "LSR DAC", NULL, "LSR Mixer" },
906
907 { "LSOUTL", "Speaker Left Switch", "LSL DAC"},
908 { "LSOUTR", "Speaker Left Switch", "LSR DAC"},
909
910 /* Haptic map */
911 { "HAL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
912 { "HAL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
913 { "HAL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
914 { "HAL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
915 { "HAL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
916 { "HAL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
917 { "HAL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
918 { "HAL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
919
920 /* Port 2 */
921 { "HAL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
922 { "HAL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
923
924 { "HAL Mixer", "ADCL Switch", "ADC Left" },
925 { "HAL Mixer", "ADCR Switch", "ADC Right" },
926 { "HAL Mixer", "DMIC1L Switch", "DMIC1 Left" },
927 { "HAL Mixer", "DMIC1R Switch", "DMIC1 Right" },
928 { "HAL Mixer", "DMIC2L Switch", "DMIC2 Left" },
929 { "HAL Mixer", "DMIC2R Switch", "DMIC2 Right" },
930 { "HAL Mixer", "Sidetone Switch", "Sidetone" },
931
932 { "HAL DAC", NULL, "HAL Mixer" },
933
934 { "HAR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
935 { "HAR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
936 { "HAR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
937 { "HAR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
938 { "HAR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
939 { "HAR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
940 { "HAR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
941 { "HAR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
942
943 /* Port 2 */
944 { "HAR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
945 { "HAR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
946
947 { "HAR Mixer", "ADCL Switch", "ADC Left" },
948 { "HAR Mixer", "ADCR Switch", "ADC Right" },
949 { "HAR Mixer", "DMIC1L Switch", "DMIC1 Left" },
950 { "HAR Mixer", "DMIC1R Switch", "DMIC1 Right" },
951 { "HAR Mixer", "DMIC2L Switch", "DMIC2 Left" },
952 { "HAR Mixer", "DMIC2R Switch", "DMIC2 Right" },
953 { "HAR Mixer", "Sideton Switch", "Sidetone" },
954
955 { "HAR DAC", NULL, "HAR Mixer" },
956
957 { "HAOUTL", "Haptic Left Switch", "HAL DAC" },
958 { "HAOUTR", "Haptic Right Switch", "HAR DAC" },
959
960 /* Lineout map */
961 { "LOL Mixer", "Port1_1 Switch", "PORT1_1_RX" },
962 { "LOL Mixer", "Port1_2 Switch", "PORT1_2_RX" },
963 { "LOL Mixer", "Port1_3 Switch", "PORT1_3_RX" },
964 { "LOL Mixer", "Port1_4 Switch", "PORT1_4_RX" },
965 { "LOL Mixer", "Port1_5 Switch", "PORT1_5_RX" },
966 { "LOL Mixer", "Port1_6 Switch", "PORT1_6_RX" },
967 { "LOL Mixer", "Port1_7 Switch", "PORT1_7_RX" },
968 { "LOL Mixer", "Port1_8 Switch", "PORT1_8_RX" },
969
970 /* Port 2 */
971 { "LOL Mixer", "Port2_1 Switch", "PORT2_1_RX" },
972 { "LOL Mixer", "Port2_2 Switch", "PORT2_2_RX" },
973
974 { "LOL Mixer", "ADCL Switch", "ADC Left" },
975 { "LOL Mixer", "ADCR Switch", "ADC Right" },
976 { "LOL Mixer", "DMIC1L Switch", "DMIC1 Left" },
977 { "LOL Mixer", "DMIC1R Switch", "DMIC1 Right" },
978 { "LOL Mixer", "DMIC2L Switch", "DMIC2 Left" },
979 { "LOL Mixer", "DMIC2R Switch", "DMIC2 Right" },
980 { "LOL Mixer", "Sidetone Switch", "Sidetone" },
981
982 { "LOL DAC", NULL, "LOL Mixer" },
983
984 { "LOR Mixer", "Port1_1 Switch", "PORT1_1_RX" },
985 { "LOR Mixer", "Port1_2 Switch", "PORT1_2_RX" },
986 { "LOR Mixer", "Port1_3 Switch", "PORT1_3_RX" },
987 { "LOR Mixer", "Port1_4 Switch", "PORT1_4_RX" },
988 { "LOR Mixer", "Port1_5 Switch", "PORT1_5_RX" },
989 { "LOR Mixer", "Port1_6 Switch", "PORT1_6_RX" },
990 { "LOR Mixer", "Port1_7 Switch", "PORT1_7_RX" },
991 { "LOR Mixer", "Port1_8 Switch", "PORT1_8_RX" },
992
993 /* Port 2 */
994 { "LOR Mixer", "Port2_1 Switch", "PORT2_1_RX" },
995 { "LOR Mixer", "Port2_2 Switch", "PORT2_2_RX" },
996
997 { "LOR Mixer", "ADCL Switch", "ADC Left" },
998 { "LOR Mixer", "ADCR Switch", "ADC Right" },
999 { "LOR Mixer", "DMIC1L Switch", "DMIC1 Left" },
1000 { "LOR Mixer", "DMIC1R Switch", "DMIC1 Right" },
1001 { "LOR Mixer", "DMIC2L Switch", "DMIC2 Left" },
1002 { "LOR Mixer", "DMIC2R Switch", "DMIC2 Right" },
1003 { "LOR Mixer", "Sidetone Switch", "Sidetone" },
1004
1005 { "LOR DAC", NULL, "LOR Mixer" },
1006
1007 { "LOOUTL", NULL, "LOL DAC" },
1008 { "LOOUTR", NULL, "LOR DAC" },
1009
1010 /* TX map */
1011 /* Port1 mappings */
1012 { "Port1_1 Mixer", "ADCL Switch", "ADC Left" },
1013 { "Port1_1 Mixer", "ADCR Switch", "ADC Right" },
1014 { "Port1_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1015 { "Port1_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1016 { "Port1_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1017 { "Port1_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1018
1019 { "Port1_2 Mixer", "ADCL Switch", "ADC Left" },
1020 { "Port1_2 Mixer", "ADCR Switch", "ADC Right" },
1021 { "Port1_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1022 { "Port1_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1023 { "Port1_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1024 { "Port1_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1025
1026 { "Port1_3 Mixer", "ADCL Switch", "ADC Left" },
1027 { "Port1_3 Mixer", "ADCR Switch", "ADC Right" },
1028 { "Port1_3 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1029 { "Port1_3 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1030 { "Port1_3 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1031 { "Port1_3 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1032
1033 { "Port1_4 Mixer", "ADCL Switch", "ADC Left" },
1034 { "Port1_4 Mixer", "ADCR Switch", "ADC Right" },
1035 { "Port1_4 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1036 { "Port1_4 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1037 { "Port1_4 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1038 { "Port1_4 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1039
1040 { "Port1_5 Mixer", "ADCL Switch", "ADC Left" },
1041 { "Port1_5 Mixer", "ADCR Switch", "ADC Right" },
1042 { "Port1_5 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1043 { "Port1_5 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1044 { "Port1_5 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1045 { "Port1_5 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1046
1047 { "Port1_6 Mixer", "ADCL Switch", "ADC Left" },
1048 { "Port1_6 Mixer", "ADCR Switch", "ADC Right" },
1049 { "Port1_6 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1050 { "Port1_6 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1051 { "Port1_6 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1052 { "Port1_6 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1053
1054 { "Port1_7 Mixer", "ADCL Switch", "ADC Left" },
1055 { "Port1_7 Mixer", "ADCR Switch", "ADC Right" },
1056 { "Port1_7 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1057 { "Port1_7 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1058 { "Port1_7 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1059 { "Port1_7 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1060
1061 { "Port1_8 Mixer", "ADCL Switch", "ADC Left" },
1062 { "Port1_8 Mixer", "ADCR Switch", "ADC Right" },
1063 { "Port1_8 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1064 { "Port1_8 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1065 { "Port1_8 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1066 { "Port1_8 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1067
1068 { "Port2_1 Mixer", "ADCL Switch", "ADC Left" },
1069 { "Port2_1 Mixer", "ADCR Switch", "ADC Right" },
1070 { "Port2_1 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1071 { "Port2_1 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1072 { "Port2_1 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1073 { "Port2_1 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1074
1075 { "Port2_2 Mixer", "ADCL Switch", "ADC Left" },
1076 { "Port2_2 Mixer", "ADCR Switch", "ADC Right" },
1077 { "Port2_2 Mixer", "DMIC1L Switch", "DMIC1 Left" },
1078 { "Port2_2 Mixer", "DMIC1R Switch", "DMIC1 Right" },
1079 { "Port2_2 Mixer", "DMIC2L Switch", "DMIC2 Left" },
1080 { "Port2_2 Mixer", "DMIC2R Switch", "DMIC2 Right" },
1081
1082 { "P1_1_TX", NULL, "Port1_1 Mixer" },
1083 { "P1_2_TX", NULL, "Port1_2 Mixer" },
1084 { "P1_3_TX", NULL, "Port1_3 Mixer" },
1085 { "P1_4_TX", NULL, "Port1_4 Mixer" },
1086 { "P1_5_TX", NULL, "Port1_5 Mixer" },
1087 { "P1_6_TX", NULL, "Port1_6 Mixer" },
1088 { "P1_7_TX", NULL, "Port1_7 Mixer" },
1089 { "P1_8_TX", NULL, "Port1_8 Mixer" },
1090
1091 { "P2_1_TX", NULL, "Port2_1 Mixer" },
1092 { "P2_2_TX", NULL, "Port2_2 Mixer" },
1093
1094 { "PORT1_SDO", "Port1 Capture Switch", "P1_1_TX"},
1095 { "PORT1_SDO", "Port1 Capture Switch", "P1_2_TX"},
1096 { "PORT1_SDO", "Port1 Capture Switch", "P1_3_TX"},
1097 { "PORT1_SDO", "Port1 Capture Switch", "P1_4_TX"},
1098 { "PORT1_SDO", "Port1 Capture Switch", "P1_5_TX"},
1099 { "PORT1_SDO", "Port1 Capture Switch", "P1_6_TX"},
1100 { "PORT1_SDO", "Port1 Capture Switch", "P1_7_TX"},
1101 { "PORT1_SDO", "Port1 Capture Switch", "P1_8_TX"},
1102
1103 { "PORT2_SDO", "Port2 Capture Switch", "P2_1_TX"},
1104 { "PORT2_SDO", "Port2 Capture Switch", "P2_2_TX"},
1105
1106 { "Mic1 Input", NULL, "AMIC1" },
1107 { "Mic2 Input", NULL, "AMIC2" },
1108
1109 { "AUXL Input", NULL, "AUXL" },
1110 { "AUXR Input", NULL, "AUXR" },
1111
1112 /* AUX connections */
1113 { "ADCL Mux", "Aux_L", "AUXL Input" },
1114 { "ADCL Mux", "MIC1", "Mic1 Input" },
1115
1116 { "ADCR Mux", "Aux_R", "AUXR Input" },
1117 { "ADCR Mux", "MIC2", "Mic2 Input" },
1118
1119 /* ADC connection */
1120 { "ADC Left", NULL, "ADCL Mux"},
1121 { "ADC Right", NULL, "ADCR Mux"},
1122
1123 { "DMIC1 Left", NULL, "DMIC1DAT"},
1124 { "DMIC1 Right", NULL, "DMIC1DAT"},
1125 { "DMIC2 Left", NULL, "DMIC2DAT"},
1126 { "DMIC2 Right", NULL, "DMIC2DAT"},
1127
1128 /* Sidetone map */
1129 { "Sidetone Mixer", NULL, "ADC Left" },
1130 { "Sidetone Mixer", NULL, "ADC Right" },
1131 { "Sidetone Mixer", NULL, "DMIC1 Left" },
1132 { "Sidetone Mixer", NULL, "DMIC1 Right" },
1133 { "Sidetone Mixer", NULL, "DMIC2 Left" },
1134 { "Sidetone Mixer", NULL, "DMIC2 Right" },
1135
1136 { "Sidetone", "Sidetone Switch", "Sidetone Mixer" },
1137};
1138
1139static int lm49453_hw_params(struct snd_pcm_substream *substream,
1140 struct snd_pcm_hw_params *params,
1141 struct snd_soc_dai *dai)
1142{
1143 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1144 struct snd_soc_codec *codec = rtd->codec;
1145 struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1146 u16 clk_div = 0;
1147
1148 lm49453->fs_rate = params_rate(params);
1149
1150 /* Setting DAC clock dividers based on substream sample rate. */
1151 switch (lm49453->fs_rate) {
1152 case 8000:
1153 case 16000:
1154 case 32000:
1155 case 24000:
1156 case 48000:
1157 clk_div = 256;
1158 break;
1159 case 11025:
1160 case 22050:
1161 case 44100:
1162 clk_div = 216;
1163 break;
1164 case 96000:
1165 clk_div = 127;
1166 break;
1167 default:
1168 return -EINVAL;
1169 }
1170
1171 snd_soc_write(codec, LM49453_P0_ADC_CLK_DIV_REG, clk_div);
1172 snd_soc_write(codec, LM49453_P0_DAC_HP_CLK_DIV_REG, clk_div);
1173
1174 return 0;
1175}
1176
1177static int lm49453_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1178{
1179 struct snd_soc_codec *codec = codec_dai->codec;
1180
1181 int aif_val = 0;
1182 int mode = 0;
1183 int clk_phase = 0;
1184 int clk_shift = 0;
1185
1186 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1187 case SND_SOC_DAIFMT_CBS_CFS:
1188 aif_val = ~LM49453_AUDIO_PORT1_BASIC_CLK_MS |
1189 ~LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1190 break;
1191 case SND_SOC_DAIFMT_CBS_CFM:
1192 aif_val = ~LM49453_AUDIO_PORT1_BASIC_CLK_MS |
1193 LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1194 break;
1195 case SND_SOC_DAIFMT_CBM_CFS:
1196 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS |
1197 ~LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1198 break;
1199 case SND_SOC_DAIFMT_CBM_CFM:
1200 aif_val = LM49453_AUDIO_PORT1_BASIC_CLK_MS |
1201 LM49453_AUDIO_PORT1_BASIC_SYNC_MS;
1202 break;
1203 default:
1204 return -EINVAL;
1205 }
1206
1207
1208 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1209 case SND_SOC_DAIFMT_I2S:
1210 break;
1211 case SND_SOC_DAIFMT_DSP_A:
1212 mode = 1;
1213 clk_phase = (1 << 5);
1214 clk_shift = 1;
1215 break;
1216 case SND_SOC_DAIFMT_DSP_B:
1217 mode = 1;
1218 clk_phase = (1 << 5);
1219 clk_shift = 0;
1220 break;
1221 default:
1222 return -EINVAL;
1223 }
1224
1225 snd_soc_update_bits(codec, LM49453_P0_AUDIO_PORT1_BASIC_REG,
1226 LM49453_AUDIO_PORT1_BASIC_FMT_MASK|BIT(1)|BIT(5),
1227 (aif_val | mode | clk_phase));
1228
1229 snd_soc_write(codec, LM49453_P0_AUDIO_PORT1_RX_MSB_REG, clk_shift);
1230
1231 return 0;
1232}
1233
1234static int lm49453_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1235 unsigned int freq, int dir)
1236{
1237 struct snd_soc_codec *codec = dai->codec;
1238 u16 pll_clk = 0;
1239
1240 switch (freq) {
1241 case 12288000:
1242 case 26000000:
1243 case 19200000:
1244 /* pll clk slection */
1245 pll_clk = 0;
1246 break;
1247 case 48000:
1248 case 32576:
1249 /* fll clk slection */
1250 pll_clk = BIT(4);
1251 return 0;
1252 default:
1253 return -EINVAL;
1254 }
1255
1256 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG, BIT(4), pll_clk);
1257
1258 return 0;
1259}
1260
1261static int lm49453_hp_mute(struct snd_soc_dai *dai, int mute)
1262{
1263 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(1)|BIT(0),
1264 (mute ? (BIT(1)|BIT(0)) : 0));
1265 return 0;
1266}
1267
1268static int lm49453_lo_mute(struct snd_soc_dai *dai, int mute)
1269{
1270 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(3)|BIT(2),
1271 (mute ? (BIT(3)|BIT(2)) : 0));
1272 return 0;
1273}
1274
1275static int lm49453_ls_mute(struct snd_soc_dai *dai, int mute)
1276{
1277 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(5)|BIT(4),
1278 (mute ? (BIT(5)|BIT(4)) : 0));
1279 return 0;
1280}
1281
1282static int lm49453_ep_mute(struct snd_soc_dai *dai, int mute)
1283{
1284 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(4),
1285 (mute ? BIT(4) : 0));
1286 return 0;
1287}
1288
1289static int lm49453_ha_mute(struct snd_soc_dai *dai, int mute)
1290{
1291 snd_soc_update_bits(dai->codec, LM49453_P0_DAC_DSP_REG, BIT(7)|BIT(6),
1292 (mute ? (BIT(7)|BIT(6)) : 0));
1293 return 0;
1294}
1295
1296static int lm49453_set_bias_level(struct snd_soc_codec *codec,
1297 enum snd_soc_bias_level level)
1298{
1299 struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1300
1301 switch (level) {
1302 case SND_SOC_BIAS_ON:
1303 case SND_SOC_BIAS_PREPARE:
1304 break;
1305
1306 case SND_SOC_BIAS_STANDBY:
1307 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1308 regcache_sync(lm49453->regmap);
1309
1310 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1311 LM49453_PMC_SETUP_CHIP_EN, LM49453_CHIP_EN);
1312 break;
1313
1314 case SND_SOC_BIAS_OFF:
1315 snd_soc_update_bits(codec, LM49453_P0_PMC_SETUP_REG,
1316 LM49453_PMC_SETUP_CHIP_EN, 0);
1317 break;
1318 }
1319
1320 codec->dapm.bias_level = level;
1321
1322 return 0;
1323}
1324
1325/* Formates supported by LM49453 driver. */
1326#define LM49453_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1327 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1328
1329static struct snd_soc_dai_ops lm49453_headset_dai_ops = {
1330 .hw_params = lm49453_hw_params,
1331 .set_sysclk = lm49453_set_dai_sysclk,
1332 .set_fmt = lm49453_set_dai_fmt,
1333 .digital_mute = lm49453_hp_mute,
1334};
1335
1336static struct snd_soc_dai_ops lm49453_speaker_dai_ops = {
1337 .hw_params = lm49453_hw_params,
1338 .set_sysclk = lm49453_set_dai_sysclk,
1339 .set_fmt = lm49453_set_dai_fmt,
1340 .digital_mute = lm49453_ls_mute,
1341};
1342
1343static struct snd_soc_dai_ops lm49453_haptic_dai_ops = {
1344 .hw_params = lm49453_hw_params,
1345 .set_sysclk = lm49453_set_dai_sysclk,
1346 .set_fmt = lm49453_set_dai_fmt,
1347 .digital_mute = lm49453_ha_mute,
1348};
1349
1350static struct snd_soc_dai_ops lm49453_ep_dai_ops = {
1351 .hw_params = lm49453_hw_params,
1352 .set_sysclk = lm49453_set_dai_sysclk,
1353 .set_fmt = lm49453_set_dai_fmt,
1354 .digital_mute = lm49453_ep_mute,
1355};
1356
1357static struct snd_soc_dai_ops lm49453_lineout_dai_ops = {
1358 .hw_params = lm49453_hw_params,
1359 .set_sysclk = lm49453_set_dai_sysclk,
1360 .set_fmt = lm49453_set_dai_fmt,
1361 .digital_mute = lm49453_lo_mute,
1362};
1363
1364/* LM49453 dai structure. */
1365struct snd_soc_dai_driver lm49453_dai[] = {
1366 {
1367 .name = "LM49453 Headset",
1368 .playback = {
1369 .stream_name = "Headset",
1370 .channels_min = 2,
1371 .channels_max = 2,
1372 .rates = SNDRV_PCM_RATE_8000_192000,
1373 .formats = LM49453_FORMATS,
1374 },
1375 .capture = {
1376 .stream_name = "Capture",
1377 .channels_min = 1,
1378 .channels_max = 5,
1379 .rates = SNDRV_PCM_RATE_8000_192000,
1380 .formats = LM49453_FORMATS,
1381 },
1382 .ops = &lm49453_headset_dai_ops,
1383 .symmetric_rates = 1,
1384 },
1385 {
1386 .name = "LM49453 Speaker",
1387 .playback = {
1388 .stream_name = "Speaker",
1389 .channels_min = 2,
1390 .channels_max = 2,
1391 .rates = SNDRV_PCM_RATE_8000_192000,
1392 .formats = LM49453_FORMATS,
1393 },
1394 .ops = &lm49453_speaker_dai_ops,
1395 },
1396 {
1397 .name = "LM49453 Haptic",
1398 .playback = {
1399 .stream_name = "Haptic",
1400 .channels_min = 2,
1401 .channels_max = 2,
1402 .rates = SNDRV_PCM_RATE_8000_192000,
1403 .formats = LM49453_FORMATS,
1404 },
1405 .ops = &lm49453_haptic_dai_ops,
1406 },
1407 {
1408 .name = "LM49453 Earpiece",
1409 .playback = {
1410 .stream_name = "Earpiece",
1411 .channels_min = 1,
1412 .channels_max = 1,
1413 .rates = SNDRV_PCM_RATE_8000_192000,
1414 .formats = LM49453_FORMATS,
1415 },
1416 .ops = &lm49453_ep_dai_ops,
1417 },
1418 {
1419 .name = "LM49453 line out",
1420 .playback = {
1421 .stream_name = "Lineout",
1422 .channels_min = 2,
1423 .channels_max = 2,
1424 .rates = SNDRV_PCM_RATE_8000_192000,
1425 .formats = LM49453_FORMATS,
1426 },
1427 .ops = &lm49453_lineout_dai_ops,
1428 },
1429};
1430
1431static int lm49453_suspend(struct snd_soc_codec *codec)
1432{
1433 lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF);
1434 return 0;
1435}
1436
1437static int lm49453_resume(struct snd_soc_codec *codec)
1438{
1439 lm49453_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1440 return 0;
1441}
1442
1443static int lm49453_probe(struct snd_soc_codec *codec)
1444{
1445 struct lm49453_priv *lm49453 = snd_soc_codec_get_drvdata(codec);
1446 int ret = 0;
1447
1448 codec->control_data = lm49453->regmap;
1449
1450 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
1451 if (ret < 0) {
1452 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1453 return ret;
1454 }
1455
1456 return 0;
1457}
1458
1459/* power down chip */
1460static int lm49453_remove(struct snd_soc_codec *codec)
1461{
1462 lm49453_set_bias_level(codec, SND_SOC_BIAS_OFF);
1463 return 0;
1464}
1465
1466static struct snd_soc_codec_driver soc_codec_dev_lm49453 = {
1467 .probe = lm49453_probe,
1468 .remove = lm49453_remove,
1469 .suspend = lm49453_suspend,
1470 .resume = lm49453_resume,
1471 .set_bias_level = lm49453_set_bias_level,
1472 .controls = lm49453_snd_controls,
1473 .num_controls = ARRAY_SIZE(lm49453_snd_controls),
1474 .dapm_widgets = lm49453_dapm_widgets,
1475 .num_dapm_widgets = ARRAY_SIZE(lm49453_dapm_widgets),
1476 .dapm_routes = lm49453_audio_map,
1477 .num_dapm_routes = ARRAY_SIZE(lm49453_audio_map),
1478 .idle_bias_off = true,
1479};
1480
1481static const struct regmap_config lm49453_regmap_config = {
1482 .reg_bits = 8,
1483 .val_bits = 8,
1484
1485 .max_register = LM49453_MAX_REGISTER,
1486 .reg_defaults = lm49453_reg_defs,
1487 .num_reg_defaults = ARRAY_SIZE(lm49453_reg_defs),
1488 .cache_type = REGCACHE_RBTREE,
1489};
1490
1491static __devinit int lm49453_i2c_probe(struct i2c_client *i2c,
1492 const struct i2c_device_id *id)
1493{
1494 struct lm49453_priv *lm49453;
1495 int ret = 0;
1496
1497 lm49453 = devm_kzalloc(&i2c->dev, sizeof(struct lm49453_priv),
1498 GFP_KERNEL);
1499
1500 if (lm49453 == NULL)
1501 return -ENOMEM;
1502
1503 i2c_set_clientdata(i2c, lm49453);
1504
1505 lm49453->regmap = regmap_init_i2c(i2c, &lm49453_regmap_config);
1506 if (IS_ERR(lm49453->regmap)) {
1507 ret = PTR_ERR(lm49453->regmap);
1508 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1509 ret);
1510 return ret;
1511 }
1512
1513 ret = snd_soc_register_codec(&i2c->dev,
1514 &soc_codec_dev_lm49453,
1515 lm49453_dai, ARRAY_SIZE(lm49453_dai));
1516 if (ret < 0) {
1517 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1518 regmap_exit(lm49453->regmap);
1519 return ret;
1520 }
1521
1522 return ret;
1523}
1524
1525static int __devexit lm49453_i2c_remove(struct i2c_client *client)
1526{
1527 struct lm49453_priv *lm49453 = i2c_get_clientdata(client);
1528
1529 snd_soc_unregister_codec(&client->dev);
1530 regmap_exit(lm49453->regmap);
1531 return 0;
1532}
1533
1534static const struct i2c_device_id lm49453_i2c_id[] = {
1535 { "lm49453", 0 },
1536 { }
1537};
1538MODULE_DEVICE_TABLE(i2c, lm49453_i2c_id);
1539
1540static struct i2c_driver lm49453_i2c_driver = {
1541 .driver = {
1542 .name = "lm49453",
1543 .owner = THIS_MODULE,
1544 },
1545 .probe = lm49453_i2c_probe,
1546 .remove = __devexit_p(lm49453_i2c_remove),
1547 .id_table = lm49453_i2c_id,
1548};
1549
1550module_i2c_driver(lm49453_i2c_driver);
1551
1552MODULE_DESCRIPTION("ASoC LM49453 driver");
1553MODULE_AUTHOR("M R Swami Reddy <MR.Swami.Reddy@ti.com");
1554MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/lm49453.h b/sound/soc/codecs/lm49453.h
new file mode 100644
index 000000000000..a63cfa5c0883
--- /dev/null
+++ b/sound/soc/codecs/lm49453.h
@@ -0,0 +1,380 @@
1/*
2 * lm49453.h - LM49453 ALSA Soc Audio drive
3 *
4 * Copyright (c) 2012 Texas Instruments, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 */
11
12#ifndef _LM49453_H
13#define _LM49453_H
14
15#include <linux/bitops.h>
16
17/* LM49453_P0 register space for page0 */
18#define LM49453_P0_PMC_SETUP_REG 0x00
19#define LM49453_P0_PLL_CLK_SEL1_REG 0x01
20#define LM49453_P0_PLL_CLK_SEL2_REG 0x02
21#define LM49453_P0_PMC_CLK_DIV_REG 0x03
22#define LM49453_P0_HSDET_CLK_DIV_REG 0x04
23#define LM49453_P0_DMIC_CLK_DIV_REG 0x05
24#define LM49453_P0_ADC_CLK_DIV_REG 0x06
25#define LM49453_P0_DAC_OT_CLK_DIV_REG 0x07
26#define LM49453_P0_PLL_HF_M_REG 0x08
27#define LM49453_P0_PLL_LF_M_REG 0x09
28#define LM49453_P0_PLL_NL_REG 0x0A
29#define LM49453_P0_PLL_N_MODL_REG 0x0B
30#define LM49453_P0_PLL_N_MODH_REG 0x0C
31#define LM49453_P0_PLL_P1_REG 0x0D
32#define LM49453_P0_PLL_P2_REG 0x0E
33#define LM49453_P0_FLL_REF_FREQL_REG 0x0F
34#define LM49453_P0_FLL_REF_FREQH_REG 0x10
35#define LM49453_P0_VCO_TARGETLL_REG 0x11
36#define LM49453_P0_VCO_TARGETLH_REG 0x12
37#define LM49453_P0_VCO_TARGETHL_REG 0x13
38#define LM49453_P0_VCO_TARGETHH_REG 0x14
39#define LM49453_P0_PLL_CONFIG_REG 0x15
40#define LM49453_P0_DAC_CLK_SEL_REG 0x16
41#define LM49453_P0_DAC_HP_CLK_DIV_REG 0x17
42
43/* Analog Mixer Input Stages */
44#define LM49453_P0_MICL_REG 0x20
45#define LM49453_P0_MICR_REG 0x21
46#define LM49453_P0_EP_REG 0x24
47#define LM49453_P0_DIS_PKVL_FB_REG 0x25
48
49/* Analog Mixer Output Stages */
50#define LM49453_P0_ANALOG_MIXER_ADC_REG 0x2E
51
52/*ADC or DAC */
53#define LM49453_P0_ADC_DSP_REG 0x30
54#define LM49453_P0_DAC_DSP_REG 0x31
55
56/* EFFECTS ENABLES */
57#define LM49453_P0_ADC_FX_ENABLES_REG 0x33
58
59/* GPIO */
60#define LM49453_P0_GPIO1_REG 0x38
61#define LM49453_P0_GPIO2_REG 0x39
62#define LM49453_P0_GPIO3_REG 0x3A
63#define LM49453_P0_HAP_CTL_REG 0x3B
64#define LM49453_P0_HAP_FREQ_PROG_LEFTL_REG 0x3C
65#define LM49453_P0_HAP_FREQ_PROG_LEFTH_REG 0x3D
66#define LM49453_P0_HAP_FREQ_PROG_RIGHTL_REG 0x3E
67#define LM49453_P0_HAP_FREQ_PROG_RIGHTH_REG 0x3F
68
69/* DIGITAL MIXER */
70#define LM49453_P0_DMIX_CLK_SEL_REG 0x40
71#define LM49453_P0_PORT1_RX_LVL1_REG 0x41
72#define LM49453_P0_PORT1_RX_LVL2_REG 0x42
73#define LM49453_P0_PORT2_RX_LVL_REG 0x43
74#define LM49453_P0_PORT1_TX1_REG 0x44
75#define LM49453_P0_PORT1_TX2_REG 0x45
76#define LM49453_P0_PORT1_TX3_REG 0x46
77#define LM49453_P0_PORT1_TX4_REG 0x47
78#define LM49453_P0_PORT1_TX5_REG 0x48
79#define LM49453_P0_PORT1_TX6_REG 0x49
80#define LM49453_P0_PORT1_TX7_REG 0x4A
81#define LM49453_P0_PORT1_TX8_REG 0x4B
82#define LM49453_P0_PORT2_TX1_REG 0x4C
83#define LM49453_P0_PORT2_TX2_REG 0x4D
84#define LM49453_P0_STN_SEL_REG 0x4F
85#define LM49453_P0_DACHPL1_REG 0x50
86#define LM49453_P0_DACHPL2_REG 0x51
87#define LM49453_P0_DACHPR1_REG 0x52
88#define LM49453_P0_DACHPR2_REG 0x53
89#define LM49453_P0_DACLOL1_REG 0x54
90#define LM49453_P0_DACLOL2_REG 0x55
91#define LM49453_P0_DACLOR1_REG 0x56
92#define LM49453_P0_DACLOR2_REG 0x57
93#define LM49453_P0_DACLSL1_REG 0x58
94#define LM49453_P0_DACLSL2_REG 0x59
95#define LM49453_P0_DACLSR1_REG 0x5A
96#define LM49453_P0_DACLSR2_REG 0x5B
97#define LM49453_P0_DACHAL1_REG 0x5C
98#define LM49453_P0_DACHAL2_REG 0x5D
99#define LM49453_P0_DACHAR1_REG 0x5E
100#define LM49453_P0_DACHAR2_REG 0x5F
101
102/* AUDIO PORT 1 (TDM) */
103#define LM49453_P0_AUDIO_PORT1_BASIC_REG 0x60
104#define LM49453_P0_AUDIO_PORT1_CLK_GEN1_REG 0x61
105#define LM49453_P0_AUDIO_PORT1_CLK_GEN2_REG 0x62
106#define LM49453_P0_AUDIO_PORT1_CLK_GEN3_REG 0x63
107#define LM49453_P0_AUDIO_PORT1_SYNC_RATE_REG 0x64
108#define LM49453_P0_AUDIO_PORT1_SYNC_SDO_SETUP_REG 0x65
109#define LM49453_P0_AUDIO_PORT1_DATA_WIDTH_REG 0x66
110#define LM49453_P0_AUDIO_PORT1_RX_MSB_REG 0x67
111#define LM49453_P0_AUDIO_PORT1_TX_MSB_REG 0x68
112#define LM49453_P0_AUDIO_PORT1_TDM_CHANNELS_REG 0x69
113
114/* AUDIO PORT 2 */
115#define LM49453_P0_AUDIO_PORT2_BASIC_REG 0x6A
116#define LM49453_P0_AUDIO_PORT2_CLK_GEN1_REG 0x6B
117#define LM49453_P0_AUDIO_PORT2_CLK_GEN2_REG 0x6C
118#define LM49453_P0_AUDIO_PORT2_SYNC_GEN_REG 0x6D
119#define LM49453_P0_AUDIO_PORT2_DATA_WIDTH_REG 0x6E
120#define LM49453_P0_AUDIO_PORT2_RX_MODE_REG 0x6F
121#define LM49453_P0_AUDIO_PORT2_TX_MODE_REG 0x70
122
123/* SAMPLE RATE */
124#define LM49453_P0_PORT1_SR_LSB_REG 0x79
125#define LM49453_P0_PORT1_SR_MSB_REG 0x7A
126#define LM49453_P0_PORT2_SR_LSB_REG 0x7B
127#define LM49453_P0_PORT2_SR_MSB_REG 0x7C
128
129/* EFFECTS - HPFs */
130#define LM49453_P0_HPF_REG 0x80
131
132/* EFFECTS ADC ALC */
133#define LM49453_P0_ADC_ALC1_REG 0x82
134#define LM49453_P0_ADC_ALC2_REG 0x83
135#define LM49453_P0_ADC_ALC3_REG 0x84
136#define LM49453_P0_ADC_ALC4_REG 0x85
137#define LM49453_P0_ADC_ALC5_REG 0x86
138#define LM49453_P0_ADC_ALC6_REG 0x87
139#define LM49453_P0_ADC_ALC7_REG 0x88
140#define LM49453_P0_ADC_ALC8_REG 0x89
141#define LM49453_P0_DMIC1_LEVELL_REG 0x8A
142#define LM49453_P0_DMIC1_LEVELR_REG 0x8B
143#define LM49453_P0_DMIC2_LEVELL_REG 0x8C
144#define LM49453_P0_DMIC2_LEVELR_REG 0x8D
145#define LM49453_P0_ADC_LEVELL_REG 0x8E
146#define LM49453_P0_ADC_LEVELR_REG 0x8F
147#define LM49453_P0_DAC_HP_LEVELL_REG 0x90
148#define LM49453_P0_DAC_HP_LEVELR_REG 0x91
149#define LM49453_P0_DAC_LO_LEVELL_REG 0x92
150#define LM49453_P0_DAC_LO_LEVELR_REG 0x93
151#define LM49453_P0_DAC_LS_LEVELL_REG 0x94
152#define LM49453_P0_DAC_LS_LEVELR_REG 0x95
153#define LM49453_P0_DAC_HA_LEVELL_REG 0x96
154#define LM49453_P0_DAC_HA_LEVELR_REG 0x97
155#define LM49453_P0_SOFT_MUTE_REG 0x98
156#define LM49453_P0_DMIC_MUTE_CFG_REG 0x99
157#define LM49453_P0_ADC_MUTE_CFG_REG 0x9A
158#define LM49453_P0_DAC_MUTE_CFG_REG 0x9B
159
160/*DIGITAL MIC1 */
161#define LM49453_P0_DIGITAL_MIC1_CONFIG_REG 0xB0
162#define LM49453_P0_DIGITAL_MIC1_DATA_DELAYL_REG 0xB1
163#define LM49453_P0_DIGITAL_MIC1_DATA_DELAYR_REG 0xB2
164
165/*DIGITAL MIC2 */
166#define LM49453_P0_DIGITAL_MIC2_CONFIG_REG 0xB3
167#define LM49453_P0_DIGITAL_MIC2_DATA_DELAYL_REG 0xB4
168#define LM49453_P0_DIGITAL_MIC2_DATA_DELAYR_REG 0xB5
169
170/* ADC DECIMATOR */
171#define LM49453_P0_ADC_DECIMATOR_REG 0xB6
172
173/* DAC CONFIGURE */
174#define LM49453_P0_DAC_CONFIG_REG 0xB7
175
176/* SIDETONE */
177#define LM49453_P0_STN_VOL_ADCL_REG 0xB8
178#define LM49453_P0_STN_VOL_ADCR_REG 0xB9
179#define LM49453_P0_STN_VOL_DMIC1L_REG 0xBA
180#define LM49453_P0_STN_VOL_DMIC1R_REG 0xBB
181#define LM49453_P0_STN_VOL_DMIC2L_REG 0xBC
182#define LM49453_P0_STN_VOL_DMIC2R_REG 0xBD
183
184/* ADC/DAC CLIPPING MONITORS (Read Only/Write to Clear) */
185#define LM49453_P0_ADC_DEC_CLIP_REG 0xC2
186#define LM49453_P0_ADC_HPF_CLIP_REG 0xC3
187#define LM49453_P0_ADC_LVL_CLIP_REG 0xC4
188#define LM49453_P0_DAC_LVL_CLIP_REG 0xC5
189
190/* ADC ALC EFFECT MONITORS (Read Only) */
191#define LM49453_P0_ADC_LVLMONL_REG 0xC8
192#define LM49453_P0_ADC_LVLMONR_REG 0xC9
193#define LM49453_P0_ADC_ALCMONL_REG 0xCA
194#define LM49453_P0_ADC_ALCMONR_REG 0xCB
195#define LM49453_P0_ADC_MUTED_REG 0xCC
196#define LM49453_P0_DAC_MUTED_REG 0xCD
197
198/* HEADSET DETECT */
199#define LM49453_P0_HSD_PPB_LONG_CNT_LIMITL_REG 0xD0
200#define LM49453_P0_HSD_PPB_LONG_CNT_LIMITR_REG 0xD1
201#define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITL_REG 0xD2
202#define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITH_REG 0xD3
203#define LM49453_P0_HSD_TIMEOUT1_REG 0xD4
204#define LM49453_P0_HSD_TIMEOUT2_REG 0xD5
205#define LM49453_P0_HSD_TIMEOUT3_REG 0xD6
206#define LM49453_P0_HSD_PIN3_4_CFG_REG 0xD7
207#define LM49453_P0_HSD_IRQ1_REG 0xD8
208#define LM49453_P0_HSD_IRQ2_REG 0xD9
209#define LM49453_P0_HSD_IRQ3_REG 0xDA
210#define LM49453_P0_HSD_IRQ4_REG 0xDB
211#define LM49453_P0_HSD_IRQ_MASK1_REG 0xDC
212#define LM49453_P0_HSD_IRQ_MASK2_REG 0xDD
213#define LM49453_P0_HSD_IRQ_MASK3_REG 0xDE
214#define LM49453_P0_HSD_R_HPLL_REG 0xE0
215#define LM49453_P0_HSD_R_HPLH_REG 0xE1
216#define LM49453_P0_HSD_R_HPLU_REG 0xE2
217#define LM49453_P0_HSD_R_HPRL_REG 0xE3
218#define LM49453_P0_HSD_R_HPRH_REG 0xE4
219#define LM49453_P0_HSD_R_HPRU_REG 0xE5
220#define LM49453_P0_HSD_VEL_L_FINALL_REG 0xE6
221#define LM49453_P0_HSD_VEL_L_FINALH_REG 0xE7
222#define LM49453_P0_HSD_VEL_L_FINALU_REG 0xE8
223#define LM49453_P0_HSD_RO_FINALL_REG 0xE9
224#define LM49453_P0_HSD_RO_FINALH_REG 0xEA
225#define LM49453_P0_HSD_RO_FINALU_REG 0xEB
226#define LM49453_P0_HSD_VMIC_BIAS_FINALL_REG 0xEC
227#define LM49453_P0_HSD_VMIC_BIAS_FINALH_REG 0xED
228#define LM49453_P0_HSD_VMIC_BIAS_FINALU_REG 0xEE
229#define LM49453_P0_HSD_PIN_CONFIG_REG 0xEF
230#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS1_REG 0xF1
231#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS2_REG 0xF2
232#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS3_REG 0xF3
233#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEL_REG 0xF4
234#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEH_REG 0xF5
235
236/* I/O PULLDOWN CONFIG */
237#define LM49453_P0_PULL_CONFIG1_REG 0xF8
238#define LM49453_P0_PULL_CONFIG2_REG 0xF9
239#define LM49453_P0_PULL_CONFIG3_REG 0xFA
240
241/* RESET */
242#define LM49453_P0_RESET_REG 0xFE
243
244/* PAGE */
245#define LM49453_PAGE_REG 0xFF
246
247#define LM49453_MAX_REGISTER (0xFF+1)
248
249/* LM49453_P0_PMC_SETUP_REG (0x00h) */
250#define LM49453_PMC_SETUP_CHIP_EN (BIT(1)|BIT(0))
251#define LM49453_PMC_SETUP_PLL_EN BIT(2)
252#define LM49453_PMC_SETUP_PLL_P2_EN BIT(3)
253#define LM49453_PMC_SETUP_PLL_FLL BIT(4)
254#define LM49453_PMC_SETUP_MCLK_OVER BIT(5)
255#define LM49453_PMC_SETUP_RTC_CLK_OVER BIT(6)
256#define LM49453_PMC_SETUP_CHIP_ACTIVE BIT(7)
257
258/* Chip Enable bits */
259#define LM49453_CHIP_EN_SHUTDOWN 0x00
260#define LM49453_CHIP_EN 0x01
261#define LM49453_CHIP_EN_HSD_DETECT 0x02
262#define LM49453_CHIP_EN_INVALID_HSD 0x03
263
264/* LM49453_P0_PLL_CLK_SEL1_REG (0x01h) */
265#define LM49453_CLK_SEL1_MCLK_SEL 0x11
266#define LM49453_CLK_SEL1_RTC_SEL 0x11
267#define LM49453_CLK_SEL1_PORT1_SEL 0x10
268#define LM49453_CLK_SEL1_PORT2_SEL 0x11
269
270/* LM49453_P0_PLL_CLK_SEL2_REG (0x02h) */
271#define LM49453_CLK_SEL2_ADC_CLK_SEL 0x38
272
273/* LM49453_P0_FLL_REF_FREQL_REG (0x0F) */
274#define LM49453_FLL_REF_FREQ_VAL 0x8ca0001
275
276/* LM49453_P0_VCO_TARGETLL_REG (0x11) */
277#define LM49453_VCO_TARGET_VAL 0x8ca0001
278
279/* LM49453_P0_ADC_DSP_REG (0x30h) */
280#define LM49453_ADC_DSP_ADC_MUTEL BIT(0)
281#define LM49453_ADC_DSP_ADC_MUTER BIT(1)
282#define LM49453_ADC_DSP_DMIC1_MUTEL BIT(2)
283#define LM49453_ADC_DSP_DMIC1_MUTER BIT(3)
284#define LM49453_ADC_DSP_DMIC2_MUTEL BIT(4)
285#define LM49453_ADC_DSP_DMIC2_MUTER BIT(5)
286#define LM49453_ADC_DSP_MUTE_ALL 0x3F
287
288/* LM49453_P0_DAC_DSP_REG (0x31h) */
289#define LM49453_DAC_DSP_MUTE_ALL 0xFF
290
291/* LM49453_P0_AUDIO_PORT1_BASIC_REG (0x60h) */
292#define LM49453_AUDIO_PORT1_BASIC_FMT_MASK (BIT(4)|BIT(3))
293#define LM49453_AUDIO_PORT1_BASIC_CLK_MS BIT(3)
294#define LM49453_AUDIO_PORT1_BASIC_SYNC_MS BIT(4)
295
296/* LM49453_P0_RESET_REG (0xFEh) */
297#define LM49453_RESET_REG_RST BIT(0)
298
299/* Page select register bits (0xFF) */
300#define LM49453_PAGE0_SELECT 0x0
301#define LM49453_PAGE1_SELECT 0x1
302
303/* LM49453_P0_HSD_PIN3_4_CFG_REG (Jack Pin config - 0xD7) */
304#define LM49453_JACK_DISABLE 0x00
305#define LM49453_JACK_CONFIG1 0x01
306#define LM49453_JACK_CONFIG2 0x02
307#define LM49453_JACK_CONFIG3 0x03
308#define LM49453_JACK_CONFIG4 0x04
309#define LM49453_JACK_CONFIG5 0x05
310
311/* Page 1 REGISTERS */
312
313/* SIDETONE */
314#define LM49453_P1_SIDETONE_SA0L_REG 0x80
315#define LM49453_P1_SIDETONE_SA0H_REG 0x81
316#define LM49453_P1_SIDETONE_SAB0U_REG 0x82
317#define LM49453_P1_SIDETONE_SB0L_REG 0x83
318#define LM49453_P1_SIDETONE_SB0H_REG 0x84
319#define LM49453_P1_SIDETONE_SH0L_REG 0x85
320#define LM49453_P1_SIDETONE_SH0H_REG 0x86
321#define LM49453_P1_SIDETONE_SH0U_REG 0x87
322#define LM49453_P1_SIDETONE_SA1L_REG 0x88
323#define LM49453_P1_SIDETONE_SA1H_REG 0x89
324#define LM49453_P1_SIDETONE_SAB1U_REG 0x8A
325#define LM49453_P1_SIDETONE_SB1L_REG 0x8B
326#define LM49453_P1_SIDETONE_SB1H_REG 0x8C
327#define LM49453_P1_SIDETONE_SH1L_REG 0x8D
328#define LM49453_P1_SIDETONE_SH1H_REG 0x8E
329#define LM49453_P1_SIDETONE_SH1U_REG 0x8F
330#define LM49453_P1_SIDETONE_SA2L_REG 0x90
331#define LM49453_P1_SIDETONE_SA2H_REG 0x91
332#define LM49453_P1_SIDETONE_SAB2U_REG 0x92
333#define LM49453_P1_SIDETONE_SB2L_REG 0x93
334#define LM49453_P1_SIDETONE_SB2H_REG 0x94
335#define LM49453_P1_SIDETONE_SH2L_REG 0x95
336#define LM49453_P1_SIDETONE_SH2H_REG 0x96
337#define LM49453_P1_SIDETONE_SH2U_REG 0x97
338#define LM49453_P1_SIDETONE_SA3L_REG 0x98
339#define LM49453_P1_SIDETONE_SA3H_REG 0x99
340#define LM49453_P1_SIDETONE_SAB3U_REG 0x9A
341#define LM49453_P1_SIDETONE_SB3L_REG 0x9B
342#define LM49453_P1_SIDETONE_SB3H_REG 0x9C
343#define LM49453_P1_SIDETONE_SH3L_REG 0x9D
344#define LM49453_P1_SIDETONE_SH3H_REG 0x9E
345#define LM49453_P1_SIDETONE_SH3U_REG 0x9F
346#define LM49453_P1_SIDETONE_SA4L_REG 0xA0
347#define LM49453_P1_SIDETONE_SA4H_REG 0xA1
348#define LM49453_P1_SIDETONE_SAB4U_REG 0xA2
349#define LM49453_P1_SIDETONE_SB4L_REG 0xA3
350#define LM49453_P1_SIDETONE_SB4H_REG 0xA4
351#define LM49453_P1_SIDETONE_SH4L_REG 0xA5
352#define LM49453_P1_SIDETONE_SH4H_REG 0xA6
353#define LM49453_P1_SIDETONE_SH4U_REG 0xA7
354#define LM49453_P1_SIDETONE_SA5L_REG 0xA8
355#define LM49453_P1_SIDETONE_SA5H_REG 0xA9
356#define LM49453_P1_SIDETONE_SAB5U_REG 0xAA
357#define LM49453_P1_SIDETONE_SB5L_REG 0xAB
358#define LM49453_P1_SIDETONE_SB5H_REG 0xAC
359#define LM49453_P1_SIDETONE_SH5L_REG 0xAD
360#define LM49453_P1_SIDETONE_SH5H_REG 0xAE
361#define LM49453_P1_SIDETONE_SH5U_REG 0xAF
362
363/* CHARGE PUMP CONFIG */
364#define LM49453_P1_CP_CONFIG1_REG 0xB0
365#define LM49453_P1_CP_CONFIG2_REG 0xB1
366#define LM49453_P1_CP_CONFIG3_REG 0xB2
367#define LM49453_P1_CP_CONFIG4_REG 0xB3
368#define LM49453_P1_CP_LA_VTH1L_REG 0xB4
369#define LM49453_P1_CP_LA_VTH1M_REG 0xB5
370#define LM49453_P1_CP_LA_VTH2L_REG 0xB6
371#define LM49453_P1_CP_LA_VTH2M_REG 0xB7
372#define LM49453_P1_CP_LA_VTH3L_REG 0xB8
373#define LM49453_P1_CP_LA_VTH3H_REG 0xB9
374#define LM49453_P1_CP_CLK_DIV_REG 0xBA
375
376/* DAC */
377#define LM49453_P1_DAC_CHOP_REG 0xC0
378
379#define LM49453_CLK_SRC_MCLK 1
380#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 02:04:34 -0500