diff options
author | Haojian Zhuang <haojian.zhuang@marvell.com> | 2010-05-05 10:11:15 -0400 |
---|---|---|
committer | Eric Miao <eric.y.miao@gmail.com> | 2010-05-11 11:25:06 -0400 |
commit | baffe1699c68da5040de6b274054adc995795782 (patch) | |
tree | cdb8a8b80ffb7d8d14b80305c38af650a9842abf /sound | |
parent | 2503991a56483dc8477a3c6ca86da253eb5f8af9 (diff) |
[ARM] pxa: add namespace on ssp
In order to prevent code ambiguous, add namespace on functions in ssp driver.
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Diffstat (limited to 'sound')
-rw-r--r-- | sound/soc/pxa/pxa-ssp.c | 132 |
1 files changed, 66 insertions, 66 deletions
diff --git a/sound/soc/pxa/pxa-ssp.c b/sound/soc/pxa/pxa-ssp.c index 6271a100f355..a1fd23e0e3d0 100644 --- a/sound/soc/pxa/pxa-ssp.c +++ b/sound/soc/pxa/pxa-ssp.c | |||
@@ -56,15 +56,15 @@ struct ssp_priv { | |||
56 | static void dump_registers(struct ssp_device *ssp) | 56 | static void dump_registers(struct ssp_device *ssp) |
57 | { | 57 | { |
58 | dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n", | 58 | dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n", |
59 | ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1), | 59 | pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1), |
60 | ssp_read_reg(ssp, SSTO)); | 60 | pxa_ssp_read_reg(ssp, SSTO)); |
61 | 61 | ||
62 | dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n", | 62 | dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n", |
63 | ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR), | 63 | pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR), |
64 | ssp_read_reg(ssp, SSACD)); | 64 | pxa_ssp_read_reg(ssp, SSACD)); |
65 | } | 65 | } |
66 | 66 | ||
67 | static void ssp_enable(struct ssp_device *ssp) | 67 | static void pxa_ssp_enable(struct ssp_device *ssp) |
68 | { | 68 | { |
69 | uint32_t sscr0; | 69 | uint32_t sscr0; |
70 | 70 | ||
@@ -72,7 +72,7 @@ static void ssp_enable(struct ssp_device *ssp) | |||
72 | __raw_writel(sscr0, ssp->mmio_base + SSCR0); | 72 | __raw_writel(sscr0, ssp->mmio_base + SSCR0); |
73 | } | 73 | } |
74 | 74 | ||
75 | static void ssp_disable(struct ssp_device *ssp) | 75 | static void pxa_ssp_disable(struct ssp_device *ssp) |
76 | { | 76 | { |
77 | uint32_t sscr0; | 77 | uint32_t sscr0; |
78 | 78 | ||
@@ -86,7 +86,7 @@ struct pxa2xx_pcm_dma_data { | |||
86 | }; | 86 | }; |
87 | 87 | ||
88 | static struct pxa2xx_pcm_dma_params * | 88 | static struct pxa2xx_pcm_dma_params * |
89 | ssp_get_dma_params(struct ssp_device *ssp, int width4, int out) | 89 | pxa_ssp_get_dma_params(struct ssp_device *ssp, int width4, int out) |
90 | { | 90 | { |
91 | struct pxa2xx_pcm_dma_data *dma; | 91 | struct pxa2xx_pcm_dma_data *dma; |
92 | 92 | ||
@@ -118,7 +118,7 @@ static int pxa_ssp_startup(struct snd_pcm_substream *substream, | |||
118 | 118 | ||
119 | if (!cpu_dai->active) { | 119 | if (!cpu_dai->active) { |
120 | clk_enable(ssp->clk); | 120 | clk_enable(ssp->clk); |
121 | ssp_disable(ssp); | 121 | pxa_ssp_disable(ssp); |
122 | } | 122 | } |
123 | 123 | ||
124 | kfree(snd_soc_dai_get_dma_data(cpu_dai, substream)); | 124 | kfree(snd_soc_dai_get_dma_data(cpu_dai, substream)); |
@@ -136,7 +136,7 @@ static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, | |||
136 | struct ssp_device *ssp = priv->ssp; | 136 | struct ssp_device *ssp = priv->ssp; |
137 | 137 | ||
138 | if (!cpu_dai->active) { | 138 | if (!cpu_dai->active) { |
139 | ssp_disable(ssp); | 139 | pxa_ssp_disable(ssp); |
140 | clk_disable(ssp->clk); | 140 | clk_disable(ssp->clk); |
141 | } | 141 | } |
142 | 142 | ||
@@ -159,7 +159,7 @@ static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai) | |||
159 | priv->to = __raw_readl(ssp->mmio_base + SSTO); | 159 | priv->to = __raw_readl(ssp->mmio_base + SSTO); |
160 | priv->psp = __raw_readl(ssp->mmio_base + SSPSP); | 160 | priv->psp = __raw_readl(ssp->mmio_base + SSPSP); |
161 | 161 | ||
162 | ssp_disable(ssp); | 162 | pxa_ssp_disable(ssp); |
163 | clk_disable(ssp->clk); | 163 | clk_disable(ssp->clk); |
164 | return 0; | 164 | return 0; |
165 | } | 165 | } |
@@ -179,7 +179,7 @@ static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai) | |||
179 | __raw_writel(priv->psp, ssp->mmio_base + SSPSP); | 179 | __raw_writel(priv->psp, ssp->mmio_base + SSPSP); |
180 | 180 | ||
181 | if (cpu_dai->active) | 181 | if (cpu_dai->active) |
182 | ssp_enable(ssp); | 182 | pxa_ssp_enable(ssp); |
183 | else | 183 | else |
184 | clk_disable(ssp->clk); | 184 | clk_disable(ssp->clk); |
185 | 185 | ||
@@ -195,9 +195,9 @@ static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai) | |||
195 | * ssp_set_clkdiv - set SSP clock divider | 195 | * ssp_set_clkdiv - set SSP clock divider |
196 | * @div: serial clock rate divider | 196 | * @div: serial clock rate divider |
197 | */ | 197 | */ |
198 | static void ssp_set_scr(struct ssp_device *ssp, u32 div) | 198 | static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div) |
199 | { | 199 | { |
200 | u32 sscr0 = ssp_read_reg(ssp, SSCR0); | 200 | u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
201 | 201 | ||
202 | if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) { | 202 | if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) { |
203 | sscr0 &= ~0x0000ff00; | 203 | sscr0 &= ~0x0000ff00; |
@@ -206,15 +206,15 @@ static void ssp_set_scr(struct ssp_device *ssp, u32 div) | |||
206 | sscr0 &= ~0x000fff00; | 206 | sscr0 &= ~0x000fff00; |
207 | sscr0 |= (div - 1) << 8; /* 1..4096 */ | 207 | sscr0 |= (div - 1) << 8; /* 1..4096 */ |
208 | } | 208 | } |
209 | ssp_write_reg(ssp, SSCR0, sscr0); | 209 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
210 | } | 210 | } |
211 | 211 | ||
212 | /** | 212 | /** |
213 | * ssp_get_clkdiv - get SSP clock divider | 213 | * pxa_ssp_get_clkdiv - get SSP clock divider |
214 | */ | 214 | */ |
215 | static u32 ssp_get_scr(struct ssp_device *ssp) | 215 | static u32 pxa_ssp_get_scr(struct ssp_device *ssp) |
216 | { | 216 | { |
217 | u32 sscr0 = ssp_read_reg(ssp, SSCR0); | 217 | u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
218 | u32 div; | 218 | u32 div; |
219 | 219 | ||
220 | if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) | 220 | if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) |
@@ -234,7 +234,7 @@ static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |||
234 | struct ssp_device *ssp = priv->ssp; | 234 | struct ssp_device *ssp = priv->ssp; |
235 | int val; | 235 | int val; |
236 | 236 | ||
237 | u32 sscr0 = ssp_read_reg(ssp, SSCR0) & | 237 | u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & |
238 | ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); | 238 | ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); |
239 | 239 | ||
240 | dev_dbg(&ssp->pdev->dev, | 240 | dev_dbg(&ssp->pdev->dev, |
@@ -262,7 +262,7 @@ static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |||
262 | break; | 262 | break; |
263 | case PXA_SSP_CLK_AUDIO: | 263 | case PXA_SSP_CLK_AUDIO: |
264 | priv->sysclk = 0; | 264 | priv->sysclk = 0; |
265 | ssp_set_scr(ssp, 1); | 265 | pxa_ssp_set_scr(ssp, 1); |
266 | sscr0 |= SSCR0_ACS; | 266 | sscr0 |= SSCR0_ACS; |
267 | break; | 267 | break; |
268 | default: | 268 | default: |
@@ -273,8 +273,8 @@ static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, | |||
273 | * on PXA2xx. On PXA3xx it must be enabled when doing so. */ | 273 | * on PXA2xx. On PXA3xx it must be enabled when doing so. */ |
274 | if (!cpu_is_pxa3xx()) | 274 | if (!cpu_is_pxa3xx()) |
275 | clk_disable(ssp->clk); | 275 | clk_disable(ssp->clk); |
276 | val = ssp_read_reg(ssp, SSCR0) | sscr0; | 276 | val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0; |
277 | ssp_write_reg(ssp, SSCR0, val); | 277 | pxa_ssp_write_reg(ssp, SSCR0, val); |
278 | if (!cpu_is_pxa3xx()) | 278 | if (!cpu_is_pxa3xx()) |
279 | clk_enable(ssp->clk); | 279 | clk_enable(ssp->clk); |
280 | 280 | ||
@@ -293,11 +293,11 @@ static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, | |||
293 | 293 | ||
294 | switch (div_id) { | 294 | switch (div_id) { |
295 | case PXA_SSP_AUDIO_DIV_ACDS: | 295 | case PXA_SSP_AUDIO_DIV_ACDS: |
296 | val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div); | 296 | val = (pxa_ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div); |
297 | ssp_write_reg(ssp, SSACD, val); | 297 | pxa_ssp_write_reg(ssp, SSACD, val); |
298 | break; | 298 | break; |
299 | case PXA_SSP_AUDIO_DIV_SCDB: | 299 | case PXA_SSP_AUDIO_DIV_SCDB: |
300 | val = ssp_read_reg(ssp, SSACD); | 300 | val = pxa_ssp_read_reg(ssp, SSACD); |
301 | val &= ~SSACD_SCDB; | 301 | val &= ~SSACD_SCDB; |
302 | #if defined(CONFIG_PXA3xx) | 302 | #if defined(CONFIG_PXA3xx) |
303 | if (cpu_is_pxa3xx()) | 303 | if (cpu_is_pxa3xx()) |
@@ -320,10 +320,10 @@ static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, | |||
320 | default: | 320 | default: |
321 | return -EINVAL; | 321 | return -EINVAL; |
322 | } | 322 | } |
323 | ssp_write_reg(ssp, SSACD, val); | 323 | pxa_ssp_write_reg(ssp, SSACD, val); |
324 | break; | 324 | break; |
325 | case PXA_SSP_DIV_SCR: | 325 | case PXA_SSP_DIV_SCR: |
326 | ssp_set_scr(ssp, div); | 326 | pxa_ssp_set_scr(ssp, div); |
327 | break; | 327 | break; |
328 | default: | 328 | default: |
329 | return -ENODEV; | 329 | return -ENODEV; |
@@ -340,11 +340,11 @@ static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id, | |||
340 | { | 340 | { |
341 | struct ssp_priv *priv = cpu_dai->private_data; | 341 | struct ssp_priv *priv = cpu_dai->private_data; |
342 | struct ssp_device *ssp = priv->ssp; | 342 | struct ssp_device *ssp = priv->ssp; |
343 | u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70; | 343 | u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70; |
344 | 344 | ||
345 | #if defined(CONFIG_PXA3xx) | 345 | #if defined(CONFIG_PXA3xx) |
346 | if (cpu_is_pxa3xx()) | 346 | if (cpu_is_pxa3xx()) |
347 | ssp_write_reg(ssp, SSACDD, 0); | 347 | pxa_ssp_write_reg(ssp, SSACDD, 0); |
348 | #endif | 348 | #endif |
349 | 349 | ||
350 | switch (freq_out) { | 350 | switch (freq_out) { |
@@ -382,7 +382,7 @@ static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id, | |||
382 | val = tmp; | 382 | val = tmp; |
383 | 383 | ||
384 | val = (val << 16) | 64; | 384 | val = (val << 16) | 64; |
385 | ssp_write_reg(ssp, SSACDD, val); | 385 | pxa_ssp_write_reg(ssp, SSACDD, val); |
386 | 386 | ||
387 | ssacd |= (0x6 << 4); | 387 | ssacd |= (0x6 << 4); |
388 | 388 | ||
@@ -396,7 +396,7 @@ static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id, | |||
396 | return -EINVAL; | 396 | return -EINVAL; |
397 | } | 397 | } |
398 | 398 | ||
399 | ssp_write_reg(ssp, SSACD, ssacd); | 399 | pxa_ssp_write_reg(ssp, SSACD, ssacd); |
400 | 400 | ||
401 | return 0; | 401 | return 0; |
402 | } | 402 | } |
@@ -411,7 +411,7 @@ static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, | |||
411 | struct ssp_device *ssp = priv->ssp; | 411 | struct ssp_device *ssp = priv->ssp; |
412 | u32 sscr0; | 412 | u32 sscr0; |
413 | 413 | ||
414 | sscr0 = ssp_read_reg(ssp, SSCR0); | 414 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
415 | sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS); | 415 | sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS); |
416 | 416 | ||
417 | /* set slot width */ | 417 | /* set slot width */ |
@@ -428,10 +428,10 @@ static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, | |||
428 | sscr0 |= SSCR0_SlotsPerFrm(slots); | 428 | sscr0 |= SSCR0_SlotsPerFrm(slots); |
429 | 429 | ||
430 | /* set active slot mask */ | 430 | /* set active slot mask */ |
431 | ssp_write_reg(ssp, SSTSA, tx_mask); | 431 | pxa_ssp_write_reg(ssp, SSTSA, tx_mask); |
432 | ssp_write_reg(ssp, SSRSA, rx_mask); | 432 | pxa_ssp_write_reg(ssp, SSRSA, rx_mask); |
433 | } | 433 | } |
434 | ssp_write_reg(ssp, SSCR0, sscr0); | 434 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
435 | 435 | ||
436 | return 0; | 436 | return 0; |
437 | } | 437 | } |
@@ -446,12 +446,12 @@ static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai, | |||
446 | struct ssp_device *ssp = priv->ssp; | 446 | struct ssp_device *ssp = priv->ssp; |
447 | u32 sscr1; | 447 | u32 sscr1; |
448 | 448 | ||
449 | sscr1 = ssp_read_reg(ssp, SSCR1); | 449 | sscr1 = pxa_ssp_read_reg(ssp, SSCR1); |
450 | if (tristate) | 450 | if (tristate) |
451 | sscr1 &= ~SSCR1_TTE; | 451 | sscr1 &= ~SSCR1_TTE; |
452 | else | 452 | else |
453 | sscr1 |= SSCR1_TTE; | 453 | sscr1 |= SSCR1_TTE; |
454 | ssp_write_reg(ssp, SSCR1, sscr1); | 454 | pxa_ssp_write_reg(ssp, SSCR1, sscr1); |
455 | 455 | ||
456 | return 0; | 456 | return 0; |
457 | } | 457 | } |
@@ -475,14 +475,14 @@ static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
475 | return 0; | 475 | return 0; |
476 | 476 | ||
477 | /* we can only change the settings if the port is not in use */ | 477 | /* we can only change the settings if the port is not in use */ |
478 | if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) { | 478 | if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) { |
479 | dev_err(&ssp->pdev->dev, | 479 | dev_err(&ssp->pdev->dev, |
480 | "can't change hardware dai format: stream is in use"); | 480 | "can't change hardware dai format: stream is in use"); |
481 | return -EINVAL; | 481 | return -EINVAL; |
482 | } | 482 | } |
483 | 483 | ||
484 | /* reset port settings */ | 484 | /* reset port settings */ |
485 | sscr0 = ssp_read_reg(ssp, SSCR0) & | 485 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & |
486 | (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); | 486 | (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); |
487 | sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7); | 487 | sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7); |
488 | sspsp = 0; | 488 | sspsp = 0; |
@@ -534,9 +534,9 @@ static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai, | |||
534 | return -EINVAL; | 534 | return -EINVAL; |
535 | } | 535 | } |
536 | 536 | ||
537 | ssp_write_reg(ssp, SSCR0, sscr0); | 537 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
538 | ssp_write_reg(ssp, SSCR1, sscr1); | 538 | pxa_ssp_write_reg(ssp, SSCR1, sscr1); |
539 | ssp_write_reg(ssp, SSPSP, sspsp); | 539 | pxa_ssp_write_reg(ssp, SSPSP, sspsp); |
540 | 540 | ||
541 | dump_registers(ssp); | 541 | dump_registers(ssp); |
542 | 542 | ||
@@ -565,7 +565,7 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, | |||
565 | u32 sscr0; | 565 | u32 sscr0; |
566 | u32 sspsp; | 566 | u32 sspsp; |
567 | int width = snd_pcm_format_physical_width(params_format(params)); | 567 | int width = snd_pcm_format_physical_width(params_format(params)); |
568 | int ttsa = ssp_read_reg(ssp, SSTSA) & 0xf; | 568 | int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf; |
569 | struct pxa2xx_pcm_dma_params *dma_data; | 569 | struct pxa2xx_pcm_dma_params *dma_data; |
570 | 570 | ||
571 | dma_data = snd_soc_dai_get_dma_data(dai, substream); | 571 | dma_data = snd_soc_dai_get_dma_data(dai, substream); |
@@ -577,22 +577,22 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, | |||
577 | * to force 16-bit frame width on the wire (for S16_LE), even | 577 | * to force 16-bit frame width on the wire (for S16_LE), even |
578 | * with two channels. Use 16-bit DMA transfers for this case. | 578 | * with two channels. Use 16-bit DMA transfers for this case. |
579 | */ | 579 | */ |
580 | dma_data = ssp_get_dma_params(ssp, | 580 | dma_data = pxa_ssp_get_dma_params(ssp, |
581 | ((chn == 2) && (ttsa != 1)) || (width == 32), | 581 | ((chn == 2) && (ttsa != 1)) || (width == 32), |
582 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK); | 582 | substream->stream == SNDRV_PCM_STREAM_PLAYBACK); |
583 | 583 | ||
584 | snd_soc_dai_set_dma_data(dai, substream, dma_data); | 584 | snd_soc_dai_set_dma_data(dai, substream, dma_data); |
585 | 585 | ||
586 | /* we can only change the settings if the port is not in use */ | 586 | /* we can only change the settings if the port is not in use */ |
587 | if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) | 587 | if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) |
588 | return 0; | 588 | return 0; |
589 | 589 | ||
590 | /* clear selected SSP bits */ | 590 | /* clear selected SSP bits */ |
591 | sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS); | 591 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS); |
592 | ssp_write_reg(ssp, SSCR0, sscr0); | 592 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
593 | 593 | ||
594 | /* bit size */ | 594 | /* bit size */ |
595 | sscr0 = ssp_read_reg(ssp, SSCR0); | 595 | sscr0 = pxa_ssp_read_reg(ssp, SSCR0); |
596 | switch (params_format(params)) { | 596 | switch (params_format(params)) { |
597 | case SNDRV_PCM_FORMAT_S16_LE: | 597 | case SNDRV_PCM_FORMAT_S16_LE: |
598 | #ifdef CONFIG_PXA3xx | 598 | #ifdef CONFIG_PXA3xx |
@@ -608,13 +608,13 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, | |||
608 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16)); | 608 | sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16)); |
609 | break; | 609 | break; |
610 | } | 610 | } |
611 | ssp_write_reg(ssp, SSCR0, sscr0); | 611 | pxa_ssp_write_reg(ssp, SSCR0, sscr0); |
612 | 612 | ||
613 | switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | 613 | switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
614 | case SND_SOC_DAIFMT_I2S: | 614 | case SND_SOC_DAIFMT_I2S: |
615 | sspsp = ssp_read_reg(ssp, SSPSP); | 615 | sspsp = pxa_ssp_read_reg(ssp, SSPSP); |
616 | 616 | ||
617 | if ((ssp_get_scr(ssp) == 4) && (width == 16)) { | 617 | if ((pxa_ssp_get_scr(ssp) == 4) && (width == 16)) { |
618 | /* This is a special case where the bitclk is 64fs | 618 | /* This is a special case where the bitclk is 64fs |
619 | * and we're not dealing with 2*32 bits of audio | 619 | * and we're not dealing with 2*32 bits of audio |
620 | * samples. | 620 | * samples. |
@@ -648,7 +648,7 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, | |||
648 | sspsp |= SSPSP_DMYSTRT(1); | 648 | sspsp |= SSPSP_DMYSTRT(1); |
649 | } | 649 | } |
650 | 650 | ||
651 | ssp_write_reg(ssp, SSPSP, sspsp); | 651 | pxa_ssp_write_reg(ssp, SSPSP, sspsp); |
652 | break; | 652 | break; |
653 | default: | 653 | default: |
654 | break; | 654 | break; |
@@ -679,45 +679,45 @@ static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd, | |||
679 | 679 | ||
680 | switch (cmd) { | 680 | switch (cmd) { |
681 | case SNDRV_PCM_TRIGGER_RESUME: | 681 | case SNDRV_PCM_TRIGGER_RESUME: |
682 | ssp_enable(ssp); | 682 | pxa_ssp_enable(ssp); |
683 | break; | 683 | break; |
684 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | 684 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: |
685 | val = ssp_read_reg(ssp, SSCR1); | 685 | val = pxa_ssp_read_reg(ssp, SSCR1); |
686 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | 686 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
687 | val |= SSCR1_TSRE; | 687 | val |= SSCR1_TSRE; |
688 | else | 688 | else |
689 | val |= SSCR1_RSRE; | 689 | val |= SSCR1_RSRE; |
690 | ssp_write_reg(ssp, SSCR1, val); | 690 | pxa_ssp_write_reg(ssp, SSCR1, val); |
691 | val = ssp_read_reg(ssp, SSSR); | 691 | val = pxa_ssp_read_reg(ssp, SSSR); |
692 | ssp_write_reg(ssp, SSSR, val); | 692 | pxa_ssp_write_reg(ssp, SSSR, val); |
693 | break; | 693 | break; |
694 | case SNDRV_PCM_TRIGGER_START: | 694 | case SNDRV_PCM_TRIGGER_START: |
695 | val = ssp_read_reg(ssp, SSCR1); | 695 | val = pxa_ssp_read_reg(ssp, SSCR1); |
696 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | 696 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
697 | val |= SSCR1_TSRE; | 697 | val |= SSCR1_TSRE; |
698 | else | 698 | else |
699 | val |= SSCR1_RSRE; | 699 | val |= SSCR1_RSRE; |
700 | ssp_write_reg(ssp, SSCR1, val); | 700 | pxa_ssp_write_reg(ssp, SSCR1, val); |
701 | ssp_enable(ssp); | 701 | pxa_ssp_enable(ssp); |
702 | break; | 702 | break; |
703 | case SNDRV_PCM_TRIGGER_STOP: | 703 | case SNDRV_PCM_TRIGGER_STOP: |
704 | val = ssp_read_reg(ssp, SSCR1); | 704 | val = pxa_ssp_read_reg(ssp, SSCR1); |
705 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | 705 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
706 | val &= ~SSCR1_TSRE; | 706 | val &= ~SSCR1_TSRE; |
707 | else | 707 | else |
708 | val &= ~SSCR1_RSRE; | 708 | val &= ~SSCR1_RSRE; |
709 | ssp_write_reg(ssp, SSCR1, val); | 709 | pxa_ssp_write_reg(ssp, SSCR1, val); |
710 | break; | 710 | break; |
711 | case SNDRV_PCM_TRIGGER_SUSPEND: | 711 | case SNDRV_PCM_TRIGGER_SUSPEND: |
712 | ssp_disable(ssp); | 712 | pxa_ssp_disable(ssp); |
713 | break; | 713 | break; |
714 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | 714 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: |
715 | val = ssp_read_reg(ssp, SSCR1); | 715 | val = pxa_ssp_read_reg(ssp, SSCR1); |
716 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | 716 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
717 | val &= ~SSCR1_TSRE; | 717 | val &= ~SSCR1_TSRE; |
718 | else | 718 | else |
719 | val &= ~SSCR1_RSRE; | 719 | val &= ~SSCR1_RSRE; |
720 | ssp_write_reg(ssp, SSCR1, val); | 720 | pxa_ssp_write_reg(ssp, SSCR1, val); |
721 | break; | 721 | break; |
722 | 722 | ||
723 | default: | 723 | default: |
@@ -739,7 +739,7 @@ static int pxa_ssp_probe(struct platform_device *pdev, | |||
739 | if (!priv) | 739 | if (!priv) |
740 | return -ENOMEM; | 740 | return -ENOMEM; |
741 | 741 | ||
742 | priv->ssp = ssp_request(dai->id + 1, "SoC audio"); | 742 | priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio"); |
743 | if (priv->ssp == NULL) { | 743 | if (priv->ssp == NULL) { |
744 | ret = -ENODEV; | 744 | ret = -ENODEV; |
745 | goto err_priv; | 745 | goto err_priv; |
@@ -759,7 +759,7 @@ static void pxa_ssp_remove(struct platform_device *pdev, | |||
759 | struct snd_soc_dai *dai) | 759 | struct snd_soc_dai *dai) |
760 | { | 760 | { |
761 | struct ssp_priv *priv = dai->private_data; | 761 | struct ssp_priv *priv = dai->private_data; |
762 | ssp_free(priv->ssp); | 762 | pxa_ssp_free(priv->ssp); |
763 | } | 763 | } |
764 | 764 | ||
765 | #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ | 765 | #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ |