diff options
author | Fabio Estevam <fabio.estevam@freescale.com> | 2012-01-19 07:23:22 -0500 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2012-01-20 13:38:44 -0500 |
commit | 6b35f924b80a0e6d71711e66f5b3c16f427f3d2a (patch) | |
tree | 235f1cc4358754995a563b545725ee9bf3e8c601 /sound | |
parent | fed22007113cb857e917913ce016d9b539dc3a80 (diff) |
ASoC: mxs: Fix mxs-saif timeout
On a mx28evk board the following errors happens on mxs-sgtl5000 probe:
[ 0.660000] saif0_clk_set_rate: divider writing timeout
[ 0.670000] mxs-sgtl5000: probe of mxs-sgtl5000.0 failed with error -110
[ 0.670000] ALSA device list:
[ 0.680000] No soundcards found.
This timeout happens because clk_set_rate will result in writing to the DIV bits
of register HW_CLKCTRL_SAIF0 with the saif clock gated (CLKGATE bit set to one).
MX28 Reference states the following about CLKGATE:
"The DIV field can change ONLY when this clock gate bit field is low."
So call clk_prepare_enable prior to clk_set_rate to fix this problem.
After this change the mxs-saif driver can be correctly probed and audio is functional.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound')
-rw-r--r-- | sound/soc/mxs/mxs-saif.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c index dccfb37a9626..f204dbac11d4 100644 --- a/sound/soc/mxs/mxs-saif.c +++ b/sound/soc/mxs/mxs-saif.c | |||
@@ -124,6 +124,8 @@ static int mxs_saif_set_clk(struct mxs_saif *saif, | |||
124 | * | 124 | * |
125 | * If MCLK is not used, we just set saif clk to 512*fs. | 125 | * If MCLK is not used, we just set saif clk to 512*fs. |
126 | */ | 126 | */ |
127 | clk_prepare_enable(master_saif->clk); | ||
128 | |||
127 | if (master_saif->mclk_in_use) { | 129 | if (master_saif->mclk_in_use) { |
128 | if (mclk % 32 == 0) { | 130 | if (mclk % 32 == 0) { |
129 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; | 131 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; |
@@ -133,6 +135,7 @@ static int mxs_saif_set_clk(struct mxs_saif *saif, | |||
133 | ret = clk_set_rate(master_saif->clk, 384 * rate); | 135 | ret = clk_set_rate(master_saif->clk, 384 * rate); |
134 | } else { | 136 | } else { |
135 | /* SAIF MCLK should be either 32x or 48x */ | 137 | /* SAIF MCLK should be either 32x or 48x */ |
138 | clk_disable_unprepare(master_saif->clk); | ||
136 | return -EINVAL; | 139 | return -EINVAL; |
137 | } | 140 | } |
138 | } else { | 141 | } else { |
@@ -140,6 +143,8 @@ static int mxs_saif_set_clk(struct mxs_saif *saif, | |||
140 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; | 143 | scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; |
141 | } | 144 | } |
142 | 145 | ||
146 | clk_disable_unprepare(master_saif->clk); | ||
147 | |||
143 | if (ret) | 148 | if (ret) |
144 | return ret; | 149 | return ret; |
145 | 150 | ||