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authorClemens Ladisch <clemens@ladisch.de>2005-09-01 02:14:40 -0400
committerJaroslav Kysela <perex@suse.cz>2005-09-12 04:40:17 -0400
commit12bb5b78e512898034cdd8813f2889743fa6fa3d (patch)
treebadd602f9de26912b8f910e2170d05ab34582f40 /sound
parentee71508e7359c16b43d6232e52cd19ec328e1f7c (diff)
[ALSA] ad1889: add AD1889 driver
PCI drivers,AD1889 driver move the AD1889 driver to the kernel tree Acked-by: Thibaut Varene <varenet@parisc-linux.org> Acked-by: Kyle McMartin <kyle@parisc-linux.org> Signed-off-by: Clemens Ladisch <clemens@ladisch.de>
Diffstat (limited to 'sound')
-rw-r--r--sound/pci/Kconfig12
-rw-r--r--sound/pci/Makefile2
-rw-r--r--sound/pci/ad1889.c1089
-rw-r--r--sound/pci/ad1889.h189
4 files changed, 1292 insertions, 0 deletions
diff --git a/sound/pci/Kconfig b/sound/pci/Kconfig
index 1e458919cce6..a5d593c66f9f 100644
--- a/sound/pci/Kconfig
+++ b/sound/pci/Kconfig
@@ -316,6 +316,18 @@ config SND_YMFPCI
316 To compile this driver as a module, choose M here: the module 316 To compile this driver as a module, choose M here: the module
317 will be called snd-ymfpci. 317 will be called snd-ymfpci.
318 318
319config SND_AD1889
320 tristate "Analog Devices AD1889"
321 depends on SND
322 select SND_AC97_CODEC
323 help
324 Say Y here to include support for the integrated AC97 sound
325 device found in particular on the Hewlett-Packard [BCJ]-xxx0
326 class PA-RISC workstations, using the AD1819 codec.
327
328 To compile this as a module, choose M here: the module
329 will be called snd-ad1889.
330
319config SND_ALS4000 331config SND_ALS4000
320 tristate "Avance Logic ALS4000" 332 tristate "Avance Logic ALS4000"
321 depends on SND && ISA_DMA_API 333 depends on SND && ISA_DMA_API
diff --git a/sound/pci/Makefile b/sound/pci/Makefile
index b40575c3349a..42fabfcfc2a9 100644
--- a/sound/pci/Makefile
+++ b/sound/pci/Makefile
@@ -3,6 +3,7 @@
3# Copyright (c) 2001 by Jaroslav Kysela <perex@suse.cz> 3# Copyright (c) 2001 by Jaroslav Kysela <perex@suse.cz>
4# 4#
5 5
6snd-ad1889-objs := ad1889.o
6snd-als4000-objs := als4000.o 7snd-als4000-objs := als4000.o
7snd-atiixp-objs := atiixp.o 8snd-atiixp-objs := atiixp.o
8snd-atiixp-modem-objs := atiixp_modem.o 9snd-atiixp-modem-objs := atiixp_modem.o
@@ -25,6 +26,7 @@ snd-via82xx-objs := via82xx.o
25snd-via82xx-modem-objs := via82xx_modem.o 26snd-via82xx-modem-objs := via82xx_modem.o
26 27
27# Toplevel Module Dependency 28# Toplevel Module Dependency
29obj-$(CONFIG_SND_AD1889) += snd-ad1889.o
28obj-$(CONFIG_SND_ALS4000) += snd-als4000.o 30obj-$(CONFIG_SND_ALS4000) += snd-als4000.o
29obj-$(CONFIG_SND_ATIIXP) += snd-atiixp.o 31obj-$(CONFIG_SND_ATIIXP) += snd-atiixp.o
30obj-$(CONFIG_SND_ATIIXP_MODEM) += snd-atiixp-modem.o 32obj-$(CONFIG_SND_ATIIXP_MODEM) += snd-atiixp-modem.o
diff --git a/sound/pci/ad1889.c b/sound/pci/ad1889.c
new file mode 100644
index 000000000000..37e8df24711c
--- /dev/null
+++ b/sound/pci/ad1889.c
@@ -0,0 +1,1089 @@
1/* Analog Devices 1889 audio driver
2 *
3 * This is a driver for the AD1889 PCI audio chipset found
4 * on the HP PA-RISC [BCJ]-xxx0 workstations.
5 *
6 * Copyright (C) 2004-2005, Kyle McMartin <kyle@parisc-linux.org>
7 * Copyright (C) 2005, Thibaut Varene <varenet@parisc-linux.org>
8 * Based on the OSS AD1889 driver by Randolph Chung <tausq@debian.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License, version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 * TODO:
24 * Do we need to take care of CCS register?
25 * Maybe we could use finer grained locking (separate locks for pb/cap)?
26 * Wishlist:
27 * Control Interface (mixer) support
28 * Better AC97 support (VSR...)?
29 * PM support
30 * MIDI support
31 * Game Port support
32 * SG DMA support (this will need *alot* of work)
33 */
34
35#include <linux/init.h>
36#include <linux/pci.h>
37#include <linux/slab.h>
38#include <linux/interrupt.h>
39#include <linux/compiler.h>
40#include <linux/delay.h>
41
42#include <sound/driver.h>
43#include <sound/core.h>
44#include <sound/pcm.h>
45#include <sound/initval.h>
46#include <sound/ac97_codec.h>
47
48#include <asm/io.h>
49
50#include "ad1889.h"
51#include "ac97/ac97_id.h"
52
53#define AD1889_DRVVER "$Revision: 1.1 $"
54
55MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>, Thibaut Varene <t-bone@parisc-linux.org>");
56MODULE_DESCRIPTION("Analog Devices AD1889 ALSA sound driver");
57MODULE_LICENSE("GPL");
58MODULE_SUPPORTED_DEVICE("{{Analog Devices,AD1889}}");
59
60static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
61module_param_array(index, int, NULL, 0444);
62MODULE_PARM_DESC(index, "Index value for the AD1889 soundcard.");
63
64static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
65module_param_array(id, charp, NULL, 0444);
66MODULE_PARM_DESC(id, "ID string for the AD1889 soundcard.");
67
68static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
69module_param_array(enable, bool, NULL, 0444);
70MODULE_PARM_DESC(enable, "Enable AD1889 soundcard.");
71
72static char *ac97_quirk[SNDRV_CARDS];
73module_param_array(ac97_quirk, charp, NULL, 0444);
74MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
75
76#define DEVNAME "ad1889"
77#define PFX DEVNAME ": "
78
79/* let's use the global sound debug interfaces */
80#define ad1889_debug(fmt, arg...) snd_printd(KERN_DEBUG fmt, ## arg)
81
82/* keep track of some hw registers */
83struct ad1889_register_state {
84 u16 reg; /* reg setup */
85 u32 addr; /* dma base address */
86 unsigned long size; /* DMA buffer size */
87};
88
89struct snd_ad1889 {
90 snd_card_t *card;
91 struct pci_dev *pci;
92
93 int irq;
94 unsigned long bar;
95 void __iomem *iobase;
96
97 ac97_t *ac97;
98 ac97_bus_t *ac97_bus;
99 snd_pcm_t *pcm;
100 snd_info_entry_t *proc;
101
102 snd_pcm_substream_t *psubs;
103 snd_pcm_substream_t *csubs;
104
105 /* playback register state */
106 struct ad1889_register_state wave;
107 struct ad1889_register_state ramc;
108
109 spinlock_t lock;
110};
111
112static inline u16
113ad1889_readw(struct snd_ad1889 *chip, unsigned reg)
114{
115 return readw(chip->iobase + reg);
116}
117
118static inline void
119ad1889_writew(struct snd_ad1889 *chip, unsigned reg, u16 val)
120{
121 writew(val, chip->iobase + reg);
122}
123
124static inline u32
125ad1889_readl(struct snd_ad1889 *chip, unsigned reg)
126{
127 return readl(chip->iobase + reg);
128}
129
130static inline void
131ad1889_writel(struct snd_ad1889 *chip, unsigned reg, u32 val)
132{
133 writel(val, chip->iobase + reg);
134}
135
136static inline void
137ad1889_unmute(struct snd_ad1889 *chip)
138{
139 u16 st;
140 st = ad1889_readw(chip, AD_DS_WADA) &
141 ~(AD_DS_WADA_RWAM | AD_DS_WADA_LWAM);
142 ad1889_writew(chip, AD_DS_WADA, st);
143 ad1889_readw(chip, AD_DS_WADA);
144}
145
146static inline void
147ad1889_mute(struct snd_ad1889 *chip)
148{
149 u16 st;
150 st = ad1889_readw(chip, AD_DS_WADA) | AD_DS_WADA_RWAM | AD_DS_WADA_LWAM;
151 ad1889_writew(chip, AD_DS_WADA, st);
152 ad1889_readw(chip, AD_DS_WADA);
153}
154
155static inline void
156ad1889_load_adc_buffer_address(struct snd_ad1889 *chip, u32 address)
157{
158 ad1889_writel(chip, AD_DMA_ADCBA, address);
159 ad1889_writel(chip, AD_DMA_ADCCA, address);
160}
161
162static inline void
163ad1889_load_adc_buffer_count(struct snd_ad1889 *chip, u32 count)
164{
165 ad1889_writel(chip, AD_DMA_ADCBC, count);
166 ad1889_writel(chip, AD_DMA_ADCCC, count);
167}
168
169static inline void
170ad1889_load_adc_interrupt_count(struct snd_ad1889 *chip, u32 count)
171{
172 ad1889_writel(chip, AD_DMA_ADCIB, count);
173 ad1889_writel(chip, AD_DMA_ADCIC, count);
174}
175
176static inline void
177ad1889_load_wave_buffer_address(struct snd_ad1889 *chip, u32 address)
178{
179 ad1889_writel(chip, AD_DMA_WAVBA, address);
180 ad1889_writel(chip, AD_DMA_WAVCA, address);
181}
182
183static inline void
184ad1889_load_wave_buffer_count(struct snd_ad1889 *chip, u32 count)
185{
186 ad1889_writel(chip, AD_DMA_WAVBC, count);
187 ad1889_writel(chip, AD_DMA_WAVCC, count);
188}
189
190static inline void
191ad1889_load_wave_interrupt_count(struct snd_ad1889 *chip, u32 count)
192{
193 ad1889_writel(chip, AD_DMA_WAVIB, count);
194 ad1889_writel(chip, AD_DMA_WAVIC, count);
195}
196
197static void
198ad1889_channel_reset(struct snd_ad1889 *chip, unsigned int channel)
199{
200 u16 reg;
201
202 if (channel & AD_CHAN_WAV) {
203 /* Disable wave channel */
204 reg = ad1889_readw(chip, AD_DS_WSMC) & ~AD_DS_WSMC_WAEN;
205 ad1889_writew(chip, AD_DS_WSMC, reg);
206 chip->wave.reg = reg;
207
208 /* disable IRQs */
209 reg = ad1889_readw(chip, AD_DMA_WAV);
210 reg &= AD_DMA_IM_DIS;
211 reg &= ~AD_DMA_LOOP;
212 ad1889_writew(chip, AD_DMA_WAV, reg);
213
214 /* clear IRQ and address counters and pointers */
215 ad1889_load_wave_buffer_address(chip, 0x0);
216 ad1889_load_wave_buffer_count(chip, 0x0);
217 ad1889_load_wave_interrupt_count(chip, 0x0);
218
219 /* flush */
220 ad1889_readw(chip, AD_DMA_WAV);
221 }
222
223 if (channel & AD_CHAN_ADC) {
224 /* Disable ADC channel */
225 reg = ad1889_readw(chip, AD_DS_RAMC) & ~AD_DS_RAMC_ADEN;
226 ad1889_writew(chip, AD_DS_RAMC, reg);
227 chip->ramc.reg = reg;
228
229 reg = ad1889_readw(chip, AD_DMA_ADC);
230 reg &= AD_DMA_IM_DIS;
231 reg &= ~AD_DMA_LOOP;
232 ad1889_writew(chip, AD_DMA_ADC, reg);
233
234 ad1889_load_adc_buffer_address(chip, 0x0);
235 ad1889_load_adc_buffer_count(chip, 0x0);
236 ad1889_load_adc_interrupt_count(chip, 0x0);
237
238 /* flush */
239 ad1889_readw(chip, AD_DMA_ADC);
240 }
241}
242
243static inline u16
244snd_ad1889_ac97_read(ac97_t *ac97, unsigned short reg)
245{
246 struct snd_ad1889 *chip = ac97->private_data;
247 return ad1889_readw(chip, AD_AC97_BASE + reg);
248}
249
250static inline void
251snd_ad1889_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
252{
253 struct snd_ad1889 *chip = ac97->private_data;
254 ad1889_writew(chip, AD_AC97_BASE + reg, val);
255}
256
257static int
258snd_ad1889_ac97_ready(struct snd_ad1889 *chip)
259{
260 int retry = 400; /* average needs 352 msec */
261
262 while (!(ad1889_readw(chip, AD_AC97_ACIC) & AD_AC97_ACIC_ACRDY)
263 && --retry)
264 mdelay(1);
265 if (!retry) {
266 snd_printk(KERN_ERR PFX "[%s] Link is not ready.\n",
267 __FUNCTION__);
268 return -EIO;
269 }
270 ad1889_debug("[%s] ready after %d ms\n", __FUNCTION__, 400 - retry);
271
272 return 0;
273}
274
275static int
276snd_ad1889_hw_params(snd_pcm_substream_t *substream,
277 snd_pcm_hw_params_t *hw_params)
278{
279 return snd_pcm_lib_malloc_pages(substream,
280 params_buffer_bytes(hw_params));
281}
282
283static int
284snd_ad1889_hw_free(snd_pcm_substream_t *substream)
285{
286 return snd_pcm_lib_free_pages(substream);
287}
288
289static snd_pcm_hardware_t snd_ad1889_playback_hw = {
290 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
291 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER,
292 .formats = SNDRV_PCM_FMTBIT_S16_LE,
293 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
294 .rate_min = 8000, /* docs say 7000, but we're lazy */
295 .rate_max = 48000,
296 .channels_min = 1,
297 .channels_max = 2,
298 .buffer_bytes_max = BUFFER_BYTES_MAX,
299 .period_bytes_min = PERIOD_BYTES_MIN,
300 .period_bytes_max = PERIOD_BYTES_MAX,
301 .periods_min = PERIODS_MIN,
302 .periods_max = PERIODS_MAX,
303 /*.fifo_size = 0,*/
304};
305
306static snd_pcm_hardware_t snd_ad1889_capture_hw = {
307 .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
308 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER,
309 .formats = SNDRV_PCM_FMTBIT_S16_LE,
310 .rates = SNDRV_PCM_RATE_48000,
311 .rate_min = 48000, /* docs say we could to VSR, but we're lazy */
312 .rate_max = 48000,
313 .channels_min = 1,
314 .channels_max = 2,
315 .buffer_bytes_max = BUFFER_BYTES_MAX,
316 .period_bytes_min = PERIOD_BYTES_MIN,
317 .period_bytes_max = PERIOD_BYTES_MAX,
318 .periods_min = PERIODS_MIN,
319 .periods_max = PERIODS_MAX,
320 /*.fifo_size = 0,*/
321};
322
323static int
324snd_ad1889_playback_open(snd_pcm_substream_t *ss)
325{
326 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
327 snd_pcm_runtime_t *rt = ss->runtime;
328
329 chip->psubs = ss;
330 rt->hw = snd_ad1889_playback_hw;
331
332 return 0;
333}
334
335static int
336snd_ad1889_capture_open(snd_pcm_substream_t *ss)
337{
338 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
339 snd_pcm_runtime_t *rt = ss->runtime;
340
341 chip->csubs = ss;
342 rt->hw = snd_ad1889_capture_hw;
343
344 return 0;
345}
346
347static int
348snd_ad1889_playback_close(snd_pcm_substream_t *ss)
349{
350 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
351 chip->psubs = NULL;
352 return 0;
353}
354
355static int
356snd_ad1889_capture_close(snd_pcm_substream_t *ss)
357{
358 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
359 chip->csubs = NULL;
360 return 0;
361}
362
363static int
364snd_ad1889_playback_prepare(snd_pcm_substream_t *ss)
365{
366 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
367 snd_pcm_runtime_t *rt = ss->runtime;
368 unsigned int size = snd_pcm_lib_buffer_bytes(ss);
369 unsigned int count = snd_pcm_lib_period_bytes(ss);
370 u16 reg;
371
372 ad1889_channel_reset(chip, AD_CHAN_WAV);
373
374 reg = ad1889_readw(chip, AD_DS_WSMC);
375
376 /* Mask out 16-bit / Stereo */
377 reg &= ~(AD_DS_WSMC_WA16 | AD_DS_WSMC_WAST);
378
379 if (snd_pcm_format_width(rt->format) == 16)
380 reg |= AD_DS_WSMC_WA16;
381
382 if (rt->channels > 1)
383 reg |= AD_DS_WSMC_WAST;
384
385 /* let's make sure we don't clobber ourselves */
386 spin_lock_irq(&chip->lock);
387
388 chip->wave.size = size;
389 chip->wave.reg = reg;
390 chip->wave.addr = rt->dma_addr;
391
392 ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg);
393
394 /* Set sample rates on the codec */
395 ad1889_writew(chip, AD_DS_WAS, rt->rate);
396
397 /* Set up DMA */
398 ad1889_load_wave_buffer_address(chip, chip->wave.addr);
399 ad1889_load_wave_buffer_count(chip, size);
400 ad1889_load_wave_interrupt_count(chip, count);
401
402 /* writes flush */
403 ad1889_readw(chip, AD_DS_WSMC);
404
405 spin_unlock_irq(&chip->lock);
406
407 ad1889_debug("prepare playback: addr = 0x%x, count = %u, "
408 "size = %u, reg = 0x%x, rate = %u\n", chip->wave.addr,
409 count, size, reg, rt->rate);
410 return 0;
411}
412
413static int
414snd_ad1889_capture_prepare(snd_pcm_substream_t *ss)
415{
416 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
417 snd_pcm_runtime_t *rt = ss->runtime;
418 unsigned int size = snd_pcm_lib_buffer_bytes(ss);
419 unsigned int count = snd_pcm_lib_period_bytes(ss);
420 u16 reg;
421
422 ad1889_channel_reset(chip, AD_CHAN_ADC);
423
424 reg = ad1889_readw(chip, AD_DS_RAMC);
425
426 /* Mask out 16-bit / Stereo */
427 reg &= ~(AD_DS_RAMC_AD16 | AD_DS_RAMC_ADST);
428
429 if (snd_pcm_format_width(rt->format) == 16)
430 reg |= AD_DS_RAMC_AD16;
431
432 if (rt->channels > 1)
433 reg |= AD_DS_RAMC_ADST;
434
435 /* let's make sure we don't clobber ourselves */
436 spin_lock_irq(&chip->lock);
437
438 chip->ramc.size = size;
439 chip->ramc.reg = reg;
440 chip->ramc.addr = rt->dma_addr;
441
442 ad1889_writew(chip, AD_DS_RAMC, chip->ramc.reg);
443
444 /* Set up DMA */
445 ad1889_load_adc_buffer_address(chip, chip->ramc.addr);
446 ad1889_load_adc_buffer_count(chip, size);
447 ad1889_load_adc_interrupt_count(chip, count);
448
449 /* writes flush */
450 ad1889_readw(chip, AD_DS_RAMC);
451
452 spin_unlock_irq(&chip->lock);
453
454 ad1889_debug("prepare capture: addr = 0x%x, count = %u, "
455 "size = %u, reg = 0x%x, rate = %u\n", chip->ramc.addr,
456 count, size, reg, rt->rate);
457 return 0;
458}
459
460/* this is called in atomic context with IRQ disabled.
461 Must be as fast as possible and not sleep.
462 DMA should be *triggered* by this call.
463 The WSMC "WAEN" bit triggers DMA Wave On/Off */
464static int
465snd_ad1889_playback_trigger(snd_pcm_substream_t *ss, int cmd)
466{
467 u16 wsmc;
468 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
469
470 wsmc = ad1889_readw(chip, AD_DS_WSMC);
471
472 switch (cmd) {
473 case SNDRV_PCM_TRIGGER_START:
474 /* enable DMA loop & interrupts */
475 ad1889_writew(chip, AD_DMA_WAV, AD_DMA_LOOP | AD_DMA_IM_CNT);
476 wsmc |= AD_DS_WSMC_WAEN;
477 /* 1 to clear CHSS bit */
478 ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_WAVS);
479 ad1889_unmute(chip);
480 break;
481 case SNDRV_PCM_TRIGGER_STOP:
482 ad1889_mute(chip);
483 wsmc &= ~AD_DS_WSMC_WAEN;
484 break;
485 default:
486 snd_BUG();
487 return -EINVAL;
488 }
489
490 chip->wave.reg = wsmc;
491 ad1889_writew(chip, AD_DS_WSMC, wsmc);
492 ad1889_readw(chip, AD_DS_WSMC); /* flush */
493
494 /* reset the chip when STOP - will disable IRQs */
495 if (cmd == SNDRV_PCM_TRIGGER_STOP)
496 ad1889_channel_reset(chip, AD_CHAN_WAV);
497
498 return 0;
499}
500
501/* this is called in atomic context with IRQ disabled.
502 Must be as fast as possible and not sleep.
503 DMA should be *triggered* by this call.
504 The RAMC "ADEN" bit triggers DMA ADC On/Off */
505static int
506snd_ad1889_capture_trigger(snd_pcm_substream_t *ss, int cmd)
507{
508 u16 ramc;
509 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
510
511 ramc = ad1889_readw(chip, AD_DS_RAMC);
512
513 switch (cmd) {
514 case SNDRV_PCM_TRIGGER_START:
515 /* enable DMA loop & interrupts */
516 ad1889_writew(chip, AD_DMA_ADC, AD_DMA_LOOP | AD_DMA_IM_CNT);
517 ramc |= AD_DS_RAMC_ADEN;
518 /* 1 to clear CHSS bit */
519 ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_ADCS);
520 break;
521 case SNDRV_PCM_TRIGGER_STOP:
522 ramc &= ~AD_DS_RAMC_ADEN;
523 break;
524 default:
525 return -EINVAL;
526 }
527
528 chip->ramc.reg = ramc;
529 ad1889_writew(chip, AD_DS_RAMC, ramc);
530 ad1889_readw(chip, AD_DS_RAMC); /* flush */
531
532 /* reset the chip when STOP - will disable IRQs */
533 if (cmd == SNDRV_PCM_TRIGGER_STOP)
534 ad1889_channel_reset(chip, AD_CHAN_ADC);
535
536 return 0;
537}
538
539/* Called in atomic context with IRQ disabled */
540static snd_pcm_uframes_t
541snd_ad1889_playback_pointer(snd_pcm_substream_t *ss)
542{
543 size_t ptr = 0;
544 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
545
546 if (unlikely(!(chip->wave.reg & AD_DS_WSMC_WAEN)))
547 return 0;
548
549 ptr = ad1889_readl(chip, AD_DMA_WAVCA);
550 ptr -= chip->wave.addr;
551
552 snd_assert((ptr >= 0) && (ptr < chip->wave.size), return 0);
553
554 return bytes_to_frames(ss->runtime, ptr);
555}
556
557/* Called in atomic context with IRQ disabled */
558static snd_pcm_uframes_t
559snd_ad1889_capture_pointer(snd_pcm_substream_t *ss)
560{
561 size_t ptr = 0;
562 struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
563
564 if (unlikely(!(chip->ramc.reg & AD_DS_RAMC_ADEN)))
565 return 0;
566
567 ptr = ad1889_readl(chip, AD_DMA_ADCCA);
568 ptr -= chip->ramc.addr;
569
570 snd_assert((ptr >= 0) && (ptr < chip->ramc.size), return 0);
571
572 return bytes_to_frames(ss->runtime, ptr);
573}
574
575static snd_pcm_ops_t snd_ad1889_playback_ops = {
576 .open = snd_ad1889_playback_open,
577 .close = snd_ad1889_playback_close,
578 .ioctl = snd_pcm_lib_ioctl,
579 .hw_params = snd_ad1889_hw_params,
580 .hw_free = snd_ad1889_hw_free,
581 .prepare = snd_ad1889_playback_prepare,
582 .trigger = snd_ad1889_playback_trigger,
583 .pointer = snd_ad1889_playback_pointer,
584};
585
586static snd_pcm_ops_t snd_ad1889_capture_ops = {
587 .open = snd_ad1889_capture_open,
588 .close = snd_ad1889_capture_close,
589 .ioctl = snd_pcm_lib_ioctl,
590 .hw_params = snd_ad1889_hw_params,
591 .hw_free = snd_ad1889_hw_free,
592 .prepare = snd_ad1889_capture_prepare,
593 .trigger = snd_ad1889_capture_trigger,
594 .pointer = snd_ad1889_capture_pointer,
595};
596
597static irqreturn_t
598snd_ad1889_interrupt(int irq,
599 void *dev_id,
600 struct pt_regs *regs)
601{
602 unsigned long st;
603 struct snd_ad1889 *chip = dev_id;
604
605 st = ad1889_readl(chip, AD_DMA_DISR);
606
607 /* clear ISR */
608 ad1889_writel(chip, AD_DMA_DISR, st);
609
610 st &= AD_INTR_MASK;
611
612 if (unlikely(!st))
613 return IRQ_NONE;
614
615 if (st & (AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI))
616 ad1889_debug("Unexpected master or target abort interrupt!\n");
617
618 if ((st & AD_DMA_DISR_WAVI) && chip->psubs)
619 snd_pcm_period_elapsed(chip->psubs);
620 if ((st & AD_DMA_DISR_ADCI) && chip->csubs)
621 snd_pcm_period_elapsed(chip->csubs);
622
623 return IRQ_HANDLED;
624}
625
626static void
627snd_ad1889_pcm_free(snd_pcm_t *pcm)
628{
629 struct snd_ad1889 *chip = pcm->private_data;
630 chip->pcm = NULL;
631 snd_pcm_lib_preallocate_free_for_all(pcm);
632}
633
634static int __devinit
635snd_ad1889_pcm_init(struct snd_ad1889 *chip, int device, snd_pcm_t **rpcm)
636{
637 int err;
638 snd_pcm_t *pcm;
639
640 if (rpcm)
641 *rpcm = NULL;
642
643 err = snd_pcm_new(chip->card, chip->card->driver, device, 1, 1, &pcm);
644 if (err < 0)
645 return err;
646
647 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
648 &snd_ad1889_playback_ops);
649 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
650 &snd_ad1889_capture_ops);
651
652 pcm->private_data = chip;
653 pcm->private_free = snd_ad1889_pcm_free;
654 pcm->info_flags = 0;
655 strcpy(pcm->name, chip->card->shortname);
656
657 chip->pcm = pcm;
658 chip->psubs = NULL;
659 chip->csubs = NULL;
660
661 err = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
662 snd_dma_pci_data(chip->pci),
663 BUFFER_BYTES_MAX / 2,
664 BUFFER_BYTES_MAX);
665
666 if (err < 0) {
667 snd_printk(KERN_ERR PFX "buffer allocation error: %d\n", err);
668 return err;
669 }
670
671 if (rpcm)
672 *rpcm = pcm;
673
674 return 0;
675}
676
677static void
678snd_ad1889_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
679{
680 struct snd_ad1889 *chip = entry->private_data;
681 u16 reg;
682 int tmp;
683
684 reg = ad1889_readw(chip, AD_DS_WSMC);
685 snd_iprintf(buffer, "Wave output: %s\n",
686 (reg & AD_DS_WSMC_WAEN) ? "enabled" : "disabled");
687 snd_iprintf(buffer, "Wave Channels: %s\n",
688 (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
689 snd_iprintf(buffer, "Wave Quality: %d-bit linear\n",
690 (reg & AD_DS_WSMC_WA16) ? 16 : 8);
691
692 /* WARQ is at offset 12 */
693 tmp = (reg & AD_DS_WSMC_WARQ) ?
694 (((reg & AD_DS_WSMC_WARQ >> 12) & 0x01) ? 12 : 18) : 4;
695 tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1;
696
697 snd_iprintf(buffer, "Wave FIFO: %d %s words\n\n", tmp,
698 (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
699
700
701 snd_iprintf(buffer, "Synthesis output: %s\n",
702 reg & AD_DS_WSMC_SYEN ? "enabled" : "disabled");
703
704 /* SYRQ is at offset 4 */
705 tmp = (reg & AD_DS_WSMC_SYRQ) ?
706 (((reg & AD_DS_WSMC_SYRQ >> 4) & 0x01) ? 12 : 18) : 4;
707 tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1;
708
709 snd_iprintf(buffer, "Synthesis FIFO: %d %s words\n\n", tmp,
710 (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
711
712 reg = ad1889_readw(chip, AD_DS_RAMC);
713 snd_iprintf(buffer, "ADC input: %s\n",
714 (reg & AD_DS_RAMC_ADEN) ? "enabled" : "disabled");
715 snd_iprintf(buffer, "ADC Channels: %s\n",
716 (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono");
717 snd_iprintf(buffer, "ADC Quality: %d-bit linear\n",
718 (reg & AD_DS_RAMC_AD16) ? 16 : 8);
719
720 /* ACRQ is at offset 4 */
721 tmp = (reg & AD_DS_RAMC_ACRQ) ?
722 (((reg & AD_DS_RAMC_ACRQ >> 4) & 0x01) ? 12 : 18) : 4;
723 tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1;
724
725 snd_iprintf(buffer, "ADC FIFO: %d %s words\n\n", tmp,
726 (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono");
727
728 snd_iprintf(buffer, "Resampler input: %s\n",
729 reg & AD_DS_RAMC_REEN ? "enabled" : "disabled");
730
731 /* RERQ is at offset 12 */
732 tmp = (reg & AD_DS_RAMC_RERQ) ?
733 (((reg & AD_DS_RAMC_RERQ >> 12) & 0x01) ? 12 : 18) : 4;
734 tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1;
735
736 snd_iprintf(buffer, "Resampler FIFO: %d %s words\n\n", tmp,
737 (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
738
739
740 /* doc says LSB represents -1.5dB, but the max value (-94.5dB)
741 suggests that LSB is -3dB, which is more coherent with the logarithmic
742 nature of the dB scale */
743 reg = ad1889_readw(chip, AD_DS_WADA);
744 snd_iprintf(buffer, "Left: %s, -%d dB\n",
745 (reg & AD_DS_WADA_LWAM) ? "mute" : "unmute",
746 ((reg & AD_DS_WADA_LWAA) >> 8) * 3);
747 reg = ad1889_readw(chip, AD_DS_WADA);
748 snd_iprintf(buffer, "Right: %s, -%d dB\n",
749 (reg & AD_DS_WADA_RWAM) ? "mute" : "unmute",
750 ((reg & AD_DS_WADA_RWAA) >> 8) * 3);
751
752 reg = ad1889_readw(chip, AD_DS_WAS);
753 snd_iprintf(buffer, "Wave samplerate: %u Hz\n", reg);
754 reg = ad1889_readw(chip, AD_DS_RES);
755 snd_iprintf(buffer, "Resampler samplerate: %u Hz\n", reg);
756}
757
758static void __devinit
759snd_ad1889_proc_init(struct snd_ad1889 *chip)
760{
761 snd_info_entry_t *entry;
762
763 if (!snd_card_proc_new(chip->card, chip->card->driver, &entry))
764 snd_info_set_text_ops(entry, chip, 1024, snd_ad1889_proc_read);
765}
766
767static struct ac97_quirk ac97_quirks[] = {
768 {
769 .subvendor = 0x11d4, /* AD */
770 .subdevice = 0x1889, /* AD1889 */
771 .codec_id = AC97_ID_AD1819,
772 .name = "AD1889",
773 .type = AC97_TUNE_HP_ONLY
774 },
775 { } /* terminator */
776};
777
778static void __devinit
779snd_ad1889_ac97_xinit(struct snd_ad1889 *chip)
780{
781 u16 reg;
782
783 reg = ad1889_readw(chip, AD_AC97_ACIC);
784 reg |= AD_AC97_ACIC_ACRD; /* Reset Disable */
785 ad1889_writew(chip, AD_AC97_ACIC, reg);
786 ad1889_readw(chip, AD_AC97_ACIC); /* flush posted write */
787 udelay(10);
788 /* Interface Enable */
789 reg |= AD_AC97_ACIC_ACIE;
790 ad1889_writew(chip, AD_AC97_ACIC, reg);
791
792 snd_ad1889_ac97_ready(chip);
793
794 /* Audio Stream Output | Variable Sample Rate Mode */
795 reg = ad1889_readw(chip, AD_AC97_ACIC);
796 reg |= AD_AC97_ACIC_ASOE | AD_AC97_ACIC_VSRM;
797 ad1889_writew(chip, AD_AC97_ACIC, reg);
798 ad1889_readw(chip, AD_AC97_ACIC); /* flush posted write */
799
800}
801
802static void
803snd_ad1889_ac97_bus_free(ac97_bus_t *bus)
804{
805 struct snd_ad1889 *chip = bus->private_data;
806 chip->ac97_bus = NULL;
807}
808
809static void
810snd_ad1889_ac97_free(ac97_t *ac97)
811{
812 struct snd_ad1889 *chip = ac97->private_data;
813 chip->ac97 = NULL;
814}
815
816static int __devinit
817snd_ad1889_ac97_init(struct snd_ad1889 *chip, const char *quirk_override)
818{
819 int err;
820 ac97_template_t ac97;
821 static ac97_bus_ops_t ops = {
822 .write = snd_ad1889_ac97_write,
823 .read = snd_ad1889_ac97_read,
824 };
825
826 /* doing that here, it works. */
827 snd_ad1889_ac97_xinit(chip);
828
829 err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus);
830 if (err < 0)
831 return err;
832
833 chip->ac97_bus->private_free = snd_ad1889_ac97_bus_free;
834
835 memset(&ac97, 0, sizeof(ac97));
836 ac97.private_data = chip;
837 ac97.private_free = snd_ad1889_ac97_free;
838 ac97.pci = chip->pci;
839
840 err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97);
841 if (err < 0)
842 return err;
843
844 snd_ac97_tune_hardware(chip->ac97, ac97_quirks, quirk_override);
845
846 return 0;
847}
848
849static int
850snd_ad1889_free(struct snd_ad1889 *chip)
851{
852 if (chip->irq < 0)
853 goto skip_hw;
854
855 spin_lock_irq(&chip->lock);
856
857 ad1889_mute(chip);
858
859 /* Turn off interrupt on count and zero DMA registers */
860 ad1889_channel_reset(chip, AD_CHAN_WAV | AD_CHAN_ADC);
861
862 /* clear DISR. If we don't, we'd better jump off the Eiffel Tower */
863 ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PTAI | AD_DMA_DISR_PMAI);
864 ad1889_readl(chip, AD_DMA_DISR); /* flush, dammit! */
865
866 spin_unlock_irq(&chip->lock);
867
868 synchronize_irq(chip->irq);
869
870 if (chip->irq >= 0)
871 free_irq(chip->irq, (void*)chip);
872
873skip_hw:
874 if (chip->iobase)
875 iounmap(chip->iobase);
876
877 pci_release_regions(chip->pci);
878 pci_disable_device(chip->pci);
879
880 kfree(chip);
881 return 0;
882}
883
884static inline int
885snd_ad1889_dev_free(snd_device_t *device)
886{
887 struct snd_ad1889 *chip = device->device_data;
888 return snd_ad1889_free(chip);
889}
890
891static int __devinit
892snd_ad1889_init(struct snd_ad1889 *chip)
893{
894 ad1889_writew(chip, AD_DS_CCS, AD_DS_CCS_CLKEN); /* turn on clock */
895 ad1889_readw(chip, AD_DS_CCS); /* flush posted write */
896
897 mdelay(10);
898
899 /* enable Master and Target abort interrupts */
900 ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PMAE | AD_DMA_DISR_PTAE);
901
902 return 0;
903}
904
905static int __devinit
906snd_ad1889_create(snd_card_t *card,
907 struct pci_dev *pci,
908 struct snd_ad1889 **rchip)
909{
910 int err;
911
912 struct snd_ad1889 *chip;
913 static snd_device_ops_t ops = {
914 .dev_free = snd_ad1889_dev_free,
915 };
916
917 *rchip = NULL;
918
919 if ((err = pci_enable_device(pci)) < 0)
920 return err;
921
922 /* check PCI availability (32bit DMA) */
923 if (pci_set_dma_mask(pci, 0xffffffff) < 0 ||
924 pci_set_consistent_dma_mask(pci, 0xffffffff) < 0) {
925 printk(KERN_ERR PFX "error setting 32-bit DMA mask.\n");
926 pci_disable_device(pci);
927 return -ENXIO;
928 }
929
930 /* allocate chip specific data with zero-filled memory */
931 if ((chip = kcalloc(1, sizeof(*chip), GFP_KERNEL)) == NULL) {
932 pci_disable_device(pci);
933 return -ENOMEM;
934 }
935
936 chip->card = card;
937 card->private_data = chip;
938 chip->pci = pci;
939 chip->irq = -1;
940
941 /* (1) PCI resource allocation */
942 if ((err = pci_request_regions(pci, card->driver)) < 0)
943 goto free_and_ret;
944
945 chip->bar = pci_resource_start(pci, 0);
946 chip->iobase = ioremap_nocache(chip->bar, pci_resource_len(pci, 0));
947 if (chip->iobase == NULL) {
948 printk(KERN_ERR PFX "unable to reserve region.\n");
949 err = -EBUSY;
950 goto free_and_ret;
951 }
952
953 pci_set_master(pci);
954
955 spin_lock_init(&chip->lock); /* only now can we call ad1889_free */
956
957 if (request_irq(pci->irq, snd_ad1889_interrupt,
958 SA_INTERRUPT|SA_SHIRQ, card->driver, (void*)chip)) {
959 printk(KERN_ERR PFX "cannot obtain IRQ %d\n", pci->irq);
960 snd_ad1889_free(chip);
961 return -EBUSY;
962 }
963
964 chip->irq = pci->irq;
965 synchronize_irq(chip->irq);
966
967 /* (2) initialization of the chip hardware */
968 if ((err = snd_ad1889_init(chip)) < 0) {
969 snd_ad1889_free(chip);
970 return err;
971 }
972
973 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
974 snd_ad1889_free(chip);
975 return err;
976 }
977
978 snd_card_set_dev(card, &pci->dev);
979
980 *rchip = chip;
981
982 return 0;
983
984free_and_ret:
985 if (chip)
986 kfree(chip);
987 pci_disable_device(pci);
988
989 return err;
990}
991
992static int __devinit
993snd_ad1889_probe(struct pci_dev *pci,
994 const struct pci_device_id *pci_id)
995{
996 int err;
997 static int devno;
998 snd_card_t *card;
999 struct snd_ad1889 *chip;
1000
1001 /* (1) */
1002 if (devno >= SNDRV_CARDS)
1003 return -ENODEV;
1004 if (!enable[devno]) {
1005 devno++;
1006 return -ENOENT;
1007 }
1008
1009 /* (2) */
1010 card = snd_card_new(index[devno], id[devno], THIS_MODULE, 0);
1011 /* XXX REVISIT: we can probably allocate chip in this call */
1012 if (card == NULL)
1013 return -ENOMEM;
1014
1015 strcpy(card->driver, "AD1889");
1016 strcpy(card->shortname, "Analog Devices AD1889");
1017
1018 /* (3) */
1019 err = snd_ad1889_create(card, pci, &chip);
1020 if (err < 0)
1021 goto free_and_ret;
1022
1023 /* (4) */
1024 sprintf(card->longname, "%s at 0x%lx irq %i",
1025 card->shortname, chip->bar, chip->irq);
1026
1027 /* (5) */
1028 /* register AC97 mixer */
1029 err = snd_ad1889_ac97_init(chip, ac97_quirk[devno]);
1030 if (err < 0)
1031 goto free_and_ret;
1032
1033 err = snd_ad1889_pcm_init(chip, 0, NULL);
1034 if (err < 0)
1035 goto free_and_ret;
1036
1037 /* register proc interface */
1038 snd_ad1889_proc_init(chip);
1039
1040 /* (6) */
1041 err = snd_card_register(card);
1042 if (err < 0)
1043 goto free_and_ret;
1044
1045 /* (7) */
1046 pci_set_drvdata(pci, card);
1047
1048 devno++;
1049 return 0;
1050
1051free_and_ret:
1052 snd_card_free(card);
1053 return err;
1054}
1055
1056static void __devexit
1057snd_ad1889_remove(struct pci_dev *pci)
1058{
1059 snd_card_free(pci_get_drvdata(pci));
1060 pci_set_drvdata(pci, NULL);
1061}
1062
1063static struct pci_device_id snd_ad1889_ids[] = {
1064 { PCI_DEVICE(PCI_VENDOR_ID_ANALOG_DEVICES, PCI_DEVICE_ID_AD1889JS) },
1065 { 0, },
1066};
1067MODULE_DEVICE_TABLE(pci, snd_ad1889_ids);
1068
1069static struct pci_driver ad1889_pci = {
1070 .name = "AD1889 Audio",
1071 .id_table = snd_ad1889_ids,
1072 .probe = snd_ad1889_probe,
1073 .remove = __devexit_p(snd_ad1889_remove),
1074};
1075
1076static int __init
1077alsa_ad1889_init(void)
1078{
1079 return pci_register_driver(&ad1889_pci);
1080}
1081
1082static void __exit
1083alsa_ad1889_fini(void)
1084{
1085 pci_unregister_driver(&ad1889_pci);
1086}
1087
1088module_init(alsa_ad1889_init);
1089module_exit(alsa_ad1889_fini);
diff --git a/sound/pci/ad1889.h b/sound/pci/ad1889.h
new file mode 100644
index 000000000000..5e6dad5341a1
--- /dev/null
+++ b/sound/pci/ad1889.h
@@ -0,0 +1,189 @@
1/* Analog Devices 1889 audio driver
2 * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org>
3 */
4
5#ifndef __AD1889_H__
6#define __AD1889_H__
7
8#define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */
9#define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */
10#define AD_DS_WSMC_SYRQ 0x0030 /* synth. fifo request point */
11#define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */
12#define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */
13#define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */
14#define AD_DS_WSMC_WARQ 0x3000 /* wave fifo request point */
15
16#define AD_DS_RAMC 0x02 /* resampler/ADC channel mixer control */
17#define AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */
18#define AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */
19#define AD_DS_RAMC_ADEN 0x0004 /* ADC channel enable */
20#define AD_DS_RAMC_ACRQ 0x0030 /* ADC fifo request point */
21#define AD_DS_RAMC_REEN 0x0400 /* resampler channel enable */
22#define AD_DS_RAMC_RERQ 0x3000 /* res. fifo request point */
23
24#define AD_DS_WADA 0x04 /* wave channel mix attenuation */
25#define AD_DS_WADA_RWAM 0x0080 /* right wave mute */
26#define AD_DS_WADA_RWAA 0x001f /* right wave attenuation */
27#define AD_DS_WADA_LWAM 0x8000 /* left wave mute */
28#define AD_DS_WADA_LWAA 0x3e00 /* left wave attenuation */
29
30#define AD_DS_SYDA 0x06 /* synthesis channel mix attenuation */
31#define AD_DS_SYDA_RSYM 0x0080 /* right synthesis mute */
32#define AD_DS_SYDA_RSYA 0x001f /* right synthesis attenuation */
33#define AD_DS_SYDA_LSYM 0x8000 /* left synthesis mute */
34#define AD_DS_SYDA_LSYA 0x3e00 /* left synthesis attenuation */
35
36#define AD_DS_WAS 0x08 /* wave channel sample rate */
37#define AD_DS_WAS_WAS 0xffff /* sample rate mask */
38
39#define AD_DS_RES 0x0a /* resampler channel sample rate */
40#define AD_DS_RES_RES 0xffff /* sample rate mask */
41
42#define AD_DS_CCS 0x0c /* chip control/status */
43#define AD_DS_CCS_ADO 0x0001 /* ADC channel overflow */
44#define AD_DS_CCS_REO 0x0002 /* resampler channel overflow */
45#define AD_DS_CCS_SYU 0x0004 /* synthesis channel underflow */
46#define AD_DS_CCS_WAU 0x0008 /* wave channel underflow */
47/* bits 4 -> 7, 9, 11 -> 14 reserved */
48#define AD_DS_CCS_XTD 0x0100 /* xtd delay control (4096 clock cycles) */
49#define AD_DS_CCS_PDALL 0x0400 /* power */
50#define AD_DS_CCS_CLKEN 0x8000 /* clock */
51
52#define AD_DMA_RESBA 0x40 /* RES base address */
53#define AD_DMA_RESCA 0x44 /* RES current address */
54#define AD_DMA_RESBC 0x48 /* RES base count */
55#define AD_DMA_RESCC 0x4c /* RES current count */
56
57#define AD_DMA_ADCBA 0x50 /* ADC base address */
58#define AD_DMA_ADCCA 0x54 /* ADC current address */
59#define AD_DMA_ADCBC 0x58 /* ADC base count */
60#define AD_DMA_ADCCC 0x5c /* ADC current count */
61
62#define AD_DMA_SYNBA 0x60 /* synth base address */
63#define AD_DMA_SYNCA 0x64 /* synth current address */
64#define AD_DMA_SYNBC 0x68 /* synth base count */
65#define AD_DMA_SYNCC 0x6c /* synth current count */
66
67#define AD_DMA_WAVBA 0x70 /* wave base address */
68#define AD_DMA_WAVCA 0x74 /* wave current address */
69#define AD_DMA_WAVBC 0x78 /* wave base count */
70#define AD_DMA_WAVCC 0x7c /* wave current count */
71
72#define AD_DMA_RESIC 0x80 /* RES dma interrupt current byte count */
73#define AD_DMA_RESIB 0x84 /* RES dma interrupt base byte count */
74
75#define AD_DMA_ADCIC 0x88 /* ADC dma interrupt current byte count */
76#define AD_DMA_ADCIB 0x8c /* ADC dma interrupt base byte count */
77
78#define AD_DMA_SYNIC 0x90 /* synth dma interrupt current byte count */
79#define AD_DMA_SYNIB 0x94 /* synth dma interrupt base byte count */
80
81#define AD_DMA_WAVIC 0x98 /* wave dma interrupt current byte count */
82#define AD_DMA_WAVIB 0x9c /* wave dma interrupt base byte count */
83
84#define AD_DMA_ICC 0xffffff /* current byte count mask */
85#define AD_DMA_IBC 0xffffff /* base byte count mask */
86/* bits 24 -> 31 reserved */
87
88/* 4 bytes pad */
89#define AD_DMA_ADC 0xa8 /* ADC dma control and status */
90#define AD_DMA_SYNTH 0xb0 /* Synth dma control and status */
91#define AD_DMA_WAV 0xb8 /* wave dma control and status */
92#define AD_DMA_RES 0xa0 /* Resample dma control and status */
93
94#define AD_DMA_SGDE 0x0001 /* SGD mode enable */
95#define AD_DMA_LOOP 0x0002 /* loop enable */
96#define AD_DMA_IM 0x000c /* interrupt mode mask */
97#define AD_DMA_IM_DIS (~AD_DMA_IM) /* disable */
98#define AD_DMA_IM_CNT 0x0004 /* interrupt on count */
99#define AD_DMA_IM_SGD 0x0008 /* interrupt on SGD flag */
100#define AD_DMA_IM_EOL 0x000c /* interrupt on End of Linked List */
101#define AD_DMA_SGDS 0x0030 /* SGD status */
102#define AD_DMA_SFLG 0x0040 /* SGD flag */
103#define AD_DMA_EOL 0x0080 /* SGD end of list */
104/* bits 8 -> 15 reserved */
105
106#define AD_DMA_DISR 0xc0 /* dma interrupt status */
107#define AD_DMA_DISR_RESI 0x000001 /* resampler channel interrupt */
108#define AD_DMA_DISR_ADCI 0x000002 /* ADC channel interrupt */
109#define AD_DMA_DISR_SYNI 0x000004 /* synthesis channel interrupt */
110#define AD_DMA_DISR_WAVI 0x000008 /* wave channel interrupt */
111/* bits 4, 5 reserved */
112#define AD_DMA_DISR_SEPS 0x000040 /* serial eeprom status */
113/* bits 7 -> 13 reserved */
114#define AD_DMA_DISR_PMAI 0x004000 /* pci master abort interrupt */
115#define AD_DMA_DISR_PTAI 0x008000 /* pci target abort interrupt */
116#define AD_DMA_DISR_PTAE 0x010000 /* pci target abort interrupt enable */
117#define AD_DMA_DISR_PMAE 0x020000 /* pci master abort interrupt enable */
118/* bits 19 -> 31 reserved */
119
120/* interrupt mask */
121#define AD_INTR_MASK (AD_DMA_DISR_RESI|AD_DMA_DISR_ADCI| \
122 AD_DMA_DISR_WAVI|AD_DMA_DISR_SYNI| \
123 AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI)
124
125#define AD_DMA_CHSS 0xc4 /* dma channel stop status */
126#define AD_DMA_CHSS_RESS 0x000001 /* resampler channel stopped */
127#define AD_DMA_CHSS_ADCS 0x000002 /* ADC channel stopped */
128#define AD_DMA_CHSS_SYNS 0x000004 /* synthesis channel stopped */
129#define AD_DMA_CHSS_WAVS 0x000008 /* wave channel stopped */
130
131#define AD_GPIO_IPC 0xc8 /* gpio port control */
132#define AD_GPIO_OP 0xca /* gpio output port status */
133#define AD_GPIO_IP 0xcc /* gpio input port status */
134
135#define AD_AC97_BASE 0x100 /* ac97 base register */
136
137#define AD_AC97_RESET 0x100 /* reset */
138
139#define AD_AC97_PWR_CTL 0x126 /* == AC97_POWERDOWN */
140#define AD_AC97_PWR_ADC 0x0001 /* ADC ready status */
141#define AD_AC97_PWR_DAC 0x0002 /* DAC ready status */
142#define AD_AC97_PWR_PR0 0x0100 /* PR0 (ADC) powerdown */
143#define AD_AC97_PWR_PR1 0x0200 /* PR1 (DAC) powerdown */
144
145#define AD_MISC_CTL 0x176 /* misc control */
146#define AD_MISC_CTL_DACZ 0x8000 /* set for zero fill, unset for repeat */
147#define AD_MISC_CTL_ARSR 0x0001 /* set for SR1, unset for SR0 */
148#define AD_MISC_CTL_ALSR 0x0100
149#define AD_MISC_CTL_DLSR 0x0400
150#define AD_MISC_CTL_DRSR 0x0004
151
152#define AD_AC97_SR0 0x178 /* sample rate 0, 0xbb80 == 48K */
153#define AD_AC97_SR0_48K 0xbb80 /* 48KHz */
154#define AD_AC97_SR1 0x17a /* sample rate 1 */
155
156#define AD_AC97_ACIC 0x180 /* ac97 codec interface control */
157#define AD_AC97_ACIC_ACIE 0x0001 /* analog codec interface enable */
158#define AD_AC97_ACIC_ACRD 0x0002 /* analog codec reset disable */
159#define AD_AC97_ACIC_ASOE 0x0004 /* audio stream output enable */
160#define AD_AC97_ACIC_VSRM 0x0008 /* variable sample rate mode */
161#define AD_AC97_ACIC_FSDH 0x0100 /* force SDATA_OUT high */
162#define AD_AC97_ACIC_FSYH 0x0200 /* force sync high */
163#define AD_AC97_ACIC_ACRDY 0x8000 /* analog codec ready status */
164/* bits 10 -> 14 reserved */
165
166
167#define AD_DS_MEMSIZE 512
168#define AD_OPL_MEMSIZE 16
169#define AD_MIDI_MEMSIZE 16
170
171#define AD_WAV_STATE 0
172#define AD_ADC_STATE 1
173#define AD_MAX_STATES 2
174
175#define AD_CHAN_WAV 0x0001
176#define AD_CHAN_ADC 0x0002
177#define AD_CHAN_RES 0x0004
178#define AD_CHAN_SYN 0x0008
179
180
181/* The chip would support 4 GB buffers and 16 MB periods,
182 * but let's not overdo it ... */
183#define BUFFER_BYTES_MAX (256 * 1024)
184#define PERIOD_BYTES_MIN 32
185#define PERIOD_BYTES_MAX (BUFFER_BYTES_MAX / 2)
186#define PERIODS_MIN 2
187#define PERIODS_MAX (BUFFER_BYTES_MAX / PERIOD_BYTES_MIN)
188
189#endif /* __AD1889_H__ */
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