diff options
author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-04-27 15:01:56 -0400 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-04-28 06:33:04 -0400 |
commit | dde3a7e9cb187e25deeac0269733116d4840f91e (patch) | |
tree | c6abd95cc73f76c842489eb655e854f8c428be7c /sound | |
parent | cb7b76961f73e4ae934d44f7b2e7ba974442f2fe (diff) |
ASoC: Remove redundant WM8960 SYSCLKSEL clkdiv option
The SYSCLK source is automatically managed when configuring the PLL.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound')
-rw-r--r-- | sound/soc/codecs/wm8960.c | 4 | ||||
-rw-r--r-- | sound/soc/codecs/wm8960.h | 1 |
2 files changed, 0 insertions, 5 deletions
diff --git a/sound/soc/codecs/wm8960.c b/sound/soc/codecs/wm8960.c index eba3ac013119..50b2376680c1 100644 --- a/sound/soc/codecs/wm8960.c +++ b/sound/soc/codecs/wm8960.c | |||
@@ -738,10 +738,6 @@ static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai, | |||
738 | u16 reg; | 738 | u16 reg; |
739 | 739 | ||
740 | switch (div_id) { | 740 | switch (div_id) { |
741 | case WM8960_SYSCLKSEL: | ||
742 | reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1fe; | ||
743 | snd_soc_write(codec, WM8960_CLOCK1, reg | div); | ||
744 | break; | ||
745 | case WM8960_SYSCLKDIV: | 741 | case WM8960_SYSCLKDIV: |
746 | reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9; | 742 | reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9; |
747 | snd_soc_write(codec, WM8960_CLOCK1, reg | div); | 743 | snd_soc_write(codec, WM8960_CLOCK1, reg | div); |
diff --git a/sound/soc/codecs/wm8960.h b/sound/soc/codecs/wm8960.h index d67bfe1300da..a5ef65481b86 100644 --- a/sound/soc/codecs/wm8960.h +++ b/sound/soc/codecs/wm8960.h | |||
@@ -76,7 +76,6 @@ | |||
76 | #define WM8960_OPCLKDIV 2 | 76 | #define WM8960_OPCLKDIV 2 |
77 | #define WM8960_DCLKDIV 3 | 77 | #define WM8960_DCLKDIV 3 |
78 | #define WM8960_TOCLKSEL 4 | 78 | #define WM8960_TOCLKSEL 4 |
79 | #define WM8960_SYSCLKSEL 5 | ||
80 | 79 | ||
81 | #define WM8960_SYSCLK_DIV_1 (0 << 1) | 80 | #define WM8960_SYSCLK_DIV_1 (0 << 1) |
82 | #define WM8960_SYSCLK_DIV_2 (2 << 1) | 81 | #define WM8960_SYSCLK_DIV_2 (2 << 1) |