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authorTakashi Iwai <tiwai@suse.de>2009-07-26 05:07:03 -0400
committerTakashi Iwai <tiwai@suse.de>2009-07-26 05:07:03 -0400
commit7679d5c65ba8e4d27daa9181c2f4c7e618058f29 (patch)
tree2740ba29fd47b6a0f5cf70b5103a9db6fe622dfb /sound
parent4be3bd7849165e7efa6b0b35a23d6a3598d97465 (diff)
parent06c71282a90470184a78f7f0ab0f7ce0fc1f69c8 (diff)
Merge branch 'fix/asoc' into for-linus
* fix/asoc: ASoC: tlv320aic3x: Enable PLL when not bypassed
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/codecs/tlv320aic3x.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index ab099f482487..cb0d1bf34b57 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -767,6 +767,7 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
767 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; 767 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
768 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; 768 u8 data, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
769 u16 pll_d = 1; 769 u16 pll_d = 1;
770 u8 reg;
770 771
771 /* select data word length */ 772 /* select data word length */
772 data = 773 data =
@@ -801,8 +802,16 @@ static int aic3x_hw_params(struct snd_pcm_substream *substream,
801 pll_q &= 0xf; 802 pll_q &= 0xf;
802 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT); 803 aic3x_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
803 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV); 804 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
804 } else 805 /* disable PLL if it is bypassed */
806 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
807 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE);
808
809 } else {
805 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV); 810 aic3x_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
811 /* enable PLL when it is used */
812 reg = aic3x_read_reg_cache(codec, AIC3X_PLL_PROGA_REG);
813 aic3x_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE);
814 }
806 815
807 /* Route Left DAC to left channel input and 816 /* Route Left DAC to left channel input and
808 * right DAC to right channel input */ 817 * right DAC to right channel input */